diff --git a/Exercises/Code/CH2/br_pred.py b/Exercises/Code/CH2/br_pred.py
index 8b13789..14e0a47 100644
--- a/Exercises/Code/CH2/br_pred.py
+++ b/Exercises/Code/CH2/br_pred.py
@@ -1 +1,175 @@
+# -*- coding: utf-8 -*-
+# Copyright (c) 2015 Jason Power
+# All rights reserved.
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions are
+# met: redistributions of source code must retain the above copyright
+# notice, this list of conditions and the following disclaimer;
+# redistributions in binary form must reproduce the above copyright
+# notice, this list of conditions and the following disclaimer in the
+# documentation and/or other materials provided with the distribution;
+# neither the name of the copyright holders nor the names of its
+# contributors may be used to endorse or promote products derived from
+# this software without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
+# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
+# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
+# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
+# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
+# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
+# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 
+
+
+# import the m5 (gem5) library created when gem5 is built
+import m5
+
+# import all of the SimObjects
+from m5.objects import *
+# Add the common scripts to our path
+m5.util.addToPath('../../')
+
+# import the caches which we made
+from caches import *
+import argparse
+# import the SimpleOpts module
+from common import SimpleOpts
+# create the system we are going to simulate
+from common import Options
+from common import ObjectList
+system = System()
+
+# Set the clock fequency of the system (and all of its children)
+system.clk_domain = SrcClockDomain()
+system.clk_domain.clock = '1GHz'
+system.clk_domain.voltage_domain = VoltageDomain()
+
+# Set up the system
+system.mem_mode = 'timing'               # Use timing accesses
+#system.mem_mode = 'atomic'               # Use timing accesses
+
+system.mem_ranges = [AddrRange('8192MB')] # Create an address range
+
+# Create a simple CPU
+system.cpu = TimingSimpleCPU()
+# system.cpu = DerivO3CPU()
+#system.cpu = MinorCPU()
+#system.cpu = AtomicSimpleCPU()
+#system.cpu = O3CPU()
+parser = argparse.ArgumentParser(description='CPU with 2-Level cache and branch predictor')
+
+parser.add_argument("--bp-type", default=None,
+                        choices=ObjectList.bp_list.get_names(),
+                        help="""
+                        type of branch predictor to run with
+                        (if not set, use the default branch predictor of
+                        the selected CPU)""")
+                        
+args = parser.parse_args()
+if args.bp_type:
+        bpClass = ObjectList.bp_list.get(args.bp_type)
+        system.cpu.branchPred = bpClass()
+
+#parser.add_argument("binary", default="", nargs="?", type=str,
+#                    help="Path to the binary to execute.")
+#parser.add_argument("--l1i_size",
+#                    help=f"L1 instruction cache size. Default: 16kB.")
+#parser.add_argument("--l1d_size",
+#                    help="L1 data cache size. Default: Default: 64kB.")
+#parser.add_argument("--l2_size",
+#                    help="L2 cache size. Default: 256kB.")
+
+options = parser.parse_args()
+
+
+
+
+
+
+
+
+
+# Create an L1 instruction and data cache
+system.cpu.icache = L1ICache()
+system.cpu.dcache = L1DCache()
+
+
+# Connect the instruction and data caches to the CPU
+system.cpu.icache.connectCPU(system.cpu)
+system.cpu.dcache.connectCPU(system.cpu)
+
+# Create a memory bus, a coherent crossbar, in this case
+system.l2bus = L2XBar()
+
+# Hook the CPU ports up to the l2bus
+system.cpu.icache.connectBus(system.l2bus)
+system.cpu.dcache.connectBus(system.l2bus)
+
+# Create an L2 cache and connect it to the l2bus
+system.l2cache = L2Cache()
+system.l2cache.connectCPUSideBus(system.l2bus)
+
+# Create a memory bus
+system.membus = SystemXBar()
+
+# Connect the L2 cache to the membus
+system.l2cache.connectMemSideBus(system.membus)
+
+# create the interrupt controller for the CPU
+system.cpu.createInterruptController()
+
+# For x86 only, make sure the interrupts are connected to the memory
+# Note: these are directly connected to the memory bus and are not cached
+if m5.defines.buildEnv['TARGET_ISA'] == "x86":
+    system.cpu.interrupts[0].pio = system.membus.mem_side_ports
+    system.cpu.interrupts[0].int_requestor = system.membus.cpu_side_ports
+    system.cpu.interrupts[0].int_responder = system.membus.mem_side_ports
+
+# Connect the system up to the membus
+system.system_port = system.membus.cpu_side_ports
+
+# Create a DDR3 memory controller
+system.mem_ctrl = MemCtrl()
+system.mem_ctrl.dram = DDR3_1600_8x8()
+system.mem_ctrl.dram.range = system.mem_ranges[0]
+system.mem_ctrl.port = system.membus.mem_side_ports
+
+
+
+# get ISA for the binary to run.
+isa = str(m5.defines.buildEnv['TARGET_ISA']).lower()
+
+# Default to running 'hello', use the compiled ISA to find the binary
+# grab the specific path to the binary
+thispath = os.path.dirname(os.path.realpath(__file__))
+print (thispath)
+
+binary = os.path.join(thispath, '../../tests/test-progs/matmul_ijk_128.out')
+print (binary)
+
+system.workload = SEWorkload.init_compatible(binary)
+
+
+# Create a process for a simple "Hello World" application
+process = Process()
+# Set the command
+# cmd is a list which begins with the executable (like argv)
+process.cmd = [binary]
+# Set the cpu to use the process as its workload and create thread contexts
+system.cpu.workload = process
+system.cpu.createThreads()
+
+# set up the root SimObject and start the simulation
+root = Root(full_system = False, system = system)
+# instantiate all of the objects we've created above
+m5.instantiate()
+
+print("Beginning simulation!")
+exit_event = m5.simulate()
+print('Exiting @ tick %i because %s' % (m5.curTick(), exit_event.getCause()))
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