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25 lines
867 B
Verilog
25 lines
867 B
Verilog
//Copyright 1986-2019 Xilinx, Inc. All Rights Reserved.
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//--------------------------------------------------------------------------------
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//Tool Version: Vivado v.2019.1.3_CR1055600 (lin64) Build 2644227 Wed Sep 4 09:44:18 MDT 2019
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//Date : Wed Apr 8 10:49:50 2020
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//Host : apdegl15aa.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.5 (Maipo)
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//Command : generate_target a2x_axi_bd_wrapper.bd
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//Design : a2x_axi_bd_wrapper
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//Purpose : IP block netlist
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//--------------------------------------------------------------------------------
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`timescale 1 ps / 1 ps
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module a2x_axi_bd_wrapper
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(clk_in1_n_0,
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clk_in1_p_0);
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input clk_in1_n_0;
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input clk_in1_p_0;
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wire clk_in1_n_0;
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wire clk_in1_p_0;
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a2x_axi_bd a2x_axi_bd_i
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(.clk_in1_n_0(clk_in1_n_0),
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.clk_in1_p_0(clk_in1_p_0));
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endmodule
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