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132 lines
5.5 KiB
VHDL
132 lines
5.5 KiB
VHDL
-- © IBM Corp. 2020
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-- Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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-- the terms below; you may not use the files in this repository except in
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-- compliance with the License as modified.
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-- You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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--
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-- Modified Terms:
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--
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-- 1) For the purpose of the patent license granted to you in Section 3 of the
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-- License, the "Work" hereby includes implementations of the work of authorship
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-- in physical form.
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--
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-- 2) Notwithstanding any terms to the contrary in the License, any licenses
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-- necessary for implementation of the Work that are available from OpenPOWER
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-- via the Power ISA End User License Agreement (EULA) are explicitly excluded
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-- hereunder, and may be obtained from OpenPOWER under the terms and conditions
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-- of the EULA.
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--
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-- Unless required by applicable law or agreed to in writing, the reference design
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-- distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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-- WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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-- for the specific language governing permissions and limitations under the License.
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--
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-- Additional rights, including the ability to physically implement a softcore that
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-- is compliant with the required sections of the Power ISA Specification, are
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-- available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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-- obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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library ieee; use ieee.std_logic_1164.all;
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library support;
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use support.power_logic_pkg.all;
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entity c_debug_mux4 is
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generic( DBG_WIDTH : integer := 88
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);
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port(
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vd : inout power_logic;
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gd : inout power_logic;
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select_bits : in std_ulogic_vector(0 to 15);
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trace_data_in : in std_ulogic_vector(0 to DBG_WIDTH-1);
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trigger_data_in : in std_ulogic_vector(0 to 11);
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dbg_group0 : in std_ulogic_vector(0 to DBG_WIDTH-1);
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dbg_group1 : in std_ulogic_vector(0 to DBG_WIDTH-1);
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dbg_group2 : in std_ulogic_vector(0 to DBG_WIDTH-1);
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dbg_group3 : in std_ulogic_vector(0 to DBG_WIDTH-1);
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trg_group0 : in std_ulogic_vector(0 to 11);
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trg_group1 : in std_ulogic_vector(0 to 11);
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trg_group2 : in std_ulogic_vector(0 to 11);
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trg_group3 : in std_ulogic_vector(0 to 11);
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trace_data_out : out std_ulogic_vector(0 to DBG_WIDTH-1);
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trigger_data_out : out std_ulogic_vector(0 to 11)
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);
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-- synopsys translate_off
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-- synopsys translate_on
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end c_debug_mux4;
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architecture c_debug_mux4 of c_debug_mux4 is
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constant DBG_1FOURTH : positive := DBG_WIDTH/4;
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constant DBG_2FOURTH : positive := DBG_WIDTH/2;
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constant DBG_3FOURTH : positive := 3*DBG_WIDTH/4;
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signal debug_grp_selected : std_ulogic_vector(0 to DBG_WIDTH-1);
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signal debug_grp_rotated : std_ulogic_vector(0 to DBG_WIDTH-1);
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signal trigg_grp_selected : std_ulogic_vector(0 to 11);
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signal trigg_grp_rotated : std_ulogic_vector(0 to 11);
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signal unused : std_ulogic;
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begin
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unused <= select_bits(2) or select_bits(3) or select_bits(4);
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with select_bits(0 to 1) select debug_grp_selected <=
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dbg_group0 when "00",
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dbg_group1 when "01",
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dbg_group2 when "10",
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dbg_group3 when others;
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with select_bits(5 to 6) select
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debug_grp_rotated <= debug_grp_selected(DBG_1FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_1FOURTH-1) when "11",
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debug_grp_selected(DBG_2FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_2FOURTH-1) when "10",
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debug_grp_selected(DBG_3FOURTH to DBG_WIDTH-1) & debug_grp_selected(0 to DBG_3FOURTH-1) when "01",
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debug_grp_selected(0 to DBG_WIDTH-1) when others;
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with select_bits(7) select trace_data_out(0 to DBG_1FOURTH-1) <=
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trace_data_in(0 to DBG_1FOURTH-1) when '0',
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debug_grp_rotated(0 to DBG_1FOURTH-1) when others;
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with select_bits(8) select trace_data_out(DBG_1FOURTH to DBG_2FOURTH-1) <=
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trace_data_in(DBG_1FOURTH to DBG_2FOURTH-1) when '0',
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debug_grp_rotated(DBG_1FOURTH to DBG_2FOURTH-1) when others;
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with select_bits(9) select trace_data_out(DBG_2FOURTH to DBG_3FOURTH-1) <=
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trace_data_in(DBG_2FOURTH to DBG_3FOURTH-1) when '0',
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debug_grp_rotated(DBG_2FOURTH to DBG_3FOURTH-1) when others;
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with select_bits(10) select trace_data_out(DBG_3FOURTH to DBG_WIDTH-1) <=
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trace_data_in(DBG_3FOURTH to DBG_WIDTH-1) when '0',
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debug_grp_rotated(DBG_3FOURTH to DBG_WIDTH-1) when others;
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with select_bits(11 to 12) select trigg_grp_selected <=
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trg_group0 when "00",
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trg_group1 when "01",
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trg_group2 when "10",
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trg_group3 when others;
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with select_bits(13) select
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trigg_grp_rotated <= trigg_grp_selected(6 to 11) & trigg_grp_selected(0 to 5) when '1',
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trigg_grp_selected(0 to 11) when others;
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with select_bits(14) select trigger_data_out(0 to 5) <=
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trigger_data_in(0 to 5) when '0',
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trigg_grp_rotated(0 to 5) when others;
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with select_bits(15) select trigger_data_out(6 to 11) <=
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trigger_data_in(6 to 11) when '0',
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trigg_grp_rotated(6 to 11) when others;
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end c_debug_mux4;
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