// -----------------------------------------------------------------------------
// Auto-Generated by:        __   _ __      _  __
//                          / /  (_) /____ | |/_/
//                         / /__/ / __/ -_)>  <
//                        /____/_/\__/\__/_/|_|
//                     Build your hardware, easily!
//                   https://github.com/enjoy-digital/litex
//
// Filename   : cmod7.v
// Device     : xc7k410t-ffv676-1
// LiteX sha1 : 6932fc51
// Date       : 2022-08-04 07:49:47
//------------------------------------------------------------------------------


//------------------------------------------------------------------------------
// Module
//------------------------------------------------------------------------------

module cmod7 (
	output reg  serial_tx,
	input  wire serial_rx,
	(* dont_touch = "true" *)	input  wire clk12,
	output wire user_led0,
	output wire user_led1,
	input  wire user_btn0,
	input  wire user_btn1
);


//------------------------------------------------------------------------------
// Signals
//------------------------------------------------------------------------------

reg  soc_rst = 1'd0;
wire cpu_rst;
reg  [1:0] reset_storage = 2'd0;
reg  reset_re = 1'd0;
reg  [31:0] scratch_storage = 32'd305419896;
reg  scratch_re = 1'd0;
wire [31:0] bus_errors_status;
wire bus_errors_we;
reg  bus_errors_re = 1'd0;
wire bus_error;
reg  [31:0] bus_errors = 32'd0;
wire a2o_reset;
reg  [2:0] a2o_interrupt = 3'd0;
reg  a2o_interruptS = 1'd0;
wire [29:0] a2o_dbus_adr;
wire [31:0] a2o_dbus_dat_w;
wire [31:0] a2o_dbus_dat_r;
wire [3:0] a2o_dbus_sel;
wire a2o_dbus_cyc;
wire a2o_dbus_stb;
wire a2o_dbus_ack;
wire a2o_dbus_we;
reg  [2:0] a2o_dbus_cti = 3'd0;
reg  [1:0] a2o_dbus_bte = 2'd0;
wire a2o_dbus_err;
wire [1:0] a2o;
wire tx_sink_valid;
reg  tx_sink_ready = 1'd0;
wire tx_sink_first;
wire tx_sink_last;
wire [7:0] tx_sink_payload_data;
reg  [7:0] tx_data = 8'd0;
reg  [3:0] tx_count = 4'd0;
reg  tx_enable = 1'd0;
reg  tx_tick = 1'd0;
reg  [31:0] tx_phase = 32'd0;
reg  rx_source_valid = 1'd0;
wire rx_source_ready;
reg  rx_source_first = 1'd0;
reg  rx_source_last = 1'd0;
reg  [7:0] rx_source_payload_data = 8'd0;
reg  [7:0] rx_data = 8'd0;
reg  [3:0] rx_count = 4'd0;
reg  rx_enable = 1'd0;
reg  rx_tick = 1'd0;
reg  [31:0] rx_phase = 32'd0;
wire rx_rx;
reg  rx_rx_d = 1'd0;
reg  uart_rxtx_re = 1'd0;
wire [7:0] uart_rxtx_r;
reg  uart_rxtx_we = 1'd0;
wire [7:0] uart_rxtx_w;
wire uart_txfull_status;
wire uart_txfull_we;
reg  uart_txfull_re = 1'd0;
wire uart_rxempty_status;
wire uart_rxempty_we;
reg  uart_rxempty_re = 1'd0;
wire uart_irq;
wire uart_tx_status;
reg  uart_tx_pending = 1'd0;
wire uart_tx_trigger;
reg  uart_tx_clear = 1'd0;
reg  uart_tx_trigger_d = 1'd0;
wire uart_rx_status;
reg  uart_rx_pending = 1'd0;
wire uart_rx_trigger;
reg  uart_rx_clear = 1'd0;
reg  uart_rx_trigger_d = 1'd0;
wire uart_tx0;
wire uart_rx0;
reg  [1:0] uart_status_status = 2'd0;
wire uart_status_we;
reg  uart_status_re = 1'd0;
wire uart_tx1;
wire uart_rx1;
reg  [1:0] uart_pending_status = 2'd0;
wire uart_pending_we;
reg  uart_pending_re = 1'd0;
reg  [1:0] uart_pending_r = 2'd0;
wire uart_tx2;
wire uart_rx2;
reg  [1:0] uart_enable_storage = 2'd0;
reg  uart_enable_re = 1'd0;
wire uart_txempty_status;
wire uart_txempty_we;
reg  uart_txempty_re = 1'd0;
wire uart_rxfull_status;
wire uart_rxfull_we;
reg  uart_rxfull_re = 1'd0;
wire uart_uart_sink_valid;
wire uart_uart_sink_ready;
wire uart_uart_sink_first;
wire uart_uart_sink_last;
wire [7:0] uart_uart_sink_payload_data;
wire uart_uart_source_valid;
wire uart_uart_source_ready;
wire uart_uart_source_first;
wire uart_uart_source_last;
wire [7:0] uart_uart_source_payload_data;
wire uart_tx_fifo_sink_valid;
wire uart_tx_fifo_sink_ready;
reg  uart_tx_fifo_sink_first = 1'd0;
reg  uart_tx_fifo_sink_last = 1'd0;
wire [7:0] uart_tx_fifo_sink_payload_data;
wire uart_tx_fifo_source_valid;
wire uart_tx_fifo_source_ready;
wire uart_tx_fifo_source_first;
wire uart_tx_fifo_source_last;
wire [7:0] uart_tx_fifo_source_payload_data;
wire uart_tx_fifo_re;
reg  uart_tx_fifo_readable = 1'd0;
wire uart_tx_fifo_syncfifo_we;
wire uart_tx_fifo_syncfifo_writable;
wire uart_tx_fifo_syncfifo_re;
wire uart_tx_fifo_syncfifo_readable;
wire [9:0] uart_tx_fifo_syncfifo_din;
wire [9:0] uart_tx_fifo_syncfifo_dout;
reg  [4:0] uart_tx_fifo_level0 = 5'd0;
reg  uart_tx_fifo_replace = 1'd0;
reg  [3:0] uart_tx_fifo_produce = 4'd0;
reg  [3:0] uart_tx_fifo_consume = 4'd0;
reg  [3:0] uart_tx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_tx_fifo_wrport_dat_r;
wire uart_tx_fifo_wrport_we;
wire [9:0] uart_tx_fifo_wrport_dat_w;
wire uart_tx_fifo_do_read;
wire [3:0] uart_tx_fifo_rdport_adr;
wire [9:0] uart_tx_fifo_rdport_dat_r;
wire uart_tx_fifo_rdport_re;
wire [4:0] uart_tx_fifo_level1;
wire [7:0] uart_tx_fifo_fifo_in_payload_data;
wire uart_tx_fifo_fifo_in_first;
wire uart_tx_fifo_fifo_in_last;
wire [7:0] uart_tx_fifo_fifo_out_payload_data;
wire uart_tx_fifo_fifo_out_first;
wire uart_tx_fifo_fifo_out_last;
wire uart_rx_fifo_sink_valid;
wire uart_rx_fifo_sink_ready;
wire uart_rx_fifo_sink_first;
wire uart_rx_fifo_sink_last;
wire [7:0] uart_rx_fifo_sink_payload_data;
wire uart_rx_fifo_source_valid;
wire uart_rx_fifo_source_ready;
wire uart_rx_fifo_source_first;
wire uart_rx_fifo_source_last;
wire [7:0] uart_rx_fifo_source_payload_data;
wire uart_rx_fifo_re;
reg  uart_rx_fifo_readable = 1'd0;
wire uart_rx_fifo_syncfifo_we;
wire uart_rx_fifo_syncfifo_writable;
wire uart_rx_fifo_syncfifo_re;
wire uart_rx_fifo_syncfifo_readable;
wire [9:0] uart_rx_fifo_syncfifo_din;
wire [9:0] uart_rx_fifo_syncfifo_dout;
reg  [4:0] uart_rx_fifo_level0 = 5'd0;
reg  uart_rx_fifo_replace = 1'd0;
reg  [3:0] uart_rx_fifo_produce = 4'd0;
reg  [3:0] uart_rx_fifo_consume = 4'd0;
reg  [3:0] uart_rx_fifo_wrport_adr = 4'd0;
wire [9:0] uart_rx_fifo_wrport_dat_r;
wire uart_rx_fifo_wrport_we;
wire [9:0] uart_rx_fifo_wrport_dat_w;
wire uart_rx_fifo_do_read;
wire [3:0] uart_rx_fifo_rdport_adr;
wire [9:0] uart_rx_fifo_rdport_dat_r;
wire uart_rx_fifo_rdport_re;
wire [4:0] uart_rx_fifo_level1;
wire [7:0] uart_rx_fifo_fifo_in_payload_data;
wire uart_rx_fifo_fifo_in_first;
wire uart_rx_fifo_fifo_in_last;
wire [7:0] uart_rx_fifo_fifo_out_payload_data;
wire uart_rx_fifo_fifo_out_first;
wire uart_rx_fifo_fifo_out_last;
reg  [31:0] timer_load_storage = 32'd0;
reg  timer_load_re = 1'd0;
reg  [31:0] timer_reload_storage = 32'd0;
reg  timer_reload_re = 1'd0;
reg  timer_en_storage = 1'd0;
reg  timer_en_re = 1'd0;
reg  timer_update_value_storage = 1'd0;
reg  timer_update_value_re = 1'd0;
reg  [31:0] timer_value_status = 32'd0;
wire timer_value_we;
reg  timer_value_re = 1'd0;
wire timer_irq;
wire timer_zero_status;
reg  timer_zero_pending = 1'd0;
wire timer_zero_trigger;
reg  timer_zero_clear = 1'd0;
reg  timer_zero_trigger_d = 1'd0;
wire timer_zero0;
wire timer_status_status;
wire timer_status_we;
reg  timer_status_re = 1'd0;
wire timer_zero1;
wire timer_pending_status;
wire timer_pending_we;
reg  timer_pending_re = 1'd0;
reg  timer_pending_r = 1'd0;
wire timer_zero2;
reg  timer_enable_storage = 1'd0;
reg  timer_enable_re = 1'd0;
reg  [31:0] timer_value = 32'd0;
reg  crg_rst = 1'd0;
(* dont_touch = "true" *) wire sys_clk;
wire sys_rst;
wire sys2x_clk;
wire idelay_clk;
wire idelay_rst;
wire crg_reset;
reg  crg_power_down = 1'd0;
wire crg_locked;
(* dont_touch = "true" *) wire crg_clkin;
wire crg_clkout0;
wire crg_clkout_buf0;
wire crg_clkout1;
wire crg_clkout_buf1;
wire crg_clkout2;
wire crg_clkout_buf2;
reg  [3:0] crg_reset_counter = 4'd15;
reg  crg_ic_reset = 1'd1;
wire [29:0] ram_bus_adr;
wire [31:0] ram_bus_dat_w;
wire [31:0] ram_bus_dat_r;
wire [3:0] ram_bus_sel;
wire ram_bus_cyc;
wire ram_bus_stb;
reg  ram_bus_ack = 1'd0;
wire ram_bus_we;
wire [2:0] ram_bus_cti;
wire [1:0] ram_bus_bte;
reg  ram_bus_err = 1'd0;
reg  adr_burst = 1'd0;
wire [13:0] adr;
wire [31:0] dat_r;
wire [29:0] interface0_ram_bus_adr;
wire [31:0] interface0_ram_bus_dat_w;
wire [31:0] interface0_ram_bus_dat_r;
wire [3:0] interface0_ram_bus_sel;
wire interface0_ram_bus_cyc;
wire interface0_ram_bus_stb;
reg  interface0_ram_bus_ack = 1'd0;
wire interface0_ram_bus_we;
wire [2:0] interface0_ram_bus_cti;
wire [1:0] interface0_ram_bus_bte;
reg  interface0_ram_bus_err = 1'd0;
reg  sram0_adr_burst = 1'd0;
wire [13:0] sram0_adr;
wire [31:0] sram0_dat_r;
reg  [3:0] sram0_we = 4'd0;
wire [31:0] sram0_dat_w;
reg  [1:0] leds_storage = 2'd0;
reg  leds_re = 1'd0;
reg  [1:0] leds_chaser = 2'd0;
reg  leds_mode = 1'd0;
wire leds_wait;
wire leds_done;
reg  [24:0] leds_count = 25'd25000000;
reg  [1:0] leds_leds = 2'd0;
wire [1:0] buttons_status;
wire buttons_we;
reg  buttons_re = 1'd0;
wire [29:0] interface1_ram_bus_adr;
wire [31:0] interface1_ram_bus_dat_w;
wire [31:0] interface1_ram_bus_dat_r;
wire [3:0] interface1_ram_bus_sel;
wire interface1_ram_bus_cyc;
wire interface1_ram_bus_stb;
reg  interface1_ram_bus_ack = 1'd0;
wire interface1_ram_bus_we;
wire [2:0] interface1_ram_bus_cti;
wire [1:0] interface1_ram_bus_bte;
reg  interface1_ram_bus_err = 1'd0;
reg  sram1_adr_burst = 1'd0;
wire [5:0] sram1_adr;
wire [31:0] sram1_dat_r;
reg  [3:0] sram1_we = 4'd0;
wire [31:0] sram1_dat_w;
reg  [13:0] basesoc_adr = 14'd0;
reg  basesoc_we = 1'd0;
reg  [31:0] basesoc_dat_w = 32'd0;
wire [31:0] basesoc_dat_r;
wire [29:0] basesoc_wishbone_adr;
wire [31:0] basesoc_wishbone_dat_w;
reg  [31:0] basesoc_wishbone_dat_r = 32'd0;
wire [3:0] basesoc_wishbone_sel;
wire basesoc_wishbone_cyc;
wire basesoc_wishbone_stb;
reg  basesoc_wishbone_ack = 1'd0;
wire basesoc_wishbone_we;
wire [2:0] basesoc_wishbone_cti;
wire [1:0] basesoc_wishbone_bte;
reg  basesoc_wishbone_err = 1'd0;
wire [29:0] shared_adr;
wire [31:0] shared_dat_w;
reg  [31:0] shared_dat_r = 32'd0;
wire [3:0] shared_sel;
wire shared_cyc;
wire shared_stb;
reg  shared_ack = 1'd0;
wire shared_we;
wire [2:0] shared_cti;
wire [1:0] shared_bte;
wire shared_err;
wire request;
wire grant;
reg  [3:0] slave_sel = 4'd0;
reg  [3:0] slave_sel_r = 4'd0;
reg  error = 1'd0;
wire wait_1;
wire done;
reg  [19:0] count = 20'd1000000;
wire [13:0] csr_bankarray_interface0_bank_bus_adr;
wire csr_bankarray_interface0_bank_bus_we;
wire [31:0] csr_bankarray_interface0_bank_bus_dat_w;
reg  [31:0] csr_bankarray_interface0_bank_bus_dat_r = 32'd0;
reg  csr_bankarray_csrbank0_in_re = 1'd0;
wire [1:0] csr_bankarray_csrbank0_in_r;
reg  csr_bankarray_csrbank0_in_we = 1'd0;
wire [1:0] csr_bankarray_csrbank0_in_w;
wire csr_bankarray_csrbank0_sel;
wire [13:0] csr_bankarray_interface1_bank_bus_adr;
wire csr_bankarray_interface1_bank_bus_we;
wire [31:0] csr_bankarray_interface1_bank_bus_dat_w;
reg  [31:0] csr_bankarray_interface1_bank_bus_dat_r = 32'd0;
reg  csr_bankarray_csrbank1_reset0_re = 1'd0;
wire [1:0] csr_bankarray_csrbank1_reset0_r;
reg  csr_bankarray_csrbank1_reset0_we = 1'd0;
wire [1:0] csr_bankarray_csrbank1_reset0_w;
reg  csr_bankarray_csrbank1_scratch0_re = 1'd0;
wire [31:0] csr_bankarray_csrbank1_scratch0_r;
reg  csr_bankarray_csrbank1_scratch0_we = 1'd0;
wire [31:0] csr_bankarray_csrbank1_scratch0_w;
reg  csr_bankarray_csrbank1_bus_errors_re = 1'd0;
wire [31:0] csr_bankarray_csrbank1_bus_errors_r;
reg  csr_bankarray_csrbank1_bus_errors_we = 1'd0;
wire [31:0] csr_bankarray_csrbank1_bus_errors_w;
wire csr_bankarray_csrbank1_sel;
wire [13:0] csr_bankarray_sram_bus_adr;
wire csr_bankarray_sram_bus_we;
wire [31:0] csr_bankarray_sram_bus_dat_w;
reg  [31:0] csr_bankarray_sram_bus_dat_r = 32'd0;
wire [4:0] csr_bankarray_adr;
wire [7:0] csr_bankarray_dat_r;
wire csr_bankarray_sel;
reg  csr_bankarray_sel_r = 1'd0;
wire [13:0] csr_bankarray_interface2_bank_bus_adr;
wire csr_bankarray_interface2_bank_bus_we;
wire [31:0] csr_bankarray_interface2_bank_bus_dat_w;
reg  [31:0] csr_bankarray_interface2_bank_bus_dat_r = 32'd0;
reg  csr_bankarray_csrbank2_out0_re = 1'd0;
wire [1:0] csr_bankarray_csrbank2_out0_r;
reg  csr_bankarray_csrbank2_out0_we = 1'd0;
wire [1:0] csr_bankarray_csrbank2_out0_w;
wire csr_bankarray_csrbank2_sel;
wire [13:0] csr_bankarray_interface3_bank_bus_adr;
wire csr_bankarray_interface3_bank_bus_we;
wire [31:0] csr_bankarray_interface3_bank_bus_dat_w;
reg  [31:0] csr_bankarray_interface3_bank_bus_dat_r = 32'd0;
reg  csr_bankarray_csrbank3_load0_re = 1'd0;
wire [31:0] csr_bankarray_csrbank3_load0_r;
reg  csr_bankarray_csrbank3_load0_we = 1'd0;
wire [31:0] csr_bankarray_csrbank3_load0_w;
reg  csr_bankarray_csrbank3_reload0_re = 1'd0;
wire [31:0] csr_bankarray_csrbank3_reload0_r;
reg  csr_bankarray_csrbank3_reload0_we = 1'd0;
wire [31:0] csr_bankarray_csrbank3_reload0_w;
reg  csr_bankarray_csrbank3_en0_re = 1'd0;
wire csr_bankarray_csrbank3_en0_r;
reg  csr_bankarray_csrbank3_en0_we = 1'd0;
wire csr_bankarray_csrbank3_en0_w;
reg  csr_bankarray_csrbank3_update_value0_re = 1'd0;
wire csr_bankarray_csrbank3_update_value0_r;
reg  csr_bankarray_csrbank3_update_value0_we = 1'd0;
wire csr_bankarray_csrbank3_update_value0_w;
reg  csr_bankarray_csrbank3_value_re = 1'd0;
wire [31:0] csr_bankarray_csrbank3_value_r;
reg  csr_bankarray_csrbank3_value_we = 1'd0;
wire [31:0] csr_bankarray_csrbank3_value_w;
reg  csr_bankarray_csrbank3_ev_status_re = 1'd0;
wire csr_bankarray_csrbank3_ev_status_r;
reg  csr_bankarray_csrbank3_ev_status_we = 1'd0;
wire csr_bankarray_csrbank3_ev_status_w;
reg  csr_bankarray_csrbank3_ev_pending_re = 1'd0;
wire csr_bankarray_csrbank3_ev_pending_r;
reg  csr_bankarray_csrbank3_ev_pending_we = 1'd0;
wire csr_bankarray_csrbank3_ev_pending_w;
reg  csr_bankarray_csrbank3_ev_enable0_re = 1'd0;
wire csr_bankarray_csrbank3_ev_enable0_r;
reg  csr_bankarray_csrbank3_ev_enable0_we = 1'd0;
wire csr_bankarray_csrbank3_ev_enable0_w;
wire csr_bankarray_csrbank3_sel;
wire [13:0] csr_bankarray_interface4_bank_bus_adr;
wire csr_bankarray_interface4_bank_bus_we;
wire [31:0] csr_bankarray_interface4_bank_bus_dat_w;
reg  [31:0] csr_bankarray_interface4_bank_bus_dat_r = 32'd0;
reg  csr_bankarray_csrbank4_txfull_re = 1'd0;
wire csr_bankarray_csrbank4_txfull_r;
reg  csr_bankarray_csrbank4_txfull_we = 1'd0;
wire csr_bankarray_csrbank4_txfull_w;
reg  csr_bankarray_csrbank4_rxempty_re = 1'd0;
wire csr_bankarray_csrbank4_rxempty_r;
reg  csr_bankarray_csrbank4_rxempty_we = 1'd0;
wire csr_bankarray_csrbank4_rxempty_w;
reg  csr_bankarray_csrbank4_ev_status_re = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_status_r;
reg  csr_bankarray_csrbank4_ev_status_we = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_status_w;
reg  csr_bankarray_csrbank4_ev_pending_re = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_pending_r;
reg  csr_bankarray_csrbank4_ev_pending_we = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_pending_w;
reg  csr_bankarray_csrbank4_ev_enable0_re = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_enable0_r;
reg  csr_bankarray_csrbank4_ev_enable0_we = 1'd0;
wire [1:0] csr_bankarray_csrbank4_ev_enable0_w;
reg  csr_bankarray_csrbank4_txempty_re = 1'd0;
wire csr_bankarray_csrbank4_txempty_r;
reg  csr_bankarray_csrbank4_txempty_we = 1'd0;
wire csr_bankarray_csrbank4_txempty_w;
reg  csr_bankarray_csrbank4_rxfull_re = 1'd0;
wire csr_bankarray_csrbank4_rxfull_r;
reg  csr_bankarray_csrbank4_rxfull_we = 1'd0;
wire csr_bankarray_csrbank4_rxfull_w;
wire csr_bankarray_csrbank4_sel;
wire [13:0] csr_interconnect_adr;
wire csr_interconnect_we;
wire [31:0] csr_interconnect_dat_w;
wire [31:0] csr_interconnect_dat_r;
reg  basesoc_rs232phytx_state = 1'd0;
reg  basesoc_rs232phytx_next_state = 1'd0;
reg  [3:0] tx_count_rs232phytx_next_value0 = 4'd0;
reg  tx_count_rs232phytx_next_value_ce0 = 1'd0;
reg  serial_tx_rs232phytx_next_value1 = 1'd0;
reg  serial_tx_rs232phytx_next_value_ce1 = 1'd0;
reg  [7:0] tx_data_rs232phytx_next_value2 = 8'd0;
reg  tx_data_rs232phytx_next_value_ce2 = 1'd0;
reg  basesoc_rs232phyrx_state = 1'd0;
reg  basesoc_rs232phyrx_next_state = 1'd0;
reg  [3:0] rx_count_rs232phyrx_next_value0 = 4'd0;
reg  rx_count_rs232phyrx_next_value_ce0 = 1'd0;
reg  [7:0] rx_data_rs232phyrx_next_value1 = 8'd0;
reg  rx_data_rs232phyrx_next_value_ce1 = 1'd0;
wire basesoc_reset0;
wire basesoc_reset1;
wire basesoc_reset2;
wire basesoc_reset3;
wire basesoc_reset4;
wire basesoc_reset5;
wire basesoc_reset6;
wire basesoc_reset7;
wire basesoc_mmcm_fb;
reg  basesoc_state = 1'd0;
reg  basesoc_next_state = 1'd0;
reg  [29:0] array_muxed0 = 30'd0;
reg  [31:0] array_muxed1 = 32'd0;
reg  [3:0] array_muxed2 = 4'd0;
reg  array_muxed3 = 1'd0;
reg  array_muxed4 = 1'd0;
reg  array_muxed5 = 1'd0;
reg  [2:0] array_muxed6 = 3'd0;
reg  [1:0] array_muxed7 = 2'd0;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg  xilinxmultiregimpl0_regs0 = 1'd0;
(* async_reg = "true", dont_touch = "true" *) reg  xilinxmultiregimpl0_regs1 = 1'd0;
wire xilinxasyncresetsynchronizerimpl0;
wire xilinxasyncresetsynchronizerimpl0_rst_meta;
wire xilinxasyncresetsynchronizerimpl1;
wire xilinxasyncresetsynchronizerimpl1_rst_meta;
wire xilinxasyncresetsynchronizerimpl1_expr;
wire xilinxasyncresetsynchronizerimpl2;
wire xilinxasyncresetsynchronizerimpl2_rst_meta;
(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg  [1:0] xilinxmultiregimpl1_regs0 = 2'd0;
(* async_reg = "true", dont_touch = "true" *) reg  [1:0] xilinxmultiregimpl1_regs1 = 2'd0;
wire xilinxmultiregimpl1;

//------------------------------------------------------------------------------
// Combinatorial Logic
//------------------------------------------------------------------------------

assign a2o_reset = (soc_rst | cpu_rst);
always @(*) begin
	crg_rst <= 1'd0;
	if (soc_rst) begin
		crg_rst <= 1'd1;
	end
end
assign bus_error = error;
always @(*) begin
	a2o_interrupt <= 3'd0;
	a2o_interrupt[1] <= timer_irq;
	a2o_interrupt[0] <= uart_irq;
end
assign bus_errors_status = bus_errors;
always @(*) begin
	serial_tx_rs232phytx_next_value1 <= 1'd0;
	serial_tx_rs232phytx_next_value_ce1 <= 1'd0;
	tx_enable <= 1'd0;
	tx_data_rs232phytx_next_value2 <= 8'd0;
	tx_data_rs232phytx_next_value_ce2 <= 1'd0;
	tx_sink_ready <= 1'd0;
	basesoc_rs232phytx_next_state <= 1'd0;
	tx_count_rs232phytx_next_value0 <= 4'd0;
	tx_count_rs232phytx_next_value_ce0 <= 1'd0;
	basesoc_rs232phytx_next_state <= basesoc_rs232phytx_state;
	case (basesoc_rs232phytx_state)
		1'd1: begin
			tx_enable <= 1'd1;
			if (tx_tick) begin
				serial_tx_rs232phytx_next_value1 <= tx_data;
				serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
				tx_count_rs232phytx_next_value0 <= (tx_count + 1'd1);
				tx_count_rs232phytx_next_value_ce0 <= 1'd1;
				tx_data_rs232phytx_next_value2 <= {1'd1, tx_data[7:1]};
				tx_data_rs232phytx_next_value_ce2 <= 1'd1;
				if ((tx_count == 4'd9)) begin
					tx_sink_ready <= 1'd1;
					basesoc_rs232phytx_next_state <= 1'd0;
				end
			end
		end
		default: begin
			tx_count_rs232phytx_next_value0 <= 1'd0;
			tx_count_rs232phytx_next_value_ce0 <= 1'd1;
			serial_tx_rs232phytx_next_value1 <= 1'd1;
			serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
			if (tx_sink_valid) begin
				serial_tx_rs232phytx_next_value1 <= 1'd0;
				serial_tx_rs232phytx_next_value_ce1 <= 1'd1;
				tx_data_rs232phytx_next_value2 <= tx_sink_payload_data;
				tx_data_rs232phytx_next_value_ce2 <= 1'd1;
				basesoc_rs232phytx_next_state <= 1'd1;
			end
		end
	endcase
end
always @(*) begin
	rx_enable <= 1'd0;
	rx_data_rs232phyrx_next_value1 <= 8'd0;
	rx_data_rs232phyrx_next_value_ce1 <= 1'd0;
	rx_source_valid <= 1'd0;
	basesoc_rs232phyrx_next_state <= 1'd0;
	rx_count_rs232phyrx_next_value0 <= 4'd0;
	rx_count_rs232phyrx_next_value_ce0 <= 1'd0;
	rx_source_payload_data <= 8'd0;
	basesoc_rs232phyrx_next_state <= basesoc_rs232phyrx_state;
	case (basesoc_rs232phyrx_state)
		1'd1: begin
			rx_enable <= 1'd1;
			if (rx_tick) begin
				rx_count_rs232phyrx_next_value0 <= (rx_count + 1'd1);
				rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
				rx_data_rs232phyrx_next_value1 <= {rx_rx, rx_data[7:1]};
				rx_data_rs232phyrx_next_value_ce1 <= 1'd1;
				if ((rx_count == 4'd9)) begin
					rx_source_valid <= (rx_rx == 1'd1);
					rx_source_payload_data <= rx_data;
					basesoc_rs232phyrx_next_state <= 1'd0;
				end
			end
		end
		default: begin
			rx_count_rs232phyrx_next_value0 <= 1'd0;
			rx_count_rs232phyrx_next_value_ce0 <= 1'd1;
			if (((rx_rx == 1'd0) & (rx_rx_d == 1'd1))) begin
				basesoc_rs232phyrx_next_state <= 1'd1;
			end
		end
	endcase
end
assign uart_uart_sink_valid = rx_source_valid;
assign rx_source_ready = uart_uart_sink_ready;
assign uart_uart_sink_first = rx_source_first;
assign uart_uart_sink_last = rx_source_last;
assign uart_uart_sink_payload_data = rx_source_payload_data;
assign tx_sink_valid = uart_uart_source_valid;
assign uart_uart_source_ready = tx_sink_ready;
assign tx_sink_first = uart_uart_source_first;
assign tx_sink_last = uart_uart_source_last;
assign tx_sink_payload_data = uart_uart_source_payload_data;
assign uart_tx_fifo_sink_valid = uart_rxtx_re;
assign uart_tx_fifo_sink_payload_data = uart_rxtx_r;
assign uart_uart_source_valid = uart_tx_fifo_source_valid;
assign uart_tx_fifo_source_ready = uart_uart_source_ready;
assign uart_uart_source_first = uart_tx_fifo_source_first;
assign uart_uart_source_last = uart_tx_fifo_source_last;
assign uart_uart_source_payload_data = uart_tx_fifo_source_payload_data;
assign uart_txfull_status = (~uart_tx_fifo_sink_ready);
assign uart_txempty_status = (~uart_tx_fifo_source_valid);
assign uart_tx_trigger = uart_tx_fifo_sink_ready;
assign uart_rx_fifo_sink_valid = uart_uart_sink_valid;
assign uart_uart_sink_ready = uart_rx_fifo_sink_ready;
assign uart_rx_fifo_sink_first = uart_uart_sink_first;
assign uart_rx_fifo_sink_last = uart_uart_sink_last;
assign uart_rx_fifo_sink_payload_data = uart_uart_sink_payload_data;
assign uart_rxtx_w = uart_rx_fifo_source_payload_data;
assign uart_rx_fifo_source_ready = (uart_rx_clear | (1'd0 & uart_rxtx_we));
assign uart_rxempty_status = (~uart_rx_fifo_source_valid);
assign uart_rxfull_status = (~uart_rx_fifo_sink_ready);
assign uart_rx_trigger = uart_rx_fifo_source_valid;
assign uart_tx0 = uart_tx_status;
assign uart_tx1 = uart_tx_pending;
always @(*) begin
	uart_tx_clear <= 1'd0;
	if ((uart_pending_re & uart_pending_r[0])) begin
		uart_tx_clear <= 1'd1;
	end
end
assign uart_rx0 = uart_rx_status;
assign uart_rx1 = uart_rx_pending;
always @(*) begin
	uart_rx_clear <= 1'd0;
	if ((uart_pending_re & uart_pending_r[1])) begin
		uart_rx_clear <= 1'd1;
	end
end
assign uart_irq = ((uart_pending_status[0] & uart_enable_storage[0]) | (uart_pending_status[1] & uart_enable_storage[1]));
assign uart_tx_status = uart_tx_trigger;
assign uart_rx_status = uart_rx_trigger;
assign uart_tx_fifo_syncfifo_din = {uart_tx_fifo_fifo_in_last, uart_tx_fifo_fifo_in_first, uart_tx_fifo_fifo_in_payload_data};
assign {uart_tx_fifo_fifo_out_last, uart_tx_fifo_fifo_out_first, uart_tx_fifo_fifo_out_payload_data} = uart_tx_fifo_syncfifo_dout;
assign uart_tx_fifo_sink_ready = uart_tx_fifo_syncfifo_writable;
assign uart_tx_fifo_syncfifo_we = uart_tx_fifo_sink_valid;
assign uart_tx_fifo_fifo_in_first = uart_tx_fifo_sink_first;
assign uart_tx_fifo_fifo_in_last = uart_tx_fifo_sink_last;
assign uart_tx_fifo_fifo_in_payload_data = uart_tx_fifo_sink_payload_data;
assign uart_tx_fifo_source_valid = uart_tx_fifo_readable;
assign uart_tx_fifo_source_first = uart_tx_fifo_fifo_out_first;
assign uart_tx_fifo_source_last = uart_tx_fifo_fifo_out_last;
assign uart_tx_fifo_source_payload_data = uart_tx_fifo_fifo_out_payload_data;
assign uart_tx_fifo_re = uart_tx_fifo_source_ready;
assign uart_tx_fifo_syncfifo_re = (uart_tx_fifo_syncfifo_readable & ((~uart_tx_fifo_readable) | uart_tx_fifo_re));
assign uart_tx_fifo_level1 = (uart_tx_fifo_level0 + uart_tx_fifo_readable);
always @(*) begin
	uart_tx_fifo_wrport_adr <= 4'd0;
	if (uart_tx_fifo_replace) begin
		uart_tx_fifo_wrport_adr <= (uart_tx_fifo_produce - 1'd1);
	end else begin
		uart_tx_fifo_wrport_adr <= uart_tx_fifo_produce;
	end
end
assign uart_tx_fifo_wrport_dat_w = uart_tx_fifo_syncfifo_din;
assign uart_tx_fifo_wrport_we = (uart_tx_fifo_syncfifo_we & (uart_tx_fifo_syncfifo_writable | uart_tx_fifo_replace));
assign uart_tx_fifo_do_read = (uart_tx_fifo_syncfifo_readable & uart_tx_fifo_syncfifo_re);
assign uart_tx_fifo_rdport_adr = uart_tx_fifo_consume;
assign uart_tx_fifo_syncfifo_dout = uart_tx_fifo_rdport_dat_r;
assign uart_tx_fifo_rdport_re = uart_tx_fifo_do_read;
assign uart_tx_fifo_syncfifo_writable = (uart_tx_fifo_level0 != 5'd16);
assign uart_tx_fifo_syncfifo_readable = (uart_tx_fifo_level0 != 1'd0);
assign uart_rx_fifo_syncfifo_din = {uart_rx_fifo_fifo_in_last, uart_rx_fifo_fifo_in_first, uart_rx_fifo_fifo_in_payload_data};
assign {uart_rx_fifo_fifo_out_last, uart_rx_fifo_fifo_out_first, uart_rx_fifo_fifo_out_payload_data} = uart_rx_fifo_syncfifo_dout;
assign uart_rx_fifo_sink_ready = uart_rx_fifo_syncfifo_writable;
assign uart_rx_fifo_syncfifo_we = uart_rx_fifo_sink_valid;
assign uart_rx_fifo_fifo_in_first = uart_rx_fifo_sink_first;
assign uart_rx_fifo_fifo_in_last = uart_rx_fifo_sink_last;
assign uart_rx_fifo_fifo_in_payload_data = uart_rx_fifo_sink_payload_data;
assign uart_rx_fifo_source_valid = uart_rx_fifo_readable;
assign uart_rx_fifo_source_first = uart_rx_fifo_fifo_out_first;
assign uart_rx_fifo_source_last = uart_rx_fifo_fifo_out_last;
assign uart_rx_fifo_source_payload_data = uart_rx_fifo_fifo_out_payload_data;
assign uart_rx_fifo_re = uart_rx_fifo_source_ready;
assign uart_rx_fifo_syncfifo_re = (uart_rx_fifo_syncfifo_readable & ((~uart_rx_fifo_readable) | uart_rx_fifo_re));
assign uart_rx_fifo_level1 = (uart_rx_fifo_level0 + uart_rx_fifo_readable);
always @(*) begin
	uart_rx_fifo_wrport_adr <= 4'd0;
	if (uart_rx_fifo_replace) begin
		uart_rx_fifo_wrport_adr <= (uart_rx_fifo_produce - 1'd1);
	end else begin
		uart_rx_fifo_wrport_adr <= uart_rx_fifo_produce;
	end
end
assign uart_rx_fifo_wrport_dat_w = uart_rx_fifo_syncfifo_din;
assign uart_rx_fifo_wrport_we = (uart_rx_fifo_syncfifo_we & (uart_rx_fifo_syncfifo_writable | uart_rx_fifo_replace));
assign uart_rx_fifo_do_read = (uart_rx_fifo_syncfifo_readable & uart_rx_fifo_syncfifo_re);
assign uart_rx_fifo_rdport_adr = uart_rx_fifo_consume;
assign uart_rx_fifo_syncfifo_dout = uart_rx_fifo_rdport_dat_r;
assign uart_rx_fifo_rdport_re = uart_rx_fifo_do_read;
assign uart_rx_fifo_syncfifo_writable = (uart_rx_fifo_level0 != 5'd16);
assign uart_rx_fifo_syncfifo_readable = (uart_rx_fifo_level0 != 1'd0);
assign timer_zero_trigger = (timer_value == 1'd0);
assign timer_zero0 = timer_zero_status;
assign timer_zero1 = timer_zero_pending;
always @(*) begin
	timer_zero_clear <= 1'd0;
	if ((timer_pending_re & timer_pending_r)) begin
		timer_zero_clear <= 1'd1;
	end
end
assign timer_irq = (timer_pending_status & timer_enable_storage);
assign timer_zero_status = timer_zero_trigger;
assign crg_reset = crg_rst;
assign crg_clkin = clk12;
assign sys_clk = crg_clkout_buf0;
assign sys2x_clk = crg_clkout_buf1;
assign idelay_clk = crg_clkout_buf2;
assign adr = ram_bus_adr[13:0];
assign ram_bus_dat_r = dat_r;
always @(*) begin
	sram0_we <= 4'd0;
	sram0_we[0] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[0]);
	sram0_we[1] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[1]);
	sram0_we[2] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[2]);
	sram0_we[3] <= (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & interface0_ram_bus_we) & interface0_ram_bus_sel[3]);
end
assign sram0_adr = interface0_ram_bus_adr[13:0];
assign interface0_ram_bus_dat_r = sram0_dat_r;
assign sram0_dat_w = interface0_ram_bus_dat_w;
assign leds_wait = (~leds_done);
always @(*) begin
	leds_leds <= 2'd0;
	if ((leds_mode == 1'd1)) begin
		leds_leds <= leds_storage;
	end else begin
		leds_leds <= leds_chaser;
	end
end
assign {user_led1, user_led0} = (leds_leds ^ 1'd0);
assign leds_done = (leds_count == 1'd0);
always @(*) begin
	sram1_we <= 4'd0;
	sram1_we[0] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[0]);
	sram1_we[1] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[1]);
	sram1_we[2] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[2]);
	sram1_we[3] <= (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & interface1_ram_bus_we) & interface1_ram_bus_sel[3]);
end
assign sram1_adr = interface1_ram_bus_adr[5:0];
assign interface1_ram_bus_dat_r = sram1_dat_r;
assign sram1_dat_w = interface1_ram_bus_dat_w;
always @(*) begin
	basesoc_wishbone_ack <= 1'd0;
	basesoc_dat_w <= 32'd0;
	basesoc_next_state <= 1'd0;
	basesoc_wishbone_dat_r <= 32'd0;
	basesoc_adr <= 14'd0;
	basesoc_we <= 1'd0;
	basesoc_next_state <= basesoc_state;
	case (basesoc_state)
		1'd1: begin
			basesoc_wishbone_ack <= 1'd1;
			basesoc_wishbone_dat_r <= basesoc_dat_r;
			basesoc_next_state <= 1'd0;
		end
		default: begin
			basesoc_dat_w <= basesoc_wishbone_dat_w;
			if ((basesoc_wishbone_cyc & basesoc_wishbone_stb)) begin
				basesoc_adr <= basesoc_wishbone_adr;
				basesoc_we <= (basesoc_wishbone_we & (basesoc_wishbone_sel != 1'd0));
				basesoc_next_state <= 1'd1;
			end
		end
	endcase
end
assign shared_adr = array_muxed0;
assign shared_dat_w = array_muxed1;
assign shared_sel = array_muxed2;
assign shared_cyc = array_muxed3;
assign shared_stb = array_muxed4;
assign shared_we = array_muxed5;
assign shared_cti = array_muxed6;
assign shared_bte = array_muxed7;
assign a2o_dbus_dat_r = shared_dat_r;
assign a2o_dbus_ack = (shared_ack & (grant == 1'd0));
assign a2o_dbus_err = (shared_err & (grant == 1'd0));
assign request = {a2o_dbus_cyc};
assign grant = 1'd0;
always @(*) begin
	slave_sel <= 4'd0;
	slave_sel[0] <= (shared_adr[29:14] == 1'd0);
	slave_sel[1] <= (shared_adr[29:14] == 1'd1);
	slave_sel[2] <= (shared_adr[29:6] == 13'd4096);
	slave_sel[3] <= (shared_adr[29:14] == 16'd65520);
end
assign ram_bus_adr = shared_adr;
assign ram_bus_dat_w = shared_dat_w;
assign ram_bus_sel = shared_sel;
assign ram_bus_stb = shared_stb;
assign ram_bus_we = shared_we;
assign ram_bus_cti = shared_cti;
assign ram_bus_bte = shared_bte;
assign interface0_ram_bus_adr = shared_adr;
assign interface0_ram_bus_dat_w = shared_dat_w;
assign interface0_ram_bus_sel = shared_sel;
assign interface0_ram_bus_stb = shared_stb;
assign interface0_ram_bus_we = shared_we;
assign interface0_ram_bus_cti = shared_cti;
assign interface0_ram_bus_bte = shared_bte;
assign interface1_ram_bus_adr = shared_adr;
assign interface1_ram_bus_dat_w = shared_dat_w;
assign interface1_ram_bus_sel = shared_sel;
assign interface1_ram_bus_stb = shared_stb;
assign interface1_ram_bus_we = shared_we;
assign interface1_ram_bus_cti = shared_cti;
assign interface1_ram_bus_bte = shared_bte;
assign basesoc_wishbone_adr = shared_adr;
assign basesoc_wishbone_dat_w = shared_dat_w;
assign basesoc_wishbone_sel = shared_sel;
assign basesoc_wishbone_stb = shared_stb;
assign basesoc_wishbone_we = shared_we;
assign basesoc_wishbone_cti = shared_cti;
assign basesoc_wishbone_bte = shared_bte;
assign ram_bus_cyc = (shared_cyc & slave_sel[0]);
assign interface0_ram_bus_cyc = (shared_cyc & slave_sel[1]);
assign interface1_ram_bus_cyc = (shared_cyc & slave_sel[2]);
assign basesoc_wishbone_cyc = (shared_cyc & slave_sel[3]);
assign shared_err = (((ram_bus_err | interface0_ram_bus_err) | interface1_ram_bus_err) | basesoc_wishbone_err);
assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack));
always @(*) begin
	shared_ack <= 1'd0;
	error <= 1'd0;
	shared_dat_r <= 32'd0;
	shared_ack <= (((ram_bus_ack | interface0_ram_bus_ack) | interface1_ram_bus_ack) | basesoc_wishbone_ack);
	shared_dat_r <= (((({32{slave_sel_r[0]}} & ram_bus_dat_r) | ({32{slave_sel_r[1]}} & interface0_ram_bus_dat_r)) | ({32{slave_sel_r[2]}} & interface1_ram_bus_dat_r)) | ({32{slave_sel_r[3]}} & basesoc_wishbone_dat_r));
	if (done) begin
		shared_dat_r <= 32'd4294967295;
		shared_ack <= 1'd1;
		error <= 1'd1;
	end
end
assign done = (count == 1'd0);
assign csr_bankarray_csrbank0_sel = (csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4);
assign csr_bankarray_csrbank0_in_r = csr_bankarray_interface0_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank0_in_we <= 1'd0;
	csr_bankarray_csrbank0_in_re <= 1'd0;
	if ((csr_bankarray_csrbank0_sel & (csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin
		csr_bankarray_csrbank0_in_re <= csr_bankarray_interface0_bank_bus_we;
		csr_bankarray_csrbank0_in_we <= (~csr_bankarray_interface0_bank_bus_we);
	end
end
assign csr_bankarray_csrbank0_in_w = buttons_status[1:0];
assign buttons_we = csr_bankarray_csrbank0_in_we;
assign csr_bankarray_csrbank1_sel = (csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd5);
assign csr_bankarray_csrbank1_reset0_r = csr_bankarray_interface1_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank1_reset0_we <= 1'd0;
	csr_bankarray_csrbank1_reset0_re <= 1'd0;
	if ((csr_bankarray_csrbank1_sel & (csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin
		csr_bankarray_csrbank1_reset0_re <= csr_bankarray_interface1_bank_bus_we;
		csr_bankarray_csrbank1_reset0_we <= (~csr_bankarray_interface1_bank_bus_we);
	end
end
assign csr_bankarray_csrbank1_scratch0_r = csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
	csr_bankarray_csrbank1_scratch0_re <= 1'd0;
	csr_bankarray_csrbank1_scratch0_we <= 1'd0;
	if ((csr_bankarray_csrbank1_sel & (csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin
		csr_bankarray_csrbank1_scratch0_re <= csr_bankarray_interface1_bank_bus_we;
		csr_bankarray_csrbank1_scratch0_we <= (~csr_bankarray_interface1_bank_bus_we);
	end
end
assign csr_bankarray_csrbank1_bus_errors_r = csr_bankarray_interface1_bank_bus_dat_w[31:0];
always @(*) begin
	csr_bankarray_csrbank1_bus_errors_we <= 1'd0;
	csr_bankarray_csrbank1_bus_errors_re <= 1'd0;
	if ((csr_bankarray_csrbank1_sel & (csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin
		csr_bankarray_csrbank1_bus_errors_re <= csr_bankarray_interface1_bank_bus_we;
		csr_bankarray_csrbank1_bus_errors_we <= (~csr_bankarray_interface1_bank_bus_we);
	end
end
always @(*) begin
	soc_rst <= 1'd0;
	if (reset_re) begin
		soc_rst <= reset_storage[0];
	end
end
assign cpu_rst = reset_storage[1];
assign csr_bankarray_csrbank1_reset0_w = reset_storage[1:0];
assign csr_bankarray_csrbank1_scratch0_w = scratch_storage[31:0];
assign csr_bankarray_csrbank1_bus_errors_w = bus_errors_status[31:0];
assign bus_errors_we = csr_bankarray_csrbank1_bus_errors_we;
assign csr_bankarray_sel = (csr_bankarray_sram_bus_adr[13:9] == 3'd6);
always @(*) begin
	csr_bankarray_sram_bus_dat_r <= 32'd0;
	if (csr_bankarray_sel_r) begin
		csr_bankarray_sram_bus_dat_r <= csr_bankarray_dat_r;
	end
end
assign csr_bankarray_adr = csr_bankarray_sram_bus_adr[4:0];
assign csr_bankarray_csrbank2_sel = (csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3);
assign csr_bankarray_csrbank2_out0_r = csr_bankarray_interface2_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank2_out0_re <= 1'd0;
	csr_bankarray_csrbank2_out0_we <= 1'd0;
	if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin
		csr_bankarray_csrbank2_out0_re <= csr_bankarray_interface2_bank_bus_we;
		csr_bankarray_csrbank2_out0_we <= (~csr_bankarray_interface2_bank_bus_we);
	end
end
assign csr_bankarray_csrbank2_out0_w = leds_storage[1:0];
assign csr_bankarray_csrbank3_sel = (csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd7);
assign csr_bankarray_csrbank3_load0_r = csr_bankarray_interface3_bank_bus_dat_w[31:0];
always @(*) begin
	csr_bankarray_csrbank3_load0_re <= 1'd0;
	csr_bankarray_csrbank3_load0_we <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin
		csr_bankarray_csrbank3_load0_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_load0_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_reload0_r = csr_bankarray_interface3_bank_bus_dat_w[31:0];
always @(*) begin
	csr_bankarray_csrbank3_reload0_we <= 1'd0;
	csr_bankarray_csrbank3_reload0_re <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd1))) begin
		csr_bankarray_csrbank3_reload0_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_reload0_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_en0_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank3_en0_re <= 1'd0;
	csr_bankarray_csrbank3_en0_we <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin
		csr_bankarray_csrbank3_en0_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_en0_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_update_value0_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank3_update_value0_re <= 1'd0;
	csr_bankarray_csrbank3_update_value0_we <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd3))) begin
		csr_bankarray_csrbank3_update_value0_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_update_value0_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_value_r = csr_bankarray_interface3_bank_bus_dat_w[31:0];
always @(*) begin
	csr_bankarray_csrbank3_value_we <= 1'd0;
	csr_bankarray_csrbank3_value_re <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd4))) begin
		csr_bankarray_csrbank3_value_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_value_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_ev_status_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank3_ev_status_re <= 1'd0;
	csr_bankarray_csrbank3_ev_status_we <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin
		csr_bankarray_csrbank3_ev_status_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_ev_status_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_ev_pending_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank3_ev_pending_re <= 1'd0;
	csr_bankarray_csrbank3_ev_pending_we <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd6))) begin
		csr_bankarray_csrbank3_ev_pending_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_ev_pending_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_ev_enable0_r = csr_bankarray_interface3_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank3_ev_enable0_we <= 1'd0;
	csr_bankarray_csrbank3_ev_enable0_re <= 1'd0;
	if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd7))) begin
		csr_bankarray_csrbank3_ev_enable0_re <= csr_bankarray_interface3_bank_bus_we;
		csr_bankarray_csrbank3_ev_enable0_we <= (~csr_bankarray_interface3_bank_bus_we);
	end
end
assign csr_bankarray_csrbank3_load0_w = timer_load_storage[31:0];
assign csr_bankarray_csrbank3_reload0_w = timer_reload_storage[31:0];
assign csr_bankarray_csrbank3_en0_w = timer_en_storage;
assign csr_bankarray_csrbank3_update_value0_w = timer_update_value_storage;
assign csr_bankarray_csrbank3_value_w = timer_value_status[31:0];
assign timer_value_we = csr_bankarray_csrbank3_value_we;
assign timer_status_status = timer_zero0;
assign csr_bankarray_csrbank3_ev_status_w = timer_status_status;
assign timer_status_we = csr_bankarray_csrbank3_ev_status_we;
assign timer_pending_status = timer_zero1;
assign csr_bankarray_csrbank3_ev_pending_w = timer_pending_status;
assign timer_pending_we = csr_bankarray_csrbank3_ev_pending_we;
assign timer_zero2 = timer_enable_storage;
assign csr_bankarray_csrbank3_ev_enable0_w = timer_enable_storage;
assign csr_bankarray_csrbank4_sel = (csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8);
assign uart_rxtx_r = csr_bankarray_interface4_bank_bus_dat_w[7:0];
always @(*) begin
	uart_rxtx_we <= 1'd0;
	uart_rxtx_re <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin
		uart_rxtx_re <= csr_bankarray_interface4_bank_bus_we;
		uart_rxtx_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_txfull_r = csr_bankarray_interface4_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank4_txfull_we <= 1'd0;
	csr_bankarray_csrbank4_txfull_re <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin
		csr_bankarray_csrbank4_txfull_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_txfull_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_rxempty_r = csr_bankarray_interface4_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank4_rxempty_re <= 1'd0;
	csr_bankarray_csrbank4_rxempty_we <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd2))) begin
		csr_bankarray_csrbank4_rxempty_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_rxempty_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_ev_status_r = csr_bankarray_interface4_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank4_ev_status_re <= 1'd0;
	csr_bankarray_csrbank4_ev_status_we <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd3))) begin
		csr_bankarray_csrbank4_ev_status_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_ev_status_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_ev_pending_r = csr_bankarray_interface4_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank4_ev_pending_we <= 1'd0;
	csr_bankarray_csrbank4_ev_pending_re <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd4))) begin
		csr_bankarray_csrbank4_ev_pending_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_ev_pending_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_ev_enable0_r = csr_bankarray_interface4_bank_bus_dat_w[1:0];
always @(*) begin
	csr_bankarray_csrbank4_ev_enable0_re <= 1'd0;
	csr_bankarray_csrbank4_ev_enable0_we <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin
		csr_bankarray_csrbank4_ev_enable0_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_ev_enable0_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_txempty_r = csr_bankarray_interface4_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank4_txempty_re <= 1'd0;
	csr_bankarray_csrbank4_txempty_we <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd6))) begin
		csr_bankarray_csrbank4_txempty_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_txempty_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_rxfull_r = csr_bankarray_interface4_bank_bus_dat_w[0];
always @(*) begin
	csr_bankarray_csrbank4_rxfull_we <= 1'd0;
	csr_bankarray_csrbank4_rxfull_re <= 1'd0;
	if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd7))) begin
		csr_bankarray_csrbank4_rxfull_re <= csr_bankarray_interface4_bank_bus_we;
		csr_bankarray_csrbank4_rxfull_we <= (~csr_bankarray_interface4_bank_bus_we);
	end
end
assign csr_bankarray_csrbank4_txfull_w = uart_txfull_status;
assign uart_txfull_we = csr_bankarray_csrbank4_txfull_we;
assign csr_bankarray_csrbank4_rxempty_w = uart_rxempty_status;
assign uart_rxempty_we = csr_bankarray_csrbank4_rxempty_we;
always @(*) begin
	uart_status_status <= 2'd0;
	uart_status_status[0] <= uart_tx0;
	uart_status_status[1] <= uart_rx0;
end
assign csr_bankarray_csrbank4_ev_status_w = uart_status_status[1:0];
assign uart_status_we = csr_bankarray_csrbank4_ev_status_we;
always @(*) begin
	uart_pending_status <= 2'd0;
	uart_pending_status[0] <= uart_tx1;
	uart_pending_status[1] <= uart_rx1;
end
assign csr_bankarray_csrbank4_ev_pending_w = uart_pending_status[1:0];
assign uart_pending_we = csr_bankarray_csrbank4_ev_pending_we;
assign uart_tx2 = uart_enable_storage[0];
assign uart_rx2 = uart_enable_storage[1];
assign csr_bankarray_csrbank4_ev_enable0_w = uart_enable_storage[1:0];
assign csr_bankarray_csrbank4_txempty_w = uart_txempty_status;
assign uart_txempty_we = csr_bankarray_csrbank4_txempty_we;
assign csr_bankarray_csrbank4_rxfull_w = uart_rxfull_status;
assign uart_rxfull_we = csr_bankarray_csrbank4_rxfull_we;
assign csr_interconnect_adr = basesoc_adr;
assign csr_interconnect_we = basesoc_we;
assign csr_interconnect_dat_w = basesoc_dat_w;
assign basesoc_dat_r = csr_interconnect_dat_r;
assign csr_bankarray_interface0_bank_bus_adr = csr_interconnect_adr;
assign csr_bankarray_interface1_bank_bus_adr = csr_interconnect_adr;
assign csr_bankarray_interface2_bank_bus_adr = csr_interconnect_adr;
assign csr_bankarray_interface3_bank_bus_adr = csr_interconnect_adr;
assign csr_bankarray_interface4_bank_bus_adr = csr_interconnect_adr;
assign csr_bankarray_sram_bus_adr = csr_interconnect_adr;
assign csr_bankarray_interface0_bank_bus_we = csr_interconnect_we;
assign csr_bankarray_interface1_bank_bus_we = csr_interconnect_we;
assign csr_bankarray_interface2_bank_bus_we = csr_interconnect_we;
assign csr_bankarray_interface3_bank_bus_we = csr_interconnect_we;
assign csr_bankarray_interface4_bank_bus_we = csr_interconnect_we;
assign csr_bankarray_sram_bus_we = csr_interconnect_we;
assign csr_bankarray_interface0_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_bankarray_interface1_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_bankarray_interface2_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_bankarray_interface3_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_bankarray_interface4_bank_bus_dat_w = csr_interconnect_dat_w;
assign csr_bankarray_sram_bus_dat_w = csr_interconnect_dat_w;
assign csr_interconnect_dat_r = (((((csr_bankarray_interface0_bank_bus_dat_r | csr_bankarray_interface1_bank_bus_dat_r) | csr_bankarray_interface2_bank_bus_dat_r) | csr_bankarray_interface3_bank_bus_dat_r) | csr_bankarray_interface4_bank_bus_dat_r) | csr_bankarray_sram_bus_dat_r);
always @(*) begin
	array_muxed0 <= 30'd0;
	case (grant)
		default: begin
			array_muxed0 <= a2o_dbus_adr;
		end
	endcase
end
always @(*) begin
	array_muxed1 <= 32'd0;
	case (grant)
		default: begin
			array_muxed1 <= a2o_dbus_dat_w;
		end
	endcase
end
always @(*) begin
	array_muxed2 <= 4'd0;
	case (grant)
		default: begin
			array_muxed2 <= a2o_dbus_sel;
		end
	endcase
end
always @(*) begin
	array_muxed3 <= 1'd0;
	case (grant)
		default: begin
			array_muxed3 <= a2o_dbus_cyc;
		end
	endcase
end
always @(*) begin
	array_muxed4 <= 1'd0;
	case (grant)
		default: begin
			array_muxed4 <= a2o_dbus_stb;
		end
	endcase
end
always @(*) begin
	array_muxed5 <= 1'd0;
	case (grant)
		default: begin
			array_muxed5 <= a2o_dbus_we;
		end
	endcase
end
always @(*) begin
	array_muxed6 <= 3'd0;
	case (grant)
		default: begin
			array_muxed6 <= a2o_dbus_cti;
		end
	endcase
end
always @(*) begin
	array_muxed7 <= 2'd0;
	case (grant)
		default: begin
			array_muxed7 <= a2o_dbus_bte;
		end
	endcase
end
assign rx_rx = xilinxmultiregimpl0_regs1;
assign xilinxasyncresetsynchronizerimpl0 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl1 = (~crg_locked);
assign xilinxasyncresetsynchronizerimpl2 = (~crg_locked);
assign buttons_status = xilinxmultiregimpl1_regs1;
assign xilinxmultiregimpl1 = {user_btn1, user_btn0};


//------------------------------------------------------------------------------
// Synchronous Logic
//------------------------------------------------------------------------------

always @(posedge idelay_clk) begin
	if ((crg_reset_counter != 1'd0)) begin
		crg_reset_counter <= (crg_reset_counter - 1'd1);
	end else begin
		crg_ic_reset <= 1'd0;
	end
	if (idelay_rst) begin
		crg_reset_counter <= 4'd15;
		crg_ic_reset <= 1'd1;
	end
end

always @(posedge sys_clk) begin
	if ((bus_errors != 32'd4294967295)) begin
		if (bus_error) begin
			bus_errors <= (bus_errors + 1'd1);
		end
	end
	{tx_tick, tx_phase} <= 23'd4947802;
	if (tx_enable) begin
		{tx_tick, tx_phase} <= (tx_phase + 23'd4947802);
	end
	basesoc_rs232phytx_state <= basesoc_rs232phytx_next_state;
	if (tx_count_rs232phytx_next_value_ce0) begin
		tx_count <= tx_count_rs232phytx_next_value0;
	end
	if (serial_tx_rs232phytx_next_value_ce1) begin
		serial_tx <= serial_tx_rs232phytx_next_value1;
	end
	if (tx_data_rs232phytx_next_value_ce2) begin
		tx_data <= tx_data_rs232phytx_next_value2;
	end
	rx_rx_d <= rx_rx;
	{rx_tick, rx_phase} <= 32'd2147483648;
	if (rx_enable) begin
		{rx_tick, rx_phase} <= (rx_phase + 23'd4947802);
	end
	basesoc_rs232phyrx_state <= basesoc_rs232phyrx_next_state;
	if (rx_count_rs232phyrx_next_value_ce0) begin
		rx_count <= rx_count_rs232phyrx_next_value0;
	end
	if (rx_data_rs232phyrx_next_value_ce1) begin
		rx_data <= rx_data_rs232phyrx_next_value1;
	end
	if (uart_tx_clear) begin
		uart_tx_pending <= 1'd0;
	end
	uart_tx_trigger_d <= uart_tx_trigger;
	if ((uart_tx_trigger & (~uart_tx_trigger_d))) begin
		uart_tx_pending <= 1'd1;
	end
	if (uart_rx_clear) begin
		uart_rx_pending <= 1'd0;
	end
	uart_rx_trigger_d <= uart_rx_trigger;
	if ((uart_rx_trigger & (~uart_rx_trigger_d))) begin
		uart_rx_pending <= 1'd1;
	end
	if (uart_tx_fifo_syncfifo_re) begin
		uart_tx_fifo_readable <= 1'd1;
	end else begin
		if (uart_tx_fifo_re) begin
			uart_tx_fifo_readable <= 1'd0;
		end
	end
	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
		uart_tx_fifo_produce <= (uart_tx_fifo_produce + 1'd1);
	end
	if (uart_tx_fifo_do_read) begin
		uart_tx_fifo_consume <= (uart_tx_fifo_consume + 1'd1);
	end
	if (((uart_tx_fifo_syncfifo_we & uart_tx_fifo_syncfifo_writable) & (~uart_tx_fifo_replace))) begin
		if ((~uart_tx_fifo_do_read)) begin
			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 + 1'd1);
		end
	end else begin
		if (uart_tx_fifo_do_read) begin
			uart_tx_fifo_level0 <= (uart_tx_fifo_level0 - 1'd1);
		end
	end
	if (uart_rx_fifo_syncfifo_re) begin
		uart_rx_fifo_readable <= 1'd1;
	end else begin
		if (uart_rx_fifo_re) begin
			uart_rx_fifo_readable <= 1'd0;
		end
	end
	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
		uart_rx_fifo_produce <= (uart_rx_fifo_produce + 1'd1);
	end
	if (uart_rx_fifo_do_read) begin
		uart_rx_fifo_consume <= (uart_rx_fifo_consume + 1'd1);
	end
	if (((uart_rx_fifo_syncfifo_we & uart_rx_fifo_syncfifo_writable) & (~uart_rx_fifo_replace))) begin
		if ((~uart_rx_fifo_do_read)) begin
			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 + 1'd1);
		end
	end else begin
		if (uart_rx_fifo_do_read) begin
			uart_rx_fifo_level0 <= (uart_rx_fifo_level0 - 1'd1);
		end
	end
	if (timer_en_storage) begin
		if ((timer_value == 1'd0)) begin
			timer_value <= timer_reload_storage;
		end else begin
			timer_value <= (timer_value - 1'd1);
		end
	end else begin
		timer_value <= timer_load_storage;
	end
	if (timer_update_value_re) begin
		timer_value_status <= timer_value;
	end
	if (timer_zero_clear) begin
		timer_zero_pending <= 1'd0;
	end
	timer_zero_trigger_d <= timer_zero_trigger;
	if ((timer_zero_trigger & (~timer_zero_trigger_d))) begin
		timer_zero_pending <= 1'd1;
	end
	ram_bus_ack <= 1'd0;
	if (((ram_bus_cyc & ram_bus_stb) & ((~ram_bus_ack) | adr_burst))) begin
		ram_bus_ack <= 1'd1;
	end
	interface0_ram_bus_ack <= 1'd0;
	if (((interface0_ram_bus_cyc & interface0_ram_bus_stb) & ((~interface0_ram_bus_ack) | sram0_adr_burst))) begin
		interface0_ram_bus_ack <= 1'd1;
	end
	if (leds_done) begin
		leds_chaser <= {leds_chaser, (~leds_chaser[1])};
	end
	if (leds_re) begin
		leds_mode <= 1'd1;
	end
	if (leds_wait) begin
		if ((~leds_done)) begin
			leds_count <= (leds_count - 1'd1);
		end
	end else begin
		leds_count <= 25'd25000000;
	end
	interface1_ram_bus_ack <= 1'd0;
	if (((interface1_ram_bus_cyc & interface1_ram_bus_stb) & ((~interface1_ram_bus_ack) | sram1_adr_burst))) begin
		interface1_ram_bus_ack <= 1'd1;
	end
	basesoc_state <= basesoc_next_state;
	slave_sel_r <= slave_sel;
	if (wait_1) begin
		if ((~done)) begin
			count <= (count - 1'd1);
		end
	end else begin
		count <= 20'd1000000;
	end
	csr_bankarray_interface0_bank_bus_dat_r <= 1'd0;
	if (csr_bankarray_csrbank0_sel) begin
		case (csr_bankarray_interface0_bank_bus_adr[8:0])
			1'd0: begin
				csr_bankarray_interface0_bank_bus_dat_r <= csr_bankarray_csrbank0_in_w;
			end
		endcase
	end
	buttons_re <= csr_bankarray_csrbank0_in_re;
	csr_bankarray_interface1_bank_bus_dat_r <= 1'd0;
	if (csr_bankarray_csrbank1_sel) begin
		case (csr_bankarray_interface1_bank_bus_adr[8:0])
			1'd0: begin
				csr_bankarray_interface1_bank_bus_dat_r <= csr_bankarray_csrbank1_reset0_w;
			end
			1'd1: begin
				csr_bankarray_interface1_bank_bus_dat_r <= csr_bankarray_csrbank1_scratch0_w;
			end
			2'd2: begin
				csr_bankarray_interface1_bank_bus_dat_r <= csr_bankarray_csrbank1_bus_errors_w;
			end
		endcase
	end
	if (csr_bankarray_csrbank1_reset0_re) begin
		reset_storage[1:0] <= csr_bankarray_csrbank1_reset0_r;
	end
	reset_re <= csr_bankarray_csrbank1_reset0_re;
	if (csr_bankarray_csrbank1_scratch0_re) begin
		scratch_storage[31:0] <= csr_bankarray_csrbank1_scratch0_r;
	end
	scratch_re <= csr_bankarray_csrbank1_scratch0_re;
	bus_errors_re <= csr_bankarray_csrbank1_bus_errors_re;
	csr_bankarray_sel_r <= csr_bankarray_sel;
	csr_bankarray_interface2_bank_bus_dat_r <= 1'd0;
	if (csr_bankarray_csrbank2_sel) begin
		case (csr_bankarray_interface2_bank_bus_adr[8:0])
			1'd0: begin
				csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_out0_w;
			end
		endcase
	end
	if (csr_bankarray_csrbank2_out0_re) begin
		leds_storage[1:0] <= csr_bankarray_csrbank2_out0_r;
	end
	leds_re <= csr_bankarray_csrbank2_out0_re;
	csr_bankarray_interface3_bank_bus_dat_r <= 1'd0;
	if (csr_bankarray_csrbank3_sel) begin
		case (csr_bankarray_interface3_bank_bus_adr[8:0])
			1'd0: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_load0_w;
			end
			1'd1: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_reload0_w;
			end
			2'd2: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_en0_w;
			end
			2'd3: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_update_value0_w;
			end
			3'd4: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_value_w;
			end
			3'd5: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_status_w;
			end
			3'd6: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_pending_w;
			end
			3'd7: begin
				csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_enable0_w;
			end
		endcase
	end
	if (csr_bankarray_csrbank3_load0_re) begin
		timer_load_storage[31:0] <= csr_bankarray_csrbank3_load0_r;
	end
	timer_load_re <= csr_bankarray_csrbank3_load0_re;
	if (csr_bankarray_csrbank3_reload0_re) begin
		timer_reload_storage[31:0] <= csr_bankarray_csrbank3_reload0_r;
	end
	timer_reload_re <= csr_bankarray_csrbank3_reload0_re;
	if (csr_bankarray_csrbank3_en0_re) begin
		timer_en_storage <= csr_bankarray_csrbank3_en0_r;
	end
	timer_en_re <= csr_bankarray_csrbank3_en0_re;
	if (csr_bankarray_csrbank3_update_value0_re) begin
		timer_update_value_storage <= csr_bankarray_csrbank3_update_value0_r;
	end
	timer_update_value_re <= csr_bankarray_csrbank3_update_value0_re;
	timer_value_re <= csr_bankarray_csrbank3_value_re;
	timer_status_re <= csr_bankarray_csrbank3_ev_status_re;
	if (csr_bankarray_csrbank3_ev_pending_re) begin
		timer_pending_r <= csr_bankarray_csrbank3_ev_pending_r;
	end
	timer_pending_re <= csr_bankarray_csrbank3_ev_pending_re;
	if (csr_bankarray_csrbank3_ev_enable0_re) begin
		timer_enable_storage <= csr_bankarray_csrbank3_ev_enable0_r;
	end
	timer_enable_re <= csr_bankarray_csrbank3_ev_enable0_re;
	csr_bankarray_interface4_bank_bus_dat_r <= 1'd0;
	if (csr_bankarray_csrbank4_sel) begin
		case (csr_bankarray_interface4_bank_bus_adr[8:0])
			1'd0: begin
				csr_bankarray_interface4_bank_bus_dat_r <= uart_rxtx_w;
			end
			1'd1: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_txfull_w;
			end
			2'd2: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_rxempty_w;
			end
			2'd3: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_ev_status_w;
			end
			3'd4: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_ev_pending_w;
			end
			3'd5: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_ev_enable0_w;
			end
			3'd6: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_txempty_w;
			end
			3'd7: begin
				csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_rxfull_w;
			end
		endcase
	end
	uart_txfull_re <= csr_bankarray_csrbank4_txfull_re;
	uart_rxempty_re <= csr_bankarray_csrbank4_rxempty_re;
	uart_status_re <= csr_bankarray_csrbank4_ev_status_re;
	if (csr_bankarray_csrbank4_ev_pending_re) begin
		uart_pending_r[1:0] <= csr_bankarray_csrbank4_ev_pending_r;
	end
	uart_pending_re <= csr_bankarray_csrbank4_ev_pending_re;
	if (csr_bankarray_csrbank4_ev_enable0_re) begin
		uart_enable_storage[1:0] <= csr_bankarray_csrbank4_ev_enable0_r;
	end
	uart_enable_re <= csr_bankarray_csrbank4_ev_enable0_re;
	uart_txempty_re <= csr_bankarray_csrbank4_txempty_re;
	uart_rxfull_re <= csr_bankarray_csrbank4_rxfull_re;
	if (sys_rst) begin
		reset_storage <= 2'd0;
		reset_re <= 1'd0;
		scratch_storage <= 32'd305419896;
		scratch_re <= 1'd0;
		bus_errors_re <= 1'd0;
		bus_errors <= 32'd0;
		serial_tx <= 1'd1;
		tx_tick <= 1'd0;
		rx_tick <= 1'd0;
		rx_rx_d <= 1'd0;
		uart_txfull_re <= 1'd0;
		uart_rxempty_re <= 1'd0;
		uart_tx_pending <= 1'd0;
		uart_tx_trigger_d <= 1'd0;
		uart_rx_pending <= 1'd0;
		uart_rx_trigger_d <= 1'd0;
		uart_status_re <= 1'd0;
		uart_pending_re <= 1'd0;
		uart_pending_r <= 2'd0;
		uart_enable_storage <= 2'd0;
		uart_enable_re <= 1'd0;
		uart_txempty_re <= 1'd0;
		uart_rxfull_re <= 1'd0;
		uart_tx_fifo_readable <= 1'd0;
		uart_tx_fifo_level0 <= 5'd0;
		uart_tx_fifo_produce <= 4'd0;
		uart_tx_fifo_consume <= 4'd0;
		uart_rx_fifo_readable <= 1'd0;
		uart_rx_fifo_level0 <= 5'd0;
		uart_rx_fifo_produce <= 4'd0;
		uart_rx_fifo_consume <= 4'd0;
		timer_load_storage <= 32'd0;
		timer_load_re <= 1'd0;
		timer_reload_storage <= 32'd0;
		timer_reload_re <= 1'd0;
		timer_en_storage <= 1'd0;
		timer_en_re <= 1'd0;
		timer_update_value_storage <= 1'd0;
		timer_update_value_re <= 1'd0;
		timer_value_status <= 32'd0;
		timer_value_re <= 1'd0;
		timer_zero_pending <= 1'd0;
		timer_zero_trigger_d <= 1'd0;
		timer_status_re <= 1'd0;
		timer_pending_re <= 1'd0;
		timer_pending_r <= 1'd0;
		timer_enable_storage <= 1'd0;
		timer_enable_re <= 1'd0;
		timer_value <= 32'd0;
		ram_bus_ack <= 1'd0;
		interface0_ram_bus_ack <= 1'd0;
		leds_storage <= 2'd0;
		leds_re <= 1'd0;
		leds_chaser <= 2'd0;
		leds_mode <= 1'd0;
		leds_count <= 25'd25000000;
		buttons_re <= 1'd0;
		interface1_ram_bus_ack <= 1'd0;
		slave_sel_r <= 4'd0;
		count <= 20'd1000000;
		csr_bankarray_sel_r <= 1'd0;
		basesoc_rs232phytx_state <= 1'd0;
		basesoc_rs232phyrx_state <= 1'd0;
		basesoc_state <= 1'd0;
	end
	xilinxmultiregimpl0_regs0 <= serial_rx;
	xilinxmultiregimpl0_regs1 <= xilinxmultiregimpl0_regs0;
	xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0};
	xilinxmultiregimpl1_regs1 <= xilinxmultiregimpl1_regs0;
end


//------------------------------------------------------------------------------
// Specialized Logic
//------------------------------------------------------------------------------

//------------------------------------------------------------------------------
// Memory mem: 29-words x 8-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: ---- | 
reg [7:0] mem[0:28];
initial begin
	$readmemh("cmod7_mem.init", mem);
end
reg [4:0] mem_adr0;
always @(posedge sys_clk) begin
	mem_adr0 <= csr_bankarray_adr;
end
assign csr_bankarray_dat_r = mem[mem_adr0];


//------------------------------------------------------------------------------
// Memory storage: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage[0:15];
reg [9:0] storage_dat0;
reg [9:0] storage_dat1;
always @(posedge sys_clk) begin
	if (uart_tx_fifo_wrport_we)
		storage[uart_tx_fifo_wrport_adr] <= uart_tx_fifo_wrport_dat_w;
	storage_dat0 <= storage[uart_tx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_tx_fifo_rdport_re)
		storage_dat1 <= storage[uart_tx_fifo_rdport_adr];
end
assign uart_tx_fifo_wrport_dat_r = storage_dat0;
assign uart_tx_fifo_rdport_dat_r = storage_dat1;


//------------------------------------------------------------------------------
// Memory storage_1: 16-words x 10-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Read-First  | Write-Granularity: 10 
// Port 1 | Read: Sync  | Write: ---- | 
reg [9:0] storage_1[0:15];
reg [9:0] storage_1_dat0;
reg [9:0] storage_1_dat1;
always @(posedge sys_clk) begin
	if (uart_rx_fifo_wrport_we)
		storage_1[uart_rx_fifo_wrport_adr] <= uart_rx_fifo_wrport_dat_w;
	storage_1_dat0 <= storage_1[uart_rx_fifo_wrport_adr];
end
always @(posedge sys_clk) begin
	if (uart_rx_fifo_rdport_re)
		storage_1_dat1 <= storage_1[uart_rx_fifo_rdport_adr];
end
assign uart_rx_fifo_wrport_dat_r = storage_1_dat0;
assign uart_rx_fifo_rdport_dat_r = storage_1_dat1;


BUFG BUFG(
	.I(crg_clkout0),
	.O(crg_clkout_buf0)
);

BUFG BUFG_1(
	.I(crg_clkout1),
	.O(crg_clkout_buf1)
);

BUFG BUFG_2(
	.I(crg_clkout2),
	.O(crg_clkout_buf2)
);

IDELAYCTRL IDELAYCTRL(
	.REFCLK(idelay_clk),
	.RST(crg_ic_reset)
);

//------------------------------------------------------------------------------
// Memory rom: 16384-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: ---- | 
reg [31:0] rom[0:16383];
initial begin
	$readmemh("cmod7_rom.init", rom);
end
reg [31:0] rom_dat0;
always @(posedge sys_clk) begin
	rom_dat0 <= rom[adr];
end
assign dat_r = rom_dat0;


//------------------------------------------------------------------------------
// Memory sram: 16384-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [31:0] sram[0:16383];
initial begin
	$readmemh("cmod7_sram.init", sram);
end
reg [13:0] sram_adr0;
always @(posedge sys_clk) begin
	if (sram0_we[0])
		sram[sram0_adr][7:0] <= sram0_dat_w[7:0];
	if (sram0_we[1])
		sram[sram0_adr][15:8] <= sram0_dat_w[15:8];
	if (sram0_we[2])
		sram[sram0_adr][23:16] <= sram0_dat_w[23:16];
	if (sram0_we[3])
		sram[sram0_adr][31:24] <= sram0_dat_w[31:24];
	sram_adr0 <= sram0_adr;
end
assign sram0_dat_r = sram[sram_adr0];


//------------------------------------------------------------------------------
// Memory main_ram: 64-words x 32-bit
//------------------------------------------------------------------------------
// Port 0 | Read: Sync  | Write: Sync | Mode: Write-First | Write-Granularity: 8 
reg [31:0] main_ram[0:63];
initial begin
	$readmemh("cmod7_main_ram.init", main_ram);
end
reg [5:0] main_ram_adr0;
always @(posedge sys_clk) begin
	if (sram1_we[0])
		main_ram[sram1_adr][7:0] <= sram1_dat_w[7:0];
	if (sram1_we[1])
		main_ram[sram1_adr][15:8] <= sram1_dat_w[15:8];
	if (sram1_we[2])
		main_ram[sram1_adr][23:16] <= sram1_dat_w[23:16];
	if (sram1_we[3])
		main_ram[sram1_adr][31:24] <= sram1_dat_w[31:24];
	main_ram_adr0 <= sram1_adr;
end
assign sram1_dat_r = main_ram[main_ram_adr0];


a2owb a2owb(
	.cfg_wr(1'd0),
	.clk_1x(sys_clk),
	.clk_2x(sys2x_clk),
	.externalInterrupt(a2o_interrupt[0]),
	.externalInterruptS(a2o_interruptS),
	.rst((sys_rst | a2o_reset)),
	.softwareInterrupt(a2o_interrupt[2]),
	.timerInterrupt(a2o_interrupt[1]),
	.wb_ack(a2o_dbus_ack),
	.wb_datr(a2o_dbus_dat_r),
	.wb_adr({a2o, a2o_dbus_adr}),
	.wb_cyc(a2o_dbus_cyc),
	.wb_datw(a2o_dbus_dat_w),
	.wb_sel(a2o_dbus_sel),
	.wb_stb(a2o_dbus_stb),
	.wb_we(a2o_dbus_we)
);

FDCE FDCE(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(crg_reset),
	.Q(basesoc_reset0)
);

FDCE FDCE_1(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset0),
	.Q(basesoc_reset1)
);

FDCE FDCE_2(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset1),
	.Q(basesoc_reset2)
);

FDCE FDCE_3(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset2),
	.Q(basesoc_reset3)
);

FDCE FDCE_4(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset3),
	.Q(basesoc_reset4)
);

FDCE FDCE_5(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset4),
	.Q(basesoc_reset5)
);

FDCE FDCE_6(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset5),
	.Q(basesoc_reset6)
);

FDCE FDCE_7(
	.C(crg_clkin),
	.CE(1'd1),
	.CLR(1'd0),
	.D(basesoc_reset6),
	.Q(basesoc_reset7)
);

MMCME2_ADV #(
	.BANDWIDTH("OPTIMIZED"),
	.CLKFBOUT_MULT_F(6'd50),
	.CLKIN1_PERIOD(83.33333333333333),
	.CLKOUT0_DIVIDE_F(3'd6),
	.CLKOUT0_PHASE(1'd0),
	.CLKOUT1_DIVIDE(2'd3),
	.CLKOUT1_PHASE(1'd0),
	.CLKOUT2_DIVIDE(2'd3),
	.CLKOUT2_PHASE(1'd0),
	.DIVCLK_DIVIDE(1'd1),
	.REF_JITTER1(0.01)
) MMCME2_ADV (
	.CLKFBIN(basesoc_mmcm_fb),
	.CLKIN1(crg_clkin),
	.PWRDWN(crg_power_down),
	.RST(basesoc_reset7),
	.CLKFBOUT(basesoc_mmcm_fb),
	.CLKOUT0(crg_clkout0),
	.CLKOUT1(crg_clkout1),
	.CLKOUT2(crg_clkout2),
	.LOCKED(crg_locked)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE (
	.C(sys_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(xilinxasyncresetsynchronizerimpl0_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_1 (
	.C(sys_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl0_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl0),
	.Q(sys_rst)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_2 (
	.C(sys2x_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(xilinxasyncresetsynchronizerimpl1_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_3 (
	.C(sys2x_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl1_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl1),
	.Q(xilinxasyncresetsynchronizerimpl1_expr)
);

(* ars_ff1 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_4 (
	.C(idelay_clk),
	.CE(1'd1),
	.D(1'd0),
	.PRE(xilinxasyncresetsynchronizerimpl2),
	.Q(xilinxasyncresetsynchronizerimpl2_rst_meta)
);

(* ars_ff2 = "true", async_reg = "true" *) FDPE #(
	.INIT(1'd1)
) FDPE_5 (
	.C(idelay_clk),
	.CE(1'd1),
	.D(xilinxasyncresetsynchronizerimpl2_rst_meta),
	.PRE(xilinxasyncresetsynchronizerimpl2),
	.Q(idelay_rst)
);

endmodule

// -----------------------------------------------------------------------------
//  Auto-Generated by LiteX on 2022-08-04 07:49:47.
//------------------------------------------------------------------------------
