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33 lines
976 B
Markdown
33 lines
976 B
Markdown
2 years ago
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# Testing RTL with new environments
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##
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* RTL
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* updated source to remove a bunch of Verilator warnings
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* updated source for compatibility with Icaraus -g2012
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* changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator
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* Verilator
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* can IFETCH some ops in ST and SMT2 mode
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* can't get cocotb to build with Verilator (very long compile times)
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* Icarus (w/cocotb)
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* executing boot code until test call with python A2L2 interface
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* Yosys
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* finishes compile
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## Next To Do
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* create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper)
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* create simple A2L2-WB RTL for easily connecting to Litex, etc.
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* create Litex core wrapper
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* OpenLane experiments with blackbox arrays and yosys/abc/sta
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* create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and valid table
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* parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.)
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