From 173e1ad5f1e5d84eb740d182a954a2fceee90d2c Mon Sep 17 00:00:00 2001
From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com>
Date: Sat, 16 Jul 2022 15:30:52 -0500
Subject: [PATCH] fix x's on unused t1 strands

---
 dev/verilog/trilib/tri_a2o.vh   | 2 +-
 dev/verilog/work/iuq_dispatch.v | 7 ++++++-
 dev/verilog/work/iuq_spr.v      | 1 +
 3 files changed, 8 insertions(+), 2 deletions(-)

diff --git a/dev/verilog/trilib/tri_a2o.vh b/dev/verilog/trilib/tri_a2o.vh
index 7e8e379..195fa0b 100755
--- a/dev/verilog/trilib/tri_a2o.vh
+++ b/dev/verilog/trilib/tri_a2o.vh
@@ -121,7 +121,7 @@
 `define  LQ_REL_PIPE_START 2
 `define  LQ_REL_PIPE_END 4
 `define  LOAD_CREDITS   8
-`define  STORE_CREDITS 4
+`define  STORE_CREDITS 4         //wtf 32 is normal; fpga bug needed 4
 `define  IUQ_ENTRIES   4 		   // Instruction Fetch Queue Size
 `define  MMQ_ENTRIES   2 		   // MMU Queue Size
 `define  CR_WIDTH 4
diff --git a/dev/verilog/work/iuq_dispatch.v b/dev/verilog/work/iuq_dispatch.v
index acbc45b..be1c48d 100755
--- a/dev/verilog/work/iuq_dispatch.v
+++ b/dev/verilog/work/iuq_dispatch.v
@@ -2318,8 +2318,13 @@ tri_xor2 sq_cmdq_send_cnt_t1_one (sq_cmdq_send_cnt_one[1],  sq_cmdq_send_cnt[1][
       end
    endgenerate
 
+//wtf (THREADS1 is def'd)
+// iverilog sez: ../../verilog/work/iuq_dispatch.v:2322: warning: @* found no sensitivities so it will never trigger.
+// seems to be correct behavior - block won't be entered without a value change
+// make it initial, or a generate?
 `ifdef THREADS1
-   always @(*)
+   //always @(*)
+   initial
    begin: thread1_credit_proc
       fx0_credit_cnt_minus_1[1] = 1'b0;
       fx0_credit_cnt_minus_2[1] = 1'b0;
diff --git a/dev/verilog/work/iuq_spr.v b/dev/verilog/work/iuq_spr.v
index b835e94..26a810f 100755
--- a/dev/verilog/work/iuq_spr.v
+++ b/dev/verilog/work/iuq_spr.v
@@ -786,6 +786,7 @@ module iuq_spr(
                .dout(ppr32_l2[i])
             );
 
+            //wtf these need INITs DEFINE'd!!
             // hex 0A0A0E0A = 168431114
             tri_rlmreg_p #(.WIDTH(32), .INIT(168431114)) cpcr2_reg(
                .vd(vdd),