diff --git a/dev/verilog/trilib/tri_a2o.vh b/dev/verilog/trilib/tri_a2o.vh index e53730c..0624eee 100755 --- a/dev/verilog/trilib/tri_a2o.vh +++ b/dev/verilog/trilib/tri_a2o.vh @@ -135,10 +135,11 @@ //wtf: change for verilatorsim - didnt help //`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT -`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT -//`define INIT_IUCR0 16'h0000 // BP disabled -`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +//`define INIT_IUCR0 16'h0000 // BP disabled +`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_XUCR0 32'h00000460 // normal `define INIT_MASK 2'b10 `define RELQ_INCLUDE 0 // Reload Queue Included diff --git a/dev/verilog/trilib/tri_parity_recovery.v b/dev/verilog/trilib/tri_parity_recovery.v index e65bc30..acec4cf 100755 --- a/dev/verilog/trilib/tri_parity_recovery.v +++ b/dev/verilog/trilib/tri_parity_recovery.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -124,7 +124,7 @@ module tri_parity_recovery( ); - parameter THREADS = 2; + //parameter THREADS = 2; input perr_si; output perr_so; @@ -714,11 +714,8 @@ module tri_parity_recovery( assign err_regfile_parity[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ce}}; assign err_regfile_ue[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ue}}; - - - generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_err_rpt_thr1 tri_direct_err_rpt #(.WIDTH(2)) fu_err_rpt( @@ -734,7 +731,7 @@ module tri_parity_recovery( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_err_rpt_thr2 tri_direct_err_rpt #(.WIDTH(4)) fu_err_rpt( diff --git a/dev/verilog/trilib/tri_serial_scom2.v b/dev/verilog/trilib/tri_serial_scom2.v index 5fd38fa..a34e660 100755 --- a/dev/verilog/trilib/tri_serial_scom2.v +++ b/dev/verilog/trilib/tri_serial_scom2.v @@ -417,9 +417,7 @@ module tri_serial_scom2( //----------------------------------------------------------------------------- // FSM: serial => parallel => serial state machine // - always @(state_lt or got_head or gor_eofwdata or got_eofwpar or got_ulhead or sent_rdata or - p0_err or any_ack_error or match or do_write or do_read or cch_lt[0] or dch_lt or - sc_ack or wpar_err or read_nvld) + always @* begin: fsm_transition next_state = state_lt; diff --git a/dev/verilog/work/fu.v b/dev/verilog/work/fu.v index 20bc552..fbe68be 100755 --- a/dev/verilog/work/fu.v +++ b/dev/verilog/work/fu.v @@ -802,7 +802,7 @@ module fu( //---------------------------------------------------------------------- // Floating Point Register, ex0 - fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC), .threads(`THREADS)) fpr( + fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC)) fpr( .nclk(nclk), .clkoff_b(clkoff_dc_b), .act_dis(act_dis), @@ -1219,7 +1219,7 @@ module fu( //---------------------------------------------------------------------- // Control and Decode - fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC), .THREADS(`THREADS)) dcd( + fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC)) dcd( // INPUTS .act_dis(act_dis), .bcfg_scan_in(bcfg_scan_in), diff --git a/dev/verilog/work/fu_dcd.v b/dev/verilog/work/fu_dcd.v index a7e2ffa..2defdf9 100755 --- a/dev/verilog/work/fu_dcd.v +++ b/dev/verilog/work/fu_dcd.v @@ -37,7 +37,8 @@ //* DESC: This is Control and Decode //* //***************************************************************************** - `include "tri_a2o.vh" + +`include "tri_a2o.vh" module fu_dcd( act_dis, @@ -357,7 +358,6 @@ module fu_dcd( rf0_act_b ); parameter EFF_IFAR = 62; - parameter THREADS = 2; parameter ITAG_SIZE_ENC = 7; parameter THREAD_POOL_ENC = 1; parameter CR_POOL_ENC = 5; @@ -1543,13 +1543,13 @@ module fu_dcd( assign cp_flush_int[0] = cp_flush[0]; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_flush_thr1_1 assign cp_flush_int[1] = tilo; end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_flush_thr2_1 assign cp_flush_int[1] = cp_flush[1]; end @@ -1602,7 +1602,7 @@ module fu_dcd( //------------------------------------------- generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_flush_thr1_2 assign xu_rf0_flush[0] = cp_flush_q[0]; assign xu_ex0_flush[0] = cp_flush_q[0]; @@ -1630,7 +1630,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_flush_thr2_2 assign xu_rf0_flush[0:1] = cp_flush_q[0:1]; assign xu_ex0_flush[0:1] = cp_flush_q[0:1]; @@ -1738,7 +1738,7 @@ module fu_dcd( // Act Latches generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_msr_bits_thr1_2 assign fu_msr_fp[0] = xu_fu_msr_fp[0]; assign fu_msr_fp[1] = tidn; @@ -1750,7 +1750,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_msr_bits_thr2_2 assign fu_msr_fp = xu_fu_msr_fp; assign fu_msr_fe0 = xu_fu_msr_fe0; @@ -1796,7 +1796,7 @@ module fu_dcd( assign rf0_instr_match = iu_fu_rf0_instr_match; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_tid_thr1_1 assign rf0_tid[0] = iu_fu_rf0_tid[0]; assign rf0_tid[1] = tidn; @@ -1804,14 +1804,14 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_tid_thr2_1 assign rf0_tid[0:1] = iu_fu_rf0_tid[0:1]; end endgenerate generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_axu0_vld_thr1_1 assign rf0_instr_tid_1hot[0] = rv_axu0_vld[0]; assign rf0_instr_tid_1hot[1] = 1'b0; //rv_axu0_v(1); @@ -1821,7 +1821,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_axu0_vld_thr2_1 assign rf0_instr_tid_1hot[0] = rv_axu0_vld[0]; assign rf0_instr_tid_1hot[1] = rv_axu0_vld[1]; //rv_axu0_v(1); @@ -2127,7 +2127,7 @@ module fu_dcd( // LOADS generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_loadaddr_thr_1 assign ex6_load_addr[0:7] = f_fpr_ex6_load_addr[0:7]; // no tid bit assign ex6_reload_addr[0:7] = f_fpr_ex6_reload_addr[0:7]; // no tid bit @@ -2135,7 +2135,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_loadaddr_thr_2 assign ex6_load_addr[0:7] = {f_fpr_ex6_load_addr[0], f_fpr_ex6_load_addr[7], f_fpr_ex6_load_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model assign ex6_reload_addr[0:7] = {f_fpr_ex6_reload_addr[0], f_fpr_ex6_reload_addr[7], f_fpr_ex6_reload_addr[1:6]}; // bit 7 is the tid but only in the 2 thread model @@ -2674,14 +2674,14 @@ module fu_dcd( assign ex2_ifar_val[0:3] = ex2_instr_valid[0:3]; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_store_data_val_thr1_1 assign fu_lq_ex2_store_data_val[0] = ex2_str_valid & ex2_instr_valid[0] & (~ex2_ucode_preissue) & (~ex2_abort_s); end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_store_data_val_thr2_1 assign fu_lq_ex2_store_data_val[0] = ex2_str_valid & ex2_instr_valid[0] & (~ex2_ucode_preissue) & (~ex2_abort_s); assign fu_lq_ex2_store_data_val[1] = ex2_str_valid & ex2_instr_valid[1] & (~ex2_ucode_preissue) & (~ex2_abort_s); @@ -3657,14 +3657,14 @@ module fu_dcd( assign axu0_cr_w4e = ex8_cr_val | ex8_record_v; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_cr_w4a_thr1_1 assign axu0_cr_w4a[0:4] = ex8_cr_bf[0:4]; end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_cr_w4a_thr2_1 assign axu0_cr_w4a[0:5] = {ex8_cr_bf[0:4], ex8_instr_tid[1]}; end @@ -3688,7 +3688,7 @@ module fu_dcd( assign ex5_any_cr_v = (|(ex5_instr_v) & (~ex5_divsqrt_v)) & (ex5_cr_val | ex5_record | ex5_mcrfs); generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_axu0_itag_vld_thr1_1 assign axu0_rv_itag_vld[0] = (ex3_instr_vns[0] & (~ex4_instr_vns[0]) & (~ex5_cr_or_divsqrt_v[0])) | @@ -3698,7 +3698,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_axu0_itag_vld_thr2_1 assign axu0_rv_itag_vld[0] = (ex3_instr_vns[0] & (~(|(ex4_instr_vns))) & (~(|(ex5_cr_or_divsqrt_v)))) | @@ -3734,14 +3734,14 @@ module fu_dcd( (f_dsq_ex6_divsqrt_instr_frt & {6{ ex6_divsqrt_v}}); generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_itag_vld_thr1_1 assign axu1_rv_itag_vld[0] = tidn; end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_itag_vld_thr2_1 assign axu1_rv_itag_vld = 2'b00; end @@ -3757,14 +3757,14 @@ module fu_dcd( // AXU0 Instruction Executed generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_exe0_vld_thr2_1 assign axu0_iu_execute_vld[0] = (ex8_instr_valid[0] | (ex8_fdivsqrt_start[0] & (ex8_b_den_flush | ex8_regfile_err_det[0]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); assign axu0_iu_execute_vld[1] = (ex8_instr_valid[1] | (ex8_fdivsqrt_start[1] & (ex8_b_den_flush | ex8_regfile_err_det[1]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); end endgenerate generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_exe0_vld_thr1_1 assign axu0_iu_execute_vld[0] = (ex8_instr_valid[0] | (ex8_fdivsqrt_start[0] & (ex8_b_den_flush | ex8_regfile_err_det[0]))) & (~ex8_abort) & (~ex8_perr_sm_instr_v); end @@ -3809,7 +3809,7 @@ module fu_dcd( (|(ex8_fu_unavail) | ex8_fpr_wr_dis)}; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_async_fex_thr1_1 assign axu0_iu_async_fex[0] = fp_async_fex_q[0]; assign spare_unused[12] = fp_async_fex_q[1]; @@ -3822,7 +3822,7 @@ module fu_dcd( endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_async_fex_thr2_1 assign axu0_iu_async_fex[0] = fp_async_fex_q[0]; assign axu0_iu_async_fex[1] = fp_async_fex_q[1]; @@ -3863,14 +3863,14 @@ module fu_dcd( // AXU1 Instruction Executed generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_exe_vld_thr1_1 assign axu1_iu_execute_vld = 1'b0; end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_exe_vld_thr2_1 assign axu1_iu_execute_vld = 2'b00; end @@ -3887,7 +3887,7 @@ module fu_dcd( //---------------------------------------------------------------------- // Parity State Machine / parity section - tri_parity_recovery #(.THREADS(`THREADS)) fu_parity_recovery( + tri_parity_recovery fu_parity_recovery( .perr_si(perr_si), .perr_so(perr_so), .mpw1_b(mpw1_b), @@ -4170,14 +4170,14 @@ module fu_dcd( assign ex7_ram_expo[3:13] = f_rnd_ex7_res_expo[3:13]; generate - if (THREADS == 1) + if (`THREADS == 1) begin : dcd_ramactive_thr1_1 assign ex7_ram_active[0] = pc_fu_ram_active[0]; assign ex7_ram_active[1] = tilo; end endgenerate generate - if (THREADS == 2) + if (`THREADS == 2) begin : dcd_ramactive_thr2_1 assign ex7_ram_active[0] = pc_fu_ram_active[0]; assign ex7_ram_active[1] = pc_fu_ram_active[1]; diff --git a/dev/verilog/work/fu_fpr.v b/dev/verilog/work/fu_fpr.v index f25d0f3..ff3f46e 100755 --- a/dev/verilog/work/fu_fpr.v +++ b/dev/verilog/work/fu_fpr.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -162,7 +162,7 @@ module fu_fpr( ); parameter fpr_pool = 64; parameter fpr_pool_enc = 7; - parameter threads = 2; + //parameter threads = 2; parameter axu_spare_enc = 3; input [0:`NCLK_WIDTH-1] nclk; @@ -219,7 +219,7 @@ module fu_fpr( input iu_fu_rf0_str_v; // Interface to IU - input [0:threads-1] iu_fu_rf0_tid; // one hot + input [0:`THREADS-1] iu_fu_rf0_tid; // one hot input [0:5] f_dcd_rf0_fra; input [0:5] f_dcd_rf0_frb; input [0:5] f_dcd_rf0_frc; @@ -235,12 +235,12 @@ module fu_fpr( input f_rnd_ex7_res_sign; //---------------------------------------------- input xu_fu_ex5_load_val; - input [0:7+threads] xu_fu_ex5_load_tag; + input [0:7+`THREADS] xu_fu_ex5_load_tag; input [192:255] xu_fu_ex5_load_data; input lq_gpr_rel_we; input lq_gpr_rel_le; - input [0:7+threads] lq_gpr_rel_wa; + input [0:7+`THREADS] lq_gpr_rel_wa; input [64:127] lq_gpr_rel_wd; // :out std_ulogic_vector((128-STQ_DATA_SIZE) to 127); //---------------------------------------------- output [0:7] f_fpr_ex6_load_addr; @@ -606,14 +606,14 @@ module fu_fpr( // Load Data generate - if (threads == 1) + if (`THREADS == 1) begin : fpr_inj_perr_thr1_1 assign pc_fu_inj_regfile_parity_int[0:3] = {pc_fu_inj_regfile_parity[0], tidn, tidn, tidn}; end endgenerate generate - if (threads == 2) + if (`THREADS == 2) begin : fpr_inj_perr_thr2_2 assign pc_fu_inj_regfile_parity_int[0:3] = {pc_fu_inj_regfile_parity[0], pc_fu_inj_regfile_parity[1], tidn, tidn}; end @@ -645,14 +645,14 @@ module fu_fpr( assign ex5_load_v = ex5_load_val; generate - if (threads == 1) + if (`THREADS == 1) begin : dcd_loadtag_thr1_1 assign ex5_load_tag[0:9] = {xu_fu_ex5_load_tag[0:2], 1'b0, xu_fu_ex5_load_tag[3:8]}; end endgenerate generate - if (threads == 2) + if (`THREADS == 2) begin : dcd_loadtag_thr2_1 assign ex5_load_tag[0:9] = xu_fu_ex5_load_tag[0:9]; end @@ -662,14 +662,14 @@ module fu_fpr( assign ex5_reload_v = ex5_reload_val; generate - if (threads == 1) + if (`THREADS == 1) begin : dcd_reloadtag_thr1_1 assign ex5_reload_tag[0:9] = {lq_gpr_rel_wa[0:2], 1'b0, lq_gpr_rel_wa[3:8]}; end endgenerate generate - if (threads == 2) + if (`THREADS == 2) begin : dcd_reloadtag_thr2_1 assign ex5_reload_tag[0:9] = lq_gpr_rel_wa[0:9]; end @@ -1065,7 +1065,7 @@ module fu_fpr( // Target Data generate - if (threads == 1) + if (`THREADS == 1) begin : frt_addr_thr_1 assign frt_addr[1:7] = {1'b0, f_dcd_ex7_frt_addr[0:5]}; assign spare_unused[1] = f_dcd_ex7_frt_tid[1]; @@ -1073,7 +1073,7 @@ module fu_fpr( endgenerate generate - if (threads == 2) + if (`THREADS == 2) begin : frt_addr_thr_2 assign frt_addr[1:7] = {f_dcd_ex7_frt_addr[0:5], f_dcd_ex7_frt_tid[1]}; assign spare_unused[1] = tidn; @@ -1096,7 +1096,7 @@ module fu_fpr( // Source Address generate - if (threads == 1) + if (`THREADS == 1) begin : addr_gen_1 assign rf0_fra_addr[1:7] = {1'b0, f_dcd_rf0_fra[0:5]}; //uc_hook assign rf0_frb_addr[1:7] = {1'b0, f_dcd_rf0_frb[0:5]}; @@ -1105,7 +1105,7 @@ module fu_fpr( endgenerate generate - if (threads == 2) + if (`THREADS == 2) begin : addr_gen_2 assign rf0_fra_addr[1:7] = {f_dcd_rf0_fra[0:5], f_dcd_rf0_tid[1]}; //uc_hook assign rf0_frb_addr[1:7] = {f_dcd_rf0_frb[0:5], f_dcd_rf0_tid[1]}; @@ -1326,24 +1326,24 @@ module fu_fpr( .scan_out(scan_out_0), // Read Port FRA .r_late_en_1(r0e_en_func), - .r_addr_in_1(rf0_fra_addr[(3 - threads):7]), // rf0_fra_addr(1 to 7), + .r_addr_in_1(rf0_fra_addr[(3 - `THREADS):7]), // rf0_fra_addr(1 to 7), .r_data_out_1(fra_data_out), // Read Port FRC .r_late_en_2(r1e_en_func), - .r_addr_in_2(rf0_frc_addr[(3 - threads):7]), //rf0_frc_addr(1 to 7), + .r_addr_in_2(rf0_frc_addr[(3 - `THREADS):7]), //rf0_frc_addr(1 to 7), .r_data_out_2(frc_data_out), // Write Ports .w_late_en_1(w0e_en_func), - .w_addr_in_1(w0e_addr_func[(3 - threads):7]), //w0e_addr_func(1 to 7), + .w_addr_in_1(w0e_addr_func[(3 - `THREADS):7]), //w0e_addr_func(1 to 7), .w_data_in_1(w0e_data_func_f0), .w_late_en_2(w0l_en_func), - .w_addr_in_2(w0l_addr_func[(3 - threads):7]), //w0l_addr_func(1 to 7) + .w_addr_in_2(w0l_addr_func[(3 - `THREADS):7]), //w0l_addr_func(1 to 7) .w_data_in_2(w0l_data_func_f0), .w_late_en_3(reload_wen), - .w_addr_in_3(reload_addr[(3 - threads):7]), //reload_addr(1 to 7), + .w_addr_in_3(reload_addr[(3 - `THREADS):7]), //reload_addr(1 to 7), .w_data_in_3(rel_data_func_f0), .w_late_en_4(tilo), - .w_addr_in_4(zeros[(3 - threads):7]), + .w_addr_in_4(zeros[(3 - `THREADS):7]), .w_data_in_4(zeros[0:77]) ); @@ -1364,24 +1364,24 @@ module fu_fpr( .scan_out(scan_out_1), // Read Port FRB .r_late_en_1(r0e_en_func), - .r_addr_in_1(rf0_frb_addr[(3 - threads):7]), //rf0_frb_addr(1 to 7), + .r_addr_in_1(rf0_frb_addr[(3 - `THREADS):7]), //rf0_frb_addr(1 to 7), .r_data_out_1(frb_data_out), // Read Port FRS .r_late_en_2(r1e_en_func), - .r_addr_in_2(rf0_frs_addr[(3 - threads):7]), //rf0_frs_addr(1 to 7), + .r_addr_in_2(rf0_frs_addr[(3 - `THREADS):7]), //rf0_frs_addr(1 to 7), .r_data_out_2(frs_data_out), // Write Ports .w_late_en_1(w0e_en_func), - .w_addr_in_1(w0e_addr_func[(3 - threads):7]), //w0e_addr_func(1 to 7), + .w_addr_in_1(w0e_addr_func[(3 - `THREADS):7]), //w0e_addr_func(1 to 7), .w_data_in_1(w0e_data_func_f1), .w_late_en_2(w0l_en_func), - .w_addr_in_2(w0l_addr_func[(3 - threads):7]), //w0l_addr_func(1 to 7), + .w_addr_in_2(w0l_addr_func[(3 - `THREADS):7]), //w0l_addr_func(1 to 7), .w_data_in_2(w0l_data_func_f1), .w_late_en_3(reload_wen), - .w_addr_in_3(reload_addr[(3 - threads):7]), //reload_addr(1 to 7), + .w_addr_in_3(reload_addr[(3 - `THREADS):7]), //reload_addr(1 to 7), .w_data_in_3(rel_data_func_f1), .w_late_en_4(tilo), - .w_addr_in_4(zeros[(3 - threads):7]), + .w_addr_in_4(zeros[(3 - `THREADS):7]), .w_data_in_4(zeros[0:77]) ); diff --git a/dev/verilog/work/iuq_ibuf.v b/dev/verilog/work/iuq_ibuf.v index 0a8954f..b74bd09 100755 --- a/dev/verilog/work/iuq_ibuf.v +++ b/dev/verilog/work/iuq_ibuf.v @@ -708,7 +708,7 @@ assign iu4_1_isram_din = 1'b0; //-------------------------------------- -always @(iu4_stall or buffer_valid_flush or iu4_uc_mode_din or iu4_0_valid_din or iu4_0_instr_din or iu4_0_bta_din or iu4_0_ifar_din or iu4_0_ucode_din or iu4_0_ucode_ext_din or iu4_0_isram_din or iu4_0_fuse_val_din or iu4_0_fuse_data_din or iu4_1_valid_din or iu4_1_instr_din or iu4_1_bta_din or iu4_1_ifar_din or iu4_1_ucode_din or iu4_1_ucode_ext_din or iu4_1_isram_din or iu4_1_fuse_val_din or iu4_1_fuse_data_din or iu4_uc_mode_q or iu4_0_valid_q or iu4_0_instr_q or iu4_0_bta_q or iu4_0_ifar_q or iu4_0_ucode_q or iu4_0_ucode_ext_q or iu4_0_isram_q or iu4_0_fuse_val_q or iu4_0_fuse_data_q or iu4_1_valid_q or iu4_1_instr_q or iu4_1_bta_q or iu4_1_ifar_q or iu4_1_ucode_q or iu4_1_ucode_ext_q or iu4_1_isram_q or iu4_1_fuse_val_q or iu4_1_fuse_data_q) +always @* begin: iu4_proc iu4_uc_mode_d = iu4_uc_mode_din; diff --git a/dev/verilog/work/iuq_ic_ierat.v b/dev/verilog/work/iuq_ic_ierat.v index 919457f..a267c90 100755 --- a/dev/verilog/work/iuq_ic_ierat.v +++ b/dev/verilog/work/iuq_ic_ierat.v @@ -1967,7 +1967,7 @@ module iuq_ic_ierat( */ // power-on reset sequencer to load initial erat entries - always @(por_seq_q or init_alias or bcfg_q[0:106]) + always @* begin: Por_Sequencer por_wr_cam_val = 2'b0; por_wr_array_val = 2'b0; diff --git a/dev/verilog/work/iuq_idec.v b/dev/verilog/work/iuq_idec.v index 1514ef0..352c5e9 100755 --- a/dev/verilog/work/iuq_idec.v +++ b/dev/verilog/work/iuq_idec.v @@ -5421,7 +5421,7 @@ assign no_pre = assign iu5_bta_val_din = iu5_bta_val_woaxu; assign iu5_fusion_din = iu5_fusion_woaxu; - always @(iu5_vld_q or cp_flush_q or frn_fdec_iu5_stall or iu5_vld_din or iu5_ucode_din or iu5_2ucode_din or iu5_fuse_nop_din or iu5_error_din or iu5_btb_entry_din or iu5_btb_hist_din or iu5_bta_val_din or iu5_fusion_din or iu5_rte_lq_din or iu5_rte_sq_din or iu5_rte_fx0_din or iu5_rte_fx1_din or iu5_rte_axu0_din or iu5_rte_axu1_din or iu5_valop_din or iu5_ord_din or iu5_cord_din or iu5_spec_din or iu5_isram_din or iu5_isload_din or iu5_isstore_din or iu5_instr_din or iu5_ifar_din or iu5_bta_din or iu5_ilat_din or iu5_t1_v_din or iu5_t1_t_din or iu5_t1_a_din or iu5_t2_v_din or iu5_t2_a_din or iu5_t2_t_din or iu5_t3_v_din or iu5_t3_a_din or iu5_t3_t_din or iu5_s1_v_din or iu5_s1_a_din or iu5_s1_t_din or iu5_s2_v_din or iu5_s2_a_din or iu5_s2_t_din or iu5_s3_v_din or iu5_s3_a_din or iu5_s3_t_din or iu5_br_pred_din or iu5_bh_update_din or iu5_bh0_hist_din or iu5_bh1_hist_din or iu5_bh2_hist_din or iu5_gshare_din or iu5_ls_ptr_din or iu5_match_din or iu5_async_block_din or iu5_np1_flush_din or iu5_core_block_din or iu5_type_fp_din or iu5_type_ap_din or iu5_type_spv_din or iu5_type_st_din or iu5_ucode_q or iu5_2ucode_q or iu5_fuse_nop_q or iu5_error_q or iu5_btb_hist_q or iu5_btb_entry_q or iu5_bta_val_q or iu5_fusion_q or iu5_rte_lq_q or iu5_rte_sq_q or iu5_rte_fx0_q or iu5_rte_fx1_q or iu5_rte_axu0_q or iu5_rte_axu1_q or iu5_valop_q or iu5_ord_q or iu5_cord_q or iu5_spec_q or iu5_isram_q or iu5_isload_q or iu5_isstore_q or iu5_instr_q or iu5_ifar_q or iu5_bta_q or iu5_ilat_q or iu5_t1_v_q or iu5_t1_t_q or iu5_t1_a_q or iu5_t2_v_q or iu5_t2_a_q or iu5_t2_t_q or iu5_t3_v_q or iu5_t3_a_q or iu5_t3_t_q or iu5_s1_v_q or iu5_s1_a_q or iu5_s1_t_q or iu5_s2_v_q or iu5_s2_a_q or iu5_s2_t_q or iu5_s3_v_q or iu5_s3_a_q or iu5_s3_t_q or iu5_br_pred_q or iu5_bh_update_q or iu5_bh0_hist_q or iu5_bh1_hist_q or iu5_bh2_hist_q or iu5_gshare_q or iu5_ls_ptr_q or iu5_match_q or iu5_async_block_q or iu5_np1_flush_q or iu5_core_block_q or iu5_type_fp_q or iu5_type_ap_q or iu5_type_spv_q or iu5_type_st_q) + always @* begin: iu5_instr_proc iu5_vld_d = iu5_vld_din; diff --git a/dev/verilog/work/iuq_rn.v b/dev/verilog/work/iuq_rn.v index 59fdce7..e37e92b 100755 --- a/dev/verilog/work/iuq_rn.v +++ b/dev/verilog/work/iuq_rn.v @@ -2496,7 +2496,7 @@ module iuq_rn( assign frn_fdis_iu6_i1_t2_a_d = fdec_frn_iu5_i1_t2_a; - always @(fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t or fdec_frn_iu5_i1_t1_t or fdec_frn_iu5_i1_t1_a or next_gpr_0 or next_gpr_1 or next_cr_1 or next_cr_0 or au_iu_iu5_i0_t1_p or au_iu_iu5_i1_t1_p) + always @* begin: tar1_proc frn_fdis_iu6_i1_t1_p_d = fdec_frn_iu5_i1_t1_a; if (fdec_frn_iu5_i0_t1_v == 1'b1 & fdec_frn_iu5_i0_t1_t == `gpr_t & fdec_frn_iu5_i1_t1_t == `gpr_t) @@ -2515,7 +2515,7 @@ module iuq_rn( end - always @(fdec_frn_iu5_i0_t2_v or fdec_frn_iu5_i0_t2_t or fdec_frn_iu5_i1_t2_t or fdec_frn_iu5_i1_t2_a or next_ctr_1 or next_xer_1 or next_ctr_0 or next_xer_0 or au_iu_iu5_i0_t2_p or au_iu_iu5_i1_t2_p) + always @* begin: tar2_proc frn_fdis_iu6_i1_t2_p_d = fdec_frn_iu5_i1_t2_a; if (fdec_frn_iu5_i0_t2_v == 1'b1 & fdec_frn_iu5_i0_t2_t == `ctr_t & fdec_frn_iu5_i1_t2_t == `ctr_t) @@ -2538,7 +2538,7 @@ module iuq_rn( assign frn_fdis_iu6_i1_t3_a_d = fdec_frn_iu5_i1_t3_a; - always @(fdec_frn_iu5_i0_t3_v or fdec_frn_iu5_i0_t3_t or fdec_frn_iu5_i1_t3_t or fdec_frn_iu5_i1_t3_a or next_lr_1 or next_lr_0 or next_cr_1 or next_cr_0 or fdec_frn_iu5_i0_t1_v or fdec_frn_iu5_i0_t1_t) + always @* begin: tar3_proc frn_fdis_iu6_i1_t3_p_d = fdec_frn_iu5_i1_t3_a; if (fdec_frn_iu5_i0_t3_v == 1'b1 & fdec_frn_iu5_i0_t3_t == `lr_t & fdec_frn_iu5_i1_t3_t == `lr_t) diff --git a/dev/verilog/work/iuq_rn_map.v b/dev/verilog/work/iuq_rn_map.v index 4a1cf5e..30e067d 100755 --- a/dev/verilog/work/iuq_rn_map.v +++ b/dev/verilog/work/iuq_rn_map.v @@ -299,7 +299,7 @@ module iuq_rn_map #( for (i = 0; i <= ARCHITECTED_REGISTER_DEPTH - 1; i = i + 1) begin : map_set0 - always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_rename or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_rename or spec_map_arc_l2[i] or comp_map_l2[i]) + always @* begin: set_spec_map_arc_proc spec_map_arc_d[i] = spec_map_arc_l2[i]; if (flush_map == 1'b1) @@ -310,7 +310,7 @@ module iuq_rn_map #( spec_map_arc_d[i] = spec_0_wr_rename; end - always @(flush_map or spec_0_wr_val or spec_0_wr_arc or spec_0_wr_itag or spec_1_wr_val or spec_1_wr_arc or spec_1_wr_itag or spec_map_itag_l2[i] or comp_0_wr_val or comp_0_wr_itag or comp_1_wr_val or comp_1_wr_itag) + always @* begin: set_spec_map_itag_proc spec_map_itag_d[i] = spec_map_itag_l2[i]; if (flush_map == 1'b1) @@ -385,7 +385,7 @@ module iuq_rn_map #( assign free_cnt_act = flush_map | take_a | take_b | pool_free_0_v_l2 | pool_free_1_v_l2; - always @(flush_map or take_a or take_b or pool_free_0_v_l2 or pool_free_1_v_l2 or free_cnt_l2) + always @* begin: free_cnt_proc free_cnt_d = free_cnt_l2; diff --git a/dev/verilog/work/iuq_uc.v b/dev/verilog/work/iuq_uc.v index 0085457..08910fd 100755 --- a/dev/verilog/work/iuq_uc.v +++ b/dev/verilog/work/iuq_uc.v @@ -1535,7 +1535,7 @@ assign uc_legal = end endgenerate - always @(iu4_ov_valid_l2 or iu4_ifar_l2 or iu4_instr0_l2 or iu4_instr1_l2 or iu4_valid_l2 or iu4_ext0_l2 or iu4_ext1_l2 or iu4_done_l2 or iu4_ov_ifar_l2 or iu4_ov_instr0_l2 or iu4_ov_instr1_l2 or iu4_ov_ext0_l2 or iu4_ov_ext1_l2 or iu4_ov_done_l2) + always @* begin: ib_proc uc_ib_val = iu4_valid_l2; iu4_ifar_out = iu4_ifar_l2; diff --git a/dev/verilog/work/iuq_uc_cplbuffer.v b/dev/verilog/work/iuq_uc_cplbuffer.v index e70790b..5b13870 100755 --- a/dev/verilog/work/iuq_uc_cplbuffer.v +++ b/dev/verilog/work/iuq_uc_cplbuffer.v @@ -175,8 +175,7 @@ module iuq_uc_cplbuffer( for (i = 0; i < buffer_depth; i = i + 1) begin : buff_loop wire [0:buffer_depth_log-1] index=i; - always @ (write_ptr_l2 or index or buff_instr_in or buffer_l2[i] or - xer_write_ptr or xu_iu_ucode_xer_l2 or xer_l2[i]) + always @* begin buffer_d[i] = (write_ptr_l2 == index) ? buff_instr_in : buffer_l2[i]; diff --git a/dev/verilog/work/lq_derat.v b/dev/verilog/work/lq_derat.v index 61ba5e2..e6eebdb 100755 --- a/dev/verilog/work/lq_derat.v +++ b/dev/verilog/work/lq_derat.v @@ -3398,7 +3398,7 @@ module lq_derat( // power-on reset sequencer to load initial erat entries - always @(por_seq_q or init_alias or bcfg_q[0:106]) + always @* begin: Por_Sequencer por_wr_cam_val = {2{1'b0}}; por_wr_array_val = {2{1'b0}}; diff --git a/dev/verilog/work/lq_stq.v b/dev/verilog/work/lq_stq.v index b933791..f40c5b0 100755 --- a/dev/verilog/work/lq_stq.v +++ b/dev/verilog/work/lq_stq.v @@ -2366,7 +2366,7 @@ module lq_stq( assign ex5_qHit_set_oth_q[`STQ_ENTRIES] = 0; assign ex5_qHit_set_miss[`STQ_ENTRIES] = 0; - always @(stq_push_down) + always @* begin: dummy stq_cp_next_itag[`STQ_ENTRIES] = 0; set_stqe_odq_resolved[`STQ_ENTRIES] = 0; diff --git a/dev/verilog/work/mmq_htw.v b/dev/verilog/work/mmq_htw.v index 5c7f921..098ff3a 100755 --- a/dev/verilog/work/mmq_htw.v +++ b/dev/verilog/work/mmq_htw.v @@ -569,7 +569,7 @@ module mmq_htw( // HTW sequencer for servicing indirect tlb entry hits - always @(htw_seq_q or tlb_htw_req_valid_vec or tlb_htw_pte_machines_full or htw_lsu_req_taken) + always @* begin: Htw_Sequencer htw_seq_load_pteaddr = 1'b0; htw_lsu_req_valid = 1'b0; @@ -604,7 +604,7 @@ module mmq_htw( // PTE sequencer for servicing pte data reloads - always @(pte0_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte0_score_pending_q or pte0_score_dataval_q or pte0_score_error_q or pte0_score_qwbeat_q or pte0_score_ibit_q) + always @* begin: Pte0_Sequencer pte0_reload_req_valid = 1'b0; pte0_reload_req_taken = 1'b0; @@ -683,7 +683,7 @@ module mmq_htw( 1'b0; // PTE sequencer for servicing pte data reloads - always @(pte1_seq_q or pte_load_ptr_q or ptereload_ptr_q or htw_lsu_req_taken or ptereload_req_taken or pte1_score_pending_q or pte1_score_dataval_q or pte1_score_error_q or pte1_score_qwbeat_q or pte1_score_ibit_q) + always @* begin: Pte1_Sequencer pte1_reload_req_valid = 1'b0; pte1_reload_req_taken = 1'b0; diff --git a/dev/verilog/work/mmq_inval.v b/dev/verilog/work/mmq_inval.v index c9b9486..ae2f6c9 100755 --- a/dev/verilog/work/mmq_inval.v +++ b/dev/verilog/work/mmq_inval.v @@ -916,7 +916,7 @@ module mmq_inval( //Inv_Sequencer: PROCESS (inv_seq_q, por_seq_q, an_ac_back_inv, an_ac_back_inv_target, // ex6_valid_q, ex6_ttype_q) - always @(inv_seq_q or xu_mm_lmq_stq_empty or iu_mm_lmq_empty or hold_ack_q or lsu_tokens_q or xu_mm_ccr2_notlb_q[0] or snoop_ack_q or ex6_valid_q or ex6_ttype_q[0:3] or ex6_ind_q or ex6_isel_q or bus_snoop_seq_ready or mmucsr0_tlb0fi or tlbwe_back_inv_q[`MM_THREADS+1] or an_ac_back_inv_q[6] or an_ac_back_inv_addr_q[54:55] or htw_lsu_req_valid or lsu_req_q or cswitch_q[0:1] or cswitch_q[3] or power_managed_q[0] or power_managed_q[2] or power_managed_q[3]) + always @* begin: Inv_Sequencer inv_seq_idle = 1'b0; inv_seq_snoop_inprogress = 1'b0; @@ -1441,7 +1441,7 @@ module mmq_inval( hold_ack_q[1]; `endif - always @(bus_snoop_seq_q or inval_snoop_forme or bus_snoop_hold_ack_q or inv_seq_snoop_done or power_managed_q) + always @* begin: Bus_Snoop_Sequencer bus_snoop_seq_idle = 1'b0; bus_snoop_seq_hold_req = 1'b0; diff --git a/dev/verilog/work/mmq_tlb_ctl.v b/dev/verilog/work/mmq_tlb_ctl.v index 550ac75..6266522 100755 --- a/dev/verilog/work/mmq_tlb_ctl.v +++ b/dev/verilog/work/mmq_tlb_ctl.v @@ -1379,17 +1379,7 @@ module mmq_tlb_ctl( // TLB access sequencer for multiple page size compares for reloads - always @(tlb_seq_q or tlb_tag0_q[`tagpos_is + 1:`tagpos_is + 3] or tlb_tag0_q[`tagpos_size:`tagpos_size + 3] or - tlb_tag0_q[`tagpos_type:`tagpos_type + 7] or tlb_tag0_q[`tagpos_type:`tagpos_type + 7] or tlb_tag1_q[`tagpos_endflag] or - tlb_tag0_tid_notzero or tlb_tag0_q[`tagpos_nonspec] or tlb_tag4_hit_or_parerr or tlb_tag4_way_ind or tlb_addr_maxcntm1 or - tlb_cmp_erat_dup_wait or tlb_seq_ierat_req or tlb_seq_derat_req or tlb_search_req or tlb_searchresv_req or snoop_val_q[0] or - tlb_read_req or tlb_write_req or ptereload_req_valid or mmucr2[12:31] or derat_taken_q or - tlb_hashed_addr1 or tlb_hashed_addr2 or tlb_hashed_addr3 or tlb_hashed_addr4 or tlb_hashed_addr5 or - tlb_hashed_tid0_addr1 or tlb_hashed_tid0_addr2 or tlb_hashed_tid0_addr3 or tlb_hashed_tid0_addr4 or tlb_hashed_tid0_addr5 or - pgsize2_valid or pgsize3_valid or pgsize4_valid or pgsize5_valid or - pgsize2_tid0_valid or pgsize3_tid0_valid or pgsize4_tid0_valid or pgsize5_tid0_valid or - size_1M_hashed_addr or size_1M_hashed_tid0_addr or size_256M_hashed_addr or size_256M_hashed_tid0_addr or - tlb_tag0_hashed_addr or tlb_tag0_hashed_tid0_addr or tlb0cfg_ind or tlbwe_back_inv_holdoff) + always @* begin: Tlb_Sequencer tlb_seq_addr = {`TLB_ADDR_WIDTH{1'b0}}; tlb_seq_pgsize = mmucr2[28:31];