From 394137d82b2006cbcd911f2ff4bce514bad49909 Mon Sep 17 00:00:00 2001 From: Attack Orange Date: Sun, 11 May 2025 04:37:25 +0400 Subject: [PATCH] synthesis scripting fixes Fixed a commented out synthesis-breaking piece of logic related to 'define NCLK_WIDTH = 6, and changed synthesis script to the standard .ys extension --- dev/pd/synth/{synth.yo => synth.ys} | 0 dev/verilog/trilib/tri.vh | 2 +- 2 files changed, 1 insertion(+), 1 deletion(-) rename dev/pd/synth/{synth.yo => synth.ys} (100%) mode change 100755 => 100644 diff --git a/dev/pd/synth/synth.yo b/dev/pd/synth/synth.ys old mode 100755 new mode 100644 similarity index 100% rename from dev/pd/synth/synth.yo rename to dev/pd/synth/synth.ys diff --git a/dev/verilog/trilib/tri.vh b/dev/verilog/trilib/tri.vh index 9e79a06..1f9a47b 100755 --- a/dev/verilog/trilib/tri.vh +++ b/dev/verilog/trilib/tri.vh @@ -37,7 +37,7 @@ `define _tri_vh_ // separate clk, rst now -//`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk +`define NCLK_WIDTH 6 // 0 1xClk, 1 Reset, 2 2xClk, 3 4xClk, 4 Even .5xClk, 5 Odd .5x Clk `define EXPAND_TYPE 1 // Do NOT add any defines below this line