From 3b494a09a48a308f7766990cf61ffeb9533e6697 Mon Sep 17 00:00:00 2001 From: Bill Flynn <52765606+openpowerwtf@users.noreply.github.com> Date: Sun, 14 Aug 2022 19:01:57 -0500 Subject: [PATCH] Update readme.md --- dev/readme.md | 20 +++++++------------- 1 file changed, 7 insertions(+), 13 deletions(-) diff --git a/dev/readme.md b/dev/readme.md index a7bb6eb..551bc15 100755 --- a/dev/readme.md +++ b/dev/readme.md @@ -6,16 +6,17 @@ * updated source to remove a bunch of Verilator warnings * updated source for compatibility with Icaraus -g2012 - * changed the GPR/FPR macro to remove need for clk4x on FPGA; was ugly and not working with either simulator - + * changed arrays to use clk1x + * refactored nclk[] to separate clk, rst signals and removed lcb's from clock path + * Verilator - * can IFETCH some ops in ST and SMT2 mode - * can't get cocotb to build with Verilator (very long compile times) + * too big(?) to build with verilator --public with cocotb + * executing boot code and tst with a2o_litex wrapper * Icarus (w/cocotb) - * executing boot code until test call with python A2L2 interface + * executing boot code and tst with core/node/a2o_litex * Yosys @@ -24,18 +25,11 @@ ## Next To Do -* create A2L2 cpp model that can be used by Verilator and cocotb (Cython wrapper) - * eventually; don't need right now if can skip to RTL for A2L2 - -* create simple A2L2-WB RTL for easily connecting to Litex, etc. - * version 1 is pre-WB; uses RAM interface which could be sim driver or BRAM - -* create Litex core wrapper +* create Cython code for sharing between cocotb and verilator tb * OpenLane experiments with blackbox arrays and yosys/abc/sta * create FPGA version of GPR/FPR (4R4W) using (4)4R1W banks and *valid* table * parse vcd/fst and serve browser code for custom trace screens (handle spec/arch mapped facilities, arrays, etc.) - #### node * test BE/LE versions; kernel can stay BE until jump to BIOS; any problem with BIOS to initial ROM copy/zero or is it always words?