From 47428929652738f050ff429fce49613c002fad0b Mon Sep 17 00:00:00 2001 From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Tue, 9 Aug 2022 08:18:56 -0500 Subject: [PATCH] rewrite trilib --- dev/verilog/trilib/tri_aoi22_nlats_wlcb.v | 10 ++-- dev/verilog/trilib/tri_inv_nlats.v | 17 ++++--- dev/verilog/trilib/tri_nand2_nlats.v | 10 ++-- dev/verilog/trilib/tri_nlat.v | 17 ++++--- dev/verilog/trilib/tri_nlat_scan.v | 17 ++++--- dev/verilog/trilib/tri_regk.v | 53 ++++++-------------- dev/verilog/trilib/tri_regs.v | 59 +++++------------------ dev/verilog/trilib/tri_rlmlatch_p.v | 38 ++++----------- dev/verilog/trilib/tri_rlmreg_p.v | 59 +++++------------------ 9 files changed, 88 insertions(+), 192 deletions(-) mode change 100755 => 100644 dev/verilog/trilib/tri_regs.v diff --git a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v index 30b0cbf..45ee359 100755 --- a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v +++ b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v @@ -128,10 +128,12 @@ module tri_aoi22_nlats_wlcb( assign vthold_b = {WIDTH{thold_b}}; assign vthold = {WIDTH{~thold_b}}; - - always @(posedge nclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge nclk[0]) begin: l + //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + if (sreset) + int_dout <= int_din; + else if ((act | force_t) & thold_b) + int_dout <= int_din; end assign qb = (~int_dout); diff --git a/dev/verilog/trilib/tri_inv_nlats.v b/dev/verilog/trilib/tri_inv_nlats.v index d6381da..df5236e 100755 --- a/dev/verilog/trilib/tri_inv_nlats.v +++ b/dev/verilog/trilib/tri_inv_nlats.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -106,11 +106,14 @@ module tri_inv_nlats( assign vthold_b = {WIDTH{d2clk}}; assign vthold = {WIDTH{~d2clk}}; - - always @(posedge lclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge lclk[0]) begin: l + //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + if (sreset) + int_dout <= int_din; + else if (d1clk & d2clk) + int_dout <= int_din; end + assign qb = (~int_dout); assign scanout = ZEROS; diff --git a/dev/verilog/trilib/tri_nand2_nlats.v b/dev/verilog/trilib/tri_nand2_nlats.v index 7ba70a4..ef304c1 100755 --- a/dev/verilog/trilib/tri_nand2_nlats.v +++ b/dev/verilog/trilib/tri_nand2_nlats.v @@ -106,10 +106,14 @@ module tri_nand2_nlats( assign vthold_b = {WIDTH{d2clk}}; assign vthold = {WIDTH{~d2clk}}; - always @(posedge lclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge lclk[0]) begin: l + //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + if (sreset) + int_dout <= int_din; + else if (d1clk & d2clk) + int_dout <= int_din; end + assign qb = (~int_dout); assign scanout = ZEROS; diff --git a/dev/verilog/trilib/tri_nlat.v b/dev/verilog/trilib/tri_nlat.v index b6440ae..0f6492f 100755 --- a/dev/verilog/trilib/tri_nlat.v +++ b/dev/verilog/trilib/tri_nlat.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -107,11 +107,14 @@ module tri_nlat( assign vthold_b = {WIDTH{d2clk}}; assign vthold = {WIDTH{~d2clk}}; - - always @(posedge lclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge lclk[0]) begin: l + //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + if (sreset) + int_dout <= int_din; + else if (d1clk & d2clk) + int_dout <= int_din; end + assign q = int_dout; assign q_b = (~int_dout); assign scan_out = 1'b0; diff --git a/dev/verilog/trilib/tri_nlat_scan.v b/dev/verilog/trilib/tri_nlat_scan.v index a8f6cc2..669c64d 100755 --- a/dev/verilog/trilib/tri_nlat_scan.v +++ b/dev/verilog/trilib/tri_nlat_scan.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -106,11 +106,14 @@ module tri_nlat_scan( assign vthold_b = {WIDTH{d2clk}}; assign vthold = {WIDTH{~d2clk}}; - - always @(posedge lclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge lclk[0]) begin: l + //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + if (sreset) + int_dout <= int_din; + else if (d1clk & d2clk) + int_dout <= int_din; end + assign q = int_dout; assign q_b = (~int_dout); assign scan_out = ZEROS; diff --git a/dev/verilog/trilib/tri_regk.v b/dev/verilog/trilib/tri_regk.v index b776b29..851feec 100755 --- a/dev/verilog/trilib/tri_regk.v +++ b/dev/verilog/trilib/tri_regk.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -77,53 +77,28 @@ module tri_regk( output [OFFSET:OFFSET+WIDTH-1] dout; parameter [0:WIDTH-1] init_v = INIT; - parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; - - // tri_regk generate - begin + wire sreset; - wire [0:WIDTH-1] int_din; reg [0:WIDTH-1] int_dout; - wire [0:WIDTH-1] vact; - wire [0:WIDTH-1] vact_b; - wire [0:WIDTH-1] vsreset; - wire [0:WIDTH-1] vsreset_b; - wire [0:WIDTH-1] vthold; - wire [0:WIDTH-1] vthold_b; (* analysis_not_referenced="true" *) wire unused; - if (NEEDS_SRESET == 1) - begin : rst - assign sreset = nclk[1]; - end - if (NEEDS_SRESET != 1) - begin : no_rst - assign sreset = 1'b0; - end - - assign vsreset = {WIDTH{sreset}}; - assign vsreset_b = {WIDTH{~sreset}}; - assign int_din = (vsreset_b & din) | (vsreset & init_v); + assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; - assign vact = {WIDTH{act | force_t}}; - assign vact_b = {WIDTH{~(act | force_t)}}; - - assign vthold_b = {WIDTH{thold_b}}; - assign vthold = {WIDTH{~thold_b}}; - - - always @(posedge nclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge nclk[0]) begin: l + if (sreset) + int_dout <= init_v; + else if (act & thold_b) + int_dout <= din; end + assign dout = int_dout; - assign scout = ZEROS; + assign scout = {WIDTH{1'b0}}; - assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin}; - end + assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); endgenerate + endmodule diff --git a/dev/verilog/trilib/tri_regs.v b/dev/verilog/trilib/tri_regs.v old mode 100755 new mode 100644 index 03286fa..5e9eac2 --- a/dev/verilog/trilib/tri_regs.v +++ b/dev/verilog/trilib/tri_regs.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -66,63 +66,26 @@ module tri_regs( output [OFFSET:OFFSET+WIDTH-1] dout; parameter [0:WIDTH-1] init_v = INIT; - parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; - - // tri_regs generate - begin wire sreset; - wire [0:WIDTH-1] int_din; reg [0:WIDTH-1] int_dout; - wire [0:WIDTH-1] vact; - wire [0:WIDTH-1] vact_b; - wire [0:WIDTH-1] vsreset; - wire [0:WIDTH-1] vsreset_b; - wire [0:WIDTH-1] vthold; - wire [0:WIDTH-1] vthold_b; (* analysis_not_referenced="true" *) wire unused; - if (NEEDS_SRESET == 1) - begin : rst - assign sreset = nclk[1]; - end - if (NEEDS_SRESET != 1) - begin : no_rst - assign sreset = 1'b0; - end - - assign vsreset = {WIDTH{sreset}}; - assign vsreset_b = {WIDTH{~sreset}}; - - assign int_din = (vsreset_b & int_dout) | (vsreset & init_v); + assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; - assign vact = {WIDTH{force_t}}; - assign vact_b = {WIDTH{~force_t}}; - - assign vthold_b = {WIDTH{thold_b}}; - assign vthold = {WIDTH{~thold_b}}; - - - always @(posedge nclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge nclk[0]) begin: l + if (sreset) + int_dout <= init_v; end - if (IBUF == 1'b1) - begin : cob - assign dout = (~int_dout); - end + assign dout = (IBUF == 1'b1) ? ~int_dout : int_dout; - if (IBUF == 1'b0) - begin : cnob - assign dout = int_dout; - end + assign scout = {WIDTH{1'b0}}; - assign scout = ZEROS; + assign unused = |{vd, gd, delay_lclkr, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); - assign unused = | {vd, gd, nclk, delay_lclkr, scin}; - end endgenerate + endmodule diff --git a/dev/verilog/trilib/tri_rlmlatch_p.v b/dev/verilog/trilib/tri_rlmlatch_p.v index edd8274..ff3acd6 100755 --- a/dev/verilog/trilib/tri_rlmlatch_p.v +++ b/dev/verilog/trilib/tri_rlmlatch_p.v @@ -71,42 +71,22 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl (* analysis_not_referenced="true" *) wire unused; - if (NEEDS_SRESET == 1) - begin : rst - assign sreset = nclk[1]; - end - if (NEEDS_SRESET != 1) - begin : no_rst - assign sreset = 1'b0; - end + assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; - if (IBUF == 1'b1) - begin : cib - assign int_din = ((~sreset) & (~din)) | (sreset & init_v[0]); - end - if (IBUF == 1'b0) - begin : cnib - assign int_din = ((~sreset) & din) | (sreset & init_v[0]); - end + assign int_din = IBUF ? ~din : din; - always @(posedge nclk[0]) - begin: l - int_dout <= ((((act | force_t) & thold_b) | sreset) & int_din) | ((((~act) & (~force_t)) | (~thold_b)) & (~sreset) & int_dout); + always @(posedge nclk[0]) begin: l + if (sreset) // reset value + int_dout <= init_v[0]; + else if ((act | force_t) & thold_b) // activate or force, and not clk off + int_dout <= int_din; end - if (IBUF == 1'b1) - begin : cob - assign dout = (~int_dout); - end - - if (IBUF == 1'b0) - begin : cnob - assign dout = int_dout; - end + assign dout = IBUF ? ~int_dout : int_dout; assign scout = 1'b0; - assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk); + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); endgenerate endmodule diff --git a/dev/verilog/trilib/tri_rlmreg_p.v b/dev/verilog/trilib/tri_rlmreg_p.v index c38e5e7..def1426 100755 --- a/dev/verilog/trilib/tri_rlmreg_p.v +++ b/dev/verilog/trilib/tri_rlmreg_p.v @@ -67,68 +67,31 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr /* verilator lint_off WIDTH */ parameter [0:WIDTH-1] init_v = INIT; //wtf causes width mismatch warnings; would have to handle both greater and less than 32 bit cases /* verilator lint_on WIDTH */ - parameter [0:WIDTH-1] ZEROS = {WIDTH{1'b0}}; - - // tri_rlmreg_p generate wire sreset; wire [0:WIDTH-1] int_din; reg [0:WIDTH-1] int_dout; - wire [0:WIDTH-1] vact; - wire [0:WIDTH-1] vact_b; - wire [0:WIDTH-1] vsreset; - wire [0:WIDTH-1] vsreset_b; - wire [0:WIDTH-1] vthold; - wire [0:WIDTH-1] vthold_b; + (* analysis_not_referenced="true" *) wire [0:WIDTH] unused; - if (NEEDS_SRESET == 1) - begin : rst - assign sreset = nclk[1]; - end - if (NEEDS_SRESET != 1) - begin : no_rst - assign sreset = 1'b0; - end - - assign vsreset = {WIDTH{sreset}}; - assign vsreset_b = {WIDTH{~sreset}}; - - if (IBUF == 1'b1) - begin : cib - assign int_din = (vsreset_b & (~din)) | (vsreset & init_v); - end - if (IBUF == 1'b0) - begin : cnib - assign int_din = (vsreset_b & din) | (vsreset & init_v); - end - - assign vact = {WIDTH{act | force_t | ALWAYS_ACT == 1}}; - assign vact_b = {WIDTH{~(act | force_t | ALWAYS_ACT == 1)}}; + assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; - assign vthold_b = {WIDTH{thold_b}}; - assign vthold = {WIDTH{~thold_b}}; + assign int_din = sreset ? init_v : (IBUF == 1'b1) ? ~din : din; //wtf why is sreset needed here??? sim fails w/o it. - always @(posedge nclk[0]) - begin: l - int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); + always @(posedge nclk[0]) begin: l + if (sreset) // reset value + int_dout <= init_v; + else if ((act | force_t) & thold_b) // activate or force, and not clk off + int_dout <= int_din; end - if (IBUF == 1'b1) - begin : cob - assign dout = (~int_dout); - end - - if (IBUF == 1'b0) - begin : cnob - assign dout = int_dout; - end + assign dout = (IBUF == 1'b1) ? ~int_dout : int_dout; - assign scout = ZEROS; + assign scout = {WIDTH{1'b0}}; - assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk); + assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); assign unused[1:WIDTH] = scin; endgenerate