From 7f1b3e23d6d18652c0c37afe5d3ac9f5472311fb Mon Sep 17 00:00:00 2001
From: Bill Flynn <52765606+openpowerwtf@users.noreply.github.com>
Date: Sun, 14 Aug 2022 13:31:20 -0500
Subject: [PATCH] Update README.md

---
 README.md | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/README.md b/README.md
index e0fe272..6668185 100644
--- a/README.md
+++ b/README.md
@@ -7,8 +7,8 @@
    * compiles with verilator, iverilog, yosys
    * runs simple version of kernel/bios/random test with cocotb (A2L2 interface partially implemented in Python) and Verilog core wrapper (A2L2<->mem interface)
    * wrapper converts A2L2 interface to mem and Wishbone interfaces
-   * verilator builds, but does not simulate correctly
-
+   * verilator now runs with a2o_litex
+   
 ## To Do
 
    * continue with cocotb testing