From 7043a1645b5d753b0f2c0e8dd3f22fef0d3e0eed Mon Sep 17 00:00:00 2001 From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Thu, 28 Jul 2022 09:14:20 -0500 Subject: [PATCH] inits to disable cg --- dev/verilog/clkgating/mmq_spr.v | 5949 +++++++++++++++++++++++++++ dev/verilog/clkgating/tri_a2o.vh | 196 + dev/verilog/clkgating/xu_spr_cspr.v | 4970 ++++++++++++++++++++++ 3 files changed, 11115 insertions(+) create mode 100755 dev/verilog/clkgating/mmq_spr.v create mode 100755 dev/verilog/clkgating/tri_a2o.vh create mode 100755 dev/verilog/clkgating/xu_spr_cspr.v diff --git a/dev/verilog/clkgating/mmq_spr.v b/dev/verilog/clkgating/mmq_spr.v new file mode 100755 index 0000000..954a526 --- /dev/null +++ b/dev/verilog/clkgating/mmq_spr.v @@ -0,0 +1,5949 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +//******************************************************************** +//* TITLE: Memory Management Unit Special Purpose Registers +//********************************************************************* + +`timescale 1 ns / 1 ns + +`include "tri_a2o.vh" +`include "mmu_a2o.vh" + +module mmq_spr( + + inout vdd, + inout gnd, + (* pin_data ="PIN_FUNCTION=/G_CLK/" *) + input [0:`NCLK_WIDTH-1] nclk, + + input [0:`THREADS-1] cp_flush, + output [0:`MM_THREADS-1] cp_flush_p1, + + input tc_ccflush_dc, + input tc_scan_dis_dc_b, + input tc_scan_diag_dc, + input tc_lbist_en_dc, + + input lcb_d_mode_dc, + input lcb_clkoff_dc_b, + input lcb_act_dis_dc, + input [0:4] lcb_mpw1_dc_b, + input lcb_mpw2_dc_b, + input [0:4] lcb_delay_lclkr_dc, + +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input [0:1] ac_func_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output [0:1] ac_func_scan_out, +(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) + input ac_bcfg_scan_in, +(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) + output ac_bcfg_scan_out, + + input pc_sg_2, + input pc_func_sl_thold_2, + input pc_func_slp_sl_thold_2, + input pc_func_slp_nsl_thold_2, + input pc_cfg_sl_thold_2, + input pc_cfg_slp_sl_thold_2, + input pc_fce_2, + input xu_mm_ccr2_notlb_b, + input [5:6] mmucr2_act_override, + input [29:29+`MM_THREADS-1] tlb_delayed_act, + +`ifdef WAIT_UPDATES + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + input [0:5] cp_mm_except_taken_t0, +`ifdef MM_THREADS2 + input [0:5] cp_mm_except_taken_t1, +`endif + output [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q, + // 0:1 - thdid/val + // 2 - I=0/D=1 + // 3 - TLB miss + // 4 - Storage int (TLBI/PTfault) + // 5 - LRAT miss + // 6 - Mcheck +`endif + + + output [0:`PID_WIDTH-1] mm_iu_ierat_pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_iu_ierat_pid1, +`endif + output [0:19] mm_iu_ierat_mmucr0_0, +`ifdef MM_THREADS2 + output [0:19] mm_iu_ierat_mmucr0_1, +`endif + input [0:17] iu_mm_ierat_mmucr0, + input [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we, + output [0:8] mm_iu_ierat_mmucr1, + input [0:3] iu_mm_ierat_mmucr1, + input [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we, + + output [0:`PID_WIDTH-1] mm_xu_derat_pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] mm_xu_derat_pid1, +`endif + output [0:19] mm_xu_derat_mmucr0_0, +`ifdef MM_THREADS2 + output [0:19] mm_xu_derat_mmucr0_1, +`endif + input [0:17] xu_mm_derat_mmucr0, + input [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we, + output [0:9] mm_xu_derat_mmucr1, + input [0:4] xu_mm_derat_mmucr1, + input [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we, + + output [0:`PID_WIDTH-1] pid0, +`ifdef MM_THREADS2 + output [0:`PID_WIDTH-1] pid1, +`endif + output [0:`MMUCR0_WIDTH-1] mmucr0_0, +`ifdef MM_THREADS2 + output [0:`MMUCR0_WIDTH-1] mmucr0_1, +`endif + output [0:`MMUCR1_WIDTH-1] mmucr1, + output [0:`MMUCR2_WIDTH-1] mmucr2, + output [64-`MMUCR3_WIDTH:63] mmucr3_0, + output [1:3] tstmode4k_0, +`ifdef MM_THREADS2 + output [64-`MMUCR3_WIDTH:63] mmucr3_1, + output [1:3] tstmode4k_1, +`endif + + output mmucfg_lrat, + output mmucfg_twc, + output tlb0cfg_pt, + output tlb0cfg_ind, + output tlb0cfg_gtwe, + output [0:`MESR1_WIDTH+`MESR2_WIDTH-1] mmq_spr_event_mux_ctrls, + + output mas0_0_atsel, + output [0:2] mas0_0_esel, + output mas0_0_hes, + output [0:1] mas0_0_wq, + output mas1_0_v, + output mas1_0_iprot, + output [0:13] mas1_0_tid, + output mas1_0_ind, + output mas1_0_ts, + output [0:3] mas1_0_tsize, + output [0:51] mas2_0_epn, + output [0:4] mas2_0_wimge, + output [32:52] mas3_0_rpnl, + output [0:3] mas3_0_ubits, + output [0:5] mas3_0_usxwr, + output mas5_0_sgs, + output [0:7] mas5_0_slpid, + output [0:13] mas6_0_spid, + output [0:3] mas6_0_isize, + output mas6_0_sind, + output mas6_0_sas, + output [22:31] mas7_0_rpnu, + output mas8_0_tgs, + output mas8_0_vf, + output [0:7] mas8_0_tlpid, +`ifdef MM_THREADS2 + output mas0_1_atsel, + output [0:2] mas0_1_esel, + output mas0_1_hes, + output [0:1] mas0_1_wq, + output mas1_1_v, + output mas1_1_iprot, + output [0:13] mas1_1_tid, + output mas1_1_ind, + output mas1_1_ts, + output [0:3] mas1_1_tsize, + output [0:51] mas2_1_epn, + output [0:4] mas2_1_wimge, + output [32:52] mas3_1_rpnl, + output [0:3] mas3_1_ubits, + output [0:5] mas3_1_usxwr, + output mas5_1_sgs, + output [0:7] mas5_1_slpid, + output [0:13] mas6_1_spid, + output [0:3] mas6_1_isize, + output mas6_1_sind, + output mas6_1_sas, + output [22:31] mas7_1_rpnu, + output mas8_1_tgs, + output mas8_1_vf, + output [0:7] mas8_1_tlpid, +`endif + input [0:2] tlb_mas0_esel, + input tlb_mas1_v, + input tlb_mas1_iprot, + input [0:`PID_WIDTH-1] tlb_mas1_tid, + input [0:`PID_WIDTH-1] tlb_mas1_tid_error, + input tlb_mas1_ind, + input tlb_mas1_ts, + input tlb_mas1_ts_error, + input [0:3] tlb_mas1_tsize, + input [0:`EPN_WIDTH-1] tlb_mas2_epn, + input [0:`EPN_WIDTH-1] tlb_mas2_epn_error, + input [0:4] tlb_mas2_wimge, + input [32:51] tlb_mas3_rpnl, + input [0:3] tlb_mas3_ubits, + input [0:5] tlb_mas3_usxwr, + input [22:31] tlb_mas7_rpnu, + input tlb_mas8_tgs, + input tlb_mas8_vf, + input [0:7] tlb_mas8_tlpid, + + input [0:8] tlb_mmucr1_een, + input tlb_mmucr1_we, + input [0:`THDID_WIDTH-1] tlb_mmucr3_thdid, + input tlb_mmucr3_resvattr, + input [0:1] tlb_mmucr3_wlc, + input [0:`CLASS_WIDTH-1] tlb_mmucr3_class, + input [0:`EXTCLASS_WIDTH-1] tlb_mmucr3_extclass, + input [0:1] tlb_mmucr3_rc, + input tlb_mmucr3_x, + input tlb_mas_tlbre, + input tlb_mas_tlbsx_hit, + input tlb_mas_tlbsx_miss, + input tlb_mas_dtlb_error, + input tlb_mas_itlb_error, + input [0:`MM_THREADS-1] tlb_mas_thdid, + + output mmucsr0_tlb0fi, + input mmq_inval_tlb0fi_done, + + input lrat_mmucr3_x, + input [0:2] lrat_mas0_esel, + input lrat_mas1_v, + input [0:3] lrat_mas1_tsize, + input [0:51] lrat_mas2_epn, + input [32:51] lrat_mas3_rpnl, + input [22:31] lrat_mas7_rpnu, + input [0:`LPID_WIDTH-1] lrat_mas8_tlpid, + input lrat_mas_tlbre, + input lrat_mas_tlbsx_hit, + input lrat_mas_tlbsx_miss, + input [0:`MM_THREADS-1] lrat_mas_thdid, + input [0:2] lrat_tag4_hit_entry, + + input [64-`REAL_ADDR_WIDTH:51] tlb_lper_lpn, + input [60:63] tlb_lper_lps, + input [0:`MM_THREADS-1] tlb_lper_we, + + output [0:`LPID_WIDTH-1] lpidr, + output [0:`LPID_WIDTH-1] ac_an_lpar_id, + + output spr_dbg_match_64b, + output spr_dbg_match_any_mmu, + output spr_dbg_match_any_mas, + output spr_dbg_match_pid, + output spr_dbg_match_lpidr, + output spr_dbg_match_mmucr0, + output spr_dbg_match_mmucr1, + output spr_dbg_match_mmucr2, + output spr_dbg_match_mmucr3, + + output spr_dbg_match_mmucsr0, + output spr_dbg_match_mmucfg, + output spr_dbg_match_tlb0cfg, + output spr_dbg_match_tlb0ps, + output spr_dbg_match_lratcfg, + output spr_dbg_match_lratps, + output spr_dbg_match_eptcfg, + output spr_dbg_match_lper, + output spr_dbg_match_lperu, + + output spr_dbg_match_mas0, + output spr_dbg_match_mas1, + output spr_dbg_match_mas2, + output spr_dbg_match_mas2u, + output spr_dbg_match_mas3, + output spr_dbg_match_mas4, + output spr_dbg_match_mas5, + output spr_dbg_match_mas6, + output spr_dbg_match_mas7, + output spr_dbg_match_mas8, + output spr_dbg_match_mas01_64b, + output spr_dbg_match_mas56_64b, + output spr_dbg_match_mas73_64b, + output spr_dbg_match_mas81_64b, + + output spr_dbg_slowspr_val_int, + output spr_dbg_slowspr_rw_int, + output [0:1] spr_dbg_slowspr_etid_int, + output [0:9] spr_dbg_slowspr_addr_int, + output spr_dbg_slowspr_val_out, + output spr_dbg_slowspr_done_out, + output [64-`SPR_DATA_WIDTH:63] spr_dbg_slowspr_data_out, + + input xu_mm_slowspr_val, + input xu_mm_slowspr_rw, + input [0:1] xu_mm_slowspr_etid, + input [0:9] xu_mm_slowspr_addr, + input [64-`SPR_DATA_WIDTH:63] xu_mm_slowspr_data, + input xu_mm_slowspr_done, + + output mm_iu_slowspr_val, + output mm_iu_slowspr_rw, + output [0:1] mm_iu_slowspr_etid, + output [0:9] mm_iu_slowspr_addr, + output [64-`SPR_DATA_WIDTH:63] mm_iu_slowspr_data, + + output mm_iu_slowspr_done + +); + + parameter BCFG_MMUCR1_VALUE = 201326592; // mmucr1 32-bits boot value, 201326592 -> bits 4:5 csinv="11" + parameter BCFG_MMUCR2_VALUE = `INIT_MMUCR2; //685361; // mmucr2 32-bits boot value, 0xa7531 + parameter BCFG_MMUCR3_VALUE = 15; // mmucr2 15-bits boot value, 0x000f + parameter BCFG_MMUCFG_VALUE = 3; // mmucfg lrat|twc bits boot value + parameter BCFG_TLB0CFG_VALUE = 7; // tlb0cfg pt|ind|gtwe bits boot value + parameter MMQ_SPR_CSWITCH_0TO3 = 8; // chicken switch values: 8=disable mmucr1 read clear, 4=disable mmucr1.tlbwe_binv + + + parameter [0:9] Spr_Addr_PID = 10'b0000110000; + //constant Spr_Addr_LPID : std_ulogic_vector(0 to 9) := 1001111110 ; -- dec 638 + parameter [0:9] Spr_Addr_LPID = 10'b0101010010; + parameter [0:9] Spr_Addr_MMUCR0 = 10'b1111111100; + parameter [0:9] Spr_Addr_MMUCR1 = 10'b1111111101; + parameter [0:9] Spr_Addr_MMUCR2 = 10'b1111111110; + parameter [0:9] Spr_Addr_MMUCR3 = 10'b1111111111; + parameter Spr_RW_Write = 1'b0; + parameter Spr_RW_Read = 1'b1; + parameter [0:9] Spr_Addr_MESR1 = 10'b1110010100; + parameter [0:9] Spr_Addr_MESR2 = 10'b1110010101; + parameter [0:9] Spr_Addr_MAS0 = 10'b1001110000; + parameter [0:9] Spr_Addr_MAS1 = 10'b1001110001; + parameter [0:9] Spr_Addr_MAS2 = 10'b1001110010; + parameter [0:9] Spr_Addr_MAS2U = 10'b1001110111; + parameter [0:9] Spr_Addr_MAS3 = 10'b1001110011; + parameter [0:9] Spr_Addr_MAS4 = 10'b1001110100; + parameter [0:9] Spr_Addr_MAS5 = 10'b0101010011; + parameter [0:9] Spr_Addr_MAS6 = 10'b1001110110; + parameter [0:9] Spr_Addr_MAS7 = 10'b1110110000; + parameter [0:9] Spr_Addr_MAS8 = 10'b0101010101; + parameter [0:9] Spr_Addr_MAS56_64b = 10'b0101011100; + parameter [0:9] Spr_Addr_MAS81_64b = 10'b0101011101; + parameter [0:9] Spr_Addr_MAS73_64b = 10'b0101110100; + parameter [0:9] Spr_Addr_MAS01_64b = 10'b0101110101; + parameter [0:9] Spr_Addr_MMUCFG = 10'b1111110111; + parameter [0:9] Spr_Addr_MMUCSR0 = 10'b1111110100; + parameter [0:9] Spr_Addr_TLB0CFG = 10'b1010110000; + parameter [0:9] Spr_Addr_TLB0PS = 10'b0101011000; + parameter [0:9] Spr_Addr_LRATCFG = 10'b0101010110; + parameter [0:9] Spr_Addr_LRATPS = 10'b0101010111; + parameter [0:9] Spr_Addr_EPTCFG = 10'b0101011110; + parameter [0:9] Spr_Addr_LPER = 10'b0000111000; + parameter [0:9] Spr_Addr_LPERU = 10'b0000111001; + // MMUCFG: 32:35 resv, 36:39 LPIDSIZE=0x8, 40:46 RASIZE=0x2a, 47 LRAT bcfg, 48 TWC bcfg, + // 49:52 resv, 53:57 PIDSIZE=0xd, 58:59 resv, 60:61 NTLBS=0b00, 62:63 MAVN=0b01 + parameter [32:63] Spr_Data_MMUCFG = 32'b00001000010101011000001101000001; + // TLB0CFG: 32:39 ASSOC=0x04, 40:44 resv, 45 PT bcfg, 46 IND bcfg, 47 GTWE bcfg, + // 48 IPROT=1, 49 resv, 50 HES=1, 51 resv, 52:63 NENTRY=0x200 + parameter [32:63] Spr_Data_TLB0CFG = 32'b00000100000000001010001000000000; + // TLB0PS: 32:63 PS31-PS0=0x0010_4444 (PS20, PS14, PS10, PS6, PS2 = 1, others = 0) + parameter [32:63] Spr_Data_TLB0PS = 32'b00000000000100000100010001000100; + // LRATCFG: 32:39 ASSOC=0x00, 40:46 LASIZE=0x2a, 47:49 resv, 50 LPID=1, 51 resv, 52:63 NENTRY=0x008 + parameter [32:63] Spr_Data_LRATCFG = 32'b00000000010101000010000000001000; + // LRATPS: 32:63 PS31-PS0=0x5154_4400 (PS30, PS28, PS24, PS22, PS20, PS18, PS14, PS10 = 1, others = 0) + parameter [32:63] Spr_Data_LRATPS = 32'b01010001010101000100010000000000; + // EPTCFG: 32:43 resv, 44:48 PS1=0x12, 49:53 SPS1=0x06, 54:58 PS0=0x0a, 59:63 SPS0=0x02 + parameter [32:63] Spr_Data_EPTCFG = 32'b00000000000010010001100101000010; + + parameter [0:15] TSTMODE4KCONST1 = 16'b0101101001101001; // 0x5A69 + parameter [0:11] TSTMODE4KCONST2 = 12'b110000111011; // 0xC3B + + // latches scan chain constants + parameter cp_flush_offset = 0; + parameter cp_flush_p1_offset = cp_flush_offset + `MM_THREADS; + parameter spr_ctl_in_offset = cp_flush_p1_offset + `MM_THREADS; + parameter spr_etid_in_offset = spr_ctl_in_offset + `SPR_CTL_WIDTH; + parameter spr_addr_in_offset = spr_etid_in_offset + `SPR_ETID_WIDTH; + parameter spr_data_in_offset = spr_addr_in_offset + `SPR_ADDR_WIDTH; + parameter spr_ctl_int_offset = spr_data_in_offset + `SPR_DATA_WIDTH; + parameter spr_etid_int_offset = spr_ctl_int_offset + `SPR_CTL_WIDTH; + parameter spr_addr_int_offset = spr_etid_int_offset + `SPR_ETID_WIDTH; + parameter spr_data_int_offset = spr_addr_int_offset + `SPR_ADDR_WIDTH; + parameter spr_ctl_out_offset = spr_data_int_offset + `SPR_DATA_WIDTH; + parameter spr_etid_out_offset = spr_ctl_out_offset + `SPR_CTL_WIDTH; + parameter spr_addr_out_offset = spr_etid_out_offset + `SPR_ETID_WIDTH; + parameter spr_data_out_offset = spr_addr_out_offset + `SPR_ADDR_WIDTH; + parameter spr_match_any_mmu_offset = spr_data_out_offset + `SPR_DATA_WIDTH; + parameter spr_match_pid0_offset = spr_match_any_mmu_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_pid1_offset = spr_match_pid0_offset + 1; + parameter spr_match_mmucr0_0_offset = spr_match_pid1_offset + 1; + parameter spr_match_mmucr0_1_offset = spr_match_mmucr0_0_offset + 1; + parameter spr_match_mmucr1_offset = spr_match_mmucr0_1_offset + 1; +`else + parameter spr_match_mmucr0_0_offset = spr_match_pid0_offset + 1; + parameter spr_match_mmucr1_offset = spr_match_mmucr0_0_offset + 1; +`endif + parameter spr_match_mmucr2_offset = spr_match_mmucr1_offset + 1; + parameter spr_match_mmucr3_0_offset = spr_match_mmucr2_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_mmucr3_1_offset = spr_match_mmucr3_0_offset + 1; + parameter spr_match_lpidr_offset = spr_match_mmucr3_1_offset + 1; +`else + parameter spr_match_lpidr_offset = spr_match_mmucr3_0_offset + 1; +`endif + parameter spr_match_mesr1_offset = spr_match_lpidr_offset + 1; + parameter spr_match_mesr2_offset = spr_match_mesr1_offset + 1; + parameter pid0_offset = spr_match_mesr2_offset + 1; +`ifdef MM_THREADS2 + parameter pid1_offset = pid0_offset + `PID_WIDTH; + parameter mmucr0_0_offset = pid1_offset + `PID_WIDTH; +`else + parameter mmucr0_0_offset = pid0_offset + `PID_WIDTH; +`endif +`ifdef MM_THREADS2 + parameter mmucr0_1_offset = mmucr0_0_offset + `MMUCR0_WIDTH; + parameter lpidr_offset = mmucr0_1_offset + `MMUCR0_WIDTH; +`else + parameter lpidr_offset = mmucr0_0_offset + `MMUCR0_WIDTH; +`endif + parameter mesr1_offset = lpidr_offset + `LPID_WIDTH; + parameter mesr2_offset = mesr1_offset + `MESR1_WIDTH; + parameter spare_a_offset = mesr2_offset + `MESR2_WIDTH; + parameter spr_mmu_act_offset = spare_a_offset + 32; + parameter spr_val_act_offset = spr_mmu_act_offset + `MM_THREADS + 1; +`ifdef WAIT_UPDATES + parameter cp_mm_except_taken_t0_offset = spr_val_act_offset + 4; + parameter tlb_mas_dtlb_error_pending_offset = cp_mm_except_taken_t0_offset + 6; + parameter tlb_mas_itlb_error_pending_offset = tlb_mas_dtlb_error_pending_offset + `MM_THREADS; + parameter tlb_lper_we_pending_offset = tlb_mas_itlb_error_pending_offset + `MM_THREADS; + parameter tlb_mmucr1_we_pending_offset = tlb_lper_we_pending_offset + `MM_THREADS; + parameter ierat_mmucr1_we_pending_offset = tlb_mmucr1_we_pending_offset + `MM_THREADS; + parameter derat_mmucr1_we_pending_offset = ierat_mmucr1_we_pending_offset + `MM_THREADS; + parameter tlb_mas1_0_ts_error_offset = derat_mmucr1_we_pending_offset + `MM_THREADS; + parameter tlb_mas1_0_tid_error_offset = tlb_mas1_0_ts_error_offset + 1; + parameter tlb_mas2_0_epn_error_offset = tlb_mas1_0_tid_error_offset + `PID_WIDTH; + parameter tlb_lper_0_lpn_offset = tlb_mas2_0_epn_error_offset + `EPN_WIDTH; + parameter tlb_lper_0_lps_offset = tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12; + parameter tlb_mmucr1_0_een_offset = tlb_lper_0_lps_offset + 4; + parameter ierat_mmucr1_0_een_offset = tlb_mmucr1_0_een_offset + 9; + parameter derat_mmucr1_0_een_offset = ierat_mmucr1_0_een_offset + 4; +`ifdef MM_THREADS2 + parameter cp_mm_except_taken_t1_offset = derat_mmucr1_0_een_offset + 5; + parameter tlb_mas1_1_ts_error_offset = cp_mm_except_taken_t1_offset + 6; + parameter tlb_mas1_1_tid_error_offset = tlb_mas1_1_ts_error_offset + 1; + parameter tlb_mas2_1_epn_error_offset = tlb_mas1_1_tid_error_offset + `PID_WIDTH; + parameter tlb_lper_1_lpn_offset = tlb_mas2_1_epn_error_offset + `EPN_WIDTH; + parameter tlb_lper_1_lps_offset = tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12; + parameter tlb_mmucr1_1_een_offset = tlb_lper_1_lps_offset + 4; + parameter ierat_mmucr1_1_een_offset = tlb_mmucr1_1_een_offset + 9; + parameter derat_mmucr1_1_een_offset = ierat_mmucr1_1_een_offset + 4; + parameter cswitch_offset = derat_mmucr1_1_een_offset + 5; +`else + parameter cswitch_offset = derat_mmucr1_0_een_offset + 5; +`endif +`else + parameter cswitch_offset = spr_val_act_offset + 4; +`endif + parameter scan_right_0 = cswitch_offset + 4 - 1; + + + // MAS register constants + parameter spr_match_mmucsr0_offset = 0; + parameter spr_match_mmucfg_offset = spr_match_mmucsr0_offset + 1; + parameter spr_match_tlb0cfg_offset = spr_match_mmucfg_offset + 1; + parameter spr_match_tlb0ps_offset = spr_match_tlb0cfg_offset + 1; + parameter spr_match_lratcfg_offset = spr_match_tlb0ps_offset + 1; + parameter spr_match_lratps_offset = spr_match_lratcfg_offset + 1; + parameter spr_match_eptcfg_offset = spr_match_lratps_offset + 1; + parameter spr_match_lper_0_offset = spr_match_eptcfg_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_lper_1_offset = spr_match_lper_0_offset + 1; + parameter spr_match_lperu_0_offset = spr_match_lper_1_offset + 1; + parameter spr_match_lperu_1_offset = spr_match_lperu_0_offset + 1; + parameter spr_match_mas0_0_offset = spr_match_lperu_1_offset + 1; +`else + parameter spr_match_lperu_0_offset = spr_match_lper_0_offset + 1; + parameter spr_match_mas0_0_offset = spr_match_lperu_0_offset + 1; +`endif + parameter spr_match_mas1_0_offset = spr_match_mas0_0_offset + 1; + parameter spr_match_mas2_0_offset = spr_match_mas1_0_offset + 1; + parameter spr_match_mas2u_0_offset = spr_match_mas2_0_offset + 1; + parameter spr_match_mas3_0_offset = spr_match_mas2u_0_offset + 1; + parameter spr_match_mas4_0_offset = spr_match_mas3_0_offset + 1; + parameter spr_match_mas5_0_offset = spr_match_mas4_0_offset + 1; + parameter spr_match_mas6_0_offset = spr_match_mas5_0_offset + 1; + parameter spr_match_mas7_0_offset = spr_match_mas6_0_offset + 1; + parameter spr_match_mas8_0_offset = spr_match_mas7_0_offset + 1; + parameter spr_match_mas01_64b_0_offset = spr_match_mas8_0_offset + 1; + parameter spr_match_mas56_64b_0_offset = spr_match_mas01_64b_0_offset + 1; + parameter spr_match_mas73_64b_0_offset = spr_match_mas56_64b_0_offset + 1; + parameter spr_match_mas81_64b_0_offset = spr_match_mas73_64b_0_offset + 1; +`ifdef MM_THREADS2 + parameter spr_match_mas0_1_offset = spr_match_mas81_64b_0_offset + 1; + parameter spr_match_mas1_1_offset = spr_match_mas0_1_offset + 1; + parameter spr_match_mas2_1_offset = spr_match_mas1_1_offset + 1; + parameter spr_match_mas2u_1_offset = spr_match_mas2_1_offset + 1; + parameter spr_match_mas3_1_offset = spr_match_mas2u_1_offset + 1; + parameter spr_match_mas4_1_offset = spr_match_mas3_1_offset + 1; + parameter spr_match_mas5_1_offset = spr_match_mas4_1_offset + 1; + parameter spr_match_mas6_1_offset = spr_match_mas5_1_offset + 1; + parameter spr_match_mas7_1_offset = spr_match_mas6_1_offset + 1; + parameter spr_match_mas8_1_offset = spr_match_mas7_1_offset + 1; + parameter spr_match_mas01_64b_1_offset = spr_match_mas8_1_offset + 1; + parameter spr_match_mas56_64b_1_offset = spr_match_mas01_64b_1_offset + 1; + parameter spr_match_mas73_64b_1_offset = spr_match_mas56_64b_1_offset + 1; + parameter spr_match_mas81_64b_1_offset = spr_match_mas73_64b_1_offset + 1; + parameter spr_match_64b_offset = spr_match_mas81_64b_1_offset + 1; +`else + parameter spr_match_64b_offset = spr_match_mas81_64b_0_offset + 1; +`endif + parameter spr_addr_in_clone_offset = spr_match_64b_offset + 1; + parameter spr_mas_data_out_offset = spr_addr_in_clone_offset + `SPR_ADDR_WIDTH; + parameter spr_match_any_mas_offset = spr_mas_data_out_offset + `SPR_DATA_WIDTH; + parameter mas0_0_atsel_offset = spr_match_any_mas_offset + 1; + parameter mas0_0_esel_offset = mas0_0_atsel_offset + 1; + parameter mas0_0_hes_offset = mas0_0_esel_offset + 3; + parameter mas0_0_wq_offset = mas0_0_hes_offset + 1; + parameter mas1_0_v_offset = mas0_0_wq_offset + 2; + parameter mas1_0_iprot_offset = mas1_0_v_offset + 1; + parameter mas1_0_tid_offset = mas1_0_iprot_offset + 1; + parameter mas1_0_ind_offset = mas1_0_tid_offset + `PID_WIDTH; + parameter mas1_0_ts_offset = mas1_0_ind_offset + 1; + parameter mas1_0_tsize_offset = mas1_0_ts_offset + 1; + parameter mas2_0_epn_offset = mas1_0_tsize_offset + 4; + parameter mas2_0_wimge_offset = mas2_0_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; + parameter mas3_0_rpnl_offset = mas2_0_wimge_offset + 5; + parameter mas3_0_ubits_offset = mas3_0_rpnl_offset + 21; + parameter mas3_0_usxwr_offset = mas3_0_ubits_offset + 4; + parameter mas5_0_sgs_offset = mas3_0_usxwr_offset + 6; + parameter mas5_0_slpid_offset = mas5_0_sgs_offset + 1; + parameter mas6_0_spid_offset = mas5_0_slpid_offset + 8; + parameter mas6_0_isize_offset = mas6_0_spid_offset + 14; + parameter mas6_0_sind_offset = mas6_0_isize_offset + 4; + parameter mas6_0_sas_offset = mas6_0_sind_offset + 1; + parameter mas7_0_rpnu_offset = mas6_0_sas_offset + 1; + parameter mas8_0_tgs_offset = mas7_0_rpnu_offset + 10; + parameter mas8_0_vf_offset = mas8_0_tgs_offset + 1; + parameter mas8_0_tlpid_offset = mas8_0_vf_offset + 1; +`ifdef MM_THREADS2 + parameter mas0_1_atsel_offset = mas8_0_tlpid_offset + `LPID_WIDTH; + parameter mas0_1_esel_offset = mas0_1_atsel_offset + 1; + parameter mas0_1_hes_offset = mas0_1_esel_offset + 3; + parameter mas0_1_wq_offset = mas0_1_hes_offset + 1; + parameter mas1_1_v_offset = mas0_1_wq_offset + 2; + parameter mas1_1_iprot_offset = mas1_1_v_offset + 1; + parameter mas1_1_tid_offset = mas1_1_iprot_offset + 1; + parameter mas1_1_ind_offset = mas1_1_tid_offset + `PID_WIDTH; + parameter mas1_1_ts_offset = mas1_1_ind_offset + 1; + parameter mas1_1_tsize_offset = mas1_1_ts_offset + 1; + parameter mas2_1_epn_offset = mas1_1_tsize_offset + 4; + parameter mas2_1_wimge_offset = mas2_1_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; + parameter mas3_1_rpnl_offset = mas2_1_wimge_offset + 5; + parameter mas3_1_ubits_offset = mas3_1_rpnl_offset + 21; + parameter mas3_1_usxwr_offset = mas3_1_ubits_offset + 4; + parameter mas5_1_sgs_offset = mas3_1_usxwr_offset + 6; + parameter mas5_1_slpid_offset = mas5_1_sgs_offset + 1; + parameter mas6_1_spid_offset = mas5_1_slpid_offset + 8; + parameter mas6_1_isize_offset = mas6_1_spid_offset + 14; + parameter mas6_1_sind_offset = mas6_1_isize_offset + 4; + parameter mas6_1_sas_offset = mas6_1_sind_offset + 1; + parameter mas7_1_rpnu_offset = mas6_1_sas_offset + 1; + parameter mas8_1_tgs_offset = mas7_1_rpnu_offset + 10; + parameter mas8_1_vf_offset = mas8_1_tgs_offset + 1; + parameter mas8_1_tlpid_offset = mas8_1_vf_offset + 1; + parameter mmucsr0_tlb0fi_offset = mas8_1_tlpid_offset + `LPID_WIDTH; +`else + parameter mmucsr0_tlb0fi_offset = mas8_0_tlpid_offset + `LPID_WIDTH; +`endif + parameter lper_0_alpn_offset = mmucsr0_tlb0fi_offset + 1; + parameter lper_0_lps_offset = lper_0_alpn_offset + `REAL_ADDR_WIDTH - 12; +`ifdef MM_THREADS2 + parameter lper_1_alpn_offset = lper_0_lps_offset + 4; + parameter lper_1_lps_offset = lper_1_alpn_offset + `REAL_ADDR_WIDTH - 12; + parameter spare_b_offset = lper_1_lps_offset + 4; +`else + parameter spare_b_offset = lper_0_lps_offset + 4; +`endif + parameter cat_emf_act_offset = spare_b_offset + 64; + parameter scan_right_1 = cat_emf_act_offset + `MM_THREADS - 1; + + // boot config scan bits + parameter mmucfg_offset = 0; + parameter tlb0cfg_offset = mmucfg_offset + 2; + parameter mmucr1_offset = tlb0cfg_offset + 3; + parameter mmucr2_offset = mmucr1_offset + `MMUCR1_WIDTH; +`ifdef MM_THREADS2 + parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; + parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; + parameter mmucr3_1_offset = tstmode4k_0_offset + 4; + parameter tstmode4k_1_offset = mmucr3_1_offset + `MMUCR3_WIDTH; + parameter mas4_0_indd_offset = tstmode4k_1_offset + 4; + parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; + parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; + parameter mas4_1_indd_offset = mas4_0_wimged_offset + 5; + parameter mas4_1_tsized_offset = mas4_1_indd_offset + 1; + parameter mas4_1_wimged_offset = mas4_1_tsized_offset + 4; + parameter bcfg_spare_offset = mas4_1_wimged_offset + 5; + parameter boot_scan_right = bcfg_spare_offset + 16 - 1; +`else + parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; + parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; + parameter mas4_0_indd_offset = tstmode4k_0_offset + 4; + parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; + parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; + parameter bcfg_spare_offset = mas4_0_wimged_offset + 5; + parameter boot_scan_right = bcfg_spare_offset + 16 - 1; +`endif + +`ifdef MM_THREADS2 + parameter BUGSP_MM_THREADS = 2; +`else + parameter BUGSP_MM_THREADS = 1; +`endif + + wire spr_match_any_mmu; + wire spr_match_any_mmu_q; + wire spr_match_pid0; + wire spr_match_pid0_q; + wire spr_match_mmucr0_0; + wire spr_match_mmucr0_0_q; + wire spr_match_mmucr3_0; + wire spr_match_mmucr3_0_q; +`ifdef MM_THREADS2 + wire spr_match_pid1; + wire spr_match_pid1_q; + wire spr_match_mmucr0_1; + wire spr_match_mmucr0_1_q; + wire spr_match_mmucr3_1; + wire spr_match_mmucr3_1_q; +`endif + wire spr_match_mmucr1; + wire spr_match_mmucr1_q; + wire spr_match_mmucr2; + wire spr_match_mmucr2_q; + wire spr_match_lpidr; + wire spr_match_lpidr_q; + wire spr_match_mesr1; + wire spr_match_mesr1_q; + wire spr_match_mesr2; + wire spr_match_mesr2_q; + wire spr_match_mmucsr0; + wire spr_match_mmucsr0_q; + wire spr_match_mmucfg; + wire spr_match_mmucfg_q; + wire spr_match_tlb0cfg; + wire spr_match_tlb0cfg_q; + wire spr_match_tlb0ps; + wire spr_match_tlb0ps_q; + wire spr_match_lratcfg; + wire spr_match_lratcfg_q; + wire spr_match_lratps; + wire spr_match_lratps_q; + wire spr_match_eptcfg; + wire spr_match_eptcfg_q; + wire spr_match_lper_0; + wire spr_match_lper_0_q; + wire spr_match_lperu_0; + wire spr_match_lperu_0_q; +`ifdef MM_THREADS2 + wire spr_match_lper_1; + wire spr_match_lper_1_q; + wire spr_match_lperu_1; + wire spr_match_lperu_1_q; +`endif + wire spr_match_mas0_0; + wire spr_match_mas0_0_q; + wire spr_match_mas1_0; + wire spr_match_mas1_0_q; + wire spr_match_mas2_0; + wire spr_match_mas2_0_q; + wire spr_match_mas2u_0; + wire spr_match_mas2u_0_q; + wire spr_match_mas3_0; + wire spr_match_mas3_0_q; + wire spr_match_mas4_0; + wire spr_match_mas4_0_q; + wire spr_match_mas5_0; + wire spr_match_mas5_0_q; + wire spr_match_mas6_0; + wire spr_match_mas6_0_q; + wire spr_match_mas7_0; + wire spr_match_mas7_0_q; + wire spr_match_mas8_0; + wire spr_match_mas8_0_q; + wire spr_match_mas01_64b_0; + wire spr_match_mas01_64b_0_q; + wire spr_match_mas56_64b_0; + wire spr_match_mas56_64b_0_q; + wire spr_match_mas73_64b_0; + wire spr_match_mas73_64b_0_q; + wire spr_match_mas81_64b_0; + wire spr_match_mas81_64b_0_q; +`ifdef MM_THREADS2 + wire spr_match_mas0_1; + wire spr_match_mas0_1_q; + wire spr_match_mas1_1; + wire spr_match_mas1_1_q; + wire spr_match_mas2_1; + wire spr_match_mas2_1_q; + wire spr_match_mas2u_1; + wire spr_match_mas2u_1_q; + wire spr_match_mas3_1; + wire spr_match_mas3_1_q; + wire spr_match_mas4_1; + wire spr_match_mas4_1_q; + wire spr_match_mas5_1; + wire spr_match_mas5_1_q; + wire spr_match_mas6_1; + wire spr_match_mas6_1_q; + wire spr_match_mas7_1; + wire spr_match_mas7_1_q; + wire spr_match_mas8_1; + wire spr_match_mas8_1_q; + wire spr_match_mas01_64b_1; + wire spr_match_mas01_64b_1_q; + wire spr_match_mas56_64b_1; + wire spr_match_mas56_64b_1_q; + wire spr_match_mas73_64b_1; + wire spr_match_mas73_64b_1_q; + wire spr_match_mas81_64b_1; + wire spr_match_mas81_64b_1_q; +`endif + wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out; + wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out_q; + wire spr_match_any_mas; + wire spr_match_any_mas_q; + wire spr_match_mas2_64b; + wire spr_match_mas01_64b; + wire spr_match_mas56_64b; + wire spr_match_mas73_64b; + wire spr_match_mas81_64b; + wire spr_match_64b; + wire spr_match_64b_q; + // added input latches for timing with adding numerous mas regs + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_in_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_in_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_q; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_int_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_int_q; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_d; + wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_q; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_d; + wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_q; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_d; + wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_q; + wire [64-`SPR_DATA_WIDTH:63] spr_data_out_d; + wire [64-`SPR_DATA_WIDTH:63] spr_data_out_q; + wire [0:3] spr_etid_onehot; + wire [0:3] spr_etid_in_onehot; + wire [0:3] spr_etid_int_onehot; + wire [0:3] spr_etid_flushed; + wire [0:3] spr_etid_in_flushed; + wire [0:3] spr_etid_int_flushed; + wire spr_val_flushed; + wire spr_val_in_flushed; + wire spr_val_int_flushed; + wire [0:`PID_WIDTH-1] pid0_d; + wire [0:`PID_WIDTH-1] pid0_q; + wire [0:`MMUCR0_WIDTH-1] mmucr0_0_d; + wire [0:`MMUCR0_WIDTH-1] mmucr0_0_q; + wire [64-`MMUCR3_WIDTH:63] mmucr3_0_d; + wire [64-`MMUCR3_WIDTH:63] mmucr3_0_q; + wire [0:3] tstmode4k_0_d, tstmode4k_0_q; +`ifdef MM_THREADS2 + wire [0:`PID_WIDTH-1] pid1_d; + wire [0:`PID_WIDTH-1] pid1_q; + wire [0:`MMUCR0_WIDTH-1] mmucr0_1_d; + wire [0:`MMUCR0_WIDTH-1] mmucr0_1_q; + wire [64-`MMUCR3_WIDTH:63] mmucr3_1_d; + wire [64-`MMUCR3_WIDTH:63] mmucr3_1_q; + wire [0:3] tstmode4k_1_d, tstmode4k_1_q; +`endif + wire [0:`MMUCR1_WIDTH-1] mmucr1_d; + wire [0:`MMUCR1_WIDTH-1] mmucr1_q; + wire [0:`MMUCR2_WIDTH-1] mmucr2_d; + wire [0:`MMUCR2_WIDTH-1] mmucr2_q; + wire [0:`LPID_WIDTH-1] lpidr_d; + wire [0:`LPID_WIDTH-1] lpidr_q; + wire [32:32+`MESR1_WIDTH-1] mesr1_d; + wire [32:32+`MESR1_WIDTH-1] mesr1_q; + wire [32:32+`MESR2_WIDTH-1] mesr2_d; + wire [32:32+`MESR2_WIDTH-1] mesr2_q; + wire mas0_0_atsel_d; + wire mas0_0_atsel_q; + wire [0:2] mas0_0_esel_d; + wire [0:2] mas0_0_esel_q; + wire mas0_0_hes_d; + wire mas0_0_hes_q; + wire [0:1] mas0_0_wq_d; + wire [0:1] mas0_0_wq_q; + wire mas1_0_v_d; + wire mas1_0_v_q; + wire mas1_0_iprot_d; + wire mas1_0_iprot_q; + wire [0:`PID_WIDTH-1] mas1_0_tid_d; + wire [0:`PID_WIDTH-1] mas1_0_tid_q; + wire mas1_0_ind_d; + wire mas1_0_ind_q; + wire mas1_0_ts_d; + wire mas1_0_ts_q; + wire [0:3] mas1_0_tsize_d; + wire [0:3] mas1_0_tsize_q; + wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_d; + wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_q; + wire [0:4] mas2_0_wimge_d; + wire [0:4] mas2_0_wimge_q; + wire [32:52] mas3_0_rpnl_d; + wire [32:52] mas3_0_rpnl_q; + wire [0:3] mas3_0_ubits_d; + wire [0:3] mas3_0_ubits_q; + wire [0:5] mas3_0_usxwr_d; + wire [0:5] mas3_0_usxwr_q; + wire mas4_0_indd_d; + wire mas4_0_indd_q; + wire [0:3] mas4_0_tsized_d; + wire [0:3] mas4_0_tsized_q; + wire [0:4] mas4_0_wimged_d; + wire [0:4] mas4_0_wimged_q; + wire mas5_0_sgs_d; + wire mas5_0_sgs_q; + wire [0:7] mas5_0_slpid_d; + wire [0:7] mas5_0_slpid_q; + wire [0:13] mas6_0_spid_d; + wire [0:13] mas6_0_spid_q; + wire [0:3] mas6_0_isize_d; + wire [0:3] mas6_0_isize_q; + wire mas6_0_sind_d; + wire mas6_0_sind_q; + wire mas6_0_sas_d; + wire mas6_0_sas_q; + wire [22:31] mas7_0_rpnu_d; + wire [22:31] mas7_0_rpnu_q; + wire mas8_0_tgs_d; + wire mas8_0_tgs_q; + wire mas8_0_vf_d; + wire mas8_0_vf_q; + wire [0:7] mas8_0_tlpid_d; + wire [0:7] mas8_0_tlpid_q; +`ifdef MM_THREADS2 + wire mas0_1_atsel_d; + wire mas0_1_atsel_q; + wire [0:2] mas0_1_esel_d; + wire [0:2] mas0_1_esel_q; + wire mas0_1_hes_d; + wire mas0_1_hes_q; + wire [0:1] mas0_1_wq_d; + wire [0:1] mas0_1_wq_q; + wire mas1_1_v_d; + wire mas1_1_v_q; + wire mas1_1_iprot_d; + wire mas1_1_iprot_q; + wire [0:`PID_WIDTH-1] mas1_1_tid_d; + wire [0:`PID_WIDTH-1] mas1_1_tid_q; + wire mas1_1_ind_d; + wire mas1_1_ind_q; + wire mas1_1_ts_d; + wire mas1_1_ts_q; + wire [0:3] mas1_1_tsize_d; + wire [0:3] mas1_1_tsize_q; + wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_d; + wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_q; + wire [0:4] mas2_1_wimge_d; + wire [0:4] mas2_1_wimge_q; + wire [32:52] mas3_1_rpnl_d; + wire [32:52] mas3_1_rpnl_q; + wire [0:3] mas3_1_ubits_d; + wire [0:3] mas3_1_ubits_q; + wire [0:5] mas3_1_usxwr_d; + wire [0:5] mas3_1_usxwr_q; + wire mas4_1_indd_d; + wire mas4_1_indd_q; + wire [0:3] mas4_1_tsized_d; + wire [0:3] mas4_1_tsized_q; + wire [0:4] mas4_1_wimged_d; + wire [0:4] mas4_1_wimged_q; + wire mas5_1_sgs_d; + wire mas5_1_sgs_q; + wire [0:7] mas5_1_slpid_d; + wire [0:7] mas5_1_slpid_q; + wire [0:13] mas6_1_spid_d; + wire [0:13] mas6_1_spid_q; + wire [0:3] mas6_1_isize_d; + wire [0:3] mas6_1_isize_q; + wire mas6_1_sind_d; + wire mas6_1_sind_q; + wire mas6_1_sas_d; + wire mas6_1_sas_q; + wire [22:31] mas7_1_rpnu_d; + wire [22:31] mas7_1_rpnu_q; + wire mas8_1_tgs_d; + wire mas8_1_tgs_q; + wire mas8_1_vf_d; + wire mas8_1_vf_q; + wire [0:7] mas8_1_tlpid_d; + wire [0:7] mas8_1_tlpid_q; +`endif + + wire mmucsr0_tlb0fi_d; + wire mmucsr0_tlb0fi_q; + wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_q; + wire [60:63] lper_0_lps_d; + wire [60:63] lper_0_lps_q; +`ifdef MM_THREADS2 + wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_d; + wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_q; + wire [60:63] lper_1_lps_d; + wire [60:63] lper_1_lps_q; +`endif + // timing nsl's + wire [0:17] iu_mm_ierat_mmucr0_q; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we_q; + wire [0:17] xu_mm_derat_mmucr0_q; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we_q; + wire [0:3] iu_mm_ierat_mmucr1_q; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_d, iu_mm_ierat_mmucr1_we_q; + wire [0:4] xu_mm_derat_mmucr1_q; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_d, xu_mm_derat_mmucr1_we_q; + + wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_upd; + wire [0:`MM_THREADS-1] tlb_mas_itlb_error_upd; + wire [0:`MM_THREADS-1] tlb_lper_we_upd; + wire [0:`MM_THREADS-1] tlb_mmucr1_we_upd; + wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_upd; + wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_upd; + wire tlb_mas1_0_ts_error_upd; + wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_upd; + wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_upd; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_upd; + wire [60:63] tlb_lper_0_lps_upd; + wire [0:8] tlb_mmucr1_0_een_upd; + wire [0:3] ierat_mmucr1_0_een_upd; + wire [0:4] derat_mmucr1_0_een_upd; +`ifdef MM_THREADS2 + wire tlb_mas1_1_ts_error_upd; + wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_upd; + wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_upd; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_upd; + wire [60:63] tlb_lper_1_lps_upd; + wire [0:8] tlb_mmucr1_1_een_upd; + wire [0:3] ierat_mmucr1_1_een_upd; + wire [0:4] derat_mmucr1_1_een_upd; +`endif + +`ifdef WAIT_UPDATES + wire [0:5] cp_mm_except_taken_t0_d, cp_mm_except_taken_t0_q; + wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_pending_d, tlb_mas_dtlb_error_pending_q; + wire [0:`MM_THREADS-1] tlb_mas_itlb_error_pending_d, tlb_mas_itlb_error_pending_q; + wire [0:`MM_THREADS-1] tlb_lper_we_pending_d, tlb_lper_we_pending_q; + wire [0:`MM_THREADS-1] tlb_mmucr1_we_pending_d, tlb_mmucr1_we_pending_q; + wire [0:`MM_THREADS-1] ierat_mmucr1_we_pending_d, ierat_mmucr1_we_pending_q; + wire [0:`MM_THREADS-1] derat_mmucr1_we_pending_d, derat_mmucr1_we_pending_q; + + wire tlb_mas1_0_ts_error_d, tlb_mas1_0_ts_error_q; + wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_d, tlb_mas1_0_tid_error_q; + wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_d, tlb_mas2_0_epn_error_q; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_d, tlb_lper_0_lpn_q; + wire [60:63] tlb_lper_0_lps_d, tlb_lper_0_lps_q; + wire [0:8] tlb_mmucr1_0_een_d, tlb_mmucr1_0_een_q; + wire [0:3] ierat_mmucr1_0_een_d, ierat_mmucr1_0_een_q; + wire [0:4] derat_mmucr1_0_een_d, derat_mmucr1_0_een_q; +`ifdef MM_THREADS2 + wire [0:5] cp_mm_except_taken_t1_d, cp_mm_except_taken_t1_q; + wire tlb_mas1_1_ts_error_d, tlb_mas1_1_ts_error_q; + wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_d, tlb_mas1_1_tid_error_q; + wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_d, tlb_mas2_1_epn_error_q; + wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_d, tlb_lper_1_lpn_q; + wire [60:63] tlb_lper_1_lps_d, tlb_lper_1_lps_q; + wire [0:8] tlb_mmucr1_1_een_d, tlb_mmucr1_1_een_q; + wire [0:3] ierat_mmucr1_1_een_d, ierat_mmucr1_1_een_q; + wire [0:4] derat_mmucr1_1_een_d, derat_mmucr1_1_een_q; +`endif +`endif + + wire [0:31] spare_a_q; + wire [0:63] spare_b_q; + + (* analysis_not_referenced="true" *) + wire [0:13] unused_dc; + (* analysis_not_referenced="true" *) + wire [`THREADS:3] unused_dc_threads; + wire [0:45+(4*`MM_THREADS)-1] tri_regk_unused_scan; + + // Pervasive + wire pc_sg_1; + wire pc_sg_0; + wire pc_fce_1; + wire pc_fce_0; + wire pc_func_sl_thold_1; + wire pc_func_sl_thold_0; + wire pc_func_sl_thold_0_b; + wire pc_func_slp_sl_thold_1; + wire pc_func_slp_sl_thold_0; + wire pc_func_slp_sl_thold_0_b; + wire pc_func_sl_force; + wire pc_func_slp_sl_force; + wire pc_cfg_sl_thold_1; + wire pc_cfg_sl_thold_0; + wire pc_cfg_slp_sl_force; + wire pc_cfg_slp_sl_thold_1; + wire pc_cfg_slp_sl_thold_0; + wire pc_cfg_slp_sl_thold_0_b; + wire pc_func_slp_nsl_thold_1; + wire pc_func_slp_nsl_thold_0; + wire pc_func_slp_nsl_thold_0_b; + wire pc_func_slp_nsl_force; + + //signal reset_alias : std_ulogic; + wire [0:scan_right_0] siv_0; + wire [0:scan_right_0] sov_0; + wire [0:scan_right_1] siv_1; + wire [0:scan_right_1] sov_1; + wire [0:boot_scan_right] bsiv; + wire [0:boot_scan_right] bsov; + wire [47:48] mmucfg_q; + wire [45:47] tlb0cfg_q; + wire [0:15] bcfg_spare_q; + + wire pc_cfg_sl_thold_0_b; + wire pc_cfg_sl_force; + wire lcb_dclk; + wire [0:`NCLK_WIDTH-1] lcb_lclk; + wire [47:48] mmucfg_q_b; + wire [45:47] tlb0cfg_q_b; + wire [0:15] bcfg_spare_q_b; + + wire [0:`MM_THREADS-1] cat_emf_act_d; + wire [0:`MM_THREADS-1] cat_emf_act_q; + wire [0:`MM_THREADS] spr_mmu_act_d; + wire [0:`MM_THREADS] spr_mmu_act_q; + wire [0:3] spr_val_act_d; + wire [0:3] spr_val_act_q; + wire spr_val_act; + wire spr_match_act; + wire spr_match_mas_act; + wire spr_mas_data_out_act; + wire [0:`MM_THREADS-1] mas_update_pending_act; + + wire [0:3] cswitch_q; + wire [0:`MM_THREADS-1] cp_flush_d, cp_flush_q; + wire [0:`MM_THREADS-1] cp_flush_p1_d, cp_flush_p1_q; + + // array of 2 bit bin values + wire [0:1] bin_2bit [0:3]; + wire tidn; + wire tiup; + + //## figtree_source: mmq_spr.fig; + //!! Bugspray Include: mmq_spr; + + assign tidn = 1'b0; + assign tiup = 1'b1; + assign bin_2bit[0] = 2'b00; + assign bin_2bit[1] = 2'b01; + assign bin_2bit[2] = 2'b10; + assign bin_2bit[3] = 2'b11; + + genvar i; + generate + for (i=0; i<`MM_THREADS; i=i+1) + begin : genacts + assign cat_emf_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[6] | (tlb_delayed_act[29+i] & xu_mm_ccr2_notlb_b); + assign spr_mmu_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[5]; + end + endgenerate + + assign spr_mmu_act_d[`MM_THREADS] = spr_match_any_mmu | mmucr2_act_override[5]; + assign spr_val_act_d[0] = xu_mm_slowspr_val; + assign spr_val_act_d[1] = spr_val_act_q[0]; + assign spr_val_act_d[2] = spr_val_act_q[1]; + assign spr_val_act_d[3] = spr_val_act_q[2]; + assign spr_val_act = spr_val_act_q[0] | spr_val_act_q[1] | spr_val_act_q[2] | spr_val_act_q[3] | mmucr2_act_override[5]; + assign spr_match_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[5]; + assign spr_match_mas_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[6]; + assign spr_mas_data_out_act = spr_val_act_q[0] | mmucr2_act_override[6]; +`ifdef WAIT_UPDATES + assign mas_update_pending_act = cat_emf_act_q | tlb_mas_dtlb_error_pending_q | tlb_mas_itlb_error_pending_q | tlb_lper_we_pending_q | + tlb_mmucr1_we_pending_q | ierat_mmucr1_we_pending_q | derat_mmucr1_we_pending_q; +`else + assign mas_update_pending_act = cat_emf_act_q; +`endif + + + //--------------------------------------------------------------------- + // slow spr logic + //--------------------------------------------------------------------- + // input latches for spr access + assign spr_etid_onehot[0] = (xu_mm_slowspr_etid == 2'b00); + assign spr_etid_onehot[1] = (xu_mm_slowspr_etid == 2'b01); + assign spr_etid_onehot[2] = (xu_mm_slowspr_etid == 2'b10); + assign spr_etid_onehot[3] = (xu_mm_slowspr_etid == 2'b11); + assign spr_etid_in_onehot[0] = (spr_etid_in_q == 2'b00); + assign spr_etid_in_onehot[1] = (spr_etid_in_q == 2'b01); + assign spr_etid_in_onehot[2] = (spr_etid_in_q == 2'b10); + assign spr_etid_in_onehot[3] = (spr_etid_in_q == 2'b11); + assign spr_etid_int_onehot[0] = (spr_etid_int_q == 2'b00); + assign spr_etid_int_onehot[1] = (spr_etid_int_q == 2'b01); + assign spr_etid_int_onehot[2] = (spr_etid_int_q == 2'b10); + assign spr_etid_int_onehot[3] = (spr_etid_int_q == 2'b11); + + generate + begin : etid_generate + genvar tid; + for (tid = 0; tid <= 3; tid = tid + 1) + begin : mmqsprflush + if (tid < `THREADS) + begin : mmqsprtidExist + assign spr_etid_flushed[tid] = cp_flush_q[tid] & spr_etid_onehot[tid]; + assign spr_etid_in_flushed[tid] = cp_flush_q[tid] & spr_etid_in_onehot[tid]; + assign spr_etid_int_flushed[tid] = cp_flush_q[tid] & spr_etid_int_onehot[tid]; + end + if (tid >= `THREADS) + begin : mmqsprtidNExist + assign spr_etid_flushed[tid] = 1'b0; + assign spr_etid_in_flushed[tid] = 1'b0; + assign spr_etid_int_flushed[tid] = 1'b0; + assign unused_dc_threads[tid] = spr_etid_onehot[tid] | spr_etid_in_onehot[tid] | spr_etid_int_onehot[tid]; + end + end + end + endgenerate + +`ifdef WAIT_UPDATES + generate + begin : mmq_spr_tid_generate + genvar tid; + for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1) + begin : mmThreads + if (tid < `THREADS) + begin : tidExist + assign cp_flush_d[tid] = cp_flush[tid]; + end + if (tid >= `THREADS) + begin : tidNExist + assign cp_flush_d[tid] = tidn; + end + end + end + endgenerate +`endif + +assign iu_mm_ierat_mmucr1_we_d = iu_mm_ierat_mmucr1_we; +assign xu_mm_derat_mmucr1_we_d = xu_mm_derat_mmucr1_we; + + // delay because cp_mm_except_taken bus lags cp_flush from completion by 1 cyc + assign cp_flush_p1_d = cp_flush_q; + assign cp_flush_p1 = cp_flush_p1_q; + + //masthdNExist : if `THDID_WIDTH > (`MM_THREADS) generate begin + // masthdunused : for tid in (`MM_THREADS) to (`THDID_WIDTH-1) generate begin + // unused_dc_thdid(tid) <= lrat_mas_thdid(tid) or tlb_lper_we_upd(tid) or tlb_delayed_act(tid+29); + // end generate masthdunused; + //end generate masthdNExist; + assign spr_val_flushed = |(spr_etid_flushed); + assign spr_val_in_flushed = |(spr_etid_in_flushed); + assign spr_val_int_flushed = |(spr_etid_int_flushed); + assign spr_ctl_in_d[0] = xu_mm_slowspr_val & (~(spr_val_flushed)); + assign spr_ctl_in_d[1] = xu_mm_slowspr_rw; + assign spr_ctl_in_d[2] = xu_mm_slowspr_done; + assign spr_etid_in_d = xu_mm_slowspr_etid; + assign spr_addr_in_d = xu_mm_slowspr_addr; + assign spr_addr_in_clone_d = xu_mm_slowspr_addr; + assign spr_data_in_d = xu_mm_slowspr_data; + // internal select latches for spr access + assign spr_ctl_int_d[0] = spr_ctl_in_q[0] & (~(spr_val_in_flushed)); + assign spr_ctl_int_d[1:2] = spr_ctl_in_q[1:2]; + assign spr_etid_int_d = spr_etid_in_q; + assign spr_addr_int_d = spr_addr_in_q; + assign spr_data_int_d = spr_data_in_q; + + assign spr_match_any_mmu = ( spr_ctl_in_q[0] & + ((spr_addr_in_q == Spr_Addr_PID) | + (spr_addr_in_q == Spr_Addr_MMUCR0) | (spr_addr_in_q == Spr_Addr_MMUCR1) | (spr_addr_in_q == Spr_Addr_MMUCR2) | (spr_addr_in_q == Spr_Addr_MMUCR3) | + (spr_addr_in_q == Spr_Addr_LPID) | + (spr_addr_in_q == Spr_Addr_MESR1) | (spr_addr_in_q == Spr_Addr_MESR2) | + (spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | + (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | + (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | + (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | + (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | + (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | + (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b) | + (spr_addr_in_clone_q == Spr_Addr_MMUCFG) | (spr_addr_in_clone_q == Spr_Addr_MMUCSR0) | + (spr_addr_in_clone_q == Spr_Addr_TLB0CFG) | (spr_addr_in_clone_q == Spr_Addr_TLB0PS) | + (spr_addr_in_clone_q == Spr_Addr_LRATCFG) | (spr_addr_in_clone_q == Spr_Addr_LRATPS) | + (spr_addr_in_clone_q == Spr_Addr_EPTCFG) | (spr_addr_in_clone_q == Spr_Addr_LPER) | + (spr_addr_in_clone_q == Spr_Addr_LPERU)) ); + + assign spr_match_pid0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_PID)); + assign spr_match_mmucr0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR0)); + assign spr_match_mmucr3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR3)); +`ifdef MM_THREADS2 + assign spr_match_pid1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_PID)); + assign spr_match_mmucr0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR0)); + assign spr_match_mmucr3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR3)); +`endif + assign spr_match_mmucr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR1)); + assign spr_match_mmucr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR2)); + assign spr_match_lpidr = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_LPID)); + assign spr_match_mesr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR1)); + assign spr_match_mesr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR2)); + assign spr_match_mmucsr0 = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCSR0)); + assign spr_match_mmucfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCFG)); + assign spr_match_tlb0cfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0CFG)); + assign spr_match_tlb0ps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0PS)); + assign spr_match_lratcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATCFG)); + assign spr_match_lratps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATPS)); + assign spr_match_eptcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_EPTCFG)); + assign spr_match_lper_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPER)); + assign spr_match_lperu_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); +`ifdef MM_THREADS2 + assign spr_match_lper_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPER)); + assign spr_match_lperu_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); +`endif + assign spr_match_any_mas = (spr_ctl_in_q[0] & ((spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b))); + assign spr_match_mas0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); + assign spr_match_mas1_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); + assign spr_match_mas2_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas2u_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); + assign spr_match_mas3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); + assign spr_match_mas4_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); + assign spr_match_mas5_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); + assign spr_match_mas6_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); + assign spr_match_mas7_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); + assign spr_match_mas8_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); + assign spr_match_mas01_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); +`ifdef MM_THREADS2 + assign spr_match_mas0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); + assign spr_match_mas1_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); + assign spr_match_mas2_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas2u_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); + assign spr_match_mas3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); + assign spr_match_mas4_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); + assign spr_match_mas5_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); + assign spr_match_mas6_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); + assign spr_match_mas7_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); + assign spr_match_mas8_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); + assign spr_match_mas01_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); +`endif + assign spr_match_mas2_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS2)); + assign spr_match_mas01_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); + assign spr_match_mas56_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); + assign spr_match_mas73_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); + assign spr_match_mas81_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); + assign spr_match_64b = spr_match_mas2_64b | spr_match_mas01_64b | spr_match_mas56_64b | spr_match_mas73_64b | spr_match_mas81_64b; + + + assign pid0_d = ((spr_match_pid0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : + pid0_q; +`ifdef MM_THREADS2 + assign pid1_d = ((spr_match_pid1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : + pid1_q; +`endif + // mmucr0: 0-ExtClass, 1-TID_NZ, 2:3-GS/TS, 4:5-TLBSel, 6:19-TID + assign mmucr0_0_d = ((spr_match_mmucr0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_0_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : + (xu_mm_derat_mmucr0_we_q[0] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_0_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : + (iu_mm_ierat_mmucr0_we_q[0] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_0_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : + mmucr0_0_q; +`ifdef MM_THREADS2 + assign mmucr0_1_d = ((spr_match_mmucr0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_1_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : + (xu_mm_derat_mmucr0_we_q[1] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_1_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : + (iu_mm_ierat_mmucr0_we_q[1] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_1_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : + mmucr0_1_q; +`endif + + // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, + // 4-Disable any context sync inst from invalidating extclass=0 erat entries, + // 5-Disable isync inst from invalidating extclass=0 erat entries, + // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, + // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, + // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN + // 2) mmucr1: merge EEN bits into single field, seperate I/D/T ERRDET bits + // 3) mmucr1: add ICTID, ITTID, DCTID, DTTID, TLBI_REJ, and TLBI_MSB bits + assign mmucr1_d[0:16] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:48] : + mmucr1_q[0:16]; + assign mmucr1_d[17] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? (spr_data_int_q[49] & (~cswitch_q[1])) : + mmucr1_q[17]; + assign mmucr1_d[18:19] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + mmucr1_q[18:19]; + // added cswitch0 to prevent side effect of clearing on read + assign mmucr1_d[20] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[52] : + ((|(iu_mm_ierat_mmucr1_we_upd) == 1'b1 & |(xu_mm_derat_mmucr1_we_upd) == 1'b0 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[20]; + assign mmucr1_d[21] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[53] : + ((|(xu_mm_derat_mmucr1_we_upd) == 1'b1 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[21]; + assign mmucr1_d[22] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[54] : + ((|(tlb_mmucr1_we_upd) == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : + mmucr1_q[22]; + assign mmucr1_d[23:31] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? {9{1'b0}} : + ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[55:63] : + ((tlb_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_0_een_upd : +`ifdef MM_THREADS2 + ((tlb_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_1_een_upd : +`endif + ((xu_mm_derat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_0_een_upd} : +`ifdef MM_THREADS2 + ((xu_mm_derat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_1_een_upd} : +`endif + ((iu_mm_ierat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_0_een_upd} : +`ifdef MM_THREADS2 + ((iu_mm_ierat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_1_een_upd} : +`endif + mmucr1_q[23:31]; + + // mmucr2: + assign mmucr2_d[0:31] = ((spr_match_mmucr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + mmucr2_q[0:31]; + + // mmucr3: + assign mmucr3_0_d = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + mmucr3_0_q; + + assign tstmode4k_0_d[0] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_0_q[0]; + + assign tstmode4k_0_d[1] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_0_q[1]; + + assign tstmode4k_0_d[2:3] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: + ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : + tstmode4k_0_q[2:3]; + + +`ifdef MM_THREADS2 + assign mmucr3_1_d = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : + mmucr3_1_q; + + assign tstmode4k_1_d[0] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_1_q[0]; + + assign tstmode4k_1_d[1] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : + tstmode4k_1_q[1]; + + assign tstmode4k_1_d[2:3] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: + ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : + tstmode4k_1_q[2:3]; + + `endif + + assign lpidr_d = ((spr_match_lpidr_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `LPID_WIDTH:63] : + lpidr_q; + + // Perf event select registers + // Each field controls selection of 1 of 64 events per event bus bit + // mesr1: 32:37 - MUXSELEB0, + // 38:43 - MUXSELEB1, + // 44:49 - MUXSELEB2, + // 50:55 - MUXSELEB3 + // mesr2: 32:37 - MUXSELEB4, + // 38:43 - MUXSELEB5, + // 44:49 - MUXSELEB6, + // 50:55 - MUXSELEB7 + assign mesr1_d[32:32 + `MESR1_WIDTH - 1] = ((spr_match_mesr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR1_WIDTH - 1] : + mesr1_q[32:32 + `MESR1_WIDTH - 1]; + assign mesr2_d[32:32 + `MESR2_WIDTH - 1] = ((spr_match_mesr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR2_WIDTH - 1] : + mesr2_q[32:32 + `MESR2_WIDTH - 1]; + + assign mmucsr0_tlb0fi_d = ((mmucsr0_tlb0fi_q == 1'b0 & spr_match_mmucsr0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[61] == 1'b1)) ? 1'b1 : + (mmq_inval_tlb0fi_done == 1'b1) ? 1'b0 : + mmucsr0_tlb0fi_q; + + +`ifdef WAIT_UPDATES + // cp_mm_except_taken_t0_q + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + assign cp_mm_except_taken_t0_d = cp_mm_except_taken_t0; + + assign tlb_mas_dtlb_error_upd[0] = tlb_mas_dtlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b11000}}; // dtlb miss except taken + assign tlb_mas_itlb_error_upd[0] = tlb_mas_itlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b01000}}; // itlb miss except taken + assign tlb_lper_we_upd[0] = tlb_lper_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0010}}; // lrat error except taken + assign tlb_mmucr1_we_upd[0] = tlb_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // tlb mcheck except taken + assign iu_mm_ierat_mmucr1_we_upd[0] = ierat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // ierat mcheck except taken + assign xu_mm_derat_mmucr1_we_upd[0] = derat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // derat mcheck except taken + + assign tlb_mas_dtlb_error_pending_d[0] = (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b11000 ) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[0] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mas_dtlb_error_pending_q[0]; + + assign tlb_mas_itlb_error_pending_d[0] = (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b01000 ) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[0] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mas_itlb_error_pending_q[0]; + + assign tlb_lper_we_pending_d[0] = (tlb_lper_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0010 ) ? 1'b0 : + (tlb_lper_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_lper_we_pending_q[0] == 1'b0 & tlb_lper_we[0] == 1'b1) ? 1'b1 : + tlb_lper_we_pending_q[0]; + + assign tlb_mmucr1_we_pending_d[0] = (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : + tlb_mmucr1_we_pending_q[0]; + + assign ierat_mmucr1_we_pending_d[0] = (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : + ierat_mmucr1_we_pending_q[0]; + + assign derat_mmucr1_we_pending_d[0] = (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : + (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : + (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : + derat_mmucr1_we_pending_q[0]; + + + assign tlb_mas1_0_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_ts_error : + tlb_mas1_0_ts_error_q; + assign tlb_mas1_0_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_tid_error : + tlb_mas1_0_tid_error_q; + assign tlb_mas2_0_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas2_epn_error : + tlb_mas2_0_epn_error_q; + assign tlb_lper_0_lpn_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lpn : + tlb_lper_0_lpn_q; + assign tlb_lper_0_lps_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lps : + tlb_lper_0_lps_q; + + assign tlb_mmucr1_0_een_d = (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? tlb_mmucr1_een : + tlb_mmucr1_0_een_q; + + assign ierat_mmucr1_0_een_d = (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? iu_mm_ierat_mmucr1_q : + ierat_mmucr1_0_een_q; + + assign derat_mmucr1_0_een_d = (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? xu_mm_derat_mmucr1_q : + derat_mmucr1_0_een_q; + + + assign tlb_mas1_0_ts_error_upd = tlb_mas1_0_ts_error_q; + assign tlb_mas1_0_tid_error_upd = tlb_mas1_0_tid_error_q; + assign tlb_mas2_0_epn_error_upd = tlb_mas2_0_epn_error_q; + assign tlb_lper_0_lpn_upd = tlb_lper_0_lpn_q; + assign tlb_lper_0_lps_upd = tlb_lper_0_lps_q; + assign tlb_mmucr1_0_een_upd = tlb_mmucr1_0_een_q; + assign ierat_mmucr1_0_een_upd = ierat_mmucr1_0_een_q; + assign derat_mmucr1_0_een_upd = derat_mmucr1_0_een_q; + +`ifdef MM_THREADS2 + // cp_mm_except_taken_t1_q + // 0 - val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + assign cp_mm_except_taken_t1_d = cp_mm_except_taken_t1; + + assign tlb_mas_dtlb_error_upd[1] = tlb_mas_dtlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b11000}}; // dtlb miss except taken + assign tlb_mas_itlb_error_upd[1] = tlb_mas_itlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b01000}}; // itlb miss except taken + assign tlb_lper_we_upd[1] = tlb_lper_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0010}}; // lrat error except taken + assign tlb_mmucr1_we_upd[1] = tlb_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // tlb mcheck except taken + assign iu_mm_ierat_mmucr1_we_upd[1] = ierat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // ierat mcheck except taken + assign xu_mm_derat_mmucr1_we_upd[1] = derat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // derat mcheck except taken + + assign tlb_mas_dtlb_error_pending_d[1] = (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b11000 ) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mas_dtlb_error_pending_q[1] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mas_dtlb_error_pending_q[1]; + + assign tlb_mas_itlb_error_pending_d[1] = (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b01000 ) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mas_itlb_error_pending_q[1] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mas_itlb_error_pending_q[1]; + + assign tlb_lper_we_pending_d[1] = (tlb_lper_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0010 ) ? 1'b0 : + (tlb_lper_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_lper_we_pending_q[1] == 1'b0 & tlb_lper_we[1] == 1'b1) ? 1'b1 : + tlb_lper_we_pending_q[1]; + + assign tlb_mmucr1_we_pending_d[1] = (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : + tlb_mmucr1_we_pending_q[1]; + + assign ierat_mmucr1_we_pending_d[1] = (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : + ierat_mmucr1_we_pending_q[1]; + + assign derat_mmucr1_we_pending_d[1] = (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[1] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : + (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : + (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : + derat_mmucr1_we_pending_q[1]; + + assign tlb_mas1_1_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_ts_error : + tlb_mas1_1_ts_error_q; + assign tlb_mas1_1_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_tid_error : + tlb_mas1_1_tid_error_q; + assign tlb_mas2_1_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas2_epn_error : + tlb_mas2_1_epn_error_q; + assign tlb_lper_1_lpn_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lpn : + tlb_lper_1_lpn_q; + assign tlb_lper_1_lps_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lps : + tlb_lper_1_lps_q; + + assign tlb_mmucr1_1_een_d = (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? tlb_mmucr1_een : + tlb_mmucr1_1_een_q; + + assign ierat_mmucr1_1_een_d = (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? iu_mm_ierat_mmucr1_q : + ierat_mmucr1_1_een_q; + + assign derat_mmucr1_1_een_d = (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? xu_mm_derat_mmucr1_q : + derat_mmucr1_1_een_q; + + + assign tlb_mas1_1_ts_error_upd = tlb_mas1_1_ts_error_q; + assign tlb_mas1_1_tid_error_upd = tlb_mas1_1_tid_error_q; + assign tlb_mas2_1_epn_error_upd = tlb_mas2_1_epn_error_q; + assign tlb_lper_1_lpn_upd = tlb_lper_1_lpn_q; + assign tlb_lper_1_lps_upd = tlb_lper_1_lps_q; + assign tlb_mmucr1_1_een_upd = tlb_mmucr1_1_een_q; + assign ierat_mmucr1_1_een_upd = ierat_mmucr1_1_een_q; + assign derat_mmucr1_1_een_upd = derat_mmucr1_1_een_q; +`endif +`else + assign tlb_mas_dtlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_dtlb_error}}; + assign tlb_mas_itlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_itlb_error}}; + assign tlb_lper_we_upd = tlb_lper_we; + + assign tlb_mmucr1_we_upd = {`MM_THREADS{tlb_mmucr1_we}} & tlb_mas_thdid[0:`MM_THREADS-1]; + assign iu_mm_ierat_mmucr1_we_upd = iu_mm_ierat_mmucr1_we_q; + assign xu_mm_derat_mmucr1_we_upd = xu_mm_derat_mmucr1_we_q; + + assign tlb_mas1_0_ts_error_upd = tlb_mas1_ts_error; + assign tlb_mas1_0_tid_error_upd = tlb_mas1_tid_error; + assign tlb_mas2_0_epn_error_upd = tlb_mas2_epn_error; + assign tlb_lper_0_lpn_upd = tlb_lper_lpn; + assign tlb_lper_0_lps_upd = tlb_lper_lps; + assign tlb_mmucr1_0_een_upd = tlb_mmucr1_een; + assign ierat_mmucr1_0_een_upd = iu_mm_ierat_mmucr1_q; + assign derat_mmucr1_0_een_upd = xu_mm_derat_mmucr1_q; +`ifdef MM_THREADS2 + assign tlb_mas1_1_ts_error_upd = tlb_mas1_ts_error; + assign tlb_mas1_1_tid_error_upd = tlb_mas1_tid_error; + assign tlb_mas2_1_epn_error_upd = tlb_mas2_epn_error; + assign tlb_lper_1_lpn_upd = tlb_lper_lpn; + assign tlb_lper_1_lps_upd = tlb_lper_lps; + assign tlb_mmucr1_1_een_upd = tlb_mmucr1_een; + assign ierat_mmucr1_1_een_upd = iu_mm_ierat_mmucr1_q; + assign derat_mmucr1_1_een_upd = xu_mm_derat_mmucr1_q; +`endif +`endif + + + assign lper_0_alpn_d[32:51] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[32:51] : + lper_0_alpn_q[32:51]; + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_lper_0_alpn + assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : + ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_lper_0_alpn + assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + assign lper_0_lps_d = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : + (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lps_upd[60:63] : + lper_0_lps_q; + +`ifdef MM_THREADS2 + assign lper_1_alpn_d[32:51] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[32:51] : + lper_1_alpn_q[32:51]; + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_lper_1_alpn + assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : + ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_lper_1_alpn + assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : + lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; + end + endgenerate + + assign lper_1_lps_d = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : + (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lps_upd[60:63] : + lper_1_lps_q; +`endif + + + + assign mas1_0_v_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? 1'b0 : + ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_v : + ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_v : + mas1_0_v_q; + assign mas1_0_iprot_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_iprot : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_iprot_q; + assign mas1_0_tid_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_spid_q : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {`PID_WIDTH{1'b0}} : + mas1_0_tid_q; + assign mas1_0_ind_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? mas4_0_indd_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ind : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_ind_q; + assign mas1_0_ts_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_sas_q : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ts : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas1_0_ts_q; + assign mas1_0_tsize_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tsize : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_tsize : + mas1_0_tsize_q; + + assign mas2_0_epn_d[32:51] = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas2_0_epn_error_upd[32:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[32:51] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[32:51] : + mas2_0_epn_q[32:51]; + assign mas2_0_wimge_d = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_wimged_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_wimge : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 5'b0 : + mas2_0_wimge_q; + + assign mas3_0_rpnl_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {21{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : + mas3_0_rpnl_q; + assign mas3_0_ubits_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 4'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas3_ubits : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 4'b0 : + mas3_0_ubits_q; + assign mas3_0_usxwr_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 6'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 6'b0 : + mas3_0_usxwr_q; + + // no h/w updates to mas4 + assign mas4_0_indd_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : + mas4_0_indd_q; + assign mas4_0_tsized_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + mas4_0_tsized_q; + assign mas4_0_wimged_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + mas4_0_wimged_q; + + assign mas6_0_spid_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : + mas6_0_spid_q; + assign mas6_0_isize_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : + mas6_0_isize_q; + assign mas6_0_sind_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_indd_q : + mas6_0_sind_q; + assign mas6_0_sas_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : + ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : + mas6_0_sas_q; + +`ifdef MM_THREADS2 + assign mas1_1_v_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? 1'b0 : + ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_v : + ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_v : + mas1_1_v_q; + assign mas1_1_iprot_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 1'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_iprot : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_iprot_q; + assign mas1_1_tid_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_spid_q : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {`PID_WIDTH{1'b0}} : + mas1_1_tid_q; + assign mas1_1_ind_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_indd_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ind : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_ind_q; + assign mas1_1_ts_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : + ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_sas_q : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ts : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas1_1_ts_q; + assign mas1_1_tsize_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_tsized_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tsize : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_tsize : + mas1_1_tsize_q; + + assign mas2_1_epn_d[32:51] = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[32:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[32:51] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[32:51] : + mas2_1_epn_q[32:51]; + assign mas2_1_wimge_d = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_wimged_q : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_wimge : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 5'b0 : + mas2_1_wimge_q; + + assign mas3_1_rpnl_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 21'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : + mas3_1_rpnl_q; + assign mas3_1_ubits_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 4'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas3_ubits : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 4'b0 : + mas3_1_ubits_q; + assign mas3_1_usxwr_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 6'b0 : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 6'b0 : + mas3_1_usxwr_q; + + // no h/w updates to mas4 + assign mas4_1_indd_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : + mas4_1_indd_q; + assign mas4_1_tsized_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + mas4_1_tsized_q; + assign mas4_1_wimged_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : + mas4_1_wimged_q; + + assign mas6_1_spid_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : + mas6_1_spid_q; + assign mas6_1_isize_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_tsized_q : + mas6_1_isize_q; + assign mas6_1_sind_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_indd_q : + mas6_1_sind_q; + assign mas6_1_sas_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : + mas6_1_sas_q; +`endif + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas_d + assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + mas0_0_atsel_q; + assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : + mas0_0_esel_q; + assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + mas0_0_hes_q; + assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : + mas0_0_wq_q; + + assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + mas5_0_sgs_q; + assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + mas5_0_slpid_q; + + assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : + mas7_0_rpnu_q; + + assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_tgs_q; + assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_vf_q; + assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : + mas8_0_tlpid_q; + +`ifdef MM_THREADS2 + assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + mas0_1_atsel_q; + assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : + mas0_1_esel_q; + assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + mas0_1_hes_q; + assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : + mas0_1_wq_q; + + assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + mas5_1_sgs_q; + assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + mas5_1_slpid_q; + + assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : + mas7_1_rpnu_q; + + assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_tgs_q; + assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_vf_q; + assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : + mas8_1_tlpid_q; +`endif + end + endgenerate + + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas_d + assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : + mas0_0_atsel_q; + assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : + mas0_0_esel_q; + assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : + mas0_0_hes_q; + assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : + mas0_0_wq_q; + + assign mas2_0_epn_d[0:31] = ((spr_match_mas2u_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : + (((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1))) ? tlb_mas2_0_epn_error_upd[0:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[0:31] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[0:31] : + mas2_0_epn_q[0:31]; + + assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + mas5_0_sgs_q; + assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + mas5_0_slpid_q; + + assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + ((spr_match_mas73_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : + mas7_0_rpnu_q; + + assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_tgs_q; + assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : + mas8_0_vf_q; + assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : + mas8_0_tlpid_q; + +`ifdef MM_THREADS2 + assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : + mas0_1_atsel_q; + assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : + (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 3'b0 : + (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : + mas0_1_esel_q; + assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : + mas0_1_hes_q; + assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : + ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : + mas0_1_wq_q; + + assign mas2_1_epn_d[0:31] = ((spr_match_mas2u_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : + ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : + (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[0:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[0:31] : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[0:31] : + mas2_1_epn_q[0:31]; + + assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + mas5_1_sgs_q; + assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + mas5_1_slpid_q; + + assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : + (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : + ((spr_match_mas73_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : + mas7_1_rpnu_q; + + assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_tgs_q; + assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : + mas8_1_vf_q; + assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : + ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : + (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : + (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : + mas8_1_tlpid_q; +`endif + end + endgenerate + + // 0: val, 1: rw, 2: done + assign spr_ctl_out_d[0] = spr_ctl_int_q[0] & (~(spr_val_int_flushed)); + assign spr_ctl_out_d[1] = spr_ctl_int_q[1]; + assign spr_ctl_out_d[2] = (spr_ctl_int_q[2] | spr_match_any_mmu_q) & (~(spr_val_int_flushed)); + assign spr_etid_out_d = spr_etid_int_q; + assign spr_addr_out_d = spr_addr_int_q; + //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal + //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal + + assign spr_data_out_d[32:63] = ( {{32-`LPID_WIDTH{1'b0}}, lpidr_q} & {32{(spr_match_lpidr_q & spr_ctl_int_q[1])}} ) | + ( {{32-`PID_WIDTH{1'b0}}, pid0_q} & {32{(spr_match_pid0_q & spr_ctl_int_q[1])}} ) | + ( {mmucr0_0_q[0:5], 12'b0, mmucr0_0_q[6:19]} & {32{(spr_match_mmucr0_0_q & spr_ctl_int_q[1])}} ) | + ( mmucr1_q & {32{(spr_match_mmucr1_q & spr_ctl_int_q[1])}} ) | + ( mmucr2_q & {32{(spr_match_mmucr2_q & spr_ctl_int_q[1])}} ) | + ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_0_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_0_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_0_q & spr_ctl_int_q[1])}} ) | + ( {mesr1_q[32:32 + `MESR1_WIDTH - 1], {32-`MESR1_WIDTH{1'b0}}} & {32{(spr_match_mesr1_q & spr_ctl_int_q[1])}} ) | + ( {mesr2_q[32:32 + `MESR2_WIDTH - 1], {32-`MESR2_WIDTH{1'b0}}} & {32{(spr_match_mesr2_q & spr_ctl_int_q[1])}} ) | + ( {29'b0, mmucsr0_tlb0fi_q, 2'b00} & {32{(spr_match_mmucsr0_q & spr_ctl_int_q[1])}} ) | + ( {Spr_Data_MMUCFG[32:46], mmucfg_q[47:48], Spr_Data_MMUCFG[49:63]} & {32{(spr_match_mmucfg_q & spr_ctl_int_q[1])}} ) | + ( {Spr_Data_TLB0CFG[32:44], tlb0cfg_q[45:47], Spr_Data_TLB0CFG[48:63]} & {32{(spr_match_tlb0cfg_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_TLB0PS & {32{(spr_match_tlb0ps_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_LRATCFG & {32{(spr_match_lratcfg_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_LRATPS & {32{(spr_match_lratps_q & spr_ctl_int_q[1])}} ) | + ( Spr_Data_EPTCFG & {32{(spr_match_eptcfg_q & spr_ctl_int_q[1])}} ) | + ( {lper_0_alpn_q[32:51], 8'b0, lper_0_lps_q[60:63]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_0_q & spr_ctl_int_q[1])}} ) | +`ifdef MM_THREADS2 + ( {{32-`PID_WIDTH{1'b0}}, pid1_q} & {32{(spr_match_pid1_q & spr_ctl_int_q[1])}} ) | + ( {mmucr0_1_q[0:5], 12'b0, mmucr0_1_q[6:19]} & {32{(spr_match_mmucr0_1_q & spr_ctl_int_q[1])}} ) | + ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_1_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_1_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_1_q & spr_ctl_int_q[1])}} ) | + ( {lper_1_alpn_q[32:51], 8'b0, lper_1_lps_q[60:63]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_1_q & spr_ctl_int_q[1])}} ) | +`endif + ( (spr_mas_data_out_q[32:63]) & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | + ( spr_data_int_q[32:63] & {32{(~spr_match_any_mmu_q)}} ); + + assign spr_mas_data_out[32:63] = ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas0_0}} ) | + ( {mas1_0_v_q, mas1_0_iprot_q, mas1_0_tid_q, 2'b00, mas1_0_ind_q, mas1_0_ts_q, mas1_0_tsize_q, 8'b00000000} & {32{(spr_match_mas1_0 | spr_match_mas01_64b_0 | spr_match_mas81_64b_0)}} ) | + ( {mas2_0_epn_q[32:51], 7'b0000000, mas2_0_wimge_q} & {32{spr_match_mas2_0}} ) | + ( {mas2_0_epn_q[0:31]} & {32{spr_match_mas2u_0}} ) | + ( {mas3_0_rpnl_q, 1'b0, mas3_0_ubits_q, mas3_0_usxwr_q} & {32{(spr_match_mas3_0 | spr_match_mas73_64b_0)}} ) | + ( {16'b0, mas4_0_indd_q, 3'b000, mas4_0_tsized_q, 3'b000, mas4_0_wimged_q} & {32{spr_match_mas4_0}} ) | + ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas5_0}} ) | + ( {2'b00, mas6_0_spid_q, 4'b0000, mas6_0_isize_q, 6'b000000, mas6_0_sind_q, mas6_0_sas_q} & {32{(spr_match_mas6_0 | spr_match_mas56_64b_0)}} ) | + ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas7_0}} ) | +`ifdef MM_THREADS2 + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ) | + ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas0_1}} ) | + ( {mas1_1_v_q, mas1_1_iprot_q, mas1_1_tid_q, 2'b00, mas1_1_ind_q, mas1_1_ts_q, mas1_1_tsize_q, 8'b00000000} & {32{(spr_match_mas1_1 | spr_match_mas01_64b_1 | spr_match_mas81_64b_1)}} ) | + ( {mas2_1_epn_q[32:51], 7'b0000000, mas2_1_wimge_q} & {32{spr_match_mas2_1}} ) | + ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2u_1}} ) | + ( {mas3_1_rpnl_q, 1'b0, mas3_1_ubits_q, mas3_1_usxwr_q} & {32{(spr_match_mas3_1 | spr_match_mas73_64b_1)}} ) | + ( {16'b0, mas4_1_indd_q, 3'b000, mas4_1_tsized_q, 3'b000, mas4_1_wimged_q} & {32{spr_match_mas4_1}} ) | + ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas5_1}} ) | + ( {2'b00, mas6_1_spid_q, 4'b0000, mas6_1_isize_q, 6'b000000, mas6_1_sind_q, mas6_1_sas_q} & {32{(spr_match_mas6_1 | spr_match_mas56_64b_1)}} ) | + ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas7_1}} ) | + ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas8_1}} ); +`else + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ); +`endif + + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_spr_data + assign spr_mas_data_out[0:31] = ( mas2_0_epn_q[0:31] & {32{spr_match_mas2_0}} ) | + ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas01_64b_0}} ) | + ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas56_64b_0}} ) | + ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas73_64b_0}} ) | +`ifdef MM_THREADS2 + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ) | + ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2_1}} ) | + ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas01_64b_1}} ) | + ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas56_64b_1}} ) | + ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas73_64b_1}} ) | + ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas81_64b_1}} ); +`else + ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ); +`endif + + //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal + //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal + assign spr_data_out_d[0:31] = ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | +`ifdef MM_THREADS2 + ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | +`endif + ( {spr_mas_data_out_q[0:31]} & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | + ( {spr_data_int_q[0:31]} & {32{((~(spr_match_any_mmu_q)) | (~(spr_ctl_int_q[1])))}} ); + end + endgenerate + + assign mm_iu_slowspr_val = spr_ctl_out_q[0]; + assign mm_iu_slowspr_rw = spr_ctl_out_q[1]; + assign mm_iu_slowspr_etid = spr_etid_out_q; + assign mm_iu_slowspr_addr = spr_addr_out_q; + assign mm_iu_slowspr_data = spr_data_out_q; + assign mm_iu_slowspr_done = spr_ctl_out_q[2]; + + assign mm_iu_ierat_pid0 = pid0_q; + assign mm_iu_ierat_mmucr0_0 = mmucr0_0_q; + assign mm_iu_ierat_mmucr1 = {mmucr1_q[0], mmucr1_q[2:5], mmucr1_q[6:7], mmucr1_q[12:13]}; + assign mm_xu_derat_pid0 = pid0_q; + assign mm_xu_derat_mmucr0_0 = mmucr0_0_q; + assign mm_xu_derat_mmucr1 = {mmucr1_q[1], mmucr1_q[2:5], mmucr1_q[8:9], mmucr1_q[14:16]}; +`ifdef MM_THREADS2 + assign mm_iu_ierat_pid1 = pid1_q; + assign mm_iu_ierat_mmucr0_1 = mmucr0_1_q; + assign mm_xu_derat_pid1 = pid1_q; + assign mm_xu_derat_mmucr0_1 = mmucr0_1_q; +`endif + + // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, + // 4-Disable any context sync inst from invalidating extclass=0 erat entries, + // 5-Disable isync inst from invalidating extclass=0 erat entries, + // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, + // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, + // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN + assign pid0 = pid0_q; + assign mmucr0_0 = mmucr0_0_q; + assign mmucr1 = mmucr1_q; + assign mmucr2 = mmucr2_q; + assign mmucr3_0 = mmucr3_0_q; + assign tstmode4k_0 = tstmode4k_0_q[1:3]; +`ifdef MM_THREADS2 + assign pid1 = pid1_q; + assign mmucr0_1 = mmucr0_1_q; + assign mmucr3_1 = mmucr3_1_q; + assign tstmode4k_1 = tstmode4k_1_q[1:3]; +`endif + assign lpidr = lpidr_q; + assign ac_an_lpar_id = lpidr_q; + assign mmucfg_lrat = mmucfg_q[47]; + assign mmucfg_twc = mmucfg_q[48]; + assign tlb0cfg_pt = tlb0cfg_q[45]; + assign tlb0cfg_ind = tlb0cfg_q[46]; + assign tlb0cfg_gtwe = tlb0cfg_q[47]; + assign mmq_spr_event_mux_ctrls = {mesr1_q, mesr2_q}; + assign mas0_0_atsel = mas0_0_atsel_q; + assign mas0_0_esel = mas0_0_esel_q; + assign mas0_0_hes = mas0_0_hes_q; + assign mas0_0_wq = mas0_0_wq_q; + assign mas1_0_v = mas1_0_v_q; + assign mas1_0_iprot = mas1_0_iprot_q; + assign mas1_0_tid = mas1_0_tid_q; + assign mas1_0_ind = mas1_0_ind_q; + assign mas1_0_ts = mas1_0_ts_q; + assign mas1_0_tsize = mas1_0_tsize_q; + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas2_0_epn + assign mas2_0_epn[0:31] = {32{1'b0}}; + assign mas2_0_epn[32:51] = mas2_0_epn_q[32:51]; + end + endgenerate + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas2_0_epn + assign mas2_0_epn = mas2_0_epn_q; + end + endgenerate + + assign mas2_0_wimge = mas2_0_wimge_q; + assign mas3_0_rpnl = mas3_0_rpnl_q; + assign mas3_0_ubits = mas3_0_ubits_q; + assign mas3_0_usxwr = mas3_0_usxwr_q; + assign mas5_0_sgs = mas5_0_sgs_q; + assign mas5_0_slpid = mas5_0_slpid_q; + assign mas6_0_spid = mas6_0_spid_q; + assign mas6_0_isize = mas6_0_isize_q; + assign mas6_0_sind = mas6_0_sind_q; + assign mas6_0_sas = mas6_0_sas_q; + assign mas7_0_rpnu = mas7_0_rpnu_q; + assign mas8_0_tgs = mas8_0_tgs_q; + assign mas8_0_vf = mas8_0_vf_q; + assign mas8_0_tlpid = mas8_0_tlpid_q; +`ifdef MM_THREADS2 + assign mas0_1_atsel = mas0_1_atsel_q; + assign mas0_1_esel = mas0_1_esel_q; + assign mas0_1_hes = mas0_1_hes_q; + assign mas0_1_wq = mas0_1_wq_q; + assign mas1_1_v = mas1_1_v_q; + assign mas1_1_iprot = mas1_1_iprot_q; + assign mas1_1_tid = mas1_1_tid_q; + assign mas1_1_ind = mas1_1_ind_q; + assign mas1_1_ts = mas1_1_ts_q; + assign mas1_1_tsize = mas1_1_tsize_q; + + generate + if (`SPR_DATA_WIDTH == 32) + begin : gen32_mas2_1_epn + assign mas2_1_epn[0:31] = {32{1'b0}}; + assign mas2_1_epn[32:51] = mas2_1_epn_q[32:51]; + end + endgenerate + generate + if (`SPR_DATA_WIDTH == 64) + begin : gen64_mas2_1_epn + assign mas2_1_epn = mas2_1_epn_q; + end + endgenerate + + assign mas2_1_wimge = mas2_1_wimge_q; + assign mas3_1_rpnl = mas3_1_rpnl_q; + assign mas3_1_ubits = mas3_1_ubits_q; + assign mas3_1_usxwr = mas3_1_usxwr_q; + assign mas5_1_sgs = mas5_1_sgs_q; + assign mas5_1_slpid = mas5_1_slpid_q; + assign mas6_1_spid = mas6_1_spid_q; + assign mas6_1_isize = mas6_1_isize_q; + assign mas6_1_sind = mas6_1_sind_q; + assign mas6_1_sas = mas6_1_sas_q; + assign mas7_1_rpnu = mas7_1_rpnu_q; + assign mas8_1_tgs = mas8_1_tgs_q; + assign mas8_1_vf = mas8_1_vf_q; + assign mas8_1_tlpid = mas8_1_tlpid_q; +`endif + + assign mmucsr0_tlb0fi = mmucsr0_tlb0fi_q; + +`ifdef WAIT_UPDATES +`ifdef MM_THREADS2 + assign cp_mm_perf_except_taken_q[0] = cp_mm_except_taken_t0_q[0]; + assign cp_mm_perf_except_taken_q[1] = cp_mm_except_taken_t1_q[0]; + assign cp_mm_perf_except_taken_q[2:6] = (cp_mm_except_taken_t0_q[1:5] | cp_mm_except_taken_t1_q[1:5]); +`else + assign cp_mm_perf_except_taken_q = cp_mm_except_taken_t0_q; +`endif +`endif + + + // debug output formation + //spr_dbg_slowspr_val_in <= spr_ctl_in_q(0); -- 0: val, 1: rw, 2: done + //spr_dbg_slowspr_rw_in <= spr_ctl_in_q(1); + //spr_dbg_slowspr_etid_in <= spr_etid_in_q; + //spr_dbg_slowspr_addr_in <= spr_addr_in_q; + assign spr_dbg_slowspr_val_int = spr_ctl_int_q[0]; + assign spr_dbg_slowspr_rw_int = spr_ctl_int_q[1]; + assign spr_dbg_slowspr_etid_int = spr_etid_int_q; + assign spr_dbg_slowspr_addr_int = spr_addr_int_q; + assign spr_dbg_slowspr_val_out = spr_ctl_out_q[0]; + assign spr_dbg_slowspr_done_out = spr_ctl_out_q[2]; + assign spr_dbg_slowspr_data_out = spr_data_out_q; + assign spr_dbg_match_64b = spr_match_64b_q; + assign spr_dbg_match_any_mmu = spr_match_any_mmu_q; + assign spr_dbg_match_any_mas = spr_match_any_mas_q; + assign spr_dbg_match_mmucr1 = spr_match_mmucr1_q; + assign spr_dbg_match_mmucr2 = spr_match_mmucr2_q; + assign spr_dbg_match_lpidr = spr_match_lpidr_q; + assign spr_dbg_match_mmucsr0 = spr_match_mmucsr0_q; + assign spr_dbg_match_mmucfg = spr_match_mmucfg_q; + assign spr_dbg_match_tlb0cfg = spr_match_tlb0cfg_q; + assign spr_dbg_match_tlb0ps = spr_match_tlb0ps_q; + assign spr_dbg_match_lratcfg = spr_match_lratcfg; + assign spr_dbg_match_lratps = spr_match_lratps_q; + assign spr_dbg_match_eptcfg = spr_match_eptcfg_q; +`ifdef MM_THREADS2 + assign spr_dbg_match_pid = spr_match_pid0_q | spr_match_pid1_q; + assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q | spr_match_mmucr0_1_q; + assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q | spr_match_mmucr3_1_q; + assign spr_dbg_match_lper = spr_match_lper_0_q | spr_match_lper_1_q; + assign spr_dbg_match_lperu = spr_match_lperu_0_q | spr_match_lperu_1_q; + assign spr_dbg_match_mas0 = spr_match_mas0_0_q | spr_match_mas0_1_q; + assign spr_dbg_match_mas1 = spr_match_mas1_0_q | spr_match_mas1_1_q; + assign spr_dbg_match_mas2 = spr_match_mas2_0_q | spr_match_mas2_1_q; + assign spr_dbg_match_mas2u = spr_match_mas2u_0_q | spr_match_mas2u_1_q; + assign spr_dbg_match_mas3 = spr_match_mas3_0_q | spr_match_mas3_1_q; + assign spr_dbg_match_mas4 = spr_match_mas4_0_q | spr_match_mas4_1_q; + assign spr_dbg_match_mas5 = spr_match_mas5_0_q | spr_match_mas5_1_q; + assign spr_dbg_match_mas6 = spr_match_mas6_0_q | spr_match_mas6_1_q; + assign spr_dbg_match_mas7 = spr_match_mas7_0_q | spr_match_mas7_1_q; + assign spr_dbg_match_mas8 = spr_match_mas8_0_q | spr_match_mas8_1_q; + assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q | spr_match_mas01_64b_1_q; + assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q | spr_match_mas56_64b_1_q; + assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q | spr_match_mas73_64b_1_q; + assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q | spr_match_mas81_64b_1_q; +`else + assign spr_dbg_match_pid = spr_match_pid0_q; + assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q; + assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q; + assign spr_dbg_match_lper = spr_match_lper_0_q; + assign spr_dbg_match_lperu = spr_match_lperu_0_q; + assign spr_dbg_match_mas0 = spr_match_mas0_0_q; + assign spr_dbg_match_mas1 = spr_match_mas1_0_q; + assign spr_dbg_match_mas2 = spr_match_mas2_0_q; + assign spr_dbg_match_mas2u = spr_match_mas2u_0_q; + assign spr_dbg_match_mas3 = spr_match_mas3_0_q; + assign spr_dbg_match_mas4 = spr_match_mas4_0_q; + assign spr_dbg_match_mas5 = spr_match_mas5_0_q; + assign spr_dbg_match_mas6 = spr_match_mas6_0_q; + assign spr_dbg_match_mas7 = spr_match_mas7_0_q; + assign spr_dbg_match_mas8 = spr_match_mas8_0_q; + assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q; + assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q; + assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q; + assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q; +`endif + + // unused spare signal assignments + assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); + assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); + assign unused_dc[2] = pc_func_sl_force; + assign unused_dc[3] = pc_func_sl_thold_0_b; + assign unused_dc[4] = tc_scan_dis_dc_b; + assign unused_dc[5] = tc_scan_diag_dc; + assign unused_dc[6] = tc_lbist_en_dc; + +generate + if (`EXPAND_TYPE != 1) + begin + assign unused_dc[7] = |(mmucfg_q_b); + assign unused_dc[8] = |(tlb0cfg_q_b); + assign unused_dc[13] = |(bcfg_spare_q_b); + end + else + begin + assign unused_dc[7] = 1'b0; + assign unused_dc[8] = 1'b0; + assign unused_dc[13] = pc_cfg_sl_thold_0; + end +endgenerate + + assign unused_dc[9] = 1'b0; + assign unused_dc[10] = 1'b0; + assign unused_dc[11] = |(lrat_tag4_hit_entry); + assign unused_dc[12] = |(bcfg_spare_q); + + //------------------------------------------------ + // latches + //------------------------------------------------ + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), + .scout(sov_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), + .din(cp_flush_d[0:`MM_THREADS - 1]), + .dout(cp_flush_q[0:`MM_THREADS - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_p1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), + .scout(sov_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), + .din(cp_flush_p1_d[0:`MM_THREADS - 1]), + .dout(cp_flush_p1_q[0:`MM_THREADS - 1]) + ); + + // slow spr daisy-chain latches + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_in_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_in_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_in_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_in_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_in_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_in_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_clone_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_in_clone_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_in_clone_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_in_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_in_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_in_q[64 - `SPR_DATA_WIDTH:63]) + ); + // these are the spr internal select stage latches below + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_int_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_int_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_int_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_int_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_int_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_int_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_int_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_int_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_int_q[64 - `SPR_DATA_WIDTH:63]) + ); + // these are the spr out latches below + + tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), + .scout(sov_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), + .din(spr_ctl_out_d[0:`SPR_CTL_WIDTH - 1]), + .dout(spr_ctl_out_q[0:`SPR_CTL_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), + .scout(sov_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), + .din(spr_etid_out_d[0:`SPR_ETID_WIDTH - 1]), + .dout(spr_etid_out_q[0:`SPR_ETID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), + .scout(sov_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), + .din(spr_addr_out_d[0:`SPR_ADDR_WIDTH - 1]), + .dout(spr_addr_out_q[0:`SPR_ADDR_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_val_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_data_out_d[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_data_out_q[64 - `SPR_DATA_WIDTH:63]) + ); + // spr decode match latches for timing + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mmu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_any_mmu_offset]), + .scout(sov_0[spr_match_any_mmu_offset]), + .din(spr_match_any_mmu), + .dout(spr_match_any_mmu_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_pid0_offset]), + .scout(sov_0[spr_match_pid0_offset]), + .din(spr_match_pid0), + .dout(spr_match_pid0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_pid1_offset]), + .scout(sov_0[spr_match_pid1_offset]), + .din(spr_match_pid1), + .dout(spr_match_pid1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr0_0_offset]), + .scout(sov_0[spr_match_mmucr0_0_offset]), + .din(spr_match_mmucr0_0), + .dout(spr_match_mmucr0_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr0_1_offset]), + .scout(sov_0[spr_match_mmucr0_1_offset]), + .din(spr_match_mmucr0_1), + .dout(spr_match_mmucr0_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr1_offset]), + .scout(sov_0[spr_match_mmucr1_offset]), + .din(spr_match_mmucr1), + .dout(spr_match_mmucr1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr2_offset]), + .scout(sov_0[spr_match_mmucr2_offset]), + .din(spr_match_mmucr2), + .dout(spr_match_mmucr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr3_0_offset]), + .scout(sov_0[spr_match_mmucr3_0_offset]), + .din(spr_match_mmucr3_0), + .dout(spr_match_mmucr3_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mmucr3_1_offset]), + .scout(sov_0[spr_match_mmucr3_1_offset]), + .din(spr_match_mmucr3_1), + .dout(spr_match_mmucr3_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lpidr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_lpidr_offset]), + .scout(sov_0[spr_match_lpidr_offset]), + .din(spr_match_lpidr), + .dout(spr_match_lpidr_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mesr1_offset]), + .scout(sov_0[spr_match_mesr1_offset]), + .din(spr_match_mesr1), + .dout(spr_match_mesr1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_match_mesr2_offset]), + .scout(sov_0[spr_match_mesr2_offset]), + .din(spr_match_mesr2), + .dout(spr_match_mesr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucsr0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mmucsr0_offset]), + .scout(sov_1[spr_match_mmucsr0_offset]), + .din(spr_match_mmucsr0), + .dout(spr_match_mmucsr0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mmucfg_offset]), + .scout(sov_1[spr_match_mmucfg_offset]), + .din(spr_match_mmucfg), + .dout(spr_match_mmucfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0cfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_tlb0cfg_offset]), + .scout(sov_1[spr_match_tlb0cfg_offset]), + .din(spr_match_tlb0cfg), + .dout(spr_match_tlb0cfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0ps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_tlb0ps_offset]), + .scout(sov_1[spr_match_tlb0ps_offset]), + .din(spr_match_tlb0ps), + .dout(spr_match_tlb0ps_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratcfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lratcfg_offset]), + .scout(sov_1[spr_match_lratcfg_offset]), + .din(spr_match_lratcfg), + .dout(spr_match_lratcfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lratps_offset]), + .scout(sov_1[spr_match_lratps_offset]), + .din(spr_match_lratps), + .dout(spr_match_lratps_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_eptcfg_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_eptcfg_offset]), + .scout(sov_1[spr_match_eptcfg_offset]), + .din(spr_match_eptcfg), + .dout(spr_match_eptcfg_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lper_0_offset]), + .scout(sov_1[spr_match_lper_0_offset]), + .din(spr_match_lper_0), + .dout(spr_match_lper_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lperu_0_offset]), + .scout(sov_1[spr_match_lperu_0_offset]), + .din(spr_match_lperu_0), + .dout(spr_match_lperu_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lper_1_offset]), + .scout(sov_1[spr_match_lper_1_offset]), + .din(spr_match_lper_1), + .dout(spr_match_lper_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_lperu_1_offset]), + .scout(sov_1[spr_match_lperu_1_offset]), + .din(spr_match_lperu_1), + .dout(spr_match_lperu_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas0_0_offset]), + .scout(sov_1[spr_match_mas0_0_offset]), + .din(spr_match_mas0_0), + .dout(spr_match_mas0_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas1_0_offset]), + .scout(sov_1[spr_match_mas1_0_offset]), + .din(spr_match_mas1_0), + .dout(spr_match_mas1_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2_0_offset]), + .scout(sov_1[spr_match_mas2_0_offset]), + .din(spr_match_mas2_0), + .dout(spr_match_mas2_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas3_0_offset]), + .scout(sov_1[spr_match_mas3_0_offset]), + .din(spr_match_mas3_0), + .dout(spr_match_mas3_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas4_0_offset]), + .scout(sov_1[spr_match_mas4_0_offset]), + .din(spr_match_mas4_0), + .dout(spr_match_mas4_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas5_0_offset]), + .scout(sov_1[spr_match_mas5_0_offset]), + .din(spr_match_mas5_0), + .dout(spr_match_mas5_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas6_0_offset]), + .scout(sov_1[spr_match_mas6_0_offset]), + .din(spr_match_mas6_0), + .dout(spr_match_mas6_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas7_0_offset]), + .scout(sov_1[spr_match_mas7_0_offset]), + .din(spr_match_mas7_0), + .dout(spr_match_mas7_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas8_0_offset]), + .scout(sov_1[spr_match_mas8_0_offset]), + .din(spr_match_mas8_0), + .dout(spr_match_mas8_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2u_0_offset]), + .scout(sov_1[spr_match_mas2u_0_offset]), + .din(spr_match_mas2u_0), + .dout(spr_match_mas2u_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas01_64b_0_offset]), + .scout(sov_1[spr_match_mas01_64b_0_offset]), + .din(spr_match_mas01_64b_0), + .dout(spr_match_mas01_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas56_64b_0_offset]), + .scout(sov_1[spr_match_mas56_64b_0_offset]), + .din(spr_match_mas56_64b_0), + .dout(spr_match_mas56_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas73_64b_0_offset]), + .scout(sov_1[spr_match_mas73_64b_0_offset]), + .din(spr_match_mas73_64b_0), + .dout(spr_match_mas73_64b_0_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas81_64b_0_offset]), + .scout(sov_1[spr_match_mas81_64b_0_offset]), + .din(spr_match_mas81_64b_0), + .dout(spr_match_mas81_64b_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas0_1_offset]), + .scout(sov_1[spr_match_mas0_1_offset]), + .din(spr_match_mas0_1), + .dout(spr_match_mas0_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas1_1_offset]), + .scout(sov_1[spr_match_mas1_1_offset]), + .din(spr_match_mas1_1), + .dout(spr_match_mas1_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2_1_offset]), + .scout(sov_1[spr_match_mas2_1_offset]), + .din(spr_match_mas2_1), + .dout(spr_match_mas2_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas3_1_offset]), + .scout(sov_1[spr_match_mas3_1_offset]), + .din(spr_match_mas3_1), + .dout(spr_match_mas3_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas4_1_offset]), + .scout(sov_1[spr_match_mas4_1_offset]), + .din(spr_match_mas4_1), + .dout(spr_match_mas4_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas5_1_offset]), + .scout(sov_1[spr_match_mas5_1_offset]), + .din(spr_match_mas5_1), + .dout(spr_match_mas5_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas6_1_offset]), + .scout(sov_1[spr_match_mas6_1_offset]), + .din(spr_match_mas6_1), + .dout(spr_match_mas6_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas7_1_offset]), + .scout(sov_1[spr_match_mas7_1_offset]), + .din(spr_match_mas7_1), + .dout(spr_match_mas7_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas8_1_offset]), + .scout(sov_1[spr_match_mas8_1_offset]), + .din(spr_match_mas8_1), + .dout(spr_match_mas8_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas2u_1_offset]), + .scout(sov_1[spr_match_mas2u_1_offset]), + .din(spr_match_mas2u_1), + .dout(spr_match_mas2u_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas01_64b_1_offset]), + .scout(sov_1[spr_match_mas01_64b_1_offset]), + .din(spr_match_mas01_64b_1), + .dout(spr_match_mas01_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas56_64b_1_offset]), + .scout(sov_1[spr_match_mas56_64b_1_offset]), + .din(spr_match_mas56_64b_1), + .dout(spr_match_mas56_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas73_64b_1_offset]), + .scout(sov_1[spr_match_mas73_64b_1_offset]), + .din(spr_match_mas73_64b_1), + .dout(spr_match_mas73_64b_1_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_mas81_64b_1_offset]), + .scout(sov_1[spr_match_mas81_64b_1_offset]), + .din(spr_match_mas81_64b_1), + .dout(spr_match_mas81_64b_1_q) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_64b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_64b_offset]), + .scout(sov_1[spr_match_64b_offset]), + .din(spr_match_64b), + .dout(spr_match_64b_q) + ); + // internal mas data output register + + tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_mas_data_out_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mas_data_out_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), + .scout(sov_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), + .din(spr_mas_data_out[64 - `SPR_DATA_WIDTH:63]), + .dout(spr_mas_data_out_q[64 - `SPR_DATA_WIDTH:63]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_match_mas_act), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spr_match_any_mas_offset]), + .scout(sov_1[spr_match_any_mas_offset]), + .din(spr_match_any_mas), + .dout(spr_match_any_mas_q) + ); + // pid spr's + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), + .scout(sov_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), + .din(pid0_d[0:`PID_WIDTH - 1]), + .dout(pid0_q[0:`PID_WIDTH - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), + .scout(sov_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), + .din(pid1_d[0:`PID_WIDTH - 1]), + .dout(pid1_q[0:`PID_WIDTH - 1]) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), + .scout(sov_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), + .din(mmucr0_0_d[0:`MMUCR0_WIDTH - 1]), + .dout(mmucr0_0_q[0:`MMUCR0_WIDTH - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), + .scout(sov_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), + .din(mmucr0_1_d[0:`MMUCR0_WIDTH - 1]), + .dout(mmucr0_1_q[0:`MMUCR0_WIDTH - 1]) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MMUCR1_WIDTH), .INIT(BCFG_MMUCR1_VALUE), .NEEDS_SRESET(1)) mmucr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), + .scout(bsov[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), + .din(mmucr1_d[0:`MMUCR1_WIDTH - 1]), + .dout(mmucr1_q[0:`MMUCR1_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMUCR2_WIDTH), .INIT(BCFG_MMUCR2_VALUE), .NEEDS_SRESET(1)) mmucr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), + .scout(bsov[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), + .din(mmucr2_d[0:`MMUCR2_WIDTH - 1]), + .dout(mmucr2_q[0:`MMUCR2_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), + .scout(bsov[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), + .din(mmucr3_0_d[64 - `MMUCR3_WIDTH:63]), + .dout(mmucr3_0_q[64 - `MMUCR3_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tstmode4k_0_offset:tstmode4k_0_offset + 3]), + .scout(bsov[tstmode4k_0_offset:tstmode4k_0_offset + 3]), + .din(tstmode4k_0_d), + .dout(tstmode4k_0_q) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), + .scout(bsov[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), + .din(mmucr3_1_d[64 - `MMUCR3_WIDTH:63]), + .dout(mmucr3_1_q[64 - `MMUCR3_WIDTH:63]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tstmode4k_1_offset:tstmode4k_1_offset + 3]), + .scout(bsov[tstmode4k_1_offset:tstmode4k_1_offset + 3]), + .din(tstmode4k_1_d), + .dout(tstmode4k_1_q) + ); + +`endif + + tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lpidr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), + .scout(sov_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), + .din(lpidr_d[0:`LPID_WIDTH - 1]), + .dout(lpidr_q[0:`LPID_WIDTH - 1]) + ); + + tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), + .scout(sov_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), + .din(mesr1_d), + .dout(mesr1_q) + ); + + tri_rlmreg_p #(.WIDTH(`MESR2_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr2_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(spr_mmu_act_q[`MM_THREADS]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), + .scout(sov_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), + .din(mesr2_d), + .dout(mesr2_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_atsel_offset]), + .scout(sov_1[mas0_0_atsel_offset]), + .din(mas0_0_atsel_d), + .dout(mas0_0_atsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_0_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), + .scout(sov_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), + .din(mas0_0_esel_d[0:3 - 1]), + .dout(mas0_0_esel_q[0:3 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_hes_offset]), + .scout(sov_1[mas0_0_hes_offset]), + .din(mas0_0_hes_d), + .dout(mas0_0_hes_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_0_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), + .scout(sov_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), + .din(mas0_0_wq_d[0:2 - 1]), + .dout(mas0_0_wq_q[0:2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_v_offset]), + .scout(sov_1[mas1_0_v_offset]), + .din(mas1_0_v_d), + .dout(mas1_0_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_iprot_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_iprot_offset]), + .scout(sov_1[mas1_0_iprot_offset]), + .din(mas1_0_iprot_d), + .dout(mas1_0_iprot_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), + .scout(sov_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), + .din(mas1_0_tid_d[0:`PID_WIDTH - 1]), + .dout(mas1_0_tid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_ind_offset]), + .scout(sov_1[mas1_0_ind_offset]), + .din(mas1_0_ind_d), + .dout(mas1_0_ind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ts_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_ts_offset]), + .scout(sov_1[mas1_0_ts_offset]), + .din(mas1_0_ts_d), + .dout(mas1_0_ts_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tsize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), + .scout(sov_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), + .din(mas1_0_tsize_d[0:4 - 1]), + .dout(mas1_0_tsize_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_0_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .scout(sov_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .din(mas2_0_epn_d[(64-`SPR_DATA_WIDTH):51]), + .dout(mas2_0_epn_q[(64-`SPR_DATA_WIDTH):51]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_0_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), + .scout(sov_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), + .din(mas2_0_wimge_d[0:5 - 1]), + .dout(mas2_0_wimge_q[0:5 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_0_rpnl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), + .scout(sov_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), + .din(mas3_0_rpnl_d[32:32 + 21 - 1]), + .dout(mas3_0_rpnl_q[32:32 + 21 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_0_ubits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), + .scout(sov_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), + .din(mas3_0_ubits_d[0:4 - 1]), + .dout(mas3_0_ubits_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_0_usxwr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), + .scout(sov_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), + .din(mas3_0_usxwr_d[0:6 - 1]), + .dout(mas3_0_usxwr_q[0:6 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_0_indd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_indd_offset]), + .scout(bsov[mas4_0_indd_offset]), + .din(mas4_0_indd_d), + .dout(mas4_0_indd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_0_tsized_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), + .scout(bsov[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), + .din(mas4_0_tsized_d[0:4 - 1]), + .dout(mas4_0_tsized_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_0_wimged_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), + .scout(bsov[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), + .din(mas4_0_wimged_d[0:5 - 1]), + .dout(mas4_0_wimged_q[0:5 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_0_sgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_0_sgs_offset]), + .scout(sov_1[mas5_0_sgs_offset]), + .din(mas5_0_sgs_d), + .dout(mas5_0_sgs_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_0_slpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), + .scout(sov_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), + .din(mas5_0_slpid_d[0:8 - 1]), + .dout(mas5_0_slpid_q[0:8 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_0_spid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), + .scout(sov_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), + .din(mas6_0_spid_d[0:14 - 1]), + .dout(mas6_0_spid_q[0:14 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_0_isize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), + .scout(sov_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), + .din(mas6_0_isize_d[0:4 - 1]), + .dout(mas6_0_isize_q[0:4 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_sind_offset]), + .scout(sov_1[mas6_0_sind_offset]), + .din(mas6_0_sind_d), + .dout(mas6_0_sind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_0_sas_offset]), + .scout(sov_1[mas6_0_sas_offset]), + .din(mas6_0_sas_d), + .dout(mas6_0_sas_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_0_rpnu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), + .scout(sov_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), + .din(mas7_0_rpnu_d[22:22 + 10 - 1]), + .dout(mas7_0_rpnu_q[22:22 + 10 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_tgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_tgs_offset]), + .scout(sov_1[mas8_0_tgs_offset]), + .din(mas8_0_tgs_d), + .dout(mas8_0_tgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_vf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_vf_offset]), + .scout(sov_1[mas8_0_vf_offset]), + .din(mas8_0_vf_d), + .dout(mas8_0_vf_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_0_tlpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), + .scout(sov_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), + .din(mas8_0_tlpid_d[0:8 - 1]), + .dout(mas8_0_tlpid_q[0:8 - 1]) + ); + +`ifdef MM_THREADS2 + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_atsel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_atsel_offset]), + .scout(sov_1[mas0_1_atsel_offset]), + .din(mas0_1_atsel_d), + .dout(mas0_1_atsel_q) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_1_esel_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), + .scout(sov_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), + .din(mas0_1_esel_d[0:3 - 1]), + .dout(mas0_1_esel_q[0:3 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_hes_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_hes_offset]), + .scout(sov_1[mas0_1_hes_offset]), + .din(mas0_1_hes_d), + .dout(mas0_1_hes_q) + ); + + tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_1_wq_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), + .scout(sov_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), + .din(mas0_1_wq_d[0:2 - 1]), + .dout(mas0_1_wq_q[0:2 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_v_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_v_offset]), + .scout(sov_1[mas1_1_v_offset]), + .din(mas1_1_v_d), + .dout(mas1_1_v_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_iprot_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_iprot_offset]), + .scout(sov_1[mas1_1_iprot_offset]), + .din(mas1_1_iprot_d), + .dout(mas1_1_iprot_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), + .scout(sov_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), + .din(mas1_1_tid_d[0:`PID_WIDTH - 1]), + .dout(mas1_1_tid_q[0:`PID_WIDTH - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_ind_offset]), + .scout(sov_1[mas1_1_ind_offset]), + .din(mas1_1_ind_d), + .dout(mas1_1_ind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ts_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_ts_offset]), + .scout(sov_1[mas1_1_ts_offset]), + .din(mas1_1_ts_d), + .dout(mas1_1_ts_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tsize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), + .scout(sov_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), + .din(mas1_1_tsize_d[0:4 - 1]), + .dout(mas1_1_tsize_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_1_epn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .scout(sov_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), + .din(mas2_1_epn_d[(64-`SPR_DATA_WIDTH):51]), + .dout(mas2_1_epn_q[(64-`SPR_DATA_WIDTH):51]) + ); + + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_1_wimge_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), + .scout(sov_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), + .din(mas2_1_wimge_d[0:5 - 1]), + .dout(mas2_1_wimge_q[0:5 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_1_rpnl_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), + .scout(sov_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), + .din(mas3_1_rpnl_d[32:32 + 21 - 1]), + .dout(mas3_1_rpnl_q[32:32 + 21 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_1_ubits_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), + .scout(sov_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), + .din(mas3_1_ubits_d[0:4 - 1]), + .dout(mas3_1_ubits_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_1_usxwr_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), + .scout(sov_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), + .din(mas3_1_usxwr_d[0:6 - 1]), + .dout(mas3_1_usxwr_q[0:6 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_1_indd_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_indd_offset]), + .scout(bsov[mas4_1_indd_offset]), + .din(mas4_1_indd_d), + .dout(mas4_1_indd_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_1_tsized_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), + .scout(bsov[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), + .din(mas4_1_tsized_d[0:4 - 1]), + .dout(mas4_1_tsized_q[0:4 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_1_wimged_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), + .scout(bsov[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), + .din(mas4_1_wimged_d[0:5 - 1]), + .dout(mas4_1_wimged_q[0:5 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_1_sgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_1_sgs_offset]), + .scout(sov_1[mas5_1_sgs_offset]), + .din(mas5_1_sgs_d), + .dout(mas5_1_sgs_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_1_slpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), + .scout(sov_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), + .din(mas5_1_slpid_d[0:8 - 1]), + .dout(mas5_1_slpid_q[0:8 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_1_spid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), + .scout(sov_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), + .din(mas6_1_spid_d[0:14 - 1]), + .dout(mas6_1_spid_q[0:14 - 1]) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_1_isize_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), + .scout(sov_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), + .din(mas6_1_isize_d[0:4 - 1]), + .dout(mas6_1_isize_q[0:4 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sind_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_sind_offset]), + .scout(sov_1[mas6_1_sind_offset]), + .din(mas6_1_sind_d), + .dout(mas6_1_sind_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sas_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas6_1_sas_offset]), + .scout(sov_1[mas6_1_sas_offset]), + .din(mas6_1_sas_d), + .dout(mas6_1_sas_q) + ); + + tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_1_rpnu_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), + .scout(sov_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), + .din(mas7_1_rpnu_d[22:22 + 10 - 1]), + .dout(mas7_1_rpnu_q[22:22 + 10 - 1]) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_tgs_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_tgs_offset]), + .scout(sov_1[mas8_1_tgs_offset]), + .din(mas8_1_tgs_d), + .dout(mas8_1_tgs_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_vf_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_vf_offset]), + .scout(sov_1[mas8_1_vf_offset]), + .din(mas8_1_vf_d), + .dout(mas8_1_vf_q) + ); + + tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_1_tlpid_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), + .scout(sov_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), + .din(mas8_1_tlpid_d[0:8 - 1]), + .dout(mas8_1_tlpid_q[0:8 - 1]) + ); +`endif + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucsr0_tlb0fi_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[mmucsr0_tlb0fi_offset]), + .scout(sov_1[mmucsr0_tlb0fi_offset]), + .din(mmucsr0_tlb0fi_d), + .dout(mmucsr0_tlb0fi_q) + ); + + tri_rlmreg_p #(.WIDTH(52-(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_0_alpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .scout(sov_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .din(lper_0_alpn_d), + .dout(lper_0_alpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_0_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), + .scout(sov_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), + .din(lper_0_lps_d), + .dout(lper_0_lps_q) + ); + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(52 -(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_1_alpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .scout(sov_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), + .din(lper_1_alpn_d), + .dout(lper_1_alpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_1_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(mas_update_pending_act[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), + .scout(sov_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), + .din(lper_1_lps_d), + .dout(lper_1_lps_q) + ); +`endif + + tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) spr_mmu_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), + .scout(sov_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), + .din(spr_mmu_act_d), + .dout(spr_mmu_act_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) spr_val_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), + .scout(sov_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), + .din(spr_val_act_d), + .dout(spr_val_act_q) + ); + +`ifdef WAIT_UPDATES + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t0_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), + .scout(sov_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), + .din(cp_mm_except_taken_t0_d), + .dout(cp_mm_except_taken_t0_q) + ); + // cp_mm_except_taken + // 0 - thdid/val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_dtlb_error_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), + .din(tlb_mas_dtlb_error_pending_d), + .dout(tlb_mas_dtlb_error_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_itlb_error_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), + .din(tlb_mas_itlb_error_pending_d), + .dout(tlb_mas_itlb_error_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), + .din(tlb_lper_we_pending_d), + .dout(tlb_lper_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(tlb_mmucr1_we_pending_d), + .dout(tlb_mmucr1_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(ierat_mmucr1_we_pending_d), + .dout(ierat_mmucr1_we_pending_q) + ); + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_we_pending_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .scout(sov_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), + .din(derat_mmucr1_we_pending_d), + .dout(derat_mmucr1_we_pending_q) + ); + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_ts_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_0_ts_error_offset]), + .scout(sov_0[tlb_mas1_0_ts_error_offset]), + .din(tlb_mas1_0_ts_error_d), + .dout(tlb_mas1_0_ts_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_tid_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), + .scout(sov_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), + .din(tlb_mas1_0_tid_error_d), + .dout(tlb_mas1_0_tid_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_0_epn_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), + .scout(sov_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), + .din(tlb_mas2_0_epn_error_d), + .dout(tlb_mas2_0_epn_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .scout(sov_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .din(tlb_lper_0_lpn_d), + .dout(tlb_lper_0_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), + .scout(sov_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), + .din(tlb_lper_0_lps_d), + .dout(tlb_lper_0_lps_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), + .scout(sov_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), + .din(tlb_mmucr1_0_een_d), + .dout(tlb_mmucr1_0_een_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu_mm_ierat_mmucr1_we_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), + .scout(sov_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), + .din(ierat_mmucr1_0_een_d), + .dout(ierat_mmucr1_0_een_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_0_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_derat_mmucr1_we_q[0]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), + .scout(sov_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), + .din(derat_mmucr1_0_een_d), + .dout(derat_mmucr1_0_een_q) + ); + + +`ifdef MM_THREADS2 + tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t1_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), + .scout(sov_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), + .din(cp_mm_except_taken_t1_d), + .dout(cp_mm_except_taken_t1_q) + ); + // cp_mm_except_taken + // 0 - thdid/val + // 1 - I=0/D=1 + // 2 - TLB miss + // 3 - Storage int (TLBI/PTfault) + // 4 - LRAT miss + // 5 - Mcheck + + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_ts_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_1_ts_error_offset]), + .scout(sov_0[tlb_mas1_1_ts_error_offset]), + .din(tlb_mas1_1_ts_error_d), + .dout(tlb_mas1_1_ts_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_tid_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), + .scout(sov_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), + .din(tlb_mas1_1_tid_error_d), + .dout(tlb_mas1_1_tid_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_1_epn_error_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), + .scout(sov_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), + .din(tlb_mas2_1_epn_error_d), + .dout(tlb_mas2_1_epn_error_q) + ); + + tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lpn_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .scout(sov_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), + .din(tlb_lper_1_lpn_d), + .dout(tlb_lper_1_lpn_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lps_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), + .scout(sov_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), + .din(tlb_lper_1_lps_d), + .dout(tlb_lper_1_lps_q) + ); + + tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(cat_emf_act_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), + .scout(sov_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), + .din(tlb_mmucr1_1_een_d), + .dout(tlb_mmucr1_1_een_q) + ); + + tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(iu_mm_ierat_mmucr1_we_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), + .scout(sov_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), + .din(ierat_mmucr1_1_een_d), + .dout(ierat_mmucr1_1_een_q) + ); + + tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_1_een_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(xu_mm_derat_mmucr1_we_q[1]), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), + .scout(sov_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), + .din(derat_mmucr1_1_een_d), + .dout(derat_mmucr1_1_een_q) + ); + +`endif +`endif + + tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_SPR_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[cswitch_offset:cswitch_offset + 4 - 1]), + .scout(sov_0[cswitch_offset:cswitch_offset + 4 - 1]), + .din(cswitch_q), + .dout(cswitch_q) + ); + // cswitch0: 1=disable side affect of clearing I/D/TERRDET and EEN when reading mmucr1 + // cswitch1: 1=disable mmucr1.tlbwe_binv bit (make it look like it is reserved per dd1) + // cswitch2: reserved + // cswitch3: reserved + + tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cat_emf_act_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), + .scout(sov_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), + .din(cat_emf_act_d), + .dout(cat_emf_act_q) + ); + + tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_0[spare_a_offset:spare_a_offset + 32 - 1]), + .scout(sov_0[spare_a_offset:spare_a_offset + 32 - 1]), + .din(spare_a_q), + .dout(spare_a_q) + ); + + tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_func_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_func_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(siv_1[spare_b_offset:spare_b_offset + 64 - 1]), + .scout(sov_1[spare_b_offset:spare_b_offset + 64 - 1]), + .din(spare_b_q), + .dout(spare_b_q) + ); + + // non-scannable timing latches + tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[0:17]), + .scout(tri_regk_unused_scan[0:17]), + .din(iu_mm_ierat_mmucr0), + .dout(iu_mm_ierat_mmucr0_q) + ); + + tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[18:35]), + .scout(tri_regk_unused_scan[18:35]), + .din(xu_mm_derat_mmucr0), + .dout(xu_mm_derat_mmucr0_q) + ); + + tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[36:39]), + .scout(tri_regk_unused_scan[36:39]), + .din(iu_mm_ierat_mmucr1), + .dout(iu_mm_ierat_mmucr1_q) + ); + + tri_regk #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[40:44]), + .scout(tri_regk_unused_scan[40:44]), + .din(xu_mm_derat_mmucr1), + .dout(xu_mm_derat_mmucr1_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45:45+`MM_THREADS-1]), + .scout(tri_regk_unused_scan[45:45+`MM_THREADS-1]), + .din(iu_mm_ierat_mmucr1_we_d), + .dout(iu_mm_ierat_mmucr1_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), + .din(xu_mm_derat_mmucr1_we_d), + .dout(xu_mm_derat_mmucr1_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), + .din(iu_mm_ierat_mmucr0_we), + .dout(iu_mm_ierat_mmucr0_we_q) + ); + + tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_we_latch( + .nclk(nclk), + .vd(vdd), + .gd(gnd), + .act(tiup), + .sg(pc_sg_0), + .force_t(pc_func_slp_nsl_force), + .d_mode(lcb_d_mode_dc), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .thold_b(pc_func_slp_nsl_thold_0_b), + .scin(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), + .scout(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), + .din(xu_mm_derat_mmucr0_we), + .dout(xu_mm_derat_mmucr0_we_q) + ); + + //------------------------------------------------ + // scan only latches for boot config + // mmucr1, mmucr2, and mmucr3 also in boot config + //------------------------------------------------ + generate + if (`EXPAND_TYPE != 1) + begin : mpg_bcfg_gen + + tri_slat_scan #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) mmucfg_47to48_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[mmucfg_offset:mmucfg_offset + 1]), + .scan_out(bsov[mmucfg_offset:mmucfg_offset + 1]), + .q(mmucfg_q[47:48]), + .q_b(mmucfg_q_b[47:48]) + ); + + tri_slat_scan #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) tlb0cfg_45to47_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), + .scan_out(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), + .q(tlb0cfg_q[45:47]), + .q_b(tlb0cfg_q_b[45:47]) + ); + + tri_slat_scan #(.WIDTH(16), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .dclk(lcb_dclk), + .lclk(lcb_lclk), + .scan_in(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .scan_out(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .q(bcfg_spare_q), + .q_b(bcfg_spare_q_b) + ); + + // these terms in the absence of another lcbor component + // that drives the thold_b and force into the bcfg_lcb for slat's + assign pc_cfg_sl_thold_0_b = (~pc_cfg_sl_thold_0); + assign pc_cfg_sl_force = pc_sg_0; + + //------------------------------------------------ + // local clock buffer for boot config + //------------------------------------------------ + + tri_lcbs bcfg_lcb( + .vd(vdd), + .gd(gnd), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .nclk(nclk), + .force_t(pc_cfg_sl_force), + .thold_b(pc_cfg_sl_thold_0_b), + .dclk(lcb_dclk), + .lclk(lcb_lclk) + ); + + end + endgenerate + + generate + if (`EXPAND_TYPE == 1) + begin : fpga_bcfg_gen + + tri_rlmreg_p #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .NEEDS_SRESET(1)) mmucfg_47to48_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[mmucfg_offset:mmucfg_offset + 1]), + .scout(bsov[mmucfg_offset:mmucfg_offset + 1]), + .din(mmucfg_q[47:48]), + .dout(mmucfg_q[47:48]) + ); + + tri_rlmreg_p #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .NEEDS_SRESET(1)) tlb0cfg_45to47_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), + .scout(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), + .din(tlb0cfg_q[45:47]), + .dout(tlb0cfg_q[45:47]) + ); + + tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) bcfg_spare_latch( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .act(tiup), + .thold_b(pc_cfg_slp_sl_thold_0_b), + .sg(pc_sg_0), + .force_t(pc_cfg_slp_sl_force), + .delay_lclkr(lcb_delay_lclkr_dc[0]), + .mpw1_b(lcb_mpw1_dc_b[0]), + .mpw2_b(lcb_mpw2_dc_b), + .d_mode(lcb_d_mode_dc), + .scin(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .scout(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), + .din(bcfg_spare_q), + .dout(bcfg_spare_q) + ); + end + endgenerate + + // Latch counts + // 3319 + // spr_ctl_in_q 3 + // spr_etid_in_q 2 + // spr_addr_in_q 10 + // spr_data_in_q 64 79 + // spr_ctl_int_q 3 + // spr_etid_int_q 2 + // spr_addr_int_q 10 + // spr_data_int_q 64 79 + // spr_ctl_out_q 3 + // spr_etid_out_q 2 + // spr_addr_out_q 10 + // spr_data_out_q 64 79 + // lper_ 0:3 _alpn_q 30 x 4 + // lper_ 0:3 _lps_q 4 x 4 136 + // pid 0:3 _q 14 x 4 + // mmucr0_ 0:3 _q 20 x 4 + // mmucr1_q 32 + // mmucr2_q 32 + // mmucr3_ 0:3 _q 15 x 4 + // lpidr_q 8 + // mmucsr0_tlb0fi_q 1 269 + // mas0__atsel_q 1 x 4 : std_ulogic; + // mas0__esel_q 3 x 4 : std_ulogic_vector(0 to 2); + // mas0__hes_q 1 x 4 : std_ulogic; + // mas0__wq_q 2 x 4 : std_ulogic_vector(0 to 1); + // mas1__v_q 1 x 4 : std_ulogic; + // mas1__iprot_q 1 x 4 : std_ulogic; + // mas1__tid_q 14 x 4 : std_ulogic_vector(0 to 13); + // mas1__ind_q 1 x 4 : std_ulogic; + // mas1__ts_q 1 x 4 : std_ulogic; + // mas1__tsize_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas2__epn_q 52 x 4 : std_ulogic_vector(64-`SPR_DATA_WIDTH to 51); + // mas2__wimge_q 5 x 4 : std_ulogic_vector(0 to 4); + // mas3__rpnl_q 21 x 4 : std_ulogic_vector(32 to 52); + // mas3__ubits_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas3__usxwr_q 6 x 4 : std_ulogic_vector(0 to 5); + // mas4__indd_q 1 x 4 : std_ulogic; + // mas4__tsized_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas4__wimged_q 5 x 4 : std_ulogic_vector(0 to 4); + // mas5__sgs_q 1 x 4 : std_ulogic; + // mas5__slpid_q 8 x 4 : std_ulogic_vector(0 to 7); + // mas6__spid_q 14 x 4 : std_ulogic_vector(0 to 13); + // mas6__isize_q 4 x 4 : std_ulogic_vector(0 to 3); + // mas6__sind_q 1 x 4 : std_ulogic; + // mas6__sas_q 1 x 4 : std_ulogic; + // mas7__rpnu_q 10 x 4 : std_ulogic_vector(22 to 31); + // mas8__tgs_q 1 x 4 : std_ulogic; + // mas8__vf_q 1 x 4 : std_ulogic; + // mas8__tlpid_q 8 x 4 : std_ulogic_vector(0 to 7); + // subtotal 176 x 4 = 704 + //-------------------------------------------------------------- + // total 1346 + //------------------------------------------------ + //------------------------------------------------ + // thold/sg latches + //------------------------------------------------ + + tri_plat #(.WIDTH(7)) perv_2to1_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), + .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) + ); + + tri_plat #(.WIDTH(7)) perv_1to0_reg( + .vd(vdd), + .gd(gnd), + .nclk(nclk), + .flush(tc_ccflush_dc), + .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), + .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) + ); + + tri_lcbor perv_lcbor_func_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_sl_force), + .thold_b(pc_func_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_func_slp_sl_force), + .thold_b(pc_func_slp_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_cfg_slp_sl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_cfg_slp_sl_thold_0), + .sg(pc_sg_0), + .act_dis(lcb_act_dis_dc), + .force_t(pc_cfg_slp_sl_force), + .thold_b(pc_cfg_slp_sl_thold_0_b) + ); + + tri_lcbor perv_lcbor_func_slp_nsl( + .clkoff_b(lcb_clkoff_dc_b), + .thold(pc_func_slp_nsl_thold_0), + .sg(pc_fce_0), + .act_dis(tidn), + .force_t(pc_func_slp_nsl_force), + .thold_b(pc_func_slp_nsl_thold_0_b) + ); + + //--------------------------------------------------------------------- + // Scan + //--------------------------------------------------------------------- + assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; + assign ac_func_scan_out[0] = sov_0[0]; + assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; + assign ac_func_scan_out[1] = sov_1[0]; + assign bsiv[0:boot_scan_right] = {bsov[1:boot_scan_right], ac_bcfg_scan_in}; + assign ac_bcfg_scan_out = bsov[0]; + + function Eq; + input a, b; + reg result; + begin + if (a == b) + begin + result = 1'b1; + end + else + begin + result = 1'b0; + end + Eq = result; + end + endfunction + +endmodule diff --git a/dev/verilog/clkgating/tri_a2o.vh b/dev/verilog/clkgating/tri_a2o.vh new file mode 100755 index 0000000..67b79ae --- /dev/null +++ b/dev/verilog/clkgating/tri_a2o.vh @@ -0,0 +1,196 @@ +// © IBM Corp. 2022 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + + +// define inits for IUCR0, MMUCR2, XUCR0 to disable clock gating + +`ifndef _tri_a2o_vh_ +`define _tri_a2o_vh_ + +`include "tri.vh" + +// Use this line for 1 thread. Comment out for 2 thread design. +`define THREADS1 + +`define gpr_t 3'b000 +`define cr_t 3'b001 +`define lr_t 3'b010 +`define ctr_t 3'b011 +`define xer_t 3'b100 +`define spr_t 3'b101 +`define axu0_t 3'b110 +`define axu1_t 3'b111 + +`ifdef THREADS1 + `define THREADS 1 + `define THREAD_POOL_ENC 0 + `define THREADS_POOL_ENC 0 +`else + `define THREADS 2 + `define THREAD_POOL_ENC 1 + `define THREADS_POOL_ENC 1 +`endif +`define EFF_IFAR_ARCH 62 +`define EFF_IFAR_WIDTH 20 +`define EFF_IFAR 20 +`define FPR_POOL_ENC 6 +`define REGMODE 6 +`define FPR_POOL 64 +`define REAL_IFAR_WIDTH 42 +`define EMQ_ENTRIES 4 +`define GPR_WIDTH 64 +`define ITAG_SIZE_ENC 7 +`define CPL_Q_DEPTH 32 +`define CPL_Q_DEPTH_ENC 6 +`define GPR_WIDTH_ENC 6 +`define GPR_POOL_ENC 6 +`define GPR_POOL 64 +`define GPR_UCODE_POOL 4 +`define CR_POOL_ENC 5 +`define CR_POOL 24 +`define CR_UCODE_POOL 1 +`define BR_POOL_ENC 3 +`define BR_POOL 8 +`define LR_POOL_ENC 3 +`define LR_POOL 8 +`define LR_UCODE_POOL 0 +`define CTR_POOL_ENC 3 +`define CTR_POOL 8 +`define CTR_UCODE_POOL 0 +`define XER_POOL_ENC 4 +`define XER_POOL 12 +`define XER_UCODE_POOL 0 +`define LDSTQ_ENTRIES 16 +`define LDSTQ_ENTRIES_ENC 4 +`define STQ_ENTRIES 12 +`define STQ_ENTRIES_ENC 4 +`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from +`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported +`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE +`define LMQ_ENTRIES 8 +`define LMQ_ENTRIES_ENC 3 +`define LGQ_ENTRIES 8 +`define AXU_SPARE_ENC 3 +`define RV_FX0_ENTRIES 12 +`define RV_FX1_ENTRIES 12 +`define RV_LQ_ENTRIES 16 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU1_ENTRIES 0 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 +`define FXU1_ENABLE 1 +`define TYPE_WIDTH 3 +`define IBUFF_INSTR_WIDTH 70 +`define IBUFF_IFAR_WIDTH 20 +`define IBUFF_DEPTH 16 +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define FXU0_PIPE_START 1 +`define FXU0_PIPE_END 8 +`define FXU1_PIPE_START 1 +`define FXU1_PIPE_END 5 +`define LQ_LOAD_PIPE_START 4 +`define LQ_LOAD_PIPE_END 8 +`define LQ_REL_PIPE_START 2 +`define LQ_REL_PIPE_END 4 +`define LOAD_CREDITS 8 +`define STORE_CREDITS 4 //wtf 32 is normal; fpga bug needed 4 +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size +`define MMQ_ENTRIES 2 // MMU Queue Size +`define CR_WIDTH 4 +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) +`define XER_WIDTH 10 + +//wtf: change for verilatorsim - didnt help +//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +//`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +//`define INIT_IUCR0 16'h0000 // BP disabled + + +`define INIT_IUCR0 16'hC000 // BP disabled, cg=48:49 +`define INIT_XUCR0 32'h03700460 // cg=38:42 +`define INIT_MMUCR2 32'hFF0A7531 // gg=32:39 (33:34 unused?) + +`define INIT_MASK 2'b10 +`define RELQ_INCLUDE 0 // Reload Queue Included + +`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 + +//wtf: add completion stuff +/* + assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39]; + assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47]; + assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55]; + assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63]; +*/ +`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 +//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 +/* + assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47]; + assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55]; +*/ +`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 +//`define INIT_CPCR1 32'h00010100 // 1/1 + +// IERAT boot config entry values +`define IERAT_BCFG_EPN_0TO15 0 +`define IERAT_BCFG_EPN_16TO31 0 +`define IERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define IERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define IERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8181 for 512M, 65535 for 4G +`define IERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define IERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define IERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define IERAT_BCFG_ATTR 0 // u0-u3, endian + +// DERAT boot config entry values +`define DERAT_BCFG_EPN_0TO15 0 +`define DERAT_BCFG_EPN_16TO31 0 +`define DERAT_BCFG_EPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 65535 for 4G +`define DERAT_BCFG_EPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN_22TO31 0 // (2 ** 10) - 1 for x3ff +`define DERAT_BCFG_RPN_32TO47 (2 ** 16) - 1 // 1 for 64K, 8191 for 512M, 65535 for 4G +`define DERAT_BCFG_RPN_48TO51 (2 ** 4) - 1 // 15 for 64K or 4G +`define DERAT_BCFG_RPN2_32TO47 0 // 0 to match dd1 hardwired value; (2**16)-1 for same 64K page +`define DERAT_BCFG_RPN2_48TO51 0 // 0 to match dd1 hardwired value; (2**4)-2 for adjacent 4K page +`define DERAT_BCFG_ATTR 0 // u0-u3, endian + +// Do NOT add any defines below this line +`endif //_tri_a2o_vh_ diff --git a/dev/verilog/clkgating/xu_spr_cspr.v b/dev/verilog/clkgating/xu_spr_cspr.v new file mode 100755 index 0000000..d32be15 --- /dev/null +++ b/dev/verilog/clkgating/xu_spr_cspr.v @@ -0,0 +1,4970 @@ +// © IBM Corp. 2020 +// Licensed under the Apache License, Version 2.0 (the "License"), as modified by +// the terms below; you may not use the files in this repository except in +// compliance with the License as modified. +// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 +// +// Modified Terms: +// +// 1) For the purpose of the patent license granted to you in Section 3 of the +// License, the "Work" hereby includes implementations of the work of authorship +// in physical form. +// +// 2) Notwithstanding any terms to the contrary in the License, any licenses +// necessary for implementation of the Work that are available from OpenPOWER +// via the Power ISA End User License Agreement (EULA) are explicitly excluded +// hereunder, and may be obtained from OpenPOWER under the terms and conditions +// of the EULA. +// +// Unless required by applicable law or agreed to in writing, the reference design +// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT +// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License +// for the specific language governing permissions and limitations under the License. +// +// Additional rights, including the ability to physically implement a softcore that +// is compliant with the required sections of the Power ISA Specification, are +// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. + +`timescale 1 ns / 1 ns + +// Description: XU SPR - per core registers & array +// +//***************************************************************************** +`include "tri_a2o.vh" +module xu_spr_cspr +#( + parameter hvmode = 1, + parameter a2mode = 1, + parameter spr_xucr0_init = `INIT_XUCR0 +)( + input [0:`NCLK_WIDTH-1] nclk, + + // CHIP IO + input [0:`THREADS-1] an_ac_reservation_vld, + input an_ac_tb_update_enable, + input an_ac_tb_update_pulse, + input [0:`THREADS-1] an_ac_sleep_en, + input [54:61] an_ac_coreid, + input [32:35] an_ac_chipid_dc, + input [8:15] spr_pvr_version_dc, + input [12:15] spr_pvr_revision_dc, + input [16:19] spr_pvr_revision_minor_dc, + input pc_xu_instr_trace_mode, + input [0:1] pc_xu_instr_trace_tid, + output [0:`THREADS-1] instr_trace_mode, + + input d_mode_dc, + input [0:0] delay_lclkr_dc, + input [0:0] mpw1_dc_b, + input mpw2_dc_b, + + input bcfg_sl_force, + input bcfg_sl_thold_0_b, + input bcfg_slp_sl_force, + input bcfg_slp_sl_thold_0_b, + input ccfg_sl_force, + input ccfg_sl_thold_0_b, + input ccfg_slp_sl_force, + input ccfg_slp_sl_thold_0_b, + input dcfg_sl_force, + input dcfg_sl_thold_0_b, + input func_sl_force, + input func_sl_thold_0_b, + input func_slp_sl_force, + input func_slp_sl_thold_0_b, + input func_nsl_force, + input func_nsl_thold_0_b, + input sg_0, + input [0:1] scan_in, + output [0:1] scan_out, + input bcfg_scan_in, + output bcfg_scan_out, + input ccfg_scan_in, + output ccfg_scan_out, + input dcfg_scan_in, + output dcfg_scan_out, + + output cspr_tspr_rf1_act, + + // Decode + input [0:`THREADS-1] rv_xu_vld, + input rv_xu_ex0_ord, + input [0:31] rv_xu_ex0_instr, + input [62-`EFF_IFAR_WIDTH:61] rv_xu_ex0_ifar, + output [62-`EFF_IFAR_WIDTH:61] ex2_ifar, + + output spr_xu_ord_read_done, + output spr_xu_ord_write_done, + input xu_spr_ord_ready, + input [0:`THREADS-1] flush, + + // Read Data + input [0:`GPR_WIDTH*`THREADS-1] tspr_cspr_ex3_tspr_rt, + output [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, + + // Write Data + input [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, + output [0:`THREADS-1] cspr_tspr_ex3_spr_we, + output [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd_out, + + // SPRT Interface + output [0:`THREADS-1] cspr_tspr_ex2_tid, + output [0:31] cspr_tspr_ex1_instr, + output [0:`THREADS-1] cspr_tspr_dec_dbg_dis, + + // Illegal SPR + input [0:`THREADS-1] tspr_cspr_illeg_mtspr_b, + input [0:`THREADS-1] tspr_cspr_illeg_mfspr_b, + input [0:`THREADS-1] tspr_cspr_hypv_mtspr, + input [0:`THREADS-1] tspr_cspr_hypv_mfspr, + + // Array SPRs + output cspr_aspr_ex3_we, + output [0:5] cspr_aspr_ex3_waddr, + output cspr_aspr_ex1_re, + output [0:5] cspr_aspr_ex1_raddr, + input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] aspr_cspr_ex2_rdata, + + // Slow SPR Bus + output xu_slowspr_val_out, + output xu_slowspr_rw_out, + output [0:1] xu_slowspr_etid_out, + output [11:20] xu_slowspr_addr_out, + output [64-`GPR_WIDTH:63] xu_slowspr_data_out, + + // DCR Bus + output ac_an_dcr_act, + output ac_an_dcr_val, + output ac_an_dcr_read, + output ac_an_dcr_user, + output [0:1] ac_an_dcr_etid, + output [11:20] ac_an_dcr_addr, + output [64-`GPR_WIDTH:63] ac_an_dcr_data, + + // Trap + output spr_dec_ex4_spr_hypv, + output spr_dec_ex4_spr_illeg, + output spr_dec_ex4_spr_priv, + output spr_dec_ex4_np1_flush, + + output [0:9] cspr_tspr_timebase_taps, + output timer_update, + + // Run State + input pc_xu_pm_hold_thread, + input [0:`THREADS-1] iu_xu_stop, + output [0:`THREADS-1] xu_iu_run_thread, + output [0:`THREADS-1] xu_pc_spr_ccr0_we, + output [0:1] xu_pc_spr_ccr0_pme, + + // Quiesce + input [0:`THREADS-1] iu_xu_quiesce, + input [0:`THREADS-1] iu_xu_icache_quiesce, + input [0:`THREADS-1] lq_xu_quiesce, + input [0:`THREADS-1] mm_xu_quiesce, + input [0:`THREADS-1] bx_xu_quiesce, + output [0:`THREADS-1] xu_pc_running, + + // PCCR0 + input pc_xu_extirpts_dis_on_stop, + input pc_xu_timebase_dis_on_stop, + input pc_xu_decrem_dis_on_stop, + + // PERF + input [0:2] pc_xu_event_count_mode, + input pc_xu_event_bus_enable, + input [0:4*`THREADS-1] xu_event_bus_in, + output [0:4*`THREADS-1] xu_event_bus_out, + input [0:`THREADS-1] div_spr_running, + input [0:`THREADS-1] mul_spr_running, + + + // MSR Override + input [0:`THREADS-1] pc_xu_ram_active, + input pc_xu_msrovride_enab, + output [0:`THREADS-1] cspr_tspr_msrovride_en, + output [0:`THREADS-1] cspr_tspr_ram_active, + + // LiveLock + output [0:`THREADS-1] cspr_tspr_llen, + output [0:`THREADS-1] cspr_tspr_llpri, + input [0:`THREADS-1] tspr_cspr_lldet, + input [0:`THREADS-1] tspr_cspr_llpulse, + + // Reset + input pc_xu_reset_wd_complete, + input pc_xu_reset_3_complete, + input pc_xu_reset_2_complete, + input pc_xu_reset_1_complete, + output reset_wd_complete, + output reset_3_complete, + output reset_2_complete, + output reset_1_complete, + + // Async Interrupt Masking + output [0:`THREADS-1] cspr_tspr_crit_mask, + output [0:`THREADS-1] cspr_tspr_ext_mask, + output [0:`THREADS-1] cspr_tspr_dec_mask, + output [0:`THREADS-1] cspr_tspr_fit_mask, + output [0:`THREADS-1] cspr_tspr_wdog_mask, + output [0:`THREADS-1] cspr_tspr_udec_mask, + output [0:`THREADS-1] cspr_tspr_perf_mask, + output cspr_tspr_sleep_mask, + + input [0:`THREADS-1] tspr_cspr_pm_wake_up, + + // More Async Interrupts + output [0:`THREADS-1] xu_iu_dbell_interrupt, + output [0:`THREADS-1] xu_iu_cdbell_interrupt, + output [0:`THREADS-1] xu_iu_gdbell_interrupt, + output [0:`THREADS-1] xu_iu_gcdbell_interrupt, + output [0:`THREADS-1] xu_iu_gmcdbell_interrupt, + input [0:`THREADS-1] iu_xu_dbell_taken, + input [0:`THREADS-1] iu_xu_cdbell_taken, + input [0:`THREADS-1] iu_xu_gdbell_taken, + input [0:`THREADS-1] iu_xu_gcdbell_taken, + input [0:`THREADS-1] iu_xu_gmcdbell_taken, + + // DBELL Int + input lq_xu_dbell_val, + input [0:4] lq_xu_dbell_type, + input lq_xu_dbell_brdcast, + input lq_xu_dbell_lpid_match, + input [50:63] lq_xu_dbell_pirtag, + output [50:63] cspr_tspr_dbell_pirtag, + input [0:`THREADS-1] tspr_cspr_gpir_match, + + // Parity + output [0:`THREADS-1] xu_pc_err_sprg_ecc, + output [0:`THREADS-1] xu_pc_err_sprg_ue, + input [0:`THREADS-1] pc_xu_inj_sprg_ecc, + + // Debug + input [0:`THREADS-1] tspr_cspr_freeze_timers, + input [0:3*`THREADS-1] tspr_cspr_async_int, + + input [0:`THREADS-1] tspr_cspr_ex2_np1_flush, + + output [0:`THREADS-1] xu_iu_msrovride_enab, + input lq_xu_spr_xucr0_cslc_xuop, + input lq_xu_spr_xucr0_cslc_binv, + input lq_xu_spr_xucr0_clo, + input lq_xu_spr_xucr0_cul, + output cspr_ccr2_en_pc, + output cspr_ccr4_en_dnh, + input [0:`THREADS-1] tspr_msr_ee, + input [0:`THREADS-1] tspr_msr_ce, + input [0:`THREADS-1] tspr_msr_me, + input [0:`THREADS-1] tspr_msr_gs, + input [0:`THREADS-1] tspr_msr_pr, + output [0:4] cspr_xucr0_clkg_ctl, + output xu_lsu_spr_xucr0_clfc, + output [0:31] spr_xesr1, + output [0:31] spr_xesr2, + output [0:`THREADS-1] perf_event_en, + output spr_ccr2_en_dcr, + output spr_ccr2_en_trace, + output [0:8] spr_ccr2_ifratsc, + output spr_ccr2_ifrat, + output [0:8] spr_ccr2_dfratsc, + output spr_ccr2_dfrat, + output spr_ccr2_ucode_dis, + output [0:3] spr_ccr2_ap, + output spr_ccr2_en_attn, + output spr_ccr2_en_ditc, + output spr_ccr2_en_icswx, + output spr_ccr2_notlb, + output [0:3] spr_xucr0_trace_um, + output xu_lsu_spr_xucr0_mbar_ack, + output xu_lsu_spr_xucr0_tlbsync, + output spr_xucr0_cls, + output xu_lsu_spr_xucr0_aflsta, + output spr_xucr0_mddp, + output xu_lsu_spr_xucr0_cred, + output xu_lsu_spr_xucr0_rel, + output spr_xucr0_mdcp, + output xu_lsu_spr_xucr0_flsta, + output xu_lsu_spr_xucr0_l2siw, + output xu_lsu_spr_xucr0_flh2l2, + output xu_lsu_spr_xucr0_dcdis, + output xu_lsu_spr_xucr0_wlk, + output spr_xucr4_mmu_mchk, + output spr_xucr4_mddmh, + + output [0:39] cspr_debug0, + output [0:63] cspr_debug1, + + // Power + inout vdd, + inout gnd +); + + localparam DEX0 = 0; + localparam DEX1 = 0; + localparam DEX2 = 0; + localparam DEX3 = 0; + localparam DEX4 = 0; + localparam DEX5 = 0; + localparam DEX6 = 0; + localparam DWR = 0; + localparam DX = 0; + localparam a2hvmode = ((a2mode + hvmode) % 1); + // Types + // SPR Registers + // SPR Registers + wire [62:63] ccr0_d, ccr0_q; + wire [40:63] ccr1_d, ccr1_q; + wire [32:63] ccr2_d, ccr2_q; + wire [63:63] ccr4_d, ccr4_q; + wire [32:63] tbl_d, tbl_q; + wire [32:63] tbu_d, tbu_q; + wire [64-(`THREADS):63] tens_d, tens_q; + wire [32:63] xesr1_d, xesr1_q; + wire [32:63] xesr2_d, xesr2_q; + wire [38:63] xucr0_d, xucr0_q; + wire [60:63] xucr4_d, xucr4_q; + // FUNC Scanchain + localparam ccr1_offset = 0; + localparam tbl_offset = ccr1_offset + 24; + localparam tbu_offset = tbl_offset + 32; + localparam xesr1_offset = tbu_offset + 32; + localparam xesr2_offset = xesr1_offset + 32; + localparam last_reg_offset = xesr2_offset + 32; + // BCFG Scanchain + localparam ccr0_offset_bcfg = 0; + localparam tens_offset_bcfg = ccr0_offset_bcfg + 2; + localparam last_reg_offset_bcfg = tens_offset_bcfg + `THREADS; + // CCFG Scanchain + localparam ccr2_offset_ccfg = 0; + localparam ccr4_offset_ccfg = ccr2_offset_ccfg + 32; + localparam xucr0_offset_ccfg = ccr4_offset_ccfg + 1; + localparam last_reg_offset_ccfg = xucr0_offset_ccfg + 26; + // DCFG Scanchain + localparam xucr4_offset_dcfg = 0; + localparam last_reg_offset_dcfg = xucr4_offset_dcfg + 4; + // Latches + wire [1:4] exx_act_q, exx_act_d ; // input=>exx_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex0_val_q, rv2_val ; // input=>rv2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex1_val_q, ex0_val ; // input=>ex0_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex1_aspr_act_q, ex1_aspr_act_d ; // input=>ex1_aspr_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex1_aspr_tid_q, ex1_aspr_tid_d ; // input=>ex1_aspr_tid_d , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex1_tid_q, ex0_tid ; // input=>ex0_tid , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:31] ex1_instr_q ; // input=>rv_xu_ex0_instr , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:0] ex1_msr_gs_q, ex1_msr_gs_d ; // input=>ex1_msr_gs_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex2_val_q, ex1_val ; // input=>ex1_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_val_rd_q, ex2_val_rd_d ; // input=>ex2_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_val_wr_q, ex2_val_wr_d ; // input=>ex2_val_wr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex2_tid_q ; // input=>ex1_tid_q , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex2_aspr_addr_q, ex1_aspr_addr ; // input=>ex1_aspr_addr , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mfspr_q, ex1_is_mfspr ; // input=>ex1_is_mfspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mftb_q, ex1_is_mftb ; // input=>ex1_is_mftb , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtmsr_q, ex2_is_mtmsr_d ; // input=>ex1_is_mtmsr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_mtspr_q, ex1_is_mtspr ; // input=>ex1_is_mtspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_wait_q, ex1_is_wait ; // input=>ex1_is_wait , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_priv_instr_q, ex1_priv_instr ; // input=>ex1_priv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_hypv_instr_q, ex1_hypv_instr ; // input=>ex1_hypv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [9:10] ex2_wait_wc_q ; // input=>ex1_instr_q[9:10] , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_is_msgclr_q, ex1_is_msgclr ; // input=>ex1_is_msgclr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [11:20] ex2_instr_q, ex2_instr_d ; // input=>ex2_instr_d , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:0] ex2_msr_gs_q ; // input=>ex1_msr_gs_q , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_tenc_we_q, ex1_tenc_we ; // input=>ex1_tenc_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_ccr0_we_q, ex1_ccr0_we ; // input=>ex1_ccr0_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex2_aspr_re_q, ex1_aspr_re /*verilator split_var*/ ; // input=>ex1_aspr_re , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex2_dnh_q, ex1_dnh ; // input=>ex1_dnh , act=>exx_act[1] + wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_val_rd_q, ex3_val_rd_d ; // input=>ex3_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_sspr_wr_val_q, ex2_sspr_wr_val ; // input=>ex2_sspr_wr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_sspr_rd_val_q, ex2_sspr_rd_val ; // input=>ex2_sspr_rd_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_spr_we_q, ex3_spr_we_d ; // input=>ex3_spr_we_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_aspr_we_q, ex3_aspr_we_d ; // input=>ex3_aspr_we_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex3_aspr_addr_q, ex3_aspr_addr_d ; // input=>ex3_aspr_addr_d , act=>ex2_aspr_addr_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] ex3_tid_q ; // input=>ex2_tid_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex3_aspr_rdata_q, ex3_aspr_rdata_d ; // input=>ex3_aspr_rdata_d , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 + wire ex3_is_mtspr_q ; // input=>ex2_is_mtspr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [9:10] ex3_wait_wc_q ; // input=>ex2_wait_wc_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_is_msgclr_q ; // input=>ex2_is_msgclr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [11:20] ex3_instr_q, ex3_instr_d ; // input=>ex3_instr_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex3_cspr_rt_q, ex2_cspr_rt ; // input=>ex2_cspr_rt , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_hypv_spr_q, ex3_hypv_spr_d ; // input=>ex3_hypv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_illeg_spr_q, ex3_illeg_spr_d ; // input=>ex3_illeg_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex3_priv_spr_q, ex3_priv_spr_d ; // input=>ex3_priv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_rt_q, ex3_rt_d ; // input=>ex3_rt_d , act=>ex3_rt_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 + wire ex3_wait_q ; // input=>ex2_is_wait_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex3_aspr_ce_addr_q ; // input=>ex2_aspr_addr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex3_aspr_re_q ; // input=>ex2_aspr_re_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex4_val_q ; // input=>ex3_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [2-`GPR_WIDTH/32:1] ex4_aspr_re_q ; // input=>ex3_aspr_re_q , act=>exx_act[3] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex4_spr_rt_q, ex3_spr_rt ; // input=>ex3_spr_rt , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [64-`GPR_WIDTH:63] ex4_corr_rdata_q, ex3_corr_rdata ; // input=>ex3_corr_rdata , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`GPR_WIDTH/8] ex4_sprg_ce_q, ex4_sprg_ce_d ; // input=>ex4_sprg_ce_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:3] ex4_aspr_ce_addr_q ; // input=>ex3_aspr_ce_addr_q , act=>ex3_sprg_ce , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_hypv_spr_q ; // input=>ex3_hypv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_illeg_spr_q ; // input=>ex3_illeg_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_priv_spr_q ; // input=>ex3_priv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_np1_flush_q, ex4_np1_flush_d ; // input=>ex4_np1_flush_d , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex5_sprg_ce_q, ex4_sprg_ce ; // input=>ex4_sprg_ce , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_sprg_ue_q, ex4_sprg_ue_d ; // input=>ex4_sprg_ue_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ex5_sprg_ue_q, ex4_sprg_ue ; // input=>ex4_sprg_ue , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_dbell_taken_q ; // input=>iu_xu_dbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_cdbell_taken_q ; // input=>iu_xu_cdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gdbell_taken_q ; // input=>iu_xu_gdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gcdbell_taken_q ; // input=>iu_xu_gcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cpl_gmcdbell_taken_q ; // input=>iu_xu_gmcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire set_xucr0_cslc_q, set_xucr0_cslc_d ; // input=>set_xucr0_cslc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire set_xucr0_cul_q, set_xucr0_cul_d ; // input=>set_xucr0_cul_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire set_xucr0_clo_q, set_xucr0_clo_d ; // input=>set_xucr0_clo_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire ex3_np1_flush_q, ex3_np1_flush_d ; // input=>ex3_np1_flush_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] running_q, running_d ; // input=>running_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] llpri_q, llpri_d ; // input=>llpri_d , act=>llpri_inc , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1, init=>2**(``THREADS-1) + wire [0:`THREADS-1] dec_dbg_dis_q, dec_dbg_dis_d ; // input=>dec_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_dbg_dis_q, tb_dbg_dis_d ; // input=>tb_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_act_q, tb_act_d ; // input=>tb_act_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] ext_dbg_dis_q, ext_dbg_dis_d ; // input=>ext_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire msrovride_enab_q ; // input=>pc_xu_msrovride_enab , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] waitimpl_val_q, waitimpl_val_d ; // input=>waitimpl_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] waitrsv_val_q, waitrsv_val_d ; // input=>waitrsv_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] an_ac_reservation_vld_q ; // input=>an_ac_reservation_vld , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] an_ac_sleep_en_q ; // input=>an_ac_sleep_en , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [54:61] an_ac_coreid_q ; // input=>an_ac_coreid , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_enable_q ; // input=>an_ac_tb_update_enable , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_pulse_q ; // input=>an_ac_tb_update_pulse , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire tb_update_pulse_1_q ; // input=>tb_update_pulse_q , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_wd_complete_q ; // input=>pc_xu_reset_wd_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_3_complete_q ; // input=>pc_xu_reset_3_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_2_complete_q ; // input=>pc_xu_reset_2_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire pc_xu_reset_1_complete_q ; // input=>pc_xu_reset_1_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_val_q ; // input=>lq_xu_dbell_val , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:4] lq_xu_dbell_type_q ; // input=>lq_xu_dbell_type , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_brdcast_q ; // input=>lq_xu_dbell_brdcast , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire lq_xu_dbell_lpid_match_q ; // input=>lq_xu_dbell_lpid_match , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [50:63] lq_xu_dbell_pirtag_q ; // input=>lq_xu_dbell_pirtag , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] dbell_present_q, dbell_present_d ; // input=>dbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cdbell_present_q, cdbell_present_d ; // input=>cdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gdbell_present_q, gdbell_present_d ; // input=>gdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gcdbell_present_q, gcdbell_present_d ; // input=>gcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gmcdbell_present_q, gmcdbell_present_d ; // input=>gmcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire xucr0_clfc_q, xucr0_clfc_d ; // input=>xucr0_clfc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_run_thread_q, iu_run_thread_d ; // input=>iu_run_thread_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] inj_sprg_ecc_q ; // input=>pc_xu_inj_sprg_ecc , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] dbell_interrupt_q, dbell_interrupt ; // input=>dbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] cdbell_interrupt_q, cdbell_interrupt ; // input=>cdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gdbell_interrupt_q, gdbell_interrupt ; // input=>gdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gcdbell_interrupt_q, gcdbell_interrupt ; // input=>gcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] gmcdbell_interrupt_q, gmcdbell_interrupt ; // input=>gmcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_quiesce_q ; // input=>iu_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] iu_icache_quiesce_q ; // input=>iu_xu_icache_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] lsu_quiesce_q ; // input=>lq_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] mm_quiesce_q ; // input=>mm_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] bx_quiesce_q ; // input=>bx_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] quiesce_q, quiesce_d ; // input=>quiesce_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] quiesced_q, quiesced_d ; // input=>quiesced_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire instr_trace_mode_q ; // input=>pc_xu_instr_trace_mode , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:1] instr_trace_tid_q ; // input=>pc_xu_instr_trace_tid , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire timer_update_q ; // input=>timer_update_int , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire spr_xu_ord_read_done_q, spr_xu_ord_read_done_d ; // input=>spr_xu_ord_read_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire spr_xu_ord_write_done_q, spr_xu_ord_write_done_d ; // input=>spr_xu_ord_write_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire xu_spr_ord_ready_q ; // input=>xu_spr_ord_ready , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_sspr_val_q ; // input=>ex3_sspr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] flush_q ; // input=>flush , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire [62-`EFF_IFAR_WIDTH:61] ex1_ifar_q ; // input=>rv_xu_ex0_ifar , act=>exx_act[0] , scan=>Y, sleep=>N, needs_sreset=>1 + wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar_q ; // input=>ex1_ifar_q , act=>exx_act[1] , scan=>Y, sleep=>N, needs_sreset=>1 + wire [0:`THREADS-1] ram_active_q ; // input=>pc_xu_ram_active , act=>1'b1 + wire [0:4] timer_div_q, timer_div_d ; // input=>timer_div_d , act=>timer_div_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] msrovride_enab_2_q, msrovride_enab ; // input=>msrovride_enab , act=>1'b1 + wire [0:`THREADS-1] msrovride_enab_3_q ; // input=>msrovride_enab_2_q , act=>1'b1 + wire ex3_wait_flush_q, ex3_wait_flush_d ; // input=>ex3_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire ex4_wait_flush_q, ex4_wait_flush_d ; // input=>ex4_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 + wire pc_xu_pm_hold_thread_q ; // input=>pc_xu_pm_hold_thread , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire power_savings_on_q, power_savings_on_d ; // input=>power_savings_on_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:4*`THREADS-1] perf_event_bus_q, perf_event_bus_d ; // input=>perf_event_bus_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:`THREADS-1] perf_event_en_q, perf_event_en_d ; // input=>perf_event_en_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 + wire [0:15] spare_0_q, spare_0_d ; // input=>spare_0_d , act=>1'b1 , + // Scanchains + localparam exx_act_offset = last_reg_offset; + localparam ex0_val_offset = exx_act_offset + 4; + localparam ex1_val_offset = ex0_val_offset + `THREADS; + localparam ex1_aspr_act_offset = ex1_val_offset + `THREADS; + localparam ex1_aspr_tid_offset = ex1_aspr_act_offset + 1; + localparam ex1_tid_offset = ex1_aspr_tid_offset + 2; + localparam ex1_instr_offset = ex1_tid_offset + 2; + localparam ex1_msr_gs_offset = ex1_instr_offset + 32; + localparam ex2_val_offset = ex1_msr_gs_offset + 1; + localparam ex2_val_rd_offset = ex2_val_offset + `THREADS; + localparam ex2_val_wr_offset = ex2_val_rd_offset + 1; + localparam ex2_tid_offset = ex2_val_wr_offset + 1; + localparam ex2_aspr_addr_offset = ex2_tid_offset + 2; + localparam ex2_is_mfspr_offset = ex2_aspr_addr_offset + 4; + localparam ex2_is_mftb_offset = ex2_is_mfspr_offset + 1; + localparam ex2_is_mtmsr_offset = ex2_is_mftb_offset + 1; + localparam ex2_is_mtspr_offset = ex2_is_mtmsr_offset + 1; + localparam ex2_is_wait_offset = ex2_is_mtspr_offset + 1; + localparam ex2_priv_instr_offset = ex2_is_wait_offset + 1; + localparam ex2_hypv_instr_offset = ex2_priv_instr_offset + 1; + localparam ex2_wait_wc_offset = ex2_hypv_instr_offset + 1; + localparam ex2_is_msgclr_offset = ex2_wait_wc_offset + 2; + localparam ex2_instr_offset = ex2_is_msgclr_offset + 1; + localparam ex2_msr_gs_offset = ex2_instr_offset + 10; + localparam ex2_tenc_we_offset = ex2_msr_gs_offset + 1; + localparam ex2_ccr0_we_offset = ex2_tenc_we_offset + 1; + localparam ex2_aspr_re_offset = ex2_ccr0_we_offset + 1; + localparam ex2_dnh_offset = ex2_aspr_re_offset + `GPR_WIDTH/32; + localparam ex3_val_offset = ex2_dnh_offset + 1; + localparam ex3_val_rd_offset = ex3_val_offset + `THREADS; + localparam ex3_sspr_wr_val_offset = ex3_val_rd_offset + 1; + localparam ex3_sspr_rd_val_offset = ex3_sspr_wr_val_offset + 1; + localparam ex3_spr_we_offset = ex3_sspr_rd_val_offset + 1; + localparam ex3_aspr_we_offset = ex3_spr_we_offset + 1; + localparam ex3_aspr_addr_offset = ex3_aspr_we_offset + 1; + localparam ex3_tid_offset = ex3_aspr_addr_offset + 4; + localparam ex3_aspr_rdata_offset = ex3_tid_offset + 2; + localparam ex3_is_mtspr_offset = ex3_aspr_rdata_offset + `GPR_WIDTH+8; + localparam ex3_wait_wc_offset = ex3_is_mtspr_offset + 1; + localparam ex3_is_msgclr_offset = ex3_wait_wc_offset + 2; + localparam ex3_instr_offset = ex3_is_msgclr_offset + 1; + localparam ex3_cspr_rt_offset = ex3_instr_offset + 10; + localparam ex3_hypv_spr_offset = ex3_cspr_rt_offset + `GPR_WIDTH; + localparam ex3_illeg_spr_offset = ex3_hypv_spr_offset + 1; + localparam ex3_priv_spr_offset = ex3_illeg_spr_offset + 1; + localparam ex3_rt_offset = ex3_priv_spr_offset + 1; + localparam ex3_wait_offset = ex3_rt_offset + `GPR_WIDTH+8; + localparam ex3_aspr_ce_addr_offset = ex3_wait_offset + 1; + localparam ex3_aspr_re_offset = ex3_aspr_ce_addr_offset + 4; + localparam ex4_val_offset = ex3_aspr_re_offset + `GPR_WIDTH/32; + localparam ex4_aspr_re_offset = ex4_val_offset + `THREADS; + localparam ex4_spr_rt_offset = ex4_aspr_re_offset + `GPR_WIDTH/32; + localparam ex4_corr_rdata_offset = ex4_spr_rt_offset + `GPR_WIDTH; + localparam ex4_sprg_ce_offset = ex4_corr_rdata_offset + `GPR_WIDTH; + localparam ex4_aspr_ce_addr_offset = ex4_sprg_ce_offset + `GPR_WIDTH/8+1; + localparam ex4_hypv_spr_offset = ex4_aspr_ce_addr_offset + 4; + localparam ex4_illeg_spr_offset = ex4_hypv_spr_offset + 1; + localparam ex4_priv_spr_offset = ex4_illeg_spr_offset + 1; + localparam ex4_np1_flush_offset = ex4_priv_spr_offset + 1; + localparam ex5_sprg_ce_offset = ex4_np1_flush_offset + 1; + localparam ex4_sprg_ue_offset = ex5_sprg_ce_offset + `THREADS; + localparam ex5_sprg_ue_offset = ex4_sprg_ue_offset + 1; + localparam cpl_dbell_taken_offset = ex5_sprg_ue_offset + `THREADS; + localparam cpl_cdbell_taken_offset = cpl_dbell_taken_offset + `THREADS; + localparam cpl_gdbell_taken_offset = cpl_cdbell_taken_offset + `THREADS; + localparam cpl_gcdbell_taken_offset = cpl_gdbell_taken_offset + `THREADS; + localparam cpl_gmcdbell_taken_offset = cpl_gcdbell_taken_offset + `THREADS; + localparam set_xucr0_cslc_offset = cpl_gmcdbell_taken_offset + `THREADS; + localparam set_xucr0_cul_offset = set_xucr0_cslc_offset + 1; + localparam set_xucr0_clo_offset = set_xucr0_cul_offset + 1; + localparam ex3_np1_flush_offset = set_xucr0_clo_offset + 1; + localparam running_offset = ex3_np1_flush_offset + 1; + localparam llpri_offset = running_offset + `THREADS; + localparam dec_dbg_dis_offset = llpri_offset + `THREADS; + localparam tb_dbg_dis_offset = dec_dbg_dis_offset + `THREADS; + localparam tb_act_offset = tb_dbg_dis_offset + 1; + localparam ext_dbg_dis_offset = tb_act_offset + 1; + localparam msrovride_enab_offset = ext_dbg_dis_offset + `THREADS; + localparam waitimpl_val_offset = msrovride_enab_offset + 1; + localparam waitrsv_val_offset = waitimpl_val_offset + `THREADS; + localparam an_ac_reservation_vld_offset = waitrsv_val_offset + `THREADS; + localparam an_ac_sleep_en_offset = an_ac_reservation_vld_offset + `THREADS; + localparam an_ac_coreid_offset = an_ac_sleep_en_offset + `THREADS; + localparam tb_update_enable_offset = an_ac_coreid_offset + 8; + localparam tb_update_pulse_offset = tb_update_enable_offset + 1; + localparam tb_update_pulse_1_offset = tb_update_pulse_offset + 1; + localparam pc_xu_reset_wd_complete_offset = tb_update_pulse_1_offset + 1; + localparam pc_xu_reset_3_complete_offset = pc_xu_reset_wd_complete_offset + 1; + localparam pc_xu_reset_2_complete_offset = pc_xu_reset_3_complete_offset + 1; + localparam pc_xu_reset_1_complete_offset = pc_xu_reset_2_complete_offset + 1; + localparam lq_xu_dbell_val_offset = pc_xu_reset_1_complete_offset + 1; + localparam lq_xu_dbell_type_offset = lq_xu_dbell_val_offset + 1; + localparam lq_xu_dbell_brdcast_offset = lq_xu_dbell_type_offset + 5; + localparam lq_xu_dbell_lpid_match_offset = lq_xu_dbell_brdcast_offset + 1; + localparam lq_xu_dbell_pirtag_offset = lq_xu_dbell_lpid_match_offset + 1; + localparam dbell_present_offset = lq_xu_dbell_pirtag_offset + 14; + localparam cdbell_present_offset = dbell_present_offset + `THREADS; + localparam gdbell_present_offset = cdbell_present_offset + `THREADS; + localparam gcdbell_present_offset = gdbell_present_offset + `THREADS; + localparam gmcdbell_present_offset = gcdbell_present_offset + `THREADS; + localparam xucr0_clfc_offset = gmcdbell_present_offset + `THREADS; + localparam iu_run_thread_offset = xucr0_clfc_offset + 1; + localparam inj_sprg_ecc_offset = iu_run_thread_offset + `THREADS; + localparam dbell_interrupt_offset = inj_sprg_ecc_offset + `THREADS; + localparam cdbell_interrupt_offset = dbell_interrupt_offset + `THREADS; + localparam gdbell_interrupt_offset = cdbell_interrupt_offset + `THREADS; + localparam gcdbell_interrupt_offset = gdbell_interrupt_offset + `THREADS; + localparam gmcdbell_interrupt_offset = gcdbell_interrupt_offset + `THREADS; + localparam iu_quiesce_offset = gmcdbell_interrupt_offset + `THREADS; + localparam iu_icache_quiesce_offset = iu_quiesce_offset + `THREADS; + localparam lsu_quiesce_offset = iu_icache_quiesce_offset + `THREADS; + localparam mm_quiesce_offset = lsu_quiesce_offset + `THREADS; + localparam bx_quiesce_offset = mm_quiesce_offset + `THREADS; + localparam quiesce_offset = bx_quiesce_offset + `THREADS; + localparam quiesced_offset = quiesce_offset + `THREADS; + localparam instr_trace_mode_offset = quiesced_offset + `THREADS; + localparam instr_trace_tid_offset = instr_trace_mode_offset + 1; + localparam timer_update_offset = instr_trace_tid_offset + 2; + localparam spr_xu_ord_read_done_offset = timer_update_offset + 1; + localparam spr_xu_ord_write_done_offset = spr_xu_ord_read_done_offset + 1; + localparam xu_spr_ord_ready_offset = spr_xu_ord_write_done_offset + 1; + localparam ex4_sspr_val_offset = xu_spr_ord_ready_offset + 1; + localparam flush_offset = ex4_sspr_val_offset + 1; + localparam ex1_ifar_offset = flush_offset + `THREADS; + localparam ex2_ifar_offset = ex1_ifar_offset + `EFF_IFAR_WIDTH; + localparam ram_active_offset = ex2_ifar_offset + `EFF_IFAR_WIDTH; + localparam timer_div_offset = ram_active_offset + `THREADS; + localparam msrovride_enab_2_offset = timer_div_offset + 5; + localparam msrovride_enab_3_offset = msrovride_enab_2_offset + `THREADS; + localparam ex3_wait_flush_offset = msrovride_enab_3_offset + `THREADS; + localparam ex4_wait_flush_offset = ex3_wait_flush_offset + 1; + localparam pc_xu_pm_hold_thread_offset = ex4_wait_flush_offset + 1; + localparam power_savings_on_offset = pc_xu_pm_hold_thread_offset + 1; + localparam perf_event_bus_offset = power_savings_on_offset + 1; + localparam perf_event_en_offset = perf_event_bus_offset + 4*`THREADS; + localparam spare_0_offset = perf_event_en_offset + `THREADS; + localparam quiesced_ctr_offset = spare_0_offset + 16; + localparam scan_right = quiesced_ctr_offset + 1; + wire [0:scan_right-1] siv; + wire [0:scan_right-1] sov; + + + wire [0:`THREADS-1] ccr0_we_q, ccr0_we_d ; // input=>ccr0_we_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>bcfg, needs_sreset=>1 + localparam ccr0_we_offset_bcfg = last_reg_offset_bcfg; + localparam scan_right_bcfg = ccr0_we_offset_bcfg + `THREADS; + wire [0:scan_right_bcfg-1] siv_bcfg; + wire [0:scan_right_bcfg-1] sov_bcfg; + localparam scan_right_ccfg = last_reg_offset_ccfg; + wire [0:scan_right_ccfg-1] siv_ccfg; + wire [0:scan_right_ccfg-1] sov_ccfg; + localparam scan_right_dcfg = last_reg_offset_dcfg; + wire [0:scan_right_dcfg-1] siv_dcfg; + wire [0:scan_right_dcfg-1] sov_dcfg; + // Signals + wire [00:63] tidn; + wire [0:`NCLK_WIDTH-1] spare_0_lclk; + wire spare_0_d1clk; + wire spare_0_d2clk; + wire [00:63] tb; + wire ex1_opcode_is_31; + wire ex1_opcode_is_19; + wire ex1_is_mfcr; + wire ex1_is_mtcrf; + wire ex1_is_dnh; + wire ex1_is_mfmsr; + wire ex1_is_mtmsr; + wire ex3_sspr_val; + wire [0:`THREADS-1] ex2_tid; + wire ex2_illeg_mfspr; + wire ex2_illeg_mtspr; + wire ex2_illeg_mftb; + wire ex2_hypv_mfspr; + wire ex2_hypv_mtspr; + wire [11:20] ex1_instr; + wire [11:20] ex2_instr; + wire [11:20] ex3_instr; + wire ex2_slowspr_range_priv; + wire ex2_slowspr_range_hypv; + wire ex2_slowspr_range; + wire [0:`THREADS-1] ex2_wait_flush; + wire [0:`THREADS-1] ex2_ccr0_flush; + wire [0:`THREADS-1] ex2_tenc_flush; + wire [0:`THREADS-1] ex2_xucr0_flush; + wire [64-`GPR_WIDTH:63] ex3_tspr_rt; + wire [64-`GPR_WIDTH:63] ex3_cspr_rt; + wire [0:`THREADS-1] ex3_tid; + wire [64-`GPR_WIDTH:63] ex2_rt; + wire [64-`GPR_WIDTH:63] ex2_rt_inj; + wire llunmasked; + wire llmasked; + wire llpulse; + wire llpres; + wire llpri_inc; + wire [0:`THREADS-1] llmask; + wire [0:`THREADS-1] pm_wake_up; + wire [0:3] ccr0_we; + wire [0:`THREADS-1] ccr0_wen, ccr0_we_di; + wire dbell_pir_match; + wire [0:`THREADS-1] dbell_pir_thread; + wire [0:`THREADS-1] spr_ccr0_we_rev; + wire [0:`THREADS-1] spr_tens_ten_rev; + wire [0:`THREADS-1] set_dbell; + wire [0:`THREADS-1] clr_dbell; + wire [0:`THREADS-1] set_cdbell; + wire [0:`THREADS-1] clr_cdbell; + wire [0:`THREADS-1] set_gdbell; + wire [0:`THREADS-1] clr_gdbell; + wire [0:`THREADS-1] set_gcdbell; + wire [0:`THREADS-1] clr_gcdbell; + wire [0:`THREADS-1] set_gmcdbell; + wire [0:`THREADS-1] clr_gmcdbell; + wire tb_update_pulse; + wire [0:`THREADS-1] spr_tensr; + wire ex3_is_mtspr; + wire [0:63] tb_q; + wire [0:`THREADS-1] crit_mask; + wire [0:`THREADS-1] base_mask; + wire [0:`THREADS-1] dec_mask; + wire [0:`THREADS-1] fit_mask; + wire [0:`THREADS-1] ex3_wait; + wire [38:63] xucr0_di; + wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex2_eccgen_data; + wire [64:72-(64/`GPR_WIDTH)] ex2_eccgen_syn; + wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn; + wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn_b; + wire ex2_is_mfsspr_b; + wire encorr; + wire ex3_sprg_ce, ex3_sprg_ue; + wire ex2_aspr_we; + wire [64-`GPR_WIDTH:63] ex4_aspr_rt; + wire [0:`THREADS-1] quiesce_ctr_zero_b; + wire [0:`THREADS-1] quiesce_b_q; + wire [0:`THREADS-1] running; + wire timer_update_int; + wire [0:4] exx_act; + wire [1:3] exx_act_data; + wire ex0_act; + wire ex2_inj_ecc; + wire [32:47] version; + wire [48:63] revision; + wire [0:`THREADS-1] instr_trace_tid; + wire [0:`THREADS-1] ex3_val; + wire [0:3] ex2_aspr_addr; + wire ex1_spr_rd; + wire ex1_spr_wr; + wire flush_int; + wire ex2_flush; + wire ex3_flush; + wire ex1_valid; + wire ex1_is_wrtee; + wire ex1_is_wrteei; + wire ord_ready; + wire ex2_msr_pr; + wire ex2_msr_gs; + wire timer_div_act; + wire [0:4] timer_div; + wire ex3_spr_we; + wire ex2_aspr_addr_act; + wire ex3_rt_act; + wire [0:`THREADS-1] ex2_np1_flush; + wire power_savings_en, power_savings_on; + (* analysis_not_referenced="true" *) + wire unused_do_bits; + + // Data + wire [0:1] spr_ccr0_pme; + wire [0:3] spr_ccr0_we; + wire spr_ccr2_en_dcr_int; + wire spr_ccr2_en_pc; + wire spr_ccr4_en_dnh; + wire [0:`THREADS-1] spr_tens_ten; + wire [0:4] spr_xucr0_clkg_ctl; + wire spr_xucr0_tcs; + wire [0:1] spr_xucr4_tcd; + wire [62:63] ex3_ccr0_di; + wire [40:63] ex3_ccr1_di; + wire [32:63] ex3_ccr2_di; + wire [63:63] ex3_ccr4_di; + wire [32:63] ex3_tbl_di; + wire [32:63] ex3_tbu_di; + wire [64-(`THREADS):63] ex3_tens_di; + wire [32:63] ex3_xesr1_di; + wire [32:63] ex3_xesr2_di; + wire [38:63] ex3_xucr0_di; + wire [60:63] ex3_xucr4_di; + wire + ex1_gsprg0_re , ex1_gsprg1_re , ex1_gsprg2_re , ex1_gsprg3_re + , ex1_sprg0_re , ex1_sprg1_re , ex1_sprg2_re , ex1_sprg3_re + , ex1_sprg4_re , ex1_sprg5_re , ex1_sprg6_re , ex1_sprg7_re + , ex1_sprg8_re , ex1_vrsave_re ; + wire + ex1_gsprg0_rdec, ex1_gsprg1_rdec, ex1_gsprg2_rdec, ex1_gsprg3_rdec + , ex1_sprg0_rdec , ex1_sprg1_rdec , ex1_sprg2_rdec , ex1_sprg3_rdec + , ex1_sprg4_rdec , ex1_sprg5_rdec , ex1_sprg6_rdec , ex1_sprg7_rdec + , ex1_sprg8_rdec , ex1_vrsave_rdec; + wire ex2_sprg8_re; + wire + ex2_ccr0_re , ex2_ccr1_re , ex2_ccr2_re , ex2_ccr4_re + , ex2_cir_re , ex2_pir_re , ex2_pvr_re , ex2_tb_re + , ex2_tbu_re , ex2_tenc_re , ex2_tens_re , ex2_tensr_re + , ex2_tir_re , ex2_xesr1_re , ex2_xesr2_re , ex2_xucr0_re + , ex2_xucr4_re ; + wire + ex2_acop_re , ex2_axucr0_re , ex2_cpcr0_re , ex2_cpcr1_re + , ex2_cpcr2_re , ex2_cpcr3_re , ex2_cpcr4_re , ex2_cpcr5_re + , ex2_dac1_re , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re + , ex2_dbcr2_re , ex2_dbcr3_re , ex2_dscr_re , ex2_dvc1_re + , ex2_dvc2_re , ex2_eheir_re , ex2_eplc_re , ex2_epsc_re + , ex2_eptcfg_re , ex2_givpr_re , ex2_hacop_re , ex2_iac1_re + , ex2_iac2_re , ex2_iac3_re , ex2_iac4_re , ex2_immr_re + , ex2_imr_re , ex2_iucr0_re , ex2_iucr1_re , ex2_iucr2_re + , ex2_iudbg0_re , ex2_iudbg1_re , ex2_iudbg2_re , ex2_iulfsr_re + , ex2_iullcr_re , ex2_ivpr_re , ex2_lesr1_re , ex2_lesr2_re + , ex2_lper_re , ex2_lperu_re , ex2_lpidr_re , ex2_lratcfg_re + , ex2_lratps_re , ex2_lsucr0_re , ex2_mas0_re , ex2_mas0_mas1_re + , ex2_mas1_re , ex2_mas2_re , ex2_mas2u_re , ex2_mas3_re + , ex2_mas4_re , ex2_mas5_re , ex2_mas5_mas6_re, ex2_mas6_re + , ex2_mas7_re , ex2_mas7_mas3_re, ex2_mas8_re , ex2_mas8_mas1_re + , ex2_mmucfg_re , ex2_mmucr0_re , ex2_mmucr1_re , ex2_mmucr2_re + , ex2_mmucr3_re , ex2_mmucsr0_re , ex2_pesr_re , ex2_pid_re + , ex2_ppr32_re , ex2_sramd_re , ex2_tlb0cfg_re , ex2_tlb0ps_re + , ex2_xucr2_re , ex2_xudbg0_re , ex2_xudbg1_re , ex2_xudbg2_re ; + wire + ex2_ccr0_we , ex2_ccr1_we , ex2_ccr2_we , ex2_ccr4_we + , ex2_tbl_we , ex2_tbu_we , ex2_tenc_we , ex2_tens_we + , ex2_trace_we , ex2_xesr1_we , ex2_xesr2_we , ex2_xucr0_we + , ex2_xucr4_we ; + wire + ex2_acop_we , ex2_axucr0_we , ex2_cpcr0_we , ex2_cpcr1_we + , ex2_cpcr2_we , ex2_cpcr3_we , ex2_cpcr4_we , ex2_cpcr5_we + , ex2_dac1_we , ex2_dac2_we , ex2_dac3_we , ex2_dac4_we + , ex2_dbcr2_we , ex2_dbcr3_we , ex2_dscr_we , ex2_dvc1_we + , ex2_dvc2_we , ex2_eheir_we , ex2_eplc_we , ex2_epsc_we + , ex2_givpr_we , ex2_hacop_we , ex2_iac1_we , ex2_iac2_we + , ex2_iac3_we , ex2_iac4_we , ex2_immr_we , ex2_imr_we + , ex2_iucr0_we , ex2_iucr1_we , ex2_iucr2_we , ex2_iudbg0_we + , ex2_iulfsr_we , ex2_iullcr_we , ex2_ivpr_we , ex2_lesr1_we + , ex2_lesr2_we , ex2_lper_we , ex2_lperu_we , ex2_lpidr_we + , ex2_lsucr0_we , ex2_mas0_we , ex2_mas0_mas1_we, ex2_mas1_we + , ex2_mas2_we , ex2_mas2u_we , ex2_mas3_we , ex2_mas4_we + , ex2_mas5_we , ex2_mas5_mas6_we, ex2_mas6_we , ex2_mas7_we + , ex2_mas7_mas3_we, ex2_mas8_we , ex2_mas8_mas1_we, ex2_mmucr0_we + , ex2_mmucr1_we , ex2_mmucr2_we , ex2_mmucr3_we , ex2_mmucsr0_we + , ex2_pesr_we , ex2_pid_we , ex2_ppr32_we , ex2_xucr2_we + , ex2_xudbg0_we ; + wire + ex2_gsprg0_we , ex2_gsprg1_we , ex2_gsprg2_we , ex2_gsprg3_we + , ex2_sprg0_we , ex2_sprg1_we , ex2_sprg2_we , ex2_sprg3_we + , ex2_sprg4_we , ex2_sprg5_we , ex2_sprg6_we , ex2_sprg7_we + , ex2_sprg8_we , ex2_vrsave_we ; + wire + ex2_ccr0_rdec , ex2_ccr1_rdec , ex2_ccr2_rdec , ex2_ccr4_rdec + , ex2_cir_rdec , ex2_pir_rdec , ex2_pvr_rdec , ex2_tb_rdec + , ex2_tbu_rdec , ex2_tenc_rdec , ex2_tens_rdec , ex2_tensr_rdec + , ex2_tir_rdec , ex2_xesr1_rdec , ex2_xesr2_rdec , ex2_xucr0_rdec + , ex2_xucr4_rdec ; + wire + ex2_acop_rdec , ex2_axucr0_rdec, ex2_cpcr0_rdec , ex2_cpcr1_rdec + , ex2_cpcr2_rdec , ex2_cpcr3_rdec , ex2_cpcr4_rdec , ex2_cpcr5_rdec + , ex2_dac1_rdec , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec + , ex2_dbcr2_rdec , ex2_dbcr3_rdec , ex2_dscr_rdec , ex2_dvc1_rdec + , ex2_dvc2_rdec , ex2_eheir_rdec , ex2_eplc_rdec , ex2_epsc_rdec + , ex2_eptcfg_rdec, ex2_givpr_rdec , ex2_hacop_rdec , ex2_iac1_rdec + , ex2_iac2_rdec , ex2_iac3_rdec , ex2_iac4_rdec , ex2_immr_rdec + , ex2_imr_rdec , ex2_iucr0_rdec , ex2_iucr1_rdec , ex2_iucr2_rdec + , ex2_iudbg0_rdec, ex2_iudbg1_rdec, ex2_iudbg2_rdec, ex2_iulfsr_rdec + , ex2_iullcr_rdec, ex2_ivpr_rdec , ex2_lesr1_rdec , ex2_lesr2_rdec + , ex2_lper_rdec , ex2_lperu_rdec , ex2_lpidr_rdec , ex2_lratcfg_rdec + , ex2_lratps_rdec, ex2_lsucr0_rdec, ex2_mas0_rdec , ex2_mas0_mas1_rdec + , ex2_mas1_rdec , ex2_mas2_rdec , ex2_mas2u_rdec , ex2_mas3_rdec + , ex2_mas4_rdec , ex2_mas5_rdec , ex2_mas5_mas6_rdec, ex2_mas6_rdec + , ex2_mas7_rdec , ex2_mas7_mas3_rdec, ex2_mas8_rdec , ex2_mas8_mas1_rdec + , ex2_mmucfg_rdec, ex2_mmucr0_rdec, ex2_mmucr1_rdec, ex2_mmucr2_rdec + , ex2_mmucr3_rdec, ex2_mmucsr0_rdec, ex2_pesr_rdec , ex2_pid_rdec + , ex2_ppr32_rdec , ex2_sramd_rdec , ex2_tlb0cfg_rdec, ex2_tlb0ps_rdec + , ex2_xucr2_rdec , ex2_xudbg0_rdec, ex2_xudbg1_rdec, ex2_xudbg2_rdec; + wire + ex2_gsprg0_rdec, ex2_gsprg1_rdec, ex2_gsprg2_rdec, ex2_gsprg3_rdec + , ex2_sprg0_rdec , ex2_sprg1_rdec , ex2_sprg2_rdec , ex2_sprg3_rdec + , ex2_sprg4_rdec , ex2_sprg5_rdec , ex2_sprg6_rdec , ex2_sprg7_rdec + , ex2_sprg8_rdec , ex2_vrsave_rdec; + wire + ex2_ccr0_wdec , ex2_ccr1_wdec , ex2_ccr2_wdec , ex2_ccr4_wdec + , ex2_tbl_wdec , ex2_tbu_wdec , ex2_tenc_wdec , ex2_tens_wdec + , ex2_trace_wdec , ex2_xesr1_wdec , ex2_xesr2_wdec , ex2_xucr0_wdec + , ex2_xucr4_wdec ; + wire + ex2_gsprg0_wdec, ex2_gsprg1_wdec, ex2_gsprg2_wdec, ex2_gsprg3_wdec + , ex2_sprg0_wdec , ex2_sprg1_wdec , ex2_sprg2_wdec , ex2_sprg3_wdec + , ex2_sprg4_wdec , ex2_sprg5_wdec , ex2_sprg6_wdec , ex2_sprg7_wdec + , ex2_sprg8_wdec , ex2_vrsave_wdec; + wire + ex2_acop_wdec , ex2_axucr0_wdec, ex2_cpcr0_wdec , ex2_cpcr1_wdec + , ex2_cpcr2_wdec , ex2_cpcr3_wdec , ex2_cpcr4_wdec , ex2_cpcr5_wdec + , ex2_dac1_wdec , ex2_dac2_wdec , ex2_dac3_wdec , ex2_dac4_wdec + , ex2_dbcr2_wdec , ex2_dbcr3_wdec , ex2_dscr_wdec , ex2_dvc1_wdec + , ex2_dvc2_wdec , ex2_eheir_wdec , ex2_eplc_wdec , ex2_epsc_wdec + , ex2_givpr_wdec , ex2_hacop_wdec , ex2_iac1_wdec , ex2_iac2_wdec + , ex2_iac3_wdec , ex2_iac4_wdec , ex2_immr_wdec , ex2_imr_wdec + , ex2_iucr0_wdec , ex2_iucr1_wdec , ex2_iucr2_wdec , ex2_iudbg0_wdec + , ex2_iulfsr_wdec, ex2_iullcr_wdec, ex2_ivpr_wdec , ex2_lesr1_wdec + , ex2_lesr2_wdec , ex2_lper_wdec , ex2_lperu_wdec , ex2_lpidr_wdec + , ex2_lsucr0_wdec, ex2_mas0_wdec , ex2_mas0_mas1_wdec, ex2_mas1_wdec + , ex2_mas2_wdec , ex2_mas2u_wdec , ex2_mas3_wdec , ex2_mas4_wdec + , ex2_mas5_wdec , ex2_mas5_mas6_wdec, ex2_mas6_wdec , ex2_mas7_wdec + , ex2_mas7_mas3_wdec, ex2_mas8_wdec , ex2_mas8_mas1_wdec, ex2_mmucr0_wdec + , ex2_mmucr1_wdec, ex2_mmucr2_wdec, ex2_mmucr3_wdec, ex2_mmucsr0_wdec + , ex2_pesr_wdec , ex2_pid_wdec , ex2_ppr32_wdec , ex2_xucr2_wdec + , ex2_xudbg0_wdec; + wire + ex3_ccr0_we , ex3_ccr1_we , ex3_ccr2_we , ex3_ccr4_we + , ex3_tbl_we , ex3_tbu_we , ex3_tenc_we , ex3_tens_we + , ex3_xesr1_we , ex3_xesr2_we , ex3_xucr0_we , ex3_xucr4_we ; + wire + ex3_ccr0_wdec , ex3_ccr1_wdec , ex3_ccr2_wdec , ex3_ccr4_wdec + , ex3_tbl_wdec , ex3_tbu_wdec , ex3_tenc_wdec , ex3_tens_wdec + , ex3_xesr1_wdec , ex3_xesr2_wdec , ex3_xucr0_wdec , ex3_xucr4_wdec ; + wire + ccr0_act , ccr1_act , ccr2_act , ccr4_act + , cir_act , pir_act , pvr_act , tb_act + , tbl_act , tbu_act , tenc_act , tens_act + , tensr_act , tir_act , xesr1_act , xesr2_act + , xucr0_act , xucr4_act ; + wire [0:64] + ccr0_do , ccr1_do , ccr2_do , ccr4_do + , cir_do , pir_do , pvr_do , tb_do + , tbl_do , tbu_do , tenc_do , tens_do + , tensr_do , tir_do , xesr1_do , xesr2_do + , xucr0_do , xucr4_do ; + + + wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd; + + wire xu_iu_ex3_sprg_ce, xu_iu_ex3_sprg_ue; + assign xu_iu_ex3_sprg_ce = 1'b0; + assign xu_iu_ex3_sprg_ue = 1'b0; + + //!! Bugspray Include: xu_spr_cspr; + //## figtree_source: xu_spr_cspr.fig; + + assign tidn = {64{1'b0}}; + + assign cspr_xucr0_clkg_ctl = spr_xucr0_clkg_ctl; + + assign ex1_aspr_act_d = ex0_act; + + assign ex0_act = |ex0_val_q & rv_xu_ex0_ord; + assign exx_act_d[1:4] = exx_act[0:3]; + + assign exx_act[0] = ex0_act; + assign exx_act[1] = exx_act_q[1]; + assign exx_act[2] = exx_act_q[2]; + assign exx_act[3] = exx_act_q[3] | ex3_spr_we_q; + assign exx_act[4] = exx_act_q[4]; + + // Needs to be on for loads and stores, for the DEAR... + assign exx_act_data[1] = exx_act[1]; + assign exx_act_data[2] = exx_act[2]; + assign exx_act_data[3] = exx_act[3]; + + assign cspr_tspr_rf1_act = exx_act[0]; + + // Decode + assign ex1_opcode_is_19 = ex1_instr_q[0:5] == 6'b010011; + assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; + assign ex1_is_mfspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101010011); // 31/339 + assign ex1_is_mtspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111010011); // 31/467 + assign ex1_is_mfmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001010011); // 31/083 + assign ex1_is_mtmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010010); // 31/146 + assign ex1_is_mftb = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110011); // 31/371 + assign ex1_is_wait = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000111110); // 31/062 + assign ex1_is_msgclr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011101110); // 31/238 + assign ex1_is_wrtee = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010000011); // 31/131 + assign ex1_is_wrteei = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010100011); // 31/163 + assign ex1_is_mfcr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010011); // 31/19 + assign ex1_is_mtcrf = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010000); // 31/144 + assign ex1_is_dnh = (ex1_opcode_is_19 & ex1_instr_q[21:30] == 10'b0011000110); // 19/198 + + assign ex1_priv_instr = ex1_is_mtmsr | ex1_is_mfmsr | ex1_is_wrtee | ex1_is_wrteei | ex1_is_msgclr; + + assign ex1_hypv_instr = ex1_is_msgclr; + + assign ex1_spr_rd = ex1_is_mfspr | ex1_is_mfmsr | ex1_is_mftb; + assign ex1_spr_wr = ex1_is_mtspr | ex1_is_mtmsr | ex1_is_wrtee | + ex1_is_wrteei | ex1_is_msgclr | ex1_is_wait | ex1_is_dnh; + + assign ex2_is_mtmsr_d = ex1_is_mtmsr | ex1_is_wrtee | ex1_is_wrteei; + + assign rv2_val = rv_xu_vld & (~flush_q); + assign ex0_val = ex0_val_q & (~flush_q) & {`THREADS{rv_xu_ex0_ord}}; + assign ex1_val = ex1_val_q & (~flush_q); + assign ex2_val = ex2_val_q & (~flush_q); + assign ex3_val = ex3_val_q & (~flush_q); + + assign ex1_valid = |(ex1_val); + + assign ex2_flush = |(ex2_tid & flush_q) & (ex2_val_rd_q | ex2_val_wr_q); + assign ex3_flush = |(ex3_tid & flush_q) & (ex3_val_rd_q | ex2_val_wr_q); + + // For CPCRs wait until quiesce + + wire ord_quiesce = &lsu_quiesce_q | ~(ex2_is_mtspr_q & (ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec)) | ex2_is_wait_q; + + // On exception, do not wait for ord_ready. No write will occur. + assign ord_ready = xu_spr_ord_ready_q | flush_int; + + assign flush_int = ex3_hypv_spr_q | ex3_illeg_spr_q | ex3_priv_spr_q; + + assign ex2_val_rd_d = ((ex1_valid & ex1_spr_rd) | ex2_val_rd_q) & ~ex2_flush & ~ex2_val_rd_q; + assign ex2_val_wr_d = ((ex1_valid & ex1_spr_wr) | (ex2_val_wr_q & ~ex2_flush & ~(ord_ready & ord_quiesce))); + + assign ex3_val_rd_d = ex2_val_rd_q & ~ex2_flush; + + assign ex3_spr_we_d = ex2_val_wr_q & ~ex2_flush & ord_ready & ord_quiesce; + assign ex3_spr_we = ex3_spr_we_q & ~flush_int; + assign cspr_tspr_ex3_spr_we = ex3_tid & {`THREADS{ex3_spr_we}}; + + assign ex3_sspr_val = ((ex3_spr_we & ex3_sspr_wr_val_q) | (ex3_val_rd_q & ex3_sspr_rd_val_q)) & (~(ex3_flush | flush_int)); + + assign spr_xu_ord_read_done_d = ex3_spr_we_q & (~ex3_sspr_wr_val_q | flush_int) & ~ex3_flush; + assign spr_xu_ord_write_done_d = ex3_val_rd_q & (~ex3_sspr_rd_val_q | flush_int) & ~ex3_flush; + + assign spr_xu_ord_write_done = spr_xu_ord_write_done_q & ~ex3_flush; + assign spr_xu_ord_read_done = spr_xu_ord_read_done_q & ~ex3_flush; + + assign ex1_instr = ex1_instr_q[11:20]; + assign ex2_instr_d = ex1_instr_q[11:20] & {10{(ex1_is_mfspr | ex1_is_mtspr | ex1_is_wrteei | ex1_is_mftb)}}; + assign ex2_instr = ex2_instr_q[11:20]; + assign ex3_instr_d = ex2_instr_q; // or gate(ex2_dcrn_q,ex2_dcr_val_q); + assign ex3_instr = ex3_instr_q[11:20]; + assign ex3_spr_wd = ex3_rt_q; + assign ex3_spr_wd_out = ex3_rt_q; + assign ex3_is_mtspr = ex3_is_mtspr_q; + assign ex2_ifar = ex2_ifar_q; + + assign ex3_wait = ex3_tid & {`THREADS{(ex3_spr_we & ex3_wait_q & ex3_wait_flush_q)}}; + + assign spr_tens_ten_rev = reverse_threads(spr_tens_ten); + assign spr_tensr = spr_tens_ten | reverse_threads(running); + assign spr_ccr0_we_rev = reverse_threads(spr_ccr0_we[4-`THREADS:3]); + +// Run State +assign quiesce_b_q = ~(quiesce_q & ~running_q); +assign quiesce_d = iu_quiesce_q & iu_icache_quiesce_q & lsu_quiesce_q & mm_quiesce_q & bx_quiesce_q; + +assign quiesced_d = quiesce_q & ~quiesce_ctr_zero_b; + +assign xu_pc_running = running; + +assign running = running_q | ~quiesced_q; +assign running_d = ~(iu_xu_stop | spr_ccr0_we_rev) & spr_tens_ten_rev; +assign iu_run_thread_d = (running_q & llmask) & ~{`THREADS{power_savings_on}}; +assign xu_iu_run_thread = iu_run_thread_q; + +assign ex1_tenc_we = (ex1_instr_q[11:20] == 10'b1011101101); // 439 +assign ex1_ccr0_we = (ex1_instr_q[11:20] == 10'b1000011111); // 1008 + +// Power Management Control +assign xu_pc_spr_ccr0_we = spr_ccr0_we_rev & quiesced_q; +assign xu_pc_spr_ccr0_pme = spr_ccr0_pme; + +assign power_savings_on = (power_savings_en | power_savings_on_q); + +assign power_savings_on_d = power_savings_on & ~(~pc_xu_pm_hold_thread & pc_xu_pm_hold_thread_q); + +assign power_savings_en = ^spr_ccr0_pme & // Power Management Enabled + &spr_ccr0_we_rev & // Wait Enable = 1 + &quiesced_q; // Core Quiesced + +// Wakeup Condition Masking + +// Reset the mask when running +// Set the mask on a valid wait instruction +// Otherwise hold + +// WAIT[WC](0) = Resume on Imp. Specific +// WAIT[WC](1) = Resume on no reservation +generate + begin : pm_wake_up_gen + genvar t; + for (t=0;t<=`THREADS-1;t=t+1) + begin : thread + assign waitimpl_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[9] : + (pm_wake_up[t] == 1'b1) ? 1'b0 : + waitimpl_val_q[t]; + + assign waitrsv_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[10] : + (pm_wake_up[t] == 1'b1) ? 1'b0 : + waitrsv_val_q[t]; + + // Block interrupts (mask=0) if: + // Stopped via (HW Debug and pc_xu_extirpts_dis_on_stop)=1 + // Stopped via TEN=0 + // Stopped via CCR0=1, unless overriden by CCR1=1 (and wait, if applicable) + assign crit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[60-6*t]))); + assign base_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[61-6*t]))); + assign dec_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[62-6*t]))); + assign fit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[63-6*t]))); + + assign cspr_tspr_crit_mask[t] = crit_mask[t]; + assign cspr_tspr_ext_mask[t] = base_mask[t]; + assign cspr_tspr_dec_mask[t] = dec_mask[t]; + assign cspr_tspr_fit_mask[t] = fit_mask[t]; + assign cspr_tspr_wdog_mask[t] = crit_mask[t]; + assign cspr_tspr_udec_mask[t] = dec_mask[t]; + assign cspr_tspr_perf_mask[t] = base_mask[t]; + + // Generate Conditional Wait flush + // Reservation Exists + assign ex2_wait_flush[t] = ex2_tid[t] & ex2_is_wait_q & // Unconditional Wait + ((ex2_wait_wc_q == 2'b00) | (ex2_wait_wc_q == 2'b01 & an_ac_reservation_vld_q[t] & (~ccr1_q[58-6*t])) | // Reservation Exists + (ex2_wait_wc_q == 2'b10 & an_ac_sleep_en_q[t] & (~ccr1_q[59-6*t]))); // Impl. Specific Exists (Sleep enabled) + + + assign ex2_ccr0_flush[t] = ex2_is_mtspr_q & ex2_ccr0_we_q & xu_spr_ex2_rs1[55-t] & xu_spr_ex2_rs1[63-t]; + + assign ex2_tenc_flush[t] = ex2_is_mtspr_q & ex2_tenc_we_q & xu_spr_ex2_rs1[63-t]; + + assign ex2_xucr0_flush[t] = ex2_is_mtspr_q & ex2_xucr0_wdec; + end + end + endgenerate + + assign cspr_tspr_sleep_mask = ~power_savings_on_q; + + assign pm_wake_up = (~an_ac_reservation_vld_q & waitrsv_val_q) | + (~an_ac_sleep_en_q & waitimpl_val_q) | + tspr_cspr_pm_wake_up | + dbell_interrupt_q | + cdbell_interrupt_q | + gdbell_interrupt_q | + gcdbell_interrupt_q | + gmcdbell_interrupt_q; + + // Debug Timer Disable + assign tb_dbg_dis_d = &iu_xu_stop & pc_xu_timebase_dis_on_stop; + assign dec_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_decrem_dis_on_stop}}; + assign ext_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_extirpts_dis_on_stop}}; + + // LiveLock Priority + assign cspr_tspr_llen = running_q; + assign cspr_tspr_llpri = llpri_q; + assign llpres = |(tspr_cspr_lldet); + assign llunmasked = |( llpri_q & tspr_cspr_lldet); + assign llmasked = |(~llpri_q & tspr_cspr_lldet); + assign llpulse = |( llpri_q & tspr_cspr_llpulse); + + // Increment the hang priority if: + // There is a hang present, but the priority is masking it. + // There is another hang present, and there is a hang pulse. + assign llpri_inc = (llpres & (~llunmasked)) | (llpulse & llmasked & llunmasked); + + generate + if (`THREADS == 1) + begin : tid1 + assign llpri_d = 1'b1; + assign ex0_tid = 2'b00; + assign ex2_tid = 1'b1; + assign ex3_tid = 1'b1; + assign instr_trace_tid = 1'b1; + end + endgenerate + generate + if (`THREADS == 2) + begin : tid2 + assign llpri_d = {llpri_q[`THREADS - 1], llpri_q[0:`THREADS - 2]}; + assign ex0_tid = {1'b0, ex0_val_q[1]}; + assign ex2_tid[0] = ~ex2_tid_q[0] & ~ex2_tid_q[1]; + assign ex2_tid[1] = ~ex2_tid_q[0] & ex2_tid_q[1]; + assign ex3_tid[0] = ~ex3_tid_q[0] & ~ex3_tid_q[1]; + assign ex3_tid[1] = ~ex3_tid_q[0] & ex3_tid_q[1]; + assign instr_trace_tid[0] = ~instr_trace_tid_q[0] & ~instr_trace_tid_q[1]; + assign instr_trace_tid[1] = ~instr_trace_tid_q[0] & instr_trace_tid_q[1]; + end + endgenerate + +assign llmask = (llpri_q & tspr_cspr_lldet) | ~{`THREADS{llpres}}; + +assign instr_trace_mode = instr_trace_tid & {`THREADS{instr_trace_mode_q}}; + +assign ex1_msr_gs_d = {1{|(tspr_msr_gs & ex0_val_q)}}; + +assign cspr_tspr_ram_active = ram_active_q; + +assign cspr_tspr_msrovride_en = msrovride_enab; +assign msrovride_enab = ram_active_q & {`THREADS{msrovride_enab_q}}; + +assign xu_iu_msrovride_enab = msrovride_enab_2_q | msrovride_enab_3_q; + +// Perf Events + +assign perf_event_en_d = ( tspr_msr_pr & {`THREADS{pc_xu_event_count_mode[0]}}) | // User + (~tspr_msr_pr & tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[1]}}) | // Guest Supervisor + (~tspr_msr_pr & ~tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[2]}}) ; // Hypervisor + + +wire [0:16*`THREADS-1] perf_events; +wire [0:0] core_event; + generate + begin : perf_count + genvar t; + for (t = 0; t <= `THREADS - 1; t = t + 1) + begin : thread + assign core_event = perf_event_en_q[t] & running[t]; + + assign perf_events[0+16*t] = core_event[0]; + assign perf_events[1+16*t] = perf_event_en_q[t] & running[t]; + assign perf_events[2+16*t] = perf_event_en_q[t] & tb_act_q; + assign perf_events[3+16*t] = perf_event_en_q[t] & waitrsv_val_q[t]; + assign perf_events[4+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[0+3*t]; + assign perf_events[5+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[1+3*t]; + assign perf_events[6+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[2+3*t]; + assign perf_events[7+16*t] = perf_event_en_q[t] & (cpl_dbell_taken_q[t] | cpl_cdbell_taken_q[t] | cpl_gdbell_taken_q[t] | cpl_gcdbell_taken_q[t] | cpl_gmcdbell_taken_q[t]); + assign perf_events[8+16*t] = perf_event_en_q[t] & div_spr_running[t]; + assign perf_events[9+16*t] = perf_event_en_q[t] & mul_spr_running[t]; + assign perf_events[10+16*t:15+16*t] = 6'd0; + + tri_event_mux1t #(.EVENTS_IN(16),.EVENTS_OUT(4)) perf_mux ( + .unit_events_in(perf_events[1+16*t:15+16*t]), + .select_bits(xesr1_q[32+16*t:47+16*t]), + .event_bus_out(perf_event_bus_d[0+4*t:3+4*t]), + .event_bus_in(xu_event_bus_in[0+4*t:3+4*t]), + .vd(vdd),.gd(gnd)); + + end + end + endgenerate + assign xu_event_bus_out = perf_event_bus_q; + assign spr_xesr1 = xesr1_q; + assign spr_xesr2 = xesr2_q; + assign perf_event_en = perf_event_en_q; + + // SPR Input Control + // CIR + assign cir_act = 1'b0; + + // CCR0 + // CCR0[PME] + assign ccr0_act = ex3_ccr0_we; + assign ccr0_d = ex3_ccr0_di; + + // CCR0[WE] + // Generate Bit Mask + assign ccr0_wen = ex3_spr_wd[56-`THREADS:55] & {`THREADS{ex3_ccr0_we}}; + // Apply bit-Mask + assign ccr0_we_di = (ex3_spr_wd[64-`THREADS:63] & ccr0_wen[0:`THREADS-1]) | (ccr0_we_q[0:`THREADS-1] & (~ccr0_wen[0:`THREADS-1])); + // Update based upon wake-up + assign ccr0_we_d = (ccr0_we_di[0:`THREADS-1] | reverse_threads(ex3_wait[0:`THREADS-1])) & ~(reverse_threads(pm_wake_up[0:`THREADS-1])); + // Padded version + assign ccr0_we = {{4-`THREADS{1'b0}},ccr0_we_q}; + + + // CCR1 + assign ccr1_act = ex3_ccr1_we; + assign ccr1_d = ex3_ccr1_di; + + // CCR2 + assign ccr2_act = ex3_ccr2_we; + assign ccr2_d = ex3_ccr2_di; + + // CCR4 + assign ccr4_act = ex3_ccr4_we; + assign ccr4_d = ex3_ccr4_di; + + // PIR + assign pir_act = 1'b1; + + // PVR + assign pvr_act = 1'b1; + + assign version = {8'h00, spr_pvr_version_dc[8:15]}; + assign revision = {4'h0, spr_pvr_revision_dc[12:15], 4'h0, spr_pvr_revision_minor_dc[16:19]}; + + // TB + assign tb_update_pulse = (tb_update_pulse_q ^ tb_update_pulse_1_q); // Any Edge + + // Update on external signal selected by XUCR0[TCS] + assign timer_div_act = tb_update_enable_q & (tb_update_pulse | (~spr_xucr0_tcs)); + + assign timer_div_d = timer_div_q + 5'd1; + + assign timer_div = (timer_div_q ^ timer_div_d) & {5{timer_div_act}}; + + // Select timer clock divide + + assign timer_update_int = (spr_xucr4_tcd == 2'b00) ? timer_div[4] : + (spr_xucr4_tcd == 2'b01) ? timer_div[2] : + (spr_xucr4_tcd == 2'b10) ? timer_div[1] : + timer_div[0]; + assign timer_update = timer_update_q; + + // Not Stopped via HW DBG (if enabled) + assign tb_act_d = ~tb_dbg_dis_q & ~|tspr_cspr_freeze_timers & timer_update_int; // Timers not frozen due to debug event + + assign tb_act = tb_act_q; + assign tb_q = {tbu_q, tbl_q}; + assign tb = tb_q + 1; + + // TBL + assign tbl_act = tb_act | ex3_tbl_we; + assign tbl_d = (ex3_tbl_we == 1'b1) ? ex3_tbl_di : tb[32:63]; + + // TBU + assign tbu_act = tb_act | ex3_tbu_we; + assign tbu_d = (ex3_tbu_we == 1'b1) ? ex3_tbu_di : tb[0:31]; + + // TENC + assign tenc_act = 1'b1; + + // TENS + assign tens_act = ex3_tenc_we | ex3_tens_we; + assign tens_d = (ex3_tenc_we == 1'b1) ? (tens_q & ~ex3_tens_di) : (tens_q | ex3_tens_di); + + // TENSR + assign tensr_act = 1'b1; + + // TIR + assign tir_act = 1'b1; + + // XESR1 + assign xesr1_act = ex3_xesr1_we; + assign xesr1_d = ex3_xesr1_di; + + // XESR2 + assign xesr2_act = ex3_xesr2_we; + assign xesr2_d = ex3_xesr2_di; + + // XUCR0 + assign set_xucr0_cslc_d = lq_xu_spr_xucr0_cslc_xuop | lq_xu_spr_xucr0_cslc_binv; + assign set_xucr0_cul_d = lq_xu_spr_xucr0_cul; + assign set_xucr0_clo_d = lq_xu_spr_xucr0_clo; + + assign xucr0_act = ex3_xucr0_we | set_xucr0_cslc_q | set_xucr0_cul_q | set_xucr0_clo_q; + + assign xucr0_d = {xucr0_di[38:60], + (xucr0_di[61] | set_xucr0_cslc_q), + (xucr0_di[62] | set_xucr0_cul_q), + (xucr0_di[63] | set_xucr0_clo_q)}; + + assign xucr0_di = (ex3_xucr0_we == 1'b1) ? ex3_xucr0_di : xucr0_q; + + // XUCR4 + assign xucr4_act = ex3_xucr4_we; + assign xucr4_d = ex3_xucr4_di; + + // IO signal assignments + + // FIT LL WDOG + assign cspr_tspr_timebase_taps[8] = tbl_q[32 + 23]; // 9 x + assign cspr_tspr_timebase_taps[7] = tbl_q[32 + 11]; // 21 x + assign cspr_tspr_timebase_taps[6] = tbl_q[32 + 7]; // 25 x + assign cspr_tspr_timebase_taps[5] = tbl_q[32 + 21]; // 11 x x + assign cspr_tspr_timebase_taps[4] = tbl_q[32 + 17]; // 15 x x + assign cspr_tspr_timebase_taps[3] = tbl_q[32 + 13]; // 19 x x x + assign cspr_tspr_timebase_taps[2] = tbl_q[32 + 9]; // 23 x x x + assign cspr_tspr_timebase_taps[1] = tbl_q[32 + 5]; // 27 x x + assign cspr_tspr_timebase_taps[0] = tbl_q[32 + 1]; // 31 x + assign cspr_tspr_timebase_taps[9] = tbl_q[32 + 7]; // 29 x -- Replaced 1 for wdog + + assign cspr_tspr_ex2_tid = ex2_tid; + assign cspr_tspr_ex1_instr = ex1_instr_q; + assign cspr_tspr_dec_dbg_dis = dec_dbg_dis_q; + + assign reset_wd_complete = pc_xu_reset_wd_complete_q; + assign reset_3_complete = pc_xu_reset_3_complete_q; + assign reset_2_complete = pc_xu_reset_2_complete_q; + assign reset_1_complete = pc_xu_reset_1_complete_q; + + assign ex1_aspr_tid_d = ex0_tid; + + assign cspr_aspr_ex3_we = (ex3_spr_we & ex3_aspr_we_q) | |ex5_sprg_ce_q; + assign cspr_aspr_ex3_waddr = {ex3_aspr_addr_q, ex3_tid_q}; + assign cspr_aspr_ex1_re = ex1_aspr_re[1] & ex1_aspr_act_q; + assign cspr_aspr_ex1_raddr = {ex1_aspr_addr, ex1_aspr_tid_q}; + + assign xu_slowspr_val_out = ex4_sspr_val_q; + assign xu_slowspr_rw_out = (~ex3_is_mtspr_q); + assign xu_slowspr_etid_out = ex3_tid_q; + assign xu_slowspr_addr_out = {ex3_instr_q[16:20], ex3_instr_q[11:15]}; + assign xu_slowspr_data_out = ex3_spr_wd[64 - `GPR_WIDTH:63]; + + assign ac_an_dcr_act = 1'b0; + assign ac_an_dcr_val = 1'b0; + assign ac_an_dcr_read = 1'b0; + assign ac_an_dcr_user = 1'b0; + assign ac_an_dcr_etid = {2{1'b0}}; + assign ac_an_dcr_addr = {10{1'b0}}; + assign ac_an_dcr_data = {`GPR_WIDTH{1'b0}}; + + assign spr_dec_ex4_spr_hypv = ex4_hypv_spr_q; + assign spr_dec_ex4_spr_illeg = ex4_illeg_spr_q; + assign spr_dec_ex4_spr_priv = ex4_priv_spr_q; + assign spr_dec_ex4_np1_flush = ex4_np1_flush_q | ex4_wait_flush_q | (|ex4_sprg_ue); + + assign dbell_pir_match = (lq_xu_dbell_pirtag_q[50:61] == pir_do[51:62]); + + assign cspr_tspr_dbell_pirtag = lq_xu_dbell_pirtag_q; + + generate + begin : dbell + genvar t; + for (t=0;t<=`THREADS-1;t=t+1) + begin : thread + wire [0:1] tid = t; + + assign dbell_pir_thread[t] = lq_xu_dbell_pirtag_q[62:63] == tid; + + assign set_dbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00000 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); + assign set_cdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00001 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); + assign set_gdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00010 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + assign set_gcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00011 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + assign set_gmcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00100 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); + + assign clr_dbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00000); + assign clr_cdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00001); + assign clr_gdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00010); + assign clr_gcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00011); + assign clr_gmcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00100); + end + end + endgenerate + + assign dbell_present_d = set_dbell | (dbell_present_q & ~(clr_dbell | cpl_dbell_taken_q)); + assign cdbell_present_d = set_cdbell | (cdbell_present_q & ~(clr_cdbell | cpl_cdbell_taken_q)); + assign gdbell_present_d = set_gdbell | (gdbell_present_q & ~(clr_gdbell | cpl_gdbell_taken_q)); + assign gcdbell_present_d = set_gcdbell | (gcdbell_present_q & ~(clr_gcdbell | cpl_gcdbell_taken_q)); + assign gmcdbell_present_d = set_gmcdbell | (gmcdbell_present_q & ~(clr_gmcdbell | cpl_gmcdbell_taken_q)); + + assign dbell_interrupt = dbell_present_q & base_mask & (tspr_msr_ee | tspr_msr_gs); + assign cdbell_interrupt = cdbell_present_q & crit_mask & (tspr_msr_ce | tspr_msr_gs); + assign gdbell_interrupt = gdbell_present_q & base_mask & tspr_msr_ee & tspr_msr_gs; + assign gcdbell_interrupt = gcdbell_present_q & crit_mask & tspr_msr_ce & tspr_msr_gs; + assign gmcdbell_interrupt = gmcdbell_present_q & crit_mask & tspr_msr_me & tspr_msr_gs; + + assign xu_iu_dbell_interrupt = ~{`THREADS{power_savings_on_q}} & dbell_interrupt_q; + assign xu_iu_cdbell_interrupt = ~{`THREADS{power_savings_on_q}} & cdbell_interrupt_q; + assign xu_iu_gdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gdbell_interrupt_q; + assign xu_iu_gcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gcdbell_interrupt_q; + assign xu_iu_gmcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gmcdbell_interrupt_q; + + // Debug + assign cspr_debug0 = {40{1'b0}}; + assign cspr_debug1 = {64{1'b0}}; + + // Array ECC Check + + assign ex3_aspr_rdata_d[64-`GPR_WIDTH] = aspr_cspr_ex2_rdata[64-`GPR_WIDTH]; + assign ex3_aspr_rdata_d[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)] = aspr_cspr_ex2_rdata[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)]; + + assign ex3_eccchk_syn_b = ~ex3_eccchk_syn; + + + tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_rd_eccgen( + .din(ex3_aspr_rdata_q), + .syn(ex3_eccchk_syn) + ); + + + tri_eccchk #(.REGSIZE(`GPR_WIDTH)) xu_spr_eccchk( + .din(ex3_aspr_rdata_q[64-`GPR_WIDTH:63]), + .encorr(encorr), + .nsyn(ex3_eccchk_syn_b), + .corrd(ex3_corr_rdata), + .sbe(ex3_sprg_ce), + .ue(ex3_sprg_ue) + ); + + assign encorr = 1'b1; + + assign ex4_sprg_ue_d = (|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ue); + + assign ex4_sprg_ce_d = {`GPR_WIDTH/8+1{(|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ce)}}; + + + tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ce_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(ex5_sprg_ce_q), + .err_out(xu_pc_err_sprg_ecc) + ); + + tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ue_err_rpt( + .vd(vdd), + .gd(gnd), + .err_in(ex5_sprg_ue_q), + .err_out(xu_pc_err_sprg_ue) + ); + + assign ex4_aspr_rt[32:63] = ex4_corr_rdata_q[32:63] & {32{ex4_aspr_re_q[1]}}; + generate + if (`GPR_WIDTH > 32) + begin : aspr_rt + assign ex4_aspr_rt[64-`GPR_WIDTH:31] = ex4_corr_rdata_q[64-`GPR_WIDTH:31] & {`GPR_WIDTH-32{ex4_aspr_re_q[0]}}; + end + endgenerate + + `ifdef THREADS1 + assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt; + `else + assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt[0:`GPR_WIDTH-1] | tspr_cspr_ex3_tspr_rt[`GPR_WIDTH:2*`GPR_WIDTH-1]; + `endif + + assign ex3_cspr_rt = ex3_cspr_rt_q & {`GPR_WIDTH{(~((ex3_sspr_wr_val_q | ex3_sspr_rd_val_q)))}}; + + assign ex3_spr_rt = ex3_tspr_rt | ex3_cspr_rt; + + assign spr_xu_ex4_rd_data = ex4_spr_rt_q | ex4_aspr_rt; + + // Fast SPR Read + generate + if (a2mode == 0 & hvmode == 0) + begin : readmux_00 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 0 & hvmode == 1) + begin : readmux_01 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 0) + begin : readmux_10 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + generate + if (a2mode == 1 & hvmode == 1) + begin : readmux_11 + assign ex2_cspr_rt = + (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | + (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | + (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | + (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | + (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | + (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | + (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | + (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | + (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | + (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | + (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | + (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | + (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | + (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | + (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | + (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | + (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); + end + endgenerate + + // Fast SPR Write + assign ex3_ccr0_wdec = (ex3_instr[11:20] == 10'b1000011111); // 1008 + assign ex3_ccr1_wdec = (ex3_instr[11:20] == 10'b1000111111); // 1009 + assign ex3_ccr2_wdec = (ex3_instr[11:20] == 10'b1001011111); // 1010 + assign ex3_ccr4_wdec = (ex3_instr[11:20] == 10'b1011011010); // 854 + assign ex3_tbl_wdec = (ex3_instr[11:20] == 10'b1110001000); // 284 + assign ex3_tbu_wdec = ((ex3_instr[11:20] == 10'b1110101000)); // 285 + assign ex3_tenc_wdec = (ex3_instr[11:20] == 10'b1011101101); // 439 + assign ex3_tens_wdec = (ex3_instr[11:20] == 10'b1011001101); // 438 + assign ex3_xesr1_wdec = (ex3_instr[11:20] == 10'b1011011100); // 918 + assign ex3_xesr2_wdec = (ex3_instr[11:20] == 10'b1011111100); // 919 + assign ex3_xucr0_wdec = (ex3_instr[11:20] == 10'b1011011111); // 1014 + assign ex3_xucr4_wdec = (ex3_instr[11:20] == 10'b1010111010); // 853 + assign ex3_ccr0_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr0_wdec; + assign ex3_ccr1_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr1_wdec; + assign ex3_ccr2_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr2_wdec; + assign ex3_ccr4_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr4_wdec; + assign ex3_tbl_we = ex3_spr_we & ex3_is_mtspr & ex3_tbl_wdec; + assign ex3_tbu_we = ex3_spr_we & ex3_is_mtspr & ex3_tbu_wdec; + assign ex3_tenc_we = ex3_spr_we & ex3_is_mtspr & ex3_tenc_wdec; + assign ex3_tens_we = ex3_spr_we & ex3_is_mtspr & ex3_tens_wdec; + assign ex3_xesr1_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr1_wdec; + assign ex3_xesr2_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr2_wdec; + assign ex3_xucr0_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr0_wdec; + assign ex3_xucr4_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr4_wdec; + + // Array Read + assign ex1_gsprg0_rdec = (ex1_instr[11:20] == 10'b1000001011); // 368 + assign ex1_gsprg1_rdec = (ex1_instr[11:20] == 10'b1000101011); // 369 + assign ex1_gsprg2_rdec = (ex1_instr[11:20] == 10'b1001001011); // 370 + assign ex1_gsprg3_rdec = (ex1_instr[11:20] == 10'b1001101011); // 371 + assign ex1_sprg0_rdec = (ex1_instr[11:20] == 10'b1000001000); // 272 + assign ex1_sprg1_rdec = (ex1_instr[11:20] == 10'b1000101000); // 273 + assign ex1_sprg2_rdec = (ex1_instr[11:20] == 10'b1001001000); // 274 + assign ex1_sprg3_rdec = ((ex1_instr[11:20] == 10'b1001101000) | // 275 + (ex1_instr[11:20] == 10'b0001101000)); // 259 + assign ex1_sprg4_rdec = ((ex1_instr[11:20] == 10'b1010001000) | // 276 + (ex1_instr[11:20] == 10'b0010001000)); // 260 + assign ex1_sprg5_rdec = ((ex1_instr[11:20] == 10'b1010101000) | // 277 + (ex1_instr[11:20] == 10'b0010101000)); // 261 + assign ex1_sprg6_rdec = ((ex1_instr[11:20] == 10'b1011001000) | // 278 + (ex1_instr[11:20] == 10'b0011001000)); // 262 + assign ex1_sprg7_rdec = ((ex1_instr[11:20] == 10'b1011101000) | // 279 + (ex1_instr[11:20] == 10'b0011101000)); // 263 + assign ex1_sprg8_rdec = (ex1_instr[11:20] == 10'b1110010010); // 604 + assign ex1_vrsave_rdec = (ex1_instr[11:20] == 10'b0000001000); // 256 + assign ex1_gsprg0_re = (ex1_gsprg0_rdec | (ex1_sprg0_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg1_re = (ex1_gsprg1_rdec | (ex1_sprg1_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg2_re = (ex1_gsprg2_rdec | (ex1_sprg2_rdec & ex1_msr_gs_q[0])); + assign ex1_gsprg3_re = (ex1_gsprg3_rdec | (ex1_sprg3_rdec & ex1_msr_gs_q[0])); + assign ex1_sprg0_re = ex1_sprg0_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg1_re = ex1_sprg1_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg2_re = ex1_sprg2_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg3_re = ex1_sprg3_rdec & ~ex1_msr_gs_q[0]; + assign ex1_sprg4_re = ex1_sprg4_rdec; + assign ex1_sprg5_re = ex1_sprg5_rdec; + assign ex1_sprg6_re = ex1_sprg6_rdec; + assign ex1_sprg7_re = ex1_sprg7_rdec; + assign ex1_sprg8_re = ex1_sprg8_rdec; + assign ex1_vrsave_re = ex1_vrsave_rdec; + + assign ex1_aspr_re[1] = ex1_is_mfspr & ( + ex1_gsprg0_re | ex1_gsprg1_re | ex1_gsprg2_re + | ex1_gsprg3_re | ex1_sprg0_re | ex1_sprg1_re + | ex1_sprg2_re | ex1_sprg3_re | ex1_sprg4_re + | ex1_sprg5_re | ex1_sprg6_re | ex1_sprg7_re + | ex1_sprg8_re | ex1_vrsave_re ); + + generate + if (`GPR_WIDTH > 32) + begin : ex1_aspr_re0_gen + assign ex1_aspr_re[0] = ex1_aspr_re[1] & ~( + ex1_vrsave_re ); + end + endgenerate + + assign ex1_aspr_addr = + (4'b0000 & {4{ex1_gsprg0_re }}) | + (4'b0001 & {4{ex1_gsprg1_re }}) | + (4'b0010 & {4{ex1_gsprg2_re }}) | + (4'b0011 & {4{ex1_gsprg3_re }}) | + (4'b0100 & {4{ex1_sprg0_re }}) | + (4'b0101 & {4{ex1_sprg1_re }}) | + (4'b0110 & {4{ex1_sprg2_re }}) | + (4'b0111 & {4{ex1_sprg3_re }}) | + (4'b1000 & {4{ex1_sprg4_re }}) | + (4'b1001 & {4{ex1_sprg5_re }}) | + (4'b1010 & {4{ex1_sprg6_re }}) | + (4'b1011 & {4{ex1_sprg7_re }}) | + (4'b1100 & {4{ex1_sprg8_re }}) | + (4'b1101 & {4{ex1_vrsave_re }}); + + + // Array Writes + + // Generate ECC + assign ex2_inj_ecc = |(inj_sprg_ecc_q & ex2_tid) & ~ex4_sprg_ce_q[0]; + + assign ex3_aspr_addr_d = (ex4_sprg_ce_q[`GPR_WIDTH/8] == 1'b1) ? ex4_aspr_ce_addr_q : ex2_aspr_addr; + + + generate + genvar i; + for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex2_rt_gen + assign ex2_rt[i] = (ex4_corr_rdata_q[i] & ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) | + (xu_spr_ex2_rs1[i] & ~ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) ; + end + endgenerate + + assign ex2_rt_inj[63] = ex2_rt[63] ^ ex2_inj_ecc; + assign ex2_rt_inj[64-`GPR_WIDTH:62] = ex2_rt[64 - `GPR_WIDTH:62]; + + assign ex2_eccgen_data = {ex2_rt, tidn[0:8 - (64/`GPR_WIDTH)]}; + + + tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_wr_eccgen( + .din(ex2_eccgen_data), + .syn(ex2_eccgen_syn) + ); + + assign ex2_is_mfsspr_b = ~ex2_sspr_rd_val; + + assign ex2_aspr_addr_act = exx_act_data[2] | ex4_sprg_ce_q[0]; + + assign ex3_rt_act = exx_act_data[2] | ex4_sprg_ce_q[0]; + assign ex3_rt_d = {(ex2_rt_inj & {`GPR_WIDTH{ex2_is_mfsspr_b}}), ex2_eccgen_syn}; + + assign ex4_sprg_ue = ex4_val_q & {`THREADS{ex4_sprg_ue_q}}; + assign ex4_sprg_ce = ex4_val_q & {`THREADS{ex4_sprg_ce_q[0]}}; + assign ex3_aspr_we_d = |(ex2_val) & ex2_aspr_we; + + assign ex2_aspr_we = ex2_is_mtspr_q & ( + ex2_gsprg0_we | ex2_gsprg1_we | ex2_gsprg2_we + | ex2_gsprg3_we | ex2_sprg0_we | ex2_sprg1_we + | ex2_sprg2_we | ex2_sprg3_we | ex2_sprg4_we + | ex2_sprg5_we | ex2_sprg6_we | ex2_sprg7_we + | ex2_sprg8_we | ex2_vrsave_we ); + + assign ex2_gsprg0_wdec = (ex2_instr[11:20] == 10'b1000001011); // 368 + assign ex2_gsprg1_wdec = (ex2_instr[11:20] == 10'b1000101011); // 369 + assign ex2_gsprg2_wdec = (ex2_instr[11:20] == 10'b1001001011); // 370 + assign ex2_gsprg3_wdec = (ex2_instr[11:20] == 10'b1001101011); // 371 + assign ex2_sprg0_wdec = (ex2_instr[11:20] == 10'b1000001000); // 272 + assign ex2_sprg1_wdec = (ex2_instr[11:20] == 10'b1000101000); // 273 + assign ex2_sprg2_wdec = (ex2_instr[11:20] == 10'b1001001000); // 274 + assign ex2_sprg3_wdec = ((ex2_instr[11:20] == 10'b1001101000)); // 275 + assign ex2_sprg4_wdec = ((ex2_instr[11:20] == 10'b1010001000)); // 276 + assign ex2_sprg5_wdec = ((ex2_instr[11:20] == 10'b1010101000)); // 277 + assign ex2_sprg6_wdec = ((ex2_instr[11:20] == 10'b1011001000)); // 278 + assign ex2_sprg7_wdec = ((ex2_instr[11:20] == 10'b1011101000)); // 279 + assign ex2_sprg8_wdec = (ex2_instr[11:20] == 10'b1110010010); // 604 + assign ex2_vrsave_wdec = (ex2_instr[11:20] == 10'b0000001000); // 256 + assign ex2_gsprg0_we = (ex2_gsprg0_wdec | (ex2_sprg0_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg1_we = (ex2_gsprg1_wdec | (ex2_sprg1_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg2_we = (ex2_gsprg2_wdec | (ex2_sprg2_wdec & ex2_msr_gs_q[0])); + assign ex2_gsprg3_we = (ex2_gsprg3_wdec | (ex2_sprg3_wdec & ex2_msr_gs_q[0])); + assign ex2_sprg0_we = ex2_sprg0_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg1_we = ex2_sprg1_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg2_we = ex2_sprg2_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg3_we = ex2_sprg3_wdec & ~ex2_msr_gs_q[0]; + assign ex2_sprg4_we = ex2_sprg4_wdec; + assign ex2_sprg5_we = ex2_sprg5_wdec; + assign ex2_sprg6_we = ex2_sprg6_wdec; + assign ex2_sprg7_we = ex2_sprg7_wdec; + assign ex2_sprg8_we = ex2_sprg8_wdec; + assign ex2_vrsave_we = ex2_vrsave_wdec; + + assign ex2_aspr_addr = + (4'b0000 & {4{ex2_gsprg0_we }}) | + (4'b0001 & {4{ex2_gsprg1_we }}) | + (4'b0010 & {4{ex2_gsprg2_we }}) | + (4'b0011 & {4{ex2_gsprg3_we }}) | + (4'b0100 & {4{ex2_sprg0_we }}) | + (4'b0101 & {4{ex2_sprg1_we }}) | + (4'b0110 & {4{ex2_sprg2_we }}) | + (4'b0111 & {4{ex2_sprg3_we }}) | + (4'b1000 & {4{ex2_sprg4_we }}) | + (4'b1001 & {4{ex2_sprg5_we }}) | + (4'b1010 & {4{ex2_sprg6_we }}) | + (4'b1011 & {4{ex2_sprg7_we }}) | + (4'b1100 & {4{ex2_sprg8_we }}) | + (4'b1101 & {4{ex2_vrsave_we }}); + + // Slow SPR + assign ex2_acop_rdec = (ex2_instr[11:20] == 10'b1111100000); // 31 + assign ex2_axucr0_rdec = (ex2_instr[11:20] == 10'b1000011110); // 976 + assign ex2_cpcr0_rdec = (ex2_instr[11:20] == 10'b1000011001); // 816 + assign ex2_cpcr1_rdec = (ex2_instr[11:20] == 10'b1000111001); // 817 + assign ex2_cpcr2_rdec = (ex2_instr[11:20] == 10'b1001011001); // 818 + assign ex2_cpcr3_rdec = (ex2_instr[11:20] == 10'b1010011001); // 820 + assign ex2_cpcr4_rdec = (ex2_instr[11:20] == 10'b1010111001); // 821 + assign ex2_cpcr5_rdec = (ex2_instr[11:20] == 10'b1011011001); // 822 + assign ex2_dac1_rdec = (ex2_instr[11:20] == 10'b1110001001); // 316 + assign ex2_dac2_rdec = (ex2_instr[11:20] == 10'b1110101001); // 317 + assign ex2_dac3_rdec = (ex2_instr[11:20] == 10'b1000111010); // 849 + assign ex2_dac4_rdec = (ex2_instr[11:20] == 10'b1001011010); // 850 + assign ex2_dbcr2_rdec = (ex2_instr[11:20] == 10'b1011001001); // 310 + assign ex2_dbcr3_rdec = (ex2_instr[11:20] == 10'b1000011010); // 848 + assign ex2_dscr_rdec = (ex2_instr[11:20] == 10'b1000100000); // 17 + assign ex2_dvc1_rdec = (ex2_instr[11:20] == 10'b1111001001); // 318 + assign ex2_dvc2_rdec = (ex2_instr[11:20] == 10'b1111101001); // 319 + assign ex2_eheir_rdec = (ex2_instr[11:20] == 10'b1010000001); // 52 + assign ex2_eplc_rdec = (ex2_instr[11:20] == 10'b1001111101); // 947 + assign ex2_epsc_rdec = (ex2_instr[11:20] == 10'b1010011101); // 948 + assign ex2_eptcfg_rdec = (ex2_instr[11:20] == 10'b1111001010); // 350 + assign ex2_givpr_rdec = (ex2_instr[11:20] == 10'b1111101101); // 447 + assign ex2_hacop_rdec = (ex2_instr[11:20] == 10'b1111101010); // 351 + assign ex2_iac1_rdec = (ex2_instr[11:20] == 10'b1100001001); // 312 + assign ex2_iac2_rdec = (ex2_instr[11:20] == 10'b1100101001); // 313 + assign ex2_iac3_rdec = (ex2_instr[11:20] == 10'b1101001001); // 314 + assign ex2_iac4_rdec = (ex2_instr[11:20] == 10'b1101101001); // 315 + assign ex2_immr_rdec = (ex2_instr[11:20] == 10'b1000111011); // 881 + assign ex2_imr_rdec = (ex2_instr[11:20] == 10'b1000011011); // 880 + assign ex2_iucr0_rdec = (ex2_instr[11:20] == 10'b1001111111); // 1011 + assign ex2_iucr1_rdec = (ex2_instr[11:20] == 10'b1001111011); // 883 + assign ex2_iucr2_rdec = (ex2_instr[11:20] == 10'b1010011011); // 884 + assign ex2_iudbg0_rdec = (ex2_instr[11:20] == 10'b1100011011); // 888 + assign ex2_iudbg1_rdec = (ex2_instr[11:20] == 10'b1100111011); // 889 + assign ex2_iudbg2_rdec = (ex2_instr[11:20] == 10'b1101011011); // 890 + assign ex2_iulfsr_rdec = (ex2_instr[11:20] == 10'b1101111011); // 891 + assign ex2_iullcr_rdec = (ex2_instr[11:20] == 10'b1110011011); // 892 + assign ex2_ivpr_rdec = (ex2_instr[11:20] == 10'b1111100001); // 63 + assign ex2_lesr1_rdec = (ex2_instr[11:20] == 10'b1100011100); // 920 + assign ex2_lesr2_rdec = (ex2_instr[11:20] == 10'b1100111100); // 921 + assign ex2_lper_rdec = (ex2_instr[11:20] == 10'b1100000001); // 56 + assign ex2_lperu_rdec = (ex2_instr[11:20] == 10'b1100100001); // 57 + assign ex2_lpidr_rdec = (ex2_instr[11:20] == 10'b1001001010); // 338 + assign ex2_lratcfg_rdec = (ex2_instr[11:20] == 10'b1011001010); // 342 + assign ex2_lratps_rdec = (ex2_instr[11:20] == 10'b1011101010); // 343 + assign ex2_lsucr0_rdec = (ex2_instr[11:20] == 10'b1001111001); // 819 + assign ex2_mas0_rdec = (ex2_instr[11:20] == 10'b1000010011); // 624 + assign ex2_mas0_mas1_rdec = (ex2_instr[11:20] == 10'b1010101011); // 373 + assign ex2_mas1_rdec = (ex2_instr[11:20] == 10'b1000110011); // 625 + assign ex2_mas2_rdec = (ex2_instr[11:20] == 10'b1001010011); // 626 + assign ex2_mas2u_rdec = (ex2_instr[11:20] == 10'b1011110011); // 631 + assign ex2_mas3_rdec = (ex2_instr[11:20] == 10'b1001110011); // 627 + assign ex2_mas4_rdec = (ex2_instr[11:20] == 10'b1010010011); // 628 + assign ex2_mas5_rdec = (ex2_instr[11:20] == 10'b1001101010); // 339 + assign ex2_mas5_mas6_rdec = (ex2_instr[11:20] == 10'b1110001010); // 348 + assign ex2_mas6_rdec = (ex2_instr[11:20] == 10'b1011010011); // 630 + assign ex2_mas7_rdec = (ex2_instr[11:20] == 10'b1000011101); // 944 + assign ex2_mas7_mas3_rdec = (ex2_instr[11:20] == 10'b1010001011); // 372 + assign ex2_mas8_rdec = (ex2_instr[11:20] == 10'b1010101010); // 341 + assign ex2_mas8_mas1_rdec = (ex2_instr[11:20] == 10'b1110101010); // 349 + assign ex2_mmucfg_rdec = (ex2_instr[11:20] == 10'b1011111111); // 1015 + assign ex2_mmucr0_rdec = (ex2_instr[11:20] == 10'b1110011111); // 1020 + assign ex2_mmucr1_rdec = (ex2_instr[11:20] == 10'b1110111111); // 1021 + assign ex2_mmucr2_rdec = (ex2_instr[11:20] == 10'b1111011111); // 1022 + assign ex2_mmucr3_rdec = (ex2_instr[11:20] == 10'b1111111111); // 1023 + assign ex2_mmucsr0_rdec = (ex2_instr[11:20] == 10'b1010011111); // 1012 + assign ex2_pesr_rdec = (ex2_instr[11:20] == 10'b1110111011); // 893 + assign ex2_pid_rdec = (ex2_instr[11:20] == 10'b1000000001); // 48 + assign ex2_ppr32_rdec = (ex2_instr[11:20] == 10'b0001011100); // 898 + assign ex2_sramd_rdec = (ex2_instr[11:20] == 10'b1111011011); // 894 + assign ex2_tlb0cfg_rdec = (ex2_instr[11:20] == 10'b1000010101); // 688 + assign ex2_tlb0ps_rdec = (ex2_instr[11:20] == 10'b1100001010); // 344 + assign ex2_xucr2_rdec = (ex2_instr[11:20] == 10'b1100011111); // 1016 + assign ex2_xudbg0_rdec = (ex2_instr[11:20] == 10'b1010111011); // 885 + assign ex2_xudbg1_rdec = (ex2_instr[11:20] == 10'b1011011011); // 886 + assign ex2_xudbg2_rdec = (ex2_instr[11:20] == 10'b1011111011); // 887 + assign ex2_acop_re = ex2_acop_rdec; + assign ex2_axucr0_re = ex2_axucr0_rdec; + assign ex2_cpcr0_re = ex2_cpcr0_rdec; + assign ex2_cpcr1_re = ex2_cpcr1_rdec; + assign ex2_cpcr2_re = ex2_cpcr2_rdec; + assign ex2_cpcr3_re = ex2_cpcr3_rdec; + assign ex2_cpcr4_re = ex2_cpcr4_rdec; + assign ex2_cpcr5_re = ex2_cpcr5_rdec; + assign ex2_dac1_re = ex2_dac1_rdec; + assign ex2_dac2_re = ex2_dac2_rdec; + assign ex2_dac3_re = ex2_dac3_rdec; + assign ex2_dac4_re = ex2_dac4_rdec; + assign ex2_dbcr2_re = ex2_dbcr2_rdec; + assign ex2_dbcr3_re = ex2_dbcr3_rdec; + assign ex2_dscr_re = ex2_dscr_rdec; + assign ex2_dvc1_re = ex2_dvc1_rdec; + assign ex2_dvc2_re = ex2_dvc2_rdec; + assign ex2_eheir_re = ex2_eheir_rdec; + assign ex2_eplc_re = ex2_eplc_rdec; + assign ex2_epsc_re = ex2_epsc_rdec; + assign ex2_eptcfg_re = ex2_eptcfg_rdec; + assign ex2_givpr_re = ex2_givpr_rdec; + assign ex2_hacop_re = ex2_hacop_rdec; + assign ex2_iac1_re = ex2_iac1_rdec; + assign ex2_iac2_re = ex2_iac2_rdec; + assign ex2_iac3_re = ex2_iac3_rdec; + assign ex2_iac4_re = ex2_iac4_rdec; + assign ex2_immr_re = ex2_immr_rdec; + assign ex2_imr_re = ex2_imr_rdec; + assign ex2_iucr0_re = ex2_iucr0_rdec; + assign ex2_iucr1_re = ex2_iucr1_rdec; + assign ex2_iucr2_re = ex2_iucr2_rdec; + assign ex2_iudbg0_re = ex2_iudbg0_rdec; + assign ex2_iudbg1_re = ex2_iudbg1_rdec; + assign ex2_iudbg2_re = ex2_iudbg2_rdec; + assign ex2_iulfsr_re = ex2_iulfsr_rdec; + assign ex2_iullcr_re = ex2_iullcr_rdec; + assign ex2_ivpr_re = ex2_ivpr_rdec; + assign ex2_lesr1_re = ex2_lesr1_rdec; + assign ex2_lesr2_re = ex2_lesr2_rdec; + assign ex2_lper_re = ex2_lper_rdec; + assign ex2_lperu_re = ex2_lperu_rdec; + assign ex2_lpidr_re = ex2_lpidr_rdec; + assign ex2_lratcfg_re = ex2_lratcfg_rdec; + assign ex2_lratps_re = ex2_lratps_rdec; + assign ex2_lsucr0_re = ex2_lsucr0_rdec; + assign ex2_mas0_re = ex2_mas0_rdec; + assign ex2_mas0_mas1_re = ex2_mas0_mas1_rdec; + assign ex2_mas1_re = ex2_mas1_rdec; + assign ex2_mas2_re = ex2_mas2_rdec; + assign ex2_mas2u_re = ex2_mas2u_rdec; + assign ex2_mas3_re = ex2_mas3_rdec; + assign ex2_mas4_re = ex2_mas4_rdec; + assign ex2_mas5_re = ex2_mas5_rdec; + assign ex2_mas5_mas6_re = ex2_mas5_mas6_rdec; + assign ex2_mas6_re = ex2_mas6_rdec; + assign ex2_mas7_re = ex2_mas7_rdec; + assign ex2_mas7_mas3_re = ex2_mas7_mas3_rdec; + assign ex2_mas8_re = ex2_mas8_rdec; + assign ex2_mas8_mas1_re = ex2_mas8_mas1_rdec; + assign ex2_mmucfg_re = ex2_mmucfg_rdec; + assign ex2_mmucr0_re = ex2_mmucr0_rdec; + assign ex2_mmucr1_re = ex2_mmucr1_rdec; + assign ex2_mmucr2_re = ex2_mmucr2_rdec; + assign ex2_mmucr3_re = ex2_mmucr3_rdec; + assign ex2_mmucsr0_re = ex2_mmucsr0_rdec; + assign ex2_pesr_re = ex2_pesr_rdec; + assign ex2_pid_re = ex2_pid_rdec; + assign ex2_ppr32_re = ex2_ppr32_rdec; + assign ex2_sramd_re = ex2_sramd_rdec; + assign ex2_tlb0cfg_re = ex2_tlb0cfg_rdec; + assign ex2_tlb0ps_re = ex2_tlb0ps_rdec; + assign ex2_xucr2_re = ex2_xucr2_rdec; + assign ex2_xudbg0_re = ex2_xudbg0_rdec; + assign ex2_xudbg1_re = ex2_xudbg1_rdec; + assign ex2_xudbg2_re = ex2_xudbg2_rdec; + assign ex2_acop_wdec = ex2_acop_rdec; + assign ex2_axucr0_wdec = ex2_axucr0_rdec; + assign ex2_cpcr0_wdec = ex2_cpcr0_rdec; + assign ex2_cpcr1_wdec = ex2_cpcr1_rdec; + assign ex2_cpcr2_wdec = ex2_cpcr2_rdec; + assign ex2_cpcr3_wdec = ex2_cpcr3_rdec; + assign ex2_cpcr4_wdec = ex2_cpcr4_rdec; + assign ex2_cpcr5_wdec = ex2_cpcr5_rdec; + assign ex2_dac1_wdec = ex2_dac1_rdec; + assign ex2_dac2_wdec = ex2_dac2_rdec; + assign ex2_dac3_wdec = ex2_dac3_rdec; + assign ex2_dac4_wdec = ex2_dac4_rdec; + assign ex2_dbcr2_wdec = ex2_dbcr2_rdec; + assign ex2_dbcr3_wdec = ex2_dbcr3_rdec; + assign ex2_dscr_wdec = ex2_dscr_rdec; + assign ex2_dvc1_wdec = ex2_dvc1_rdec; + assign ex2_dvc2_wdec = ex2_dvc2_rdec; + assign ex2_eheir_wdec = ex2_eheir_rdec; + assign ex2_eplc_wdec = ex2_eplc_rdec; + assign ex2_epsc_wdec = ex2_epsc_rdec; + assign ex2_givpr_wdec = (ex2_instr[11:20] == 10'b1111101101); // 447 + assign ex2_hacop_wdec = (ex2_instr[11:20] == 10'b1111101010); // 351 + assign ex2_iac1_wdec = ex2_iac1_rdec; + assign ex2_iac2_wdec = ex2_iac2_rdec; + assign ex2_iac3_wdec = ex2_iac3_rdec; + assign ex2_iac4_wdec = ex2_iac4_rdec; + assign ex2_immr_wdec = ex2_immr_rdec; + assign ex2_imr_wdec = ex2_imr_rdec; + assign ex2_iucr0_wdec = ex2_iucr0_rdec; + assign ex2_iucr1_wdec = ex2_iucr1_rdec; + assign ex2_iucr2_wdec = ex2_iucr2_rdec; + assign ex2_iudbg0_wdec = ex2_iudbg0_rdec; + assign ex2_iulfsr_wdec = ex2_iulfsr_rdec; + assign ex2_iullcr_wdec = ex2_iullcr_rdec; + assign ex2_ivpr_wdec = ex2_ivpr_rdec; + assign ex2_lesr1_wdec = ex2_lesr1_rdec; + assign ex2_lesr2_wdec = ex2_lesr2_rdec; + assign ex2_lper_wdec = ex2_lper_rdec; + assign ex2_lperu_wdec = ex2_lperu_rdec; + assign ex2_lpidr_wdec = ex2_lpidr_rdec; + assign ex2_lsucr0_wdec = ex2_lsucr0_rdec; + assign ex2_mas0_wdec = ex2_mas0_rdec; + assign ex2_mas0_mas1_wdec = ex2_mas0_mas1_rdec; + assign ex2_mas1_wdec = ex2_mas1_rdec; + assign ex2_mas2_wdec = ex2_mas2_rdec; + assign ex2_mas2u_wdec = ex2_mas2u_rdec; + assign ex2_mas3_wdec = ex2_mas3_rdec; + assign ex2_mas4_wdec = ex2_mas4_rdec; + assign ex2_mas5_wdec = ex2_mas5_rdec; + assign ex2_mas5_mas6_wdec = ex2_mas5_mas6_rdec; + assign ex2_mas6_wdec = ex2_mas6_rdec; + assign ex2_mas7_wdec = ex2_mas7_rdec; + assign ex2_mas7_mas3_wdec = ex2_mas7_mas3_rdec; + assign ex2_mas8_wdec = ex2_mas8_rdec; + assign ex2_mas8_mas1_wdec = ex2_mas8_mas1_rdec; + assign ex2_mmucr0_wdec = ex2_mmucr0_rdec; + assign ex2_mmucr1_wdec = ex2_mmucr1_rdec; + assign ex2_mmucr2_wdec = ex2_mmucr2_rdec; + assign ex2_mmucr3_wdec = ex2_mmucr3_rdec; + assign ex2_mmucsr0_wdec = ex2_mmucsr0_rdec; + assign ex2_pesr_wdec = ex2_pesr_rdec; + assign ex2_pid_wdec = ex2_pid_rdec; + assign ex2_ppr32_wdec = ex2_ppr32_rdec; + assign ex2_xucr2_wdec = ex2_xucr2_rdec; + assign ex2_xudbg0_wdec = ex2_xudbg0_rdec; + assign ex2_acop_we = ex2_acop_wdec; + assign ex2_axucr0_we = ex2_axucr0_wdec; + assign ex2_cpcr0_we = ex2_cpcr0_wdec; + assign ex2_cpcr1_we = ex2_cpcr1_wdec; + assign ex2_cpcr2_we = ex2_cpcr2_wdec; + assign ex2_cpcr3_we = ex2_cpcr3_wdec; + assign ex2_cpcr4_we = ex2_cpcr4_wdec; + assign ex2_cpcr5_we = ex2_cpcr5_wdec; + assign ex2_dac1_we = ex2_dac1_wdec; + assign ex2_dac2_we = ex2_dac2_wdec; + assign ex2_dac3_we = ex2_dac3_wdec; + assign ex2_dac4_we = ex2_dac4_wdec; + assign ex2_dbcr2_we = ex2_dbcr2_wdec; + assign ex2_dbcr3_we = ex2_dbcr3_wdec; + assign ex2_dscr_we = ex2_dscr_wdec; + assign ex2_dvc1_we = ex2_dvc1_wdec; + assign ex2_dvc2_we = ex2_dvc2_wdec; + assign ex2_eheir_we = ex2_eheir_wdec; + assign ex2_eplc_we = ex2_eplc_wdec; + assign ex2_epsc_we = ex2_epsc_wdec; + assign ex2_givpr_we = ex2_givpr_wdec; + assign ex2_hacop_we = ex2_hacop_wdec; + assign ex2_iac1_we = ex2_iac1_wdec; + assign ex2_iac2_we = ex2_iac2_wdec; + assign ex2_iac3_we = ex2_iac3_wdec; + assign ex2_iac4_we = ex2_iac4_wdec; + assign ex2_immr_we = ex2_immr_wdec; + assign ex2_imr_we = ex2_imr_wdec; + assign ex2_iucr0_we = ex2_iucr0_wdec; + assign ex2_iucr1_we = ex2_iucr1_wdec; + assign ex2_iucr2_we = ex2_iucr2_wdec; + assign ex2_iudbg0_we = ex2_iudbg0_wdec; + assign ex2_iulfsr_we = ex2_iulfsr_wdec; + assign ex2_iullcr_we = ex2_iullcr_wdec; + assign ex2_ivpr_we = ex2_ivpr_wdec; + assign ex2_lesr1_we = ex2_lesr1_wdec; + assign ex2_lesr2_we = ex2_lesr2_wdec; + assign ex2_lper_we = ex2_lper_wdec; + assign ex2_lperu_we = ex2_lperu_wdec; + assign ex2_lpidr_we = ex2_lpidr_wdec; + assign ex2_lsucr0_we = ex2_lsucr0_wdec; + assign ex2_mas0_we = ex2_mas0_wdec; + assign ex2_mas0_mas1_we = ex2_mas0_mas1_wdec; + assign ex2_mas1_we = ex2_mas1_wdec; + assign ex2_mas2_we = ex2_mas2_wdec; + assign ex2_mas2u_we = ex2_mas2u_wdec; + assign ex2_mas3_we = ex2_mas3_wdec; + assign ex2_mas4_we = ex2_mas4_wdec; + assign ex2_mas5_we = ex2_mas5_wdec; + assign ex2_mas5_mas6_we = ex2_mas5_mas6_wdec; + assign ex2_mas6_we = ex2_mas6_wdec; + assign ex2_mas7_we = ex2_mas7_wdec; + assign ex2_mas7_mas3_we = ex2_mas7_mas3_wdec; + assign ex2_mas8_we = ex2_mas8_wdec; + assign ex2_mas8_mas1_we = ex2_mas8_mas1_wdec; + assign ex2_mmucr0_we = ex2_mmucr0_wdec; + assign ex2_mmucr1_we = ex2_mmucr1_wdec; + assign ex2_mmucr2_we = ex2_mmucr2_wdec; + assign ex2_mmucr3_we = ex2_mmucr3_wdec; + assign ex2_mmucsr0_we = ex2_mmucsr0_wdec; + assign ex2_pesr_we = ex2_pesr_wdec; + assign ex2_pid_we = ex2_pid_wdec; + assign ex2_ppr32_we = ex2_ppr32_wdec; + assign ex2_xucr2_we = ex2_xucr2_wdec; + assign ex2_xudbg0_we = ex2_xudbg0_wdec; + assign ex2_slowspr_range_hypv = ex2_instr[11] & ex2_instr[16:20] == 5'b11110; // 976-991 + assign ex2_slowspr_range_priv = ex2_instr[11] & ex2_instr[16:20] == 5'b11100 & (~(ex2_xesr1_rdec | ex2_xesr2_rdec)); // 912-927 except 918/919 + assign ex2_slowspr_range = ex2_slowspr_range_priv | ex2_slowspr_range_hypv; + + // mftb encode is only legal for tbr=268,269 -- "0110-01000" + assign ex2_illeg_mftb = ex2_is_mftb_q & (~(ex2_instr[11:14] == 4'b0110 & ex2_instr[16:20] == 5'b01000)); + + assign ex2_sspr_wr_val = ex2_is_mtspr_q & (ex2_slowspr_range | + ex2_acop_we | ex2_axucr0_we | ex2_cpcr0_we + | ex2_cpcr1_we | ex2_cpcr2_we | ex2_cpcr3_we + | ex2_cpcr4_we | ex2_cpcr5_we | ex2_dac1_we + | ex2_dac2_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr2_we | ex2_dbcr3_we | ex2_dscr_we + | ex2_dvc1_we | ex2_dvc2_we | ex2_eheir_we + | ex2_eplc_we | ex2_epsc_we | ex2_givpr_we + | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we + | ex2_iac3_we | ex2_iac4_we | ex2_immr_we + | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lesr1_we + | ex2_lesr2_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas0_we + | ex2_mas0_mas1_we | ex2_mas1_we | ex2_mas2_we + | ex2_mas2u_we | ex2_mas3_we | ex2_mas4_we + | ex2_mas5_we | ex2_mas5_mas6_we | ex2_mas6_we + | ex2_mas7_we | ex2_mas7_mas3_we | ex2_mas8_we + | ex2_mas8_mas1_we | ex2_mmucr0_we | ex2_mmucr1_we + | ex2_mmucr2_we | ex2_mmucr3_we | ex2_mmucsr0_we + | ex2_pesr_we | ex2_pid_we | ex2_ppr32_we + | ex2_xucr2_we | ex2_xudbg0_we ); + + assign ex2_sspr_rd_val = ex2_is_mfspr_q & (ex2_slowspr_range | + ex2_acop_re | ex2_axucr0_re | ex2_cpcr0_re + | ex2_cpcr1_re | ex2_cpcr2_re | ex2_cpcr3_re + | ex2_cpcr4_re | ex2_cpcr5_re | ex2_dac1_re + | ex2_dac2_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr2_re | ex2_dbcr3_re | ex2_dscr_re + | ex2_dvc1_re | ex2_dvc2_re | ex2_eheir_re + | ex2_eplc_re | ex2_epsc_re | ex2_eptcfg_re + | ex2_givpr_re | ex2_hacop_re | ex2_iac1_re + | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re + | ex2_immr_re | ex2_imr_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lesr1_re + | ex2_lesr2_re | ex2_lper_re | ex2_lperu_re + | ex2_lpidr_re | ex2_lratcfg_re | ex2_lratps_re + | ex2_lsucr0_re | ex2_mas0_re | ex2_mas0_mas1_re + | ex2_mas1_re | ex2_mas2_re | ex2_mas2u_re + | ex2_mas3_re | ex2_mas4_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas6_re | ex2_mas7_re + | ex2_mas7_mas3_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re + | ex2_mmucr2_re | ex2_mmucr3_re | ex2_mmucsr0_re + | ex2_pesr_re | ex2_pid_re | ex2_ppr32_re + | ex2_sramd_re | ex2_tlb0cfg_re | ex2_tlb0ps_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re ); + + // Illegal SPR checks + assign ex2_sprg8_re = ex2_sprg8_rdec; + assign ex2_gsprg0_rdec = (ex2_instr[11:20] == 10'b1000001011); // 368 + assign ex2_gsprg1_rdec = (ex2_instr[11:20] == 10'b1000101011); // 369 + assign ex2_gsprg2_rdec = (ex2_instr[11:20] == 10'b1001001011); // 370 + assign ex2_gsprg3_rdec = (ex2_instr[11:20] == 10'b1001101011); // 371 + assign ex2_sprg0_rdec = (ex2_instr[11:20] == 10'b1000001000); // 272 + assign ex2_sprg1_rdec = (ex2_instr[11:20] == 10'b1000101000); // 273 + assign ex2_sprg2_rdec = (ex2_instr[11:20] == 10'b1001001000); // 274 + assign ex2_sprg3_rdec = ((ex2_instr[11:20] == 10'b1001101000) | // 275 + (ex2_instr[11:20] == 10'b0001101000)); // 259 + assign ex2_sprg4_rdec = ((ex2_instr[11:20] == 10'b1010001000) | // 276 + (ex2_instr[11:20] == 10'b0010001000)); // 260 + assign ex2_sprg5_rdec = ((ex2_instr[11:20] == 10'b1010101000) | // 277 + (ex2_instr[11:20] == 10'b0010101000)); // 261 + assign ex2_sprg6_rdec = ((ex2_instr[11:20] == 10'b1011001000) | // 278 + (ex2_instr[11:20] == 10'b0011001000)); // 262 + assign ex2_sprg7_rdec = ((ex2_instr[11:20] == 10'b1011101000) | // 279 + (ex2_instr[11:20] == 10'b0011101000)); // 263 + assign ex2_sprg8_rdec = (ex2_instr[11:20] == 10'b1110010010); // 604 + assign ex2_vrsave_rdec = (ex2_instr[11:20] == 10'b0000001000); // 256 + assign ex2_ccr0_rdec = (ex2_instr[11:20] == 10'b1000011111); // 1008 + assign ex2_ccr1_rdec = (ex2_instr[11:20] == 10'b1000111111); // 1009 + assign ex2_ccr2_rdec = (ex2_instr[11:20] == 10'b1001011111); // 1010 + assign ex2_ccr4_rdec = (ex2_instr[11:20] == 10'b1011011010); // 854 + assign ex2_cir_rdec = (ex2_instr[11:20] == 10'b1101101000); // 283 + assign ex2_pir_rdec = (ex2_instr[11:20] == 10'b1111001000); // 286 + assign ex2_pvr_rdec = (ex2_instr[11:20] == 10'b1111101000); // 287 + assign ex2_tb_rdec = (ex2_instr[11:20] == 10'b0110001000); // 268 + assign ex2_tbu_rdec = ((ex2_instr[11:20] == 10'b0110101000)); // 269 + assign ex2_tenc_rdec = (ex2_instr[11:20] == 10'b1011101101); // 439 + assign ex2_tens_rdec = (ex2_instr[11:20] == 10'b1011001101); // 438 + assign ex2_tensr_rdec = (ex2_instr[11:20] == 10'b1010101101); // 437 + assign ex2_tir_rdec = (ex2_instr[11:20] == 10'b1111001101); // 446 + assign ex2_xesr1_rdec = (ex2_instr[11:20] == 10'b1011011100); // 918 + assign ex2_xesr2_rdec = (ex2_instr[11:20] == 10'b1011111100); // 919 + assign ex2_xucr0_rdec = (ex2_instr[11:20] == 10'b1011011111); // 1014 + assign ex2_xucr4_rdec = (ex2_instr[11:20] == 10'b1010111010); // 853 + assign ex2_ccr0_re = ex2_ccr0_rdec; + assign ex2_ccr1_re = ex2_ccr1_rdec; + assign ex2_ccr2_re = ex2_ccr2_rdec; + assign ex2_ccr4_re = ex2_ccr4_rdec; + assign ex2_cir_re = ex2_cir_rdec; + assign ex2_pir_re = ex2_pir_rdec & ~ex2_msr_gs_q[0]; + assign ex2_pvr_re = ex2_pvr_rdec; + assign ex2_tb_re = ex2_tb_rdec; + assign ex2_tbu_re = ex2_tbu_rdec; + assign ex2_tenc_re = ex2_tenc_rdec; + assign ex2_tens_re = ex2_tens_rdec; + assign ex2_tensr_re = ex2_tensr_rdec; + assign ex2_tir_re = ex2_tir_rdec; + assign ex2_xesr1_re = ex2_xesr1_rdec; + assign ex2_xesr2_re = ex2_xesr2_rdec; + assign ex2_xucr0_re = ex2_xucr0_rdec; + assign ex2_xucr4_re = ex2_xucr4_rdec; + assign ex2_ccr0_wdec = ex2_ccr0_rdec; + assign ex2_ccr1_wdec = ex2_ccr1_rdec; + assign ex2_ccr2_wdec = ex2_ccr2_rdec; + assign ex2_ccr4_wdec = ex2_ccr4_rdec; + assign ex2_tbl_wdec = (ex2_instr[11:20] == 10'b1110001000); // 284 + assign ex2_tbu_wdec = ((ex2_instr[11:20] == 10'b1110101000)); // 285 + assign ex2_tenc_wdec = ex2_tenc_rdec; + assign ex2_tens_wdec = ex2_tens_rdec; + assign ex2_trace_wdec = (ex2_instr[11:20] == 10'b0111011111); // 1006 + assign ex2_xesr1_wdec = ex2_xesr1_rdec; + assign ex2_xesr2_wdec = ex2_xesr2_rdec; + assign ex2_xucr0_wdec = ex2_xucr0_rdec; + assign ex2_xucr4_wdec = ex2_xucr4_rdec; + assign ex2_ccr0_we = ex2_ccr0_wdec; + assign ex2_ccr1_we = ex2_ccr1_wdec; + assign ex2_ccr2_we = ex2_ccr2_wdec; + assign ex2_ccr4_we = ex2_ccr4_wdec; + assign ex2_tbl_we = ex2_tbl_wdec; + assign ex2_tbu_we = ex2_tbu_wdec; + assign ex2_tenc_we = ex2_tenc_wdec; + assign ex2_tens_we = ex2_tens_wdec; + assign ex2_trace_we = ex2_trace_wdec; + assign ex2_xesr1_we = ex2_xesr1_wdec; + assign ex2_xesr2_we = ex2_xesr2_wdec; + assign ex2_xucr0_we = ex2_xucr0_wdec; + assign ex2_xucr4_we = ex2_xucr4_wdec; + + generate + if (a2mode == 0 & hvmode == 0) + begin : ill_spr_00 + + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec + | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec + | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec + | ex2_vrsave_rdec | + ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec + | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec + | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec + | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iucr0_rdec + | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec + | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec + | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec + | ex2_lesr2_rdec | ex2_lpidr_rdec | ex2_lsucr0_rdec + | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec + | ex2_sramd_rdec | ex2_xucr2_rdec | ex2_xudbg0_rdec + | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec + | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec + | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec + | ex2_vrsave_wdec | + ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec + | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec + | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec + | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iucr0_wdec + | ex2_iucr1_wdec | ex2_iucr2_wdec | ex2_iudbg0_wdec + | ex2_iulfsr_wdec | ex2_iullcr_wdec | ex2_ivpr_wdec + | ex2_lesr1_wdec | ex2_lesr2_wdec | ex2_lpidr_wdec + | ex2_lsucr0_wdec | ex2_pesr_wdec | ex2_pid_wdec + | ex2_ppr32_wdec | ex2_xucr2_wdec | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr3_re | ex2_eheir_re | ex2_iac1_re + | ex2_iac2_re | ex2_iucr0_re | ex2_iucr1_re + | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re + | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re + | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr3_we | ex2_eheir_we | ex2_iac1_we + | ex2_iac2_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we + | ex2_lsucr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + + end + endgenerate + + generate + if (a2mode == 0 & hvmode == 1) + begin : ill_spr_01 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec + | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec + | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec + | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec + | ex2_sprg8_rdec | ex2_vrsave_rdec | + ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec + | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec + | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec + | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec + | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec + | ex2_iac2_rdec | ex2_iucr0_rdec | ex2_iucr1_rdec + | ex2_iucr2_rdec | ex2_iudbg0_rdec | ex2_iudbg1_rdec + | ex2_iudbg2_rdec | ex2_iulfsr_rdec | ex2_iullcr_rdec + | ex2_ivpr_rdec | ex2_lesr1_rdec | ex2_lesr2_rdec + | ex2_lper_rdec | ex2_lperu_rdec | ex2_lpidr_rdec + | ex2_lratcfg_rdec | ex2_lratps_rdec | ex2_lsucr0_rdec + | ex2_mas0_rdec | ex2_mas0_mas1_rdec | ex2_mas1_rdec + | ex2_mas2_rdec | ex2_mas2u_rdec | ex2_mas3_rdec + | ex2_mas4_rdec | ex2_mas5_rdec | ex2_mas5_mas6_rdec + | ex2_mas6_rdec | ex2_mas7_rdec | ex2_mas7_mas3_rdec + | ex2_mas8_rdec | ex2_mas8_mas1_rdec | ex2_mmucfg_rdec + | ex2_mmucr3_rdec | ex2_mmucsr0_rdec | ex2_pesr_rdec + | ex2_pid_rdec | ex2_ppr32_rdec | ex2_sramd_rdec + | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec | ex2_xucr2_rdec + | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec + | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec + | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec + | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec + | ex2_sprg8_wdec | ex2_vrsave_wdec | + ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec + | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec + | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec + | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec + | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec + | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec + | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec + | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec + | ex2_lper_wdec | ex2_lperu_wdec | ex2_lpidr_wdec + | ex2_lsucr0_wdec | ex2_mas0_wdec | ex2_mas0_mas1_wdec + | ex2_mas1_wdec | ex2_mas2_wdec | ex2_mas2u_wdec + | ex2_mas3_wdec | ex2_mas4_wdec | ex2_mas5_wdec + | ex2_mas5_mas6_wdec | ex2_mas6_wdec | ex2_mas7_wdec + | ex2_mas7_mas3_wdec | ex2_mas8_wdec | ex2_mas8_mas1_wdec + | ex2_mmucr3_wdec | ex2_mmucsr0_wdec | ex2_pesr_wdec + | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec + | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re + | ex2_dbcr3_re | ex2_eheir_re | ex2_eptcfg_re + | ex2_iac1_re | ex2_iac2_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re + | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re + | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucsr0_re | ex2_tlb0cfg_re + | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re + | ex2_xudbg1_re | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we + | ex2_dbcr3_we | ex2_eheir_we | ex2_givpr_we + | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we + | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we + | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we + | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we + | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we + | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 0) + begin : ill_spr_10 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec + | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec + | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec + | ex2_vrsave_rdec | + ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec + | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec + | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec + | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec + | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec + | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iac3_rdec + | ex2_iac4_rdec | ex2_immr_rdec | ex2_imr_rdec + | ex2_iucr0_rdec | ex2_iucr1_rdec | ex2_iucr2_rdec + | ex2_iudbg0_rdec | ex2_iudbg1_rdec | ex2_iudbg2_rdec + | ex2_iulfsr_rdec | ex2_iullcr_rdec | ex2_ivpr_rdec + | ex2_lesr1_rdec | ex2_lesr2_rdec | ex2_lpidr_rdec + | ex2_lsucr0_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec + | ex2_mmucr2_rdec | ex2_pesr_rdec | ex2_pid_rdec + | ex2_ppr32_rdec | ex2_sramd_rdec | ex2_xucr2_rdec + | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec + | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec + | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec + | ex2_vrsave_wdec | + ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec + | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec + | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec + | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec + | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec + | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iac3_wdec + | ex2_iac4_wdec | ex2_immr_wdec | ex2_imr_wdec + | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec + | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec + | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec + | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mmucr0_wdec + | ex2_mmucr1_wdec | ex2_mmucr2_wdec | ex2_pesr_wdec + | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec + | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re + | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re + | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re + | ex2_eheir_re | ex2_iac1_re | ex2_iac2_re + | ex2_iac3_re | ex2_iac4_re | ex2_immr_re + | ex2_imr_re | ex2_iucr0_re | ex2_iucr1_re + | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re + | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re + | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re + | ex2_mmucr0_re | ex2_mmucr1_re | ex2_mmucr2_re + | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re + | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we + | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we + | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we + | ex2_eheir_we | ex2_iac1_we | ex2_iac2_we + | ex2_iac3_we | ex2_iac4_we | ex2_immr_we + | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we + | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we + | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we + | ex2_lsucr0_we | ex2_mmucr0_we | ex2_mmucr1_we + | ex2_mmucr2_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + end + endgenerate + + generate + if (a2mode == 1 & hvmode == 1) + begin : ill_spr_11 + assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( + ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec + | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec + | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec + | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec + | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec + | ex2_xucr0_rdec | ex2_xucr4_rdec | + ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec + | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec + | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec + | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec + | ex2_sprg8_rdec | ex2_vrsave_rdec | + ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec + | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec + | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec + | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec + | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec + | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec + | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec + | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec + | ex2_iac2_rdec | ex2_iac3_rdec | ex2_iac4_rdec + | ex2_immr_rdec | ex2_imr_rdec | ex2_iucr0_rdec + | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec + | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec + | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec + | ex2_lesr2_rdec | ex2_lper_rdec | ex2_lperu_rdec + | ex2_lpidr_rdec | ex2_lratcfg_rdec | ex2_lratps_rdec + | ex2_lsucr0_rdec | ex2_mas0_rdec | ex2_mas0_mas1_rdec + | ex2_mas1_rdec | ex2_mas2_rdec | ex2_mas2u_rdec + | ex2_mas3_rdec | ex2_mas4_rdec | ex2_mas5_rdec + | ex2_mas5_mas6_rdec | ex2_mas6_rdec | ex2_mas7_rdec + | ex2_mas7_mas3_rdec | ex2_mas8_rdec | ex2_mas8_mas1_rdec + | ex2_mmucfg_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec + | ex2_mmucr2_rdec | ex2_mmucr3_rdec | ex2_mmucsr0_rdec + | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec + | ex2_sramd_rdec | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec + | ex2_xucr2_rdec | ex2_xudbg0_rdec | ex2_xudbg1_rdec + | ex2_xudbg2_rdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mfspr_b & ex2_tid)); + + assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( + ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec + | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec + | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec + | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec + | ex2_xucr4_wdec | + ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec + | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec + | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec + | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec + | ex2_sprg8_wdec | ex2_vrsave_wdec | + ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec + | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec + | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec + | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec + | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec + | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec + | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec + | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec + | ex2_iac3_wdec | ex2_iac4_wdec | ex2_immr_wdec + | ex2_imr_wdec | ex2_iucr0_wdec | ex2_iucr1_wdec + | ex2_iucr2_wdec | ex2_iudbg0_wdec | ex2_iulfsr_wdec + | ex2_iullcr_wdec | ex2_ivpr_wdec | ex2_lesr1_wdec + | ex2_lesr2_wdec | ex2_lper_wdec | ex2_lperu_wdec + | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mas0_wdec + | ex2_mas0_mas1_wdec | ex2_mas1_wdec | ex2_mas2_wdec + | ex2_mas2u_wdec | ex2_mas3_wdec | ex2_mas4_wdec + | ex2_mas5_wdec | ex2_mas5_mas6_wdec | ex2_mas6_wdec + | ex2_mas7_wdec | ex2_mas7_mas3_wdec | ex2_mas8_wdec + | ex2_mas8_mas1_wdec | ex2_mmucr0_wdec | ex2_mmucr1_wdec + | ex2_mmucr2_wdec | ex2_mmucr3_wdec | ex2_mmucsr0_wdec + | ex2_pesr_wdec | ex2_pid_wdec | ex2_ppr32_wdec + | ex2_xucr2_wdec | ex2_xudbg0_wdec | + ex2_slowspr_range | + |(tspr_cspr_illeg_mtspr_b & ex2_tid)); + + assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( + ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re + | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re + | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re + | ex2_xucr4_re | + ex2_sprg8_re | + ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re + | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re + | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re + | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re + | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re + | ex2_eheir_re | ex2_eptcfg_re | ex2_iac1_re + | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re + | ex2_immr_re | ex2_imr_re | ex2_iucr0_re + | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re + | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re + | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re + | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re + | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re + | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re + | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re + | ex2_mmucr2_re | ex2_mmucsr0_re | ex2_tlb0cfg_re + | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re + | ex2_xudbg1_re | ex2_xudbg2_re | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mfspr & ex2_tid)); + + assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( + ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we + | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we + | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we + | ex2_xucr4_we | + ex2_sprg8_we | + ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we + | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we + | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we + | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we + | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we + | ex2_eheir_we | ex2_givpr_we | ex2_hacop_we + | ex2_iac1_we | ex2_iac2_we | ex2_iac3_we + | ex2_iac4_we | ex2_immr_we | ex2_imr_we + | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we + | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we + | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we + | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we + | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we + | ex2_mmucr0_we | ex2_mmucr1_we | ex2_mmucr2_we + | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | + ex2_slowspr_range_hypv | + |(tspr_cspr_hypv_mtspr & ex2_tid)); + end + endgenerate + + assign ex1_dnh = ex1_valid & ex1_is_dnh & spr_ccr4_en_dnh; + + assign ex3_wait_flush_d = |ex2_wait_flush; + + assign ex2_np1_flush = (ex2_ccr0_flush | ex2_tenc_flush | ex2_xucr0_flush) & ex2_tid; + + assign ex3_np1_flush_d = (|tspr_cspr_ex2_np1_flush) | |(ex2_np1_flush) | ex2_dnh_q | (ex2_is_mtspr_q & (ex2_ccr2_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec |ex2_pid_wdec | ex2_lpidr_wdec | ex2_mmucr1_wdec | ex2_xucr0_wdec | ex2_iucr2_wdec | ex2_mmucsr0_wdec)) | ex2_is_mtmsr_q; + + assign ex4_np1_flush_d = ex3_spr_we & ex3_np1_flush_q; + assign ex4_wait_flush_d = ex3_spr_we & ex3_wait_flush_q; + + assign ex2_msr_pr = |(ex2_tid & tspr_msr_pr); + assign ex2_msr_gs = |(ex2_tid & tspr_msr_gs); + + assign ex3_hypv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (~ex2_msr_pr) & ex2_msr_gs & (ex2_hypv_mfspr | ex2_hypv_mtspr | ex2_hypv_instr_q); + + assign ex3_illeg_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (((ex2_illeg_mfspr | ex2_illeg_mtspr | ex2_illeg_mftb) & ~(ex2_instr_q[11] & ex2_msr_pr)) | (ex2_hypv_instr_q & ~spr_ccr2_en_pc)); + + assign ex3_priv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & ex2_msr_pr & ((ex2_instr_q[11] & (ex2_is_mtspr_q | ex2_is_mfspr_q)) | ex2_priv_instr_q); + + assign spr_ccr0_pme = ccr0_q[62:63]; + assign spr_ccr0_we = ccr0_we; + assign spr_ccr2_en_dcr = spr_ccr2_en_dcr_int; + assign spr_ccr2_en_dcr_int = ccr2_q[32]; + assign spr_ccr2_en_trace = ccr2_q[33]; + assign spr_ccr2_en_pc = ccr2_q[34]; + assign spr_ccr2_ifratsc = ccr2_q[35:43]; + assign spr_ccr2_ifrat = ccr2_q[44]; + assign spr_ccr2_dfratsc = ccr2_q[45:53]; + assign spr_ccr2_dfrat = ccr2_q[54]; + assign spr_ccr2_ucode_dis = ccr2_q[55]; + assign spr_ccr2_ap = ccr2_q[56:59]; + assign spr_ccr2_en_attn = ccr2_q[60]; + assign spr_ccr2_en_ditc = ccr2_q[61]; + assign spr_ccr2_en_icswx = ccr2_q[62]; + assign spr_ccr2_notlb = ccr2_q[63]; + assign spr_ccr4_en_dnh = ccr4_q[63]; + assign spr_tens_ten = tens_q[64-(`THREADS):63]; + assign spr_xucr0_clkg_ctl = xucr0_q[38:42]; + assign spr_xucr0_trace_um = xucr0_q[43:46]; + assign xu_lsu_spr_xucr0_mbar_ack = xucr0_q[47]; + assign xu_lsu_spr_xucr0_tlbsync = xucr0_q[48]; + assign spr_xucr0_cls = xucr0_q[49]; + assign xu_lsu_spr_xucr0_aflsta = xucr0_q[50]; + assign spr_xucr0_mddp = xucr0_q[51]; + assign xu_lsu_spr_xucr0_cred = xucr0_q[52]; + assign xu_lsu_spr_xucr0_rel = xucr0_q[53]; + assign spr_xucr0_mdcp = xucr0_q[54]; + assign spr_xucr0_tcs = xucr0_q[55]; + assign xu_lsu_spr_xucr0_flsta = xucr0_q[56]; + assign xu_lsu_spr_xucr0_l2siw = xucr0_q[57]; + assign xu_lsu_spr_xucr0_flh2l2 = xucr0_q[58]; + assign xu_lsu_spr_xucr0_dcdis = xucr0_q[59]; + assign xu_lsu_spr_xucr0_wlk = xucr0_q[60]; + assign spr_xucr4_mmu_mchk = xucr4_q[60]; + assign spr_xucr4_mddmh = xucr4_q[61]; + assign spr_xucr4_tcd = xucr4_q[62:63]; + assign xucr0_clfc_d = ex3_xucr0_we & ex3_spr_wd[63]; + assign xu_lsu_spr_xucr0_clfc = xucr0_clfc_q; + assign cspr_ccr2_en_pc = spr_ccr2_en_pc; + assign cspr_ccr4_en_dnh = spr_ccr4_en_dnh; + + // CCR0 + assign ex3_ccr0_di = { ex3_spr_wd[32:33] }; //PME + + assign ccr0_do = { tidn[0:0] , + tidn[0:31] , ///// + ccr0_q[62:63] , //PME + tidn[34:51] , ///// + 4'b0000 , //WEM + tidn[56:59] , ///// + ccr0_we }; //WE + // CCR1 + assign ex3_ccr1_di = { ex3_spr_wd[34:39] , //WC3 + ex3_spr_wd[42:47] , //WC2 + ex3_spr_wd[50:55] , //WC1 + ex3_spr_wd[58:63] }; //WC0 + + assign ccr1_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:33] , ///// + ccr1_q[40:45] , //WC3 + tidn[40:41] , ///// + ccr1_q[46:51] , //WC2 + tidn[48:49] , ///// + ccr1_q[52:57] , //WC1 + tidn[56:57] , ///// + ccr1_q[58:63] }; //WC0 + // CCR2 + assign ex3_ccr2_di = { ex3_spr_wd[32:32] , //EN_DCR + ex3_spr_wd[33:33] , //EN_TRACE + ex3_spr_wd[34:34] , //EN_PC + ex3_spr_wd[35:43] , //IFRATSC + ex3_spr_wd[44:44] , //IFRAT + ex3_spr_wd[45:53] , //DFRATSC + ex3_spr_wd[54:54] , //DFRAT + ex3_spr_wd[55:55] , //UCODE_DIS + ex3_spr_wd[56:59] , //AP + ex3_spr_wd[60:60] , //EN_ATTN + ex3_spr_wd[61:61] , //EN_DITC + ex3_spr_wd[62:62] , //EN_ICSWX + ex3_spr_wd[63:63] }; //NOTLB + + assign ccr2_do = { tidn[0:0] , + tidn[0:31] , ///// + ccr2_q[32:32] , //EN_DCR + ccr2_q[33:33] , //EN_TRACE + ccr2_q[34:34] , //EN_PC + ccr2_q[35:43] , //IFRATSC + ccr2_q[44:44] , //IFRAT + ccr2_q[45:53] , //DFRATSC + ccr2_q[54:54] , //DFRAT + ccr2_q[55:55] , //UCODE_DIS + ccr2_q[56:59] , //AP + ccr2_q[60:60] , //EN_ATTN + ccr2_q[61:61] , //EN_DITC + ccr2_q[62:62] , //EN_ICSWX + ccr2_q[63:63] }; //NOTLB + // CCR4 + assign ex3_ccr4_di = { ex3_spr_wd[63:63] }; //EN_DNH + + assign ccr4_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:62] , ///// + ccr4_q[63:63] }; //EN_DNH + // CIR + assign cir_do = { tidn[0:0] , + tidn[0:31] , ///// + an_ac_chipid_dc[32:35] , //ID + tidn[36:63] }; ///// + // PIR + assign pir_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:53] , ///// + an_ac_coreid_q[54:61] , //CID + ex2_tid_q[0:1] }; //TID + // PVR + assign pvr_do = { tidn[0:0] , + tidn[0:31] , ///// + version[32:47] , //VERSION + revision[48:63] }; //REVISION + // TB + assign tb_do = { tidn[0:0] , + tbu_q[32:63] , //TBU + tbl_q[32:63] }; //TBL + // TBL + assign ex3_tbl_di = { ex3_spr_wd[32:63] }; //TBL + + assign tbl_do = { tidn[0:0] , + tidn[0:31] , ///// + tbl_q[32:63] }; //TBL + // TBU + assign ex3_tbu_di = { ex3_spr_wd[32:63] }; //TBU + + assign tbu_do = { tidn[0:0] , + tidn[0:31] , ///// + tbu_q[32:63] }; //TBU + // TENC + assign tenc_do = { tidn[0:64-`THREADS] , + tens_q[64-`THREADS:63] }; //TEN + // TENS + assign ex3_tens_di = { ex3_spr_wd[64-(`THREADS):63] }; //TEN + + assign tens_do = { tidn[0:64-(`THREADS)] , + tens_q[64-(`THREADS):63] }; //TEN + // TENSR + assign tensr_do = { tidn[0:64-`THREADS] , + spr_tensr[0:`THREADS-1] }; //TENSR + // TIR + assign tir_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:61] , ///// + ex2_tid_q[0:1] }; //TID + // XESR1 + assign ex3_xesr1_di = { ex3_spr_wd[32:35] , //MUXSELEB0 + ex3_spr_wd[36:39] , //MUXSELEB1 + ex3_spr_wd[40:43] , //MUXSELEB2 + ex3_spr_wd[44:47] , //MUXSELEB3 + ex3_spr_wd[48:51] , //MUXSELEB4 + ex3_spr_wd[52:55] , //MUXSELEB5 + ex3_spr_wd[56:59] , //MUXSELEB6 + ex3_spr_wd[60:63] }; //MUXSELEB7 + + assign xesr1_do = { tidn[0:0] , + tidn[0:31] , ///// + xesr1_q[32:35] , //MUXSELEB0 + xesr1_q[36:39] , //MUXSELEB1 + xesr1_q[40:43] , //MUXSELEB2 + xesr1_q[44:47] , //MUXSELEB3 + xesr1_q[48:51] , //MUXSELEB4 + xesr1_q[52:55] , //MUXSELEB5 + xesr1_q[56:59] , //MUXSELEB6 + xesr1_q[60:63] }; //MUXSELEB7 + // XESR2 + assign ex3_xesr2_di = { ex3_spr_wd[32:35] , //MUXSELEB0 + ex3_spr_wd[36:39] , //MUXSELEB1 + ex3_spr_wd[40:43] , //MUXSELEB2 + ex3_spr_wd[44:47] , //MUXSELEB3 + ex3_spr_wd[48:51] , //MUXSELEB4 + ex3_spr_wd[52:55] , //MUXSELEB5 + ex3_spr_wd[56:59] , //MUXSELEB6 + ex3_spr_wd[60:63] }; //MUXSELEB7 + + assign xesr2_do = { tidn[0:0] , + tidn[0:31] , ///// + xesr2_q[32:35] , //MUXSELEB0 + xesr2_q[36:39] , //MUXSELEB1 + xesr2_q[40:43] , //MUXSELEB2 + xesr2_q[44:47] , //MUXSELEB3 + xesr2_q[48:51] , //MUXSELEB4 + xesr2_q[52:55] , //MUXSELEB5 + xesr2_q[56:59] , //MUXSELEB6 + xesr2_q[60:63] }; //MUXSELEB7 + // XUCR0 + assign ex3_xucr0_di = { ex3_spr_wd[32:36] , //CLKG_CTL + ex3_spr_wd[37:40] , //TRACE_UM + ex3_spr_wd[41:41] , //MBAR_ACK + ex3_spr_wd[42:42] , //TLBSYNC + xucr0_q[49:49] , //CLS + ex3_spr_wd[49:49] , //AFLSTA + ex3_spr_wd[50:50] , //MDDP + ex3_spr_wd[51:51] , //CRED + xucr0_q[53:53] , //REL + ex3_spr_wd[53:53] , //MDCP + ex3_spr_wd[54:54] , //TCS + ex3_spr_wd[55:55] , //FLSTA + xucr0_q[57:57] , //L2SIW + xucr0_q[58:58] , //FLH2L2 + ex3_spr_wd[58:58] , //DCDIS + ex3_spr_wd[59:59] , //WLK + ex3_spr_wd[60:60] , //CSLC + ex3_spr_wd[61:61] , //CUL + ex3_spr_wd[62:62] }; //CLO + + assign xucr0_do = { tidn[0:0] , + tidn[0:31] , ///// + xucr0_q[38:42] , //CLKG_CTL + xucr0_q[43:46] , //TRACE_UM + xucr0_q[47:47] , //MBAR_ACK + xucr0_q[48:48] , //TLBSYNC + tidn[43:47] , ///// + xucr0_q[49:49] , //CLS + xucr0_q[50:50] , //AFLSTA + xucr0_q[51:51] , //MDDP + xucr0_q[52:52] , //CRED + xucr0_q[53:53] , //REL + xucr0_q[54:54] , //MDCP + xucr0_q[55:55] , //TCS + xucr0_q[56:56] , //FLSTA + xucr0_q[57:57] , //L2SIW + xucr0_q[58:58] , //FLH2L2 + xucr0_q[59:59] , //DCDIS + xucr0_q[60:60] , //WLK + xucr0_q[61:61] , //CSLC + xucr0_q[62:62] , //CUL + xucr0_q[63:63] , //CLO + 1'b0 }; //CLFC + // XUCR4 + assign ex3_xucr4_di = { ex3_spr_wd[46:46] , //MMU_MCHK + ex3_spr_wd[47:47] , //MDDMH + ex3_spr_wd[56:57] }; //TCD + + assign xucr4_do = { tidn[0:0] , + tidn[0:31] , ///// + tidn[32:45] , ///// + xucr4_q[60:60] , //MMU_MCHK + xucr4_q[61:61] , //MDDMH + tidn[48:55] , ///// + xucr4_q[62:63] , //TCD + tidn[58:63] }; ///// + + // Unused Signals + assign unused_do_bits = |{ + ccr0_do[0:64-`GPR_WIDTH] + ,ccr1_do[0:64-`GPR_WIDTH] + ,ccr2_do[0:64-`GPR_WIDTH] + ,ccr4_do[0:64-`GPR_WIDTH] + ,cir_do[0:64-`GPR_WIDTH] + ,pir_do[0:64-`GPR_WIDTH] + ,pvr_do[0:64-`GPR_WIDTH] + ,tb_do[0:64-`GPR_WIDTH] + ,tbl_do[0:64-`GPR_WIDTH] + ,tbu_do[0:64-`GPR_WIDTH] + ,tenc_do[0:64-`GPR_WIDTH] + ,tens_do[0:64-`GPR_WIDTH] + ,tensr_do[0:64-`GPR_WIDTH] + ,tir_do[0:64-`GPR_WIDTH] + ,xesr1_do[0:64-`GPR_WIDTH] + ,xesr2_do[0:64-`GPR_WIDTH] + ,xucr0_do[0:64-`GPR_WIDTH] + ,xucr4_do[0:64-`GPR_WIDTH] + }; + + tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr0_act), + .force_t(bcfg_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(bcfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), + .scout(sov_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), + .din(ccr0_d), + .dout(ccr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(24), .INIT(3994575), .NEEDS_SRESET(1)) ccr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ccr1_offset:ccr1_offset + 24 - 1]), + .scout(sov[ccr1_offset:ccr1_offset + 24 - 1]), + .din(ccr1_d), + .dout(ccr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) ccr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr2_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), + .scout(sov_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), + .din(ccr2_d), + .dout(ccr2_q) + ); + tri_ser_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccr4_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(ccr4_act), + .force_t(ccfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), + .scout(sov_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), + .din(ccr4_d), + .dout(ccr4_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbl_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tbl_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tbl_offset:tbl_offset + 32 - 1]), + .scout(sov[tbl_offset:tbl_offset + 32 - 1]), + .din(tbl_d), + .dout(tbl_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbu_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tbu_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tbu_offset:tbu_offset + 32 - 1]), + .scout(sov[tbu_offset:tbu_offset + 32 - 1]), + .din(tbu_d), + .dout(tbu_q) + ); + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) tens_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(tens_act), + .force_t(bcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(bcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), + .scout(sov_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), + .din(tens_d), + .dout(tens_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr1_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xesr1_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xesr1_offset:xesr1_offset + 32 - 1]), + .scout(sov[xesr1_offset:xesr1_offset + 32 - 1]), + .din(xesr1_d), + .dout(xesr1_q) + ); + tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr2_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xesr2_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xesr2_offset:xesr2_offset + 32 - 1]), + .scout(sov[xesr2_offset:xesr2_offset + 32 - 1]), + .din(xesr2_d), + .dout(xesr2_q) + ); + tri_ser_rlmreg_p #(.WIDTH(26), .INIT((spr_xucr0_init)), .NEEDS_SRESET(1)) xucr0_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr0_act), + .force_t(ccfg_slp_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(ccfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), + .scout(sov_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), + .din(xucr0_d), + .dout(xucr0_q) + ); + tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xucr4_latch( + .nclk(nclk),.vd(vdd),.gd(gnd), + .act(xucr4_act), + .force_t(dcfg_sl_force), + .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), + .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), + .thold_b(dcfg_sl_thold_0_b), + .sg(sg_0), + .scin(siv_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), + .scout(sov_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), + .din(xucr4_d), + .dout(xucr4_q) + ); + + + + // Latch Instances + tri_rlmreg_p #(.WIDTH(4), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[exx_act_offset : exx_act_offset + 4-1]), + .scout(sov[exx_act_offset : exx_act_offset + 4-1]), + .din(exx_act_d), + .dout(exx_act_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), + .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .scout(sov[ex0_val_offset : ex0_val_offset + `THREADS-1]), + .din(rv2_val), + .dout(ex0_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .scout(sov[ex1_val_offset : ex1_val_offset + `THREADS-1]), + .din(ex0_val), + .dout(ex1_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_aspr_act_offset]), + .scout(sov[ex1_aspr_act_offset]), + .din(ex1_aspr_act_d), + .dout(ex1_aspr_act_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), + .scout(sov[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), + .din(ex1_aspr_tid_d), + .dout(ex1_aspr_tid_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_tid_offset : ex1_tid_offset + 2-1]), + .scout(sov[ex1_tid_offset : ex1_tid_offset + 2-1]), + .din(ex0_tid), + .dout(ex1_tid_q) + ); + tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_instr_offset : ex1_instr_offset + 32-1]), + .scout(sov[ex1_instr_offset : ex1_instr_offset + 32-1]), + .din(rv_xu_ex0_instr), + .dout(ex1_instr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex1_msr_gs_offset]), + .scout(sov[ex1_msr_gs_offset]), + .din(ex1_msr_gs_d), + .dout(ex1_msr_gs_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .scout(sov[ex2_val_offset : ex2_val_offset + `THREADS-1]), + .din(ex1_val), + .dout(ex2_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_rd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_rd_offset]), + .scout(sov[ex2_val_rd_offset]), + .din(ex2_val_rd_d), + .dout(ex2_val_rd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_wr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_val_wr_offset]), + .scout(sov[ex2_val_wr_offset]), + .din(ex2_val_wr_d), + .dout(ex2_val_wr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_tid_offset : ex2_tid_offset + 2-1]), + .scout(sov[ex2_tid_offset : ex2_tid_offset + 2-1]), + .din(ex1_tid_q), + .dout(ex2_tid_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), + .scout(sov[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), + .din(ex1_aspr_addr), + .dout(ex2_aspr_addr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mfspr_offset]), + .scout(sov[ex2_is_mfspr_offset]), + .din(ex1_is_mfspr), + .dout(ex2_is_mfspr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mftb_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mftb_offset]), + .scout(sov[ex2_is_mftb_offset]), + .din(ex1_is_mftb), + .dout(ex2_is_mftb_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtmsr_offset]), + .scout(sov[ex2_is_mtmsr_offset]), + .din(ex2_is_mtmsr_d), + .dout(ex2_is_mtmsr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_mtspr_offset]), + .scout(sov[ex2_is_mtspr_offset]), + .din(ex1_is_mtspr), + .dout(ex2_is_mtspr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_wait_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_wait_offset]), + .scout(sov[ex2_is_wait_offset]), + .din(ex1_is_wait), + .dout(ex2_is_wait_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_priv_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_priv_instr_offset]), + .scout(sov[ex2_priv_instr_offset]), + .din(ex1_priv_instr), + .dout(ex2_priv_instr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_hypv_instr_offset]), + .scout(sov[ex2_hypv_instr_offset]), + .din(ex1_hypv_instr), + .dout(ex2_hypv_instr_q) + ); + tri_regk #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex2_wait_wc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), + .scout(sov[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), + .din(ex1_instr_q[9:10]), + .dout(ex2_wait_wc_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_msgclr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_is_msgclr_offset]), + .scout(sov[ex2_is_msgclr_offset]), + .din(ex1_is_msgclr), + .dout(ex2_is_msgclr_q) + ); + tri_regk #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_instr_offset : ex2_instr_offset + 10-1]), + .scout(sov[ex2_instr_offset : ex2_instr_offset + 10-1]), + .din(ex2_instr_d), + .dout(ex2_instr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_msr_gs_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_msr_gs_offset]), + .scout(sov[ex2_msr_gs_offset]), + .din(ex1_msr_gs_q), + .dout(ex2_msr_gs_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tenc_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_tenc_we_offset]), + .scout(sov[ex2_tenc_we_offset]), + .din(ex1_tenc_we), + .dout(ex2_tenc_we_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ccr0_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_ccr0_we_offset]), + .scout(sov[ex2_ccr0_we_offset]), + .din(ex1_ccr0_we), + .dout(ex2_ccr0_we_q) + ); + tri_regk #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex1_aspr_re), + .dout(ex2_aspr_re_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex2_dnh_offset]), + .scout(sov[ex2_dnh_offset]), + .din(ex1_dnh), + .dout(ex2_dnh_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .scout(sov[ex3_val_offset : ex3_val_offset + `THREADS-1]), + .din(ex2_val), + .dout(ex3_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_rd_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_val_rd_offset]), + .scout(sov[ex3_val_rd_offset]), + .din(ex3_val_rd_d), + .dout(ex3_val_rd_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_wr_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sspr_wr_val_offset]), + .scout(sov[ex3_sspr_wr_val_offset]), + .din(ex2_sspr_wr_val), + .dout(ex3_sspr_wr_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_rd_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_sspr_rd_val_offset]), + .scout(sov[ex3_sspr_rd_val_offset]), + .din(ex2_sspr_rd_val), + .dout(ex3_sspr_rd_val_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_spr_we_offset]), + .scout(sov[ex3_spr_we_offset]), + .din(ex3_spr_we_d), + .dout(ex3_spr_we_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_aspr_we_offset]), + .scout(sov[ex3_aspr_we_offset]), + .din(ex3_aspr_we_d), + .dout(ex3_aspr_we_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex2_aspr_addr_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), + .scout(sov[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), + .din(ex3_aspr_addr_d), + .dout(ex3_aspr_addr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_tid_offset : ex3_tid_offset + 2-1]), + .scout(sov[ex3_tid_offset : ex3_tid_offset + 2-1]), + .din(ex2_tid_q), + .dout(ex3_tid_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_rdata_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), + .scout(sov[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), + .din(ex3_aspr_rdata_d), + .dout(ex3_aspr_rdata_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_mtspr_offset]), + .scout(sov[ex3_is_mtspr_offset]), + .din(ex2_is_mtspr_q), + .dout(ex3_is_mtspr_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex3_wait_wc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), + .scout(sov[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), + .din(ex2_wait_wc_q), + .dout(ex3_wait_wc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_msgclr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_is_msgclr_offset]), + .scout(sov[ex3_is_msgclr_offset]), + .din(ex2_is_msgclr_q), + .dout(ex3_is_msgclr_q) + ); + tri_rlmreg_p #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_instr_offset : ex3_instr_offset + 10-1]), + .scout(sov[ex3_instr_offset : ex3_instr_offset + 10-1]), + .din(ex3_instr_d), + .dout(ex3_instr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_cspr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), + .din(ex2_cspr_rt), + .dout(ex3_cspr_rt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_hypv_spr_offset]), + .scout(sov[ex3_hypv_spr_offset]), + .din(ex3_hypv_spr_d), + .dout(ex3_hypv_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_illeg_spr_offset]), + .scout(sov[ex3_illeg_spr_offset]), + .din(ex3_illeg_spr_d), + .dout(ex3_illeg_spr_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_priv_spr_offset]), + .scout(sov[ex3_priv_spr_offset]), + .din(ex3_priv_spr_d), + .dout(ex3_priv_spr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_rt_act), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), + .scout(sov[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), + .din(ex3_rt_d), + .dout(ex3_rt_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_wait_offset]), + .scout(sov[ex3_wait_offset]), + .din(ex2_is_wait_q), + .dout(ex3_wait_q) + ); + tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_ce_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), + .scout(sov[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), + .din(ex2_aspr_addr_q), + .dout(ex3_aspr_ce_addr_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex2_aspr_re_q), + .dout(ex3_aspr_re_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .scout(sov[ex4_val_offset : ex4_val_offset + `THREADS-1]), + .din(ex3_val), + .dout(ex4_val_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_re_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), + .scout(sov[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), + .din(ex3_aspr_re_q), + .dout(ex4_aspr_re_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_spr_rt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), + .din(ex3_spr_rt), + .dout(ex4_spr_rt_q) + ); + tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_corr_rdata_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act_data[3]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), + .scout(sov[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), + .din(ex3_corr_rdata), + .dout(ex4_corr_rdata_q) + ); + tri_regk #(.WIDTH(`GPR_WIDTH/8+1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), + .scout(sov[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), + .din(ex4_sprg_ce_d), + .dout(ex4_sprg_ce_q) + ); + tri_regk #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_ce_addr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(ex3_sprg_ce), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), + .scout(sov[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), + .din(ex3_aspr_ce_addr_q), + .dout(ex4_aspr_ce_addr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_hypv_spr_offset]), + .scout(sov[ex4_hypv_spr_offset]), + .din(ex3_hypv_spr_q), + .dout(ex4_hypv_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_illeg_spr_offset]), + .scout(sov[ex4_illeg_spr_offset]), + .din(ex3_illeg_spr_q), + .dout(ex4_illeg_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_priv_spr_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_priv_spr_offset]), + .scout(sov[ex4_priv_spr_offset]), + .din(ex3_priv_spr_q), + .dout(ex4_priv_spr_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[3]), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_np1_flush_offset]), + .scout(sov[ex4_np1_flush_offset]), + .din(ex4_np1_flush_d), + .dout(ex4_np1_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), + .scout(sov[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), + .din(ex4_sprg_ce), + .dout(ex5_sprg_ce_q) + ); + tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ue_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_nsl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_nsl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sprg_ue_offset]), + .scout(sov[ex4_sprg_ue_offset]), + .din(ex4_sprg_ue_d), + .dout(ex4_sprg_ue_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ue_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), + .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), + .scout(sov[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), + .din(ex4_sprg_ue), + .dout(ex5_sprg_ue_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_dbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), + .din(iu_xu_dbell_taken), + .dout(cpl_dbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_cdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), + .din(iu_xu_cdbell_taken), + .dout(cpl_cdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gdbell_taken), + .dout(cpl_gdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gcdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gcdbell_taken), + .dout(cpl_gcdbell_taken_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gmcdbell_taken_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), + .scout(sov[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), + .din(iu_xu_gmcdbell_taken), + .dout(cpl_gmcdbell_taken_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cslc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_cslc_offset]), + .scout(sov[set_xucr0_cslc_offset]), + .din(set_xucr0_cslc_d), + .dout(set_xucr0_cslc_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cul_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_cul_offset]), + .scout(sov[set_xucr0_cul_offset]), + .din(set_xucr0_cul_d), + .dout(set_xucr0_cul_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_clo_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[set_xucr0_clo_offset]), + .scout(sov[set_xucr0_clo_offset]), + .din(set_xucr0_clo_d), + .dout(set_xucr0_clo_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_np1_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[2]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex3_np1_flush_offset]), + .scout(sov[ex3_np1_flush_offset]), + .din(ex3_np1_flush_d), + .dout(ex3_np1_flush_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) running_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[running_offset : running_offset + `THREADS-1]), + .scout(sov[running_offset : running_offset + `THREADS-1]), + .din(running_d), + .dout(running_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(2**(`THREADS-1)), .NEEDS_SRESET(1)) llpri_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(llpri_inc), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[llpri_offset : llpri_offset + `THREADS-1]), + .scout(sov[llpri_offset : llpri_offset + `THREADS-1]), + .din(llpri_d), + .dout(llpri_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dec_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), + .scout(sov[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), + .din(dec_dbg_dis_d), + .dout(dec_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_dbg_dis_offset]), + .scout(sov[tb_dbg_dis_offset]), + .din(tb_dbg_dis_d), + .dout(tb_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_act_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_act_offset]), + .scout(sov[tb_act_offset]), + .din(tb_act_d), + .dout(tb_act_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ext_dbg_dis_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), + .scout(sov[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), + .din(ext_dbg_dis_d), + .dout(ext_dbg_dis_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[msrovride_enab_offset]), + .scout(sov[msrovride_enab_offset]), + .din(pc_xu_msrovride_enab), + .dout(msrovride_enab_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitimpl_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), + .scout(sov[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), + .din(waitimpl_val_d), + .dout(waitimpl_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitrsv_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), + .scout(sov[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), + .din(waitrsv_val_d), + .dout(waitrsv_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_reservation_vld_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), + .scout(sov[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), + .din(an_ac_reservation_vld), + .dout(an_ac_reservation_vld_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_sleep_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), + .scout(sov[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), + .din(an_ac_sleep_en), + .dout(an_ac_sleep_en_q) + ); + tri_rlmreg_p #(.WIDTH(8), .OFFSET(54),.INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), + .scout(sov[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), + .din(an_ac_coreid), + .dout(an_ac_coreid_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_enable_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_enable_offset]), + .scout(sov[tb_update_enable_offset]), + .din(an_ac_tb_update_enable), + .dout(tb_update_enable_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_pulse_offset]), + .scout(sov[tb_update_pulse_offset]), + .din(an_ac_tb_update_pulse), + .dout(tb_update_pulse_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_1_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[tb_update_pulse_1_offset]), + .scout(sov[tb_update_pulse_1_offset]), + .din(tb_update_pulse_q), + .dout(tb_update_pulse_1_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_wd_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_wd_complete_offset]), + .scout(sov[pc_xu_reset_wd_complete_offset]), + .din(pc_xu_reset_wd_complete), + .dout(pc_xu_reset_wd_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_3_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_3_complete_offset]), + .scout(sov[pc_xu_reset_3_complete_offset]), + .din(pc_xu_reset_3_complete), + .dout(pc_xu_reset_3_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_2_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_2_complete_offset]), + .scout(sov[pc_xu_reset_2_complete_offset]), + .din(pc_xu_reset_2_complete), + .dout(pc_xu_reset_2_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_1_complete_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_reset_1_complete_offset]), + .scout(sov[pc_xu_reset_1_complete_offset]), + .din(pc_xu_reset_1_complete), + .dout(pc_xu_reset_1_complete_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_val_offset]), + .scout(sov[lq_xu_dbell_val_offset]), + .din(lq_xu_dbell_val), + .dout(lq_xu_dbell_val_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_type_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), + .scout(sov[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), + .din(lq_xu_dbell_type), + .dout(lq_xu_dbell_type_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_brdcast_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_brdcast_offset]), + .scout(sov[lq_xu_dbell_brdcast_offset]), + .din(lq_xu_dbell_brdcast), + .dout(lq_xu_dbell_brdcast_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_lpid_match_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[lq_xu_dbell_lpid_match_offset]), + .scout(sov[lq_xu_dbell_lpid_match_offset]), + .din(lq_xu_dbell_lpid_match), + .dout(lq_xu_dbell_lpid_match_q) + ); + tri_rlmreg_p #(.WIDTH(14), .OFFSET(50),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_pirtag_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), + .scout(sov[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), + .din(lq_xu_dbell_pirtag), + .dout(lq_xu_dbell_pirtag_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dbell_present_offset : dbell_present_offset + `THREADS-1]), + .scout(sov[dbell_present_offset : dbell_present_offset + `THREADS-1]), + .din(dbell_present_d), + .dout(dbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), + .scout(sov[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), + .din(cdbell_present_d), + .dout(cdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), + .scout(sov[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), + .din(gdbell_present_d), + .dout(gdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), + .scout(sov[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), + .din(gcdbell_present_d), + .dout(gcdbell_present_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_present_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), + .scout(sov[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), + .din(gmcdbell_present_d), + .dout(gmcdbell_present_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clfc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xucr0_clfc_offset]), + .scout(sov[xucr0_clfc_offset]), + .din(xucr0_clfc_d), + .dout(xucr0_clfc_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_run_thread_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), + .scout(sov[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), + .din(iu_run_thread_d), + .dout(iu_run_thread_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) inj_sprg_ecc_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), + .scout(sov[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), + .din(pc_xu_inj_sprg_ecc), + .dout(inj_sprg_ecc_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), + .scout(sov[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), + .din(dbell_interrupt), + .dout(dbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), + .scout(sov[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), + .din(cdbell_interrupt), + .dout(cdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), + .din(gdbell_interrupt), + .dout(gdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), + .din(gcdbell_interrupt), + .dout(gcdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_interrupt_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), + .scout(sov[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), + .din(gmcdbell_interrupt), + .dout(gmcdbell_interrupt_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), + .scout(sov[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), + .din(iu_xu_quiesce), + .dout(iu_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_icache_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), + .scout(sov[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), + .din(iu_xu_icache_quiesce), + .dout(iu_icache_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lsu_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), + .scout(sov[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), + .din(lq_xu_quiesce), + .dout(lsu_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), + .scout(sov[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), + .din(mm_xu_quiesce), + .dout(mm_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) bx_quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), + .scout(sov[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), + .din(bx_xu_quiesce), + .dout(bx_quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesce_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[quiesce_offset : quiesce_offset + `THREADS-1]), + .scout(sov[quiesce_offset : quiesce_offset + `THREADS-1]), + .din(quiesce_d), + .dout(quiesce_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesced_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[quiesced_offset : quiesced_offset + `THREADS-1]), + .scout(sov[quiesced_offset : quiesced_offset + `THREADS-1]), + .din(quiesced_d), + .dout(quiesced_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) instr_trace_mode_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[instr_trace_mode_offset]), + .scout(sov[instr_trace_mode_offset]), + .din(pc_xu_instr_trace_mode), + .dout(instr_trace_mode_q) + ); + tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) instr_trace_tid_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), + .scout(sov[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), + .din(pc_xu_instr_trace_tid), + .dout(instr_trace_tid_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) timer_update_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[timer_update_offset]), + .scout(sov[timer_update_offset]), + .din(timer_update_int), + .dout(timer_update_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_read_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xu_ord_read_done_offset]), + .scout(sov[spr_xu_ord_read_done_offset]), + .din(spr_xu_ord_read_done_d), + .dout(spr_xu_ord_read_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_write_done_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[spr_xu_ord_write_done_offset]), + .scout(sov[spr_xu_ord_write_done_offset]), + .din(spr_xu_ord_write_done_d), + .dout(spr_xu_ord_write_done_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_spr_ord_ready_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[xu_spr_ord_ready_offset]), + .scout(sov[xu_spr_ord_ready_offset]), + .din(xu_spr_ord_ready), + .dout(xu_spr_ord_ready_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sspr_val_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[ex4_sspr_val_offset]), + .scout(sov[ex4_sspr_val_offset]), + .din(ex3_sspr_val), + .dout(ex4_sspr_val_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[flush_offset : flush_offset + `THREADS-1]), + .scout(sov[flush_offset : flush_offset + `THREADS-1]), + .din(flush), + .dout(flush_q) + ); + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex1_ifar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[0]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), + .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), + .scout(sov[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), + .din(rv_xu_ex0_ifar), + .dout(ex1_ifar_q) + ); + tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ifar_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(exx_act[1]), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), + .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), + .scout(sov[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), + .din(ex1_ifar_q), + .dout(ex2_ifar_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ram_active_offset : ram_active_offset + `THREADS-1]), + .scout(sov[ram_active_offset : ram_active_offset + `THREADS-1]), + .din(pc_xu_ram_active), + .dout(ram_active_q) + ); + tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timer_div_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(timer_div_act), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[timer_div_offset : timer_div_offset + 5-1]), + .scout(sov[timer_div_offset : timer_div_offset + 5-1]), + .din(timer_div_d), + .dout(timer_div_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_2_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), + .scout(sov[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), + .din(msrovride_enab), + .dout(msrovride_enab_2_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_3_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), + .scout(sov[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), + .din(msrovride_enab_2_q), + .dout(msrovride_enab_3_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), + .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex3_wait_flush_offset]), + .scout(sov[ex3_wait_flush_offset]), + .din(ex3_wait_flush_d), + .dout(ex3_wait_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wait_flush_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), + .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin (siv[ex4_wait_flush_offset]), + .scout(sov[ex4_wait_flush_offset]), + .din(ex4_wait_flush_d), + .dout(ex4_wait_flush_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_pm_hold_thread_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[pc_xu_pm_hold_thread_offset]), + .scout(sov[pc_xu_pm_hold_thread_offset]), + .din(pc_xu_pm_hold_thread), + .dout(pc_xu_pm_hold_thread_q) + ); + tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) power_savings_on_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin(siv[power_savings_on_offset]), + .scout(sov[power_savings_on_offset]), + .din(power_savings_on_d), + .dout(power_savings_on_q) + ); + tri_rlmreg_p #(.WIDTH(4*`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_bus_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(pc_xu_event_bus_enable), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), + .scout(sov[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), + .din(perf_event_bus_d), + .dout(perf_event_bus_q) + ); + tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_en_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(pc_xu_event_bus_enable), + .force_t(func_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(func_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), + .scout(sov[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), + .din(perf_event_en_d), + .dout(perf_event_en_q) + ); + + + tri_lcbnd spare_0_lcb( + .vd(vdd), + .gd(gnd), + .act(1'b1), + .nclk(nclk), + .force_t(func_sl_force), + .thold_b(func_sl_thold_0_b), + .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), + .mpw2_b(mpw2_dc_b), + .sg(sg_0), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk) + ); + + tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch( + .vd(vdd), + .gd(gnd), + .lclk(spare_0_lclk), + .d1clk(spare_0_d1clk), + .d2clk(spare_0_d2clk), + .scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]), + .scanout(sov[spare_0_offset:spare_0_offset + 16 - 1]), + .d(spare_0_d), + .qb(spare_0_q) + ); + assign spare_0_d = (~spare_0_q); + + xu_fctr #(.WIDTH(`THREADS), .PASSTHRU(0), .DELAY_WIDTH(4), .CLOCKGATE(1)) quiesced_fctr( + .nclk(nclk), + .vdd(vdd), + .gnd(gnd), + .force_t(func_sl_force), + .d_mode(d_mode_dc), + .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), + .mpw2_b(mpw2_dc_b), + .thold_b(func_sl_thold_0_b), + .sg(sg_0), + .scin(siv[quiesced_ctr_offset]), + .scout(sov[quiesced_ctr_offset]), + .delay(4'b1111), + .din(quiesce_b_q), + .dout(quiesce_ctr_zero_b) + ); + + + tri_ser_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ccr0_we_latch( + .nclk(nclk), .vd(vdd), .gd(gnd), + .act(1'b1), + .force_t(bcfg_slp_sl_force), + .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), + .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), + .thold_b(bcfg_slp_sl_thold_0_b), + .sg(sg_0), + .scin (siv_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), + .scout(sov_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), + .din(ccr0_we_d), + .dout(ccr0_we_q) + ); + + + + assign siv[0:399] = {sov[1:399], scan_in[0]}; + assign scan_out[0] = sov[0]; + + assign siv[400:scan_right-1] = {sov[401:scan_right-1], scan_in[1]}; + assign scan_out[1] = sov[400]; + + generate + // BCFG + if (scan_right_bcfg > 1) + begin : bcfg_l + assign siv_bcfg[0:scan_right_bcfg - 1] = {sov_bcfg[1:scan_right_bcfg-1], bcfg_scan_in}; + assign bcfg_scan_out = sov_bcfg[0]; + end + if (scan_right_bcfg == 1) + begin : bcfg_s + assign siv_bcfg[0] = bcfg_scan_in; + assign bcfg_scan_out = sov_bcfg[0]; + end + if (scan_right_bcfg == 0) + begin : bcfg_z + assign bcfg_scan_out = bcfg_scan_in; + end + // CCFG + if (scan_right_ccfg > 1) + begin : ccfg_l + assign siv_ccfg[0:scan_right_ccfg - 1] = {sov_ccfg[1:scan_right_ccfg - 1], ccfg_scan_in}; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 1) + begin : ccfg_s + assign siv_ccfg[0] = ccfg_scan_in; + assign ccfg_scan_out = sov_ccfg[0]; + end + if (scan_right_ccfg == 0) + begin : ccfg_z + assign ccfg_scan_out = ccfg_scan_in; + end + // DCFG + if (scan_right_dcfg > 1) + begin : dcfg_l + assign siv_dcfg[0:scan_right_dcfg - 1] = {sov_dcfg[1:scan_right_dcfg - 1], dcfg_scan_in}; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 1) + begin : dcfg_s + assign siv_dcfg[0] = dcfg_scan_in; + assign dcfg_scan_out = sov_dcfg[0]; + end + if (scan_right_dcfg == 0) + begin : dcfg_z + assign dcfg_scan_out = dcfg_scan_in; + end + endgenerate + + + function [0:`THREADS-1] reverse_threads; + input [0:`THREADS-1] a; + integer t; + begin + for (t=0;t<`THREADS;t=t+1) + begin : threads_loop + reverse_threads[t] = a[`THREADS-1-t]; + end + end + endfunction + + +endmodule