From 7256fa3539e78a5b73d517055992f5ffbf44ecb5 Mon Sep 17 00:00:00 2001 From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Wed, 3 Aug 2022 13:39:50 -0500 Subject: [PATCH] parm experiments and cleanup --- dev/verilog/a2o_litex/a2l2wb.v | 21 +- dev/verilog/a2o_litex/a2owb.v | 218 +++-------- dev/verilog/a2o_litex/tri_a2o.vh | 309 +++++++++++---- dev/verilog/unisims/bram_model.v | 7 +- dev/verilog/work/iuq_dec_top.v | 8 +- dev/verilog/work/iuq_dispatch.v | 9 +- dev/verilog/work/iuq_ibuf.v | 2 + dev/verilog/work/iuq_ifetch.v | 1 + dev/verilog/work/iuq_uc.v | 156 ++++---- dev/verilog/work/iuq_uc_rom_even.v | 448 +++++++++++----------- dev/verilog/work/lq_ctl.v | 4 +- dev/verilog/work/lq_stq.v | 14 +- dev/verilog/work/mmq.v | 216 +++++------ dev/verilog/work/mmq_tlb_lrat_matchline.v | 19 +- dev/verilog/work/mmu_a2o.vh | 23 +- 15 files changed, 779 insertions(+), 676 deletions(-) diff --git a/dev/verilog/a2o_litex/a2l2wb.v b/dev/verilog/a2o_litex/a2l2wb.v index 01ab9c8..d3197a2 100644 --- a/dev/verilog/a2o_litex/a2l2wb.v +++ b/dev/verilog/a2o_litex/a2l2wb.v @@ -49,6 +49,17 @@ module a2l2wb #( input rst, input [0:31] cfg_dat, + +// chg to cfg_cmd +// 000 nop +// 001 +// 010 +// 011 +// 100 write +// 101 write mask set +// 110 write mask rst +// 111 write mask xor + input cfg_wr, output [0:31] status, @@ -120,7 +131,7 @@ module a2l2wb #( output an_ac_tb_update_pulse, input [0:7] ac_an_lpar_id, input [0:`THREADS-1] ac_an_special_attn, - input [0:`THREADS-1] ac_an_checkstop, //supposed to be 0:2 always? + input [0:2] ac_an_checkstop, output an_ac_checkstop, input [0:`THREADS-1] ac_an_machine_check, output [0:`THREADS-1] an_ac_external_mchk, @@ -206,7 +217,7 @@ module a2l2wb #( reg [0:31] cfg_q; // depend on MEM_MODE - reg [0:127] mem[MEM_QW]; + reg [0:127] mem[0:MEM_QW-1]; wire [0:127] mem_dat_int; reg [0:3] wbseq_q; wire [0:3] wbseq_d; @@ -629,10 +640,10 @@ endgenerate assign an_ac_pm_thread_stop[0] = cfg_q[0]; assign an_ac_pm_fetch_halt[0] = cfg_q[1]; - assign status = {ac_an_pm_thread_running[0], ac_an_special_attn[0], ac_an_machine_check[0], ac_an_checkstop[0], - ac_an_debug_trigger[0], ac_an_power_managed, ac_an_rvwinkle_mode, 1'b0, + assign status = {ac_an_pm_thread_running[0], ac_an_special_attn[0], ac_an_machine_check[0], + ac_an_debug_trigger[0], ac_an_power_managed, ac_an_rvwinkle_mode, 2'b0, 8'b0, 8'b0, - 7'b0, err_q + 4'b0, ac_an_checkstop[0:2], err_q }; diff --git a/dev/verilog/a2o_litex/a2owb.v b/dev/verilog/a2o_litex/a2owb.v index 6d3df2b..0fda29d 100644 --- a/dev/verilog/a2o_litex/a2owb.v +++ b/dev/verilog/a2o_litex/a2owb.v @@ -60,140 +60,27 @@ module a2owb ( -/* - input [0:`NCLK_WIDTH-1] nclk, - input scan_in, - output scan_out, -*/ - input clk_1x, - input clk_2x, - input rst, - -/* - // Pervasive clock control - input an_ac_rtim_sl_thold_8, - input an_ac_func_sl_thold_8, - input an_ac_func_nsl_thold_8, - input an_ac_ary_nsl_thold_8, - input an_ac_sg_8, - input an_ac_fce_8, - input [0:7] an_ac_abst_scan_in, - - - //SCOM Satellite - input [0:3] an_ac_scom_sat_id, - input an_ac_scom_dch, - input an_ac_scom_cch, -*/ - -/* - output ac_an_scom_dch, - output ac_an_scom_cch, - - // FIR and Error Signals - output [0:`THREADS-1] ac_an_special_attn, - output [0:2] ac_an_checkstop, - output [0:2] ac_an_local_checkstop, - output [0:2] ac_an_recov_err, - output ac_an_trace_error, - output ac_an_livelock_active, - - // Perfmon Event Bus - output [0:4*`THREADS-1] ac_an_event_bus0, - output [0:4*`THREADS-1] ac_an_event_bus1, -*/ - -/* - // Power Management - output [0:`THREADS-1] ac_an_pm_thread_running, - input [0:`THREADS-1] an_ac_pm_thread_stop, - input [0:`THREADS-1] an_ac_pm_fetch_halt, -*/ - -/* - // Clock, Test, and LCB Controls - input an_ac_gsd_test_enable_dc, - input an_ac_gsd_test_acmode_dc, - input an_ac_ccflush_dc, - input an_ac_ccenable_dc, - input an_ac_lbist_en_dc, - input an_ac_lbist_ip_dc, - input an_ac_lbist_ac_mode_dc, - input an_ac_scan_diag_dc, - input an_ac_scan_dis_dc_b, - - //Thold input to clock control macro - input [0:8] an_ac_scan_type_dc, -*/ -/* - // Pervasive - output ac_an_reset_1_request, - output ac_an_reset_2_request, - output ac_an_reset_3_request, - output ac_an_reset_wd_request, -*/ -/* - input an_ac_lbist_ary_wrt_thru_dc, -*/ -// intr - input timerInterrupt, - input externalInterrupt, - input softwareInterrupt, - input externalInterruptS, - -/* - input [0:`THREADS-1] an_ac_ext_interrupt, - input [0:`THREADS-1] an_ac_crit_interrupt, - input [0:`THREADS-1] an_ac_perf_interrupt, -*/ -/* - input [0:`THREADS-1] an_ac_sleep_en, - input [0:`THREADS-1] an_ac_hang_pulse, -*/ -/* - input an_ac_tb_update_enable, - input an_ac_tb_update_pulse, -*/ -/* - input [0:3] an_ac_chipid_dc, - input [0:7] an_ac_coreid, -*/ -/* - output [0:`THREADS-1] ac_an_machine_check, - input an_ac_debug_stop, - output [0:`THREADS-1] ac_an_debug_trigger, - input [0:`THREADS-1] an_ac_uncond_dbg_event, - output [0:31] ac_an_debug_bus, - output ac_an_coretrace_first_valid, - output ac_an_coretrace_valid, - output [0:1] ac_an_coretrace_type, - input an_ac_flh2l2_gate, - input an_ac_reset_1_complete, - input an_ac_reset_2_complete, - input an_ac_reset_3_complete, - input an_ac_reset_wd_complete, - output an_ac_checkstop, - input [0:`THREADS-1] an_ac_external_mchk, - output ac_an_power_managed, - output ac_an_rvwinkle_mode, -*/ -/* - // direct-attach mem - output [0:31] mem_adr, - input [0:127] mem_dat, - output mem_wr_val, - output [0:15] mem_wr_be, - output [0:127] mem_wr_dat, -*/ - // wishbone - output wb_stb, - output wb_cyc, - output [31:0] wb_adr, - output wb_we, - output [3:0] wb_sel, - output [31:0] wb_datw, - input wb_ack, - input [31:0] wb_datr + input clk_1x, + input clk_2x, + input rst, + + input [0:31] cfg_dat, + input cfg_wr, + output [0:31] status, + + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input externalInterruptS, + + output wb_stb, + output wb_cyc, + output [31:0] wb_adr, + output wb_we, + output [3:0] wb_sel, + output [31:0] wb_datw, + input wb_ack, + input [31:0] wb_datr ); wire [0:`NCLK_WIDTH-1] nclk; @@ -284,25 +171,24 @@ wire an_ac_reset_2_complete; wire an_ac_reset_3_complete; wire an_ac_reset_wd_complete; wire [0:`THREADS-1] an_ac_uncond_dbg_event; +wire [0:2] ac_an_checkstop; +wire [0:127] mem_wr_dat; // not connected -wire scan_out; -wire [0:31] ac_an_debug_bus; -wire [0:31] mem_adr; -wire mem_wr_val; -wire [0:15] mem_wr_be; -wire [0:127] mem_wr_dat; -wire [0:2] ac_an_checkstop; -wire [0:2] ac_an_local_checkstop; -wire [0:2] ac_an_recov_err; -wire ac_an_trace_err; -wire ac_an_livelock_active; -wire [0:4*`THREADS-1] ac_an_event_bus0; -wire [0:4*`THREADS-1] ac_an_event_bus1; -wire ac_an_reset_1_request; -wire ac_an_reset_2_request; -wire ac_an_reset_3_request; -wire ac_an_reset_wd_request; +//wire scan_out; +//wire [0:31] mem_adr; +//wire mem_wr_val; +//wire [0:15] mem_wr_be; +//wire [0:2] ac_an_local_checkstop; +//wire [0:2] ac_an_recov_err; +//wire ac_an_trace_err; +//wire ac_an_livelock_active; +//wire [0:4*`THREADS-1] ac_an_event_bus0; +//wire [0:4*`THREADS-1] ac_an_event_bus1; +//wire ac_an_reset_1_request; +//wire ac_an_reset_2_request; +//wire ac_an_reset_3_request; +//wire ac_an_reset_wd_request; assign nclk = {clk_1x, rst, clk_2x, 3'b00}; @@ -351,7 +237,7 @@ assign an_ac_uncond_dbg_event = 0; c c0( .nclk(nclk), .scan_in(scan_in), - .scan_out(scan_out), + .scan_out(), .an_ac_rtim_sl_thold_8(an_ac_rtim_sl_thold_8), .an_ac_func_sl_thold_8(an_ac_func_sl_thold_8), @@ -406,14 +292,14 @@ c c0( .ac_an_special_attn(ac_an_special_attn), .ac_an_checkstop(ac_an_checkstop), - .ac_an_local_checkstop(ac_an_local_checkstop), - .ac_an_recov_err(ac_an_recov_err), - .ac_an_trace_error(ac_an_trace_error), - .ac_an_livelock_active(ac_an_livelock_active), + .ac_an_local_checkstop(), + .ac_an_recov_err(), + .ac_an_trace_error(), + .ac_an_livelock_active(), .an_ac_checkstop(an_ac_checkstop), .an_ac_external_mchk(an_ac_external_mchk), - .ac_an_event_bus0(ac_an_event_bus0), + .ac_an_event_bus0(), .an_ac_reset_1_complete(an_ac_reset_1_complete), .an_ac_reset_2_complete(an_ac_reset_2_complete), @@ -435,10 +321,10 @@ c c0( .an_ac_scan_diag_dc(an_ac_scan_diag_dc), .an_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), .an_ac_scan_type_dc(an_ac_scan_type_dc), - .ac_an_reset_1_request(ac_an_reset_1_request), - .ac_an_reset_2_request(ac_an_reset_2_request), - .ac_an_reset_3_request(ac_an_reset_3_request), - .ac_an_reset_wd_request(ac_an_reset_wd_request), + .ac_an_reset_1_request(), + .ac_an_reset_2_request(), + .ac_an_reset_3_request(), + .ac_an_reset_wd_request(), .an_ac_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc), .an_ac_sleep_en(an_ac_sleep_en), .an_ac_ext_interrupt(an_ac_ext_interrupt), @@ -477,6 +363,10 @@ a2l2wb n0( .clk(clk_1x), .rst(rst), + .cfg_wr(cfg_wr), + .cfg_dat(cfg_dat), + .status(status), + .timerInterrupt(timerInterrupt), .externalInterrupt(externalInterrupt), .softwareInterrupt(softwareInterrupt), @@ -592,10 +482,10 @@ a2l2wb n0( .ac_an_rvwinkle_mode(ac_an_rvwinkle_mode), // direct-attach mem - .mem_adr(mem_adr), + .mem_adr(), .mem_dat(mem_dat), - .mem_wr_be(mem_wr_be), - .mem_wr_val(mem_wr_val), + .mem_wr_be(), + .mem_wr_val(), .mem_wr_dat(mem_wr_dat), diff --git a/dev/verilog/a2o_litex/tri_a2o.vh b/dev/verilog/a2o_litex/tri_a2o.vh index ad1814a..a2060f7 100755 --- a/dev/verilog/a2o_litex/tri_a2o.vh +++ b/dev/verilog/a2o_litex/tri_a2o.vh @@ -28,96 +28,286 @@ // Transaction limiting // LOAD_CREDITS=1, STORE_CREDITS=1, XUCR0[52]=1 +// +// Experiments with downsizing +// ;tldr most dont work! `ifndef _tri_a2o_vh_ `define _tri_a2o_vh_ `include "tri.vh" -// Use this line for 1 thread. Comment out for 2 thread design. -`define THREADS1 +// Experiments with downsizing -//`define RESET_VECTOR 32'hFFFFFFFC -`define RESET_VECTOR 32'h00000000 +// normal settings +`define LQ_NORMAL +`define DC_32 +`define IU_NORMAL // this one actually works if keep erat bypass +`define RN_CP_NORMAL +`define RV_NORMAL // needs rtl updates to support changes -`define gpr_t 3'b000 -`define cr_t 3'b001 -`define lr_t 3'b010 -`define ctr_t 3'b011 -`define xer_t 3'b100 -`define spr_t 3'b101 -`define axu0_t 3'b110 -`define axu1_t 3'b111 +`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array +//`define EXPAND_TLB_TYPE 0 // doesn't work in sim + + +/*wtf these are a mess; need to be doc'd and create dependency reqts and legal ranges; + shrinking values causes lots of bit sel vector problems, and sim fails + + can ic size/ways be easily added? + can dc ways use parameter? +*/ + +// ******************************************************************************************************** +// Load/Store +`ifdef LQ_NORMAL + +`define LDSTQ_ENTRIES 16 +`define LDSTQ_ENTRIES_ENC 4 +`define STQ_ENTRIES 12 +`define STQ_ENTRIES_ENC 4 +`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from +`define LMQ_ENTRIES 8 +`define LMQ_ENTRIES_ENC 3 +`define LGQ_ENTRIES 8 +`define EMQ_ENTRIES 4 // erat miss queue (d-only?) +`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size (lq) +`define MMQ_ENTRIES 2 // MMU Queue Size (lq) -`ifdef THREADS1 - `define THREADS 1 - `define THREAD_POOL_ENC 0 - `define THREADS_POOL_ENC 0 `else - `define THREADS 2 - `define THREAD_POOL_ENC 1 - `define THREADS_POOL_ENC 1 + +/* +// these values comp/elab and DON'T pass test3 (coco) +// and vivado still gets an elab error: +// ERROR: [Synth 8-524] part-select [0:4] out of range of prefix 'stq3_cmmt_ptr_q' [/data/projects/a2o/dev/build/litex/a2o/verilog/work/lq_stq.v:2171] +// not sure if it's a true requirement or the hardcoded 0:4 can use `STQ_ENTRIES +`define LDSTQ_ENTRIES 4 // ?order? +`define LDSTQ_ENTRIES_ENC 2 +`define STQ_ENTRIES 4 +`define STQ_ENTRIES_ENC 2 +`define STQ_FWD_ENTRIES 2 // number of stq entries that can be forwarded from +`define LMQ_ENTRIES 4 +`define LMQ_ENTRIES_ENC 2 +`define LGQ_ENTRIES 4 +*/ +// above w/STQ_ENTRIES=5 +// these values comp/elab and fail test3 (coco) with cp hang after 8700 cys +`define LDSTQ_ENTRIES 4 // ?order? +`define LDSTQ_ENTRIES_ENC 2 +`define STQ_ENTRIES 5 +`define STQ_ENTRIES_ENC 3 +`define STQ_FWD_ENTRIES 2 // number of stq entries that can be forwarded from +`define LMQ_ENTRIES 4 +`define LMQ_ENTRIES_ENC 2 +`define LGQ_ENTRIES 4 +`define EMQ_ENTRIES 1 // erat miss queue (d-only?) +`define IUQ_ENTRIES 1 // Instruction Fetch Queue Size (lq) +`define MMQ_ENTRIES 1 // MMU Queue Size (lq) + `endif -`define EFF_IFAR_ARCH 62 -`define EFF_IFAR_WIDTH 20 -`define EFF_IFAR 20 -`define FPR_POOL_ENC 6 -`define REGMODE 6 -`define FPR_POOL 64 -`define REAL_IFAR_WIDTH 42 -`define EMQ_ENTRIES 4 -`define GPR_WIDTH 64 -`define ITAG_SIZE_ENC 7 +// ******************************************************************************************************** + +// ******************************************************************************************************** +// DC Size +//wtf modify ways also? + +`ifdef DC_32 + +`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported +`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE + +`else + +//wtf this gets 8 vector size warnings in iverilog and hangs early in coco test3 +`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported +`define DC_SIZE 14 // 14 => 16K L1D$, 15 => 32K L1D$ +`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE + +`endif +// ******************************************************************************************************** + +// ******************************************************************************************************** +// IU +//wtf NO IC SIZE +// iuq_ic_dir: parameter ways = 4; +// dir_rd_addr,dir_wr_addr hardcoded 0:6 - but somewhat easy change to use smaller IC? hold bits to 0 and change lookup + +`ifdef IU_NORMAL + +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) + +`define IBUFF_DEPTH 16 + +`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries + +`else + +// compiles and fails after first op executes in coco test3 - IERAT_BYPASS=0 +`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) + +// these work so far! +`define IBUFF_DEPTH 6 //wtf 4 fails compile in iuq_ibuf equations using -5 + +`define BUILD_PFETCH 0 // 1=> include pfetch in the build, 0=> build without pfetch +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define PF_IFAR_WIDTH 12 +`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch +`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) +`define PFETCH_Q_SIZE 8 // number of entries + +`endif + +// ******************************************************************************************************** + + +//******************************************************************************************************** +// Rename-Completion +`ifdef RN_CP_NORMAL + `define CPL_Q_DEPTH 32 `define CPL_Q_DEPTH_ENC 6 -`define GPR_WIDTH_ENC 6 -`define GPR_POOL_ENC 6 + `define GPR_POOL 64 +`define GPR_POOL_ENC 6 `define GPR_UCODE_POOL 4 -`define CR_POOL_ENC 5 +`define FPR_POOL 64 +`define FPR_POOL_ENC 6 `define CR_POOL 24 +`define CR_POOL_ENC 5 +`define CR_WIDTH 4 `define CR_UCODE_POOL 1 `define BR_POOL_ENC 3 `define BR_POOL 8 +`define CTR_POOL_ENC 3 +`define CTR_POOL 8 +`define CTR_UCODE_POOL 0 `define LR_POOL_ENC 3 `define LR_POOL 8 `define LR_UCODE_POOL 0 +`define XER_POOL 12 +`define XER_POOL_ENC 4 +`define XER_WIDTH 10 +`define XER_UCODE_POOL 0 + +`else + +`define CPL_Q_DEPTH 16 // 16/5: ok, 8/4, 4/3: fail +`define CPL_Q_DEPTH_ENC 5 + +`define GPR_POOL 64 +`define GPR_POOL_ENC 6 +`define GPR_UCODE_POOL 4 +`define FPR_POOL 64 +`define FPR_POOL_ENC 6 +`define CR_POOL 24 +`define CR_POOL_ENC 5 +`define CR_WIDTH 4 +`define CR_UCODE_POOL 1 +`define BR_POOL_ENC 3 +`define BR_POOL 8 `define CTR_POOL_ENC 3 `define CTR_POOL 8 `define CTR_UCODE_POOL 0 -`define XER_POOL_ENC 4 +`define LR_POOL_ENC 3 +`define LR_POOL 8 +`define LR_UCODE_POOL 0 `define XER_POOL 12 +`define XER_POOL_ENC 4 +`define XER_WIDTH 10 `define XER_UCODE_POOL 0 -`define LDSTQ_ENTRIES 16 -`define LDSTQ_ENTRIES_ENC 4 -`define STQ_ENTRIES 12 -`define STQ_ENTRIES_ENC 4 -`define STQ_FWD_ENTRIES 4 // number of stq entries that can be forwarded from -`define STQ_DATA_SIZE 64 // 64 or 128 Bit store data sizes supported -`define DC_SIZE 15 // 14 => 16K L1D$, 15 => 32K L1D$ -`define CL_SIZE 6 // 6 => 64B CLINE, 7 => 128B CLINE -`define LMQ_ENTRIES 8 -`define LMQ_ENTRIES_ENC 3 -`define LGQ_ENTRIES 8 -`define AXU_SPARE_ENC 3 + +`endif + +//******************************************************************************************************** +// Reservation Stations + +`ifdef RV_NORMAL + `define RV_FX0_ENTRIES 12 -`define RV_FX1_ENTRIES 12 -`define RV_LQ_ENTRIES 16 -`define RV_AXU0_ENTRIES 12 -`define RV_AXU1_ENTRIES 0 `define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES 12 `define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES 16 `define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES 12 `define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES 0 `define RV_AXU1_ENTRIES_ENC 1 `define UCODE_ENTRIES 8 `define UCODE_ENTRIES_ENC 3 -`define FXU1_ENABLE 1 + +`else + +//wtf there are hardcoded bit 4's in enc eqs; try not touching the enc widths (the '4' DOES come from a +// parameter though (q_barf_enc_g) so may just need rewrite, or is dont-care cuz some are always 0). +// but eqs must be related - changing entry count still fails +`define RV_FX0_ENTRIES 12 +`define RV_FX0_ENTRIES_ENC 4 +`define RV_FX1_ENTRIES 12 +`define RV_FX1_ENTRIES_ENC 4 +`define RV_LQ_ENTRIES 16 +`define RV_LQ_ENTRIES_ENC 4 +`define RV_AXU0_ENTRIES 12 +`define RV_AXU0_ENTRIES_ENC 4 +`define RV_AXU1_ENTRIES 0 +`define RV_AXU1_ENTRIES_ENC 1 +`define UCODE_ENTRIES 8 +`define UCODE_ENTRIES_ENC 3 + +`endif + +//******************************************************************************************************** + +/* FXU*/ +`define FXU1_ENABLE 1 //wtf don't see this except in dispatch; must need some other stuff (like if deleting mmu/fpu) + +// Use this line for 1 thread. Comment out for 2 thread design. +`define THREADS1 + +//`define RESET_VECTOR 32'hFFFFFFFC +`define RESET_VECTOR 32'h00000000 + +`ifdef THREADS1 + `define THREADS 1 + `define THREAD_POOL_ENC 0 + `define THREADS_POOL_ENC 0 +`else + `define THREADS 2 + `define THREAD_POOL_ENC 1 + `define THREADS_POOL_ENC 1 +`endif + +`define LOAD_CREDITS 1 +`define STORE_CREDITS 1 +`define INIT_XUCR0 32'h00000C60 // 52:single-credit LS + +`define REGMODE 6 // 32/64b +`define EFF_IFAR_ARCH 62 +`define EFF_IFAR_WIDTH 20 +`define EFF_IFAR 20 +`define REAL_IFAR_WIDTH 42 + +`define gpr_t 3'b000 +`define cr_t 3'b001 +`define lr_t 3'b010 +`define ctr_t 3'b011 +`define xer_t 3'b100 +`define spr_t 3'b101 +`define axu0_t 3'b110 +`define axu1_t 3'b111 + +`define ITAG_SIZE_ENC 7 +`define GPR_WIDTH 64 +`define GPR_WIDTH_ENC 6 +`define AXU_SPARE_ENC 3 `define TYPE_WIDTH 3 `define IBUFF_INSTR_WIDTH 70 `define IBUFF_IFAR_WIDTH 20 -`define IBUFF_DEPTH 16 -`define PF_IAR_BITS 12 // number of IAR bits used by prefetch `define FXU0_PIPE_START 1 `define FXU0_PIPE_END 8 `define FXU1_PIPE_START 1 @@ -126,18 +316,6 @@ `define LQ_LOAD_PIPE_END 8 `define LQ_REL_PIPE_START 2 `define LQ_REL_PIPE_END 4 -`define LOAD_CREDITS 1 -`define STORE_CREDITS 1 -`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size -`define MMQ_ENTRIES 2 // MMU Queue Size -`define CR_WIDTH 4 -`define BUILD_PFETCH 1 // 1=> include pfetch in the build, 0=> build without pfetch -`define PF_IFAR_WIDTH 12 -`define PFETCH_INITIAL_DEPTH 0 // the initial value for the SPR that determines how many lines to prefetch -`define PFETCH_Q_SIZE_ENC 3 // number of bits to address queue size (3 => 8 entries, 4 => 16 entries) -`define PFETCH_Q_SIZE 8 // number of entries -`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) -`define XER_WIDTH 10 //wtf: change for verilatorsim - didnt help //`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT @@ -145,7 +323,6 @@ //`define INIT_IUCR0 16'h0000 // BP disabled `define INIT_IUCR0 16'h00FA // BP enabled - `define INIT_MASK 2'b10 `define RELQ_INCLUDE 0 // Reload Queue Included @@ -167,8 +344,6 @@ `define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 //`define INIT_CPCR1 32'h00010100 // 1/1 -`define INIT_XUCR0 32'h00000C60 // 52:single-credit LS - // IERAT boot config entry values `define IERAT_BCFG_EPN_0TO15 0 `define IERAT_BCFG_EPN_16TO31 0 diff --git a/dev/verilog/unisims/bram_model.v b/dev/verilog/unisims/bram_model.v index 09b445f..6a36408 100755 --- a/dev/verilog/unisims/bram_model.v +++ b/dev/verilog/unisims/bram_model.v @@ -24,25 +24,26 @@ module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA, reg [data_w-1:0] DOB_q; - initial begin + initial begin: init integer i; for (i = 0; i < 2**addr_w; i = i + 1) MEM[i] = 0; end - always @(posedge CLKA, posedge CLKB) begin: BRAM_MODEL + always @(posedge CLKA) begin: BRAM_MODEL if (ENA) begin if (WEA) begin MEM[ADDRA] <= DIA; end end + end + always @(posedge CLKB) begin: BRAM_MODEL_B if (ENB) begin if (WEB) begin MEM[ADDRB] <= DIB; end end - end always @(posedge CLKA) begin diff --git a/dev/verilog/work/iuq_dec_top.v b/dev/verilog/work/iuq_dec_top.v index d130a9e..319acfc 100755 --- a/dev/verilog/work/iuq_dec_top.v +++ b/dev/verilog/work/iuq_dec_top.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -599,7 +599,7 @@ module iuq_dec_top( .delay_lclkr(delay_lclkr), .mpw1_b(mpw1_b), .mpw2_b(mpw2_b), - + .fu_dec_debug(), // tied 0 .iu_au_iu4_isram(ib_id_iu4_0_isram), .iu_au_ucode_restart(1'b0), .iu_au_config_iucr(iu_au_config_iucr), diff --git a/dev/verilog/work/iuq_dispatch.v b/dev/verilog/work/iuq_dispatch.v index be1c48d..3c63a7d 100755 --- a/dev/verilog/work/iuq_dispatch.v +++ b/dev/verilog/work/iuq_dispatch.v @@ -601,12 +601,17 @@ module iuq_dispatch( output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t0_i1_s3_p, output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t0_i1_s3_itag, output [0:2] iu_rv_iu6_t0_i1_s3_t, +`ifdef THREADS1 + output iu_rv_iu6_t0_i1_s3_dep_hit +`else output iu_rv_iu6_t0_i1_s3_dep_hit, +`endif `ifndef THREADS1 //---------------------------------------------------------------- // Interface with rename //---------------------------------------------------------------- + output iu_rv_iu6_t1_i0_vld, output iu_rv_iu6_t1_i0_act, output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i0_itag, @@ -749,9 +754,9 @@ module iuq_dispatch( output [0:`GPR_POOL_ENC-1] iu_rv_iu6_t1_i1_s3_p, output [0:`ITAG_SIZE_ENC-1] iu_rv_iu6_t1_i1_s3_itag, output [0:2] iu_rv_iu6_t1_i1_s3_t, - output iu_rv_iu6_t1_i1_s3_dep_hit, + output iu_rv_iu6_t1_i1_s3_dep_hit `endif - input [0:`THREADS-1] spr_cpcr2_we + //input [0:`THREADS-1] spr_cpcr2_we ); localparam [0:31] value_1 = 32'h00000001; diff --git a/dev/verilog/work/iuq_ibuf.v b/dev/verilog/work/iuq_ibuf.v index b74bd09..2d1f439 100755 --- a/dev/verilog/work/iuq_ibuf.v +++ b/dev/verilog/work/iuq_ibuf.v @@ -381,6 +381,7 @@ module iuq_ibuf( assign buffer_valid_act = buffer_valid_flush | valid_in[0] | (buffer_valid_q[0] & (buffer_advance[1] | buffer_advance[2])); //wtf update for IBUFF_DEPTH < 5 + // still fails - the right-side here and below have a -5 assign buffer_valid_din[0:`IBUFF_DEPTH - 1] = (buffer_advance[0] == 1'b1 & valid_in[3] == 1'b1) ? {4'b1111, buffer_valid_q[0:`IBUFF_DEPTH - 5]} : (buffer_advance[1] == 1'b1 & valid_in[3] == 1'b1) ? {3'b111, buffer_valid_q[0:`IBUFF_DEPTH - 4]} : (buffer_advance[2] == 1'b1 & valid_in[3] == 1'b1) ? {2'b11, buffer_valid_q[0:`IBUFF_DEPTH - 3]} : @@ -404,6 +405,7 @@ module iuq_ibuf( assign buffer_head_act = buffer_valid_flush | valid_in[0]; //wtf update for IBUFF_DEPTH < 5 + // still fails assign buffer_head_din[0:`IBUFF_DEPTH - 1] = (buffer_bypass[2] == 1'b1 & valid_in[3] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 2:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 3]} : (buffer_bypass[2] == 1'b1 & valid_in[2] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 2]} : (buffer_bypass[1] == 1'b1 & valid_in[3] == 1'b1) ? {buffer_head_q[`IBUFF_DEPTH - 3:`IBUFF_DEPTH - 1], buffer_head_q[0:`IBUFF_DEPTH - 4]} : diff --git a/dev/verilog/work/iuq_ifetch.v b/dev/verilog/work/iuq_ifetch.v index 2a17659..9fad2bb 100755 --- a/dev/verilog/work/iuq_ifetch.v +++ b/dev/verilog/work/iuq_ifetch.v @@ -1058,6 +1058,7 @@ module iuq_ifetch( for (i = 0; i < `THREADS; i = i + 1) begin : bp_gen iuq_bp iuq_bp0( + .bp_ic_iu3_hold(), // tied 0 in iuq_bp .iu2_0_bh0_rd_data(iu2_0_bh0_rd_data), .iu2_1_bh0_rd_data(iu2_1_bh0_rd_data), .iu2_2_bh0_rd_data(iu2_2_bh0_rd_data), diff --git a/dev/verilog/work/iuq_uc.v b/dev/verilog/work/iuq_uc.v index 08910fd..6813b3e 100755 --- a/dev/verilog/work/iuq_uc.v +++ b/dev/verilog/work/iuq_uc.v @@ -609,7 +609,7 @@ assign get_address_pt[1] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0001001101001110); + }) == 16'b0001001101001110); assign get_address_pt[2] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -619,7 +619,7 @@ assign get_address_pt[2] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b1111110010000000); + }) == 16'b1111110010000000); assign get_address_pt[3] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -629,7 +629,7 @@ assign get_address_pt[3] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0111111000000000); + }) == 16'b0111111000000000); assign get_address_pt[4] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -638,7 +638,7 @@ assign get_address_pt[4] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111101011111); + next_instr[30] }) == 15'b011111101011111); assign get_address_pt[5] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -648,7 +648,7 @@ assign get_address_pt[5] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] , iu3_2ucode_l2 - }) === 16'b0111110000110110); + }) == 16'b0111110000110110); assign get_address_pt[6] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -658,7 +658,7 @@ assign get_address_pt[6] = next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] , iu3_2ucode_l2 - }) === 16'b0111111001101110); + }) == 16'b0111111001101110); assign get_address_pt[7] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -668,7 +668,7 @@ assign get_address_pt[7] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] , iu3_2ucode_l2 - }) === 16'b0111110101110111); + }) == 16'b0111110101110111); assign get_address_pt[8] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -677,7 +677,7 @@ assign get_address_pt[8] = next_instr[23] , next_instr[24] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111010110101); + next_instr[30] }) == 15'b011111010110101); assign get_address_pt[9] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -687,7 +687,7 @@ assign get_address_pt[9] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] , - iu3_2ucode_l2 }) === 17'b01111101001101110); + iu3_2ucode_l2 }) == 17'b01111101001101110); assign get_address_pt[10] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -696,7 +696,7 @@ assign get_address_pt[10] = next_instr[23] , next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111101101111); + next_instr[30] }) == 15'b011111101101111); assign get_address_pt[11] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -705,7 +705,7 @@ assign get_address_pt[11] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111111010111); + next_instr[30] }) == 15'b011111111010111); assign get_address_pt[12] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -714,7 +714,7 @@ assign get_address_pt[12] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111100011111); + }) == 14'b01111100011111); assign get_address_pt[13] = (({ next_instr[0] , next_instr[1] , next_instr[3] , next_instr[4] , @@ -723,7 +723,7 @@ assign get_address_pt[13] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b111111011000111); + next_instr[30] }) == 15'b111111011000111); assign get_address_pt[14] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -732,7 +732,7 @@ assign get_address_pt[14] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] - }) === 14'b01111100001111); + }) == 14'b01111100001111); assign get_address_pt[15] = (({ next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , @@ -741,7 +741,7 @@ assign get_address_pt[15] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b11111110010110); + }) == 14'b11111110010110); assign get_address_pt[16] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -751,7 +751,7 @@ assign get_address_pt[16] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] , iu3_2ucode_l2 - }) === 16'b0111110101110110); + }) == 16'b0111110101110110); assign get_address_pt[17] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -760,7 +760,7 @@ assign get_address_pt[17] = next_instr[23] , next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , - next_instr[30] }) === 15'b011111010101011); + next_instr[30] }) == 15'b011111010101011); assign get_address_pt[18] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -769,7 +769,7 @@ assign get_address_pt[18] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111100010101); + next_instr[30] }) == 15'b011111100010101); assign get_address_pt[19] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -779,7 +779,7 @@ assign get_address_pt[19] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0111110010010000); + }) == 16'b0111110010010000); assign get_address_pt[20] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -789,7 +789,7 @@ assign get_address_pt[20] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0111111101110111); + }) == 16'b0111111101110111); assign get_address_pt[21] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -799,7 +799,7 @@ assign get_address_pt[21] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0111110001110111); + }) == 16'b0111110001110111); assign get_address_pt[22] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -808,7 +808,7 @@ assign get_address_pt[22] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111101110111); + next_instr[30] }) == 15'b011111101110111); assign get_address_pt[23] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -817,7 +817,7 @@ assign get_address_pt[23] = next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] , iu3_2ucode_l2 - }) === 14'b01111100101111); + }) == 14'b01111100101111); assign get_address_pt[24] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -826,7 +826,7 @@ assign get_address_pt[24] = next_instr[23] , next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] - }) === 14'b01111110100101); + }) == 14'b01111110100101); assign get_address_pt[25] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -835,7 +835,7 @@ assign get_address_pt[25] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111101001111); + }) == 14'b01111101001111); assign get_address_pt[26] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -844,7 +844,7 @@ assign get_address_pt[26] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] , - iu3_2ucode_l2 }) === 15'b011111001101111); + iu3_2ucode_l2 }) == 15'b011111001101111); assign get_address_pt[27] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -853,7 +853,7 @@ assign get_address_pt[27] = next_instr[23] , next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[30] - }) === 14'b01111100100111); + }) == 14'b01111100100111); assign get_address_pt[28] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -862,7 +862,7 @@ assign get_address_pt[28] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111100001111); + }) == 14'b01111100001111); assign get_address_pt[29] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -872,7 +872,7 @@ assign get_address_pt[29] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 16'b0111110000010011); + }) == 16'b0111110000010011); assign get_address_pt[30] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -881,7 +881,7 @@ assign get_address_pt[30] = next_instr[23] , next_instr[24] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] - }) === 14'b01111100101011); + }) == 14'b01111100101011); assign get_address_pt[31] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -890,7 +890,7 @@ assign get_address_pt[31] = next_instr[23] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[30] - }) === 14'b01111110101011); + }) == 14'b01111110101011); assign get_address_pt[32] = (({ next_instr[0] , next_instr[1] , next_instr[3] , next_instr[4] , @@ -898,7 +898,7 @@ assign get_address_pt[32] = next_instr[22] , next_instr[24] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 13'b1111100000000); + next_instr[30] }) == 13'b1111100000000); assign get_address_pt[33] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -907,7 +907,7 @@ assign get_address_pt[33] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] - }) === 14'b01111110001011); + }) == 14'b01111110001011); assign get_address_pt[34] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -916,7 +916,7 @@ assign get_address_pt[34] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111000110101); + next_instr[30] }) == 15'b011111000110101); assign get_address_pt[35] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -925,7 +925,7 @@ assign get_address_pt[35] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111110010110); + }) == 14'b01111110010110); assign get_address_pt[36] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -934,7 +934,7 @@ assign get_address_pt[36] = next_instr[23] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111110110111); + }) == 14'b01111110110111); assign get_address_pt[37] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -943,7 +943,7 @@ assign get_address_pt[37] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111010110111); + next_instr[30] }) == 15'b011111010110111); assign get_address_pt[38] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , @@ -951,7 +951,7 @@ assign get_address_pt[38] = next_instr[22] , next_instr[24] , next_instr[25] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 13'b1111111101110); + next_instr[30] }) == 13'b1111111101110); assign get_address_pt[39] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -960,7 +960,7 @@ assign get_address_pt[39] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] - }) === 14'b01111110001010); + }) == 14'b01111110001010); assign get_address_pt[40] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -969,7 +969,7 @@ assign get_address_pt[40] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111101010101); + next_instr[30] }) == 15'b011111101010101); assign get_address_pt[41] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -978,7 +978,7 @@ assign get_address_pt[41] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111100001101); + }) == 14'b01111100001101); assign get_address_pt[42] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -987,7 +987,7 @@ assign get_address_pt[42] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 15'b011111111010111); + next_instr[30] }) == 15'b011111111010111); assign get_address_pt[43] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -996,7 +996,7 @@ assign get_address_pt[43] = next_instr[25] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111100110111); + }) == 14'b01111100110111); assign get_address_pt[44] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -1005,7 +1005,7 @@ assign get_address_pt[44] = next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 14'b01111110101111); + }) == 14'b01111110101111); assign get_address_pt[45] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -1013,13 +1013,13 @@ assign get_address_pt[45] = next_instr[21] , next_instr[24] , next_instr[25] , next_instr[26] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 13'b0111110001111); + next_instr[30] }) == 13'b0111110001111); assign get_address_pt[46] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] , next_instr[30] , next_instr[31] , - iu3_2ucode_l2 }) === 9'b111010010); + iu3_2ucode_l2 }) == 9'b111010010); assign get_address_pt[47] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , @@ -1027,156 +1027,156 @@ assign get_address_pt[47] = next_instr[21] , next_instr[22] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , - next_instr[30] }) === 13'b0111111010111); + next_instr[30] }) == 13'b0111111010111); assign get_address_pt[48] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[28] , next_instr[30] - }) === 8'b00000001); + }) == 8'b00000001); assign get_address_pt[49] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[27] , next_instr[30] - }) === 8'b00000110); + }) == 8'b00000110); assign get_address_pt[50] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[27] , next_instr[28] - }) === 8'b00000111); + }) == 8'b00000111); assign get_address_pt[51] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[28] , next_instr[29] - }) === 8'b00000110); + }) == 8'b00000110); assign get_address_pt[52] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] , - iu3_2ucode_l2 }) === 7'b1100110); + iu3_2ucode_l2 }) == 7'b1100110); assign get_address_pt[53] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[30] , - next_instr[31] }) === 7'b1111001); + next_instr[31] }) == 7'b1111001); assign get_address_pt[54] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] , - iu3_2ucode_l2 }) === 7'b1010010); + iu3_2ucode_l2 }) == 7'b1010010); assign get_address_pt[55] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] , next_instr[30] , next_instr[31] - }) === 8'b11101010); + }) == 8'b11101010); assign get_address_pt[56] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] , - iu3_2ucode_l2 }) === 7'b1010110); + iu3_2ucode_l2 }) == 7'b1010110); assign get_address_pt[57] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[27] , next_instr[28] , next_instr[29] , next_instr[30] - }) === 10'b1111110010); + }) == 10'b1111110010); assign get_address_pt[58] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[5] , iu3_2ucode_l2 - }) === 6'b110010); + }) == 6'b110010); assign get_address_pt[59] = (({ next_instr[0] , next_instr[2] , next_instr[3] , next_instr[5] , - iu3_2ucode_l2 }) === 5'b10010); + iu3_2ucode_l2 }) == 5'b10010); assign get_address_pt[60] = (({ next_instr[0] , next_instr[1] , next_instr[3] , next_instr[4] , next_instr[5] , next_instr[30] - }) === 6'b111100); + }) == 6'b111100); assign get_address_pt[61] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , next_instr[4] , next_instr[5] - }) === 6'b100011); + }) == 6'b100011); assign get_address_pt[62] = (({ next_instr[0] , next_instr[1] , next_instr[3] , next_instr[4] - }) === 4'b1010); + }) == 4'b1010); assign get_address_pt[63] = (({ next_instr[0] , next_instr[1] , next_instr[3] , next_instr[5] - }) === 4'b1001); + }) == 4'b1001); assign get_address_pt[64] = (({ next_instr[0] , next_instr[2] , next_instr[4] , next_instr[5] - }) === 4'b1001); + }) == 4'b1001); assign get_address_pt[65] = (({ next_instr[0] , next_instr[1] , next_instr[4] , next_instr[5] , - next_instr[30] }) === 5'b11100); + next_instr[30] }) == 5'b11100); assign get_address_pt[66] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[27] , next_instr[30] - }) === 8'b11111110); + }) == 8'b11111110); assign get_address_pt[67] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] - }) === 4'b1011); + }) == 4'b1011); assign get_address_pt[68] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] - }) === 4'b1101); + }) == 4'b1101); assign get_address_pt[69] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , - next_instr[4] }) === 5'b10111); + next_instr[4] }) == 5'b10111); assign get_address_pt[70] = (({ next_instr[0] , next_instr[2] , - next_instr[4] }) === 3'b100); + next_instr[4] }) == 3'b100); assign get_address_pt[71] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[27] , next_instr[28] - }) === 8'b11111111); + }) == 8'b11111111); assign get_address_pt[72] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[28] , next_instr[29] - }) === 8'b11111110); + }) == 8'b11111110); assign get_address_pt[73] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[3] , - next_instr[5] }) === 5'b10111); + next_instr[5] }) == 5'b10111); assign get_address_pt[74] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[5] - }) === 4'b1101); + }) == 4'b1101); assign get_address_pt[75] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] , next_instr[5] , next_instr[26] , next_instr[28] , next_instr[30] - }) === 8'b11111110); + }) == 8'b11111110); assign get_address_pt[76] = (({ next_instr[0] , next_instr[1] , - next_instr[2] }) === 3'b110); + next_instr[2] }) == 3'b110); assign get_address_pt[77] = (({ next_instr[0] , next_instr[1] , - next_instr[2] }) === 3'b101); + next_instr[2] }) == 3'b101); assign get_address_pt[78] = (({ next_instr[0] , next_instr[1] , next_instr[2] , next_instr[4] - }) === 4'b1101); + }) == 4'b1101); assign start_addr[0] = (get_address_pt[1] | get_address_pt[5] | get_address_pt[9] | get_address_pt[13] diff --git a/dev/verilog/work/iuq_uc_rom_even.v b/dev/verilog/work/iuq_uc_rom_even.v index 0e77bdd..324d7ea 100755 --- a/dev/verilog/work/iuq_uc_rom_even.v +++ b/dev/verilog/work/iuq_uc_rom_even.v @@ -470,1003 +470,1003 @@ assign rom_instr_pt[1] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0000000); + rom_addr_l2[8] }) == 7'b0000000); assign rom_instr_pt[2] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0000000); + rom_addr_l2[8] }) == 7'b0000000); assign rom_instr_pt[3] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1010000); + rom_addr_l2[8] }) == 7'b1010000); assign rom_instr_pt[4] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000000); + }) == 6'b000000); assign rom_instr_pt[5] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b100000); + }) == 6'b100000); assign rom_instr_pt[6] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0001000); + rom_addr_l2[8] }) == 7'b0001000); assign rom_instr_pt[7] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 8'b11101000); + }) == 8'b11101000); assign rom_instr_pt[8] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 8'b10111000); + }) == 8'b10111000); assign rom_instr_pt[9] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011000); + rom_addr_l2[8] }) == 7'b0011000); assign rom_instr_pt[10] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b011000); + }) == 6'b011000); assign rom_instr_pt[11] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0100000); + rom_addr_l2[8] }) == 7'b0100000); assign rom_instr_pt[12] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0100000); + rom_addr_l2[8] }) == 7'b0100000); assign rom_instr_pt[13] = (({ rom_addr_l2[0] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b001000); + }) == 6'b001000); assign rom_instr_pt[14] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b111000); + }) == 6'b111000); assign rom_instr_pt[15] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b101000); + }) == 6'b101000); assign rom_instr_pt[16] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b101000); + }) == 6'b101000); assign rom_instr_pt[17] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b111000); + }) == 6'b111000); assign rom_instr_pt[18] = (({ rom_addr_l2[0] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01000); + rom_addr_l2[8] }) == 5'b01000); assign rom_instr_pt[19] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1000000); + rom_addr_l2[8] }) == 7'b1000000); assign rom_instr_pt[20] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1110000); + rom_addr_l2[8] }) == 7'b1110000); assign rom_instr_pt[21] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1101000); + rom_addr_l2[8] }) == 7'b1101000); assign rom_instr_pt[22] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11000); + rom_addr_l2[8] }) == 5'b11000); assign rom_instr_pt[23] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0100100); + rom_addr_l2[8] }) == 7'b0100100); assign rom_instr_pt[24] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011100); + rom_addr_l2[8] }) == 7'b0011100); assign rom_instr_pt[25] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011100); + rom_addr_l2[8] }) == 7'b0011100); assign rom_instr_pt[26] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b011100); + }) == 6'b011100); assign rom_instr_pt[27] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111100); + rom_addr_l2[8] }) == 7'b0111100); assign rom_instr_pt[28] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01100); + rom_addr_l2[8] }) == 5'b01100); assign rom_instr_pt[29] = (({ rom_addr_l2[0] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b001000); + }) == 6'b001000); assign rom_instr_pt[30] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111100); + rom_addr_l2[8] }) == 7'b0111100); assign rom_instr_pt[31] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0110000); + rom_addr_l2[8] }) == 7'b0110000); assign rom_instr_pt[32] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 8'b01001010); + }) == 8'b01001010); assign rom_instr_pt[33] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111010); + rom_addr_l2[8] }) == 7'b0111010); assign rom_instr_pt[34] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0110010); + rom_addr_l2[8] }) == 7'b0110010); assign rom_instr_pt[35] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10110); + rom_addr_l2[8] }) == 5'b10110); assign rom_instr_pt[36] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01110); + rom_addr_l2[8] }) == 5'b01110); assign rom_instr_pt[37] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10110); + rom_addr_l2[8] }) == 5'b10110); assign rom_instr_pt[38] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11110); + rom_addr_l2[8] }) == 5'b11110); assign rom_instr_pt[39] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0110010); + rom_addr_l2[8] }) == 7'b0110010); assign rom_instr_pt[40] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010010); + }) == 6'b010010); assign rom_instr_pt[41] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00010); + rom_addr_l2[8] }) == 5'b00010); assign rom_instr_pt[42] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011010); + rom_addr_l2[8] }) == 7'b0011010); assign rom_instr_pt[43] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000010); + }) == 6'b000010); assign rom_instr_pt[44] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b001010); + }) == 6'b001010); assign rom_instr_pt[45] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0000110); + rom_addr_l2[8] }) == 7'b0000110); assign rom_instr_pt[46] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0100110); + rom_addr_l2[8] }) == 7'b0100110); assign rom_instr_pt[47] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b001110); + }) == 6'b001110); assign rom_instr_pt[48] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b110010); + }) == 6'b110010); assign rom_instr_pt[49] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0101010); + rom_addr_l2[8] }) == 7'b0101010); assign rom_instr_pt[50] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11010); + rom_addr_l2[8] }) == 5'b11010); assign rom_instr_pt[51] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b111110); + }) == 6'b111110); assign rom_instr_pt[52] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10110); + rom_addr_l2[8] }) == 5'b10110); assign rom_instr_pt[53] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11010); + rom_addr_l2[8] }) == 5'b11010); assign rom_instr_pt[54] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 4'b1110); + }) == 4'b1110); assign rom_instr_pt[55] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b10000); + rom_addr_l2[8] }) == 5'b10000); assign rom_instr_pt[56] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11010); + rom_addr_l2[8] }) == 5'b11010); assign rom_instr_pt[57] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b100010); + }) == 6'b100010); assign rom_instr_pt[58] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b01010); + rom_addr_l2[8] }) == 5'b01010); assign rom_instr_pt[59] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b10110); + rom_addr_l2[8] }) == 5'b10110); assign rom_instr_pt[60] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11110); + rom_addr_l2[8] }) == 5'b11110); assign rom_instr_pt[61] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11110); + rom_addr_l2[8] }) == 5'b11110); assign rom_instr_pt[62] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b111010); + }) == 6'b111010); assign rom_instr_pt[63] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b00110); + rom_addr_l2[8] }) == 5'b00110); assign rom_instr_pt[64] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b110110); + }) == 6'b110110); assign rom_instr_pt[65] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11110); + rom_addr_l2[8] }) == 5'b11110); assign rom_instr_pt[66] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[8] }) === 7'b0011000); + rom_addr_l2[8] }) == 7'b0011000); assign rom_instr_pt[67] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b011000); + }) == 6'b011000); assign rom_instr_pt[68] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b111100); + }) == 6'b111100); assign rom_instr_pt[69] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[8] - }) === 4'b1100); + }) == 4'b1100); assign rom_instr_pt[70] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1010001); + rom_addr_l2[8] }) == 7'b1010001); assign rom_instr_pt[71] = (({ rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b101001); + }) == 6'b101001); assign rom_instr_pt[72] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111001); + rom_addr_l2[8] }) == 7'b0111001); assign rom_instr_pt[73] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1111001); + rom_addr_l2[8] }) == 7'b1111001); assign rom_instr_pt[74] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111001); + rom_addr_l2[8] }) == 7'b0111001); assign rom_instr_pt[75] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1100001); + rom_addr_l2[8] }) == 7'b1100001); assign rom_instr_pt[76] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b100001); + }) == 6'b100001); assign rom_instr_pt[77] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000001); + }) == 6'b000001); assign rom_instr_pt[78] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b100001); + }) == 6'b100001); assign rom_instr_pt[79] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1110001); + rom_addr_l2[8] }) == 7'b1110001); assign rom_instr_pt[80] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10001); + rom_addr_l2[8] }) == 5'b10001); assign rom_instr_pt[81] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b001001); + }) == 6'b001001); assign rom_instr_pt[82] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00001); + rom_addr_l2[8] }) == 5'b00001); assign rom_instr_pt[83] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b110001); + }) == 6'b110001); assign rom_instr_pt[84] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011101); + rom_addr_l2[8] }) == 7'b0011101); assign rom_instr_pt[85] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000101); + }) == 6'b000101); assign rom_instr_pt[86] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010101); + }) == 6'b010101); assign rom_instr_pt[87] = (({ rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 4'b0101); + }) == 4'b0101); assign rom_instr_pt[88] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0011101); + rom_addr_l2[8] }) == 7'b0011101); assign rom_instr_pt[89] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111101); + rom_addr_l2[8] }) == 7'b0111101); assign rom_instr_pt[90] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11101); + rom_addr_l2[8] }) == 5'b11101); assign rom_instr_pt[91] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000001); + }) == 6'b000001); assign rom_instr_pt[92] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0001101); + rom_addr_l2[8] }) == 7'b0001101); assign rom_instr_pt[93] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0111101); + rom_addr_l2[8] }) == 7'b0111101); assign rom_instr_pt[94] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0101001); + rom_addr_l2[8] }) == 7'b0101001); assign rom_instr_pt[95] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010001); + }) == 6'b010001); assign rom_instr_pt[96] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b100101); + }) == 6'b100101); assign rom_instr_pt[97] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010001); + }) == 6'b010001); assign rom_instr_pt[98] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00101); + rom_addr_l2[8] }) == 5'b00101); assign rom_instr_pt[99] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10001); + rom_addr_l2[8] }) == 5'b10001); assign rom_instr_pt[100] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 8'b01101011); + }) == 8'b01101011); assign rom_instr_pt[101] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b1110011); + rom_addr_l2[8] }) == 7'b1110011); assign rom_instr_pt[102] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b011011); + }) == 6'b011011); assign rom_instr_pt[103] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11011); + rom_addr_l2[8] }) == 5'b11011); assign rom_instr_pt[104] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10111); + rom_addr_l2[8] }) == 5'b10111); assign rom_instr_pt[105] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10111); + rom_addr_l2[8] }) == 5'b10111); assign rom_instr_pt[106] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01111); + rom_addr_l2[8] }) == 5'b01111); assign rom_instr_pt[107] = (({ rom_addr_l2[2] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 4'b0111); + }) == 4'b0111); assign rom_instr_pt[108] = (({ rom_addr_l2[1] , rom_addr_l2[6] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 4'b0111); + }) == 4'b0111); assign rom_instr_pt[109] = (({ rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01011); + rom_addr_l2[8] }) == 5'b01011); assign rom_instr_pt[110] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b000011); + }) == 6'b000011); assign rom_instr_pt[111] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00011); + rom_addr_l2[8] }) == 5'b00011); assign rom_instr_pt[112] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00011); + rom_addr_l2[8] }) == 5'b00011); assign rom_instr_pt[113] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b01011); + rom_addr_l2[8] }) == 5'b01011); assign rom_instr_pt[114] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b110011); + }) == 6'b110011); assign rom_instr_pt[115] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b011011); + }) == 6'b011011); assign rom_instr_pt[116] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0100111); + rom_addr_l2[8] }) == 7'b0100111); assign rom_instr_pt[117] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 7'b0000111); + rom_addr_l2[8] }) == 7'b0000111); assign rom_instr_pt[118] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00111); + rom_addr_l2[8] }) == 5'b00111); assign rom_instr_pt[119] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b110111); + }) == 6'b110111); assign rom_instr_pt[120] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010011); + }) == 6'b010011); assign rom_instr_pt[121] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b101011); + }) == 6'b101011); assign rom_instr_pt[122] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b010011); + }) == 6'b010011); assign rom_instr_pt[123] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 6'b100111); + }) == 6'b100111); assign rom_instr_pt[124] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11111); + rom_addr_l2[8] }) == 5'b11111); assign rom_instr_pt[125] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10011); + rom_addr_l2[8] }) == 5'b10011); assign rom_instr_pt[126] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b00111); + rom_addr_l2[8] }) == 5'b00111); assign rom_instr_pt[127] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b10011); + rom_addr_l2[8] }) == 5'b10011); assign rom_instr_pt[128] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[7] , - rom_addr_l2[8] }) === 5'b11111); + rom_addr_l2[8] }) == 5'b11111); assign rom_instr_pt[129] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[7] , rom_addr_l2[8] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[130] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b111001); + }) == 6'b111001); assign rom_instr_pt[131] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 7'b0101101); + rom_addr_l2[8] }) == 7'b0101101); assign rom_instr_pt[132] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b010001); + }) == 6'b010001); assign rom_instr_pt[133] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b010001); + }) == 6'b010001); assign rom_instr_pt[134] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b01001); + rom_addr_l2[8] }) == 5'b01001); assign rom_instr_pt[135] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b011101); + }) == 6'b011101); assign rom_instr_pt[136] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b010011); + }) == 6'b010011); assign rom_instr_pt[137] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b110011); + }) == 6'b110011); assign rom_instr_pt[138] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b10011); + rom_addr_l2[8] }) == 5'b10011); assign rom_instr_pt[139] = (({ rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 4'b0011); + }) == 4'b0011); assign rom_instr_pt[140] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 7'b0100111); + rom_addr_l2[8] }) == 7'b0100111); assign rom_instr_pt[141] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b110111); + }) == 6'b110111); assign rom_instr_pt[142] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b00111); + rom_addr_l2[8] }) == 5'b00111); assign rom_instr_pt[143] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b110111); + }) == 6'b110111); assign rom_instr_pt[144] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b000011); + }) == 6'b000011); assign rom_instr_pt[145] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b100011); + }) == 6'b100011); assign rom_instr_pt[146] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b010011); + }) == 6'b010011); assign rom_instr_pt[147] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11111); + rom_addr_l2[8] }) == 5'b11111); assign rom_instr_pt[148] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 4'b0011); + }) == 4'b0011); assign rom_instr_pt[149] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b111011); + }) == 6'b111011); assign rom_instr_pt[150] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 6'b110111); + }) == 6'b110111); assign rom_instr_pt[151] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[6] , rom_addr_l2[8] - }) === 4'b0011); + }) == 4'b0011); assign rom_instr_pt[152] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[6] , - rom_addr_l2[8] }) === 5'b11011); + rom_addr_l2[8] }) == 5'b11011); assign rom_instr_pt[153] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b011001); + }) == 6'b011001); assign rom_instr_pt[154] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[8] }) === 5'b11001); + rom_addr_l2[8] }) == 5'b11001); assign rom_instr_pt[155] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b010101); + }) == 6'b010101); assign rom_instr_pt[156] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b011101); + }) == 6'b011101); assign rom_instr_pt[157] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[8] - }) === 6'b010111); + }) == 6'b010111); assign rom_instr_pt[158] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[8] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[159] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[8] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[160] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[8] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[161] = (({ rom_addr_l2[3] , rom_addr_l2[8] - }) === 2'b11); + }) == 2'b11); assign rom_instr_pt[162] = (({ rom_addr_l2[1] , rom_addr_l2[2] , - rom_addr_l2[8] }) === 3'b011); + rom_addr_l2[8] }) == 3'b011); assign rom_instr_pt[163] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[6] , rom_addr_l2[7] - }) === 6'b011100); + }) == 6'b011100); assign rom_instr_pt[164] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[7] }) === 5'b10000); + rom_addr_l2[7] }) == 5'b10000); assign rom_instr_pt[165] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , rom_addr_l2[7] - }) === 6'b010000); + }) == 6'b010000); assign rom_instr_pt[166] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 6'b011100); + }) == 6'b011100); assign rom_instr_pt[167] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 6'b000010); + }) == 6'b000010); assign rom_instr_pt[168] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] , - rom_addr_l2[7] }) === 7'b0101101); + rom_addr_l2[7] }) == 7'b0101101); assign rom_instr_pt[169] = (({ rom_addr_l2[0] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , - rom_addr_l2[7] }) === 5'b00101); + rom_addr_l2[7] }) == 5'b00101); assign rom_instr_pt[170] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] , - rom_addr_l2[7] }) === 5'b11101); + rom_addr_l2[7] }) == 5'b11101); assign rom_instr_pt[171] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] , - rom_addr_l2[7] }) === 5'b01101); + rom_addr_l2[7] }) == 5'b01101); assign rom_instr_pt[172] = (({ rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] - }) === 4'b0011); + }) == 4'b0011); assign rom_instr_pt[173] = (({ rom_addr_l2[1] , rom_addr_l2[4] , rom_addr_l2[6] , rom_addr_l2[7] - }) === 4'b0111); + }) == 4'b0111); assign rom_instr_pt[174] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[7] }) === 5'b10101); + rom_addr_l2[7] }) == 5'b10101); assign rom_instr_pt[175] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[7] }) === 5'b10101); + rom_addr_l2[7] }) == 5'b10101); assign rom_instr_pt[176] = (({ rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 4'b1101); + }) == 4'b1101); assign rom_instr_pt[177] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , - rom_addr_l2[7] }) === 5'b10001); + rom_addr_l2[7] }) == 5'b10001); assign rom_instr_pt[178] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 4'b0001); + }) == 4'b0001); assign rom_instr_pt[179] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 4'b1101); + }) == 4'b1101); assign rom_instr_pt[180] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 6'b010111); + }) == 6'b010111); assign rom_instr_pt[181] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 6'b000011); + }) == 6'b000011); assign rom_instr_pt[182] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] , rom_addr_l2[7] - }) === 6'b010011); + }) == 6'b010011); assign rom_instr_pt[183] = (({ rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[7] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[184] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , - rom_addr_l2[7] }) === 5'b01011); + rom_addr_l2[7] }) == 5'b01011); assign rom_instr_pt[185] = (({ rom_addr_l2[0] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] - }) === 4'b1100); + }) == 4'b1100); assign rom_instr_pt[186] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[6] }) === 5'b01110); + rom_addr_l2[6] }) == 5'b01110); assign rom_instr_pt[187] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[6] }) === 5'b11110); + rom_addr_l2[6] }) == 5'b11110); assign rom_instr_pt[188] = (({ rom_addr_l2[3] , rom_addr_l2[5] , - rom_addr_l2[6] }) === 3'b010); + rom_addr_l2[6] }) == 3'b010); assign rom_instr_pt[189] = (({ rom_addr_l2[5] , rom_addr_l2[6] - }) === 2'b10); + }) == 2'b10); assign rom_instr_pt[190] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , - rom_addr_l2[6] }) === 5'b10000); + rom_addr_l2[6] }) == 5'b10000); assign rom_instr_pt[191] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] - }) === 4'b1110); + }) == 4'b1110); assign rom_instr_pt[192] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , - rom_addr_l2[6] }) === 5'b11110); + rom_addr_l2[6] }) == 5'b11110); assign rom_instr_pt[193] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] - }) === 4'b1110); + }) == 4'b1110); assign rom_instr_pt[194] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] , rom_addr_l2[6] - }) === 6'b010001); + }) == 6'b010001); assign rom_instr_pt[195] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[6] }) === 7'b0101011); + rom_addr_l2[6] }) == 7'b0101011); assign rom_instr_pt[196] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] , - rom_addr_l2[6] }) === 5'b11111); + rom_addr_l2[6] }) == 5'b11111); assign rom_instr_pt[197] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , - rom_addr_l2[6] }) === 5'b00001); + rom_addr_l2[6] }) == 5'b00001); assign rom_instr_pt[198] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , - rom_addr_l2[6] }) === 5'b00001); + rom_addr_l2[6] }) == 5'b00001); assign rom_instr_pt[199] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] - }) === 4'b0001); + }) == 4'b0001); assign rom_instr_pt[200] = (({ rom_addr_l2[0] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] - }) === 4'b0001); + }) == 4'b0001); assign rom_instr_pt[201] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , - rom_addr_l2[6] }) === 5'b00011); + rom_addr_l2[6] }) == 5'b00011); assign rom_instr_pt[202] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[6] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[203] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[6] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[204] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , - rom_addr_l2[6] }) === 5'b10001); + rom_addr_l2[6] }) == 5'b10001); assign rom_instr_pt[205] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] - }) === 4'b0001); + }) == 4'b0001); assign rom_instr_pt[206] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[6] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[207] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[6] - }) === 4'b0111); + }) == 4'b0111); assign rom_instr_pt[208] = (({ rom_addr_l2[2] , rom_addr_l2[6] - }) === 2'b01); + }) == 2'b01); assign rom_instr_pt[209] = (({ rom_addr_l2[0] , rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] - }) === 6'b011100); + }) == 6'b011100); assign rom_instr_pt[210] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[4] , rom_addr_l2[5] - }) === 4'b1010); + }) == 4'b1010); assign rom_instr_pt[211] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] - }) === 4'b1000); + }) == 4'b1000); assign rom_instr_pt[212] = (({ rom_addr_l2[3] , rom_addr_l2[5] - }) === 2'b00); + }) == 2'b00); assign rom_instr_pt[213] = (({ rom_addr_l2[1] , rom_addr_l2[3] , - rom_addr_l2[5] }) === 3'b010); + rom_addr_l2[5] }) == 3'b010); assign rom_instr_pt[214] = (({ rom_addr_l2[1] , rom_addr_l2[3] , rom_addr_l2[4] , rom_addr_l2[5] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[215] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] - }) === 4'b0111); + }) == 4'b0111); assign rom_instr_pt[216] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[5] - }) === 4'b1111); + }) == 4'b1111); assign rom_instr_pt[217] = (({ rom_addr_l2[0] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] - }) === 4'b1000); + }) == 4'b1000); assign rom_instr_pt[218] = (({ rom_addr_l2[3] , rom_addr_l2[4] - }) === 2'b00); + }) == 2'b00); assign rom_instr_pt[219] = (({ rom_addr_l2[1] , rom_addr_l2[2] , rom_addr_l2[3] , rom_addr_l2[4] - }) === 4'b1001); + }) == 4'b1001); assign rom_instr_pt[220] = (({ rom_addr_l2[3] , rom_addr_l2[4] - }) === 2'b11); + }) == 2'b11); assign rom_instr_pt[221] = (({ rom_addr_l2[0] , rom_addr_l2[2] , - rom_addr_l2[4] }) === 3'b111); + rom_addr_l2[4] }) == 3'b111); assign rom_instr_pt[222] = (({ rom_addr_l2[1] , rom_addr_l2[4] - }) === 2'b11); + }) == 2'b11); assign rom_instr_pt[223] = (({ rom_addr_l2[0] , rom_addr_l2[2] , - rom_addr_l2[3] }) === 3'b111); + rom_addr_l2[3] }) == 3'b111); assign rom_instr_pt[224] = - (({ rom_addr_l2[2] }) === 1'b0); + (({ rom_addr_l2[2] }) == 1'b0); assign rom_instr_pt[225] = 1'b1; assign template[0] = diff --git a/dev/verilog/work/lq_ctl.v b/dev/verilog/work/lq_ctl.v index b533fbd..f786126 100755 --- a/dev/verilog/work/lq_ctl.v +++ b/dev/verilog/work/lq_ctl.v @@ -3325,7 +3325,9 @@ endgenerate generate if (`BUILD_PFETCH == 0) begin : nopf - assign pf_dec_req_addr = {(63 - `CL_SIZE-64 - (2 ** `GPR_WIDTH_ENC))+1{1'b0}}; + //assign pf_dec_req_addr = {(63 - `CL_SIZE-64 - (2 ** `GPR_WIDTH_ENC))+1{1'b0}}; //wtf failed trying downsizing: -70 repeat + // [64-(2**`GPR_WIDTH_ENC):63-`CL_SIZE] + assign pf_dec_req_addr = 0; assign pf_dec_req_thrd = {`THREADS{1'b0}}; assign pf_dec_req_val = 1'b0; assign func_scan_out_int[10] = spr_pf_func_scan; diff --git a/dev/verilog/work/lq_stq.v b/dev/verilog/work/lq_stq.v index f40c5b0..a6d0352 100755 --- a/dev/verilog/work/lq_stq.v +++ b/dev/verilog/work/lq_stq.v @@ -2167,7 +2167,9 @@ module lq_stq( assign stq_push_down = stq7_cmmt_flushed_q | (stq7_cmmt_val_q & stq7_cmmt_ptr_q[0]); // since the stq is pushed down in stq7, the stq3 commit pointer will never be higher than 4 - + /*wtf downsizing experiments - this is wrong if STQ_ENTRIES < 5; is this a real requirement? + wire [0:`STQ_ENTRIES-1] stq3_cmmt_ptr_q; + */ assign stq_arb_stq3_cTag[2:4] = (stq3_cmmt_ptr_q[0:4] == 5'b10000) ? 3'b000 : (stq3_cmmt_ptr_q[0:4] == 5'b01000) ? 3'b001 : (stq3_cmmt_ptr_q[0:4] == 5'b00100) ? 3'b010 : @@ -2366,11 +2368,11 @@ module lq_stq( assign ex5_qHit_set_oth_q[`STQ_ENTRIES] = 0; assign ex5_qHit_set_miss[`STQ_ENTRIES] = 0; - always @* - begin: dummy - stq_cp_next_itag[`STQ_ENTRIES] = 0; - set_stqe_odq_resolved[`STQ_ENTRIES] = 0; - end + //always @* + initial begin + stq_cp_next_itag[`STQ_ENTRIES] = 0; + set_stqe_odq_resolved[`STQ_ENTRIES] = 0; + end always @(*) diff --git a/dev/verilog/work/mmq.v b/dev/verilog/work/mmq.v index 7f0b0cb..39cebde 100755 --- a/dev/verilog/work/mmq.v +++ b/dev/verilog/work/mmq.v @@ -2480,119 +2480,119 @@ mmq_perv mmq_perv( generate if (`EXPAND_TLB_TYPE == 0) begin : eratonly_tieoffs_gen - assign mm_iu_ierat_rel_val_sig = {-3{1'b0}}; - assign mm_iu_ierat_rel_data_sig = {`ERAT_REL_DATA_WIDTH{1'b0}}; - assign mm_xu_derat_rel_val_sig = {-3{1'b0}}; - assign mm_xu_derat_rel_data_sig = {`ERAT_REL_DATA_WIDTH{1'b0}}; - assign tlb_cmp_ierat_dup_val_sig = {-5{1'b0}}; - assign tlb_cmp_derat_dup_val_sig = {-5{1'b0}}; - assign tlb_cmp_erat_dup_wait_sig = {0{1'b0}}; - assign tlb_ctl_barrier_done_sig = {0{1'b0}}; - assign tlb_ctl_ex2_flush_req_sig = {0{1'b0}}; - assign tlb_ctl_ex2_illeg_instr_sig = {0{1'b0}}; - assign tlb_ctl_ex6_illeg_instr_sig = {0{1'b0}}; - assign tlb_ctl_ex2_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; - assign tlb_ctl_ord_type = {-1{1'b0}}; - assign tlb_tag4_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; - assign tlb_tag5_itag_sig = {`ITAG_SIZE_ENC{1'b0}}; - assign tlb_tag5_emq_sig = {`EMQ_ENTRIES{1'b0}}; - assign tlb_tag5_except = {0{1'b0}}; + assign mm_iu_ierat_rel_val_sig = 0; + assign mm_iu_ierat_rel_data_sig = 0; + assign mm_xu_derat_rel_val_sig = 0; + assign mm_xu_derat_rel_data_sig = 0; + assign tlb_cmp_ierat_dup_val_sig = 0; + assign tlb_cmp_derat_dup_val_sig = 0; + assign tlb_cmp_erat_dup_wait_sig = 0; + assign tlb_ctl_barrier_done_sig = 0; + assign tlb_ctl_ex2_flush_req_sig = 0; + assign tlb_ctl_ex2_illeg_instr_sig = 0; + assign tlb_ctl_ex6_illeg_instr_sig = 0; + assign tlb_ctl_ex2_itag_sig = 0; + assign tlb_ctl_ord_type = 0; + assign tlb_tag4_itag_sig = 0; + assign tlb_tag5_itag_sig = 0; + assign tlb_tag5_emq_sig = 0; + assign tlb_tag5_except = 0; assign tlb_req_quiesce_sig = {`THDID_WIDTH{1'b1}}; assign tlb_ctl_quiesce_sig = {`MM_THREADS{1'b1}}; assign htw_quiesce_sig = {`THDID_WIDTH{1'b1}}; // missing perf count signals - assign tlb_cmp_perf_event_t0 = {10{1'b0}}; - assign tlb_cmp_perf_event_t1 = {10{1'b0}}; - assign tlb_cmp_perf_state = {0{1'b0}}; - assign derat_req0_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign derat_req0_emq_sig = {`EMQ_ENTRIES{1'b0}}; - assign derat_req0_valid_sig = 1'b0; - assign derat_req0_nonspec_sig = 1'b0; - assign derat_req1_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign derat_req1_emq_sig = {`EMQ_ENTRIES{1'b0}}; - assign derat_req1_valid_sig = 1'b0; - assign derat_req1_nonspec_sig = 1'b0; - assign derat_req2_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign derat_req2_emq_sig = {`EMQ_ENTRIES{1'b0}}; - assign derat_req2_valid_sig = 1'b0; - assign derat_req2_nonspec_sig = 1'b0; - assign derat_req3_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign derat_req3_emq_sig = {`EMQ_ENTRIES{1'b0}}; - assign derat_req3_valid_sig = 1'b0; - assign derat_req3_nonspec_sig = 1'b0; - assign ierat_req0_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign ierat_req0_valid_sig = 1'b0; - assign ierat_req0_nonspec_sig = 1'b0; - assign ierat_req1_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign ierat_req1_valid_sig = 1'b0; - assign ierat_req1_nonspec_sig = 1'b0; - assign ierat_req2_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign ierat_req2_valid_sig = 1'b0; - assign ierat_req2_nonspec_sig = 1'b0; - assign ierat_req3_thdid_sig = {`THDID_WIDTH{1'b0}}; - assign ierat_req3_valid_sig = 1'b0; - assign ierat_req3_nonspec_sig = 1'b0; - assign tlb_tag0_thdid = {`THDID_WIDTH{1'b0}}; - assign tlb_tag0_type = {-6{1'b0}}; - assign tlb_seq_idle = 1'b0; - assign htw_req0_valid = 1'b0; - assign htw_req0_thdid = {`THDID_WIDTH{1'b0}}; - assign htw_req0_type = {0{1'b0}}; - assign htw_req1_valid = 1'b0; - assign htw_req1_thdid = {`THDID_WIDTH{1'b0}}; - assign htw_req1_type = {0{1'b0}}; - assign htw_req2_valid = 1'b0; - assign htw_req2_thdid = {`THDID_WIDTH{1'b0}}; - assign htw_req2_type = {0{1'b0}}; - assign htw_req3_valid = 1'b0; - assign htw_req3_thdid = {`THDID_WIDTH{1'b0}}; - assign htw_req3_type = {0{1'b0}}; - assign tlb_cmp_perf_miss_direct = 1'b0; - assign tlb_cmp_perf_hit_direct = 1'b0; - assign tlb_cmp_perf_hit_indirect = 1'b0; - assign tlb_cmp_perf_hit_first_page = 1'b0; - assign tlb_cmp_perf_ptereload = 1'b0; - assign tlb_cmp_perf_ptereload_noexcep = 1'b0; - assign tlb_cmp_perf_lrat_request = 1'b0; - assign tlb_cmp_perf_lrat_miss = 1'b0; - assign tlb_cmp_perf_pt_fault = 1'b0; - assign tlb_cmp_perf_pt_inelig = 1'b0; - assign tlb_ctl_perf_tlbwec_resv = 1'b0; - assign tlb_ctl_perf_tlbwec_noresv = 1'b0; + assign tlb_cmp_perf_event_t0 = 0; + assign tlb_cmp_perf_event_t1 = 0; + assign tlb_cmp_perf_state = 0; + assign derat_req0_thdid_sig = 0; + assign derat_req0_emq_sig = 0; + assign derat_req0_valid_sig = 0; + assign derat_req0_nonspec_sig = 0; + assign derat_req1_thdid_sig = 0; + assign derat_req1_emq_sig = 0; + assign derat_req1_valid_sig = 0; + assign derat_req1_nonspec_sig = 0; + assign derat_req2_thdid_sig = 0; + assign derat_req2_emq_sig = 0; + assign derat_req2_valid_sig = 0; + assign derat_req2_nonspec_sig = 0; + assign derat_req3_thdid_sig = 0; + assign derat_req3_emq_sig = 0; + assign derat_req3_valid_sig = 0; + assign derat_req3_nonspec_sig = 0; + assign ierat_req0_thdid_sig = 0; + assign ierat_req0_valid_sig = 0; + assign ierat_req0_nonspec_sig = 0; + assign ierat_req1_thdid_sig = 0; + assign ierat_req1_valid_sig = 0; + assign ierat_req1_nonspec_sig = 0; + assign ierat_req2_thdid_sig = 0; + assign ierat_req2_valid_sig = 0; + assign ierat_req2_nonspec_sig = 0; + assign ierat_req3_thdid_sig = 0; + assign ierat_req3_valid_sig = 0; + assign ierat_req3_nonspec_sig = 0; + assign tlb_tag0_thdid = 0; + assign tlb_tag0_type = 0; + assign tlb_seq_idle = 0; + assign htw_req0_valid = 0; + assign htw_req0_thdid = 0; + assign htw_req0_type = 0; + assign htw_req1_valid = 0; + assign htw_req1_thdid = 0; + assign htw_req1_type = 0; + assign htw_req2_valid = 0; + assign htw_req2_thdid = 0; + assign htw_req2_type = 0; + assign htw_req3_valid = 0; + assign htw_req3_thdid = 0; + assign htw_req3_type = 0; + assign tlb_cmp_perf_miss_direct = 0; + assign tlb_cmp_perf_hit_direct = 0; + assign tlb_cmp_perf_hit_indirect = 0; + assign tlb_cmp_perf_hit_first_page = 0; + assign tlb_cmp_perf_ptereload = 0; + assign tlb_cmp_perf_ptereload_noexcep = 0; + assign tlb_cmp_perf_lrat_request = 0; + assign tlb_cmp_perf_lrat_miss = 0; + assign tlb_cmp_perf_pt_fault = 0; + assign tlb_cmp_perf_pt_inelig = 0; + assign tlb_ctl_perf_tlbwec_resv = 0; + assign tlb_ctl_perf_tlbwec_noresv = 0; // missing debug signals - assign tlb_cmp_dbg_tag4 = {`TLB_TAG_WIDTH{1'b0}}; - assign tlb_cmp_dbg_tag4_wayhit = {`TLB_WAYS+1{1'b0}}; - assign tlb_cmp_dbg_addr4 = {`TLB_ADDR_WIDTH{1'b0}}; - assign tlb_cmp_dbg_tag4_way = {`TLB_WAY_WIDTH{1'b0}}; - assign mm_xu_eratmiss_done_sig = {0{1'b0}}; - assign mm_xu_tlb_miss_sig = {0{1'b0}}; - assign mm_xu_lrat_miss_sig = {0{1'b0}}; - assign mm_xu_tlb_inelig_sig = {0{1'b0}}; - assign mm_xu_pt_fault_sig = {0{1'b0}}; - assign mm_xu_hv_priv_sig = {0{1'b0}}; - assign mm_xu_cr0_eq_sig = {0{1'b0}}; - assign mm_xu_cr0_eq_valid_sig = {0{1'b0}}; - assign mm_xu_esr_pt_sig = {0{1'b0}}; - assign mm_xu_esr_data_sig = {0{1'b0}}; - assign mm_xu_esr_epid_sig = {0{1'b0}}; - assign mm_xu_esr_st_sig = {0{1'b0}}; - assign mm_xu_tlb_miss_ored_sig = 1'b0; - assign mm_xu_lrat_miss_ored_sig = 1'b0; - assign mm_xu_tlb_inelig_ored_sig = 1'b0; - assign mm_xu_pt_fault_ored_sig = 1'b0; - assign mm_xu_hv_priv_ored_sig = 1'b0; - assign mm_xu_cr0_eq_ored_sig = 1'b0; - assign mm_xu_cr0_eq_valid_ored_sig = 1'b0; - assign mm_xu_tlb_multihit_err_sig = {0{1'b0}}; - assign mm_xu_tlb_par_err_sig = {0{1'b0}}; - assign mm_xu_lru_par_err_sig = {0{1'b0}}; - assign mm_xu_ord_tlb_multihit_sig = {0{1'b0}}; - assign mm_xu_ord_tlb_par_err_sig = {0{1'b0}}; - assign mm_xu_ord_lru_par_err_sig = {0{1'b0}}; - assign mm_pc_tlb_multihit_err_ored_sig = 1'b0; - assign mm_pc_tlb_par_err_ored_sig = 1'b0; - assign mm_pc_lru_par_err_ored_sig = 1'b0; - assign tlb_snoop_ack = 1'b0; + assign tlb_cmp_dbg_tag4 = 0; + assign tlb_cmp_dbg_tag4_wayhit = 0; + assign tlb_cmp_dbg_addr4 = 0; + assign tlb_cmp_dbg_tag4_way = 0; + assign mm_xu_eratmiss_done_sig = 0; + assign mm_xu_tlb_miss_sig = 0; + assign mm_xu_lrat_miss_sig = 0; + assign mm_xu_tlb_inelig_sig = 0; + assign mm_xu_pt_fault_sig = 0; + assign mm_xu_hv_priv_sig = 0; + assign mm_xu_cr0_eq_sig = 0; + assign mm_xu_cr0_eq_valid_sig = 0; + assign mm_xu_esr_pt_sig = 0; + assign mm_xu_esr_data_sig = 0; + assign mm_xu_esr_epid_sig = 0; + assign mm_xu_esr_st_sig = 0; + assign mm_xu_tlb_miss_ored_sig = 0; + assign mm_xu_lrat_miss_ored_sig = 0; + assign mm_xu_tlb_inelig_ored_sig = 0; + assign mm_xu_pt_fault_ored_sig = 0; + assign mm_xu_hv_priv_ored_sig = 0; + assign mm_xu_cr0_eq_ored_sig = 0; + assign mm_xu_cr0_eq_valid_ored_sig = 0; + assign mm_xu_tlb_multihit_err_sig = 0; + assign mm_xu_tlb_par_err_sig = 0; + assign mm_xu_lru_par_err_sig = 0; + assign mm_xu_ord_tlb_multihit_sig = 0; + assign mm_xu_ord_tlb_par_err_sig = 0; + assign mm_xu_ord_lru_par_err_sig = 0; + assign mm_pc_tlb_multihit_err_ored_sig = 0; + assign mm_pc_tlb_par_err_ored_sig = 0; + assign mm_pc_lru_par_err_ored_sig = 0; + assign tlb_snoop_ack = 0; end endgenerate diff --git a/dev/verilog/work/mmq_tlb_lrat_matchline.v b/dev/verilog/work/mmq_tlb_lrat_matchline.v index 1c860a3..8a84d9c 100755 --- a/dev/verilog/work/mmq_tlb_lrat_matchline.v +++ b/dev/verilog/work/mmq_tlb_lrat_matchline.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* @@ -43,9 +43,16 @@ `include "tri_a2o.vh" `include "mmu_a2o.vh" -`define LRAT_MAXSIZE_LOG2 40 // 1T largest pgsize -`define LRAT_MINSIZE_LOG2 20 // 1M smallest pgsize -`define LRAT_CMPMASK_WIDTH 7 + +`ifndef LRATE_MAXSIZE_LOG2 // 1T largest pgsize +`define LRAT_MAXSIZE_LOG2 40 +`endif +`ifndef LRAT_MINSIZE_LOG2 // 1M smallest pgsize +`define LRAT_MINSIZE_LOG2 20 +`endif +`ifndef LRAT_CMPMASK_WIDTH +`define LRAT_CMPMASK_WIDTH 7 +`endif module mmq_tlb_lrat_matchline( diff --git a/dev/verilog/work/mmu_a2o.vh b/dev/verilog/work/mmu_a2o.vh index de2decf..8a25aa5 100755 --- a/dev/verilog/work/mmu_a2o.vh +++ b/dev/verilog/work/mmu_a2o.vh @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // *!**************************************************************** // *! FILENAME : mmu_a2o.vh @@ -35,8 +35,15 @@ `ifndef _mmu_a2o_vh_ `define _mmu_a2o_vh_ -`define EXPAND_TYPE 2 // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) -`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array + +// why not use main setting? +`ifndef EXPAND_TYPE +`define EXPAND_TYPE 1 // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) +`endif + +`ifndef EXPAND_TLB_TYPE +`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array +`endif // Use this line for A2o core. Comment out for A2i design. `define A2O @@ -63,8 +70,6 @@ `define MM_THREADS_POOL_ENC 0 `endif - - `define THDID_WIDTH 4 // this is a pre-defined tag field width `define PID_WIDTH 14 `define PID_WIDTH_ERAT 8 @@ -111,9 +116,11 @@ `define CHECK_PARITY 1 `ifdef A2O +`ifndef EMQ_ENTRIES +`define EMQ_ENTRIES 4 +`endif `define DEBUG_TRACE_WIDTH 32 `define ITAG_SIZE_ENC 7 -`define EMQ_ENTRIES 4 `define TLB_TAG_WIDTH 122 `define MESR1_WIDTH 24 // 4 x 6 bits, 1 of 64 events `define MESR2_WIDTH 24