From 975bb2445dded9d16fcbae6ea7aab0e49d82e5bc Mon Sep 17 00:00:00 2001
From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com>
Date: Sat, 16 Jul 2022 15:32:15 -0500
Subject: [PATCH] make mem visible in iverilog dump

---
 dev/verilog/trilib_clk1x/tri_144x78_2r4w.v | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v b/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v
index 6c8de0c..49b8517 100755
--- a/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v
+++ b/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v
@@ -105,6 +105,18 @@ module tri_144x78_2r4w(
          mem[i] = 0;
    end
 
+   //wtf:icarus $dumpvars cannot dump a vpiMemory
+   generate
+       genvar j;
+       for (j = 0; j < 144; j=j+1) begin: loc
+          wire [64-`GPR_WIDTH:63] dat;
+          wire [0:7] par;
+          // 4b0
+          assign dat = mem[j][64-`GPR_WIDTH:63];
+          assign par = mem[j][64:63 + `GPR_WIDTH/8];
+       end
+   endgenerate
+
    assign r1a_d = r_addr_in_1;
    assign r2a_d = r_addr_in_2;