From 9ffdf5ac76f3930871bfe79c2861083b257e4017 Mon Sep 17 00:00:00 2001
From: Bill Flynn <52765606+openpowerwtf@users.noreply.github.com>
Date: Sun, 14 Aug 2022 12:11:07 -0500
Subject: [PATCH] Update README.md

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 93d8981..e0fe272 100644
--- a/README.md
+++ b/README.md
@@ -6,12 +6,12 @@
 
    * compiles with verilator, iverilog, yosys
    * runs simple version of kernel/bios/random test with cocotb (A2L2 interface partially implemented in Python) and Verilog core wrapper (A2L2<->mem interface)
+   * wrapper converts A2L2 interface to mem and Wishbone interfaces
    * verilator builds, but does not simulate correctly
 
 ## To Do
 
    * continue with cocotb testing
-   * add A2Node bridge to WB, and Litex wrapper
    * experiment with parameters to create smaller version(s) for OpenLane
 
 # Original Release