diff --git a/dev/verilog/a2node/a2owb.v b/dev/verilog/a2node/a2owb.v index e1d99eb..5c52303 100644 --- a/dev/verilog/a2node/a2owb.v +++ b/dev/verilog/a2node/a2owb.v @@ -32,7 +32,8 @@ module a2owb ( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_in, output scan_out, @@ -183,7 +184,8 @@ wire [0:`THREADS-1] an_ac_sync_ack; wire [0:`THREADS-1] an_ac_reservation_vld; c c0( - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(scan_in), .scan_out(scan_out), @@ -308,7 +310,7 @@ c c0( ); a2l2wb n0( - .clk(clk_1x), + .clk(clk), .rst(rst), // request @@ -437,11 +439,4 @@ a2l2wb n0( ); -wire clk_1x, clk_2x, clk_4x, rst; - -assign clk_1x = nclk[0]; -assign clk_2x = nclk[2]; -assign clk_4x = nclk[3]; -assign rst = nclk[1]; - endmodule \ No newline at end of file diff --git a/dev/verilog/a2node_verilator/a2owb.v b/dev/verilog/a2node_verilator/a2owb.v index 4161aea..ee9e79a 100644 --- a/dev/verilog/a2node_verilator/a2owb.v +++ b/dev/verilog/a2node_verilator/a2owb.v @@ -34,7 +34,8 @@ module a2owb ( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_in, output scan_out, @@ -251,7 +252,8 @@ assign an_ac_lbist_ary_wrt_thru_dc = 0; c c0( - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(scan_in), .scan_out(scan_out), @@ -376,7 +378,7 @@ c c0( ); a2l2wb n0( - .clk(clk_1x), + .clk(clk), .rst(rst), // request @@ -505,11 +507,4 @@ a2l2wb n0( ); -wire clk_1x, clk_2x, clk_4x, rst; - -assign clk_1x = nclk[0]; -assign clk_2x = nclk[2]; -assign clk_4x = nclk[3]; -assign rst = nclk[1]; - endmodule \ No newline at end of file diff --git a/dev/verilog/a2node_verilator/vtable b/dev/verilog/a2node_verilator/vtable deleted file mode 100755 index 83fe740..0000000 --- a/dev/verilog/a2node_verilator/vtable +++ /dev/null @@ -1,427 +0,0 @@ -#!/usr/bin/python3 -# -# Parse table comments and create equations. - -from optparse import OptionParser -import re -from shutil import copyfile - -#-------------------------------------------------------------------------------------------------- -# Initialize - -TYPE_INPUT = 0 -TYPE_OUTPUT = 1 -TYPE_SKIP = 99 - -lines = [] -tableMatches = [] -tableNames = [] -tableLines = [] -tables = {} - -failOnError = True -inFile = 'test.vhdl' -outFileExt = 'vtable' -overwrite = True -backupExt = 'orig' -backup = True -noisy = False -quiet = False -verilog = False - -#-------------------------------------------------------------------------------------------------- -# Handle command line - -usage = 'vtable [options] inFile' - -parser = OptionParser(usage) -parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt) -parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite)) -parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup)) -parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet)) -parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy)) -parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog)) - -options, args = parser.parse_args() - -if len(args) != 1: - parser.error(usage) - quit(-1) -else: - inFile = args[0] - -if options.overwrite == '0': - overwrite = False -elif options.overwrite == '1': - overwrite == True - if options.outFile is not None: - parser.error('Can\'t specify outfile and overrite!') - quit(-1) -elif options.overwrite is not None: - parser.error('overwrite: 0|1') - quit(-1) - -if options.quiet is not None: - quiet = True - -if options.noisy is not None: - noisy = True - -if options.verilog is not None: - verilog = True - -if options.backup == '0': - backup = False -elif options.backup == '1': - backup == True -elif options.backup is not None: - parser.error('backup: 0|1') - quit(-1) - -if options.outFile is not None: - outFile = options.outFile -elif overwrite: - outFile = inFile -else: - outFile = inFile + '.' + outFileExt - -backupFile = inFile + '.' + backupExt - -#-------------------------------------------------------------------------------------------------- -# Objects - -class Signal: - - def __init__(self, name, type): - self.name = name; - self.type = type; - -class Table: - - def __init__(self, name): - self.name = name - self.source = [] - self.signals = {} - self.signalsByCol = {} - self.typesByCol = {} - self.specs = [] # list of specsByCol - self.equations = [] - self.added = False - - def validate(self): - # check that all signals have a good type - for col in self.signalsByCol: - if col not in self.typesByCol: - error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col]) - elif self.typesByCol[col] == None: - error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col])) - - def makeRTL(self, form=None): - outputsByCol = {} - - - #for col,type in self.typesByCol.items(): - for col in sorted(self.typesByCol): - type = self.typesByCol[col] - if type == TYPE_OUTPUT: - if col in self.signalsByCol: - outputsByCol[col] = self.signalsByCol[col] - else: - print(self.signalsByCol) - print(self.typesByCol) - error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists') - - #for sigCol,sig in outputsByCol.items(): - for sigCol in sorted(outputsByCol): - sig = outputsByCol[sigCol] - if not verilog: - line = sig + ' <= ' - else: - line = 'assign ' + sig + ' = ' - nonzero = False - for specsByCol in self.specs: - terms = [] - if sigCol not in specsByCol: - #error('* Output ' + sig + ' has no specified value for column ' + str(col)) - 1 # no error, can be dontcare - elif specsByCol[sigCol] == '1': - for col,val in specsByCol.items(): - if col not in self.typesByCol: - if noisy: - error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!! - elif self.typesByCol[col] == TYPE_INPUT: - if val == '0': - terms.append(opNot + self.signalsByCol[col]) - if nonzero and len(terms) == 1: - line = line + ') ' + opOr + '\n ('; - elif len(terms) == 1: - line = line + '\n (' - nonzero = True - elif val == '1': - terms.append(self.signalsByCol[col]) - if nonzero and len(terms) == 1: - line = line + ') ' + opOr + '\n ('; - elif len(terms) == 1: - line = line + '\n (' - nonzero = True - else: - error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')') - if len(terms) > 0: - line = line + (' ' + opAnd + ' ').join(terms) - if not nonzero: - line = line + zero + ";"; - else: - line = line + ');' - self.equations.append(line) - - return self.equations - - def printv(self): - self.makeRTL() - print('\n'.join(self.equations)) - - def printinfo(self): - print('Table: ' + self.name) - print - for l in self.source: - print(l) - print - print('Signals by column:') - for col in sorted(self.signalsByCol): - print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out')) - - -#-------------------------------------------------------------------------------------------------- -# Functions - -def error(msg, quitOverride=None): - print('*** ' + msg) - if quitOverride == False: - 1 - elif (quitOverride == None) or failOnError: - quit(-10) - elif quitOverride: - quit(-10) - -#-------------------------------------------------------------------------------------------------- -# Do something - -if not verilog: - openBracket = '(' - closeBracket = ')' - opAnd = 'and' - opOr = 'or' - opNot = 'not ' - zero = "'0'" - tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)') - tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)') - commentPattern = re.compile(r'^\s*?(--.*$|\s*$)') - tableLinePattern = re.compile(r'^.*?--(.*)') - namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)') -else: - openBracket = '[' - closeBracket = ']' - opAnd = '&' - opOr = '|' - opNot = '~' - zero = "'b0" - tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)') - tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)') - commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)') - tableLinePattern = re.compile(r'^.*?\/\/(.*)') - namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)') - -# find the lines with table spec -try: - inf = open(inFile) - for i, line in enumerate(inf): - lines.append(line.strip('\n')) - for match in re.finditer(tablePattern, line): - tableMatches.append(i) - inf.close() -except Exception as e: - error('Error opening input file ' + inFile + '\n' + str(e), True) - -# validate matches; should be paired, nothing but comments and empties; table may be named -# between them - -for i in range(0, len(tableMatches), 2): - - if i + 1 > len(tableMatches) - 1: - error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True) - - tLines = lines[tableMatches[i]:tableMatches[i+1]+1] - tableLines.append(tLines) - tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0] - if tName is None: - tName = 'noname_' + str(tableMatches[i] + 1) - tableNames.append(tName) - - for line in tLines: - if not re.match(commentPattern, line): - error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True) - -print('Found tables: ' + ', '.join(tableNames)) - -# build table objects - -for table, tName in zip(tableLines, tableNames): - print('Parsing ' + tName + '...') - namesByCol = {} - colsByName = {} - bitsByCol = {} - typesByCol = {} - specs = [] - -# parse the table - do by Table.parse() - tLines = table[1:-1] # exclude --tbl - for line in tLines: - if line.strip() == '': - continue - try: - spec = re.search(tableLinePattern, line).groups()[0] - except Exception as e: - error('Problem parsing table line:\n' + line, True) - if len(spec) > 0: - if spec[0] == 'n': - for match in re.finditer(namePattern, spec[1:]): - # col 0 is first col after n - namesByCol[match.start()] = match.groups()[0] - colsByName[match.groups()[0]] = match.start() - elif spec[0] == 'b': - for i, c in enumerate(spec[1:]): - if c == ' ' or c == '|': - continue - try: - bit = int(c) - except: - error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line) - bit = None - if i in bitsByCol and bitsByCol[i] is not None: - bitsByCol[i] = bitsByCol[i]*10+bit - else: - bitsByCol[i] = bit - elif spec[0] == 't': - for i, c in enumerate(spec[1:]): - if c.lower() == 'i': - typesByCol[i] = TYPE_INPUT - elif c.lower() == 'o': - typesByCol[i] = TYPE_OUTPUT - elif c.lower() == '*': - typesByCol[i] = TYPE_SKIP - elif c != ' ': - error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line) - typesByCol[i] = None - else: - typesByCol[i] = None - elif spec[0] == 's': - specsByCol = {} - for i, c in enumerate(spec[1:]): - if c == '0' or c == '1': - specsByCol[i] = c - specs.append(specsByCol) - else: - #print('other:') - #print(line) - 1 - -# create table object - -# add strand to name where defined; don't combine for now into vector -# consecutive strands belong to the last defined name - lastName = None - lastCol = 0 - signalsByCol = {} - - for col,name in namesByCol.items(): # load with unstranded names - signalsByCol[col] = name - -# sort by col so consecutive columns can be easily tracked - #for col,val in bitsByCol.items(): # update with stranded names - for col in sorted(bitsByCol): - val = bitsByCol[col] - - if col > lastCol + 1: - lastName = None - if val is None: - lastName = None - if col in namesByCol: - if val is None: - signalsByCol[col] = namesByCol[col] - else: - lastName = namesByCol[col] - signalsByCol[col] = lastName + openBracket + str(val) + closeBracket - elif lastName is not None: - signalsByCol[col] = lastName + openBracket + str(val) + closeBracket - else: - error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.') - lastCol = col - - t = Table(tName) - t.source = table - t.signalsByCol = signalsByCol - t.typesByCol = typesByCol - t.specs = specs - - tables[tName] = t - -for name in tables: - t = tables[name] - t.validate() - t.makeRTL() - -print() -print('Results:') - -# find the lines with generate spec and replace them with new version -outLines = [] -inTable = False -for i, line in enumerate(lines): - if not inTable: - match = re.search(tableGenPattern, line) - if match is not None: - tName = match.groups(1)[0] - if tName not in tables: - if tName == 1: - tName = '' - error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True) - else: - outLines.append(line) - outLines += tables[tName].equations - tables[tName].added = True - inTable = True - else: - outLines.append(line) - else: - match = re.search(tableGenPattern, line) - if match is not None: - if match.groups(1)[0] != tName: - error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True) - outLines.append(line) - inTable = False - else: - 1#print('stripped: ' + line) - -if backup: - try: - copyfile(inFile, backupFile) - except Exception as e: - error('Error creating backup file!\n' + str(e), True) - -try: - of = open(outFile, 'w') - for line in outLines: - of.write("%s\n" % line) -except Exception as e: - error('Error writing output file ' + outFile + '!\n' + str(e), True) - -print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames)) -notAdded = {} -for table in tables: - if not tables[table].added: - notAdded[table] = True -print('Output file: ' + outFile) -if backup: - print('Backup file: ' + backupFile) -if len(notAdded) != 0: - error('Tables generated but not added to file! ' + ', '.join(notAdded)) diff --git a/dev/verilog/a2node_wb/a2owb.v b/dev/verilog/a2node_wb/a2owb.v index 4161aea..2cfa922 100644 --- a/dev/verilog/a2node_wb/a2owb.v +++ b/dev/verilog/a2node_wb/a2owb.v @@ -34,7 +34,8 @@ module a2owb ( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_in, output scan_out, @@ -251,7 +252,8 @@ assign an_ac_lbist_ary_wrt_thru_dc = 0; c c0( - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(scan_in), .scan_out(scan_out), @@ -505,11 +507,4 @@ a2l2wb n0( ); -wire clk_1x, clk_2x, clk_4x, rst; - -assign clk_1x = nclk[0]; -assign clk_2x = nclk[2]; -assign clk_4x = nclk[3]; -assign rst = nclk[1]; - endmodule \ No newline at end of file diff --git a/dev/verilog/a2o_litex/a2owb.v b/dev/verilog/a2o_litex/a2owb.v index bbe0c30..a861c89 100644 --- a/dev/verilog/a2o_litex/a2owb.v +++ b/dev/verilog/a2o_litex/a2owb.v @@ -60,8 +60,7 @@ module a2owb ( - input clk_1x, - input clk_2x, + input clk, input rst, input [0:31] cfg_dat, @@ -83,7 +82,6 @@ module a2owb ( input [31:0] wb_datr ); -wire [0:`NCLK_WIDTH-1] nclk; wire [0:`THREADS-1] an_ac_stcx_complete /*verilator public */; wire [0:`THREADS-1] an_ac_stcx_pass; wire an_ac_icbi_ack; @@ -206,8 +204,6 @@ wire an_ac_hang_pulse; //wire ac_an_reset_3_request; //wire ac_an_reset_wd_request; -assign nclk = {clk_1x, rst, clk_2x, 3'b00}; - assign mem_dat = 0; assign an_ac_chipid_dc = 4'h0; @@ -251,7 +247,8 @@ assign an_ac_uncond_dbg_event = 0; c c0( - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(scan_in), .scan_out(), @@ -379,7 +376,7 @@ c c0( ); a2l2wb n0( - .clk(clk_1x), + .clk(clk), .rst(rst), .cfg_wr(cfg_wr), diff --git a/dev/verilog/a2o_litex/tri_a2o.vh b/dev/verilog/a2o_litex/tri_a2o.vh index a2060f7..400ff43 100755 --- a/dev/verilog/a2o_litex/tri_a2o.vh +++ b/dev/verilog/a2o_litex/tri_a2o.vh @@ -49,6 +49,9 @@ `define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array //`define EXPAND_TLB_TYPE 0 // doesn't work in sim +// 0: none 1: DP +//`define FLOAT_TYPE 0 // fails with completion x's in sim +`define FLOAT_TYPE 1 /*wtf these are a mess; need to be doc'd and create dependency reqts and legal ranges; shrinking values causes lots of bit sel vector problems, and sim fails diff --git a/dev/verilog/clkgating/mmq_spr.v b/dev/verilog/clkgating/mmq_spr.v deleted file mode 100755 index 954a526..0000000 --- a/dev/verilog/clkgating/mmq_spr.v +++ /dev/null @@ -1,5949 +0,0 @@ -// © IBM Corp. 2020 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -//******************************************************************** -//* TITLE: Memory Management Unit Special Purpose Registers -//********************************************************************* - -`timescale 1 ns / 1 ns - -`include "tri_a2o.vh" -`include "mmu_a2o.vh" - -module mmq_spr( - - inout vdd, - inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, - - input [0:`THREADS-1] cp_flush, - output [0:`MM_THREADS-1] cp_flush_p1, - - input tc_ccflush_dc, - input tc_scan_dis_dc_b, - input tc_scan_diag_dc, - input tc_lbist_en_dc, - - input lcb_d_mode_dc, - input lcb_clkoff_dc_b, - input lcb_act_dis_dc, - input [0:4] lcb_mpw1_dc_b, - input lcb_mpw2_dc_b, - input [0:4] lcb_delay_lclkr_dc, - -(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) - input [0:1] ac_func_scan_in, -(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) - output [0:1] ac_func_scan_out, -(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) - input ac_bcfg_scan_in, -(* pin_data="PIN_FUNCTION=/SCAN_OUT/" *) - output ac_bcfg_scan_out, - - input pc_sg_2, - input pc_func_sl_thold_2, - input pc_func_slp_sl_thold_2, - input pc_func_slp_nsl_thold_2, - input pc_cfg_sl_thold_2, - input pc_cfg_slp_sl_thold_2, - input pc_fce_2, - input xu_mm_ccr2_notlb_b, - input [5:6] mmucr2_act_override, - input [29:29+`MM_THREADS-1] tlb_delayed_act, - -`ifdef WAIT_UPDATES - // 0 - val - // 1 - I=0/D=1 - // 2 - TLB miss - // 3 - Storage int (TLBI/PTfault) - // 4 - LRAT miss - // 5 - Mcheck - input [0:5] cp_mm_except_taken_t0, -`ifdef MM_THREADS2 - input [0:5] cp_mm_except_taken_t1, -`endif - output [0:`MM_THREADS+5-1] cp_mm_perf_except_taken_q, - // 0:1 - thdid/val - // 2 - I=0/D=1 - // 3 - TLB miss - // 4 - Storage int (TLBI/PTfault) - // 5 - LRAT miss - // 6 - Mcheck -`endif - - - output [0:`PID_WIDTH-1] mm_iu_ierat_pid0, -`ifdef MM_THREADS2 - output [0:`PID_WIDTH-1] mm_iu_ierat_pid1, -`endif - output [0:19] mm_iu_ierat_mmucr0_0, -`ifdef MM_THREADS2 - output [0:19] mm_iu_ierat_mmucr0_1, -`endif - input [0:17] iu_mm_ierat_mmucr0, - input [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we, - output [0:8] mm_iu_ierat_mmucr1, - input [0:3] iu_mm_ierat_mmucr1, - input [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we, - - output [0:`PID_WIDTH-1] mm_xu_derat_pid0, -`ifdef MM_THREADS2 - output [0:`PID_WIDTH-1] mm_xu_derat_pid1, -`endif - output [0:19] mm_xu_derat_mmucr0_0, -`ifdef MM_THREADS2 - output [0:19] mm_xu_derat_mmucr0_1, -`endif - input [0:17] xu_mm_derat_mmucr0, - input [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we, - output [0:9] mm_xu_derat_mmucr1, - input [0:4] xu_mm_derat_mmucr1, - input [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we, - - output [0:`PID_WIDTH-1] pid0, -`ifdef MM_THREADS2 - output [0:`PID_WIDTH-1] pid1, -`endif - output [0:`MMUCR0_WIDTH-1] mmucr0_0, -`ifdef MM_THREADS2 - output [0:`MMUCR0_WIDTH-1] mmucr0_1, -`endif - output [0:`MMUCR1_WIDTH-1] mmucr1, - output [0:`MMUCR2_WIDTH-1] mmucr2, - output [64-`MMUCR3_WIDTH:63] mmucr3_0, - output [1:3] tstmode4k_0, -`ifdef MM_THREADS2 - output [64-`MMUCR3_WIDTH:63] mmucr3_1, - output [1:3] tstmode4k_1, -`endif - - output mmucfg_lrat, - output mmucfg_twc, - output tlb0cfg_pt, - output tlb0cfg_ind, - output tlb0cfg_gtwe, - output [0:`MESR1_WIDTH+`MESR2_WIDTH-1] mmq_spr_event_mux_ctrls, - - output mas0_0_atsel, - output [0:2] mas0_0_esel, - output mas0_0_hes, - output [0:1] mas0_0_wq, - output mas1_0_v, - output mas1_0_iprot, - output [0:13] mas1_0_tid, - output mas1_0_ind, - output mas1_0_ts, - output [0:3] mas1_0_tsize, - output [0:51] mas2_0_epn, - output [0:4] mas2_0_wimge, - output [32:52] mas3_0_rpnl, - output [0:3] mas3_0_ubits, - output [0:5] mas3_0_usxwr, - output mas5_0_sgs, - output [0:7] mas5_0_slpid, - output [0:13] mas6_0_spid, - output [0:3] mas6_0_isize, - output mas6_0_sind, - output mas6_0_sas, - output [22:31] mas7_0_rpnu, - output mas8_0_tgs, - output mas8_0_vf, - output [0:7] mas8_0_tlpid, -`ifdef MM_THREADS2 - output mas0_1_atsel, - output [0:2] mas0_1_esel, - output mas0_1_hes, - output [0:1] mas0_1_wq, - output mas1_1_v, - output mas1_1_iprot, - output [0:13] mas1_1_tid, - output mas1_1_ind, - output mas1_1_ts, - output [0:3] mas1_1_tsize, - output [0:51] mas2_1_epn, - output [0:4] mas2_1_wimge, - output [32:52] mas3_1_rpnl, - output [0:3] mas3_1_ubits, - output [0:5] mas3_1_usxwr, - output mas5_1_sgs, - output [0:7] mas5_1_slpid, - output [0:13] mas6_1_spid, - output [0:3] mas6_1_isize, - output mas6_1_sind, - output mas6_1_sas, - output [22:31] mas7_1_rpnu, - output mas8_1_tgs, - output mas8_1_vf, - output [0:7] mas8_1_tlpid, -`endif - input [0:2] tlb_mas0_esel, - input tlb_mas1_v, - input tlb_mas1_iprot, - input [0:`PID_WIDTH-1] tlb_mas1_tid, - input [0:`PID_WIDTH-1] tlb_mas1_tid_error, - input tlb_mas1_ind, - input tlb_mas1_ts, - input tlb_mas1_ts_error, - input [0:3] tlb_mas1_tsize, - input [0:`EPN_WIDTH-1] tlb_mas2_epn, - input [0:`EPN_WIDTH-1] tlb_mas2_epn_error, - input [0:4] tlb_mas2_wimge, - input [32:51] tlb_mas3_rpnl, - input [0:3] tlb_mas3_ubits, - input [0:5] tlb_mas3_usxwr, - input [22:31] tlb_mas7_rpnu, - input tlb_mas8_tgs, - input tlb_mas8_vf, - input [0:7] tlb_mas8_tlpid, - - input [0:8] tlb_mmucr1_een, - input tlb_mmucr1_we, - input [0:`THDID_WIDTH-1] tlb_mmucr3_thdid, - input tlb_mmucr3_resvattr, - input [0:1] tlb_mmucr3_wlc, - input [0:`CLASS_WIDTH-1] tlb_mmucr3_class, - input [0:`EXTCLASS_WIDTH-1] tlb_mmucr3_extclass, - input [0:1] tlb_mmucr3_rc, - input tlb_mmucr3_x, - input tlb_mas_tlbre, - input tlb_mas_tlbsx_hit, - input tlb_mas_tlbsx_miss, - input tlb_mas_dtlb_error, - input tlb_mas_itlb_error, - input [0:`MM_THREADS-1] tlb_mas_thdid, - - output mmucsr0_tlb0fi, - input mmq_inval_tlb0fi_done, - - input lrat_mmucr3_x, - input [0:2] lrat_mas0_esel, - input lrat_mas1_v, - input [0:3] lrat_mas1_tsize, - input [0:51] lrat_mas2_epn, - input [32:51] lrat_mas3_rpnl, - input [22:31] lrat_mas7_rpnu, - input [0:`LPID_WIDTH-1] lrat_mas8_tlpid, - input lrat_mas_tlbre, - input lrat_mas_tlbsx_hit, - input lrat_mas_tlbsx_miss, - input [0:`MM_THREADS-1] lrat_mas_thdid, - input [0:2] lrat_tag4_hit_entry, - - input [64-`REAL_ADDR_WIDTH:51] tlb_lper_lpn, - input [60:63] tlb_lper_lps, - input [0:`MM_THREADS-1] tlb_lper_we, - - output [0:`LPID_WIDTH-1] lpidr, - output [0:`LPID_WIDTH-1] ac_an_lpar_id, - - output spr_dbg_match_64b, - output spr_dbg_match_any_mmu, - output spr_dbg_match_any_mas, - output spr_dbg_match_pid, - output spr_dbg_match_lpidr, - output spr_dbg_match_mmucr0, - output spr_dbg_match_mmucr1, - output spr_dbg_match_mmucr2, - output spr_dbg_match_mmucr3, - - output spr_dbg_match_mmucsr0, - output spr_dbg_match_mmucfg, - output spr_dbg_match_tlb0cfg, - output spr_dbg_match_tlb0ps, - output spr_dbg_match_lratcfg, - output spr_dbg_match_lratps, - output spr_dbg_match_eptcfg, - output spr_dbg_match_lper, - output spr_dbg_match_lperu, - - output spr_dbg_match_mas0, - output spr_dbg_match_mas1, - output spr_dbg_match_mas2, - output spr_dbg_match_mas2u, - output spr_dbg_match_mas3, - output spr_dbg_match_mas4, - output spr_dbg_match_mas5, - output spr_dbg_match_mas6, - output spr_dbg_match_mas7, - output spr_dbg_match_mas8, - output spr_dbg_match_mas01_64b, - output spr_dbg_match_mas56_64b, - output spr_dbg_match_mas73_64b, - output spr_dbg_match_mas81_64b, - - output spr_dbg_slowspr_val_int, - output spr_dbg_slowspr_rw_int, - output [0:1] spr_dbg_slowspr_etid_int, - output [0:9] spr_dbg_slowspr_addr_int, - output spr_dbg_slowspr_val_out, - output spr_dbg_slowspr_done_out, - output [64-`SPR_DATA_WIDTH:63] spr_dbg_slowspr_data_out, - - input xu_mm_slowspr_val, - input xu_mm_slowspr_rw, - input [0:1] xu_mm_slowspr_etid, - input [0:9] xu_mm_slowspr_addr, - input [64-`SPR_DATA_WIDTH:63] xu_mm_slowspr_data, - input xu_mm_slowspr_done, - - output mm_iu_slowspr_val, - output mm_iu_slowspr_rw, - output [0:1] mm_iu_slowspr_etid, - output [0:9] mm_iu_slowspr_addr, - output [64-`SPR_DATA_WIDTH:63] mm_iu_slowspr_data, - - output mm_iu_slowspr_done - -); - - parameter BCFG_MMUCR1_VALUE = 201326592; // mmucr1 32-bits boot value, 201326592 -> bits 4:5 csinv="11" - parameter BCFG_MMUCR2_VALUE = `INIT_MMUCR2; //685361; // mmucr2 32-bits boot value, 0xa7531 - parameter BCFG_MMUCR3_VALUE = 15; // mmucr2 15-bits boot value, 0x000f - parameter BCFG_MMUCFG_VALUE = 3; // mmucfg lrat|twc bits boot value - parameter BCFG_TLB0CFG_VALUE = 7; // tlb0cfg pt|ind|gtwe bits boot value - parameter MMQ_SPR_CSWITCH_0TO3 = 8; // chicken switch values: 8=disable mmucr1 read clear, 4=disable mmucr1.tlbwe_binv - - - parameter [0:9] Spr_Addr_PID = 10'b0000110000; - //constant Spr_Addr_LPID : std_ulogic_vector(0 to 9) := 1001111110 ; -- dec 638 - parameter [0:9] Spr_Addr_LPID = 10'b0101010010; - parameter [0:9] Spr_Addr_MMUCR0 = 10'b1111111100; - parameter [0:9] Spr_Addr_MMUCR1 = 10'b1111111101; - parameter [0:9] Spr_Addr_MMUCR2 = 10'b1111111110; - parameter [0:9] Spr_Addr_MMUCR3 = 10'b1111111111; - parameter Spr_RW_Write = 1'b0; - parameter Spr_RW_Read = 1'b1; - parameter [0:9] Spr_Addr_MESR1 = 10'b1110010100; - parameter [0:9] Spr_Addr_MESR2 = 10'b1110010101; - parameter [0:9] Spr_Addr_MAS0 = 10'b1001110000; - parameter [0:9] Spr_Addr_MAS1 = 10'b1001110001; - parameter [0:9] Spr_Addr_MAS2 = 10'b1001110010; - parameter [0:9] Spr_Addr_MAS2U = 10'b1001110111; - parameter [0:9] Spr_Addr_MAS3 = 10'b1001110011; - parameter [0:9] Spr_Addr_MAS4 = 10'b1001110100; - parameter [0:9] Spr_Addr_MAS5 = 10'b0101010011; - parameter [0:9] Spr_Addr_MAS6 = 10'b1001110110; - parameter [0:9] Spr_Addr_MAS7 = 10'b1110110000; - parameter [0:9] Spr_Addr_MAS8 = 10'b0101010101; - parameter [0:9] Spr_Addr_MAS56_64b = 10'b0101011100; - parameter [0:9] Spr_Addr_MAS81_64b = 10'b0101011101; - parameter [0:9] Spr_Addr_MAS73_64b = 10'b0101110100; - parameter [0:9] Spr_Addr_MAS01_64b = 10'b0101110101; - parameter [0:9] Spr_Addr_MMUCFG = 10'b1111110111; - parameter [0:9] Spr_Addr_MMUCSR0 = 10'b1111110100; - parameter [0:9] Spr_Addr_TLB0CFG = 10'b1010110000; - parameter [0:9] Spr_Addr_TLB0PS = 10'b0101011000; - parameter [0:9] Spr_Addr_LRATCFG = 10'b0101010110; - parameter [0:9] Spr_Addr_LRATPS = 10'b0101010111; - parameter [0:9] Spr_Addr_EPTCFG = 10'b0101011110; - parameter [0:9] Spr_Addr_LPER = 10'b0000111000; - parameter [0:9] Spr_Addr_LPERU = 10'b0000111001; - // MMUCFG: 32:35 resv, 36:39 LPIDSIZE=0x8, 40:46 RASIZE=0x2a, 47 LRAT bcfg, 48 TWC bcfg, - // 49:52 resv, 53:57 PIDSIZE=0xd, 58:59 resv, 60:61 NTLBS=0b00, 62:63 MAVN=0b01 - parameter [32:63] Spr_Data_MMUCFG = 32'b00001000010101011000001101000001; - // TLB0CFG: 32:39 ASSOC=0x04, 40:44 resv, 45 PT bcfg, 46 IND bcfg, 47 GTWE bcfg, - // 48 IPROT=1, 49 resv, 50 HES=1, 51 resv, 52:63 NENTRY=0x200 - parameter [32:63] Spr_Data_TLB0CFG = 32'b00000100000000001010001000000000; - // TLB0PS: 32:63 PS31-PS0=0x0010_4444 (PS20, PS14, PS10, PS6, PS2 = 1, others = 0) - parameter [32:63] Spr_Data_TLB0PS = 32'b00000000000100000100010001000100; - // LRATCFG: 32:39 ASSOC=0x00, 40:46 LASIZE=0x2a, 47:49 resv, 50 LPID=1, 51 resv, 52:63 NENTRY=0x008 - parameter [32:63] Spr_Data_LRATCFG = 32'b00000000010101000010000000001000; - // LRATPS: 32:63 PS31-PS0=0x5154_4400 (PS30, PS28, PS24, PS22, PS20, PS18, PS14, PS10 = 1, others = 0) - parameter [32:63] Spr_Data_LRATPS = 32'b01010001010101000100010000000000; - // EPTCFG: 32:43 resv, 44:48 PS1=0x12, 49:53 SPS1=0x06, 54:58 PS0=0x0a, 59:63 SPS0=0x02 - parameter [32:63] Spr_Data_EPTCFG = 32'b00000000000010010001100101000010; - - parameter [0:15] TSTMODE4KCONST1 = 16'b0101101001101001; // 0x5A69 - parameter [0:11] TSTMODE4KCONST2 = 12'b110000111011; // 0xC3B - - // latches scan chain constants - parameter cp_flush_offset = 0; - parameter cp_flush_p1_offset = cp_flush_offset + `MM_THREADS; - parameter spr_ctl_in_offset = cp_flush_p1_offset + `MM_THREADS; - parameter spr_etid_in_offset = spr_ctl_in_offset + `SPR_CTL_WIDTH; - parameter spr_addr_in_offset = spr_etid_in_offset + `SPR_ETID_WIDTH; - parameter spr_data_in_offset = spr_addr_in_offset + `SPR_ADDR_WIDTH; - parameter spr_ctl_int_offset = spr_data_in_offset + `SPR_DATA_WIDTH; - parameter spr_etid_int_offset = spr_ctl_int_offset + `SPR_CTL_WIDTH; - parameter spr_addr_int_offset = spr_etid_int_offset + `SPR_ETID_WIDTH; - parameter spr_data_int_offset = spr_addr_int_offset + `SPR_ADDR_WIDTH; - parameter spr_ctl_out_offset = spr_data_int_offset + `SPR_DATA_WIDTH; - parameter spr_etid_out_offset = spr_ctl_out_offset + `SPR_CTL_WIDTH; - parameter spr_addr_out_offset = spr_etid_out_offset + `SPR_ETID_WIDTH; - parameter spr_data_out_offset = spr_addr_out_offset + `SPR_ADDR_WIDTH; - parameter spr_match_any_mmu_offset = spr_data_out_offset + `SPR_DATA_WIDTH; - parameter spr_match_pid0_offset = spr_match_any_mmu_offset + 1; -`ifdef MM_THREADS2 - parameter spr_match_pid1_offset = spr_match_pid0_offset + 1; - parameter spr_match_mmucr0_0_offset = spr_match_pid1_offset + 1; - parameter spr_match_mmucr0_1_offset = spr_match_mmucr0_0_offset + 1; - parameter spr_match_mmucr1_offset = spr_match_mmucr0_1_offset + 1; -`else - parameter spr_match_mmucr0_0_offset = spr_match_pid0_offset + 1; - parameter spr_match_mmucr1_offset = spr_match_mmucr0_0_offset + 1; -`endif - parameter spr_match_mmucr2_offset = spr_match_mmucr1_offset + 1; - parameter spr_match_mmucr3_0_offset = spr_match_mmucr2_offset + 1; -`ifdef MM_THREADS2 - parameter spr_match_mmucr3_1_offset = spr_match_mmucr3_0_offset + 1; - parameter spr_match_lpidr_offset = spr_match_mmucr3_1_offset + 1; -`else - parameter spr_match_lpidr_offset = spr_match_mmucr3_0_offset + 1; -`endif - parameter spr_match_mesr1_offset = spr_match_lpidr_offset + 1; - parameter spr_match_mesr2_offset = spr_match_mesr1_offset + 1; - parameter pid0_offset = spr_match_mesr2_offset + 1; -`ifdef MM_THREADS2 - parameter pid1_offset = pid0_offset + `PID_WIDTH; - parameter mmucr0_0_offset = pid1_offset + `PID_WIDTH; -`else - parameter mmucr0_0_offset = pid0_offset + `PID_WIDTH; -`endif -`ifdef MM_THREADS2 - parameter mmucr0_1_offset = mmucr0_0_offset + `MMUCR0_WIDTH; - parameter lpidr_offset = mmucr0_1_offset + `MMUCR0_WIDTH; -`else - parameter lpidr_offset = mmucr0_0_offset + `MMUCR0_WIDTH; -`endif - parameter mesr1_offset = lpidr_offset + `LPID_WIDTH; - parameter mesr2_offset = mesr1_offset + `MESR1_WIDTH; - parameter spare_a_offset = mesr2_offset + `MESR2_WIDTH; - parameter spr_mmu_act_offset = spare_a_offset + 32; - parameter spr_val_act_offset = spr_mmu_act_offset + `MM_THREADS + 1; -`ifdef WAIT_UPDATES - parameter cp_mm_except_taken_t0_offset = spr_val_act_offset + 4; - parameter tlb_mas_dtlb_error_pending_offset = cp_mm_except_taken_t0_offset + 6; - parameter tlb_mas_itlb_error_pending_offset = tlb_mas_dtlb_error_pending_offset + `MM_THREADS; - parameter tlb_lper_we_pending_offset = tlb_mas_itlb_error_pending_offset + `MM_THREADS; - parameter tlb_mmucr1_we_pending_offset = tlb_lper_we_pending_offset + `MM_THREADS; - parameter ierat_mmucr1_we_pending_offset = tlb_mmucr1_we_pending_offset + `MM_THREADS; - parameter derat_mmucr1_we_pending_offset = ierat_mmucr1_we_pending_offset + `MM_THREADS; - parameter tlb_mas1_0_ts_error_offset = derat_mmucr1_we_pending_offset + `MM_THREADS; - parameter tlb_mas1_0_tid_error_offset = tlb_mas1_0_ts_error_offset + 1; - parameter tlb_mas2_0_epn_error_offset = tlb_mas1_0_tid_error_offset + `PID_WIDTH; - parameter tlb_lper_0_lpn_offset = tlb_mas2_0_epn_error_offset + `EPN_WIDTH; - parameter tlb_lper_0_lps_offset = tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12; - parameter tlb_mmucr1_0_een_offset = tlb_lper_0_lps_offset + 4; - parameter ierat_mmucr1_0_een_offset = tlb_mmucr1_0_een_offset + 9; - parameter derat_mmucr1_0_een_offset = ierat_mmucr1_0_een_offset + 4; -`ifdef MM_THREADS2 - parameter cp_mm_except_taken_t1_offset = derat_mmucr1_0_een_offset + 5; - parameter tlb_mas1_1_ts_error_offset = cp_mm_except_taken_t1_offset + 6; - parameter tlb_mas1_1_tid_error_offset = tlb_mas1_1_ts_error_offset + 1; - parameter tlb_mas2_1_epn_error_offset = tlb_mas1_1_tid_error_offset + `PID_WIDTH; - parameter tlb_lper_1_lpn_offset = tlb_mas2_1_epn_error_offset + `EPN_WIDTH; - parameter tlb_lper_1_lps_offset = tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12; - parameter tlb_mmucr1_1_een_offset = tlb_lper_1_lps_offset + 4; - parameter ierat_mmucr1_1_een_offset = tlb_mmucr1_1_een_offset + 9; - parameter derat_mmucr1_1_een_offset = ierat_mmucr1_1_een_offset + 4; - parameter cswitch_offset = derat_mmucr1_1_een_offset + 5; -`else - parameter cswitch_offset = derat_mmucr1_0_een_offset + 5; -`endif -`else - parameter cswitch_offset = spr_val_act_offset + 4; -`endif - parameter scan_right_0 = cswitch_offset + 4 - 1; - - - // MAS register constants - parameter spr_match_mmucsr0_offset = 0; - parameter spr_match_mmucfg_offset = spr_match_mmucsr0_offset + 1; - parameter spr_match_tlb0cfg_offset = spr_match_mmucfg_offset + 1; - parameter spr_match_tlb0ps_offset = spr_match_tlb0cfg_offset + 1; - parameter spr_match_lratcfg_offset = spr_match_tlb0ps_offset + 1; - parameter spr_match_lratps_offset = spr_match_lratcfg_offset + 1; - parameter spr_match_eptcfg_offset = spr_match_lratps_offset + 1; - parameter spr_match_lper_0_offset = spr_match_eptcfg_offset + 1; -`ifdef MM_THREADS2 - parameter spr_match_lper_1_offset = spr_match_lper_0_offset + 1; - parameter spr_match_lperu_0_offset = spr_match_lper_1_offset + 1; - parameter spr_match_lperu_1_offset = spr_match_lperu_0_offset + 1; - parameter spr_match_mas0_0_offset = spr_match_lperu_1_offset + 1; -`else - parameter spr_match_lperu_0_offset = spr_match_lper_0_offset + 1; - parameter spr_match_mas0_0_offset = spr_match_lperu_0_offset + 1; -`endif - parameter spr_match_mas1_0_offset = spr_match_mas0_0_offset + 1; - parameter spr_match_mas2_0_offset = spr_match_mas1_0_offset + 1; - parameter spr_match_mas2u_0_offset = spr_match_mas2_0_offset + 1; - parameter spr_match_mas3_0_offset = spr_match_mas2u_0_offset + 1; - parameter spr_match_mas4_0_offset = spr_match_mas3_0_offset + 1; - parameter spr_match_mas5_0_offset = spr_match_mas4_0_offset + 1; - parameter spr_match_mas6_0_offset = spr_match_mas5_0_offset + 1; - parameter spr_match_mas7_0_offset = spr_match_mas6_0_offset + 1; - parameter spr_match_mas8_0_offset = spr_match_mas7_0_offset + 1; - parameter spr_match_mas01_64b_0_offset = spr_match_mas8_0_offset + 1; - parameter spr_match_mas56_64b_0_offset = spr_match_mas01_64b_0_offset + 1; - parameter spr_match_mas73_64b_0_offset = spr_match_mas56_64b_0_offset + 1; - parameter spr_match_mas81_64b_0_offset = spr_match_mas73_64b_0_offset + 1; -`ifdef MM_THREADS2 - parameter spr_match_mas0_1_offset = spr_match_mas81_64b_0_offset + 1; - parameter spr_match_mas1_1_offset = spr_match_mas0_1_offset + 1; - parameter spr_match_mas2_1_offset = spr_match_mas1_1_offset + 1; - parameter spr_match_mas2u_1_offset = spr_match_mas2_1_offset + 1; - parameter spr_match_mas3_1_offset = spr_match_mas2u_1_offset + 1; - parameter spr_match_mas4_1_offset = spr_match_mas3_1_offset + 1; - parameter spr_match_mas5_1_offset = spr_match_mas4_1_offset + 1; - parameter spr_match_mas6_1_offset = spr_match_mas5_1_offset + 1; - parameter spr_match_mas7_1_offset = spr_match_mas6_1_offset + 1; - parameter spr_match_mas8_1_offset = spr_match_mas7_1_offset + 1; - parameter spr_match_mas01_64b_1_offset = spr_match_mas8_1_offset + 1; - parameter spr_match_mas56_64b_1_offset = spr_match_mas01_64b_1_offset + 1; - parameter spr_match_mas73_64b_1_offset = spr_match_mas56_64b_1_offset + 1; - parameter spr_match_mas81_64b_1_offset = spr_match_mas73_64b_1_offset + 1; - parameter spr_match_64b_offset = spr_match_mas81_64b_1_offset + 1; -`else - parameter spr_match_64b_offset = spr_match_mas81_64b_0_offset + 1; -`endif - parameter spr_addr_in_clone_offset = spr_match_64b_offset + 1; - parameter spr_mas_data_out_offset = spr_addr_in_clone_offset + `SPR_ADDR_WIDTH; - parameter spr_match_any_mas_offset = spr_mas_data_out_offset + `SPR_DATA_WIDTH; - parameter mas0_0_atsel_offset = spr_match_any_mas_offset + 1; - parameter mas0_0_esel_offset = mas0_0_atsel_offset + 1; - parameter mas0_0_hes_offset = mas0_0_esel_offset + 3; - parameter mas0_0_wq_offset = mas0_0_hes_offset + 1; - parameter mas1_0_v_offset = mas0_0_wq_offset + 2; - parameter mas1_0_iprot_offset = mas1_0_v_offset + 1; - parameter mas1_0_tid_offset = mas1_0_iprot_offset + 1; - parameter mas1_0_ind_offset = mas1_0_tid_offset + `PID_WIDTH; - parameter mas1_0_ts_offset = mas1_0_ind_offset + 1; - parameter mas1_0_tsize_offset = mas1_0_ts_offset + 1; - parameter mas2_0_epn_offset = mas1_0_tsize_offset + 4; - parameter mas2_0_wimge_offset = mas2_0_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; - parameter mas3_0_rpnl_offset = mas2_0_wimge_offset + 5; - parameter mas3_0_ubits_offset = mas3_0_rpnl_offset + 21; - parameter mas3_0_usxwr_offset = mas3_0_ubits_offset + 4; - parameter mas5_0_sgs_offset = mas3_0_usxwr_offset + 6; - parameter mas5_0_slpid_offset = mas5_0_sgs_offset + 1; - parameter mas6_0_spid_offset = mas5_0_slpid_offset + 8; - parameter mas6_0_isize_offset = mas6_0_spid_offset + 14; - parameter mas6_0_sind_offset = mas6_0_isize_offset + 4; - parameter mas6_0_sas_offset = mas6_0_sind_offset + 1; - parameter mas7_0_rpnu_offset = mas6_0_sas_offset + 1; - parameter mas8_0_tgs_offset = mas7_0_rpnu_offset + 10; - parameter mas8_0_vf_offset = mas8_0_tgs_offset + 1; - parameter mas8_0_tlpid_offset = mas8_0_vf_offset + 1; -`ifdef MM_THREADS2 - parameter mas0_1_atsel_offset = mas8_0_tlpid_offset + `LPID_WIDTH; - parameter mas0_1_esel_offset = mas0_1_atsel_offset + 1; - parameter mas0_1_hes_offset = mas0_1_esel_offset + 3; - parameter mas0_1_wq_offset = mas0_1_hes_offset + 1; - parameter mas1_1_v_offset = mas0_1_wq_offset + 2; - parameter mas1_1_iprot_offset = mas1_1_v_offset + 1; - parameter mas1_1_tid_offset = mas1_1_iprot_offset + 1; - parameter mas1_1_ind_offset = mas1_1_tid_offset + `PID_WIDTH; - parameter mas1_1_ts_offset = mas1_1_ind_offset + 1; - parameter mas1_1_tsize_offset = mas1_1_ts_offset + 1; - parameter mas2_1_epn_offset = mas1_1_tsize_offset + 4; - parameter mas2_1_wimge_offset = mas2_1_epn_offset + `EPN_WIDTH + `SPR_DATA_WIDTH - 64; - parameter mas3_1_rpnl_offset = mas2_1_wimge_offset + 5; - parameter mas3_1_ubits_offset = mas3_1_rpnl_offset + 21; - parameter mas3_1_usxwr_offset = mas3_1_ubits_offset + 4; - parameter mas5_1_sgs_offset = mas3_1_usxwr_offset + 6; - parameter mas5_1_slpid_offset = mas5_1_sgs_offset + 1; - parameter mas6_1_spid_offset = mas5_1_slpid_offset + 8; - parameter mas6_1_isize_offset = mas6_1_spid_offset + 14; - parameter mas6_1_sind_offset = mas6_1_isize_offset + 4; - parameter mas6_1_sas_offset = mas6_1_sind_offset + 1; - parameter mas7_1_rpnu_offset = mas6_1_sas_offset + 1; - parameter mas8_1_tgs_offset = mas7_1_rpnu_offset + 10; - parameter mas8_1_vf_offset = mas8_1_tgs_offset + 1; - parameter mas8_1_tlpid_offset = mas8_1_vf_offset + 1; - parameter mmucsr0_tlb0fi_offset = mas8_1_tlpid_offset + `LPID_WIDTH; -`else - parameter mmucsr0_tlb0fi_offset = mas8_0_tlpid_offset + `LPID_WIDTH; -`endif - parameter lper_0_alpn_offset = mmucsr0_tlb0fi_offset + 1; - parameter lper_0_lps_offset = lper_0_alpn_offset + `REAL_ADDR_WIDTH - 12; -`ifdef MM_THREADS2 - parameter lper_1_alpn_offset = lper_0_lps_offset + 4; - parameter lper_1_lps_offset = lper_1_alpn_offset + `REAL_ADDR_WIDTH - 12; - parameter spare_b_offset = lper_1_lps_offset + 4; -`else - parameter spare_b_offset = lper_0_lps_offset + 4; -`endif - parameter cat_emf_act_offset = spare_b_offset + 64; - parameter scan_right_1 = cat_emf_act_offset + `MM_THREADS - 1; - - // boot config scan bits - parameter mmucfg_offset = 0; - parameter tlb0cfg_offset = mmucfg_offset + 2; - parameter mmucr1_offset = tlb0cfg_offset + 3; - parameter mmucr2_offset = mmucr1_offset + `MMUCR1_WIDTH; -`ifdef MM_THREADS2 - parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; - parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; - parameter mmucr3_1_offset = tstmode4k_0_offset + 4; - parameter tstmode4k_1_offset = mmucr3_1_offset + `MMUCR3_WIDTH; - parameter mas4_0_indd_offset = tstmode4k_1_offset + 4; - parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; - parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; - parameter mas4_1_indd_offset = mas4_0_wimged_offset + 5; - parameter mas4_1_tsized_offset = mas4_1_indd_offset + 1; - parameter mas4_1_wimged_offset = mas4_1_tsized_offset + 4; - parameter bcfg_spare_offset = mas4_1_wimged_offset + 5; - parameter boot_scan_right = bcfg_spare_offset + 16 - 1; -`else - parameter mmucr3_0_offset = mmucr2_offset + `MMUCR2_WIDTH; - parameter tstmode4k_0_offset = mmucr3_0_offset + `MMUCR3_WIDTH; - parameter mas4_0_indd_offset = tstmode4k_0_offset + 4; - parameter mas4_0_tsized_offset = mas4_0_indd_offset + 1; - parameter mas4_0_wimged_offset = mas4_0_tsized_offset + 4; - parameter bcfg_spare_offset = mas4_0_wimged_offset + 5; - parameter boot_scan_right = bcfg_spare_offset + 16 - 1; -`endif - -`ifdef MM_THREADS2 - parameter BUGSP_MM_THREADS = 2; -`else - parameter BUGSP_MM_THREADS = 1; -`endif - - wire spr_match_any_mmu; - wire spr_match_any_mmu_q; - wire spr_match_pid0; - wire spr_match_pid0_q; - wire spr_match_mmucr0_0; - wire spr_match_mmucr0_0_q; - wire spr_match_mmucr3_0; - wire spr_match_mmucr3_0_q; -`ifdef MM_THREADS2 - wire spr_match_pid1; - wire spr_match_pid1_q; - wire spr_match_mmucr0_1; - wire spr_match_mmucr0_1_q; - wire spr_match_mmucr3_1; - wire spr_match_mmucr3_1_q; -`endif - wire spr_match_mmucr1; - wire spr_match_mmucr1_q; - wire spr_match_mmucr2; - wire spr_match_mmucr2_q; - wire spr_match_lpidr; - wire spr_match_lpidr_q; - wire spr_match_mesr1; - wire spr_match_mesr1_q; - wire spr_match_mesr2; - wire spr_match_mesr2_q; - wire spr_match_mmucsr0; - wire spr_match_mmucsr0_q; - wire spr_match_mmucfg; - wire spr_match_mmucfg_q; - wire spr_match_tlb0cfg; - wire spr_match_tlb0cfg_q; - wire spr_match_tlb0ps; - wire spr_match_tlb0ps_q; - wire spr_match_lratcfg; - wire spr_match_lratcfg_q; - wire spr_match_lratps; - wire spr_match_lratps_q; - wire spr_match_eptcfg; - wire spr_match_eptcfg_q; - wire spr_match_lper_0; - wire spr_match_lper_0_q; - wire spr_match_lperu_0; - wire spr_match_lperu_0_q; -`ifdef MM_THREADS2 - wire spr_match_lper_1; - wire spr_match_lper_1_q; - wire spr_match_lperu_1; - wire spr_match_lperu_1_q; -`endif - wire spr_match_mas0_0; - wire spr_match_mas0_0_q; - wire spr_match_mas1_0; - wire spr_match_mas1_0_q; - wire spr_match_mas2_0; - wire spr_match_mas2_0_q; - wire spr_match_mas2u_0; - wire spr_match_mas2u_0_q; - wire spr_match_mas3_0; - wire spr_match_mas3_0_q; - wire spr_match_mas4_0; - wire spr_match_mas4_0_q; - wire spr_match_mas5_0; - wire spr_match_mas5_0_q; - wire spr_match_mas6_0; - wire spr_match_mas6_0_q; - wire spr_match_mas7_0; - wire spr_match_mas7_0_q; - wire spr_match_mas8_0; - wire spr_match_mas8_0_q; - wire spr_match_mas01_64b_0; - wire spr_match_mas01_64b_0_q; - wire spr_match_mas56_64b_0; - wire spr_match_mas56_64b_0_q; - wire spr_match_mas73_64b_0; - wire spr_match_mas73_64b_0_q; - wire spr_match_mas81_64b_0; - wire spr_match_mas81_64b_0_q; -`ifdef MM_THREADS2 - wire spr_match_mas0_1; - wire spr_match_mas0_1_q; - wire spr_match_mas1_1; - wire spr_match_mas1_1_q; - wire spr_match_mas2_1; - wire spr_match_mas2_1_q; - wire spr_match_mas2u_1; - wire spr_match_mas2u_1_q; - wire spr_match_mas3_1; - wire spr_match_mas3_1_q; - wire spr_match_mas4_1; - wire spr_match_mas4_1_q; - wire spr_match_mas5_1; - wire spr_match_mas5_1_q; - wire spr_match_mas6_1; - wire spr_match_mas6_1_q; - wire spr_match_mas7_1; - wire spr_match_mas7_1_q; - wire spr_match_mas8_1; - wire spr_match_mas8_1_q; - wire spr_match_mas01_64b_1; - wire spr_match_mas01_64b_1_q; - wire spr_match_mas56_64b_1; - wire spr_match_mas56_64b_1_q; - wire spr_match_mas73_64b_1; - wire spr_match_mas73_64b_1_q; - wire spr_match_mas81_64b_1; - wire spr_match_mas81_64b_1_q; -`endif - wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out; - wire [64-`SPR_DATA_WIDTH:63] spr_mas_data_out_q; - wire spr_match_any_mas; - wire spr_match_any_mas_q; - wire spr_match_mas2_64b; - wire spr_match_mas01_64b; - wire spr_match_mas56_64b; - wire spr_match_mas73_64b; - wire spr_match_mas81_64b; - wire spr_match_64b; - wire spr_match_64b_q; - // added input latches for timing with adding numerous mas regs - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_d; - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_in_q; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_d; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_in_q; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_d; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_q; - wire [64-`SPR_DATA_WIDTH:63] spr_data_in_d; - wire [64-`SPR_DATA_WIDTH:63] spr_data_in_q; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_d; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_in_clone_q; - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_d; - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_int_q; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_d; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_int_q; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_d; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_int_q; - wire [64-`SPR_DATA_WIDTH:63] spr_data_int_d; - wire [64-`SPR_DATA_WIDTH:63] spr_data_int_q; - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_d; - wire [0:`SPR_CTL_WIDTH-1] spr_ctl_out_q; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_d; - wire [0:`SPR_ETID_WIDTH-1] spr_etid_out_q; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_d; - wire [0:`SPR_ADDR_WIDTH-1] spr_addr_out_q; - wire [64-`SPR_DATA_WIDTH:63] spr_data_out_d; - wire [64-`SPR_DATA_WIDTH:63] spr_data_out_q; - wire [0:3] spr_etid_onehot; - wire [0:3] spr_etid_in_onehot; - wire [0:3] spr_etid_int_onehot; - wire [0:3] spr_etid_flushed; - wire [0:3] spr_etid_in_flushed; - wire [0:3] spr_etid_int_flushed; - wire spr_val_flushed; - wire spr_val_in_flushed; - wire spr_val_int_flushed; - wire [0:`PID_WIDTH-1] pid0_d; - wire [0:`PID_WIDTH-1] pid0_q; - wire [0:`MMUCR0_WIDTH-1] mmucr0_0_d; - wire [0:`MMUCR0_WIDTH-1] mmucr0_0_q; - wire [64-`MMUCR3_WIDTH:63] mmucr3_0_d; - wire [64-`MMUCR3_WIDTH:63] mmucr3_0_q; - wire [0:3] tstmode4k_0_d, tstmode4k_0_q; -`ifdef MM_THREADS2 - wire [0:`PID_WIDTH-1] pid1_d; - wire [0:`PID_WIDTH-1] pid1_q; - wire [0:`MMUCR0_WIDTH-1] mmucr0_1_d; - wire [0:`MMUCR0_WIDTH-1] mmucr0_1_q; - wire [64-`MMUCR3_WIDTH:63] mmucr3_1_d; - wire [64-`MMUCR3_WIDTH:63] mmucr3_1_q; - wire [0:3] tstmode4k_1_d, tstmode4k_1_q; -`endif - wire [0:`MMUCR1_WIDTH-1] mmucr1_d; - wire [0:`MMUCR1_WIDTH-1] mmucr1_q; - wire [0:`MMUCR2_WIDTH-1] mmucr2_d; - wire [0:`MMUCR2_WIDTH-1] mmucr2_q; - wire [0:`LPID_WIDTH-1] lpidr_d; - wire [0:`LPID_WIDTH-1] lpidr_q; - wire [32:32+`MESR1_WIDTH-1] mesr1_d; - wire [32:32+`MESR1_WIDTH-1] mesr1_q; - wire [32:32+`MESR2_WIDTH-1] mesr2_d; - wire [32:32+`MESR2_WIDTH-1] mesr2_q; - wire mas0_0_atsel_d; - wire mas0_0_atsel_q; - wire [0:2] mas0_0_esel_d; - wire [0:2] mas0_0_esel_q; - wire mas0_0_hes_d; - wire mas0_0_hes_q; - wire [0:1] mas0_0_wq_d; - wire [0:1] mas0_0_wq_q; - wire mas1_0_v_d; - wire mas1_0_v_q; - wire mas1_0_iprot_d; - wire mas1_0_iprot_q; - wire [0:`PID_WIDTH-1] mas1_0_tid_d; - wire [0:`PID_WIDTH-1] mas1_0_tid_q; - wire mas1_0_ind_d; - wire mas1_0_ind_q; - wire mas1_0_ts_d; - wire mas1_0_ts_q; - wire [0:3] mas1_0_tsize_d; - wire [0:3] mas1_0_tsize_q; - wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_d; - wire [64-`SPR_DATA_WIDTH:51] mas2_0_epn_q; - wire [0:4] mas2_0_wimge_d; - wire [0:4] mas2_0_wimge_q; - wire [32:52] mas3_0_rpnl_d; - wire [32:52] mas3_0_rpnl_q; - wire [0:3] mas3_0_ubits_d; - wire [0:3] mas3_0_ubits_q; - wire [0:5] mas3_0_usxwr_d; - wire [0:5] mas3_0_usxwr_q; - wire mas4_0_indd_d; - wire mas4_0_indd_q; - wire [0:3] mas4_0_tsized_d; - wire [0:3] mas4_0_tsized_q; - wire [0:4] mas4_0_wimged_d; - wire [0:4] mas4_0_wimged_q; - wire mas5_0_sgs_d; - wire mas5_0_sgs_q; - wire [0:7] mas5_0_slpid_d; - wire [0:7] mas5_0_slpid_q; - wire [0:13] mas6_0_spid_d; - wire [0:13] mas6_0_spid_q; - wire [0:3] mas6_0_isize_d; - wire [0:3] mas6_0_isize_q; - wire mas6_0_sind_d; - wire mas6_0_sind_q; - wire mas6_0_sas_d; - wire mas6_0_sas_q; - wire [22:31] mas7_0_rpnu_d; - wire [22:31] mas7_0_rpnu_q; - wire mas8_0_tgs_d; - wire mas8_0_tgs_q; - wire mas8_0_vf_d; - wire mas8_0_vf_q; - wire [0:7] mas8_0_tlpid_d; - wire [0:7] mas8_0_tlpid_q; -`ifdef MM_THREADS2 - wire mas0_1_atsel_d; - wire mas0_1_atsel_q; - wire [0:2] mas0_1_esel_d; - wire [0:2] mas0_1_esel_q; - wire mas0_1_hes_d; - wire mas0_1_hes_q; - wire [0:1] mas0_1_wq_d; - wire [0:1] mas0_1_wq_q; - wire mas1_1_v_d; - wire mas1_1_v_q; - wire mas1_1_iprot_d; - wire mas1_1_iprot_q; - wire [0:`PID_WIDTH-1] mas1_1_tid_d; - wire [0:`PID_WIDTH-1] mas1_1_tid_q; - wire mas1_1_ind_d; - wire mas1_1_ind_q; - wire mas1_1_ts_d; - wire mas1_1_ts_q; - wire [0:3] mas1_1_tsize_d; - wire [0:3] mas1_1_tsize_q; - wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_d; - wire [64-`SPR_DATA_WIDTH:51] mas2_1_epn_q; - wire [0:4] mas2_1_wimge_d; - wire [0:4] mas2_1_wimge_q; - wire [32:52] mas3_1_rpnl_d; - wire [32:52] mas3_1_rpnl_q; - wire [0:3] mas3_1_ubits_d; - wire [0:3] mas3_1_ubits_q; - wire [0:5] mas3_1_usxwr_d; - wire [0:5] mas3_1_usxwr_q; - wire mas4_1_indd_d; - wire mas4_1_indd_q; - wire [0:3] mas4_1_tsized_d; - wire [0:3] mas4_1_tsized_q; - wire [0:4] mas4_1_wimged_d; - wire [0:4] mas4_1_wimged_q; - wire mas5_1_sgs_d; - wire mas5_1_sgs_q; - wire [0:7] mas5_1_slpid_d; - wire [0:7] mas5_1_slpid_q; - wire [0:13] mas6_1_spid_d; - wire [0:13] mas6_1_spid_q; - wire [0:3] mas6_1_isize_d; - wire [0:3] mas6_1_isize_q; - wire mas6_1_sind_d; - wire mas6_1_sind_q; - wire mas6_1_sas_d; - wire mas6_1_sas_q; - wire [22:31] mas7_1_rpnu_d; - wire [22:31] mas7_1_rpnu_q; - wire mas8_1_tgs_d; - wire mas8_1_tgs_q; - wire mas8_1_vf_d; - wire mas8_1_vf_q; - wire [0:7] mas8_1_tlpid_d; - wire [0:7] mas8_1_tlpid_q; -`endif - - wire mmucsr0_tlb0fi_d; - wire mmucsr0_tlb0fi_q; - wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_d; - wire [64-`REAL_ADDR_WIDTH:51] lper_0_alpn_q; - wire [60:63] lper_0_lps_d; - wire [60:63] lper_0_lps_q; -`ifdef MM_THREADS2 - wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_d; - wire [64-`REAL_ADDR_WIDTH:51] lper_1_alpn_q; - wire [60:63] lper_1_lps_d; - wire [60:63] lper_1_lps_q; -`endif - // timing nsl's - wire [0:17] iu_mm_ierat_mmucr0_q; - wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr0_we_q; - wire [0:17] xu_mm_derat_mmucr0_q; - wire [0:`MM_THREADS-1] xu_mm_derat_mmucr0_we_q; - wire [0:3] iu_mm_ierat_mmucr1_q; - wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_d, iu_mm_ierat_mmucr1_we_q; - wire [0:4] xu_mm_derat_mmucr1_q; - wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_d, xu_mm_derat_mmucr1_we_q; - - wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_upd; - wire [0:`MM_THREADS-1] tlb_mas_itlb_error_upd; - wire [0:`MM_THREADS-1] tlb_lper_we_upd; - wire [0:`MM_THREADS-1] tlb_mmucr1_we_upd; - wire [0:`MM_THREADS-1] iu_mm_ierat_mmucr1_we_upd; - wire [0:`MM_THREADS-1] xu_mm_derat_mmucr1_we_upd; - wire tlb_mas1_0_ts_error_upd; - wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_upd; - wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_upd; - wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_upd; - wire [60:63] tlb_lper_0_lps_upd; - wire [0:8] tlb_mmucr1_0_een_upd; - wire [0:3] ierat_mmucr1_0_een_upd; - wire [0:4] derat_mmucr1_0_een_upd; -`ifdef MM_THREADS2 - wire tlb_mas1_1_ts_error_upd; - wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_upd; - wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_upd; - wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_upd; - wire [60:63] tlb_lper_1_lps_upd; - wire [0:8] tlb_mmucr1_1_een_upd; - wire [0:3] ierat_mmucr1_1_een_upd; - wire [0:4] derat_mmucr1_1_een_upd; -`endif - -`ifdef WAIT_UPDATES - wire [0:5] cp_mm_except_taken_t0_d, cp_mm_except_taken_t0_q; - wire [0:`MM_THREADS-1] tlb_mas_dtlb_error_pending_d, tlb_mas_dtlb_error_pending_q; - wire [0:`MM_THREADS-1] tlb_mas_itlb_error_pending_d, tlb_mas_itlb_error_pending_q; - wire [0:`MM_THREADS-1] tlb_lper_we_pending_d, tlb_lper_we_pending_q; - wire [0:`MM_THREADS-1] tlb_mmucr1_we_pending_d, tlb_mmucr1_we_pending_q; - wire [0:`MM_THREADS-1] ierat_mmucr1_we_pending_d, ierat_mmucr1_we_pending_q; - wire [0:`MM_THREADS-1] derat_mmucr1_we_pending_d, derat_mmucr1_we_pending_q; - - wire tlb_mas1_0_ts_error_d, tlb_mas1_0_ts_error_q; - wire [0:`PID_WIDTH-1] tlb_mas1_0_tid_error_d, tlb_mas1_0_tid_error_q; - wire [0:`EPN_WIDTH-1] tlb_mas2_0_epn_error_d, tlb_mas2_0_epn_error_q; - wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_0_lpn_d, tlb_lper_0_lpn_q; - wire [60:63] tlb_lper_0_lps_d, tlb_lper_0_lps_q; - wire [0:8] tlb_mmucr1_0_een_d, tlb_mmucr1_0_een_q; - wire [0:3] ierat_mmucr1_0_een_d, ierat_mmucr1_0_een_q; - wire [0:4] derat_mmucr1_0_een_d, derat_mmucr1_0_een_q; -`ifdef MM_THREADS2 - wire [0:5] cp_mm_except_taken_t1_d, cp_mm_except_taken_t1_q; - wire tlb_mas1_1_ts_error_d, tlb_mas1_1_ts_error_q; - wire [0:`PID_WIDTH-1] tlb_mas1_1_tid_error_d, tlb_mas1_1_tid_error_q; - wire [0:`EPN_WIDTH-1] tlb_mas2_1_epn_error_d, tlb_mas2_1_epn_error_q; - wire [64-`REAL_ADDR_WIDTH:51] tlb_lper_1_lpn_d, tlb_lper_1_lpn_q; - wire [60:63] tlb_lper_1_lps_d, tlb_lper_1_lps_q; - wire [0:8] tlb_mmucr1_1_een_d, tlb_mmucr1_1_een_q; - wire [0:3] ierat_mmucr1_1_een_d, ierat_mmucr1_1_een_q; - wire [0:4] derat_mmucr1_1_een_d, derat_mmucr1_1_een_q; -`endif -`endif - - wire [0:31] spare_a_q; - wire [0:63] spare_b_q; - - (* analysis_not_referenced="true" *) - wire [0:13] unused_dc; - (* analysis_not_referenced="true" *) - wire [`THREADS:3] unused_dc_threads; - wire [0:45+(4*`MM_THREADS)-1] tri_regk_unused_scan; - - // Pervasive - wire pc_sg_1; - wire pc_sg_0; - wire pc_fce_1; - wire pc_fce_0; - wire pc_func_sl_thold_1; - wire pc_func_sl_thold_0; - wire pc_func_sl_thold_0_b; - wire pc_func_slp_sl_thold_1; - wire pc_func_slp_sl_thold_0; - wire pc_func_slp_sl_thold_0_b; - wire pc_func_sl_force; - wire pc_func_slp_sl_force; - wire pc_cfg_sl_thold_1; - wire pc_cfg_sl_thold_0; - wire pc_cfg_slp_sl_force; - wire pc_cfg_slp_sl_thold_1; - wire pc_cfg_slp_sl_thold_0; - wire pc_cfg_slp_sl_thold_0_b; - wire pc_func_slp_nsl_thold_1; - wire pc_func_slp_nsl_thold_0; - wire pc_func_slp_nsl_thold_0_b; - wire pc_func_slp_nsl_force; - - //signal reset_alias : std_ulogic; - wire [0:scan_right_0] siv_0; - wire [0:scan_right_0] sov_0; - wire [0:scan_right_1] siv_1; - wire [0:scan_right_1] sov_1; - wire [0:boot_scan_right] bsiv; - wire [0:boot_scan_right] bsov; - wire [47:48] mmucfg_q; - wire [45:47] tlb0cfg_q; - wire [0:15] bcfg_spare_q; - - wire pc_cfg_sl_thold_0_b; - wire pc_cfg_sl_force; - wire lcb_dclk; - wire [0:`NCLK_WIDTH-1] lcb_lclk; - wire [47:48] mmucfg_q_b; - wire [45:47] tlb0cfg_q_b; - wire [0:15] bcfg_spare_q_b; - - wire [0:`MM_THREADS-1] cat_emf_act_d; - wire [0:`MM_THREADS-1] cat_emf_act_q; - wire [0:`MM_THREADS] spr_mmu_act_d; - wire [0:`MM_THREADS] spr_mmu_act_q; - wire [0:3] spr_val_act_d; - wire [0:3] spr_val_act_q; - wire spr_val_act; - wire spr_match_act; - wire spr_match_mas_act; - wire spr_mas_data_out_act; - wire [0:`MM_THREADS-1] mas_update_pending_act; - - wire [0:3] cswitch_q; - wire [0:`MM_THREADS-1] cp_flush_d, cp_flush_q; - wire [0:`MM_THREADS-1] cp_flush_p1_d, cp_flush_p1_q; - - // array of 2 bit bin values - wire [0:1] bin_2bit [0:3]; - wire tidn; - wire tiup; - - //## figtree_source: mmq_spr.fig; - //!! Bugspray Include: mmq_spr; - - assign tidn = 1'b0; - assign tiup = 1'b1; - assign bin_2bit[0] = 2'b00; - assign bin_2bit[1] = 2'b01; - assign bin_2bit[2] = 2'b10; - assign bin_2bit[3] = 2'b11; - - genvar i; - generate - for (i=0; i<`MM_THREADS; i=i+1) - begin : genacts - assign cat_emf_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[6] | (tlb_delayed_act[29+i] & xu_mm_ccr2_notlb_b); - assign spr_mmu_act_d[i] = (spr_match_any_mmu & (spr_etid_in_q == bin_2bit[i])) | mmucr2_act_override[5]; - end - endgenerate - - assign spr_mmu_act_d[`MM_THREADS] = spr_match_any_mmu | mmucr2_act_override[5]; - assign spr_val_act_d[0] = xu_mm_slowspr_val; - assign spr_val_act_d[1] = spr_val_act_q[0]; - assign spr_val_act_d[2] = spr_val_act_q[1]; - assign spr_val_act_d[3] = spr_val_act_q[2]; - assign spr_val_act = spr_val_act_q[0] | spr_val_act_q[1] | spr_val_act_q[2] | spr_val_act_q[3] | mmucr2_act_override[5]; - assign spr_match_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[5]; - assign spr_match_mas_act = spr_val_act_q[0] | spr_val_act_q[1] | mmucr2_act_override[6]; - assign spr_mas_data_out_act = spr_val_act_q[0] | mmucr2_act_override[6]; -`ifdef WAIT_UPDATES - assign mas_update_pending_act = cat_emf_act_q | tlb_mas_dtlb_error_pending_q | tlb_mas_itlb_error_pending_q | tlb_lper_we_pending_q | - tlb_mmucr1_we_pending_q | ierat_mmucr1_we_pending_q | derat_mmucr1_we_pending_q; -`else - assign mas_update_pending_act = cat_emf_act_q; -`endif - - - //--------------------------------------------------------------------- - // slow spr logic - //--------------------------------------------------------------------- - // input latches for spr access - assign spr_etid_onehot[0] = (xu_mm_slowspr_etid == 2'b00); - assign spr_etid_onehot[1] = (xu_mm_slowspr_etid == 2'b01); - assign spr_etid_onehot[2] = (xu_mm_slowspr_etid == 2'b10); - assign spr_etid_onehot[3] = (xu_mm_slowspr_etid == 2'b11); - assign spr_etid_in_onehot[0] = (spr_etid_in_q == 2'b00); - assign spr_etid_in_onehot[1] = (spr_etid_in_q == 2'b01); - assign spr_etid_in_onehot[2] = (spr_etid_in_q == 2'b10); - assign spr_etid_in_onehot[3] = (spr_etid_in_q == 2'b11); - assign spr_etid_int_onehot[0] = (spr_etid_int_q == 2'b00); - assign spr_etid_int_onehot[1] = (spr_etid_int_q == 2'b01); - assign spr_etid_int_onehot[2] = (spr_etid_int_q == 2'b10); - assign spr_etid_int_onehot[3] = (spr_etid_int_q == 2'b11); - - generate - begin : etid_generate - genvar tid; - for (tid = 0; tid <= 3; tid = tid + 1) - begin : mmqsprflush - if (tid < `THREADS) - begin : mmqsprtidExist - assign spr_etid_flushed[tid] = cp_flush_q[tid] & spr_etid_onehot[tid]; - assign spr_etid_in_flushed[tid] = cp_flush_q[tid] & spr_etid_in_onehot[tid]; - assign spr_etid_int_flushed[tid] = cp_flush_q[tid] & spr_etid_int_onehot[tid]; - end - if (tid >= `THREADS) - begin : mmqsprtidNExist - assign spr_etid_flushed[tid] = 1'b0; - assign spr_etid_in_flushed[tid] = 1'b0; - assign spr_etid_int_flushed[tid] = 1'b0; - assign unused_dc_threads[tid] = spr_etid_onehot[tid] | spr_etid_in_onehot[tid] | spr_etid_int_onehot[tid]; - end - end - end - endgenerate - -`ifdef WAIT_UPDATES - generate - begin : mmq_spr_tid_generate - genvar tid; - for (tid = 0; tid <= `MM_THREADS-1; tid = tid + 1) - begin : mmThreads - if (tid < `THREADS) - begin : tidExist - assign cp_flush_d[tid] = cp_flush[tid]; - end - if (tid >= `THREADS) - begin : tidNExist - assign cp_flush_d[tid] = tidn; - end - end - end - endgenerate -`endif - -assign iu_mm_ierat_mmucr1_we_d = iu_mm_ierat_mmucr1_we; -assign xu_mm_derat_mmucr1_we_d = xu_mm_derat_mmucr1_we; - - // delay because cp_mm_except_taken bus lags cp_flush from completion by 1 cyc - assign cp_flush_p1_d = cp_flush_q; - assign cp_flush_p1 = cp_flush_p1_q; - - //masthdNExist : if `THDID_WIDTH > (`MM_THREADS) generate begin - // masthdunused : for tid in (`MM_THREADS) to (`THDID_WIDTH-1) generate begin - // unused_dc_thdid(tid) <= lrat_mas_thdid(tid) or tlb_lper_we_upd(tid) or tlb_delayed_act(tid+29); - // end generate masthdunused; - //end generate masthdNExist; - assign spr_val_flushed = |(spr_etid_flushed); - assign spr_val_in_flushed = |(spr_etid_in_flushed); - assign spr_val_int_flushed = |(spr_etid_int_flushed); - assign spr_ctl_in_d[0] = xu_mm_slowspr_val & (~(spr_val_flushed)); - assign spr_ctl_in_d[1] = xu_mm_slowspr_rw; - assign spr_ctl_in_d[2] = xu_mm_slowspr_done; - assign spr_etid_in_d = xu_mm_slowspr_etid; - assign spr_addr_in_d = xu_mm_slowspr_addr; - assign spr_addr_in_clone_d = xu_mm_slowspr_addr; - assign spr_data_in_d = xu_mm_slowspr_data; - // internal select latches for spr access - assign spr_ctl_int_d[0] = spr_ctl_in_q[0] & (~(spr_val_in_flushed)); - assign spr_ctl_int_d[1:2] = spr_ctl_in_q[1:2]; - assign spr_etid_int_d = spr_etid_in_q; - assign spr_addr_int_d = spr_addr_in_q; - assign spr_data_int_d = spr_data_in_q; - - assign spr_match_any_mmu = ( spr_ctl_in_q[0] & - ((spr_addr_in_q == Spr_Addr_PID) | - (spr_addr_in_q == Spr_Addr_MMUCR0) | (spr_addr_in_q == Spr_Addr_MMUCR1) | (spr_addr_in_q == Spr_Addr_MMUCR2) | (spr_addr_in_q == Spr_Addr_MMUCR3) | - (spr_addr_in_q == Spr_Addr_LPID) | - (spr_addr_in_q == Spr_Addr_MESR1) | (spr_addr_in_q == Spr_Addr_MESR2) | - (spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | - (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | - (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | - (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | - (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | - (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | - (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b) | - (spr_addr_in_clone_q == Spr_Addr_MMUCFG) | (spr_addr_in_clone_q == Spr_Addr_MMUCSR0) | - (spr_addr_in_clone_q == Spr_Addr_TLB0CFG) | (spr_addr_in_clone_q == Spr_Addr_TLB0PS) | - (spr_addr_in_clone_q == Spr_Addr_LRATCFG) | (spr_addr_in_clone_q == Spr_Addr_LRATPS) | - (spr_addr_in_clone_q == Spr_Addr_EPTCFG) | (spr_addr_in_clone_q == Spr_Addr_LPER) | - (spr_addr_in_clone_q == Spr_Addr_LPERU)) ); - - assign spr_match_pid0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_PID)); - assign spr_match_mmucr0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR0)); - assign spr_match_mmucr3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_q == Spr_Addr_MMUCR3)); -`ifdef MM_THREADS2 - assign spr_match_pid1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_PID)); - assign spr_match_mmucr0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR0)); - assign spr_match_mmucr3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_q == Spr_Addr_MMUCR3)); -`endif - assign spr_match_mmucr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR1)); - assign spr_match_mmucr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MMUCR2)); - assign spr_match_lpidr = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_LPID)); - assign spr_match_mesr1 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR1)); - assign spr_match_mesr2 = (spr_ctl_in_q[0] & (spr_addr_in_q == Spr_Addr_MESR2)); - assign spr_match_mmucsr0 = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCSR0)); - assign spr_match_mmucfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MMUCFG)); - assign spr_match_tlb0cfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0CFG)); - assign spr_match_tlb0ps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_TLB0PS)); - assign spr_match_lratcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATCFG)); - assign spr_match_lratps = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_LRATPS)); - assign spr_match_eptcfg = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_EPTCFG)); - assign spr_match_lper_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPER)); - assign spr_match_lperu_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); -`ifdef MM_THREADS2 - assign spr_match_lper_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPER)); - assign spr_match_lperu_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_LPERU)); -`endif - assign spr_match_any_mas = (spr_ctl_in_q[0] & ((spr_addr_in_clone_q == Spr_Addr_MAS0) | (spr_addr_in_clone_q == Spr_Addr_MAS1) | (spr_addr_in_clone_q == Spr_Addr_MAS2) | (spr_addr_in_clone_q == Spr_Addr_MAS2U) | (spr_addr_in_clone_q == Spr_Addr_MAS3) | (spr_addr_in_clone_q == Spr_Addr_MAS4) | (spr_addr_in_clone_q == Spr_Addr_MAS5) | (spr_addr_in_clone_q == Spr_Addr_MAS6) | (spr_addr_in_clone_q == Spr_Addr_MAS7) | (spr_addr_in_clone_q == Spr_Addr_MAS8) | (spr_addr_in_clone_q == Spr_Addr_MAS01_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS56_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS73_64b) | (spr_addr_in_clone_q == Spr_Addr_MAS81_64b))); - assign spr_match_mas0_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); - assign spr_match_mas1_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); - assign spr_match_mas2_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); - assign spr_match_mas2u_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); - assign spr_match_mas3_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); - assign spr_match_mas4_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); - assign spr_match_mas5_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); - assign spr_match_mas6_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); - assign spr_match_mas7_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); - assign spr_match_mas8_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); - assign spr_match_mas01_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); - assign spr_match_mas56_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); - assign spr_match_mas73_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); - assign spr_match_mas81_64b_0 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b00) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); -`ifdef MM_THREADS2 - assign spr_match_mas0_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS0)); - assign spr_match_mas1_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS1)); - assign spr_match_mas2_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2)); - assign spr_match_mas2u_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS2U)); - assign spr_match_mas3_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS3)); - assign spr_match_mas4_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS4)); - assign spr_match_mas5_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS5)); - assign spr_match_mas6_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS6)); - assign spr_match_mas7_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS7)); - assign spr_match_mas8_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS8)); - assign spr_match_mas01_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); - assign spr_match_mas56_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); - assign spr_match_mas73_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); - assign spr_match_mas81_64b_1 = (spr_ctl_in_q[0] & (spr_etid_in_q == 2'b01) & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); -`endif - assign spr_match_mas2_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS2)); - assign spr_match_mas01_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS01_64b)); - assign spr_match_mas56_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS56_64b)); - assign spr_match_mas73_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS73_64b)); - assign spr_match_mas81_64b = (spr_ctl_in_q[0] & (spr_addr_in_clone_q == Spr_Addr_MAS81_64b)); - assign spr_match_64b = spr_match_mas2_64b | spr_match_mas01_64b | spr_match_mas56_64b | spr_match_mas73_64b | spr_match_mas81_64b; - - - assign pid0_d = ((spr_match_pid0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : - pid0_q; -`ifdef MM_THREADS2 - assign pid1_d = ((spr_match_pid1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `PID_WIDTH:63] : - pid1_q; -`endif - // mmucr0: 0-ExtClass, 1-TID_NZ, 2:3-GS/TS, 4:5-TLBSel, 6:19-TID - assign mmucr0_0_d = ((spr_match_mmucr0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : - (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : - (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_0_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : - (xu_mm_derat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : - (xu_mm_derat_mmucr0_we_q[0] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : - (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_0_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : - (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_0_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : - (iu_mm_ierat_mmucr0_we_q[0] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : - (iu_mm_ierat_mmucr0_we_q[0] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_0_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : - mmucr0_0_q; -`ifdef MM_THREADS2 - assign mmucr0_1_d = ((spr_match_mmucr0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? {spr_data_int_q[32], |(spr_data_int_q[50:63]), spr_data_int_q[34:37], spr_data_int_q[50:63]} : - (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b01) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], xu_mm_derat_mmucr0_q[6:17]} : - (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b10) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:5], mmucr0_1_q[8:11], xu_mm_derat_mmucr0_q[10:17]} : - (xu_mm_derat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[14:15] == 2'b11) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, xu_mm_derat_mmucr0_q[4:17]} : - (xu_mm_derat_mmucr0_we_q[1] == 1'b1) ? {xu_mm_derat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:11], xu_mm_derat_mmucr0_q[10:17]} : - (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b01) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, mmucr0_1_q[6:7], iu_mm_ierat_mmucr0_q[6:17]} : - (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b10) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:5], mmucr0_1_q[8:11], iu_mm_ierat_mmucr0_q[10:17]} : - (iu_mm_ierat_mmucr0_we_q[1] == 1'b1 & mmucr1_q[12:13] == 2'b11) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b11, iu_mm_ierat_mmucr0_q[4:17]} : - (iu_mm_ierat_mmucr0_we_q[1] == 1'b1) ? {iu_mm_ierat_mmucr0_q[0:3], 2'b10, mmucr0_1_q[6:11], iu_mm_ierat_mmucr0_q[10:17]} : - mmucr0_1_q; -`endif - - // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, - // 4-Disable any context sync inst from invalidating extclass=0 erat entries, - // 5-Disable isync inst from invalidating extclass=0 erat entries, - // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, - // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, - // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN - // 2) mmucr1: merge EEN bits into single field, seperate I/D/T ERRDET bits - // 3) mmucr1: add ICTID, ITTID, DCTID, DTTID, TLBI_REJ, and TLBI_MSB bits - assign mmucr1_d[0:16] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:48] : - mmucr1_q[0:16]; - assign mmucr1_d[17] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? (spr_data_int_q[49] & (~cswitch_q[1])) : - mmucr1_q[17]; - assign mmucr1_d[18:19] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : - mmucr1_q[18:19]; - // added cswitch0 to prevent side effect of clearing on read - assign mmucr1_d[20] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : - ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[52] : - ((|(iu_mm_ierat_mmucr1_we_upd) == 1'b1 & |(xu_mm_derat_mmucr1_we_upd) == 1'b0 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : - mmucr1_q[20]; - assign mmucr1_d[21] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : - ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[53] : - ((|(xu_mm_derat_mmucr1_we_upd) == 1'b1 & |(tlb_mmucr1_we_upd) == 1'b0 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : - mmucr1_q[21]; - assign mmucr1_d[22] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? 1'b0 : - ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[54] : - ((|(tlb_mmucr1_we_upd) == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? 1'b1 : - mmucr1_q[22]; - assign mmucr1_d[23:31] = ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Read & cswitch_q[0] == 1'b0)) ? {9{1'b0}} : - ((spr_match_mmucr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & cswitch_q[0] == 1'b1)) ? spr_data_int_q[55:63] : - ((tlb_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_0_een_upd : -`ifdef MM_THREADS2 - ((tlb_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? tlb_mmucr1_1_een_upd : -`endif - ((xu_mm_derat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_0_een_upd} : -`ifdef MM_THREADS2 - ((xu_mm_derat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {4'b0000, derat_mmucr1_1_een_upd} : -`endif - ((iu_mm_ierat_mmucr1_we_upd[0] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_0_een_upd} : -`ifdef MM_THREADS2 - ((iu_mm_ierat_mmucr1_we_upd[1] == 1'b1 & mmucr1_q[20:22] == 3'b000)) ? {5'b00000, ierat_mmucr1_1_een_upd} : -`endif - mmucr1_q[23:31]; - - // mmucr2: - assign mmucr2_d[0:31] = ((spr_match_mmucr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : - mmucr2_q[0:31]; - - // mmucr3: - assign mmucr3_0_d = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - mmucr3_0_q; - - assign tstmode4k_0_d[0] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : - ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : - tstmode4k_0_q[0]; - - assign tstmode4k_0_d[1] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : - ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : - tstmode4k_0_q[1]; - - assign tstmode4k_0_d[2:3] = ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_0_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: - ((spr_match_mmucr3_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : - tstmode4k_0_q[2:3]; - - -`ifdef MM_THREADS2 - assign mmucr3_1_d = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? { spr_data_int_q[64 - `MMUCR3_WIDTH:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? { tlb_mmucr3_x, tlb_mmucr3_rc, tlb_mmucr3_extclass, tlb_mmucr3_class, tlb_mmucr3_wlc, tlb_mmucr3_resvattr, 1'b0, tlb_mmucr3_thdid[0:`MM_THREADS-1], {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? { lrat_mmucr3_x, 2'b00, 1'b0, 1'b0, 2'b00, 2'b00, 1'b0, 1'b0, {`MM_THREADS{1'b1}}, {`THDID_WIDTH-`MM_THREADS{1'b0}} } : - mmucr3_1_q; - - assign tstmode4k_1_d[0] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[32:47] == TSTMODE4KCONST1 )) ? 1'b1 : - ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : - tstmode4k_1_q[0]; - - assign tstmode4k_1_d[1] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? 1'b1 : - ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 1'b0 : - tstmode4k_1_q[1]; - - assign tstmode4k_1_d[2:3] = ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & tstmode4k_1_q[0] == 1'b1 & spr_data_int_q[32:43] == TSTMODE4KCONST2 )) ? spr_data_int_q[46:47]: - ((spr_match_mmucr3_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write )) ? 2'b00 : - tstmode4k_1_q[2:3]; - - `endif - - assign lpidr_d = ((spr_match_lpidr_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `LPID_WIDTH:63] : - lpidr_q; - - // Perf event select registers - // Each field controls selection of 1 of 64 events per event bus bit - // mesr1: 32:37 - MUXSELEB0, - // 38:43 - MUXSELEB1, - // 44:49 - MUXSELEB2, - // 50:55 - MUXSELEB3 - // mesr2: 32:37 - MUXSELEB4, - // 38:43 - MUXSELEB5, - // 44:49 - MUXSELEB6, - // 50:55 - MUXSELEB7 - assign mesr1_d[32:32 + `MESR1_WIDTH - 1] = ((spr_match_mesr1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR1_WIDTH - 1] : - mesr1_q[32:32 + `MESR1_WIDTH - 1]; - assign mesr2_d[32:32 + `MESR2_WIDTH - 1] = ((spr_match_mesr2_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:32 + `MESR2_WIDTH - 1] : - mesr2_q[32:32 + `MESR2_WIDTH - 1]; - - assign mmucsr0_tlb0fi_d = ((mmucsr0_tlb0fi_q == 1'b0 & spr_match_mmucsr0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write & spr_data_int_q[61] == 1'b1)) ? 1'b1 : - (mmq_inval_tlb0fi_done == 1'b1) ? 1'b0 : - mmucsr0_tlb0fi_q; - - -`ifdef WAIT_UPDATES - // cp_mm_except_taken_t0_q - // 0 - val - // 1 - I=0/D=1 - // 2 - TLB miss - // 3 - Storage int (TLBI/PTfault) - // 4 - LRAT miss - // 5 - Mcheck - - assign cp_mm_except_taken_t0_d = cp_mm_except_taken_t0; - - assign tlb_mas_dtlb_error_upd[0] = tlb_mas_dtlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b11000}}; // dtlb miss except taken - assign tlb_mas_itlb_error_upd[0] = tlb_mas_itlb_error_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[1:5] == 5'b01000}}; // itlb miss except taken - assign tlb_lper_we_upd[0] = tlb_lper_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0010}}; // lrat error except taken - assign tlb_mmucr1_we_upd[0] = tlb_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // tlb mcheck except taken - assign iu_mm_ierat_mmucr1_we_upd[0] = ierat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // ierat mcheck except taken - assign xu_mm_derat_mmucr1_we_upd[0] = derat_mmucr1_we_pending_q[0] & cp_mm_except_taken_t0_q[0] & {1{cp_mm_except_taken_t0_q[2:5] == 4'b0001}}; // derat mcheck except taken - - assign tlb_mas_dtlb_error_pending_d[0] = (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b11000 ) ? 1'b0 : - (tlb_mas_dtlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (tlb_mas_dtlb_error_pending_q[0] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : - tlb_mas_dtlb_error_pending_q[0]; - - assign tlb_mas_itlb_error_pending_d[0] = (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[1:5] == 5'b01000 ) ? 1'b0 : - (tlb_mas_itlb_error_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (tlb_mas_itlb_error_pending_q[0] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : - tlb_mas_itlb_error_pending_q[0]; - - assign tlb_lper_we_pending_d[0] = (tlb_lper_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0010 ) ? 1'b0 : - (tlb_lper_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (tlb_lper_we_pending_q[0] == 1'b0 & tlb_lper_we[0] == 1'b1) ? 1'b1 : - tlb_lper_we_pending_q[0]; - - assign tlb_mmucr1_we_pending_d[0] = (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : - (tlb_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? 1'b1 : - tlb_mmucr1_we_pending_q[0]; - - assign ierat_mmucr1_we_pending_d[0] = (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : - (ierat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : - ierat_mmucr1_we_pending_q[0]; - - assign derat_mmucr1_we_pending_d[0] = (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_mm_except_taken_t0_q[0] == 1'b1 & cp_mm_except_taken_t0_q[2:5] == 4'b0001 ) ? 1'b0 : - (derat_mmucr1_we_pending_q[0] == 1'b1 & cp_flush_p1_q[0] == 1'b1) ? 1'b0 : - (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? 1'b1 : - derat_mmucr1_we_pending_q[0]; - - - assign tlb_mas1_0_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_ts_error : - tlb_mas1_0_ts_error_q; - assign tlb_mas1_0_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas1_tid_error : - tlb_mas1_0_tid_error_q; - assign tlb_mas2_0_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[0] == 1'b1) ? tlb_mas2_epn_error : - tlb_mas2_0_epn_error_q; - assign tlb_lper_0_lpn_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lpn : - tlb_lper_0_lpn_q; - assign tlb_lper_0_lps_d = (tlb_lper_we[0] == 1'b1) ? tlb_lper_lps : - tlb_lper_0_lps_q; - - assign tlb_mmucr1_0_een_d = (tlb_mmucr1_we_pending_q[0] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[0] == 1'b1) ? tlb_mmucr1_een : - tlb_mmucr1_0_een_q; - - assign ierat_mmucr1_0_een_d = (ierat_mmucr1_we_pending_q[0] == 1'b0 & iu_mm_ierat_mmucr1_we_q[0] == 1'b1) ? iu_mm_ierat_mmucr1_q : - ierat_mmucr1_0_een_q; - - assign derat_mmucr1_0_een_d = (derat_mmucr1_we_pending_q[0] == 1'b0 & xu_mm_derat_mmucr1_we_q[0] == 1'b1) ? xu_mm_derat_mmucr1_q : - derat_mmucr1_0_een_q; - - - assign tlb_mas1_0_ts_error_upd = tlb_mas1_0_ts_error_q; - assign tlb_mas1_0_tid_error_upd = tlb_mas1_0_tid_error_q; - assign tlb_mas2_0_epn_error_upd = tlb_mas2_0_epn_error_q; - assign tlb_lper_0_lpn_upd = tlb_lper_0_lpn_q; - assign tlb_lper_0_lps_upd = tlb_lper_0_lps_q; - assign tlb_mmucr1_0_een_upd = tlb_mmucr1_0_een_q; - assign ierat_mmucr1_0_een_upd = ierat_mmucr1_0_een_q; - assign derat_mmucr1_0_een_upd = derat_mmucr1_0_een_q; - -`ifdef MM_THREADS2 - // cp_mm_except_taken_t1_q - // 0 - val - // 1 - I=0/D=1 - // 2 - TLB miss - // 3 - Storage int (TLBI/PTfault) - // 4 - LRAT miss - // 5 - Mcheck - assign cp_mm_except_taken_t1_d = cp_mm_except_taken_t1; - - assign tlb_mas_dtlb_error_upd[1] = tlb_mas_dtlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b11000}}; // dtlb miss except taken - assign tlb_mas_itlb_error_upd[1] = tlb_mas_itlb_error_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[1:5] == 5'b01000}}; // itlb miss except taken - assign tlb_lper_we_upd[1] = tlb_lper_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0010}}; // lrat error except taken - assign tlb_mmucr1_we_upd[1] = tlb_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // tlb mcheck except taken - assign iu_mm_ierat_mmucr1_we_upd[1] = ierat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // ierat mcheck except taken - assign xu_mm_derat_mmucr1_we_upd[1] = derat_mmucr1_we_pending_q[1] & cp_mm_except_taken_t1_q[0] & {1{cp_mm_except_taken_t1_q[2:5] == 4'b0001}}; // derat mcheck except taken - - assign tlb_mas_dtlb_error_pending_d[1] = (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b11000 ) ? 1'b0 : - (tlb_mas_dtlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (tlb_mas_dtlb_error_pending_q[1] == 1'b0 & tlb_mas_dtlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : - tlb_mas_dtlb_error_pending_q[1]; - - assign tlb_mas_itlb_error_pending_d[1] = (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[1:5] == 5'b01000 ) ? 1'b0 : - (tlb_mas_itlb_error_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (tlb_mas_itlb_error_pending_q[1] == 1'b0 & tlb_mas_itlb_error == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : - tlb_mas_itlb_error_pending_q[1]; - - assign tlb_lper_we_pending_d[1] = (tlb_lper_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0010 ) ? 1'b0 : - (tlb_lper_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (tlb_lper_we_pending_q[1] == 1'b0 & tlb_lper_we[1] == 1'b1) ? 1'b1 : - tlb_lper_we_pending_q[1]; - - assign tlb_mmucr1_we_pending_d[1] = (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : - (tlb_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? 1'b1 : - tlb_mmucr1_we_pending_q[1]; - - assign ierat_mmucr1_we_pending_d[1] = (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[0] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : - (ierat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : - ierat_mmucr1_we_pending_q[1]; - - assign derat_mmucr1_we_pending_d[1] = (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_mm_except_taken_t1_q[1] == 1'b1 & cp_mm_except_taken_t1_q[2:5] == 4'b0001 ) ? 1'b0 : - (derat_mmucr1_we_pending_q[1] == 1'b1 & cp_flush_p1_q[1] == 1'b1) ? 1'b0 : - (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? 1'b1 : - derat_mmucr1_we_pending_q[1]; - - assign tlb_mas1_1_ts_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_ts_error : - tlb_mas1_1_ts_error_q; - assign tlb_mas1_1_tid_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas1_tid_error : - tlb_mas1_1_tid_error_q; - assign tlb_mas2_1_epn_error_d = ((tlb_mas_dtlb_error == 1'b1 | tlb_mas_itlb_error == 1'b1) & tlb_mas_thdid[1] == 1'b1) ? tlb_mas2_epn_error : - tlb_mas2_1_epn_error_q; - assign tlb_lper_1_lpn_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lpn : - tlb_lper_1_lpn_q; - assign tlb_lper_1_lps_d = (tlb_lper_we[1] == 1'b1) ? tlb_lper_lps : - tlb_lper_1_lps_q; - - assign tlb_mmucr1_1_een_d = (tlb_mmucr1_we_pending_q[1] == 1'b0 & tlb_mmucr1_we == 1'b1 & tlb_mas_thdid[1] == 1'b1) ? tlb_mmucr1_een : - tlb_mmucr1_1_een_q; - - assign ierat_mmucr1_1_een_d = (ierat_mmucr1_we_pending_q[1] == 1'b0 & iu_mm_ierat_mmucr1_we_q[1] == 1'b1) ? iu_mm_ierat_mmucr1_q : - ierat_mmucr1_1_een_q; - - assign derat_mmucr1_1_een_d = (derat_mmucr1_we_pending_q[1] == 1'b0 & xu_mm_derat_mmucr1_we_q[1] == 1'b1) ? xu_mm_derat_mmucr1_q : - derat_mmucr1_1_een_q; - - - assign tlb_mas1_1_ts_error_upd = tlb_mas1_1_ts_error_q; - assign tlb_mas1_1_tid_error_upd = tlb_mas1_1_tid_error_q; - assign tlb_mas2_1_epn_error_upd = tlb_mas2_1_epn_error_q; - assign tlb_lper_1_lpn_upd = tlb_lper_1_lpn_q; - assign tlb_lper_1_lps_upd = tlb_lper_1_lps_q; - assign tlb_mmucr1_1_een_upd = tlb_mmucr1_1_een_q; - assign ierat_mmucr1_1_een_upd = ierat_mmucr1_1_een_q; - assign derat_mmucr1_1_een_upd = derat_mmucr1_1_een_q; -`endif -`else - assign tlb_mas_dtlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_dtlb_error}}; - assign tlb_mas_itlb_error_upd = tlb_mas_thdid & {`MM_THREADS{tlb_mas_itlb_error}}; - assign tlb_lper_we_upd = tlb_lper_we; - - assign tlb_mmucr1_we_upd = {`MM_THREADS{tlb_mmucr1_we}} & tlb_mas_thdid[0:`MM_THREADS-1]; - assign iu_mm_ierat_mmucr1_we_upd = iu_mm_ierat_mmucr1_we_q; - assign xu_mm_derat_mmucr1_we_upd = xu_mm_derat_mmucr1_we_q; - - assign tlb_mas1_0_ts_error_upd = tlb_mas1_ts_error; - assign tlb_mas1_0_tid_error_upd = tlb_mas1_tid_error; - assign tlb_mas2_0_epn_error_upd = tlb_mas2_epn_error; - assign tlb_lper_0_lpn_upd = tlb_lper_lpn; - assign tlb_lper_0_lps_upd = tlb_lper_lps; - assign tlb_mmucr1_0_een_upd = tlb_mmucr1_een; - assign ierat_mmucr1_0_een_upd = iu_mm_ierat_mmucr1_q; - assign derat_mmucr1_0_een_upd = xu_mm_derat_mmucr1_q; -`ifdef MM_THREADS2 - assign tlb_mas1_1_ts_error_upd = tlb_mas1_ts_error; - assign tlb_mas1_1_tid_error_upd = tlb_mas1_tid_error; - assign tlb_mas2_1_epn_error_upd = tlb_mas2_epn_error; - assign tlb_lper_1_lpn_upd = tlb_lper_lpn; - assign tlb_lper_1_lps_upd = tlb_lper_lps; - assign tlb_mmucr1_1_een_upd = tlb_mmucr1_een; - assign ierat_mmucr1_1_een_upd = iu_mm_ierat_mmucr1_q; - assign derat_mmucr1_1_een_upd = xu_mm_derat_mmucr1_q; -`endif -`endif - - - assign lper_0_alpn_d[32:51] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : - (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[32:51] : - lper_0_alpn_q[32:51]; - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_lper_0_alpn - assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : - ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : - (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : - lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; - end - endgenerate - - generate - if (`SPR_DATA_WIDTH == 32) - begin : gen32_lper_0_alpn - assign lper_0_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : - (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : - lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]; - end - endgenerate - - assign lper_0_lps_d = ((spr_match_lper_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : - (tlb_lper_we_upd[0] == 1'b1) ? tlb_lper_0_lps_upd[60:63] : - lper_0_lps_q; - -`ifdef MM_THREADS2 - assign lper_1_alpn_d[32:51] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : - (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[32:51] : - lper_1_alpn_q[32:51]; - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_lper_1_alpn - assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH:31] : - ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : - (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : - lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; - end - endgenerate - - generate - if (`SPR_DATA_WIDTH == 32) - begin : gen32_lper_1_alpn - assign lper_1_alpn_d[64 - `REAL_ADDR_WIDTH:31] = ((spr_match_lperu_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[64 - `REAL_ADDR_WIDTH + 32:63] : - (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lpn_upd[64 - `REAL_ADDR_WIDTH:31] : - lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]; - end - endgenerate - - assign lper_1_lps_d = ((spr_match_lper_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[60:63] : - (tlb_lper_we_upd[1] == 1'b1) ? tlb_lper_1_lps_upd[60:63] : - lper_1_lps_q; -`endif - - - - assign mas1_0_v_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? 1'b0 : - ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : - ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_v : - ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : - ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_v : - mas1_0_v_q; - assign mas1_0_iprot_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_iprot : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas1_0_iprot_q; - assign mas1_0_tid_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_spid_q : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {`PID_WIDTH{1'b0}} : - mas1_0_tid_q; - assign mas1_0_ind_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? mas4_0_indd_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ind : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas1_0_ind_q; - assign mas1_0_ts_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1)) ? mas6_0_sas_q : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_ts : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas1_0_ts_q; - assign mas1_0_tsize_d = (((spr_match_mas1_0_q == 1'b1 | spr_match_mas01_64b_0_q == 1'b1 | spr_match_mas81_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas1_tsize : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas1_tsize : - mas1_0_tsize_q; - - assign mas2_0_epn_d[32:51] = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas2_0_epn_error_upd[32:51] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[32:51] : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[32:51] : - mas2_0_epn_q[32:51]; - assign mas2_0_wimge_d = ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_wimged_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_wimge : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 5'b0 : - mas2_0_wimge_q; - - assign mas3_0_rpnl_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {21{1'b0}} : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : - mas3_0_rpnl_q; - assign mas3_0_ubits_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 4'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas3_ubits : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 4'b0 : - mas3_0_ubits_q; - assign mas3_0_usxwr_d = (((spr_match_mas3_0_q == 1'b1 | spr_match_mas73_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 6'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 6'b0 : - mas3_0_usxwr_q; - - // no h/w updates to mas4 - assign mas4_0_indd_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : - mas4_0_indd_q; - assign mas4_0_tsized_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - mas4_0_tsized_q; - assign mas4_0_wimged_d = ((spr_match_mas4_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : - mas4_0_wimged_q; - - assign mas6_0_spid_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_tid_error_upd : - mas6_0_spid_q; - assign mas6_0_isize_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_tsized_q : - mas6_0_isize_q; - assign mas6_0_sind_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? mas4_0_indd_q : - mas6_0_sind_q; - assign mas6_0_sas_d = (((spr_match_mas6_0_q == 1'b1 | spr_match_mas56_64b_0_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : - ((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? tlb_mas1_0_ts_error_upd : - mas6_0_sas_q; - -`ifdef MM_THREADS2 - assign mas1_1_v_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? 1'b0 : - ((tlb_mas_tlbsx_hit == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : - ((tlb_mas_tlbre == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_v : - ((lrat_mas_tlbsx_miss == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - ((lrat_mas_tlbsx_hit == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : - ((lrat_mas_tlbre == 1'b1 & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_v : - mas1_1_v_q; - assign mas1_1_iprot_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 1'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_iprot : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas1_1_iprot_q; - assign mas1_1_tid_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_spid_q : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {`PID_WIDTH{1'b0}} : - mas1_1_tid_q; - assign mas1_1_ind_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_indd_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ind : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas1_1_ind_q; - assign mas1_1_ts_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[51] : - ((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1)) ? mas6_1_sas_q : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_ts : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas1_1_ts_q; - assign mas1_1_tsize_d = (((spr_match_mas1_1_q == 1'b1 | spr_match_mas01_64b_1_q == 1'b1 | spr_match_mas81_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_tsized_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas1_tsize : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas1_tsize : - mas1_1_tsize_q; - - assign mas2_1_epn_d[32:51] = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:51] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[32:51] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[32:51] : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[32:51] : - mas2_1_epn_q[32:51]; - assign mas2_1_wimge_d = ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? mas4_1_wimged_q : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_wimge : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 5'b0 : - mas2_1_wimge_q; - - assign mas3_1_rpnl_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:52] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 21'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? {tlb_mas3_rpnl, (tlb_mas3_usxwr[5] & tlb_mas1_ind)} : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? {lrat_mas3_rpnl, 1'b0} : - mas3_1_rpnl_q; - assign mas3_1_ubits_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:57] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 4'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas3_ubits : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 4'b0 : - mas3_1_ubits_q; - assign mas3_1_usxwr_d = (((spr_match_mas3_1_q == 1'b1 | spr_match_mas73_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[58:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 6'b0 : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? ({tlb_mas3_usxwr[0:4], (tlb_mas3_usxwr[5] & (~tlb_mas1_ind))}) : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 6'b0 : - mas3_1_usxwr_q; - - // no h/w updates to mas4 - assign mas4_1_indd_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[48] : - mas4_1_indd_q; - assign mas4_1_tsized_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - mas4_1_tsized_q; - assign mas4_1_wimged_d = ((spr_match_mas4_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[59:63] : - mas4_1_wimged_q; - - assign mas6_1_spid_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[34:47] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_tid_error_upd : - mas6_1_spid_q; - assign mas6_1_isize_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[52:55] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_tsized_q : - mas6_1_isize_q; - assign mas6_1_sind_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[62] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? mas4_1_indd_q : - mas6_1_sind_q; - assign mas6_1_sas_d = (((spr_match_mas6_1_q == 1'b1 | spr_match_mas56_64b_1_q == 1'b1) & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[63] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas1_1_ts_error_upd : - mas6_1_sas_q; -`endif - - generate - if (`SPR_DATA_WIDTH == 32) - begin : gen32_mas_d - assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : - mas0_0_atsel_q; - assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : - (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : - (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : - mas0_0_esel_q; - assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : - mas0_0_hes_q; - assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : - mas0_0_wq_q; - - assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - mas5_0_sgs_q; - assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - mas5_0_slpid_q; - - assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : - mas7_0_rpnu_q; - - assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas8_0_tgs_q; - assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas8_0_vf_q; - assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : - mas8_0_tlpid_q; - -`ifdef MM_THREADS2 - assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : - mas0_1_atsel_q; - assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : - (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : - (((tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 3'b0 : - (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : - mas0_1_esel_q; - assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : - mas0_1_hes_q; - assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : - mas0_1_wq_q; - - assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - mas5_1_sgs_q; - assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - mas5_1_slpid_q; - - assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : - mas7_1_rpnu_q; - - assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas8_1_tgs_q; - assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas8_1_vf_q; - assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : - mas8_1_tlpid_q; -`endif - end - endgenerate - - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_mas_d - assign mas0_0_atsel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b0 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b1 : - mas0_0_atsel_q; - assign mas0_0_esel_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : - ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : - (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas0_esel : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? 3'b0 : - (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas0_esel : - mas0_0_esel_q; - assign mas0_0_hes_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : - ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 1'b1 : - mas0_0_hes_q; - assign mas0_0_wq_d = ((spr_match_mas0_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : - ((spr_match_mas01_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1) ? 2'b01 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 2'b00 : - mas0_0_wq_q; - - assign mas2_0_epn_d[0:31] = ((spr_match_mas2u_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : - ((spr_match_mas2_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : - (((tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1))) ? tlb_mas2_0_epn_error_upd[0:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas2_epn[0:31] : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas2_epn[0:31] : - mas2_0_epn_q[0:31]; - - assign mas5_0_sgs_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - mas5_0_sgs_q; - assign mas5_0_slpid_d = ((spr_match_mas5_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - ((spr_match_mas56_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : - mas5_0_slpid_q; - - assign mas7_0_rpnu_d = ((spr_match_mas7_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[0] == 1'b1) | tlb_mas_dtlb_error_upd[0] == 1'b1 | tlb_mas_itlb_error_upd[0] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : - ((spr_match_mas73_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas7_rpnu : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas7_rpnu : - mas7_0_rpnu_q; - - assign mas8_0_tgs_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tgs : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas8_0_tgs_q; - assign mas8_0_vf_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_vf : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? 1'b0 : - mas8_0_vf_q; - assign mas8_0_tlpid_d = ((spr_match_mas8_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - ((spr_match_mas81_64b_0_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[0] == 1'b1)) ? tlb_mas8_tlpid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[0] == 1'b1)) ? lrat_mas8_tlpid : - mas8_0_tlpid_q; - -`ifdef MM_THREADS2 - assign mas0_1_atsel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b0 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b1 : - mas0_1_atsel_q; - assign mas0_1_esel_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[45:47] : - ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[13:15] : - (((tlb_mas_tlbsx_hit == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas0_esel : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? 3'b0 : - (((lrat_mas_tlbsx_hit == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas0_esel : - mas0_1_esel_q; - assign mas0_1_hes_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[49] : - ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[17] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 1'b1 : - mas0_1_hes_q; - assign mas0_1_wq_d = ((spr_match_mas0_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[50:51] : - ((spr_match_mas01_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[18:19] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbsx_miss == 1'b1) & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1) ? 2'b01 : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbsx_miss == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 2'b00 : - mas0_1_wq_q; - - assign mas2_1_epn_d[0:31] = ((spr_match_mas2u_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32:63] : - ((spr_match_mas2_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0:31] : - (((tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1))) ? tlb_mas2_1_epn_error_upd[0:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas2_epn[0:31] : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas2_epn[0:31] : - mas2_1_epn_q[0:31]; - - assign mas5_1_sgs_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - mas5_1_sgs_q; - assign mas5_1_slpid_d = ((spr_match_mas5_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - ((spr_match_mas56_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : - mas5_1_slpid_q; - - assign mas7_1_rpnu_d = ((spr_match_mas7_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[54:63] : - (((tlb_mas_tlbsx_miss == 1'b1 & tlb_mas_thdid[1] == 1'b1) | tlb_mas_dtlb_error_upd[1] == 1'b1 | tlb_mas_itlb_error_upd[1] == 1'b1)) ? {`REAL_ADDR_WIDTH-32{1'b0}} : - ((spr_match_mas73_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[22:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas7_rpnu : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas7_rpnu : - mas7_1_rpnu_q; - - assign mas8_1_tgs_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[32] : - ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[0] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tgs : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas8_1_tgs_q; - assign mas8_1_vf_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[33] : - ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[1] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_vf : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? 1'b0 : - mas8_1_vf_q; - assign mas8_1_tlpid_d = ((spr_match_mas8_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[56:63] : - ((spr_match_mas81_64b_1_q == 1'b1 & spr_ctl_int_q[1] == Spr_RW_Write)) ? spr_data_int_q[24:31] : - (((tlb_mas_tlbsx_hit == 1'b1 | tlb_mas_tlbre == 1'b1) & tlb_mas_thdid[1] == 1'b1)) ? tlb_mas8_tlpid : - (((lrat_mas_tlbsx_hit == 1'b1 | lrat_mas_tlbre == 1'b1) & lrat_mas_thdid[1] == 1'b1)) ? lrat_mas8_tlpid : - mas8_1_tlpid_q; -`endif - end - endgenerate - - // 0: val, 1: rw, 2: done - assign spr_ctl_out_d[0] = spr_ctl_int_q[0] & (~(spr_val_int_flushed)); - assign spr_ctl_out_d[1] = spr_ctl_int_q[1]; - assign spr_ctl_out_d[2] = (spr_ctl_int_q[2] | spr_match_any_mmu_q) & (~(spr_val_int_flushed)); - assign spr_etid_out_d = spr_etid_int_q; - assign spr_addr_out_d = spr_addr_int_q; - //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal - //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal - - assign spr_data_out_d[32:63] = ( {{32-`LPID_WIDTH{1'b0}}, lpidr_q} & {32{(spr_match_lpidr_q & spr_ctl_int_q[1])}} ) | - ( {{32-`PID_WIDTH{1'b0}}, pid0_q} & {32{(spr_match_pid0_q & spr_ctl_int_q[1])}} ) | - ( {mmucr0_0_q[0:5], 12'b0, mmucr0_0_q[6:19]} & {32{(spr_match_mmucr0_0_q & spr_ctl_int_q[1])}} ) | - ( mmucr1_q & {32{(spr_match_mmucr1_q & spr_ctl_int_q[1])}} ) | - ( mmucr2_q & {32{(spr_match_mmucr2_q & spr_ctl_int_q[1])}} ) | - ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_0_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_0_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_0_q & spr_ctl_int_q[1])}} ) | - ( {mesr1_q[32:32 + `MESR1_WIDTH - 1], {32-`MESR1_WIDTH{1'b0}}} & {32{(spr_match_mesr1_q & spr_ctl_int_q[1])}} ) | - ( {mesr2_q[32:32 + `MESR2_WIDTH - 1], {32-`MESR2_WIDTH{1'b0}}} & {32{(spr_match_mesr2_q & spr_ctl_int_q[1])}} ) | - ( {29'b0, mmucsr0_tlb0fi_q, 2'b00} & {32{(spr_match_mmucsr0_q & spr_ctl_int_q[1])}} ) | - ( {Spr_Data_MMUCFG[32:46], mmucfg_q[47:48], Spr_Data_MMUCFG[49:63]} & {32{(spr_match_mmucfg_q & spr_ctl_int_q[1])}} ) | - ( {Spr_Data_TLB0CFG[32:44], tlb0cfg_q[45:47], Spr_Data_TLB0CFG[48:63]} & {32{(spr_match_tlb0cfg_q & spr_ctl_int_q[1])}} ) | - ( Spr_Data_TLB0PS & {32{(spr_match_tlb0ps_q & spr_ctl_int_q[1])}} ) | - ( Spr_Data_LRATCFG & {32{(spr_match_lratcfg_q & spr_ctl_int_q[1])}} ) | - ( Spr_Data_LRATPS & {32{(spr_match_lratps_q & spr_ctl_int_q[1])}} ) | - ( Spr_Data_EPTCFG & {32{(spr_match_eptcfg_q & spr_ctl_int_q[1])}} ) | - ( {lper_0_alpn_q[32:51], 8'b0, lper_0_lps_q[60:63]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | - ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_0_q & spr_ctl_int_q[1])}} ) | -`ifdef MM_THREADS2 - ( {{32-`PID_WIDTH{1'b0}}, pid1_q} & {32{(spr_match_pid1_q & spr_ctl_int_q[1])}} ) | - ( {mmucr0_1_q[0:5], 12'b0, mmucr0_1_q[6:19]} & {32{(spr_match_mmucr0_1_q & spr_ctl_int_q[1])}} ) | - ( {{32-`MMUCR3_WIDTH{1'b0}}, mmucr3_1_q[64 - `MMUCR3_WIDTH:58], 1'b0, mmucr3_1_q[60:59+`MM_THREADS], {`THDID_WIDTH-`MM_THREADS{1'b0}} } & {32{(spr_match_mmucr3_1_q & spr_ctl_int_q[1])}} ) | - ( {lper_1_alpn_q[32:51], 8'b0, lper_1_lps_q[60:63]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | - ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lperu_1_q & spr_ctl_int_q[1])}} ) | -`endif - ( (spr_mas_data_out_q[32:63]) & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | - ( spr_data_int_q[32:63] & {32{(~spr_match_any_mmu_q)}} ); - - assign spr_mas_data_out[32:63] = ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas0_0}} ) | - ( {mas1_0_v_q, mas1_0_iprot_q, mas1_0_tid_q, 2'b00, mas1_0_ind_q, mas1_0_ts_q, mas1_0_tsize_q, 8'b00000000} & {32{(spr_match_mas1_0 | spr_match_mas01_64b_0 | spr_match_mas81_64b_0)}} ) | - ( {mas2_0_epn_q[32:51], 7'b0000000, mas2_0_wimge_q} & {32{spr_match_mas2_0}} ) | - ( {mas2_0_epn_q[0:31]} & {32{spr_match_mas2u_0}} ) | - ( {mas3_0_rpnl_q, 1'b0, mas3_0_ubits_q, mas3_0_usxwr_q} & {32{(spr_match_mas3_0 | spr_match_mas73_64b_0)}} ) | - ( {16'b0, mas4_0_indd_q, 3'b000, mas4_0_tsized_q, 3'b000, mas4_0_wimged_q} & {32{spr_match_mas4_0}} ) | - ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas5_0}} ) | - ( {2'b00, mas6_0_spid_q, 4'b0000, mas6_0_isize_q, 6'b000000, mas6_0_sind_q, mas6_0_sas_q} & {32{(spr_match_mas6_0 | spr_match_mas56_64b_0)}} ) | - ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas7_0}} ) | -`ifdef MM_THREADS2 - ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ) | - ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas0_1}} ) | - ( {mas1_1_v_q, mas1_1_iprot_q, mas1_1_tid_q, 2'b00, mas1_1_ind_q, mas1_1_ts_q, mas1_1_tsize_q, 8'b00000000} & {32{(spr_match_mas1_1 | spr_match_mas01_64b_1 | spr_match_mas81_64b_1)}} ) | - ( {mas2_1_epn_q[32:51], 7'b0000000, mas2_1_wimge_q} & {32{spr_match_mas2_1}} ) | - ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2u_1}} ) | - ( {mas3_1_rpnl_q, 1'b0, mas3_1_ubits_q, mas3_1_usxwr_q} & {32{(spr_match_mas3_1 | spr_match_mas73_64b_1)}} ) | - ( {16'b0, mas4_1_indd_q, 3'b000, mas4_1_tsized_q, 3'b000, mas4_1_wimged_q} & {32{spr_match_mas4_1}} ) | - ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas5_1}} ) | - ( {2'b00, mas6_1_spid_q, 4'b0000, mas6_1_isize_q, 6'b000000, mas6_1_sind_q, mas6_1_sas_q} & {32{(spr_match_mas6_1 | spr_match_mas56_64b_1)}} ) | - ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas7_1}} ) | - ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas8_1}} ); -`else - ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas8_0}} ); -`endif - - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_spr_data - assign spr_mas_data_out[0:31] = ( mas2_0_epn_q[0:31] & {32{spr_match_mas2_0}} ) | - ( {mas0_0_atsel_q, 12'b0, mas0_0_esel_q, 1'b0, mas0_0_hes_q, mas0_0_wq_q, 12'b0} & {32{spr_match_mas01_64b_0}} ) | - ( {mas5_0_sgs_q, 23'b0, mas5_0_slpid_q} & {32{spr_match_mas56_64b_0}} ) | - ( {22'b0, mas7_0_rpnu_q} & {32{spr_match_mas73_64b_0}} ) | -`ifdef MM_THREADS2 - ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ) | - ( {mas2_1_epn_q[0:31]} & {32{spr_match_mas2_1}} ) | - ( {mas0_1_atsel_q, 12'b0, mas0_1_esel_q, 1'b0, mas0_1_hes_q, mas0_1_wq_q, 12'b0} & {32{spr_match_mas01_64b_1}} ) | - ( {mas5_1_sgs_q, 23'b0, mas5_1_slpid_q} & {32{spr_match_mas56_64b_1}} ) | - ( {22'b0, mas7_1_rpnu_q} & {32{spr_match_mas73_64b_1}} ) | - ( {mas8_1_tgs_q, mas8_1_vf_q, 22'b0, mas8_1_tlpid_q} & {32{spr_match_mas81_64b_1}} ); -`else - ( {mas8_0_tgs_q, mas8_0_vf_q, 22'b0, mas8_0_tlpid_q} & {32{spr_match_mas81_64b_0}} ); -`endif - - //constant Spr_RW_Write : std_ulogic := '0'; -- write value for rw signal - //constant Spr_RW_Read : std_ulogic := '1'; -- read value for rw signal - assign spr_data_out_d[0:31] = ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_0_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_0_q & spr_ctl_int_q[1])}} ) | -`ifdef MM_THREADS2 - ( {{64-`REAL_ADDR_WIDTH{1'b0}}, lper_1_alpn_q[64 - `REAL_ADDR_WIDTH:31]} & {32{(spr_match_lper_1_q & spr_ctl_int_q[1])}} ) | -`endif - ( {spr_mas_data_out_q[0:31]} & {32{(spr_match_any_mas_q & spr_ctl_int_q[1])}} ) | - ( {spr_data_int_q[0:31]} & {32{((~(spr_match_any_mmu_q)) | (~(spr_ctl_int_q[1])))}} ); - end - endgenerate - - assign mm_iu_slowspr_val = spr_ctl_out_q[0]; - assign mm_iu_slowspr_rw = spr_ctl_out_q[1]; - assign mm_iu_slowspr_etid = spr_etid_out_q; - assign mm_iu_slowspr_addr = spr_addr_out_q; - assign mm_iu_slowspr_data = spr_data_out_q; - assign mm_iu_slowspr_done = spr_ctl_out_q[2]; - - assign mm_iu_ierat_pid0 = pid0_q; - assign mm_iu_ierat_mmucr0_0 = mmucr0_0_q; - assign mm_iu_ierat_mmucr1 = {mmucr1_q[0], mmucr1_q[2:5], mmucr1_q[6:7], mmucr1_q[12:13]}; - assign mm_xu_derat_pid0 = pid0_q; - assign mm_xu_derat_mmucr0_0 = mmucr0_0_q; - assign mm_xu_derat_mmucr1 = {mmucr1_q[1], mmucr1_q[2:5], mmucr1_q[8:9], mmucr1_q[14:16]}; -`ifdef MM_THREADS2 - assign mm_iu_ierat_pid1 = pid1_q; - assign mm_iu_ierat_mmucr0_1 = mmucr0_1_q; - assign mm_xu_derat_pid1 = pid1_q; - assign mm_xu_derat_mmucr0_1 = mmucr0_1_q; -`endif - - // mmucr1: 0-IRRE, 1-DRRE, 2-REE, 3-CEE, - // 4-Disable any context sync inst from invalidating extclass=0 erat entries, - // 5-Disable isync inst from invalidating extclass=0 erat entries, - // 6:7-IPEI, 8:9-DPEI, 10:11-TPEI, 12:13-ICTID/ITTID, 14:15-DCTID/DTTID, - // 16-DCCD, 17-TLBWE_BINV, 18-TLBI_MSB, 19-TLBI_REJ, - // 20-IERRDET, 21-DERRDET, 22-TERRDET, 23:31-EEN - assign pid0 = pid0_q; - assign mmucr0_0 = mmucr0_0_q; - assign mmucr1 = mmucr1_q; - assign mmucr2 = mmucr2_q; - assign mmucr3_0 = mmucr3_0_q; - assign tstmode4k_0 = tstmode4k_0_q[1:3]; -`ifdef MM_THREADS2 - assign pid1 = pid1_q; - assign mmucr0_1 = mmucr0_1_q; - assign mmucr3_1 = mmucr3_1_q; - assign tstmode4k_1 = tstmode4k_1_q[1:3]; -`endif - assign lpidr = lpidr_q; - assign ac_an_lpar_id = lpidr_q; - assign mmucfg_lrat = mmucfg_q[47]; - assign mmucfg_twc = mmucfg_q[48]; - assign tlb0cfg_pt = tlb0cfg_q[45]; - assign tlb0cfg_ind = tlb0cfg_q[46]; - assign tlb0cfg_gtwe = tlb0cfg_q[47]; - assign mmq_spr_event_mux_ctrls = {mesr1_q, mesr2_q}; - assign mas0_0_atsel = mas0_0_atsel_q; - assign mas0_0_esel = mas0_0_esel_q; - assign mas0_0_hes = mas0_0_hes_q; - assign mas0_0_wq = mas0_0_wq_q; - assign mas1_0_v = mas1_0_v_q; - assign mas1_0_iprot = mas1_0_iprot_q; - assign mas1_0_tid = mas1_0_tid_q; - assign mas1_0_ind = mas1_0_ind_q; - assign mas1_0_ts = mas1_0_ts_q; - assign mas1_0_tsize = mas1_0_tsize_q; - - generate - if (`SPR_DATA_WIDTH == 32) - begin : gen32_mas2_0_epn - assign mas2_0_epn[0:31] = {32{1'b0}}; - assign mas2_0_epn[32:51] = mas2_0_epn_q[32:51]; - end - endgenerate - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_mas2_0_epn - assign mas2_0_epn = mas2_0_epn_q; - end - endgenerate - - assign mas2_0_wimge = mas2_0_wimge_q; - assign mas3_0_rpnl = mas3_0_rpnl_q; - assign mas3_0_ubits = mas3_0_ubits_q; - assign mas3_0_usxwr = mas3_0_usxwr_q; - assign mas5_0_sgs = mas5_0_sgs_q; - assign mas5_0_slpid = mas5_0_slpid_q; - assign mas6_0_spid = mas6_0_spid_q; - assign mas6_0_isize = mas6_0_isize_q; - assign mas6_0_sind = mas6_0_sind_q; - assign mas6_0_sas = mas6_0_sas_q; - assign mas7_0_rpnu = mas7_0_rpnu_q; - assign mas8_0_tgs = mas8_0_tgs_q; - assign mas8_0_vf = mas8_0_vf_q; - assign mas8_0_tlpid = mas8_0_tlpid_q; -`ifdef MM_THREADS2 - assign mas0_1_atsel = mas0_1_atsel_q; - assign mas0_1_esel = mas0_1_esel_q; - assign mas0_1_hes = mas0_1_hes_q; - assign mas0_1_wq = mas0_1_wq_q; - assign mas1_1_v = mas1_1_v_q; - assign mas1_1_iprot = mas1_1_iprot_q; - assign mas1_1_tid = mas1_1_tid_q; - assign mas1_1_ind = mas1_1_ind_q; - assign mas1_1_ts = mas1_1_ts_q; - assign mas1_1_tsize = mas1_1_tsize_q; - - generate - if (`SPR_DATA_WIDTH == 32) - begin : gen32_mas2_1_epn - assign mas2_1_epn[0:31] = {32{1'b0}}; - assign mas2_1_epn[32:51] = mas2_1_epn_q[32:51]; - end - endgenerate - generate - if (`SPR_DATA_WIDTH == 64) - begin : gen64_mas2_1_epn - assign mas2_1_epn = mas2_1_epn_q; - end - endgenerate - - assign mas2_1_wimge = mas2_1_wimge_q; - assign mas3_1_rpnl = mas3_1_rpnl_q; - assign mas3_1_ubits = mas3_1_ubits_q; - assign mas3_1_usxwr = mas3_1_usxwr_q; - assign mas5_1_sgs = mas5_1_sgs_q; - assign mas5_1_slpid = mas5_1_slpid_q; - assign mas6_1_spid = mas6_1_spid_q; - assign mas6_1_isize = mas6_1_isize_q; - assign mas6_1_sind = mas6_1_sind_q; - assign mas6_1_sas = mas6_1_sas_q; - assign mas7_1_rpnu = mas7_1_rpnu_q; - assign mas8_1_tgs = mas8_1_tgs_q; - assign mas8_1_vf = mas8_1_vf_q; - assign mas8_1_tlpid = mas8_1_tlpid_q; -`endif - - assign mmucsr0_tlb0fi = mmucsr0_tlb0fi_q; - -`ifdef WAIT_UPDATES -`ifdef MM_THREADS2 - assign cp_mm_perf_except_taken_q[0] = cp_mm_except_taken_t0_q[0]; - assign cp_mm_perf_except_taken_q[1] = cp_mm_except_taken_t1_q[0]; - assign cp_mm_perf_except_taken_q[2:6] = (cp_mm_except_taken_t0_q[1:5] | cp_mm_except_taken_t1_q[1:5]); -`else - assign cp_mm_perf_except_taken_q = cp_mm_except_taken_t0_q; -`endif -`endif - - - // debug output formation - //spr_dbg_slowspr_val_in <= spr_ctl_in_q(0); -- 0: val, 1: rw, 2: done - //spr_dbg_slowspr_rw_in <= spr_ctl_in_q(1); - //spr_dbg_slowspr_etid_in <= spr_etid_in_q; - //spr_dbg_slowspr_addr_in <= spr_addr_in_q; - assign spr_dbg_slowspr_val_int = spr_ctl_int_q[0]; - assign spr_dbg_slowspr_rw_int = spr_ctl_int_q[1]; - assign spr_dbg_slowspr_etid_int = spr_etid_int_q; - assign spr_dbg_slowspr_addr_int = spr_addr_int_q; - assign spr_dbg_slowspr_val_out = spr_ctl_out_q[0]; - assign spr_dbg_slowspr_done_out = spr_ctl_out_q[2]; - assign spr_dbg_slowspr_data_out = spr_data_out_q; - assign spr_dbg_match_64b = spr_match_64b_q; - assign spr_dbg_match_any_mmu = spr_match_any_mmu_q; - assign spr_dbg_match_any_mas = spr_match_any_mas_q; - assign spr_dbg_match_mmucr1 = spr_match_mmucr1_q; - assign spr_dbg_match_mmucr2 = spr_match_mmucr2_q; - assign spr_dbg_match_lpidr = spr_match_lpidr_q; - assign spr_dbg_match_mmucsr0 = spr_match_mmucsr0_q; - assign spr_dbg_match_mmucfg = spr_match_mmucfg_q; - assign spr_dbg_match_tlb0cfg = spr_match_tlb0cfg_q; - assign spr_dbg_match_tlb0ps = spr_match_tlb0ps_q; - assign spr_dbg_match_lratcfg = spr_match_lratcfg; - assign spr_dbg_match_lratps = spr_match_lratps_q; - assign spr_dbg_match_eptcfg = spr_match_eptcfg_q; -`ifdef MM_THREADS2 - assign spr_dbg_match_pid = spr_match_pid0_q | spr_match_pid1_q; - assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q | spr_match_mmucr0_1_q; - assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q | spr_match_mmucr3_1_q; - assign spr_dbg_match_lper = spr_match_lper_0_q | spr_match_lper_1_q; - assign spr_dbg_match_lperu = spr_match_lperu_0_q | spr_match_lperu_1_q; - assign spr_dbg_match_mas0 = spr_match_mas0_0_q | spr_match_mas0_1_q; - assign spr_dbg_match_mas1 = spr_match_mas1_0_q | spr_match_mas1_1_q; - assign spr_dbg_match_mas2 = spr_match_mas2_0_q | spr_match_mas2_1_q; - assign spr_dbg_match_mas2u = spr_match_mas2u_0_q | spr_match_mas2u_1_q; - assign spr_dbg_match_mas3 = spr_match_mas3_0_q | spr_match_mas3_1_q; - assign spr_dbg_match_mas4 = spr_match_mas4_0_q | spr_match_mas4_1_q; - assign spr_dbg_match_mas5 = spr_match_mas5_0_q | spr_match_mas5_1_q; - assign spr_dbg_match_mas6 = spr_match_mas6_0_q | spr_match_mas6_1_q; - assign spr_dbg_match_mas7 = spr_match_mas7_0_q | spr_match_mas7_1_q; - assign spr_dbg_match_mas8 = spr_match_mas8_0_q | spr_match_mas8_1_q; - assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q | spr_match_mas01_64b_1_q; - assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q | spr_match_mas56_64b_1_q; - assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q | spr_match_mas73_64b_1_q; - assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q | spr_match_mas81_64b_1_q; -`else - assign spr_dbg_match_pid = spr_match_pid0_q; - assign spr_dbg_match_mmucr0 = spr_match_mmucr0_0_q; - assign spr_dbg_match_mmucr3 = spr_match_mmucr3_0_q; - assign spr_dbg_match_lper = spr_match_lper_0_q; - assign spr_dbg_match_lperu = spr_match_lperu_0_q; - assign spr_dbg_match_mas0 = spr_match_mas0_0_q; - assign spr_dbg_match_mas1 = spr_match_mas1_0_q; - assign spr_dbg_match_mas2 = spr_match_mas2_0_q; - assign spr_dbg_match_mas2u = spr_match_mas2u_0_q; - assign spr_dbg_match_mas3 = spr_match_mas3_0_q; - assign spr_dbg_match_mas4 = spr_match_mas4_0_q; - assign spr_dbg_match_mas5 = spr_match_mas5_0_q; - assign spr_dbg_match_mas6 = spr_match_mas6_0_q; - assign spr_dbg_match_mas7 = spr_match_mas7_0_q; - assign spr_dbg_match_mas8 = spr_match_mas8_0_q; - assign spr_dbg_match_mas01_64b = spr_match_mas01_64b_0_q; - assign spr_dbg_match_mas56_64b = spr_match_mas56_64b_0_q; - assign spr_dbg_match_mas73_64b = spr_match_mas73_64b_0_q; - assign spr_dbg_match_mas81_64b = spr_match_mas81_64b_0_q; -`endif - - // unused spare signal assignments - assign unused_dc[0] = |(lcb_delay_lclkr_dc[1:4]); - assign unused_dc[1] = |(lcb_mpw1_dc_b[1:4]); - assign unused_dc[2] = pc_func_sl_force; - assign unused_dc[3] = pc_func_sl_thold_0_b; - assign unused_dc[4] = tc_scan_dis_dc_b; - assign unused_dc[5] = tc_scan_diag_dc; - assign unused_dc[6] = tc_lbist_en_dc; - -generate - if (`EXPAND_TYPE != 1) - begin - assign unused_dc[7] = |(mmucfg_q_b); - assign unused_dc[8] = |(tlb0cfg_q_b); - assign unused_dc[13] = |(bcfg_spare_q_b); - end - else - begin - assign unused_dc[7] = 1'b0; - assign unused_dc[8] = 1'b0; - assign unused_dc[13] = pc_cfg_sl_thold_0; - end -endgenerate - - assign unused_dc[9] = 1'b0; - assign unused_dc[10] = 1'b0; - assign unused_dc[11] = |(lrat_tag4_hit_entry); - assign unused_dc[12] = |(bcfg_spare_q); - - //------------------------------------------------ - // latches - //------------------------------------------------ - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), - .scout(sov_0[cp_flush_offset:cp_flush_offset + `MM_THREADS - 1]), - .din(cp_flush_d[0:`MM_THREADS - 1]), - .dout(cp_flush_q[0:`MM_THREADS - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_p1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), - .scout(sov_0[cp_flush_p1_offset:cp_flush_p1_offset + `MM_THREADS - 1]), - .din(cp_flush_p1_d[0:`MM_THREADS - 1]), - .dout(cp_flush_p1_q[0:`MM_THREADS - 1]) - ); - - // slow spr daisy-chain latches - - tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_in_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), - .scout(sov_0[spr_ctl_in_offset:spr_ctl_in_offset + `SPR_CTL_WIDTH - 1]), - .din(spr_ctl_in_d[0:`SPR_CTL_WIDTH - 1]), - .dout(spr_ctl_in_q[0:`SPR_CTL_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_in_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), - .scout(sov_0[spr_etid_in_offset:spr_etid_in_offset + `SPR_ETID_WIDTH - 1]), - .din(spr_etid_in_d[0:`SPR_ETID_WIDTH - 1]), - .dout(spr_etid_in_q[0:`SPR_ETID_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), - .scout(sov_0[spr_addr_in_offset:spr_addr_in_offset + `SPR_ADDR_WIDTH - 1]), - .din(spr_addr_in_d[0:`SPR_ADDR_WIDTH - 1]), - .dout(spr_addr_in_q[0:`SPR_ADDR_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_clone_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), - .scout(sov_1[spr_addr_in_clone_offset:spr_addr_in_clone_offset + `SPR_ADDR_WIDTH - 1]), - .din(spr_addr_in_clone_d[0:`SPR_ADDR_WIDTH - 1]), - .dout(spr_addr_in_clone_q[0:`SPR_ADDR_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_in_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), - .scout(sov_0[spr_data_in_offset:spr_data_in_offset + `SPR_DATA_WIDTH - 1]), - .din(spr_data_in_d[64 - `SPR_DATA_WIDTH:63]), - .dout(spr_data_in_q[64 - `SPR_DATA_WIDTH:63]) - ); - // these are the spr internal select stage latches below - - tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_int_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), - .scout(sov_0[spr_ctl_int_offset:spr_ctl_int_offset + `SPR_CTL_WIDTH - 1]), - .din(spr_ctl_int_d[0:`SPR_CTL_WIDTH - 1]), - .dout(spr_ctl_int_q[0:`SPR_CTL_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_int_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), - .scout(sov_0[spr_etid_int_offset:spr_etid_int_offset + `SPR_ETID_WIDTH - 1]), - .din(spr_etid_int_d[0:`SPR_ETID_WIDTH - 1]), - .dout(spr_etid_int_q[0:`SPR_ETID_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_int_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), - .scout(sov_0[spr_addr_int_offset:spr_addr_int_offset + `SPR_ADDR_WIDTH - 1]), - .din(spr_addr_int_d[0:`SPR_ADDR_WIDTH - 1]), - .dout(spr_addr_int_q[0:`SPR_ADDR_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_int_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), - .scout(sov_0[spr_data_int_offset:spr_data_int_offset + `SPR_DATA_WIDTH - 1]), - .din(spr_data_int_d[64 - `SPR_DATA_WIDTH:63]), - .dout(spr_data_int_q[64 - `SPR_DATA_WIDTH:63]) - ); - // these are the spr out latches below - - tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_out_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), - .scout(sov_0[spr_ctl_out_offset:spr_ctl_out_offset + `SPR_CTL_WIDTH - 1]), - .din(spr_ctl_out_d[0:`SPR_CTL_WIDTH - 1]), - .dout(spr_ctl_out_q[0:`SPR_CTL_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_out_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), - .scout(sov_0[spr_etid_out_offset:spr_etid_out_offset + `SPR_ETID_WIDTH - 1]), - .din(spr_etid_out_d[0:`SPR_ETID_WIDTH - 1]), - .dout(spr_etid_out_q[0:`SPR_ETID_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_out_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), - .scout(sov_0[spr_addr_out_offset:spr_addr_out_offset + `SPR_ADDR_WIDTH - 1]), - .din(spr_addr_out_d[0:`SPR_ADDR_WIDTH - 1]), - .dout(spr_addr_out_q[0:`SPR_ADDR_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_out_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_val_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), - .scout(sov_0[spr_data_out_offset:spr_data_out_offset + `SPR_DATA_WIDTH - 1]), - .din(spr_data_out_d[64 - `SPR_DATA_WIDTH:63]), - .dout(spr_data_out_q[64 - `SPR_DATA_WIDTH:63]) - ); - // spr decode match latches for timing - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mmu_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_any_mmu_offset]), - .scout(sov_0[spr_match_any_mmu_offset]), - .din(spr_match_any_mmu), - .dout(spr_match_any_mmu_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_pid0_offset]), - .scout(sov_0[spr_match_pid0_offset]), - .din(spr_match_pid0), - .dout(spr_match_pid0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_pid1_offset]), - .scout(sov_0[spr_match_pid1_offset]), - .din(spr_match_pid1), - .dout(spr_match_pid1_q) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr0_0_offset]), - .scout(sov_0[spr_match_mmucr0_0_offset]), - .din(spr_match_mmucr0_0), - .dout(spr_match_mmucr0_0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr0_1_offset]), - .scout(sov_0[spr_match_mmucr0_1_offset]), - .din(spr_match_mmucr0_1), - .dout(spr_match_mmucr0_1_q) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr1_offset]), - .scout(sov_0[spr_match_mmucr1_offset]), - .din(spr_match_mmucr1), - .dout(spr_match_mmucr1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr2_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr2_offset]), - .scout(sov_0[spr_match_mmucr2_offset]), - .din(spr_match_mmucr2), - .dout(spr_match_mmucr2_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr3_0_offset]), - .scout(sov_0[spr_match_mmucr3_0_offset]), - .din(spr_match_mmucr3_0), - .dout(spr_match_mmucr3_0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mmucr3_1_offset]), - .scout(sov_0[spr_match_mmucr3_1_offset]), - .din(spr_match_mmucr3_1), - .dout(spr_match_mmucr3_1_q) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lpidr_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_lpidr_offset]), - .scout(sov_0[spr_match_lpidr_offset]), - .din(spr_match_lpidr), - .dout(spr_match_lpidr_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mesr1_offset]), - .scout(sov_0[spr_match_mesr1_offset]), - .din(spr_match_mesr1), - .dout(spr_match_mesr1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr2_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_match_mesr2_offset]), - .scout(sov_0[spr_match_mesr2_offset]), - .din(spr_match_mesr2), - .dout(spr_match_mesr2_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucsr0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mmucsr0_offset]), - .scout(sov_1[spr_match_mmucsr0_offset]), - .din(spr_match_mmucsr0), - .dout(spr_match_mmucsr0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucfg_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mmucfg_offset]), - .scout(sov_1[spr_match_mmucfg_offset]), - .din(spr_match_mmucfg), - .dout(spr_match_mmucfg_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0cfg_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_tlb0cfg_offset]), - .scout(sov_1[spr_match_tlb0cfg_offset]), - .din(spr_match_tlb0cfg), - .dout(spr_match_tlb0cfg_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0ps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_tlb0ps_offset]), - .scout(sov_1[spr_match_tlb0ps_offset]), - .din(spr_match_tlb0ps), - .dout(spr_match_tlb0ps_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratcfg_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lratcfg_offset]), - .scout(sov_1[spr_match_lratcfg_offset]), - .din(spr_match_lratcfg), - .dout(spr_match_lratcfg_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lratps_offset]), - .scout(sov_1[spr_match_lratps_offset]), - .din(spr_match_lratps), - .dout(spr_match_lratps_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_eptcfg_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_eptcfg_offset]), - .scout(sov_1[spr_match_eptcfg_offset]), - .din(spr_match_eptcfg), - .dout(spr_match_eptcfg_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lper_0_offset]), - .scout(sov_1[spr_match_lper_0_offset]), - .din(spr_match_lper_0), - .dout(spr_match_lper_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lperu_0_offset]), - .scout(sov_1[spr_match_lperu_0_offset]), - .din(spr_match_lperu_0), - .dout(spr_match_lperu_0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lper_1_offset]), - .scout(sov_1[spr_match_lper_1_offset]), - .din(spr_match_lper_1), - .dout(spr_match_lper_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_lperu_1_offset]), - .scout(sov_1[spr_match_lperu_1_offset]), - .din(spr_match_lperu_1), - .dout(spr_match_lperu_1_q) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas0_0_offset]), - .scout(sov_1[spr_match_mas0_0_offset]), - .din(spr_match_mas0_0), - .dout(spr_match_mas0_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas1_0_offset]), - .scout(sov_1[spr_match_mas1_0_offset]), - .din(spr_match_mas1_0), - .dout(spr_match_mas1_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas2_0_offset]), - .scout(sov_1[spr_match_mas2_0_offset]), - .din(spr_match_mas2_0), - .dout(spr_match_mas2_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas3_0_offset]), - .scout(sov_1[spr_match_mas3_0_offset]), - .din(spr_match_mas3_0), - .dout(spr_match_mas3_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas4_0_offset]), - .scout(sov_1[spr_match_mas4_0_offset]), - .din(spr_match_mas4_0), - .dout(spr_match_mas4_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas5_0_offset]), - .scout(sov_1[spr_match_mas5_0_offset]), - .din(spr_match_mas5_0), - .dout(spr_match_mas5_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas6_0_offset]), - .scout(sov_1[spr_match_mas6_0_offset]), - .din(spr_match_mas6_0), - .dout(spr_match_mas6_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas7_0_offset]), - .scout(sov_1[spr_match_mas7_0_offset]), - .din(spr_match_mas7_0), - .dout(spr_match_mas7_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas8_0_offset]), - .scout(sov_1[spr_match_mas8_0_offset]), - .din(spr_match_mas8_0), - .dout(spr_match_mas8_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas2u_0_offset]), - .scout(sov_1[spr_match_mas2u_0_offset]), - .din(spr_match_mas2u_0), - .dout(spr_match_mas2u_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas01_64b_0_offset]), - .scout(sov_1[spr_match_mas01_64b_0_offset]), - .din(spr_match_mas01_64b_0), - .dout(spr_match_mas01_64b_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas56_64b_0_offset]), - .scout(sov_1[spr_match_mas56_64b_0_offset]), - .din(spr_match_mas56_64b_0), - .dout(spr_match_mas56_64b_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas73_64b_0_offset]), - .scout(sov_1[spr_match_mas73_64b_0_offset]), - .din(spr_match_mas73_64b_0), - .dout(spr_match_mas73_64b_0_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas81_64b_0_offset]), - .scout(sov_1[spr_match_mas81_64b_0_offset]), - .din(spr_match_mas81_64b_0), - .dout(spr_match_mas81_64b_0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas0_1_offset]), - .scout(sov_1[spr_match_mas0_1_offset]), - .din(spr_match_mas0_1), - .dout(spr_match_mas0_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas1_1_offset]), - .scout(sov_1[spr_match_mas1_1_offset]), - .din(spr_match_mas1_1), - .dout(spr_match_mas1_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas2_1_offset]), - .scout(sov_1[spr_match_mas2_1_offset]), - .din(spr_match_mas2_1), - .dout(spr_match_mas2_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas3_1_offset]), - .scout(sov_1[spr_match_mas3_1_offset]), - .din(spr_match_mas3_1), - .dout(spr_match_mas3_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas4_1_offset]), - .scout(sov_1[spr_match_mas4_1_offset]), - .din(spr_match_mas4_1), - .dout(spr_match_mas4_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas5_1_offset]), - .scout(sov_1[spr_match_mas5_1_offset]), - .din(spr_match_mas5_1), - .dout(spr_match_mas5_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas6_1_offset]), - .scout(sov_1[spr_match_mas6_1_offset]), - .din(spr_match_mas6_1), - .dout(spr_match_mas6_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas7_1_offset]), - .scout(sov_1[spr_match_mas7_1_offset]), - .din(spr_match_mas7_1), - .dout(spr_match_mas7_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas8_1_offset]), - .scout(sov_1[spr_match_mas8_1_offset]), - .din(spr_match_mas8_1), - .dout(spr_match_mas8_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas2u_1_offset]), - .scout(sov_1[spr_match_mas2u_1_offset]), - .din(spr_match_mas2u_1), - .dout(spr_match_mas2u_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas01_64b_1_offset]), - .scout(sov_1[spr_match_mas01_64b_1_offset]), - .din(spr_match_mas01_64b_1), - .dout(spr_match_mas01_64b_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas56_64b_1_offset]), - .scout(sov_1[spr_match_mas56_64b_1_offset]), - .din(spr_match_mas56_64b_1), - .dout(spr_match_mas56_64b_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas73_64b_1_offset]), - .scout(sov_1[spr_match_mas73_64b_1_offset]), - .din(spr_match_mas73_64b_1), - .dout(spr_match_mas73_64b_1_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_mas81_64b_1_offset]), - .scout(sov_1[spr_match_mas81_64b_1_offset]), - .din(spr_match_mas81_64b_1), - .dout(spr_match_mas81_64b_1_q) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_64b_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_64b_offset]), - .scout(sov_1[spr_match_64b_offset]), - .din(spr_match_64b), - .dout(spr_match_64b_q) - ); - // internal mas data output register - - tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_mas_data_out_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mas_data_out_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), - .scout(sov_1[spr_mas_data_out_offset:spr_mas_data_out_offset + `SPR_DATA_WIDTH - 1]), - .din(spr_mas_data_out[64 - `SPR_DATA_WIDTH:63]), - .dout(spr_mas_data_out_q[64 - `SPR_DATA_WIDTH:63]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mas_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_match_mas_act), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spr_match_any_mas_offset]), - .scout(sov_1[spr_match_any_mas_offset]), - .din(spr_match_any_mas), - .dout(spr_match_any_mas_q) - ); - // pid spr's - - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mmu_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), - .scout(sov_0[pid0_offset:pid0_offset + `PID_WIDTH - 1]), - .din(pid0_d[0:`PID_WIDTH - 1]), - .dout(pid0_q[0:`PID_WIDTH - 1]) - ); - -`ifdef MM_THREADS2 - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mmu_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), - .scout(sov_0[pid1_offset:pid1_offset + `PID_WIDTH - 1]), - .din(pid1_d[0:`PID_WIDTH - 1]), - .dout(pid1_q[0:`PID_WIDTH - 1]) - ); -`endif - - tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), - .scout(sov_0[mmucr0_0_offset:mmucr0_0_offset + `MMUCR0_WIDTH - 1]), - .din(mmucr0_0_d[0:`MMUCR0_WIDTH - 1]), - .dout(mmucr0_0_q[0:`MMUCR0_WIDTH - 1]) - ); - -`ifdef MM_THREADS2 - tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), - .scout(sov_0[mmucr0_1_offset:mmucr0_1_offset + `MMUCR0_WIDTH - 1]), - .din(mmucr0_1_d[0:`MMUCR0_WIDTH - 1]), - .dout(mmucr0_1_q[0:`MMUCR0_WIDTH - 1]) - ); -`endif - - tri_rlmreg_p #(.WIDTH(`MMUCR1_WIDTH), .INIT(BCFG_MMUCR1_VALUE), .NEEDS_SRESET(1)) mmucr1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), - .scout(bsov[mmucr1_offset:mmucr1_offset + `MMUCR1_WIDTH - 1]), - .din(mmucr1_d[0:`MMUCR1_WIDTH - 1]), - .dout(mmucr1_q[0:`MMUCR1_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`MMUCR2_WIDTH), .INIT(BCFG_MMUCR2_VALUE), .NEEDS_SRESET(1)) mmucr2_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), - .scout(bsov[mmucr2_offset:mmucr2_offset + `MMUCR2_WIDTH - 1]), - .din(mmucr2_d[0:`MMUCR2_WIDTH - 1]), - .dout(mmucr2_q[0:`MMUCR2_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), - .scout(bsov[mmucr3_0_offset:mmucr3_0_offset + `MMUCR3_WIDTH - 1]), - .din(mmucr3_0_d[64 - `MMUCR3_WIDTH:63]), - .dout(mmucr3_0_q[64 - `MMUCR3_WIDTH:63]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[tstmode4k_0_offset:tstmode4k_0_offset + 3]), - .scout(bsov[tstmode4k_0_offset:tstmode4k_0_offset + 3]), - .din(tstmode4k_0_d), - .dout(tstmode4k_0_q) - ); - -`ifdef MM_THREADS2 - tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), - .scout(bsov[mmucr3_1_offset:mmucr3_1_offset + `MMUCR3_WIDTH - 1]), - .din(mmucr3_1_d[64 - `MMUCR3_WIDTH:63]), - .dout(mmucr3_1_q[64 - `MMUCR3_WIDTH:63]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[tstmode4k_1_offset:tstmode4k_1_offset + 3]), - .scout(bsov[tstmode4k_1_offset:tstmode4k_1_offset + 3]), - .din(tstmode4k_1_d), - .dout(tstmode4k_1_q) - ); - -`endif - - tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lpidr_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mmu_act_q[`MM_THREADS]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), - .scout(sov_0[lpidr_offset:lpidr_offset + `LPID_WIDTH - 1]), - .din(lpidr_d[0:`LPID_WIDTH - 1]), - .dout(lpidr_q[0:`LPID_WIDTH - 1]) - ); - - tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mmu_act_q[`MM_THREADS]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), - .scout(sov_0[mesr1_offset:mesr1_offset + `MESR1_WIDTH - 1]), - .din(mesr1_d), - .dout(mesr1_q) - ); - - tri_rlmreg_p #(.WIDTH(`MESR2_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr2_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(spr_mmu_act_q[`MM_THREADS]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), - .scout(sov_0[mesr2_offset:mesr2_offset + `MESR2_WIDTH - 1]), - .din(mesr2_d), - .dout(mesr2_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_atsel_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_0_atsel_offset]), - .scout(sov_1[mas0_0_atsel_offset]), - .din(mas0_0_atsel_d), - .dout(mas0_0_atsel_q) - ); - - tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_0_esel_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), - .scout(sov_1[mas0_0_esel_offset:mas0_0_esel_offset + 3 - 1]), - .din(mas0_0_esel_d[0:3 - 1]), - .dout(mas0_0_esel_q[0:3 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_hes_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_0_hes_offset]), - .scout(sov_1[mas0_0_hes_offset]), - .din(mas0_0_hes_d), - .dout(mas0_0_hes_q) - ); - - tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_0_wq_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), - .scout(sov_1[mas0_0_wq_offset:mas0_0_wq_offset + 2 - 1]), - .din(mas0_0_wq_d[0:2 - 1]), - .dout(mas0_0_wq_q[0:2 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_v_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_v_offset]), - .scout(sov_1[mas1_0_v_offset]), - .din(mas1_0_v_d), - .dout(mas1_0_v_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_iprot_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_iprot_offset]), - .scout(sov_1[mas1_0_iprot_offset]), - .din(mas1_0_iprot_d), - .dout(mas1_0_iprot_q) - ); - - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), - .scout(sov_1[mas1_0_tid_offset:mas1_0_tid_offset + 14 - 1]), - .din(mas1_0_tid_d[0:`PID_WIDTH - 1]), - .dout(mas1_0_tid_q[0:`PID_WIDTH - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ind_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_ind_offset]), - .scout(sov_1[mas1_0_ind_offset]), - .din(mas1_0_ind_d), - .dout(mas1_0_ind_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ts_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_ts_offset]), - .scout(sov_1[mas1_0_ts_offset]), - .din(mas1_0_ts_d), - .dout(mas1_0_ts_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tsize_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), - .scout(sov_1[mas1_0_tsize_offset:mas1_0_tsize_offset + 4 - 1]), - .din(mas1_0_tsize_d[0:4 - 1]), - .dout(mas1_0_tsize_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_0_epn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), - .scout(sov_1[mas2_0_epn_offset:mas2_0_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), - .din(mas2_0_epn_d[(64-`SPR_DATA_WIDTH):51]), - .dout(mas2_0_epn_q[(64-`SPR_DATA_WIDTH):51]) - ); - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_0_wimge_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), - .scout(sov_1[mas2_0_wimge_offset:mas2_0_wimge_offset + 5 - 1]), - .din(mas2_0_wimge_d[0:5 - 1]), - .dout(mas2_0_wimge_q[0:5 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_0_rpnl_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), - .scout(sov_1[mas3_0_rpnl_offset:mas3_0_rpnl_offset + 21 - 1]), - .din(mas3_0_rpnl_d[32:32 + 21 - 1]), - .dout(mas3_0_rpnl_q[32:32 + 21 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_0_ubits_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), - .scout(sov_1[mas3_0_ubits_offset:mas3_0_ubits_offset + 4 - 1]), - .din(mas3_0_ubits_d[0:4 - 1]), - .dout(mas3_0_ubits_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_0_usxwr_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), - .scout(sov_1[mas3_0_usxwr_offset:mas3_0_usxwr_offset + 6 - 1]), - .din(mas3_0_usxwr_d[0:6 - 1]), - .dout(mas3_0_usxwr_q[0:6 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_0_indd_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_0_indd_offset]), - .scout(bsov[mas4_0_indd_offset]), - .din(mas4_0_indd_d), - .dout(mas4_0_indd_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_0_tsized_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), - .scout(bsov[mas4_0_tsized_offset:mas4_0_tsized_offset + 4 - 1]), - .din(mas4_0_tsized_d[0:4 - 1]), - .dout(mas4_0_tsized_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_0_wimged_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), - .scout(bsov[mas4_0_wimged_offset:mas4_0_wimged_offset + 5 - 1]), - .din(mas4_0_wimged_d[0:5 - 1]), - .dout(mas4_0_wimged_q[0:5 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_0_sgs_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas5_0_sgs_offset]), - .scout(sov_1[mas5_0_sgs_offset]), - .din(mas5_0_sgs_d), - .dout(mas5_0_sgs_q) - ); - - tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_0_slpid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), - .scout(sov_1[mas5_0_slpid_offset:mas5_0_slpid_offset + 8 - 1]), - .din(mas5_0_slpid_d[0:8 - 1]), - .dout(mas5_0_slpid_q[0:8 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_0_spid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), - .scout(sov_1[mas6_0_spid_offset:mas6_0_spid_offset + 14 - 1]), - .din(mas6_0_spid_d[0:14 - 1]), - .dout(mas6_0_spid_q[0:14 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_0_isize_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), - .scout(sov_1[mas6_0_isize_offset:mas6_0_isize_offset + 4 - 1]), - .din(mas6_0_isize_d[0:4 - 1]), - .dout(mas6_0_isize_q[0:4 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sind_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_0_sind_offset]), - .scout(sov_1[mas6_0_sind_offset]), - .din(mas6_0_sind_d), - .dout(mas6_0_sind_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sas_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_0_sas_offset]), - .scout(sov_1[mas6_0_sas_offset]), - .din(mas6_0_sas_d), - .dout(mas6_0_sas_q) - ); - - tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_0_rpnu_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), - .scout(sov_1[mas7_0_rpnu_offset:mas7_0_rpnu_offset + 10 - 1]), - .din(mas7_0_rpnu_d[22:22 + 10 - 1]), - .dout(mas7_0_rpnu_q[22:22 + 10 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_tgs_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_0_tgs_offset]), - .scout(sov_1[mas8_0_tgs_offset]), - .din(mas8_0_tgs_d), - .dout(mas8_0_tgs_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_vf_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_0_vf_offset]), - .scout(sov_1[mas8_0_vf_offset]), - .din(mas8_0_vf_d), - .dout(mas8_0_vf_q) - ); - - tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_0_tlpid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), - .scout(sov_1[mas8_0_tlpid_offset:mas8_0_tlpid_offset + 8 - 1]), - .din(mas8_0_tlpid_d[0:8 - 1]), - .dout(mas8_0_tlpid_q[0:8 - 1]) - ); - -`ifdef MM_THREADS2 - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_atsel_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_1_atsel_offset]), - .scout(sov_1[mas0_1_atsel_offset]), - .din(mas0_1_atsel_d), - .dout(mas0_1_atsel_q) - ); - - tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_1_esel_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), - .scout(sov_1[mas0_1_esel_offset:mas0_1_esel_offset + 3 - 1]), - .din(mas0_1_esel_d[0:3 - 1]), - .dout(mas0_1_esel_q[0:3 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_hes_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_1_hes_offset]), - .scout(sov_1[mas0_1_hes_offset]), - .din(mas0_1_hes_d), - .dout(mas0_1_hes_q) - ); - - tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_1_wq_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), - .scout(sov_1[mas0_1_wq_offset:mas0_1_wq_offset + 2 - 1]), - .din(mas0_1_wq_d[0:2 - 1]), - .dout(mas0_1_wq_q[0:2 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_v_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_v_offset]), - .scout(sov_1[mas1_1_v_offset]), - .din(mas1_1_v_d), - .dout(mas1_1_v_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_iprot_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_iprot_offset]), - .scout(sov_1[mas1_1_iprot_offset]), - .din(mas1_1_iprot_d), - .dout(mas1_1_iprot_q) - ); - - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), - .scout(sov_1[mas1_1_tid_offset:mas1_1_tid_offset + 14 - 1]), - .din(mas1_1_tid_d[0:`PID_WIDTH - 1]), - .dout(mas1_1_tid_q[0:`PID_WIDTH - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ind_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_ind_offset]), - .scout(sov_1[mas1_1_ind_offset]), - .din(mas1_1_ind_d), - .dout(mas1_1_ind_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ts_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_ts_offset]), - .scout(sov_1[mas1_1_ts_offset]), - .din(mas1_1_ts_d), - .dout(mas1_1_ts_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tsize_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), - .scout(sov_1[mas1_1_tsize_offset:mas1_1_tsize_offset + 4 - 1]), - .din(mas1_1_tsize_d[0:4 - 1]), - .dout(mas1_1_tsize_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_1_epn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), - .scout(sov_1[mas2_1_epn_offset:mas2_1_epn_offset + (52-(64-`SPR_DATA_WIDTH)) - 1]), - .din(mas2_1_epn_d[(64-`SPR_DATA_WIDTH):51]), - .dout(mas2_1_epn_q[(64-`SPR_DATA_WIDTH):51]) - ); - - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_1_wimge_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), - .scout(sov_1[mas2_1_wimge_offset:mas2_1_wimge_offset + 5 - 1]), - .din(mas2_1_wimge_d[0:5 - 1]), - .dout(mas2_1_wimge_q[0:5 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_1_rpnl_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), - .scout(sov_1[mas3_1_rpnl_offset:mas3_1_rpnl_offset + 21 - 1]), - .din(mas3_1_rpnl_d[32:32 + 21 - 1]), - .dout(mas3_1_rpnl_q[32:32 + 21 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_1_ubits_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), - .scout(sov_1[mas3_1_ubits_offset:mas3_1_ubits_offset + 4 - 1]), - .din(mas3_1_ubits_d[0:4 - 1]), - .dout(mas3_1_ubits_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_1_usxwr_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), - .scout(sov_1[mas3_1_usxwr_offset:mas3_1_usxwr_offset + 6 - 1]), - .din(mas3_1_usxwr_d[0:6 - 1]), - .dout(mas3_1_usxwr_q[0:6 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_1_indd_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_1_indd_offset]), - .scout(bsov[mas4_1_indd_offset]), - .din(mas4_1_indd_d), - .dout(mas4_1_indd_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_1_tsized_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), - .scout(bsov[mas4_1_tsized_offset:mas4_1_tsized_offset + 4 - 1]), - .din(mas4_1_tsized_d[0:4 - 1]), - .dout(mas4_1_tsized_q[0:4 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_1_wimged_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), - .scout(bsov[mas4_1_wimged_offset:mas4_1_wimged_offset + 5 - 1]), - .din(mas4_1_wimged_d[0:5 - 1]), - .dout(mas4_1_wimged_q[0:5 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_1_sgs_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas5_1_sgs_offset]), - .scout(sov_1[mas5_1_sgs_offset]), - .din(mas5_1_sgs_d), - .dout(mas5_1_sgs_q) - ); - - tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_1_slpid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), - .scout(sov_1[mas5_1_slpid_offset:mas5_1_slpid_offset + 8 - 1]), - .din(mas5_1_slpid_d[0:8 - 1]), - .dout(mas5_1_slpid_q[0:8 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_1_spid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), - .scout(sov_1[mas6_1_spid_offset:mas6_1_spid_offset + 14 - 1]), - .din(mas6_1_spid_d[0:14 - 1]), - .dout(mas6_1_spid_q[0:14 - 1]) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_1_isize_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), - .scout(sov_1[mas6_1_isize_offset:mas6_1_isize_offset + 4 - 1]), - .din(mas6_1_isize_d[0:4 - 1]), - .dout(mas6_1_isize_q[0:4 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sind_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_1_sind_offset]), - .scout(sov_1[mas6_1_sind_offset]), - .din(mas6_1_sind_d), - .dout(mas6_1_sind_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sas_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas6_1_sas_offset]), - .scout(sov_1[mas6_1_sas_offset]), - .din(mas6_1_sas_d), - .dout(mas6_1_sas_q) - ); - - tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_1_rpnu_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), - .scout(sov_1[mas7_1_rpnu_offset:mas7_1_rpnu_offset + 10 - 1]), - .din(mas7_1_rpnu_d[22:22 + 10 - 1]), - .dout(mas7_1_rpnu_q[22:22 + 10 - 1]) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_tgs_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_1_tgs_offset]), - .scout(sov_1[mas8_1_tgs_offset]), - .din(mas8_1_tgs_d), - .dout(mas8_1_tgs_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_vf_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_1_vf_offset]), - .scout(sov_1[mas8_1_vf_offset]), - .din(mas8_1_vf_d), - .dout(mas8_1_vf_q) - ); - - tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_1_tlpid_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), - .scout(sov_1[mas8_1_tlpid_offset:mas8_1_tlpid_offset + 8 - 1]), - .din(mas8_1_tlpid_d[0:8 - 1]), - .dout(mas8_1_tlpid_q[0:8 - 1]) - ); -`endif - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucsr0_tlb0fi_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[mmucsr0_tlb0fi_offset]), - .scout(sov_1[mmucsr0_tlb0fi_offset]), - .din(mmucsr0_tlb0fi_d), - .dout(mmucsr0_tlb0fi_q) - ); - - tri_rlmreg_p #(.WIDTH(52-(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_0_alpn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), - .scout(sov_1[lper_0_alpn_offset:lper_0_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), - .din(lper_0_alpn_d), - .dout(lper_0_alpn_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_0_lps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), - .scout(sov_1[lper_0_lps_offset:lper_0_lps_offset + 4 - 1]), - .din(lper_0_lps_d), - .dout(lper_0_lps_q) - ); - -`ifdef MM_THREADS2 - tri_rlmreg_p #(.WIDTH(52 -(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_1_alpn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), - .scout(sov_1[lper_1_alpn_offset:lper_1_alpn_offset + (52 -(64-`REAL_ADDR_WIDTH)) - 1]), - .din(lper_1_alpn_d), - .dout(lper_1_alpn_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_1_lps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(mas_update_pending_act[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), - .scout(sov_1[lper_1_lps_offset:lper_1_lps_offset + 4 - 1]), - .din(lper_1_lps_d), - .dout(lper_1_lps_q) - ); -`endif - - tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) spr_mmu_act_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), - .scout(sov_0[spr_mmu_act_offset:spr_mmu_act_offset + `MM_THREADS+1 - 1]), - .din(spr_mmu_act_d), - .dout(spr_mmu_act_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) spr_val_act_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), - .scout(sov_0[spr_val_act_offset:spr_val_act_offset + 4 - 1]), - .din(spr_val_act_d), - .dout(spr_val_act_q) - ); - -`ifdef WAIT_UPDATES - tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t0_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), - .scout(sov_0[cp_mm_except_taken_t0_offset:cp_mm_except_taken_t0_offset + 6 - 1]), - .din(cp_mm_except_taken_t0_d), - .dout(cp_mm_except_taken_t0_q) - ); - // cp_mm_except_taken - // 0 - thdid/val - // 1 - I=0/D=1 - // 2 - TLB miss - // 3 - Storage int (TLBI/PTfault) - // 4 - LRAT miss - // 5 - Mcheck - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_dtlb_error_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[tlb_mas_dtlb_error_pending_offset:tlb_mas_dtlb_error_pending_offset + `MM_THREADS - 1]), - .din(tlb_mas_dtlb_error_pending_d), - .dout(tlb_mas_dtlb_error_pending_q) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_itlb_error_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[tlb_mas_itlb_error_pending_offset:tlb_mas_itlb_error_pending_offset + `MM_THREADS - 1]), - .din(tlb_mas_itlb_error_pending_d), - .dout(tlb_mas_itlb_error_pending_q) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_we_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[tlb_lper_we_pending_offset:tlb_lper_we_pending_offset + `MM_THREADS - 1]), - .din(tlb_lper_we_pending_d), - .dout(tlb_lper_we_pending_q) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_we_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[tlb_mmucr1_we_pending_offset:tlb_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .din(tlb_mmucr1_we_pending_d), - .dout(tlb_mmucr1_we_pending_q) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_we_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[ierat_mmucr1_we_pending_offset:ierat_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .din(ierat_mmucr1_we_pending_d), - .dout(ierat_mmucr1_we_pending_q) - ); - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_we_pending_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .scout(sov_0[derat_mmucr1_we_pending_offset:derat_mmucr1_we_pending_offset + `MM_THREADS - 1]), - .din(derat_mmucr1_we_pending_d), - .dout(derat_mmucr1_we_pending_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_ts_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas1_0_ts_error_offset]), - .scout(sov_0[tlb_mas1_0_ts_error_offset]), - .din(tlb_mas1_0_ts_error_d), - .dout(tlb_mas1_0_ts_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_tid_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), - .scout(sov_0[tlb_mas1_0_tid_error_offset:tlb_mas1_0_tid_error_offset + `PID_WIDTH - 1]), - .din(tlb_mas1_0_tid_error_d), - .dout(tlb_mas1_0_tid_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_0_epn_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), - .scout(sov_0[tlb_mas2_0_epn_error_offset:tlb_mas2_0_epn_error_offset + `EPN_WIDTH - 1]), - .din(tlb_mas2_0_epn_error_d), - .dout(tlb_mas2_0_epn_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lpn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), - .scout(sov_0[tlb_lper_0_lpn_offset:tlb_lper_0_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), - .din(tlb_lper_0_lpn_d), - .dout(tlb_lper_0_lpn_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), - .scout(sov_0[tlb_lper_0_lps_offset:tlb_lper_0_lps_offset + 4 - 1]), - .din(tlb_lper_0_lps_d), - .dout(tlb_lper_0_lps_q) - ); - - tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_0_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), - .scout(sov_0[tlb_mmucr1_0_een_offset:tlb_mmucr1_0_een_offset + 9 - 1]), - .din(tlb_mmucr1_0_een_d), - .dout(tlb_mmucr1_0_een_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_0_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(iu_mm_ierat_mmucr1_we_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), - .scout(sov_0[ierat_mmucr1_0_een_offset:ierat_mmucr1_0_een_offset + 4 - 1]), - .din(ierat_mmucr1_0_een_d), - .dout(ierat_mmucr1_0_een_q) - ); - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_0_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(xu_mm_derat_mmucr1_we_q[0]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), - .scout(sov_0[derat_mmucr1_0_een_offset:derat_mmucr1_0_een_offset + 5 - 1]), - .din(derat_mmucr1_0_een_d), - .dout(derat_mmucr1_0_een_q) - ); - - -`ifdef MM_THREADS2 - tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t1_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), - .scout(sov_0[cp_mm_except_taken_t1_offset:cp_mm_except_taken_t1_offset + 6 - 1]), - .din(cp_mm_except_taken_t1_d), - .dout(cp_mm_except_taken_t1_q) - ); - // cp_mm_except_taken - // 0 - thdid/val - // 1 - I=0/D=1 - // 2 - TLB miss - // 3 - Storage int (TLBI/PTfault) - // 4 - LRAT miss - // 5 - Mcheck - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_ts_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas1_1_ts_error_offset]), - .scout(sov_0[tlb_mas1_1_ts_error_offset]), - .din(tlb_mas1_1_ts_error_d), - .dout(tlb_mas1_1_ts_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_tid_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), - .scout(sov_0[tlb_mas1_1_tid_error_offset:tlb_mas1_1_tid_error_offset + `PID_WIDTH - 1]), - .din(tlb_mas1_1_tid_error_d), - .dout(tlb_mas1_1_tid_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_1_epn_error_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), - .scout(sov_0[tlb_mas2_1_epn_error_offset:tlb_mas2_1_epn_error_offset + `EPN_WIDTH - 1]), - .din(tlb_mas2_1_epn_error_d), - .dout(tlb_mas2_1_epn_error_q) - ); - - tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lpn_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), - .scout(sov_0[tlb_lper_1_lpn_offset:tlb_lper_1_lpn_offset + `REAL_ADDR_WIDTH-12 - 1]), - .din(tlb_lper_1_lpn_d), - .dout(tlb_lper_1_lpn_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lps_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), - .scout(sov_0[tlb_lper_1_lps_offset:tlb_lper_1_lps_offset + 4 - 1]), - .din(tlb_lper_1_lps_d), - .dout(tlb_lper_1_lps_q) - ); - - tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_1_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(cat_emf_act_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), - .scout(sov_0[tlb_mmucr1_1_een_offset:tlb_mmucr1_1_een_offset + 9 - 1]), - .din(tlb_mmucr1_1_een_d), - .dout(tlb_mmucr1_1_een_q) - ); - - tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_1_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(iu_mm_ierat_mmucr1_we_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), - .scout(sov_0[ierat_mmucr1_1_een_offset:ierat_mmucr1_1_een_offset + 4 - 1]), - .din(ierat_mmucr1_1_een_d), - .dout(ierat_mmucr1_1_een_q) - ); - - tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_1_een_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(xu_mm_derat_mmucr1_we_q[1]), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), - .scout(sov_0[derat_mmucr1_1_een_offset:derat_mmucr1_1_een_offset + 5 - 1]), - .din(derat_mmucr1_1_een_d), - .dout(derat_mmucr1_1_een_q) - ); - -`endif -`endif - - tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_SPR_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[cswitch_offset:cswitch_offset + 4 - 1]), - .scout(sov_0[cswitch_offset:cswitch_offset + 4 - 1]), - .din(cswitch_q), - .dout(cswitch_q) - ); - // cswitch0: 1=disable side affect of clearing I/D/TERRDET and EEN when reading mmucr1 - // cswitch1: 1=disable mmucr1.tlbwe_binv bit (make it look like it is reserved per dd1) - // cswitch2: reserved - // cswitch3: reserved - - tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cat_emf_act_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), - .scout(sov_1[cat_emf_act_offset:cat_emf_act_offset + `MM_THREADS - 1]), - .din(cat_emf_act_d), - .dout(cat_emf_act_q) - ); - - tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_0[spare_a_offset:spare_a_offset + 32 - 1]), - .scout(sov_0[spare_a_offset:spare_a_offset + 32 - 1]), - .din(spare_a_q), - .dout(spare_a_q) - ); - - tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_func_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_func_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(siv_1[spare_b_offset:spare_b_offset + 64 - 1]), - .scout(sov_1[spare_b_offset:spare_b_offset + 64 - 1]), - .din(spare_b_q), - .dout(spare_b_q) - ); - - // non-scannable timing latches - tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[0:17]), - .scout(tri_regk_unused_scan[0:17]), - .din(iu_mm_ierat_mmucr0), - .dout(iu_mm_ierat_mmucr0_q) - ); - - tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[18:35]), - .scout(tri_regk_unused_scan[18:35]), - .din(xu_mm_derat_mmucr0), - .dout(xu_mm_derat_mmucr0_q) - ); - - tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[36:39]), - .scout(tri_regk_unused_scan[36:39]), - .din(iu_mm_ierat_mmucr1), - .dout(iu_mm_ierat_mmucr1_q) - ); - - tri_regk #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[40:44]), - .scout(tri_regk_unused_scan[40:44]), - .din(xu_mm_derat_mmucr1), - .dout(xu_mm_derat_mmucr1_q) - ); - - tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_we_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[45:45+`MM_THREADS-1]), - .scout(tri_regk_unused_scan[45:45+`MM_THREADS-1]), - .din(iu_mm_ierat_mmucr1_we_d), - .dout(iu_mm_ierat_mmucr1_we_q) - ); - - tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_we_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), - .scout(tri_regk_unused_scan[45+`MM_THREADS:45+(2*`MM_THREADS)-1]), - .din(xu_mm_derat_mmucr1_we_d), - .dout(xu_mm_derat_mmucr1_we_q) - ); - - tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_we_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), - .scout(tri_regk_unused_scan[45+(2*`MM_THREADS):45+(3*`MM_THREADS)-1]), - .din(iu_mm_ierat_mmucr0_we), - .dout(iu_mm_ierat_mmucr0_we_q) - ); - - tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_we_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .sg(pc_sg_0), - .force_t(pc_func_slp_nsl_force), - .d_mode(lcb_d_mode_dc), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .thold_b(pc_func_slp_nsl_thold_0_b), - .scin(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), - .scout(tri_regk_unused_scan[45+(3*`MM_THREADS):45+(4*`MM_THREADS)-1]), - .din(xu_mm_derat_mmucr0_we), - .dout(xu_mm_derat_mmucr0_we_q) - ); - - //------------------------------------------------ - // scan only latches for boot config - // mmucr1, mmucr2, and mmucr3 also in boot config - //------------------------------------------------ - generate - if (`EXPAND_TYPE != 1) - begin : mpg_bcfg_gen - - tri_slat_scan #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) mmucfg_47to48_latch( - .vd(vdd), - .gd(gnd), - .dclk(lcb_dclk), - .lclk(lcb_lclk), - .scan_in(bsiv[mmucfg_offset:mmucfg_offset + 1]), - .scan_out(bsov[mmucfg_offset:mmucfg_offset + 1]), - .q(mmucfg_q[47:48]), - .q_b(mmucfg_q_b[47:48]) - ); - - tri_slat_scan #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .RESET_INVERTS_SCAN(1'b1)) tlb0cfg_45to47_latch( - .vd(vdd), - .gd(gnd), - .dclk(lcb_dclk), - .lclk(lcb_lclk), - .scan_in(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), - .scan_out(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), - .q(tlb0cfg_q[45:47]), - .q_b(tlb0cfg_q_b[45:47]) - ); - - tri_slat_scan #(.WIDTH(16), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) bcfg_spare_latch( - .vd(vdd), - .gd(gnd), - .dclk(lcb_dclk), - .lclk(lcb_lclk), - .scan_in(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), - .scan_out(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), - .q(bcfg_spare_q), - .q_b(bcfg_spare_q_b) - ); - - // these terms in the absence of another lcbor component - // that drives the thold_b and force into the bcfg_lcb for slat's - assign pc_cfg_sl_thold_0_b = (~pc_cfg_sl_thold_0); - assign pc_cfg_sl_force = pc_sg_0; - - //------------------------------------------------ - // local clock buffer for boot config - //------------------------------------------------ - - tri_lcbs bcfg_lcb( - .vd(vdd), - .gd(gnd), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .nclk(nclk), - .force_t(pc_cfg_sl_force), - .thold_b(pc_cfg_sl_thold_0_b), - .dclk(lcb_dclk), - .lclk(lcb_lclk) - ); - - end - endgenerate - - generate - if (`EXPAND_TYPE == 1) - begin : fpga_bcfg_gen - - tri_rlmreg_p #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .NEEDS_SRESET(1)) mmucfg_47to48_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[mmucfg_offset:mmucfg_offset + 1]), - .scout(bsov[mmucfg_offset:mmucfg_offset + 1]), - .din(mmucfg_q[47:48]), - .dout(mmucfg_q[47:48]) - ); - - tri_rlmreg_p #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .NEEDS_SRESET(1)) tlb0cfg_45to47_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[tlb0cfg_offset:tlb0cfg_offset + 2]), - .scout(bsov[tlb0cfg_offset:tlb0cfg_offset + 2]), - .din(tlb0cfg_q[45:47]), - .dout(tlb0cfg_q[45:47]) - ); - - tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) bcfg_spare_latch( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .act(tiup), - .thold_b(pc_cfg_slp_sl_thold_0_b), - .sg(pc_sg_0), - .force_t(pc_cfg_slp_sl_force), - .delay_lclkr(lcb_delay_lclkr_dc[0]), - .mpw1_b(lcb_mpw1_dc_b[0]), - .mpw2_b(lcb_mpw2_dc_b), - .d_mode(lcb_d_mode_dc), - .scin(bsiv[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), - .scout(bsov[bcfg_spare_offset:bcfg_spare_offset + 16 - 1]), - .din(bcfg_spare_q), - .dout(bcfg_spare_q) - ); - end - endgenerate - - // Latch counts - // 3319 - // spr_ctl_in_q 3 - // spr_etid_in_q 2 - // spr_addr_in_q 10 - // spr_data_in_q 64 79 - // spr_ctl_int_q 3 - // spr_etid_int_q 2 - // spr_addr_int_q 10 - // spr_data_int_q 64 79 - // spr_ctl_out_q 3 - // spr_etid_out_q 2 - // spr_addr_out_q 10 - // spr_data_out_q 64 79 - // lper_ 0:3 _alpn_q 30 x 4 - // lper_ 0:3 _lps_q 4 x 4 136 - // pid 0:3 _q 14 x 4 - // mmucr0_ 0:3 _q 20 x 4 - // mmucr1_q 32 - // mmucr2_q 32 - // mmucr3_ 0:3 _q 15 x 4 - // lpidr_q 8 - // mmucsr0_tlb0fi_q 1 269 - // mas0__atsel_q 1 x 4 : std_ulogic; - // mas0__esel_q 3 x 4 : std_ulogic_vector(0 to 2); - // mas0__hes_q 1 x 4 : std_ulogic; - // mas0__wq_q 2 x 4 : std_ulogic_vector(0 to 1); - // mas1__v_q 1 x 4 : std_ulogic; - // mas1__iprot_q 1 x 4 : std_ulogic; - // mas1__tid_q 14 x 4 : std_ulogic_vector(0 to 13); - // mas1__ind_q 1 x 4 : std_ulogic; - // mas1__ts_q 1 x 4 : std_ulogic; - // mas1__tsize_q 4 x 4 : std_ulogic_vector(0 to 3); - // mas2__epn_q 52 x 4 : std_ulogic_vector(64-`SPR_DATA_WIDTH to 51); - // mas2__wimge_q 5 x 4 : std_ulogic_vector(0 to 4); - // mas3__rpnl_q 21 x 4 : std_ulogic_vector(32 to 52); - // mas3__ubits_q 4 x 4 : std_ulogic_vector(0 to 3); - // mas3__usxwr_q 6 x 4 : std_ulogic_vector(0 to 5); - // mas4__indd_q 1 x 4 : std_ulogic; - // mas4__tsized_q 4 x 4 : std_ulogic_vector(0 to 3); - // mas4__wimged_q 5 x 4 : std_ulogic_vector(0 to 4); - // mas5__sgs_q 1 x 4 : std_ulogic; - // mas5__slpid_q 8 x 4 : std_ulogic_vector(0 to 7); - // mas6__spid_q 14 x 4 : std_ulogic_vector(0 to 13); - // mas6__isize_q 4 x 4 : std_ulogic_vector(0 to 3); - // mas6__sind_q 1 x 4 : std_ulogic; - // mas6__sas_q 1 x 4 : std_ulogic; - // mas7__rpnu_q 10 x 4 : std_ulogic_vector(22 to 31); - // mas8__tgs_q 1 x 4 : std_ulogic; - // mas8__vf_q 1 x 4 : std_ulogic; - // mas8__tlpid_q 8 x 4 : std_ulogic_vector(0 to 7); - // subtotal 176 x 4 = 704 - //-------------------------------------------------------------- - // total 1346 - //------------------------------------------------ - //------------------------------------------------ - // thold/sg latches - //------------------------------------------------ - - tri_plat #(.WIDTH(7)) perv_2to1_reg( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .flush(tc_ccflush_dc), - .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), - .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) - ); - - tri_plat #(.WIDTH(7)) perv_1to0_reg( - .vd(vdd), - .gd(gnd), - .nclk(nclk), - .flush(tc_ccflush_dc), - .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), - .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) - ); - - tri_lcbor perv_lcbor_func_sl( - .clkoff_b(lcb_clkoff_dc_b), - .thold(pc_func_sl_thold_0), - .sg(pc_sg_0), - .act_dis(lcb_act_dis_dc), - .force_t(pc_func_sl_force), - .thold_b(pc_func_sl_thold_0_b) - ); - - tri_lcbor perv_lcbor_func_slp_sl( - .clkoff_b(lcb_clkoff_dc_b), - .thold(pc_func_slp_sl_thold_0), - .sg(pc_sg_0), - .act_dis(lcb_act_dis_dc), - .force_t(pc_func_slp_sl_force), - .thold_b(pc_func_slp_sl_thold_0_b) - ); - - tri_lcbor perv_lcbor_cfg_slp_sl( - .clkoff_b(lcb_clkoff_dc_b), - .thold(pc_cfg_slp_sl_thold_0), - .sg(pc_sg_0), - .act_dis(lcb_act_dis_dc), - .force_t(pc_cfg_slp_sl_force), - .thold_b(pc_cfg_slp_sl_thold_0_b) - ); - - tri_lcbor perv_lcbor_func_slp_nsl( - .clkoff_b(lcb_clkoff_dc_b), - .thold(pc_func_slp_nsl_thold_0), - .sg(pc_fce_0), - .act_dis(tidn), - .force_t(pc_func_slp_nsl_force), - .thold_b(pc_func_slp_nsl_thold_0_b) - ); - - //--------------------------------------------------------------------- - // Scan - //--------------------------------------------------------------------- - assign siv_0[0:scan_right_0] = {sov_0[1:scan_right_0], ac_func_scan_in[0]}; - assign ac_func_scan_out[0] = sov_0[0]; - assign siv_1[0:scan_right_1] = {sov_1[1:scan_right_1], ac_func_scan_in[1]}; - assign ac_func_scan_out[1] = sov_1[0]; - assign bsiv[0:boot_scan_right] = {bsov[1:boot_scan_right], ac_bcfg_scan_in}; - assign ac_bcfg_scan_out = bsov[0]; - - function Eq; - input a, b; - reg result; - begin - if (a == b) - begin - result = 1'b1; - end - else - begin - result = 1'b0; - end - Eq = result; - end - endfunction - -endmodule diff --git a/dev/verilog/clkgating/xu_spr_cspr.v b/dev/verilog/clkgating/xu_spr_cspr.v deleted file mode 100755 index d32be15..0000000 --- a/dev/verilog/clkgating/xu_spr_cspr.v +++ /dev/null @@ -1,4970 +0,0 @@ -// © IBM Corp. 2020 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -// Description: XU SPR - per core registers & array -// -//***************************************************************************** -`include "tri_a2o.vh" -module xu_spr_cspr -#( - parameter hvmode = 1, - parameter a2mode = 1, - parameter spr_xucr0_init = `INIT_XUCR0 -)( - input [0:`NCLK_WIDTH-1] nclk, - - // CHIP IO - input [0:`THREADS-1] an_ac_reservation_vld, - input an_ac_tb_update_enable, - input an_ac_tb_update_pulse, - input [0:`THREADS-1] an_ac_sleep_en, - input [54:61] an_ac_coreid, - input [32:35] an_ac_chipid_dc, - input [8:15] spr_pvr_version_dc, - input [12:15] spr_pvr_revision_dc, - input [16:19] spr_pvr_revision_minor_dc, - input pc_xu_instr_trace_mode, - input [0:1] pc_xu_instr_trace_tid, - output [0:`THREADS-1] instr_trace_mode, - - input d_mode_dc, - input [0:0] delay_lclkr_dc, - input [0:0] mpw1_dc_b, - input mpw2_dc_b, - - input bcfg_sl_force, - input bcfg_sl_thold_0_b, - input bcfg_slp_sl_force, - input bcfg_slp_sl_thold_0_b, - input ccfg_sl_force, - input ccfg_sl_thold_0_b, - input ccfg_slp_sl_force, - input ccfg_slp_sl_thold_0_b, - input dcfg_sl_force, - input dcfg_sl_thold_0_b, - input func_sl_force, - input func_sl_thold_0_b, - input func_slp_sl_force, - input func_slp_sl_thold_0_b, - input func_nsl_force, - input func_nsl_thold_0_b, - input sg_0, - input [0:1] scan_in, - output [0:1] scan_out, - input bcfg_scan_in, - output bcfg_scan_out, - input ccfg_scan_in, - output ccfg_scan_out, - input dcfg_scan_in, - output dcfg_scan_out, - - output cspr_tspr_rf1_act, - - // Decode - input [0:`THREADS-1] rv_xu_vld, - input rv_xu_ex0_ord, - input [0:31] rv_xu_ex0_instr, - input [62-`EFF_IFAR_WIDTH:61] rv_xu_ex0_ifar, - output [62-`EFF_IFAR_WIDTH:61] ex2_ifar, - - output spr_xu_ord_read_done, - output spr_xu_ord_write_done, - input xu_spr_ord_ready, - input [0:`THREADS-1] flush, - - // Read Data - input [0:`GPR_WIDTH*`THREADS-1] tspr_cspr_ex3_tspr_rt, - output [64-`GPR_WIDTH:63] spr_xu_ex4_rd_data, - - // Write Data - input [64-`GPR_WIDTH:63] xu_spr_ex2_rs1, - output [0:`THREADS-1] cspr_tspr_ex3_spr_we, - output [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd_out, - - // SPRT Interface - output [0:`THREADS-1] cspr_tspr_ex2_tid, - output [0:31] cspr_tspr_ex1_instr, - output [0:`THREADS-1] cspr_tspr_dec_dbg_dis, - - // Illegal SPR - input [0:`THREADS-1] tspr_cspr_illeg_mtspr_b, - input [0:`THREADS-1] tspr_cspr_illeg_mfspr_b, - input [0:`THREADS-1] tspr_cspr_hypv_mtspr, - input [0:`THREADS-1] tspr_cspr_hypv_mfspr, - - // Array SPRs - output cspr_aspr_ex3_we, - output [0:5] cspr_aspr_ex3_waddr, - output cspr_aspr_ex1_re, - output [0:5] cspr_aspr_ex1_raddr, - input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] aspr_cspr_ex2_rdata, - - // Slow SPR Bus - output xu_slowspr_val_out, - output xu_slowspr_rw_out, - output [0:1] xu_slowspr_etid_out, - output [11:20] xu_slowspr_addr_out, - output [64-`GPR_WIDTH:63] xu_slowspr_data_out, - - // DCR Bus - output ac_an_dcr_act, - output ac_an_dcr_val, - output ac_an_dcr_read, - output ac_an_dcr_user, - output [0:1] ac_an_dcr_etid, - output [11:20] ac_an_dcr_addr, - output [64-`GPR_WIDTH:63] ac_an_dcr_data, - - // Trap - output spr_dec_ex4_spr_hypv, - output spr_dec_ex4_spr_illeg, - output spr_dec_ex4_spr_priv, - output spr_dec_ex4_np1_flush, - - output [0:9] cspr_tspr_timebase_taps, - output timer_update, - - // Run State - input pc_xu_pm_hold_thread, - input [0:`THREADS-1] iu_xu_stop, - output [0:`THREADS-1] xu_iu_run_thread, - output [0:`THREADS-1] xu_pc_spr_ccr0_we, - output [0:1] xu_pc_spr_ccr0_pme, - - // Quiesce - input [0:`THREADS-1] iu_xu_quiesce, - input [0:`THREADS-1] iu_xu_icache_quiesce, - input [0:`THREADS-1] lq_xu_quiesce, - input [0:`THREADS-1] mm_xu_quiesce, - input [0:`THREADS-1] bx_xu_quiesce, - output [0:`THREADS-1] xu_pc_running, - - // PCCR0 - input pc_xu_extirpts_dis_on_stop, - input pc_xu_timebase_dis_on_stop, - input pc_xu_decrem_dis_on_stop, - - // PERF - input [0:2] pc_xu_event_count_mode, - input pc_xu_event_bus_enable, - input [0:4*`THREADS-1] xu_event_bus_in, - output [0:4*`THREADS-1] xu_event_bus_out, - input [0:`THREADS-1] div_spr_running, - input [0:`THREADS-1] mul_spr_running, - - - // MSR Override - input [0:`THREADS-1] pc_xu_ram_active, - input pc_xu_msrovride_enab, - output [0:`THREADS-1] cspr_tspr_msrovride_en, - output [0:`THREADS-1] cspr_tspr_ram_active, - - // LiveLock - output [0:`THREADS-1] cspr_tspr_llen, - output [0:`THREADS-1] cspr_tspr_llpri, - input [0:`THREADS-1] tspr_cspr_lldet, - input [0:`THREADS-1] tspr_cspr_llpulse, - - // Reset - input pc_xu_reset_wd_complete, - input pc_xu_reset_3_complete, - input pc_xu_reset_2_complete, - input pc_xu_reset_1_complete, - output reset_wd_complete, - output reset_3_complete, - output reset_2_complete, - output reset_1_complete, - - // Async Interrupt Masking - output [0:`THREADS-1] cspr_tspr_crit_mask, - output [0:`THREADS-1] cspr_tspr_ext_mask, - output [0:`THREADS-1] cspr_tspr_dec_mask, - output [0:`THREADS-1] cspr_tspr_fit_mask, - output [0:`THREADS-1] cspr_tspr_wdog_mask, - output [0:`THREADS-1] cspr_tspr_udec_mask, - output [0:`THREADS-1] cspr_tspr_perf_mask, - output cspr_tspr_sleep_mask, - - input [0:`THREADS-1] tspr_cspr_pm_wake_up, - - // More Async Interrupts - output [0:`THREADS-1] xu_iu_dbell_interrupt, - output [0:`THREADS-1] xu_iu_cdbell_interrupt, - output [0:`THREADS-1] xu_iu_gdbell_interrupt, - output [0:`THREADS-1] xu_iu_gcdbell_interrupt, - output [0:`THREADS-1] xu_iu_gmcdbell_interrupt, - input [0:`THREADS-1] iu_xu_dbell_taken, - input [0:`THREADS-1] iu_xu_cdbell_taken, - input [0:`THREADS-1] iu_xu_gdbell_taken, - input [0:`THREADS-1] iu_xu_gcdbell_taken, - input [0:`THREADS-1] iu_xu_gmcdbell_taken, - - // DBELL Int - input lq_xu_dbell_val, - input [0:4] lq_xu_dbell_type, - input lq_xu_dbell_brdcast, - input lq_xu_dbell_lpid_match, - input [50:63] lq_xu_dbell_pirtag, - output [50:63] cspr_tspr_dbell_pirtag, - input [0:`THREADS-1] tspr_cspr_gpir_match, - - // Parity - output [0:`THREADS-1] xu_pc_err_sprg_ecc, - output [0:`THREADS-1] xu_pc_err_sprg_ue, - input [0:`THREADS-1] pc_xu_inj_sprg_ecc, - - // Debug - input [0:`THREADS-1] tspr_cspr_freeze_timers, - input [0:3*`THREADS-1] tspr_cspr_async_int, - - input [0:`THREADS-1] tspr_cspr_ex2_np1_flush, - - output [0:`THREADS-1] xu_iu_msrovride_enab, - input lq_xu_spr_xucr0_cslc_xuop, - input lq_xu_spr_xucr0_cslc_binv, - input lq_xu_spr_xucr0_clo, - input lq_xu_spr_xucr0_cul, - output cspr_ccr2_en_pc, - output cspr_ccr4_en_dnh, - input [0:`THREADS-1] tspr_msr_ee, - input [0:`THREADS-1] tspr_msr_ce, - input [0:`THREADS-1] tspr_msr_me, - input [0:`THREADS-1] tspr_msr_gs, - input [0:`THREADS-1] tspr_msr_pr, - output [0:4] cspr_xucr0_clkg_ctl, - output xu_lsu_spr_xucr0_clfc, - output [0:31] spr_xesr1, - output [0:31] spr_xesr2, - output [0:`THREADS-1] perf_event_en, - output spr_ccr2_en_dcr, - output spr_ccr2_en_trace, - output [0:8] spr_ccr2_ifratsc, - output spr_ccr2_ifrat, - output [0:8] spr_ccr2_dfratsc, - output spr_ccr2_dfrat, - output spr_ccr2_ucode_dis, - output [0:3] spr_ccr2_ap, - output spr_ccr2_en_attn, - output spr_ccr2_en_ditc, - output spr_ccr2_en_icswx, - output spr_ccr2_notlb, - output [0:3] spr_xucr0_trace_um, - output xu_lsu_spr_xucr0_mbar_ack, - output xu_lsu_spr_xucr0_tlbsync, - output spr_xucr0_cls, - output xu_lsu_spr_xucr0_aflsta, - output spr_xucr0_mddp, - output xu_lsu_spr_xucr0_cred, - output xu_lsu_spr_xucr0_rel, - output spr_xucr0_mdcp, - output xu_lsu_spr_xucr0_flsta, - output xu_lsu_spr_xucr0_l2siw, - output xu_lsu_spr_xucr0_flh2l2, - output xu_lsu_spr_xucr0_dcdis, - output xu_lsu_spr_xucr0_wlk, - output spr_xucr4_mmu_mchk, - output spr_xucr4_mddmh, - - output [0:39] cspr_debug0, - output [0:63] cspr_debug1, - - // Power - inout vdd, - inout gnd -); - - localparam DEX0 = 0; - localparam DEX1 = 0; - localparam DEX2 = 0; - localparam DEX3 = 0; - localparam DEX4 = 0; - localparam DEX5 = 0; - localparam DEX6 = 0; - localparam DWR = 0; - localparam DX = 0; - localparam a2hvmode = ((a2mode + hvmode) % 1); - // Types - // SPR Registers - // SPR Registers - wire [62:63] ccr0_d, ccr0_q; - wire [40:63] ccr1_d, ccr1_q; - wire [32:63] ccr2_d, ccr2_q; - wire [63:63] ccr4_d, ccr4_q; - wire [32:63] tbl_d, tbl_q; - wire [32:63] tbu_d, tbu_q; - wire [64-(`THREADS):63] tens_d, tens_q; - wire [32:63] xesr1_d, xesr1_q; - wire [32:63] xesr2_d, xesr2_q; - wire [38:63] xucr0_d, xucr0_q; - wire [60:63] xucr4_d, xucr4_q; - // FUNC Scanchain - localparam ccr1_offset = 0; - localparam tbl_offset = ccr1_offset + 24; - localparam tbu_offset = tbl_offset + 32; - localparam xesr1_offset = tbu_offset + 32; - localparam xesr2_offset = xesr1_offset + 32; - localparam last_reg_offset = xesr2_offset + 32; - // BCFG Scanchain - localparam ccr0_offset_bcfg = 0; - localparam tens_offset_bcfg = ccr0_offset_bcfg + 2; - localparam last_reg_offset_bcfg = tens_offset_bcfg + `THREADS; - // CCFG Scanchain - localparam ccr2_offset_ccfg = 0; - localparam ccr4_offset_ccfg = ccr2_offset_ccfg + 32; - localparam xucr0_offset_ccfg = ccr4_offset_ccfg + 1; - localparam last_reg_offset_ccfg = xucr0_offset_ccfg + 26; - // DCFG Scanchain - localparam xucr4_offset_dcfg = 0; - localparam last_reg_offset_dcfg = xucr4_offset_dcfg + 4; - // Latches - wire [1:4] exx_act_q, exx_act_d ; // input=>exx_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex0_val_q, rv2_val ; // input=>rv2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex1_val_q, ex0_val ; // input=>ex0_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex1_aspr_act_q, ex1_aspr_act_d ; // input=>ex1_aspr_act_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:1] ex1_aspr_tid_q, ex1_aspr_tid_d ; // input=>ex1_aspr_tid_d , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:1] ex1_tid_q, ex0_tid ; // input=>ex0_tid , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:31] ex1_instr_q ; // input=>rv_xu_ex0_instr , act=>exx_act[0] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:0] ex1_msr_gs_q, ex1_msr_gs_d ; // input=>ex1_msr_gs_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex2_val_q, ex1_val ; // input=>ex1_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_val_rd_q, ex2_val_rd_d ; // input=>ex2_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_val_wr_q, ex2_val_wr_d ; // input=>ex2_val_wr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:1] ex2_tid_q ; // input=>ex1_tid_q , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:3] ex2_aspr_addr_q, ex1_aspr_addr ; // input=>ex1_aspr_addr , act=>exx_act[1] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_mfspr_q, ex1_is_mfspr ; // input=>ex1_is_mfspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_mftb_q, ex1_is_mftb ; // input=>ex1_is_mftb , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_mtmsr_q, ex2_is_mtmsr_d ; // input=>ex1_is_mtmsr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_mtspr_q, ex1_is_mtspr ; // input=>ex1_is_mtspr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_wait_q, ex1_is_wait ; // input=>ex1_is_wait , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_priv_instr_q, ex1_priv_instr ; // input=>ex1_priv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_hypv_instr_q, ex1_hypv_instr ; // input=>ex1_hypv_instr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [9:10] ex2_wait_wc_q ; // input=>ex1_instr_q[9:10] , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_is_msgclr_q, ex1_is_msgclr ; // input=>ex1_is_msgclr , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [11:20] ex2_instr_q, ex2_instr_d ; // input=>ex2_instr_d , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:0] ex2_msr_gs_q ; // input=>ex1_msr_gs_q , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_tenc_we_q, ex1_tenc_we ; // input=>ex1_tenc_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_ccr0_we_q, ex1_ccr0_we ; // input=>ex1_ccr0_we , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [2-`GPR_WIDTH/32:1] ex2_aspr_re_q, ex1_aspr_re /*verilator split_var*/ ; // input=>ex1_aspr_re , act=>exx_act[1] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex2_dnh_q, ex1_dnh ; // input=>ex1_dnh , act=>exx_act[1] - wire [0:`THREADS-1] ex3_val_q, ex2_val ; // input=>ex2_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_val_rd_q, ex3_val_rd_d ; // input=>ex3_val_rd_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_sspr_wr_val_q, ex2_sspr_wr_val ; // input=>ex2_sspr_wr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_sspr_rd_val_q, ex2_sspr_rd_val ; // input=>ex2_sspr_rd_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_spr_we_q, ex3_spr_we_d ; // input=>ex3_spr_we_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_aspr_we_q, ex3_aspr_we_d ; // input=>ex3_aspr_we_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:3] ex3_aspr_addr_q, ex3_aspr_addr_d ; // input=>ex3_aspr_addr_d , act=>ex2_aspr_addr_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:1] ex3_tid_q ; // input=>ex2_tid_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex3_aspr_rdata_q, ex3_aspr_rdata_d ; // input=>ex3_aspr_rdata_d , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 - wire ex3_is_mtspr_q ; // input=>ex2_is_mtspr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [9:10] ex3_wait_wc_q ; // input=>ex2_wait_wc_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_is_msgclr_q ; // input=>ex2_is_msgclr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [11:20] ex3_instr_q, ex3_instr_d ; // input=>ex3_instr_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [64-`GPR_WIDTH:63] ex3_cspr_rt_q, ex2_cspr_rt ; // input=>ex2_cspr_rt , act=>exx_act_data[2], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_hypv_spr_q, ex3_hypv_spr_d ; // input=>ex3_hypv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_illeg_spr_q, ex3_illeg_spr_d ; // input=>ex3_illeg_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex3_priv_spr_q, ex3_priv_spr_d ; // input=>ex3_priv_spr_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_rt_q, ex3_rt_d ; // input=>ex3_rt_d , act=>ex3_rt_act , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1, size=>`GPR_WIDTH+8 - wire ex3_wait_q ; // input=>ex2_is_wait_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:3] ex3_aspr_ce_addr_q ; // input=>ex2_aspr_addr_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [2-`GPR_WIDTH/32:1] ex3_aspr_re_q ; // input=>ex2_aspr_re_q , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex4_val_q ; // input=>ex3_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [2-`GPR_WIDTH/32:1] ex4_aspr_re_q ; // input=>ex3_aspr_re_q , act=>exx_act[3] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [64-`GPR_WIDTH:63] ex4_spr_rt_q, ex3_spr_rt ; // input=>ex3_spr_rt , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [64-`GPR_WIDTH:63] ex4_corr_rdata_q, ex3_corr_rdata ; // input=>ex3_corr_rdata , act=>exx_act_data[3], scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`GPR_WIDTH/8] ex4_sprg_ce_q, ex4_sprg_ce_d ; // input=>ex4_sprg_ce_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:3] ex4_aspr_ce_addr_q ; // input=>ex3_aspr_ce_addr_q , act=>ex3_sprg_ce , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_hypv_spr_q ; // input=>ex3_hypv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_illeg_spr_q ; // input=>ex3_illeg_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_priv_spr_q ; // input=>ex3_priv_spr_q , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_np1_flush_q, ex4_np1_flush_d ; // input=>ex4_np1_flush_d , act=>exx_act[3] , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex5_sprg_ce_q, ex4_sprg_ce ; // input=>ex4_sprg_ce , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_sprg_ue_q, ex4_sprg_ue_d ; // input=>ex4_sprg_ue_d , act=>1'b1 , scan=>N, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ex5_sprg_ue_q, ex4_sprg_ue ; // input=>ex4_sprg_ue , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cpl_dbell_taken_q ; // input=>iu_xu_dbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cpl_cdbell_taken_q ; // input=>iu_xu_cdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cpl_gdbell_taken_q ; // input=>iu_xu_gdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cpl_gcdbell_taken_q ; // input=>iu_xu_gcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cpl_gmcdbell_taken_q ; // input=>iu_xu_gmcdbell_taken , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire set_xucr0_cslc_q, set_xucr0_cslc_d ; // input=>set_xucr0_cslc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire set_xucr0_cul_q, set_xucr0_cul_d ; // input=>set_xucr0_cul_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire set_xucr0_clo_q, set_xucr0_clo_d ; // input=>set_xucr0_clo_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire ex3_np1_flush_q, ex3_np1_flush_d ; // input=>ex3_np1_flush_d , act=>exx_act[2] , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] running_q, running_d ; // input=>running_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] llpri_q, llpri_d ; // input=>llpri_d , act=>llpri_inc , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1, init=>2**(``THREADS-1) - wire [0:`THREADS-1] dec_dbg_dis_q, dec_dbg_dis_d ; // input=>dec_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire tb_dbg_dis_q, tb_dbg_dis_d ; // input=>tb_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire tb_act_q, tb_act_d ; // input=>tb_act_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] ext_dbg_dis_q, ext_dbg_dis_d ; // input=>ext_dbg_dis_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire msrovride_enab_q ; // input=>pc_xu_msrovride_enab , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] waitimpl_val_q, waitimpl_val_d ; // input=>waitimpl_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] waitrsv_val_q, waitrsv_val_d ; // input=>waitrsv_val_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] an_ac_reservation_vld_q ; // input=>an_ac_reservation_vld , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] an_ac_sleep_en_q ; // input=>an_ac_sleep_en , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [54:61] an_ac_coreid_q ; // input=>an_ac_coreid , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire tb_update_enable_q ; // input=>an_ac_tb_update_enable , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire tb_update_pulse_q ; // input=>an_ac_tb_update_pulse , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire tb_update_pulse_1_q ; // input=>tb_update_pulse_q , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire pc_xu_reset_wd_complete_q ; // input=>pc_xu_reset_wd_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire pc_xu_reset_3_complete_q ; // input=>pc_xu_reset_3_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire pc_xu_reset_2_complete_q ; // input=>pc_xu_reset_2_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire pc_xu_reset_1_complete_q ; // input=>pc_xu_reset_1_complete , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire lq_xu_dbell_val_q ; // input=>lq_xu_dbell_val , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:4] lq_xu_dbell_type_q ; // input=>lq_xu_dbell_type , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire lq_xu_dbell_brdcast_q ; // input=>lq_xu_dbell_brdcast , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire lq_xu_dbell_lpid_match_q ; // input=>lq_xu_dbell_lpid_match , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [50:63] lq_xu_dbell_pirtag_q ; // input=>lq_xu_dbell_pirtag , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] dbell_present_q, dbell_present_d ; // input=>dbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cdbell_present_q, cdbell_present_d ; // input=>cdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gdbell_present_q, gdbell_present_d ; // input=>gdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gcdbell_present_q, gcdbell_present_d ; // input=>gcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gmcdbell_present_q, gmcdbell_present_d ; // input=>gmcdbell_present_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire xucr0_clfc_q, xucr0_clfc_d ; // input=>xucr0_clfc_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] iu_run_thread_q, iu_run_thread_d ; // input=>iu_run_thread_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] inj_sprg_ecc_q ; // input=>pc_xu_inj_sprg_ecc , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] dbell_interrupt_q, dbell_interrupt ; // input=>dbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] cdbell_interrupt_q, cdbell_interrupt ; // input=>cdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gdbell_interrupt_q, gdbell_interrupt ; // input=>gdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gcdbell_interrupt_q, gcdbell_interrupt ; // input=>gcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] gmcdbell_interrupt_q, gmcdbell_interrupt ; // input=>gmcdbell_interrupt , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] iu_quiesce_q ; // input=>iu_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] iu_icache_quiesce_q ; // input=>iu_xu_icache_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] lsu_quiesce_q ; // input=>lq_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] mm_quiesce_q ; // input=>mm_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] bx_quiesce_q ; // input=>bx_xu_quiesce , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] quiesce_q, quiesce_d ; // input=>quiesce_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] quiesced_q, quiesced_d ; // input=>quiesced_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire instr_trace_mode_q ; // input=>pc_xu_instr_trace_mode , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:1] instr_trace_tid_q ; // input=>pc_xu_instr_trace_tid , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire timer_update_q ; // input=>timer_update_int , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire spr_xu_ord_read_done_q, spr_xu_ord_read_done_d ; // input=>spr_xu_ord_read_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire spr_xu_ord_write_done_q, spr_xu_ord_write_done_d ; // input=>spr_xu_ord_write_done_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire xu_spr_ord_ready_q ; // input=>xu_spr_ord_ready , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_sspr_val_q ; // input=>ex3_sspr_val , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] flush_q ; // input=>flush , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire [62-`EFF_IFAR_WIDTH:61] ex1_ifar_q ; // input=>rv_xu_ex0_ifar , act=>exx_act[0] , scan=>Y, sleep=>N, needs_sreset=>1 - wire [62-`EFF_IFAR_WIDTH:61] ex2_ifar_q ; // input=>ex1_ifar_q , act=>exx_act[1] , scan=>Y, sleep=>N, needs_sreset=>1 - wire [0:`THREADS-1] ram_active_q ; // input=>pc_xu_ram_active , act=>1'b1 - wire [0:4] timer_div_q, timer_div_d ; // input=>timer_div_d , act=>timer_div_act , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] msrovride_enab_2_q, msrovride_enab ; // input=>msrovride_enab , act=>1'b1 - wire [0:`THREADS-1] msrovride_enab_3_q ; // input=>msrovride_enab_2_q , act=>1'b1 - wire ex3_wait_flush_q, ex3_wait_flush_d ; // input=>ex3_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire ex4_wait_flush_q, ex4_wait_flush_d ; // input=>ex4_wait_flush_d , act=>1'b1 , scan=>Y, sleep=>N, ring=>func, needs_sreset=>1 - wire pc_xu_pm_hold_thread_q ; // input=>pc_xu_pm_hold_thread , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire power_savings_on_q, power_savings_on_d ; // input=>power_savings_on_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:4*`THREADS-1] perf_event_bus_q, perf_event_bus_d ; // input=>perf_event_bus_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:`THREADS-1] perf_event_en_q, perf_event_en_d ; // input=>perf_event_en_d , act=>pc_xu_event_bus_enable , scan=>Y, sleep=>Y, ring=>func, needs_sreset=>1 - wire [0:15] spare_0_q, spare_0_d ; // input=>spare_0_d , act=>1'b1 , - // Scanchains - localparam exx_act_offset = last_reg_offset; - localparam ex0_val_offset = exx_act_offset + 4; - localparam ex1_val_offset = ex0_val_offset + `THREADS; - localparam ex1_aspr_act_offset = ex1_val_offset + `THREADS; - localparam ex1_aspr_tid_offset = ex1_aspr_act_offset + 1; - localparam ex1_tid_offset = ex1_aspr_tid_offset + 2; - localparam ex1_instr_offset = ex1_tid_offset + 2; - localparam ex1_msr_gs_offset = ex1_instr_offset + 32; - localparam ex2_val_offset = ex1_msr_gs_offset + 1; - localparam ex2_val_rd_offset = ex2_val_offset + `THREADS; - localparam ex2_val_wr_offset = ex2_val_rd_offset + 1; - localparam ex2_tid_offset = ex2_val_wr_offset + 1; - localparam ex2_aspr_addr_offset = ex2_tid_offset + 2; - localparam ex2_is_mfspr_offset = ex2_aspr_addr_offset + 4; - localparam ex2_is_mftb_offset = ex2_is_mfspr_offset + 1; - localparam ex2_is_mtmsr_offset = ex2_is_mftb_offset + 1; - localparam ex2_is_mtspr_offset = ex2_is_mtmsr_offset + 1; - localparam ex2_is_wait_offset = ex2_is_mtspr_offset + 1; - localparam ex2_priv_instr_offset = ex2_is_wait_offset + 1; - localparam ex2_hypv_instr_offset = ex2_priv_instr_offset + 1; - localparam ex2_wait_wc_offset = ex2_hypv_instr_offset + 1; - localparam ex2_is_msgclr_offset = ex2_wait_wc_offset + 2; - localparam ex2_instr_offset = ex2_is_msgclr_offset + 1; - localparam ex2_msr_gs_offset = ex2_instr_offset + 10; - localparam ex2_tenc_we_offset = ex2_msr_gs_offset + 1; - localparam ex2_ccr0_we_offset = ex2_tenc_we_offset + 1; - localparam ex2_aspr_re_offset = ex2_ccr0_we_offset + 1; - localparam ex2_dnh_offset = ex2_aspr_re_offset + `GPR_WIDTH/32; - localparam ex3_val_offset = ex2_dnh_offset + 1; - localparam ex3_val_rd_offset = ex3_val_offset + `THREADS; - localparam ex3_sspr_wr_val_offset = ex3_val_rd_offset + 1; - localparam ex3_sspr_rd_val_offset = ex3_sspr_wr_val_offset + 1; - localparam ex3_spr_we_offset = ex3_sspr_rd_val_offset + 1; - localparam ex3_aspr_we_offset = ex3_spr_we_offset + 1; - localparam ex3_aspr_addr_offset = ex3_aspr_we_offset + 1; - localparam ex3_tid_offset = ex3_aspr_addr_offset + 4; - localparam ex3_aspr_rdata_offset = ex3_tid_offset + 2; - localparam ex3_is_mtspr_offset = ex3_aspr_rdata_offset + `GPR_WIDTH+8; - localparam ex3_wait_wc_offset = ex3_is_mtspr_offset + 1; - localparam ex3_is_msgclr_offset = ex3_wait_wc_offset + 2; - localparam ex3_instr_offset = ex3_is_msgclr_offset + 1; - localparam ex3_cspr_rt_offset = ex3_instr_offset + 10; - localparam ex3_hypv_spr_offset = ex3_cspr_rt_offset + `GPR_WIDTH; - localparam ex3_illeg_spr_offset = ex3_hypv_spr_offset + 1; - localparam ex3_priv_spr_offset = ex3_illeg_spr_offset + 1; - localparam ex3_rt_offset = ex3_priv_spr_offset + 1; - localparam ex3_wait_offset = ex3_rt_offset + `GPR_WIDTH+8; - localparam ex3_aspr_ce_addr_offset = ex3_wait_offset + 1; - localparam ex3_aspr_re_offset = ex3_aspr_ce_addr_offset + 4; - localparam ex4_val_offset = ex3_aspr_re_offset + `GPR_WIDTH/32; - localparam ex4_aspr_re_offset = ex4_val_offset + `THREADS; - localparam ex4_spr_rt_offset = ex4_aspr_re_offset + `GPR_WIDTH/32; - localparam ex4_corr_rdata_offset = ex4_spr_rt_offset + `GPR_WIDTH; - localparam ex4_sprg_ce_offset = ex4_corr_rdata_offset + `GPR_WIDTH; - localparam ex4_aspr_ce_addr_offset = ex4_sprg_ce_offset + `GPR_WIDTH/8+1; - localparam ex4_hypv_spr_offset = ex4_aspr_ce_addr_offset + 4; - localparam ex4_illeg_spr_offset = ex4_hypv_spr_offset + 1; - localparam ex4_priv_spr_offset = ex4_illeg_spr_offset + 1; - localparam ex4_np1_flush_offset = ex4_priv_spr_offset + 1; - localparam ex5_sprg_ce_offset = ex4_np1_flush_offset + 1; - localparam ex4_sprg_ue_offset = ex5_sprg_ce_offset + `THREADS; - localparam ex5_sprg_ue_offset = ex4_sprg_ue_offset + 1; - localparam cpl_dbell_taken_offset = ex5_sprg_ue_offset + `THREADS; - localparam cpl_cdbell_taken_offset = cpl_dbell_taken_offset + `THREADS; - localparam cpl_gdbell_taken_offset = cpl_cdbell_taken_offset + `THREADS; - localparam cpl_gcdbell_taken_offset = cpl_gdbell_taken_offset + `THREADS; - localparam cpl_gmcdbell_taken_offset = cpl_gcdbell_taken_offset + `THREADS; - localparam set_xucr0_cslc_offset = cpl_gmcdbell_taken_offset + `THREADS; - localparam set_xucr0_cul_offset = set_xucr0_cslc_offset + 1; - localparam set_xucr0_clo_offset = set_xucr0_cul_offset + 1; - localparam ex3_np1_flush_offset = set_xucr0_clo_offset + 1; - localparam running_offset = ex3_np1_flush_offset + 1; - localparam llpri_offset = running_offset + `THREADS; - localparam dec_dbg_dis_offset = llpri_offset + `THREADS; - localparam tb_dbg_dis_offset = dec_dbg_dis_offset + `THREADS; - localparam tb_act_offset = tb_dbg_dis_offset + 1; - localparam ext_dbg_dis_offset = tb_act_offset + 1; - localparam msrovride_enab_offset = ext_dbg_dis_offset + `THREADS; - localparam waitimpl_val_offset = msrovride_enab_offset + 1; - localparam waitrsv_val_offset = waitimpl_val_offset + `THREADS; - localparam an_ac_reservation_vld_offset = waitrsv_val_offset + `THREADS; - localparam an_ac_sleep_en_offset = an_ac_reservation_vld_offset + `THREADS; - localparam an_ac_coreid_offset = an_ac_sleep_en_offset + `THREADS; - localparam tb_update_enable_offset = an_ac_coreid_offset + 8; - localparam tb_update_pulse_offset = tb_update_enable_offset + 1; - localparam tb_update_pulse_1_offset = tb_update_pulse_offset + 1; - localparam pc_xu_reset_wd_complete_offset = tb_update_pulse_1_offset + 1; - localparam pc_xu_reset_3_complete_offset = pc_xu_reset_wd_complete_offset + 1; - localparam pc_xu_reset_2_complete_offset = pc_xu_reset_3_complete_offset + 1; - localparam pc_xu_reset_1_complete_offset = pc_xu_reset_2_complete_offset + 1; - localparam lq_xu_dbell_val_offset = pc_xu_reset_1_complete_offset + 1; - localparam lq_xu_dbell_type_offset = lq_xu_dbell_val_offset + 1; - localparam lq_xu_dbell_brdcast_offset = lq_xu_dbell_type_offset + 5; - localparam lq_xu_dbell_lpid_match_offset = lq_xu_dbell_brdcast_offset + 1; - localparam lq_xu_dbell_pirtag_offset = lq_xu_dbell_lpid_match_offset + 1; - localparam dbell_present_offset = lq_xu_dbell_pirtag_offset + 14; - localparam cdbell_present_offset = dbell_present_offset + `THREADS; - localparam gdbell_present_offset = cdbell_present_offset + `THREADS; - localparam gcdbell_present_offset = gdbell_present_offset + `THREADS; - localparam gmcdbell_present_offset = gcdbell_present_offset + `THREADS; - localparam xucr0_clfc_offset = gmcdbell_present_offset + `THREADS; - localparam iu_run_thread_offset = xucr0_clfc_offset + 1; - localparam inj_sprg_ecc_offset = iu_run_thread_offset + `THREADS; - localparam dbell_interrupt_offset = inj_sprg_ecc_offset + `THREADS; - localparam cdbell_interrupt_offset = dbell_interrupt_offset + `THREADS; - localparam gdbell_interrupt_offset = cdbell_interrupt_offset + `THREADS; - localparam gcdbell_interrupt_offset = gdbell_interrupt_offset + `THREADS; - localparam gmcdbell_interrupt_offset = gcdbell_interrupt_offset + `THREADS; - localparam iu_quiesce_offset = gmcdbell_interrupt_offset + `THREADS; - localparam iu_icache_quiesce_offset = iu_quiesce_offset + `THREADS; - localparam lsu_quiesce_offset = iu_icache_quiesce_offset + `THREADS; - localparam mm_quiesce_offset = lsu_quiesce_offset + `THREADS; - localparam bx_quiesce_offset = mm_quiesce_offset + `THREADS; - localparam quiesce_offset = bx_quiesce_offset + `THREADS; - localparam quiesced_offset = quiesce_offset + `THREADS; - localparam instr_trace_mode_offset = quiesced_offset + `THREADS; - localparam instr_trace_tid_offset = instr_trace_mode_offset + 1; - localparam timer_update_offset = instr_trace_tid_offset + 2; - localparam spr_xu_ord_read_done_offset = timer_update_offset + 1; - localparam spr_xu_ord_write_done_offset = spr_xu_ord_read_done_offset + 1; - localparam xu_spr_ord_ready_offset = spr_xu_ord_write_done_offset + 1; - localparam ex4_sspr_val_offset = xu_spr_ord_ready_offset + 1; - localparam flush_offset = ex4_sspr_val_offset + 1; - localparam ex1_ifar_offset = flush_offset + `THREADS; - localparam ex2_ifar_offset = ex1_ifar_offset + `EFF_IFAR_WIDTH; - localparam ram_active_offset = ex2_ifar_offset + `EFF_IFAR_WIDTH; - localparam timer_div_offset = ram_active_offset + `THREADS; - localparam msrovride_enab_2_offset = timer_div_offset + 5; - localparam msrovride_enab_3_offset = msrovride_enab_2_offset + `THREADS; - localparam ex3_wait_flush_offset = msrovride_enab_3_offset + `THREADS; - localparam ex4_wait_flush_offset = ex3_wait_flush_offset + 1; - localparam pc_xu_pm_hold_thread_offset = ex4_wait_flush_offset + 1; - localparam power_savings_on_offset = pc_xu_pm_hold_thread_offset + 1; - localparam perf_event_bus_offset = power_savings_on_offset + 1; - localparam perf_event_en_offset = perf_event_bus_offset + 4*`THREADS; - localparam spare_0_offset = perf_event_en_offset + `THREADS; - localparam quiesced_ctr_offset = spare_0_offset + 16; - localparam scan_right = quiesced_ctr_offset + 1; - wire [0:scan_right-1] siv; - wire [0:scan_right-1] sov; - - - wire [0:`THREADS-1] ccr0_we_q, ccr0_we_d ; // input=>ccr0_we_d , act=>1'b1 , scan=>Y, sleep=>Y, ring=>bcfg, needs_sreset=>1 - localparam ccr0_we_offset_bcfg = last_reg_offset_bcfg; - localparam scan_right_bcfg = ccr0_we_offset_bcfg + `THREADS; - wire [0:scan_right_bcfg-1] siv_bcfg; - wire [0:scan_right_bcfg-1] sov_bcfg; - localparam scan_right_ccfg = last_reg_offset_ccfg; - wire [0:scan_right_ccfg-1] siv_ccfg; - wire [0:scan_right_ccfg-1] sov_ccfg; - localparam scan_right_dcfg = last_reg_offset_dcfg; - wire [0:scan_right_dcfg-1] siv_dcfg; - wire [0:scan_right_dcfg-1] sov_dcfg; - // Signals - wire [00:63] tidn; - wire [0:`NCLK_WIDTH-1] spare_0_lclk; - wire spare_0_d1clk; - wire spare_0_d2clk; - wire [00:63] tb; - wire ex1_opcode_is_31; - wire ex1_opcode_is_19; - wire ex1_is_mfcr; - wire ex1_is_mtcrf; - wire ex1_is_dnh; - wire ex1_is_mfmsr; - wire ex1_is_mtmsr; - wire ex3_sspr_val; - wire [0:`THREADS-1] ex2_tid; - wire ex2_illeg_mfspr; - wire ex2_illeg_mtspr; - wire ex2_illeg_mftb; - wire ex2_hypv_mfspr; - wire ex2_hypv_mtspr; - wire [11:20] ex1_instr; - wire [11:20] ex2_instr; - wire [11:20] ex3_instr; - wire ex2_slowspr_range_priv; - wire ex2_slowspr_range_hypv; - wire ex2_slowspr_range; - wire [0:`THREADS-1] ex2_wait_flush; - wire [0:`THREADS-1] ex2_ccr0_flush; - wire [0:`THREADS-1] ex2_tenc_flush; - wire [0:`THREADS-1] ex2_xucr0_flush; - wire [64-`GPR_WIDTH:63] ex3_tspr_rt; - wire [64-`GPR_WIDTH:63] ex3_cspr_rt; - wire [0:`THREADS-1] ex3_tid; - wire [64-`GPR_WIDTH:63] ex2_rt; - wire [64-`GPR_WIDTH:63] ex2_rt_inj; - wire llunmasked; - wire llmasked; - wire llpulse; - wire llpres; - wire llpri_inc; - wire [0:`THREADS-1] llmask; - wire [0:`THREADS-1] pm_wake_up; - wire [0:3] ccr0_we; - wire [0:`THREADS-1] ccr0_wen, ccr0_we_di; - wire dbell_pir_match; - wire [0:`THREADS-1] dbell_pir_thread; - wire [0:`THREADS-1] spr_ccr0_we_rev; - wire [0:`THREADS-1] spr_tens_ten_rev; - wire [0:`THREADS-1] set_dbell; - wire [0:`THREADS-1] clr_dbell; - wire [0:`THREADS-1] set_cdbell; - wire [0:`THREADS-1] clr_cdbell; - wire [0:`THREADS-1] set_gdbell; - wire [0:`THREADS-1] clr_gdbell; - wire [0:`THREADS-1] set_gcdbell; - wire [0:`THREADS-1] clr_gcdbell; - wire [0:`THREADS-1] set_gmcdbell; - wire [0:`THREADS-1] clr_gmcdbell; - wire tb_update_pulse; - wire [0:`THREADS-1] spr_tensr; - wire ex3_is_mtspr; - wire [0:63] tb_q; - wire [0:`THREADS-1] crit_mask; - wire [0:`THREADS-1] base_mask; - wire [0:`THREADS-1] dec_mask; - wire [0:`THREADS-1] fit_mask; - wire [0:`THREADS-1] ex3_wait; - wire [38:63] xucr0_di; - wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] ex2_eccgen_data; - wire [64:72-(64/`GPR_WIDTH)] ex2_eccgen_syn; - wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn; - wire [64:72-(64/`GPR_WIDTH)] ex3_eccchk_syn_b; - wire ex2_is_mfsspr_b; - wire encorr; - wire ex3_sprg_ce, ex3_sprg_ue; - wire ex2_aspr_we; - wire [64-`GPR_WIDTH:63] ex4_aspr_rt; - wire [0:`THREADS-1] quiesce_ctr_zero_b; - wire [0:`THREADS-1] quiesce_b_q; - wire [0:`THREADS-1] running; - wire timer_update_int; - wire [0:4] exx_act; - wire [1:3] exx_act_data; - wire ex0_act; - wire ex2_inj_ecc; - wire [32:47] version; - wire [48:63] revision; - wire [0:`THREADS-1] instr_trace_tid; - wire [0:`THREADS-1] ex3_val; - wire [0:3] ex2_aspr_addr; - wire ex1_spr_rd; - wire ex1_spr_wr; - wire flush_int; - wire ex2_flush; - wire ex3_flush; - wire ex1_valid; - wire ex1_is_wrtee; - wire ex1_is_wrteei; - wire ord_ready; - wire ex2_msr_pr; - wire ex2_msr_gs; - wire timer_div_act; - wire [0:4] timer_div; - wire ex3_spr_we; - wire ex2_aspr_addr_act; - wire ex3_rt_act; - wire [0:`THREADS-1] ex2_np1_flush; - wire power_savings_en, power_savings_on; - (* analysis_not_referenced="true" *) - wire unused_do_bits; - - // Data - wire [0:1] spr_ccr0_pme; - wire [0:3] spr_ccr0_we; - wire spr_ccr2_en_dcr_int; - wire spr_ccr2_en_pc; - wire spr_ccr4_en_dnh; - wire [0:`THREADS-1] spr_tens_ten; - wire [0:4] spr_xucr0_clkg_ctl; - wire spr_xucr0_tcs; - wire [0:1] spr_xucr4_tcd; - wire [62:63] ex3_ccr0_di; - wire [40:63] ex3_ccr1_di; - wire [32:63] ex3_ccr2_di; - wire [63:63] ex3_ccr4_di; - wire [32:63] ex3_tbl_di; - wire [32:63] ex3_tbu_di; - wire [64-(`THREADS):63] ex3_tens_di; - wire [32:63] ex3_xesr1_di; - wire [32:63] ex3_xesr2_di; - wire [38:63] ex3_xucr0_di; - wire [60:63] ex3_xucr4_di; - wire - ex1_gsprg0_re , ex1_gsprg1_re , ex1_gsprg2_re , ex1_gsprg3_re - , ex1_sprg0_re , ex1_sprg1_re , ex1_sprg2_re , ex1_sprg3_re - , ex1_sprg4_re , ex1_sprg5_re , ex1_sprg6_re , ex1_sprg7_re - , ex1_sprg8_re , ex1_vrsave_re ; - wire - ex1_gsprg0_rdec, ex1_gsprg1_rdec, ex1_gsprg2_rdec, ex1_gsprg3_rdec - , ex1_sprg0_rdec , ex1_sprg1_rdec , ex1_sprg2_rdec , ex1_sprg3_rdec - , ex1_sprg4_rdec , ex1_sprg5_rdec , ex1_sprg6_rdec , ex1_sprg7_rdec - , ex1_sprg8_rdec , ex1_vrsave_rdec; - wire ex2_sprg8_re; - wire - ex2_ccr0_re , ex2_ccr1_re , ex2_ccr2_re , ex2_ccr4_re - , ex2_cir_re , ex2_pir_re , ex2_pvr_re , ex2_tb_re - , ex2_tbu_re , ex2_tenc_re , ex2_tens_re , ex2_tensr_re - , ex2_tir_re , ex2_xesr1_re , ex2_xesr2_re , ex2_xucr0_re - , ex2_xucr4_re ; - wire - ex2_acop_re , ex2_axucr0_re , ex2_cpcr0_re , ex2_cpcr1_re - , ex2_cpcr2_re , ex2_cpcr3_re , ex2_cpcr4_re , ex2_cpcr5_re - , ex2_dac1_re , ex2_dac2_re , ex2_dac3_re , ex2_dac4_re - , ex2_dbcr2_re , ex2_dbcr3_re , ex2_dscr_re , ex2_dvc1_re - , ex2_dvc2_re , ex2_eheir_re , ex2_eplc_re , ex2_epsc_re - , ex2_eptcfg_re , ex2_givpr_re , ex2_hacop_re , ex2_iac1_re - , ex2_iac2_re , ex2_iac3_re , ex2_iac4_re , ex2_immr_re - , ex2_imr_re , ex2_iucr0_re , ex2_iucr1_re , ex2_iucr2_re - , ex2_iudbg0_re , ex2_iudbg1_re , ex2_iudbg2_re , ex2_iulfsr_re - , ex2_iullcr_re , ex2_ivpr_re , ex2_lesr1_re , ex2_lesr2_re - , ex2_lper_re , ex2_lperu_re , ex2_lpidr_re , ex2_lratcfg_re - , ex2_lratps_re , ex2_lsucr0_re , ex2_mas0_re , ex2_mas0_mas1_re - , ex2_mas1_re , ex2_mas2_re , ex2_mas2u_re , ex2_mas3_re - , ex2_mas4_re , ex2_mas5_re , ex2_mas5_mas6_re, ex2_mas6_re - , ex2_mas7_re , ex2_mas7_mas3_re, ex2_mas8_re , ex2_mas8_mas1_re - , ex2_mmucfg_re , ex2_mmucr0_re , ex2_mmucr1_re , ex2_mmucr2_re - , ex2_mmucr3_re , ex2_mmucsr0_re , ex2_pesr_re , ex2_pid_re - , ex2_ppr32_re , ex2_sramd_re , ex2_tlb0cfg_re , ex2_tlb0ps_re - , ex2_xucr2_re , ex2_xudbg0_re , ex2_xudbg1_re , ex2_xudbg2_re ; - wire - ex2_ccr0_we , ex2_ccr1_we , ex2_ccr2_we , ex2_ccr4_we - , ex2_tbl_we , ex2_tbu_we , ex2_tenc_we , ex2_tens_we - , ex2_trace_we , ex2_xesr1_we , ex2_xesr2_we , ex2_xucr0_we - , ex2_xucr4_we ; - wire - ex2_acop_we , ex2_axucr0_we , ex2_cpcr0_we , ex2_cpcr1_we - , ex2_cpcr2_we , ex2_cpcr3_we , ex2_cpcr4_we , ex2_cpcr5_we - , ex2_dac1_we , ex2_dac2_we , ex2_dac3_we , ex2_dac4_we - , ex2_dbcr2_we , ex2_dbcr3_we , ex2_dscr_we , ex2_dvc1_we - , ex2_dvc2_we , ex2_eheir_we , ex2_eplc_we , ex2_epsc_we - , ex2_givpr_we , ex2_hacop_we , ex2_iac1_we , ex2_iac2_we - , ex2_iac3_we , ex2_iac4_we , ex2_immr_we , ex2_imr_we - , ex2_iucr0_we , ex2_iucr1_we , ex2_iucr2_we , ex2_iudbg0_we - , ex2_iulfsr_we , ex2_iullcr_we , ex2_ivpr_we , ex2_lesr1_we - , ex2_lesr2_we , ex2_lper_we , ex2_lperu_we , ex2_lpidr_we - , ex2_lsucr0_we , ex2_mas0_we , ex2_mas0_mas1_we, ex2_mas1_we - , ex2_mas2_we , ex2_mas2u_we , ex2_mas3_we , ex2_mas4_we - , ex2_mas5_we , ex2_mas5_mas6_we, ex2_mas6_we , ex2_mas7_we - , ex2_mas7_mas3_we, ex2_mas8_we , ex2_mas8_mas1_we, ex2_mmucr0_we - , ex2_mmucr1_we , ex2_mmucr2_we , ex2_mmucr3_we , ex2_mmucsr0_we - , ex2_pesr_we , ex2_pid_we , ex2_ppr32_we , ex2_xucr2_we - , ex2_xudbg0_we ; - wire - ex2_gsprg0_we , ex2_gsprg1_we , ex2_gsprg2_we , ex2_gsprg3_we - , ex2_sprg0_we , ex2_sprg1_we , ex2_sprg2_we , ex2_sprg3_we - , ex2_sprg4_we , ex2_sprg5_we , ex2_sprg6_we , ex2_sprg7_we - , ex2_sprg8_we , ex2_vrsave_we ; - wire - ex2_ccr0_rdec , ex2_ccr1_rdec , ex2_ccr2_rdec , ex2_ccr4_rdec - , ex2_cir_rdec , ex2_pir_rdec , ex2_pvr_rdec , ex2_tb_rdec - , ex2_tbu_rdec , ex2_tenc_rdec , ex2_tens_rdec , ex2_tensr_rdec - , ex2_tir_rdec , ex2_xesr1_rdec , ex2_xesr2_rdec , ex2_xucr0_rdec - , ex2_xucr4_rdec ; - wire - ex2_acop_rdec , ex2_axucr0_rdec, ex2_cpcr0_rdec , ex2_cpcr1_rdec - , ex2_cpcr2_rdec , ex2_cpcr3_rdec , ex2_cpcr4_rdec , ex2_cpcr5_rdec - , ex2_dac1_rdec , ex2_dac2_rdec , ex2_dac3_rdec , ex2_dac4_rdec - , ex2_dbcr2_rdec , ex2_dbcr3_rdec , ex2_dscr_rdec , ex2_dvc1_rdec - , ex2_dvc2_rdec , ex2_eheir_rdec , ex2_eplc_rdec , ex2_epsc_rdec - , ex2_eptcfg_rdec, ex2_givpr_rdec , ex2_hacop_rdec , ex2_iac1_rdec - , ex2_iac2_rdec , ex2_iac3_rdec , ex2_iac4_rdec , ex2_immr_rdec - , ex2_imr_rdec , ex2_iucr0_rdec , ex2_iucr1_rdec , ex2_iucr2_rdec - , ex2_iudbg0_rdec, ex2_iudbg1_rdec, ex2_iudbg2_rdec, ex2_iulfsr_rdec - , ex2_iullcr_rdec, ex2_ivpr_rdec , ex2_lesr1_rdec , ex2_lesr2_rdec - , ex2_lper_rdec , ex2_lperu_rdec , ex2_lpidr_rdec , ex2_lratcfg_rdec - , ex2_lratps_rdec, ex2_lsucr0_rdec, ex2_mas0_rdec , ex2_mas0_mas1_rdec - , ex2_mas1_rdec , ex2_mas2_rdec , ex2_mas2u_rdec , ex2_mas3_rdec - , ex2_mas4_rdec , ex2_mas5_rdec , ex2_mas5_mas6_rdec, ex2_mas6_rdec - , ex2_mas7_rdec , ex2_mas7_mas3_rdec, ex2_mas8_rdec , ex2_mas8_mas1_rdec - , ex2_mmucfg_rdec, ex2_mmucr0_rdec, ex2_mmucr1_rdec, ex2_mmucr2_rdec - , ex2_mmucr3_rdec, ex2_mmucsr0_rdec, ex2_pesr_rdec , ex2_pid_rdec - , ex2_ppr32_rdec , ex2_sramd_rdec , ex2_tlb0cfg_rdec, ex2_tlb0ps_rdec - , ex2_xucr2_rdec , ex2_xudbg0_rdec, ex2_xudbg1_rdec, ex2_xudbg2_rdec; - wire - ex2_gsprg0_rdec, ex2_gsprg1_rdec, ex2_gsprg2_rdec, ex2_gsprg3_rdec - , ex2_sprg0_rdec , ex2_sprg1_rdec , ex2_sprg2_rdec , ex2_sprg3_rdec - , ex2_sprg4_rdec , ex2_sprg5_rdec , ex2_sprg6_rdec , ex2_sprg7_rdec - , ex2_sprg8_rdec , ex2_vrsave_rdec; - wire - ex2_ccr0_wdec , ex2_ccr1_wdec , ex2_ccr2_wdec , ex2_ccr4_wdec - , ex2_tbl_wdec , ex2_tbu_wdec , ex2_tenc_wdec , ex2_tens_wdec - , ex2_trace_wdec , ex2_xesr1_wdec , ex2_xesr2_wdec , ex2_xucr0_wdec - , ex2_xucr4_wdec ; - wire - ex2_gsprg0_wdec, ex2_gsprg1_wdec, ex2_gsprg2_wdec, ex2_gsprg3_wdec - , ex2_sprg0_wdec , ex2_sprg1_wdec , ex2_sprg2_wdec , ex2_sprg3_wdec - , ex2_sprg4_wdec , ex2_sprg5_wdec , ex2_sprg6_wdec , ex2_sprg7_wdec - , ex2_sprg8_wdec , ex2_vrsave_wdec; - wire - ex2_acop_wdec , ex2_axucr0_wdec, ex2_cpcr0_wdec , ex2_cpcr1_wdec - , ex2_cpcr2_wdec , ex2_cpcr3_wdec , ex2_cpcr4_wdec , ex2_cpcr5_wdec - , ex2_dac1_wdec , ex2_dac2_wdec , ex2_dac3_wdec , ex2_dac4_wdec - , ex2_dbcr2_wdec , ex2_dbcr3_wdec , ex2_dscr_wdec , ex2_dvc1_wdec - , ex2_dvc2_wdec , ex2_eheir_wdec , ex2_eplc_wdec , ex2_epsc_wdec - , ex2_givpr_wdec , ex2_hacop_wdec , ex2_iac1_wdec , ex2_iac2_wdec - , ex2_iac3_wdec , ex2_iac4_wdec , ex2_immr_wdec , ex2_imr_wdec - , ex2_iucr0_wdec , ex2_iucr1_wdec , ex2_iucr2_wdec , ex2_iudbg0_wdec - , ex2_iulfsr_wdec, ex2_iullcr_wdec, ex2_ivpr_wdec , ex2_lesr1_wdec - , ex2_lesr2_wdec , ex2_lper_wdec , ex2_lperu_wdec , ex2_lpidr_wdec - , ex2_lsucr0_wdec, ex2_mas0_wdec , ex2_mas0_mas1_wdec, ex2_mas1_wdec - , ex2_mas2_wdec , ex2_mas2u_wdec , ex2_mas3_wdec , ex2_mas4_wdec - , ex2_mas5_wdec , ex2_mas5_mas6_wdec, ex2_mas6_wdec , ex2_mas7_wdec - , ex2_mas7_mas3_wdec, ex2_mas8_wdec , ex2_mas8_mas1_wdec, ex2_mmucr0_wdec - , ex2_mmucr1_wdec, ex2_mmucr2_wdec, ex2_mmucr3_wdec, ex2_mmucsr0_wdec - , ex2_pesr_wdec , ex2_pid_wdec , ex2_ppr32_wdec , ex2_xucr2_wdec - , ex2_xudbg0_wdec; - wire - ex3_ccr0_we , ex3_ccr1_we , ex3_ccr2_we , ex3_ccr4_we - , ex3_tbl_we , ex3_tbu_we , ex3_tenc_we , ex3_tens_we - , ex3_xesr1_we , ex3_xesr2_we , ex3_xucr0_we , ex3_xucr4_we ; - wire - ex3_ccr0_wdec , ex3_ccr1_wdec , ex3_ccr2_wdec , ex3_ccr4_wdec - , ex3_tbl_wdec , ex3_tbu_wdec , ex3_tenc_wdec , ex3_tens_wdec - , ex3_xesr1_wdec , ex3_xesr2_wdec , ex3_xucr0_wdec , ex3_xucr4_wdec ; - wire - ccr0_act , ccr1_act , ccr2_act , ccr4_act - , cir_act , pir_act , pvr_act , tb_act - , tbl_act , tbu_act , tenc_act , tens_act - , tensr_act , tir_act , xesr1_act , xesr2_act - , xucr0_act , xucr4_act ; - wire [0:64] - ccr0_do , ccr1_do , ccr2_do , ccr4_do - , cir_do , pir_do , pvr_do , tb_do - , tbl_do , tbu_do , tenc_do , tens_do - , tensr_do , tir_do , xesr1_do , xesr2_do - , xucr0_do , xucr4_do ; - - - wire [64-`GPR_WIDTH:64+8-(64/`GPR_WIDTH)] ex3_spr_wd; - - wire xu_iu_ex3_sprg_ce, xu_iu_ex3_sprg_ue; - assign xu_iu_ex3_sprg_ce = 1'b0; - assign xu_iu_ex3_sprg_ue = 1'b0; - - //!! Bugspray Include: xu_spr_cspr; - //## figtree_source: xu_spr_cspr.fig; - - assign tidn = {64{1'b0}}; - - assign cspr_xucr0_clkg_ctl = spr_xucr0_clkg_ctl; - - assign ex1_aspr_act_d = ex0_act; - - assign ex0_act = |ex0_val_q & rv_xu_ex0_ord; - assign exx_act_d[1:4] = exx_act[0:3]; - - assign exx_act[0] = ex0_act; - assign exx_act[1] = exx_act_q[1]; - assign exx_act[2] = exx_act_q[2]; - assign exx_act[3] = exx_act_q[3] | ex3_spr_we_q; - assign exx_act[4] = exx_act_q[4]; - - // Needs to be on for loads and stores, for the DEAR... - assign exx_act_data[1] = exx_act[1]; - assign exx_act_data[2] = exx_act[2]; - assign exx_act_data[3] = exx_act[3]; - - assign cspr_tspr_rf1_act = exx_act[0]; - - // Decode - assign ex1_opcode_is_19 = ex1_instr_q[0:5] == 6'b010011; - assign ex1_opcode_is_31 = ex1_instr_q[0:5] == 6'b011111; - assign ex1_is_mfspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101010011); // 31/339 - assign ex1_is_mtspr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0111010011); // 31/467 - assign ex1_is_mfmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0001010011); // 31/083 - assign ex1_is_mtmsr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010010); // 31/146 - assign ex1_is_mftb = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0101110011); // 31/371 - assign ex1_is_wait = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000111110); // 31/062 - assign ex1_is_msgclr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0011101110); // 31/238 - assign ex1_is_wrtee = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010000011); // 31/131 - assign ex1_is_wrteei = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010100011); // 31/163 - assign ex1_is_mfcr = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0000010011); // 31/19 - assign ex1_is_mtcrf = (ex1_opcode_is_31 & ex1_instr_q[21:30] == 10'b0010010000); // 31/144 - assign ex1_is_dnh = (ex1_opcode_is_19 & ex1_instr_q[21:30] == 10'b0011000110); // 19/198 - - assign ex1_priv_instr = ex1_is_mtmsr | ex1_is_mfmsr | ex1_is_wrtee | ex1_is_wrteei | ex1_is_msgclr; - - assign ex1_hypv_instr = ex1_is_msgclr; - - assign ex1_spr_rd = ex1_is_mfspr | ex1_is_mfmsr | ex1_is_mftb; - assign ex1_spr_wr = ex1_is_mtspr | ex1_is_mtmsr | ex1_is_wrtee | - ex1_is_wrteei | ex1_is_msgclr | ex1_is_wait | ex1_is_dnh; - - assign ex2_is_mtmsr_d = ex1_is_mtmsr | ex1_is_wrtee | ex1_is_wrteei; - - assign rv2_val = rv_xu_vld & (~flush_q); - assign ex0_val = ex0_val_q & (~flush_q) & {`THREADS{rv_xu_ex0_ord}}; - assign ex1_val = ex1_val_q & (~flush_q); - assign ex2_val = ex2_val_q & (~flush_q); - assign ex3_val = ex3_val_q & (~flush_q); - - assign ex1_valid = |(ex1_val); - - assign ex2_flush = |(ex2_tid & flush_q) & (ex2_val_rd_q | ex2_val_wr_q); - assign ex3_flush = |(ex3_tid & flush_q) & (ex3_val_rd_q | ex2_val_wr_q); - - // For CPCRs wait until quiesce - - wire ord_quiesce = &lsu_quiesce_q | ~(ex2_is_mtspr_q & (ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec)) | ex2_is_wait_q; - - // On exception, do not wait for ord_ready. No write will occur. - assign ord_ready = xu_spr_ord_ready_q | flush_int; - - assign flush_int = ex3_hypv_spr_q | ex3_illeg_spr_q | ex3_priv_spr_q; - - assign ex2_val_rd_d = ((ex1_valid & ex1_spr_rd) | ex2_val_rd_q) & ~ex2_flush & ~ex2_val_rd_q; - assign ex2_val_wr_d = ((ex1_valid & ex1_spr_wr) | (ex2_val_wr_q & ~ex2_flush & ~(ord_ready & ord_quiesce))); - - assign ex3_val_rd_d = ex2_val_rd_q & ~ex2_flush; - - assign ex3_spr_we_d = ex2_val_wr_q & ~ex2_flush & ord_ready & ord_quiesce; - assign ex3_spr_we = ex3_spr_we_q & ~flush_int; - assign cspr_tspr_ex3_spr_we = ex3_tid & {`THREADS{ex3_spr_we}}; - - assign ex3_sspr_val = ((ex3_spr_we & ex3_sspr_wr_val_q) | (ex3_val_rd_q & ex3_sspr_rd_val_q)) & (~(ex3_flush | flush_int)); - - assign spr_xu_ord_read_done_d = ex3_spr_we_q & (~ex3_sspr_wr_val_q | flush_int) & ~ex3_flush; - assign spr_xu_ord_write_done_d = ex3_val_rd_q & (~ex3_sspr_rd_val_q | flush_int) & ~ex3_flush; - - assign spr_xu_ord_write_done = spr_xu_ord_write_done_q & ~ex3_flush; - assign spr_xu_ord_read_done = spr_xu_ord_read_done_q & ~ex3_flush; - - assign ex1_instr = ex1_instr_q[11:20]; - assign ex2_instr_d = ex1_instr_q[11:20] & {10{(ex1_is_mfspr | ex1_is_mtspr | ex1_is_wrteei | ex1_is_mftb)}}; - assign ex2_instr = ex2_instr_q[11:20]; - assign ex3_instr_d = ex2_instr_q; // or gate(ex2_dcrn_q,ex2_dcr_val_q); - assign ex3_instr = ex3_instr_q[11:20]; - assign ex3_spr_wd = ex3_rt_q; - assign ex3_spr_wd_out = ex3_rt_q; - assign ex3_is_mtspr = ex3_is_mtspr_q; - assign ex2_ifar = ex2_ifar_q; - - assign ex3_wait = ex3_tid & {`THREADS{(ex3_spr_we & ex3_wait_q & ex3_wait_flush_q)}}; - - assign spr_tens_ten_rev = reverse_threads(spr_tens_ten); - assign spr_tensr = spr_tens_ten | reverse_threads(running); - assign spr_ccr0_we_rev = reverse_threads(spr_ccr0_we[4-`THREADS:3]); - -// Run State -assign quiesce_b_q = ~(quiesce_q & ~running_q); -assign quiesce_d = iu_quiesce_q & iu_icache_quiesce_q & lsu_quiesce_q & mm_quiesce_q & bx_quiesce_q; - -assign quiesced_d = quiesce_q & ~quiesce_ctr_zero_b; - -assign xu_pc_running = running; - -assign running = running_q | ~quiesced_q; -assign running_d = ~(iu_xu_stop | spr_ccr0_we_rev) & spr_tens_ten_rev; -assign iu_run_thread_d = (running_q & llmask) & ~{`THREADS{power_savings_on}}; -assign xu_iu_run_thread = iu_run_thread_q; - -assign ex1_tenc_we = (ex1_instr_q[11:20] == 10'b1011101101); // 439 -assign ex1_ccr0_we = (ex1_instr_q[11:20] == 10'b1000011111); // 1008 - -// Power Management Control -assign xu_pc_spr_ccr0_we = spr_ccr0_we_rev & quiesced_q; -assign xu_pc_spr_ccr0_pme = spr_ccr0_pme; - -assign power_savings_on = (power_savings_en | power_savings_on_q); - -assign power_savings_on_d = power_savings_on & ~(~pc_xu_pm_hold_thread & pc_xu_pm_hold_thread_q); - -assign power_savings_en = ^spr_ccr0_pme & // Power Management Enabled - &spr_ccr0_we_rev & // Wait Enable = 1 - &quiesced_q; // Core Quiesced - -// Wakeup Condition Masking - -// Reset the mask when running -// Set the mask on a valid wait instruction -// Otherwise hold - -// WAIT[WC](0) = Resume on Imp. Specific -// WAIT[WC](1) = Resume on no reservation -generate - begin : pm_wake_up_gen - genvar t; - for (t=0;t<=`THREADS-1;t=t+1) - begin : thread - assign waitimpl_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[9] : - (pm_wake_up[t] == 1'b1) ? 1'b0 : - waitimpl_val_q[t]; - - assign waitrsv_val_d[t] = (ex3_wait[t] == 1'b1) ? ex3_wait_wc_q[10] : - (pm_wake_up[t] == 1'b1) ? 1'b0 : - waitrsv_val_q[t]; - - // Block interrupts (mask=0) if: - // Stopped via (HW Debug and pc_xu_extirpts_dis_on_stop)=1 - // Stopped via TEN=0 - // Stopped via CCR0=1, unless overriden by CCR1=1 (and wait, if applicable) - assign crit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[60-6*t]))); - assign base_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[61-6*t]))); - assign dec_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[62-6*t]))); - assign fit_mask[t] = (~(ext_dbg_dis_q[t] | ~spr_tens_ten_rev[t] | (spr_ccr0_we_rev[t] & ~ccr1_q[63-6*t]))); - - assign cspr_tspr_crit_mask[t] = crit_mask[t]; - assign cspr_tspr_ext_mask[t] = base_mask[t]; - assign cspr_tspr_dec_mask[t] = dec_mask[t]; - assign cspr_tspr_fit_mask[t] = fit_mask[t]; - assign cspr_tspr_wdog_mask[t] = crit_mask[t]; - assign cspr_tspr_udec_mask[t] = dec_mask[t]; - assign cspr_tspr_perf_mask[t] = base_mask[t]; - - // Generate Conditional Wait flush - // Reservation Exists - assign ex2_wait_flush[t] = ex2_tid[t] & ex2_is_wait_q & // Unconditional Wait - ((ex2_wait_wc_q == 2'b00) | (ex2_wait_wc_q == 2'b01 & an_ac_reservation_vld_q[t] & (~ccr1_q[58-6*t])) | // Reservation Exists - (ex2_wait_wc_q == 2'b10 & an_ac_sleep_en_q[t] & (~ccr1_q[59-6*t]))); // Impl. Specific Exists (Sleep enabled) - - - assign ex2_ccr0_flush[t] = ex2_is_mtspr_q & ex2_ccr0_we_q & xu_spr_ex2_rs1[55-t] & xu_spr_ex2_rs1[63-t]; - - assign ex2_tenc_flush[t] = ex2_is_mtspr_q & ex2_tenc_we_q & xu_spr_ex2_rs1[63-t]; - - assign ex2_xucr0_flush[t] = ex2_is_mtspr_q & ex2_xucr0_wdec; - end - end - endgenerate - - assign cspr_tspr_sleep_mask = ~power_savings_on_q; - - assign pm_wake_up = (~an_ac_reservation_vld_q & waitrsv_val_q) | - (~an_ac_sleep_en_q & waitimpl_val_q) | - tspr_cspr_pm_wake_up | - dbell_interrupt_q | - cdbell_interrupt_q | - gdbell_interrupt_q | - gcdbell_interrupt_q | - gmcdbell_interrupt_q; - - // Debug Timer Disable - assign tb_dbg_dis_d = &iu_xu_stop & pc_xu_timebase_dis_on_stop; - assign dec_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_decrem_dis_on_stop}}; - assign ext_dbg_dis_d = iu_xu_stop & {`THREADS{pc_xu_extirpts_dis_on_stop}}; - - // LiveLock Priority - assign cspr_tspr_llen = running_q; - assign cspr_tspr_llpri = llpri_q; - assign llpres = |(tspr_cspr_lldet); - assign llunmasked = |( llpri_q & tspr_cspr_lldet); - assign llmasked = |(~llpri_q & tspr_cspr_lldet); - assign llpulse = |( llpri_q & tspr_cspr_llpulse); - - // Increment the hang priority if: - // There is a hang present, but the priority is masking it. - // There is another hang present, and there is a hang pulse. - assign llpri_inc = (llpres & (~llunmasked)) | (llpulse & llmasked & llunmasked); - - generate - if (`THREADS == 1) - begin : tid1 - assign llpri_d = 1'b1; - assign ex0_tid = 2'b00; - assign ex2_tid = 1'b1; - assign ex3_tid = 1'b1; - assign instr_trace_tid = 1'b1; - end - endgenerate - generate - if (`THREADS == 2) - begin : tid2 - assign llpri_d = {llpri_q[`THREADS - 1], llpri_q[0:`THREADS - 2]}; - assign ex0_tid = {1'b0, ex0_val_q[1]}; - assign ex2_tid[0] = ~ex2_tid_q[0] & ~ex2_tid_q[1]; - assign ex2_tid[1] = ~ex2_tid_q[0] & ex2_tid_q[1]; - assign ex3_tid[0] = ~ex3_tid_q[0] & ~ex3_tid_q[1]; - assign ex3_tid[1] = ~ex3_tid_q[0] & ex3_tid_q[1]; - assign instr_trace_tid[0] = ~instr_trace_tid_q[0] & ~instr_trace_tid_q[1]; - assign instr_trace_tid[1] = ~instr_trace_tid_q[0] & instr_trace_tid_q[1]; - end - endgenerate - -assign llmask = (llpri_q & tspr_cspr_lldet) | ~{`THREADS{llpres}}; - -assign instr_trace_mode = instr_trace_tid & {`THREADS{instr_trace_mode_q}}; - -assign ex1_msr_gs_d = {1{|(tspr_msr_gs & ex0_val_q)}}; - -assign cspr_tspr_ram_active = ram_active_q; - -assign cspr_tspr_msrovride_en = msrovride_enab; -assign msrovride_enab = ram_active_q & {`THREADS{msrovride_enab_q}}; - -assign xu_iu_msrovride_enab = msrovride_enab_2_q | msrovride_enab_3_q; - -// Perf Events - -assign perf_event_en_d = ( tspr_msr_pr & {`THREADS{pc_xu_event_count_mode[0]}}) | // User - (~tspr_msr_pr & tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[1]}}) | // Guest Supervisor - (~tspr_msr_pr & ~tspr_msr_gs & {`THREADS{pc_xu_event_count_mode[2]}}) ; // Hypervisor - - -wire [0:16*`THREADS-1] perf_events; -wire [0:0] core_event; - generate - begin : perf_count - genvar t; - for (t = 0; t <= `THREADS - 1; t = t + 1) - begin : thread - assign core_event = perf_event_en_q[t] & running[t]; - - assign perf_events[0+16*t] = core_event[0]; - assign perf_events[1+16*t] = perf_event_en_q[t] & running[t]; - assign perf_events[2+16*t] = perf_event_en_q[t] & tb_act_q; - assign perf_events[3+16*t] = perf_event_en_q[t] & waitrsv_val_q[t]; - assign perf_events[4+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[0+3*t]; - assign perf_events[5+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[1+3*t]; - assign perf_events[6+16*t] = perf_event_en_q[t] & tspr_cspr_async_int[2+3*t]; - assign perf_events[7+16*t] = perf_event_en_q[t] & (cpl_dbell_taken_q[t] | cpl_cdbell_taken_q[t] | cpl_gdbell_taken_q[t] | cpl_gcdbell_taken_q[t] | cpl_gmcdbell_taken_q[t]); - assign perf_events[8+16*t] = perf_event_en_q[t] & div_spr_running[t]; - assign perf_events[9+16*t] = perf_event_en_q[t] & mul_spr_running[t]; - assign perf_events[10+16*t:15+16*t] = 6'd0; - - tri_event_mux1t #(.EVENTS_IN(16),.EVENTS_OUT(4)) perf_mux ( - .unit_events_in(perf_events[1+16*t:15+16*t]), - .select_bits(xesr1_q[32+16*t:47+16*t]), - .event_bus_out(perf_event_bus_d[0+4*t:3+4*t]), - .event_bus_in(xu_event_bus_in[0+4*t:3+4*t]), - .vd(vdd),.gd(gnd)); - - end - end - endgenerate - assign xu_event_bus_out = perf_event_bus_q; - assign spr_xesr1 = xesr1_q; - assign spr_xesr2 = xesr2_q; - assign perf_event_en = perf_event_en_q; - - // SPR Input Control - // CIR - assign cir_act = 1'b0; - - // CCR0 - // CCR0[PME] - assign ccr0_act = ex3_ccr0_we; - assign ccr0_d = ex3_ccr0_di; - - // CCR0[WE] - // Generate Bit Mask - assign ccr0_wen = ex3_spr_wd[56-`THREADS:55] & {`THREADS{ex3_ccr0_we}}; - // Apply bit-Mask - assign ccr0_we_di = (ex3_spr_wd[64-`THREADS:63] & ccr0_wen[0:`THREADS-1]) | (ccr0_we_q[0:`THREADS-1] & (~ccr0_wen[0:`THREADS-1])); - // Update based upon wake-up - assign ccr0_we_d = (ccr0_we_di[0:`THREADS-1] | reverse_threads(ex3_wait[0:`THREADS-1])) & ~(reverse_threads(pm_wake_up[0:`THREADS-1])); - // Padded version - assign ccr0_we = {{4-`THREADS{1'b0}},ccr0_we_q}; - - - // CCR1 - assign ccr1_act = ex3_ccr1_we; - assign ccr1_d = ex3_ccr1_di; - - // CCR2 - assign ccr2_act = ex3_ccr2_we; - assign ccr2_d = ex3_ccr2_di; - - // CCR4 - assign ccr4_act = ex3_ccr4_we; - assign ccr4_d = ex3_ccr4_di; - - // PIR - assign pir_act = 1'b1; - - // PVR - assign pvr_act = 1'b1; - - assign version = {8'h00, spr_pvr_version_dc[8:15]}; - assign revision = {4'h0, spr_pvr_revision_dc[12:15], 4'h0, spr_pvr_revision_minor_dc[16:19]}; - - // TB - assign tb_update_pulse = (tb_update_pulse_q ^ tb_update_pulse_1_q); // Any Edge - - // Update on external signal selected by XUCR0[TCS] - assign timer_div_act = tb_update_enable_q & (tb_update_pulse | (~spr_xucr0_tcs)); - - assign timer_div_d = timer_div_q + 5'd1; - - assign timer_div = (timer_div_q ^ timer_div_d) & {5{timer_div_act}}; - - // Select timer clock divide - - assign timer_update_int = (spr_xucr4_tcd == 2'b00) ? timer_div[4] : - (spr_xucr4_tcd == 2'b01) ? timer_div[2] : - (spr_xucr4_tcd == 2'b10) ? timer_div[1] : - timer_div[0]; - assign timer_update = timer_update_q; - - // Not Stopped via HW DBG (if enabled) - assign tb_act_d = ~tb_dbg_dis_q & ~|tspr_cspr_freeze_timers & timer_update_int; // Timers not frozen due to debug event - - assign tb_act = tb_act_q; - assign tb_q = {tbu_q, tbl_q}; - assign tb = tb_q + 1; - - // TBL - assign tbl_act = tb_act | ex3_tbl_we; - assign tbl_d = (ex3_tbl_we == 1'b1) ? ex3_tbl_di : tb[32:63]; - - // TBU - assign tbu_act = tb_act | ex3_tbu_we; - assign tbu_d = (ex3_tbu_we == 1'b1) ? ex3_tbu_di : tb[0:31]; - - // TENC - assign tenc_act = 1'b1; - - // TENS - assign tens_act = ex3_tenc_we | ex3_tens_we; - assign tens_d = (ex3_tenc_we == 1'b1) ? (tens_q & ~ex3_tens_di) : (tens_q | ex3_tens_di); - - // TENSR - assign tensr_act = 1'b1; - - // TIR - assign tir_act = 1'b1; - - // XESR1 - assign xesr1_act = ex3_xesr1_we; - assign xesr1_d = ex3_xesr1_di; - - // XESR2 - assign xesr2_act = ex3_xesr2_we; - assign xesr2_d = ex3_xesr2_di; - - // XUCR0 - assign set_xucr0_cslc_d = lq_xu_spr_xucr0_cslc_xuop | lq_xu_spr_xucr0_cslc_binv; - assign set_xucr0_cul_d = lq_xu_spr_xucr0_cul; - assign set_xucr0_clo_d = lq_xu_spr_xucr0_clo; - - assign xucr0_act = ex3_xucr0_we | set_xucr0_cslc_q | set_xucr0_cul_q | set_xucr0_clo_q; - - assign xucr0_d = {xucr0_di[38:60], - (xucr0_di[61] | set_xucr0_cslc_q), - (xucr0_di[62] | set_xucr0_cul_q), - (xucr0_di[63] | set_xucr0_clo_q)}; - - assign xucr0_di = (ex3_xucr0_we == 1'b1) ? ex3_xucr0_di : xucr0_q; - - // XUCR4 - assign xucr4_act = ex3_xucr4_we; - assign xucr4_d = ex3_xucr4_di; - - // IO signal assignments - - // FIT LL WDOG - assign cspr_tspr_timebase_taps[8] = tbl_q[32 + 23]; // 9 x - assign cspr_tspr_timebase_taps[7] = tbl_q[32 + 11]; // 21 x - assign cspr_tspr_timebase_taps[6] = tbl_q[32 + 7]; // 25 x - assign cspr_tspr_timebase_taps[5] = tbl_q[32 + 21]; // 11 x x - assign cspr_tspr_timebase_taps[4] = tbl_q[32 + 17]; // 15 x x - assign cspr_tspr_timebase_taps[3] = tbl_q[32 + 13]; // 19 x x x - assign cspr_tspr_timebase_taps[2] = tbl_q[32 + 9]; // 23 x x x - assign cspr_tspr_timebase_taps[1] = tbl_q[32 + 5]; // 27 x x - assign cspr_tspr_timebase_taps[0] = tbl_q[32 + 1]; // 31 x - assign cspr_tspr_timebase_taps[9] = tbl_q[32 + 7]; // 29 x -- Replaced 1 for wdog - - assign cspr_tspr_ex2_tid = ex2_tid; - assign cspr_tspr_ex1_instr = ex1_instr_q; - assign cspr_tspr_dec_dbg_dis = dec_dbg_dis_q; - - assign reset_wd_complete = pc_xu_reset_wd_complete_q; - assign reset_3_complete = pc_xu_reset_3_complete_q; - assign reset_2_complete = pc_xu_reset_2_complete_q; - assign reset_1_complete = pc_xu_reset_1_complete_q; - - assign ex1_aspr_tid_d = ex0_tid; - - assign cspr_aspr_ex3_we = (ex3_spr_we & ex3_aspr_we_q) | |ex5_sprg_ce_q; - assign cspr_aspr_ex3_waddr = {ex3_aspr_addr_q, ex3_tid_q}; - assign cspr_aspr_ex1_re = ex1_aspr_re[1] & ex1_aspr_act_q; - assign cspr_aspr_ex1_raddr = {ex1_aspr_addr, ex1_aspr_tid_q}; - - assign xu_slowspr_val_out = ex4_sspr_val_q; - assign xu_slowspr_rw_out = (~ex3_is_mtspr_q); - assign xu_slowspr_etid_out = ex3_tid_q; - assign xu_slowspr_addr_out = {ex3_instr_q[16:20], ex3_instr_q[11:15]}; - assign xu_slowspr_data_out = ex3_spr_wd[64 - `GPR_WIDTH:63]; - - assign ac_an_dcr_act = 1'b0; - assign ac_an_dcr_val = 1'b0; - assign ac_an_dcr_read = 1'b0; - assign ac_an_dcr_user = 1'b0; - assign ac_an_dcr_etid = {2{1'b0}}; - assign ac_an_dcr_addr = {10{1'b0}}; - assign ac_an_dcr_data = {`GPR_WIDTH{1'b0}}; - - assign spr_dec_ex4_spr_hypv = ex4_hypv_spr_q; - assign spr_dec_ex4_spr_illeg = ex4_illeg_spr_q; - assign spr_dec_ex4_spr_priv = ex4_priv_spr_q; - assign spr_dec_ex4_np1_flush = ex4_np1_flush_q | ex4_wait_flush_q | (|ex4_sprg_ue); - - assign dbell_pir_match = (lq_xu_dbell_pirtag_q[50:61] == pir_do[51:62]); - - assign cspr_tspr_dbell_pirtag = lq_xu_dbell_pirtag_q; - - generate - begin : dbell - genvar t; - for (t=0;t<=`THREADS-1;t=t+1) - begin : thread - wire [0:1] tid = t; - - assign dbell_pir_thread[t] = lq_xu_dbell_pirtag_q[62:63] == tid; - - assign set_dbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00000 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); - assign set_cdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00001 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | (dbell_pir_match & dbell_pir_thread[t])); - assign set_gdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00010 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); - assign set_gcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00011 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); - assign set_gmcdbell[t] = lq_xu_dbell_val_q & lq_xu_dbell_type_q == 5'b00100 & lq_xu_dbell_lpid_match_q & (lq_xu_dbell_brdcast_q | tspr_cspr_gpir_match[t]); - - assign clr_dbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00000); - assign clr_cdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00001); - assign clr_gdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00010); - assign clr_gcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00011); - assign clr_gmcdbell[t] = ex3_spr_we & ex3_tid[t] & ex3_is_msgclr_q & (ex3_spr_wd[32:36] == 5'b00100); - end - end - endgenerate - - assign dbell_present_d = set_dbell | (dbell_present_q & ~(clr_dbell | cpl_dbell_taken_q)); - assign cdbell_present_d = set_cdbell | (cdbell_present_q & ~(clr_cdbell | cpl_cdbell_taken_q)); - assign gdbell_present_d = set_gdbell | (gdbell_present_q & ~(clr_gdbell | cpl_gdbell_taken_q)); - assign gcdbell_present_d = set_gcdbell | (gcdbell_present_q & ~(clr_gcdbell | cpl_gcdbell_taken_q)); - assign gmcdbell_present_d = set_gmcdbell | (gmcdbell_present_q & ~(clr_gmcdbell | cpl_gmcdbell_taken_q)); - - assign dbell_interrupt = dbell_present_q & base_mask & (tspr_msr_ee | tspr_msr_gs); - assign cdbell_interrupt = cdbell_present_q & crit_mask & (tspr_msr_ce | tspr_msr_gs); - assign gdbell_interrupt = gdbell_present_q & base_mask & tspr_msr_ee & tspr_msr_gs; - assign gcdbell_interrupt = gcdbell_present_q & crit_mask & tspr_msr_ce & tspr_msr_gs; - assign gmcdbell_interrupt = gmcdbell_present_q & crit_mask & tspr_msr_me & tspr_msr_gs; - - assign xu_iu_dbell_interrupt = ~{`THREADS{power_savings_on_q}} & dbell_interrupt_q; - assign xu_iu_cdbell_interrupt = ~{`THREADS{power_savings_on_q}} & cdbell_interrupt_q; - assign xu_iu_gdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gdbell_interrupt_q; - assign xu_iu_gcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gcdbell_interrupt_q; - assign xu_iu_gmcdbell_interrupt = ~{`THREADS{power_savings_on_q}} & gmcdbell_interrupt_q; - - // Debug - assign cspr_debug0 = {40{1'b0}}; - assign cspr_debug1 = {64{1'b0}}; - - // Array ECC Check - - assign ex3_aspr_rdata_d[64-`GPR_WIDTH] = aspr_cspr_ex2_rdata[64-`GPR_WIDTH]; - assign ex3_aspr_rdata_d[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)] = aspr_cspr_ex2_rdata[65-`GPR_WIDTH:72-(64/`GPR_WIDTH)]; - - assign ex3_eccchk_syn_b = ~ex3_eccchk_syn; - - - tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_rd_eccgen( - .din(ex3_aspr_rdata_q), - .syn(ex3_eccchk_syn) - ); - - - tri_eccchk #(.REGSIZE(`GPR_WIDTH)) xu_spr_eccchk( - .din(ex3_aspr_rdata_q[64-`GPR_WIDTH:63]), - .encorr(encorr), - .nsyn(ex3_eccchk_syn_b), - .corrd(ex3_corr_rdata), - .sbe(ex3_sprg_ce), - .ue(ex3_sprg_ue) - ); - - assign encorr = 1'b1; - - assign ex4_sprg_ue_d = (|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ue); - - assign ex4_sprg_ce_d = {`GPR_WIDTH/8+1{(|ex3_val_rd_q & |ex3_aspr_re_q & ex3_sprg_ce)}}; - - - tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ce_err_rpt( - .vd(vdd), - .gd(gnd), - .err_in(ex5_sprg_ce_q), - .err_out(xu_pc_err_sprg_ecc) - ); - - tri_direct_err_rpt #(.WIDTH(`THREADS)) xu_spr_cspr_ue_err_rpt( - .vd(vdd), - .gd(gnd), - .err_in(ex5_sprg_ue_q), - .err_out(xu_pc_err_sprg_ue) - ); - - assign ex4_aspr_rt[32:63] = ex4_corr_rdata_q[32:63] & {32{ex4_aspr_re_q[1]}}; - generate - if (`GPR_WIDTH > 32) - begin : aspr_rt - assign ex4_aspr_rt[64-`GPR_WIDTH:31] = ex4_corr_rdata_q[64-`GPR_WIDTH:31] & {`GPR_WIDTH-32{ex4_aspr_re_q[0]}}; - end - endgenerate - - `ifdef THREADS1 - assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt; - `else - assign ex3_tspr_rt = tspr_cspr_ex3_tspr_rt[0:`GPR_WIDTH-1] | tspr_cspr_ex3_tspr_rt[`GPR_WIDTH:2*`GPR_WIDTH-1]; - `endif - - assign ex3_cspr_rt = ex3_cspr_rt_q & {`GPR_WIDTH{(~((ex3_sspr_wr_val_q | ex3_sspr_rd_val_q)))}}; - - assign ex3_spr_rt = ex3_tspr_rt | ex3_cspr_rt; - - assign spr_xu_ex4_rd_data = ex4_spr_rt_q | ex4_aspr_rt; - - // Fast SPR Read - generate - if (a2mode == 0 & hvmode == 0) - begin : readmux_00 - assign ex2_cspr_rt = - (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | - (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | - (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | - (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | - (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | - (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | - (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | - (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | - (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | - (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | - (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | - (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | - (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | - (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | - (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | - (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | - (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); - end - endgenerate - generate - if (a2mode == 0 & hvmode == 1) - begin : readmux_01 - assign ex2_cspr_rt = - (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | - (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | - (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | - (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | - (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | - (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | - (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | - (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | - (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | - (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | - (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | - (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | - (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | - (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | - (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | - (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | - (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); - end - endgenerate - generate - if (a2mode == 1 & hvmode == 0) - begin : readmux_10 - assign ex2_cspr_rt = - (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | - (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | - (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | - (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | - (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | - (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | - (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | - (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | - (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | - (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | - (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | - (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | - (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | - (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | - (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | - (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | - (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); - end - endgenerate - generate - if (a2mode == 1 & hvmode == 1) - begin : readmux_11 - assign ex2_cspr_rt = - (ccr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr0_re }}) | - (ccr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr1_re }}) | - (ccr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr2_re }}) | - (ccr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_ccr4_re }}) | - (cir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_cir_re }}) | - (pir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pir_re }}) | - (pvr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_pvr_re }}) | - (tb_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tb_re }}) | - (tbu_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tbu_re }}) | - (tenc_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tenc_re }}) | - (tens_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tens_re }}) | - (tensr_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tensr_re }}) | - (tir_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_tir_re }}) | - (xesr1_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr1_re }}) | - (xesr2_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xesr2_re }}) | - (xucr0_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr0_re }}) | - (xucr4_do[65-`GPR_WIDTH:64] & {`GPR_WIDTH{ex2_xucr4_re }}); - end - endgenerate - - // Fast SPR Write - assign ex3_ccr0_wdec = (ex3_instr[11:20] == 10'b1000011111); // 1008 - assign ex3_ccr1_wdec = (ex3_instr[11:20] == 10'b1000111111); // 1009 - assign ex3_ccr2_wdec = (ex3_instr[11:20] == 10'b1001011111); // 1010 - assign ex3_ccr4_wdec = (ex3_instr[11:20] == 10'b1011011010); // 854 - assign ex3_tbl_wdec = (ex3_instr[11:20] == 10'b1110001000); // 284 - assign ex3_tbu_wdec = ((ex3_instr[11:20] == 10'b1110101000)); // 285 - assign ex3_tenc_wdec = (ex3_instr[11:20] == 10'b1011101101); // 439 - assign ex3_tens_wdec = (ex3_instr[11:20] == 10'b1011001101); // 438 - assign ex3_xesr1_wdec = (ex3_instr[11:20] == 10'b1011011100); // 918 - assign ex3_xesr2_wdec = (ex3_instr[11:20] == 10'b1011111100); // 919 - assign ex3_xucr0_wdec = (ex3_instr[11:20] == 10'b1011011111); // 1014 - assign ex3_xucr4_wdec = (ex3_instr[11:20] == 10'b1010111010); // 853 - assign ex3_ccr0_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr0_wdec; - assign ex3_ccr1_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr1_wdec; - assign ex3_ccr2_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr2_wdec; - assign ex3_ccr4_we = ex3_spr_we & ex3_is_mtspr & ex3_ccr4_wdec; - assign ex3_tbl_we = ex3_spr_we & ex3_is_mtspr & ex3_tbl_wdec; - assign ex3_tbu_we = ex3_spr_we & ex3_is_mtspr & ex3_tbu_wdec; - assign ex3_tenc_we = ex3_spr_we & ex3_is_mtspr & ex3_tenc_wdec; - assign ex3_tens_we = ex3_spr_we & ex3_is_mtspr & ex3_tens_wdec; - assign ex3_xesr1_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr1_wdec; - assign ex3_xesr2_we = ex3_spr_we & ex3_is_mtspr & ex3_xesr2_wdec; - assign ex3_xucr0_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr0_wdec; - assign ex3_xucr4_we = ex3_spr_we & ex3_is_mtspr & ex3_xucr4_wdec; - - // Array Read - assign ex1_gsprg0_rdec = (ex1_instr[11:20] == 10'b1000001011); // 368 - assign ex1_gsprg1_rdec = (ex1_instr[11:20] == 10'b1000101011); // 369 - assign ex1_gsprg2_rdec = (ex1_instr[11:20] == 10'b1001001011); // 370 - assign ex1_gsprg3_rdec = (ex1_instr[11:20] == 10'b1001101011); // 371 - assign ex1_sprg0_rdec = (ex1_instr[11:20] == 10'b1000001000); // 272 - assign ex1_sprg1_rdec = (ex1_instr[11:20] == 10'b1000101000); // 273 - assign ex1_sprg2_rdec = (ex1_instr[11:20] == 10'b1001001000); // 274 - assign ex1_sprg3_rdec = ((ex1_instr[11:20] == 10'b1001101000) | // 275 - (ex1_instr[11:20] == 10'b0001101000)); // 259 - assign ex1_sprg4_rdec = ((ex1_instr[11:20] == 10'b1010001000) | // 276 - (ex1_instr[11:20] == 10'b0010001000)); // 260 - assign ex1_sprg5_rdec = ((ex1_instr[11:20] == 10'b1010101000) | // 277 - (ex1_instr[11:20] == 10'b0010101000)); // 261 - assign ex1_sprg6_rdec = ((ex1_instr[11:20] == 10'b1011001000) | // 278 - (ex1_instr[11:20] == 10'b0011001000)); // 262 - assign ex1_sprg7_rdec = ((ex1_instr[11:20] == 10'b1011101000) | // 279 - (ex1_instr[11:20] == 10'b0011101000)); // 263 - assign ex1_sprg8_rdec = (ex1_instr[11:20] == 10'b1110010010); // 604 - assign ex1_vrsave_rdec = (ex1_instr[11:20] == 10'b0000001000); // 256 - assign ex1_gsprg0_re = (ex1_gsprg0_rdec | (ex1_sprg0_rdec & ex1_msr_gs_q[0])); - assign ex1_gsprg1_re = (ex1_gsprg1_rdec | (ex1_sprg1_rdec & ex1_msr_gs_q[0])); - assign ex1_gsprg2_re = (ex1_gsprg2_rdec | (ex1_sprg2_rdec & ex1_msr_gs_q[0])); - assign ex1_gsprg3_re = (ex1_gsprg3_rdec | (ex1_sprg3_rdec & ex1_msr_gs_q[0])); - assign ex1_sprg0_re = ex1_sprg0_rdec & ~ex1_msr_gs_q[0]; - assign ex1_sprg1_re = ex1_sprg1_rdec & ~ex1_msr_gs_q[0]; - assign ex1_sprg2_re = ex1_sprg2_rdec & ~ex1_msr_gs_q[0]; - assign ex1_sprg3_re = ex1_sprg3_rdec & ~ex1_msr_gs_q[0]; - assign ex1_sprg4_re = ex1_sprg4_rdec; - assign ex1_sprg5_re = ex1_sprg5_rdec; - assign ex1_sprg6_re = ex1_sprg6_rdec; - assign ex1_sprg7_re = ex1_sprg7_rdec; - assign ex1_sprg8_re = ex1_sprg8_rdec; - assign ex1_vrsave_re = ex1_vrsave_rdec; - - assign ex1_aspr_re[1] = ex1_is_mfspr & ( - ex1_gsprg0_re | ex1_gsprg1_re | ex1_gsprg2_re - | ex1_gsprg3_re | ex1_sprg0_re | ex1_sprg1_re - | ex1_sprg2_re | ex1_sprg3_re | ex1_sprg4_re - | ex1_sprg5_re | ex1_sprg6_re | ex1_sprg7_re - | ex1_sprg8_re | ex1_vrsave_re ); - - generate - if (`GPR_WIDTH > 32) - begin : ex1_aspr_re0_gen - assign ex1_aspr_re[0] = ex1_aspr_re[1] & ~( - ex1_vrsave_re ); - end - endgenerate - - assign ex1_aspr_addr = - (4'b0000 & {4{ex1_gsprg0_re }}) | - (4'b0001 & {4{ex1_gsprg1_re }}) | - (4'b0010 & {4{ex1_gsprg2_re }}) | - (4'b0011 & {4{ex1_gsprg3_re }}) | - (4'b0100 & {4{ex1_sprg0_re }}) | - (4'b0101 & {4{ex1_sprg1_re }}) | - (4'b0110 & {4{ex1_sprg2_re }}) | - (4'b0111 & {4{ex1_sprg3_re }}) | - (4'b1000 & {4{ex1_sprg4_re }}) | - (4'b1001 & {4{ex1_sprg5_re }}) | - (4'b1010 & {4{ex1_sprg6_re }}) | - (4'b1011 & {4{ex1_sprg7_re }}) | - (4'b1100 & {4{ex1_sprg8_re }}) | - (4'b1101 & {4{ex1_vrsave_re }}); - - - // Array Writes - - // Generate ECC - assign ex2_inj_ecc = |(inj_sprg_ecc_q & ex2_tid) & ~ex4_sprg_ce_q[0]; - - assign ex3_aspr_addr_d = (ex4_sprg_ce_q[`GPR_WIDTH/8] == 1'b1) ? ex4_aspr_ce_addr_q : ex2_aspr_addr; - - - generate - genvar i; - for (i=0; i<`GPR_WIDTH; i=i+1) begin : ex2_rt_gen - assign ex2_rt[i] = (ex4_corr_rdata_q[i] & ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) | - (xu_spr_ex2_rs1[i] & ~ex4_sprg_ce_q[i % (`GPR_WIDTH/8)]) ; - end - endgenerate - - assign ex2_rt_inj[63] = ex2_rt[63] ^ ex2_inj_ecc; - assign ex2_rt_inj[64-`GPR_WIDTH:62] = ex2_rt[64 - `GPR_WIDTH:62]; - - assign ex2_eccgen_data = {ex2_rt, tidn[0:8 - (64/`GPR_WIDTH)]}; - - - tri_eccgen #(.REGSIZE(`GPR_WIDTH)) xu_spr_wr_eccgen( - .din(ex2_eccgen_data), - .syn(ex2_eccgen_syn) - ); - - assign ex2_is_mfsspr_b = ~ex2_sspr_rd_val; - - assign ex2_aspr_addr_act = exx_act_data[2] | ex4_sprg_ce_q[0]; - - assign ex3_rt_act = exx_act_data[2] | ex4_sprg_ce_q[0]; - assign ex3_rt_d = {(ex2_rt_inj & {`GPR_WIDTH{ex2_is_mfsspr_b}}), ex2_eccgen_syn}; - - assign ex4_sprg_ue = ex4_val_q & {`THREADS{ex4_sprg_ue_q}}; - assign ex4_sprg_ce = ex4_val_q & {`THREADS{ex4_sprg_ce_q[0]}}; - assign ex3_aspr_we_d = |(ex2_val) & ex2_aspr_we; - - assign ex2_aspr_we = ex2_is_mtspr_q & ( - ex2_gsprg0_we | ex2_gsprg1_we | ex2_gsprg2_we - | ex2_gsprg3_we | ex2_sprg0_we | ex2_sprg1_we - | ex2_sprg2_we | ex2_sprg3_we | ex2_sprg4_we - | ex2_sprg5_we | ex2_sprg6_we | ex2_sprg7_we - | ex2_sprg8_we | ex2_vrsave_we ); - - assign ex2_gsprg0_wdec = (ex2_instr[11:20] == 10'b1000001011); // 368 - assign ex2_gsprg1_wdec = (ex2_instr[11:20] == 10'b1000101011); // 369 - assign ex2_gsprg2_wdec = (ex2_instr[11:20] == 10'b1001001011); // 370 - assign ex2_gsprg3_wdec = (ex2_instr[11:20] == 10'b1001101011); // 371 - assign ex2_sprg0_wdec = (ex2_instr[11:20] == 10'b1000001000); // 272 - assign ex2_sprg1_wdec = (ex2_instr[11:20] == 10'b1000101000); // 273 - assign ex2_sprg2_wdec = (ex2_instr[11:20] == 10'b1001001000); // 274 - assign ex2_sprg3_wdec = ((ex2_instr[11:20] == 10'b1001101000)); // 275 - assign ex2_sprg4_wdec = ((ex2_instr[11:20] == 10'b1010001000)); // 276 - assign ex2_sprg5_wdec = ((ex2_instr[11:20] == 10'b1010101000)); // 277 - assign ex2_sprg6_wdec = ((ex2_instr[11:20] == 10'b1011001000)); // 278 - assign ex2_sprg7_wdec = ((ex2_instr[11:20] == 10'b1011101000)); // 279 - assign ex2_sprg8_wdec = (ex2_instr[11:20] == 10'b1110010010); // 604 - assign ex2_vrsave_wdec = (ex2_instr[11:20] == 10'b0000001000); // 256 - assign ex2_gsprg0_we = (ex2_gsprg0_wdec | (ex2_sprg0_wdec & ex2_msr_gs_q[0])); - assign ex2_gsprg1_we = (ex2_gsprg1_wdec | (ex2_sprg1_wdec & ex2_msr_gs_q[0])); - assign ex2_gsprg2_we = (ex2_gsprg2_wdec | (ex2_sprg2_wdec & ex2_msr_gs_q[0])); - assign ex2_gsprg3_we = (ex2_gsprg3_wdec | (ex2_sprg3_wdec & ex2_msr_gs_q[0])); - assign ex2_sprg0_we = ex2_sprg0_wdec & ~ex2_msr_gs_q[0]; - assign ex2_sprg1_we = ex2_sprg1_wdec & ~ex2_msr_gs_q[0]; - assign ex2_sprg2_we = ex2_sprg2_wdec & ~ex2_msr_gs_q[0]; - assign ex2_sprg3_we = ex2_sprg3_wdec & ~ex2_msr_gs_q[0]; - assign ex2_sprg4_we = ex2_sprg4_wdec; - assign ex2_sprg5_we = ex2_sprg5_wdec; - assign ex2_sprg6_we = ex2_sprg6_wdec; - assign ex2_sprg7_we = ex2_sprg7_wdec; - assign ex2_sprg8_we = ex2_sprg8_wdec; - assign ex2_vrsave_we = ex2_vrsave_wdec; - - assign ex2_aspr_addr = - (4'b0000 & {4{ex2_gsprg0_we }}) | - (4'b0001 & {4{ex2_gsprg1_we }}) | - (4'b0010 & {4{ex2_gsprg2_we }}) | - (4'b0011 & {4{ex2_gsprg3_we }}) | - (4'b0100 & {4{ex2_sprg0_we }}) | - (4'b0101 & {4{ex2_sprg1_we }}) | - (4'b0110 & {4{ex2_sprg2_we }}) | - (4'b0111 & {4{ex2_sprg3_we }}) | - (4'b1000 & {4{ex2_sprg4_we }}) | - (4'b1001 & {4{ex2_sprg5_we }}) | - (4'b1010 & {4{ex2_sprg6_we }}) | - (4'b1011 & {4{ex2_sprg7_we }}) | - (4'b1100 & {4{ex2_sprg8_we }}) | - (4'b1101 & {4{ex2_vrsave_we }}); - - // Slow SPR - assign ex2_acop_rdec = (ex2_instr[11:20] == 10'b1111100000); // 31 - assign ex2_axucr0_rdec = (ex2_instr[11:20] == 10'b1000011110); // 976 - assign ex2_cpcr0_rdec = (ex2_instr[11:20] == 10'b1000011001); // 816 - assign ex2_cpcr1_rdec = (ex2_instr[11:20] == 10'b1000111001); // 817 - assign ex2_cpcr2_rdec = (ex2_instr[11:20] == 10'b1001011001); // 818 - assign ex2_cpcr3_rdec = (ex2_instr[11:20] == 10'b1010011001); // 820 - assign ex2_cpcr4_rdec = (ex2_instr[11:20] == 10'b1010111001); // 821 - assign ex2_cpcr5_rdec = (ex2_instr[11:20] == 10'b1011011001); // 822 - assign ex2_dac1_rdec = (ex2_instr[11:20] == 10'b1110001001); // 316 - assign ex2_dac2_rdec = (ex2_instr[11:20] == 10'b1110101001); // 317 - assign ex2_dac3_rdec = (ex2_instr[11:20] == 10'b1000111010); // 849 - assign ex2_dac4_rdec = (ex2_instr[11:20] == 10'b1001011010); // 850 - assign ex2_dbcr2_rdec = (ex2_instr[11:20] == 10'b1011001001); // 310 - assign ex2_dbcr3_rdec = (ex2_instr[11:20] == 10'b1000011010); // 848 - assign ex2_dscr_rdec = (ex2_instr[11:20] == 10'b1000100000); // 17 - assign ex2_dvc1_rdec = (ex2_instr[11:20] == 10'b1111001001); // 318 - assign ex2_dvc2_rdec = (ex2_instr[11:20] == 10'b1111101001); // 319 - assign ex2_eheir_rdec = (ex2_instr[11:20] == 10'b1010000001); // 52 - assign ex2_eplc_rdec = (ex2_instr[11:20] == 10'b1001111101); // 947 - assign ex2_epsc_rdec = (ex2_instr[11:20] == 10'b1010011101); // 948 - assign ex2_eptcfg_rdec = (ex2_instr[11:20] == 10'b1111001010); // 350 - assign ex2_givpr_rdec = (ex2_instr[11:20] == 10'b1111101101); // 447 - assign ex2_hacop_rdec = (ex2_instr[11:20] == 10'b1111101010); // 351 - assign ex2_iac1_rdec = (ex2_instr[11:20] == 10'b1100001001); // 312 - assign ex2_iac2_rdec = (ex2_instr[11:20] == 10'b1100101001); // 313 - assign ex2_iac3_rdec = (ex2_instr[11:20] == 10'b1101001001); // 314 - assign ex2_iac4_rdec = (ex2_instr[11:20] == 10'b1101101001); // 315 - assign ex2_immr_rdec = (ex2_instr[11:20] == 10'b1000111011); // 881 - assign ex2_imr_rdec = (ex2_instr[11:20] == 10'b1000011011); // 880 - assign ex2_iucr0_rdec = (ex2_instr[11:20] == 10'b1001111111); // 1011 - assign ex2_iucr1_rdec = (ex2_instr[11:20] == 10'b1001111011); // 883 - assign ex2_iucr2_rdec = (ex2_instr[11:20] == 10'b1010011011); // 884 - assign ex2_iudbg0_rdec = (ex2_instr[11:20] == 10'b1100011011); // 888 - assign ex2_iudbg1_rdec = (ex2_instr[11:20] == 10'b1100111011); // 889 - assign ex2_iudbg2_rdec = (ex2_instr[11:20] == 10'b1101011011); // 890 - assign ex2_iulfsr_rdec = (ex2_instr[11:20] == 10'b1101111011); // 891 - assign ex2_iullcr_rdec = (ex2_instr[11:20] == 10'b1110011011); // 892 - assign ex2_ivpr_rdec = (ex2_instr[11:20] == 10'b1111100001); // 63 - assign ex2_lesr1_rdec = (ex2_instr[11:20] == 10'b1100011100); // 920 - assign ex2_lesr2_rdec = (ex2_instr[11:20] == 10'b1100111100); // 921 - assign ex2_lper_rdec = (ex2_instr[11:20] == 10'b1100000001); // 56 - assign ex2_lperu_rdec = (ex2_instr[11:20] == 10'b1100100001); // 57 - assign ex2_lpidr_rdec = (ex2_instr[11:20] == 10'b1001001010); // 338 - assign ex2_lratcfg_rdec = (ex2_instr[11:20] == 10'b1011001010); // 342 - assign ex2_lratps_rdec = (ex2_instr[11:20] == 10'b1011101010); // 343 - assign ex2_lsucr0_rdec = (ex2_instr[11:20] == 10'b1001111001); // 819 - assign ex2_mas0_rdec = (ex2_instr[11:20] == 10'b1000010011); // 624 - assign ex2_mas0_mas1_rdec = (ex2_instr[11:20] == 10'b1010101011); // 373 - assign ex2_mas1_rdec = (ex2_instr[11:20] == 10'b1000110011); // 625 - assign ex2_mas2_rdec = (ex2_instr[11:20] == 10'b1001010011); // 626 - assign ex2_mas2u_rdec = (ex2_instr[11:20] == 10'b1011110011); // 631 - assign ex2_mas3_rdec = (ex2_instr[11:20] == 10'b1001110011); // 627 - assign ex2_mas4_rdec = (ex2_instr[11:20] == 10'b1010010011); // 628 - assign ex2_mas5_rdec = (ex2_instr[11:20] == 10'b1001101010); // 339 - assign ex2_mas5_mas6_rdec = (ex2_instr[11:20] == 10'b1110001010); // 348 - assign ex2_mas6_rdec = (ex2_instr[11:20] == 10'b1011010011); // 630 - assign ex2_mas7_rdec = (ex2_instr[11:20] == 10'b1000011101); // 944 - assign ex2_mas7_mas3_rdec = (ex2_instr[11:20] == 10'b1010001011); // 372 - assign ex2_mas8_rdec = (ex2_instr[11:20] == 10'b1010101010); // 341 - assign ex2_mas8_mas1_rdec = (ex2_instr[11:20] == 10'b1110101010); // 349 - assign ex2_mmucfg_rdec = (ex2_instr[11:20] == 10'b1011111111); // 1015 - assign ex2_mmucr0_rdec = (ex2_instr[11:20] == 10'b1110011111); // 1020 - assign ex2_mmucr1_rdec = (ex2_instr[11:20] == 10'b1110111111); // 1021 - assign ex2_mmucr2_rdec = (ex2_instr[11:20] == 10'b1111011111); // 1022 - assign ex2_mmucr3_rdec = (ex2_instr[11:20] == 10'b1111111111); // 1023 - assign ex2_mmucsr0_rdec = (ex2_instr[11:20] == 10'b1010011111); // 1012 - assign ex2_pesr_rdec = (ex2_instr[11:20] == 10'b1110111011); // 893 - assign ex2_pid_rdec = (ex2_instr[11:20] == 10'b1000000001); // 48 - assign ex2_ppr32_rdec = (ex2_instr[11:20] == 10'b0001011100); // 898 - assign ex2_sramd_rdec = (ex2_instr[11:20] == 10'b1111011011); // 894 - assign ex2_tlb0cfg_rdec = (ex2_instr[11:20] == 10'b1000010101); // 688 - assign ex2_tlb0ps_rdec = (ex2_instr[11:20] == 10'b1100001010); // 344 - assign ex2_xucr2_rdec = (ex2_instr[11:20] == 10'b1100011111); // 1016 - assign ex2_xudbg0_rdec = (ex2_instr[11:20] == 10'b1010111011); // 885 - assign ex2_xudbg1_rdec = (ex2_instr[11:20] == 10'b1011011011); // 886 - assign ex2_xudbg2_rdec = (ex2_instr[11:20] == 10'b1011111011); // 887 - assign ex2_acop_re = ex2_acop_rdec; - assign ex2_axucr0_re = ex2_axucr0_rdec; - assign ex2_cpcr0_re = ex2_cpcr0_rdec; - assign ex2_cpcr1_re = ex2_cpcr1_rdec; - assign ex2_cpcr2_re = ex2_cpcr2_rdec; - assign ex2_cpcr3_re = ex2_cpcr3_rdec; - assign ex2_cpcr4_re = ex2_cpcr4_rdec; - assign ex2_cpcr5_re = ex2_cpcr5_rdec; - assign ex2_dac1_re = ex2_dac1_rdec; - assign ex2_dac2_re = ex2_dac2_rdec; - assign ex2_dac3_re = ex2_dac3_rdec; - assign ex2_dac4_re = ex2_dac4_rdec; - assign ex2_dbcr2_re = ex2_dbcr2_rdec; - assign ex2_dbcr3_re = ex2_dbcr3_rdec; - assign ex2_dscr_re = ex2_dscr_rdec; - assign ex2_dvc1_re = ex2_dvc1_rdec; - assign ex2_dvc2_re = ex2_dvc2_rdec; - assign ex2_eheir_re = ex2_eheir_rdec; - assign ex2_eplc_re = ex2_eplc_rdec; - assign ex2_epsc_re = ex2_epsc_rdec; - assign ex2_eptcfg_re = ex2_eptcfg_rdec; - assign ex2_givpr_re = ex2_givpr_rdec; - assign ex2_hacop_re = ex2_hacop_rdec; - assign ex2_iac1_re = ex2_iac1_rdec; - assign ex2_iac2_re = ex2_iac2_rdec; - assign ex2_iac3_re = ex2_iac3_rdec; - assign ex2_iac4_re = ex2_iac4_rdec; - assign ex2_immr_re = ex2_immr_rdec; - assign ex2_imr_re = ex2_imr_rdec; - assign ex2_iucr0_re = ex2_iucr0_rdec; - assign ex2_iucr1_re = ex2_iucr1_rdec; - assign ex2_iucr2_re = ex2_iucr2_rdec; - assign ex2_iudbg0_re = ex2_iudbg0_rdec; - assign ex2_iudbg1_re = ex2_iudbg1_rdec; - assign ex2_iudbg2_re = ex2_iudbg2_rdec; - assign ex2_iulfsr_re = ex2_iulfsr_rdec; - assign ex2_iullcr_re = ex2_iullcr_rdec; - assign ex2_ivpr_re = ex2_ivpr_rdec; - assign ex2_lesr1_re = ex2_lesr1_rdec; - assign ex2_lesr2_re = ex2_lesr2_rdec; - assign ex2_lper_re = ex2_lper_rdec; - assign ex2_lperu_re = ex2_lperu_rdec; - assign ex2_lpidr_re = ex2_lpidr_rdec; - assign ex2_lratcfg_re = ex2_lratcfg_rdec; - assign ex2_lratps_re = ex2_lratps_rdec; - assign ex2_lsucr0_re = ex2_lsucr0_rdec; - assign ex2_mas0_re = ex2_mas0_rdec; - assign ex2_mas0_mas1_re = ex2_mas0_mas1_rdec; - assign ex2_mas1_re = ex2_mas1_rdec; - assign ex2_mas2_re = ex2_mas2_rdec; - assign ex2_mas2u_re = ex2_mas2u_rdec; - assign ex2_mas3_re = ex2_mas3_rdec; - assign ex2_mas4_re = ex2_mas4_rdec; - assign ex2_mas5_re = ex2_mas5_rdec; - assign ex2_mas5_mas6_re = ex2_mas5_mas6_rdec; - assign ex2_mas6_re = ex2_mas6_rdec; - assign ex2_mas7_re = ex2_mas7_rdec; - assign ex2_mas7_mas3_re = ex2_mas7_mas3_rdec; - assign ex2_mas8_re = ex2_mas8_rdec; - assign ex2_mas8_mas1_re = ex2_mas8_mas1_rdec; - assign ex2_mmucfg_re = ex2_mmucfg_rdec; - assign ex2_mmucr0_re = ex2_mmucr0_rdec; - assign ex2_mmucr1_re = ex2_mmucr1_rdec; - assign ex2_mmucr2_re = ex2_mmucr2_rdec; - assign ex2_mmucr3_re = ex2_mmucr3_rdec; - assign ex2_mmucsr0_re = ex2_mmucsr0_rdec; - assign ex2_pesr_re = ex2_pesr_rdec; - assign ex2_pid_re = ex2_pid_rdec; - assign ex2_ppr32_re = ex2_ppr32_rdec; - assign ex2_sramd_re = ex2_sramd_rdec; - assign ex2_tlb0cfg_re = ex2_tlb0cfg_rdec; - assign ex2_tlb0ps_re = ex2_tlb0ps_rdec; - assign ex2_xucr2_re = ex2_xucr2_rdec; - assign ex2_xudbg0_re = ex2_xudbg0_rdec; - assign ex2_xudbg1_re = ex2_xudbg1_rdec; - assign ex2_xudbg2_re = ex2_xudbg2_rdec; - assign ex2_acop_wdec = ex2_acop_rdec; - assign ex2_axucr0_wdec = ex2_axucr0_rdec; - assign ex2_cpcr0_wdec = ex2_cpcr0_rdec; - assign ex2_cpcr1_wdec = ex2_cpcr1_rdec; - assign ex2_cpcr2_wdec = ex2_cpcr2_rdec; - assign ex2_cpcr3_wdec = ex2_cpcr3_rdec; - assign ex2_cpcr4_wdec = ex2_cpcr4_rdec; - assign ex2_cpcr5_wdec = ex2_cpcr5_rdec; - assign ex2_dac1_wdec = ex2_dac1_rdec; - assign ex2_dac2_wdec = ex2_dac2_rdec; - assign ex2_dac3_wdec = ex2_dac3_rdec; - assign ex2_dac4_wdec = ex2_dac4_rdec; - assign ex2_dbcr2_wdec = ex2_dbcr2_rdec; - assign ex2_dbcr3_wdec = ex2_dbcr3_rdec; - assign ex2_dscr_wdec = ex2_dscr_rdec; - assign ex2_dvc1_wdec = ex2_dvc1_rdec; - assign ex2_dvc2_wdec = ex2_dvc2_rdec; - assign ex2_eheir_wdec = ex2_eheir_rdec; - assign ex2_eplc_wdec = ex2_eplc_rdec; - assign ex2_epsc_wdec = ex2_epsc_rdec; - assign ex2_givpr_wdec = (ex2_instr[11:20] == 10'b1111101101); // 447 - assign ex2_hacop_wdec = (ex2_instr[11:20] == 10'b1111101010); // 351 - assign ex2_iac1_wdec = ex2_iac1_rdec; - assign ex2_iac2_wdec = ex2_iac2_rdec; - assign ex2_iac3_wdec = ex2_iac3_rdec; - assign ex2_iac4_wdec = ex2_iac4_rdec; - assign ex2_immr_wdec = ex2_immr_rdec; - assign ex2_imr_wdec = ex2_imr_rdec; - assign ex2_iucr0_wdec = ex2_iucr0_rdec; - assign ex2_iucr1_wdec = ex2_iucr1_rdec; - assign ex2_iucr2_wdec = ex2_iucr2_rdec; - assign ex2_iudbg0_wdec = ex2_iudbg0_rdec; - assign ex2_iulfsr_wdec = ex2_iulfsr_rdec; - assign ex2_iullcr_wdec = ex2_iullcr_rdec; - assign ex2_ivpr_wdec = ex2_ivpr_rdec; - assign ex2_lesr1_wdec = ex2_lesr1_rdec; - assign ex2_lesr2_wdec = ex2_lesr2_rdec; - assign ex2_lper_wdec = ex2_lper_rdec; - assign ex2_lperu_wdec = ex2_lperu_rdec; - assign ex2_lpidr_wdec = ex2_lpidr_rdec; - assign ex2_lsucr0_wdec = ex2_lsucr0_rdec; - assign ex2_mas0_wdec = ex2_mas0_rdec; - assign ex2_mas0_mas1_wdec = ex2_mas0_mas1_rdec; - assign ex2_mas1_wdec = ex2_mas1_rdec; - assign ex2_mas2_wdec = ex2_mas2_rdec; - assign ex2_mas2u_wdec = ex2_mas2u_rdec; - assign ex2_mas3_wdec = ex2_mas3_rdec; - assign ex2_mas4_wdec = ex2_mas4_rdec; - assign ex2_mas5_wdec = ex2_mas5_rdec; - assign ex2_mas5_mas6_wdec = ex2_mas5_mas6_rdec; - assign ex2_mas6_wdec = ex2_mas6_rdec; - assign ex2_mas7_wdec = ex2_mas7_rdec; - assign ex2_mas7_mas3_wdec = ex2_mas7_mas3_rdec; - assign ex2_mas8_wdec = ex2_mas8_rdec; - assign ex2_mas8_mas1_wdec = ex2_mas8_mas1_rdec; - assign ex2_mmucr0_wdec = ex2_mmucr0_rdec; - assign ex2_mmucr1_wdec = ex2_mmucr1_rdec; - assign ex2_mmucr2_wdec = ex2_mmucr2_rdec; - assign ex2_mmucr3_wdec = ex2_mmucr3_rdec; - assign ex2_mmucsr0_wdec = ex2_mmucsr0_rdec; - assign ex2_pesr_wdec = ex2_pesr_rdec; - assign ex2_pid_wdec = ex2_pid_rdec; - assign ex2_ppr32_wdec = ex2_ppr32_rdec; - assign ex2_xucr2_wdec = ex2_xucr2_rdec; - assign ex2_xudbg0_wdec = ex2_xudbg0_rdec; - assign ex2_acop_we = ex2_acop_wdec; - assign ex2_axucr0_we = ex2_axucr0_wdec; - assign ex2_cpcr0_we = ex2_cpcr0_wdec; - assign ex2_cpcr1_we = ex2_cpcr1_wdec; - assign ex2_cpcr2_we = ex2_cpcr2_wdec; - assign ex2_cpcr3_we = ex2_cpcr3_wdec; - assign ex2_cpcr4_we = ex2_cpcr4_wdec; - assign ex2_cpcr5_we = ex2_cpcr5_wdec; - assign ex2_dac1_we = ex2_dac1_wdec; - assign ex2_dac2_we = ex2_dac2_wdec; - assign ex2_dac3_we = ex2_dac3_wdec; - assign ex2_dac4_we = ex2_dac4_wdec; - assign ex2_dbcr2_we = ex2_dbcr2_wdec; - assign ex2_dbcr3_we = ex2_dbcr3_wdec; - assign ex2_dscr_we = ex2_dscr_wdec; - assign ex2_dvc1_we = ex2_dvc1_wdec; - assign ex2_dvc2_we = ex2_dvc2_wdec; - assign ex2_eheir_we = ex2_eheir_wdec; - assign ex2_eplc_we = ex2_eplc_wdec; - assign ex2_epsc_we = ex2_epsc_wdec; - assign ex2_givpr_we = ex2_givpr_wdec; - assign ex2_hacop_we = ex2_hacop_wdec; - assign ex2_iac1_we = ex2_iac1_wdec; - assign ex2_iac2_we = ex2_iac2_wdec; - assign ex2_iac3_we = ex2_iac3_wdec; - assign ex2_iac4_we = ex2_iac4_wdec; - assign ex2_immr_we = ex2_immr_wdec; - assign ex2_imr_we = ex2_imr_wdec; - assign ex2_iucr0_we = ex2_iucr0_wdec; - assign ex2_iucr1_we = ex2_iucr1_wdec; - assign ex2_iucr2_we = ex2_iucr2_wdec; - assign ex2_iudbg0_we = ex2_iudbg0_wdec; - assign ex2_iulfsr_we = ex2_iulfsr_wdec; - assign ex2_iullcr_we = ex2_iullcr_wdec; - assign ex2_ivpr_we = ex2_ivpr_wdec; - assign ex2_lesr1_we = ex2_lesr1_wdec; - assign ex2_lesr2_we = ex2_lesr2_wdec; - assign ex2_lper_we = ex2_lper_wdec; - assign ex2_lperu_we = ex2_lperu_wdec; - assign ex2_lpidr_we = ex2_lpidr_wdec; - assign ex2_lsucr0_we = ex2_lsucr0_wdec; - assign ex2_mas0_we = ex2_mas0_wdec; - assign ex2_mas0_mas1_we = ex2_mas0_mas1_wdec; - assign ex2_mas1_we = ex2_mas1_wdec; - assign ex2_mas2_we = ex2_mas2_wdec; - assign ex2_mas2u_we = ex2_mas2u_wdec; - assign ex2_mas3_we = ex2_mas3_wdec; - assign ex2_mas4_we = ex2_mas4_wdec; - assign ex2_mas5_we = ex2_mas5_wdec; - assign ex2_mas5_mas6_we = ex2_mas5_mas6_wdec; - assign ex2_mas6_we = ex2_mas6_wdec; - assign ex2_mas7_we = ex2_mas7_wdec; - assign ex2_mas7_mas3_we = ex2_mas7_mas3_wdec; - assign ex2_mas8_we = ex2_mas8_wdec; - assign ex2_mas8_mas1_we = ex2_mas8_mas1_wdec; - assign ex2_mmucr0_we = ex2_mmucr0_wdec; - assign ex2_mmucr1_we = ex2_mmucr1_wdec; - assign ex2_mmucr2_we = ex2_mmucr2_wdec; - assign ex2_mmucr3_we = ex2_mmucr3_wdec; - assign ex2_mmucsr0_we = ex2_mmucsr0_wdec; - assign ex2_pesr_we = ex2_pesr_wdec; - assign ex2_pid_we = ex2_pid_wdec; - assign ex2_ppr32_we = ex2_ppr32_wdec; - assign ex2_xucr2_we = ex2_xucr2_wdec; - assign ex2_xudbg0_we = ex2_xudbg0_wdec; - assign ex2_slowspr_range_hypv = ex2_instr[11] & ex2_instr[16:20] == 5'b11110; // 976-991 - assign ex2_slowspr_range_priv = ex2_instr[11] & ex2_instr[16:20] == 5'b11100 & (~(ex2_xesr1_rdec | ex2_xesr2_rdec)); // 912-927 except 918/919 - assign ex2_slowspr_range = ex2_slowspr_range_priv | ex2_slowspr_range_hypv; - - // mftb encode is only legal for tbr=268,269 -- "0110-01000" - assign ex2_illeg_mftb = ex2_is_mftb_q & (~(ex2_instr[11:14] == 4'b0110 & ex2_instr[16:20] == 5'b01000)); - - assign ex2_sspr_wr_val = ex2_is_mtspr_q & (ex2_slowspr_range | - ex2_acop_we | ex2_axucr0_we | ex2_cpcr0_we - | ex2_cpcr1_we | ex2_cpcr2_we | ex2_cpcr3_we - | ex2_cpcr4_we | ex2_cpcr5_we | ex2_dac1_we - | ex2_dac2_we | ex2_dac3_we | ex2_dac4_we - | ex2_dbcr2_we | ex2_dbcr3_we | ex2_dscr_we - | ex2_dvc1_we | ex2_dvc2_we | ex2_eheir_we - | ex2_eplc_we | ex2_epsc_we | ex2_givpr_we - | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we - | ex2_iac3_we | ex2_iac4_we | ex2_immr_we - | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we - | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we - | ex2_iullcr_we | ex2_ivpr_we | ex2_lesr1_we - | ex2_lesr2_we | ex2_lper_we | ex2_lperu_we - | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas0_we - | ex2_mas0_mas1_we | ex2_mas1_we | ex2_mas2_we - | ex2_mas2u_we | ex2_mas3_we | ex2_mas4_we - | ex2_mas5_we | ex2_mas5_mas6_we | ex2_mas6_we - | ex2_mas7_we | ex2_mas7_mas3_we | ex2_mas8_we - | ex2_mas8_mas1_we | ex2_mmucr0_we | ex2_mmucr1_we - | ex2_mmucr2_we | ex2_mmucr3_we | ex2_mmucsr0_we - | ex2_pesr_we | ex2_pid_we | ex2_ppr32_we - | ex2_xucr2_we | ex2_xudbg0_we ); - - assign ex2_sspr_rd_val = ex2_is_mfspr_q & (ex2_slowspr_range | - ex2_acop_re | ex2_axucr0_re | ex2_cpcr0_re - | ex2_cpcr1_re | ex2_cpcr2_re | ex2_cpcr3_re - | ex2_cpcr4_re | ex2_cpcr5_re | ex2_dac1_re - | ex2_dac2_re | ex2_dac3_re | ex2_dac4_re - | ex2_dbcr2_re | ex2_dbcr3_re | ex2_dscr_re - | ex2_dvc1_re | ex2_dvc2_re | ex2_eheir_re - | ex2_eplc_re | ex2_epsc_re | ex2_eptcfg_re - | ex2_givpr_re | ex2_hacop_re | ex2_iac1_re - | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re - | ex2_immr_re | ex2_imr_re | ex2_iucr0_re - | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re - | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re - | ex2_iullcr_re | ex2_ivpr_re | ex2_lesr1_re - | ex2_lesr2_re | ex2_lper_re | ex2_lperu_re - | ex2_lpidr_re | ex2_lratcfg_re | ex2_lratps_re - | ex2_lsucr0_re | ex2_mas0_re | ex2_mas0_mas1_re - | ex2_mas1_re | ex2_mas2_re | ex2_mas2u_re - | ex2_mas3_re | ex2_mas4_re | ex2_mas5_re - | ex2_mas5_mas6_re | ex2_mas6_re | ex2_mas7_re - | ex2_mas7_mas3_re | ex2_mas8_re | ex2_mas8_mas1_re - | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re - | ex2_mmucr2_re | ex2_mmucr3_re | ex2_mmucsr0_re - | ex2_pesr_re | ex2_pid_re | ex2_ppr32_re - | ex2_sramd_re | ex2_tlb0cfg_re | ex2_tlb0ps_re - | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re - | ex2_xudbg2_re ); - - // Illegal SPR checks - assign ex2_sprg8_re = ex2_sprg8_rdec; - assign ex2_gsprg0_rdec = (ex2_instr[11:20] == 10'b1000001011); // 368 - assign ex2_gsprg1_rdec = (ex2_instr[11:20] == 10'b1000101011); // 369 - assign ex2_gsprg2_rdec = (ex2_instr[11:20] == 10'b1001001011); // 370 - assign ex2_gsprg3_rdec = (ex2_instr[11:20] == 10'b1001101011); // 371 - assign ex2_sprg0_rdec = (ex2_instr[11:20] == 10'b1000001000); // 272 - assign ex2_sprg1_rdec = (ex2_instr[11:20] == 10'b1000101000); // 273 - assign ex2_sprg2_rdec = (ex2_instr[11:20] == 10'b1001001000); // 274 - assign ex2_sprg3_rdec = ((ex2_instr[11:20] == 10'b1001101000) | // 275 - (ex2_instr[11:20] == 10'b0001101000)); // 259 - assign ex2_sprg4_rdec = ((ex2_instr[11:20] == 10'b1010001000) | // 276 - (ex2_instr[11:20] == 10'b0010001000)); // 260 - assign ex2_sprg5_rdec = ((ex2_instr[11:20] == 10'b1010101000) | // 277 - (ex2_instr[11:20] == 10'b0010101000)); // 261 - assign ex2_sprg6_rdec = ((ex2_instr[11:20] == 10'b1011001000) | // 278 - (ex2_instr[11:20] == 10'b0011001000)); // 262 - assign ex2_sprg7_rdec = ((ex2_instr[11:20] == 10'b1011101000) | // 279 - (ex2_instr[11:20] == 10'b0011101000)); // 263 - assign ex2_sprg8_rdec = (ex2_instr[11:20] == 10'b1110010010); // 604 - assign ex2_vrsave_rdec = (ex2_instr[11:20] == 10'b0000001000); // 256 - assign ex2_ccr0_rdec = (ex2_instr[11:20] == 10'b1000011111); // 1008 - assign ex2_ccr1_rdec = (ex2_instr[11:20] == 10'b1000111111); // 1009 - assign ex2_ccr2_rdec = (ex2_instr[11:20] == 10'b1001011111); // 1010 - assign ex2_ccr4_rdec = (ex2_instr[11:20] == 10'b1011011010); // 854 - assign ex2_cir_rdec = (ex2_instr[11:20] == 10'b1101101000); // 283 - assign ex2_pir_rdec = (ex2_instr[11:20] == 10'b1111001000); // 286 - assign ex2_pvr_rdec = (ex2_instr[11:20] == 10'b1111101000); // 287 - assign ex2_tb_rdec = (ex2_instr[11:20] == 10'b0110001000); // 268 - assign ex2_tbu_rdec = ((ex2_instr[11:20] == 10'b0110101000)); // 269 - assign ex2_tenc_rdec = (ex2_instr[11:20] == 10'b1011101101); // 439 - assign ex2_tens_rdec = (ex2_instr[11:20] == 10'b1011001101); // 438 - assign ex2_tensr_rdec = (ex2_instr[11:20] == 10'b1010101101); // 437 - assign ex2_tir_rdec = (ex2_instr[11:20] == 10'b1111001101); // 446 - assign ex2_xesr1_rdec = (ex2_instr[11:20] == 10'b1011011100); // 918 - assign ex2_xesr2_rdec = (ex2_instr[11:20] == 10'b1011111100); // 919 - assign ex2_xucr0_rdec = (ex2_instr[11:20] == 10'b1011011111); // 1014 - assign ex2_xucr4_rdec = (ex2_instr[11:20] == 10'b1010111010); // 853 - assign ex2_ccr0_re = ex2_ccr0_rdec; - assign ex2_ccr1_re = ex2_ccr1_rdec; - assign ex2_ccr2_re = ex2_ccr2_rdec; - assign ex2_ccr4_re = ex2_ccr4_rdec; - assign ex2_cir_re = ex2_cir_rdec; - assign ex2_pir_re = ex2_pir_rdec & ~ex2_msr_gs_q[0]; - assign ex2_pvr_re = ex2_pvr_rdec; - assign ex2_tb_re = ex2_tb_rdec; - assign ex2_tbu_re = ex2_tbu_rdec; - assign ex2_tenc_re = ex2_tenc_rdec; - assign ex2_tens_re = ex2_tens_rdec; - assign ex2_tensr_re = ex2_tensr_rdec; - assign ex2_tir_re = ex2_tir_rdec; - assign ex2_xesr1_re = ex2_xesr1_rdec; - assign ex2_xesr2_re = ex2_xesr2_rdec; - assign ex2_xucr0_re = ex2_xucr0_rdec; - assign ex2_xucr4_re = ex2_xucr4_rdec; - assign ex2_ccr0_wdec = ex2_ccr0_rdec; - assign ex2_ccr1_wdec = ex2_ccr1_rdec; - assign ex2_ccr2_wdec = ex2_ccr2_rdec; - assign ex2_ccr4_wdec = ex2_ccr4_rdec; - assign ex2_tbl_wdec = (ex2_instr[11:20] == 10'b1110001000); // 284 - assign ex2_tbu_wdec = ((ex2_instr[11:20] == 10'b1110101000)); // 285 - assign ex2_tenc_wdec = ex2_tenc_rdec; - assign ex2_tens_wdec = ex2_tens_rdec; - assign ex2_trace_wdec = (ex2_instr[11:20] == 10'b0111011111); // 1006 - assign ex2_xesr1_wdec = ex2_xesr1_rdec; - assign ex2_xesr2_wdec = ex2_xesr2_rdec; - assign ex2_xucr0_wdec = ex2_xucr0_rdec; - assign ex2_xucr4_wdec = ex2_xucr4_rdec; - assign ex2_ccr0_we = ex2_ccr0_wdec; - assign ex2_ccr1_we = ex2_ccr1_wdec; - assign ex2_ccr2_we = ex2_ccr2_wdec; - assign ex2_ccr4_we = ex2_ccr4_wdec; - assign ex2_tbl_we = ex2_tbl_wdec; - assign ex2_tbu_we = ex2_tbu_wdec; - assign ex2_tenc_we = ex2_tenc_wdec; - assign ex2_tens_we = ex2_tens_wdec; - assign ex2_trace_we = ex2_trace_wdec; - assign ex2_xesr1_we = ex2_xesr1_wdec; - assign ex2_xesr2_we = ex2_xesr2_wdec; - assign ex2_xucr0_we = ex2_xucr0_wdec; - assign ex2_xucr4_we = ex2_xucr4_wdec; - - generate - if (a2mode == 0 & hvmode == 0) - begin : ill_spr_00 - - assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( - ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec - | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec - | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec - | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec - | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec - | ex2_xucr0_rdec | ex2_xucr4_rdec | - ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec - | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec - | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec - | ex2_vrsave_rdec | - ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec - | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec - | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec - | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec - | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iucr0_rdec - | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec - | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec - | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec - | ex2_lesr2_rdec | ex2_lpidr_rdec | ex2_lsucr0_rdec - | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec - | ex2_sramd_rdec | ex2_xucr2_rdec | ex2_xudbg0_rdec - | ex2_xudbg1_rdec | ex2_xudbg2_rdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mfspr_b & ex2_tid)); - - assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( - ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec - | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec - | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec - | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec - | ex2_xucr4_wdec | - ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec - | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec - | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec - | ex2_vrsave_wdec | - ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec - | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec - | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec - | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec - | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iucr0_wdec - | ex2_iucr1_wdec | ex2_iucr2_wdec | ex2_iudbg0_wdec - | ex2_iulfsr_wdec | ex2_iullcr_wdec | ex2_ivpr_wdec - | ex2_lesr1_wdec | ex2_lesr2_wdec | ex2_lpidr_wdec - | ex2_lsucr0_wdec | ex2_pesr_wdec | ex2_pid_wdec - | ex2_ppr32_wdec | ex2_xucr2_wdec | ex2_xudbg0_wdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mtspr_b & ex2_tid)); - - assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( - ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re - | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re - | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re - | ex2_xucr4_re | - ex2_sprg8_re | - ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re - | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re - | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re - | ex2_dbcr3_re | ex2_eheir_re | ex2_iac1_re - | ex2_iac2_re | ex2_iucr0_re | ex2_iucr1_re - | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re - | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re - | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re - | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re - | ex2_xudbg2_re | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mfspr & ex2_tid)); - - assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( - ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we - | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we - | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we - | ex2_xucr4_we | - ex2_sprg8_we | - ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we - | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we - | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we - | ex2_dbcr3_we | ex2_eheir_we | ex2_iac1_we - | ex2_iac2_we | ex2_iucr0_we | ex2_iucr1_we - | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we - | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we - | ex2_lsucr0_we | ex2_xucr2_we | ex2_xudbg0_we | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mtspr & ex2_tid)); - - end - endgenerate - - generate - if (a2mode == 0 & hvmode == 1) - begin : ill_spr_01 - assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( - ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec - | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec - | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec - | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec - | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec - | ex2_xucr0_rdec | ex2_xucr4_rdec | - ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec - | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec - | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec - | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec - | ex2_sprg8_rdec | ex2_vrsave_rdec | - ex2_axucr0_rdec | ex2_cpcr0_rdec | ex2_cpcr1_rdec - | ex2_cpcr2_rdec | ex2_cpcr3_rdec | ex2_cpcr4_rdec - | ex2_cpcr5_rdec | ex2_dac3_rdec | ex2_dac4_rdec - | ex2_dbcr3_rdec | ex2_dscr_rdec | ex2_eheir_rdec - | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec - | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec - | ex2_iac2_rdec | ex2_iucr0_rdec | ex2_iucr1_rdec - | ex2_iucr2_rdec | ex2_iudbg0_rdec | ex2_iudbg1_rdec - | ex2_iudbg2_rdec | ex2_iulfsr_rdec | ex2_iullcr_rdec - | ex2_ivpr_rdec | ex2_lesr1_rdec | ex2_lesr2_rdec - | ex2_lper_rdec | ex2_lperu_rdec | ex2_lpidr_rdec - | ex2_lratcfg_rdec | ex2_lratps_rdec | ex2_lsucr0_rdec - | ex2_mas0_rdec | ex2_mas0_mas1_rdec | ex2_mas1_rdec - | ex2_mas2_rdec | ex2_mas2u_rdec | ex2_mas3_rdec - | ex2_mas4_rdec | ex2_mas5_rdec | ex2_mas5_mas6_rdec - | ex2_mas6_rdec | ex2_mas7_rdec | ex2_mas7_mas3_rdec - | ex2_mas8_rdec | ex2_mas8_mas1_rdec | ex2_mmucfg_rdec - | ex2_mmucr3_rdec | ex2_mmucsr0_rdec | ex2_pesr_rdec - | ex2_pid_rdec | ex2_ppr32_rdec | ex2_sramd_rdec - | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec | ex2_xucr2_rdec - | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mfspr_b & ex2_tid)); - - assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( - ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec - | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec - | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec - | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec - | ex2_xucr4_wdec | - ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec - | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec - | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec - | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec - | ex2_sprg8_wdec | ex2_vrsave_wdec | - ex2_axucr0_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec - | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec - | ex2_cpcr5_wdec | ex2_dac3_wdec | ex2_dac4_wdec - | ex2_dbcr3_wdec | ex2_dscr_wdec | ex2_eheir_wdec - | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec - | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec - | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec - | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec - | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec - | ex2_lper_wdec | ex2_lperu_wdec | ex2_lpidr_wdec - | ex2_lsucr0_wdec | ex2_mas0_wdec | ex2_mas0_mas1_wdec - | ex2_mas1_wdec | ex2_mas2_wdec | ex2_mas2u_wdec - | ex2_mas3_wdec | ex2_mas4_wdec | ex2_mas5_wdec - | ex2_mas5_mas6_wdec | ex2_mas6_wdec | ex2_mas7_wdec - | ex2_mas7_mas3_wdec | ex2_mas8_wdec | ex2_mas8_mas1_wdec - | ex2_mmucr3_wdec | ex2_mmucsr0_wdec | ex2_pesr_wdec - | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec - | ex2_xudbg0_wdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mtspr_b & ex2_tid)); - - assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( - ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re - | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re - | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re - | ex2_xucr4_re | - ex2_sprg8_re | - ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re - | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re - | ex2_cpcr5_re | ex2_dac3_re | ex2_dac4_re - | ex2_dbcr3_re | ex2_eheir_re | ex2_eptcfg_re - | ex2_iac1_re | ex2_iac2_re | ex2_iucr0_re - | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re - | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re - | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re - | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re - | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re - | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re - | ex2_mmucfg_re | ex2_mmucsr0_re | ex2_tlb0cfg_re - | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re - | ex2_xudbg1_re | ex2_xudbg2_re | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mfspr & ex2_tid)); - - assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( - ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we - | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we - | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we - | ex2_xucr4_we | - ex2_sprg8_we | - ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we - | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we - | ex2_cpcr5_we | ex2_dac3_we | ex2_dac4_we - | ex2_dbcr3_we | ex2_eheir_we | ex2_givpr_we - | ex2_hacop_we | ex2_iac1_we | ex2_iac2_we - | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we - | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we - | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we - | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we - | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we - | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mtspr & ex2_tid)); - - end - endgenerate - - generate - if (a2mode == 1 & hvmode == 0) - begin : ill_spr_10 - assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( - ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec - | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec - | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec - | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec - | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec - | ex2_xucr0_rdec | ex2_xucr4_rdec | - ex2_sprg0_rdec | ex2_sprg1_rdec | ex2_sprg2_rdec - | ex2_sprg3_rdec | ex2_sprg4_rdec | ex2_sprg5_rdec - | ex2_sprg6_rdec | ex2_sprg7_rdec | ex2_sprg8_rdec - | ex2_vrsave_rdec | - ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec - | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec - | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec - | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec - | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec - | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec - | ex2_iac1_rdec | ex2_iac2_rdec | ex2_iac3_rdec - | ex2_iac4_rdec | ex2_immr_rdec | ex2_imr_rdec - | ex2_iucr0_rdec | ex2_iucr1_rdec | ex2_iucr2_rdec - | ex2_iudbg0_rdec | ex2_iudbg1_rdec | ex2_iudbg2_rdec - | ex2_iulfsr_rdec | ex2_iullcr_rdec | ex2_ivpr_rdec - | ex2_lesr1_rdec | ex2_lesr2_rdec | ex2_lpidr_rdec - | ex2_lsucr0_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec - | ex2_mmucr2_rdec | ex2_pesr_rdec | ex2_pid_rdec - | ex2_ppr32_rdec | ex2_sramd_rdec | ex2_xucr2_rdec - | ex2_xudbg0_rdec | ex2_xudbg1_rdec | ex2_xudbg2_rdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mfspr_b & ex2_tid)); - - assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( - ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec - | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec - | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec - | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec - | ex2_xucr4_wdec | - ex2_sprg0_wdec | ex2_sprg1_wdec | ex2_sprg2_wdec - | ex2_sprg3_wdec | ex2_sprg4_wdec | ex2_sprg5_wdec - | ex2_sprg6_wdec | ex2_sprg7_wdec | ex2_sprg8_wdec - | ex2_vrsave_wdec | - ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec - | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec - | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec - | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec - | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec - | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec - | ex2_iac1_wdec | ex2_iac2_wdec | ex2_iac3_wdec - | ex2_iac4_wdec | ex2_immr_wdec | ex2_imr_wdec - | ex2_iucr0_wdec | ex2_iucr1_wdec | ex2_iucr2_wdec - | ex2_iudbg0_wdec | ex2_iulfsr_wdec | ex2_iullcr_wdec - | ex2_ivpr_wdec | ex2_lesr1_wdec | ex2_lesr2_wdec - | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mmucr0_wdec - | ex2_mmucr1_wdec | ex2_mmucr2_wdec | ex2_pesr_wdec - | ex2_pid_wdec | ex2_ppr32_wdec | ex2_xucr2_wdec - | ex2_xudbg0_wdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mtspr_b & ex2_tid)); - - assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( - ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re - | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re - | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re - | ex2_xucr4_re | - ex2_sprg8_re | - ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re - | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re - | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re - | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re - | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re - | ex2_eheir_re | ex2_iac1_re | ex2_iac2_re - | ex2_iac3_re | ex2_iac4_re | ex2_immr_re - | ex2_imr_re | ex2_iucr0_re | ex2_iucr1_re - | ex2_iucr2_re | ex2_iudbg0_re | ex2_iudbg1_re - | ex2_iudbg2_re | ex2_iulfsr_re | ex2_iullcr_re - | ex2_ivpr_re | ex2_lpidr_re | ex2_lsucr0_re - | ex2_mmucr0_re | ex2_mmucr1_re | ex2_mmucr2_re - | ex2_xucr2_re | ex2_xudbg0_re | ex2_xudbg1_re - | ex2_xudbg2_re | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mfspr & ex2_tid)); - - assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( - ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we - | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we - | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we - | ex2_xucr4_we | - ex2_sprg8_we | - ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we - | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we - | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we - | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we - | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we - | ex2_eheir_we | ex2_iac1_we | ex2_iac2_we - | ex2_iac3_we | ex2_iac4_we | ex2_immr_we - | ex2_imr_we | ex2_iucr0_we | ex2_iucr1_we - | ex2_iucr2_we | ex2_iudbg0_we | ex2_iulfsr_we - | ex2_iullcr_we | ex2_ivpr_we | ex2_lpidr_we - | ex2_lsucr0_we | ex2_mmucr0_we | ex2_mmucr1_we - | ex2_mmucr2_we | ex2_xucr2_we | ex2_xudbg0_we | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mtspr & ex2_tid)); - end - endgenerate - - generate - if (a2mode == 1 & hvmode == 1) - begin : ill_spr_11 - assign ex2_illeg_mfspr = ex2_is_mfspr_q & ~( - ex2_ccr0_rdec | ex2_ccr1_rdec | ex2_ccr2_rdec - | ex2_ccr4_rdec | ex2_cir_rdec | ex2_pir_rdec - | ex2_pvr_rdec | ex2_tb_rdec | ex2_tbu_rdec - | ex2_tenc_rdec | ex2_tens_rdec | ex2_tensr_rdec - | ex2_tir_rdec | ex2_xesr1_rdec | ex2_xesr2_rdec - | ex2_xucr0_rdec | ex2_xucr4_rdec | - ex2_gsprg0_rdec | ex2_gsprg1_rdec | ex2_gsprg2_rdec - | ex2_gsprg3_rdec | ex2_sprg0_rdec | ex2_sprg1_rdec - | ex2_sprg2_rdec | ex2_sprg3_rdec | ex2_sprg4_rdec - | ex2_sprg5_rdec | ex2_sprg6_rdec | ex2_sprg7_rdec - | ex2_sprg8_rdec | ex2_vrsave_rdec | - ex2_acop_rdec | ex2_axucr0_rdec | ex2_cpcr0_rdec - | ex2_cpcr1_rdec | ex2_cpcr2_rdec | ex2_cpcr3_rdec - | ex2_cpcr4_rdec | ex2_cpcr5_rdec | ex2_dac1_rdec - | ex2_dac2_rdec | ex2_dac3_rdec | ex2_dac4_rdec - | ex2_dbcr2_rdec | ex2_dbcr3_rdec | ex2_dscr_rdec - | ex2_dvc1_rdec | ex2_dvc2_rdec | ex2_eheir_rdec - | ex2_eplc_rdec | ex2_epsc_rdec | ex2_eptcfg_rdec - | ex2_givpr_rdec | ex2_hacop_rdec | ex2_iac1_rdec - | ex2_iac2_rdec | ex2_iac3_rdec | ex2_iac4_rdec - | ex2_immr_rdec | ex2_imr_rdec | ex2_iucr0_rdec - | ex2_iucr1_rdec | ex2_iucr2_rdec | ex2_iudbg0_rdec - | ex2_iudbg1_rdec | ex2_iudbg2_rdec | ex2_iulfsr_rdec - | ex2_iullcr_rdec | ex2_ivpr_rdec | ex2_lesr1_rdec - | ex2_lesr2_rdec | ex2_lper_rdec | ex2_lperu_rdec - | ex2_lpidr_rdec | ex2_lratcfg_rdec | ex2_lratps_rdec - | ex2_lsucr0_rdec | ex2_mas0_rdec | ex2_mas0_mas1_rdec - | ex2_mas1_rdec | ex2_mas2_rdec | ex2_mas2u_rdec - | ex2_mas3_rdec | ex2_mas4_rdec | ex2_mas5_rdec - | ex2_mas5_mas6_rdec | ex2_mas6_rdec | ex2_mas7_rdec - | ex2_mas7_mas3_rdec | ex2_mas8_rdec | ex2_mas8_mas1_rdec - | ex2_mmucfg_rdec | ex2_mmucr0_rdec | ex2_mmucr1_rdec - | ex2_mmucr2_rdec | ex2_mmucr3_rdec | ex2_mmucsr0_rdec - | ex2_pesr_rdec | ex2_pid_rdec | ex2_ppr32_rdec - | ex2_sramd_rdec | ex2_tlb0cfg_rdec | ex2_tlb0ps_rdec - | ex2_xucr2_rdec | ex2_xudbg0_rdec | ex2_xudbg1_rdec - | ex2_xudbg2_rdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mfspr_b & ex2_tid)); - - assign ex2_illeg_mtspr = ex2_is_mtspr_q & ~( - ex2_ccr0_wdec | ex2_ccr1_wdec | ex2_ccr2_wdec - | ex2_ccr4_wdec | ex2_tbl_wdec | ex2_tbu_wdec - | ex2_tenc_wdec | ex2_tens_wdec | ex2_trace_wdec - | ex2_xesr1_wdec | ex2_xesr2_wdec | ex2_xucr0_wdec - | ex2_xucr4_wdec | - ex2_gsprg0_wdec | ex2_gsprg1_wdec | ex2_gsprg2_wdec - | ex2_gsprg3_wdec | ex2_sprg0_wdec | ex2_sprg1_wdec - | ex2_sprg2_wdec | ex2_sprg3_wdec | ex2_sprg4_wdec - | ex2_sprg5_wdec | ex2_sprg6_wdec | ex2_sprg7_wdec - | ex2_sprg8_wdec | ex2_vrsave_wdec | - ex2_acop_wdec | ex2_axucr0_wdec | ex2_cpcr0_wdec - | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec - | ex2_cpcr4_wdec | ex2_cpcr5_wdec | ex2_dac1_wdec - | ex2_dac2_wdec | ex2_dac3_wdec | ex2_dac4_wdec - | ex2_dbcr2_wdec | ex2_dbcr3_wdec | ex2_dscr_wdec - | ex2_dvc1_wdec | ex2_dvc2_wdec | ex2_eheir_wdec - | ex2_eplc_wdec | ex2_epsc_wdec | ex2_givpr_wdec - | ex2_hacop_wdec | ex2_iac1_wdec | ex2_iac2_wdec - | ex2_iac3_wdec | ex2_iac4_wdec | ex2_immr_wdec - | ex2_imr_wdec | ex2_iucr0_wdec | ex2_iucr1_wdec - | ex2_iucr2_wdec | ex2_iudbg0_wdec | ex2_iulfsr_wdec - | ex2_iullcr_wdec | ex2_ivpr_wdec | ex2_lesr1_wdec - | ex2_lesr2_wdec | ex2_lper_wdec | ex2_lperu_wdec - | ex2_lpidr_wdec | ex2_lsucr0_wdec | ex2_mas0_wdec - | ex2_mas0_mas1_wdec | ex2_mas1_wdec | ex2_mas2_wdec - | ex2_mas2u_wdec | ex2_mas3_wdec | ex2_mas4_wdec - | ex2_mas5_wdec | ex2_mas5_mas6_wdec | ex2_mas6_wdec - | ex2_mas7_wdec | ex2_mas7_mas3_wdec | ex2_mas8_wdec - | ex2_mas8_mas1_wdec | ex2_mmucr0_wdec | ex2_mmucr1_wdec - | ex2_mmucr2_wdec | ex2_mmucr3_wdec | ex2_mmucsr0_wdec - | ex2_pesr_wdec | ex2_pid_wdec | ex2_ppr32_wdec - | ex2_xucr2_wdec | ex2_xudbg0_wdec | - ex2_slowspr_range | - |(tspr_cspr_illeg_mtspr_b & ex2_tid)); - - assign ex2_hypv_mfspr = ex2_is_mfspr_q & ( - ex2_ccr0_re | ex2_ccr1_re | ex2_ccr2_re - | ex2_ccr4_re | ex2_tenc_re | ex2_tens_re - | ex2_tensr_re | ex2_tir_re | ex2_xucr0_re - | ex2_xucr4_re | - ex2_sprg8_re | - ex2_axucr0_re | ex2_cpcr0_re | ex2_cpcr1_re - | ex2_cpcr2_re | ex2_cpcr3_re | ex2_cpcr4_re - | ex2_cpcr5_re | ex2_dac1_re | ex2_dac2_re - | ex2_dac3_re | ex2_dac4_re | ex2_dbcr2_re - | ex2_dbcr3_re | ex2_dvc1_re | ex2_dvc2_re - | ex2_eheir_re | ex2_eptcfg_re | ex2_iac1_re - | ex2_iac2_re | ex2_iac3_re | ex2_iac4_re - | ex2_immr_re | ex2_imr_re | ex2_iucr0_re - | ex2_iucr1_re | ex2_iucr2_re | ex2_iudbg0_re - | ex2_iudbg1_re | ex2_iudbg2_re | ex2_iulfsr_re - | ex2_iullcr_re | ex2_ivpr_re | ex2_lper_re - | ex2_lperu_re | ex2_lpidr_re | ex2_lratcfg_re - | ex2_lratps_re | ex2_lsucr0_re | ex2_mas5_re - | ex2_mas5_mas6_re | ex2_mas8_re | ex2_mas8_mas1_re - | ex2_mmucfg_re | ex2_mmucr0_re | ex2_mmucr1_re - | ex2_mmucr2_re | ex2_mmucsr0_re | ex2_tlb0cfg_re - | ex2_tlb0ps_re | ex2_xucr2_re | ex2_xudbg0_re - | ex2_xudbg1_re | ex2_xudbg2_re | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mfspr & ex2_tid)); - - assign ex2_hypv_mtspr = ex2_is_mtspr_q & ( - ex2_ccr0_we | ex2_ccr1_we | ex2_ccr2_we - | ex2_ccr4_we | ex2_tbl_we | ex2_tbu_we - | ex2_tenc_we | ex2_tens_we | ex2_xucr0_we - | ex2_xucr4_we | - ex2_sprg8_we | - ex2_axucr0_we | ex2_cpcr0_we | ex2_cpcr1_we - | ex2_cpcr2_we | ex2_cpcr3_we | ex2_cpcr4_we - | ex2_cpcr5_we | ex2_dac1_we | ex2_dac2_we - | ex2_dac3_we | ex2_dac4_we | ex2_dbcr2_we - | ex2_dbcr3_we | ex2_dvc1_we | ex2_dvc2_we - | ex2_eheir_we | ex2_givpr_we | ex2_hacop_we - | ex2_iac1_we | ex2_iac2_we | ex2_iac3_we - | ex2_iac4_we | ex2_immr_we | ex2_imr_we - | ex2_iucr0_we | ex2_iucr1_we | ex2_iucr2_we - | ex2_iudbg0_we | ex2_iulfsr_we | ex2_iullcr_we - | ex2_ivpr_we | ex2_lper_we | ex2_lperu_we - | ex2_lpidr_we | ex2_lsucr0_we | ex2_mas5_we - | ex2_mas5_mas6_we | ex2_mas8_we | ex2_mas8_mas1_we - | ex2_mmucr0_we | ex2_mmucr1_we | ex2_mmucr2_we - | ex2_mmucsr0_we | ex2_xucr2_we | ex2_xudbg0_we | - ex2_slowspr_range_hypv | - |(tspr_cspr_hypv_mtspr & ex2_tid)); - end - endgenerate - - assign ex1_dnh = ex1_valid & ex1_is_dnh & spr_ccr4_en_dnh; - - assign ex3_wait_flush_d = |ex2_wait_flush; - - assign ex2_np1_flush = (ex2_ccr0_flush | ex2_tenc_flush | ex2_xucr0_flush) & ex2_tid; - - assign ex3_np1_flush_d = (|tspr_cspr_ex2_np1_flush) | |(ex2_np1_flush) | ex2_dnh_q | (ex2_is_mtspr_q & (ex2_ccr2_wdec | ex2_cpcr0_wdec | ex2_cpcr1_wdec | ex2_cpcr2_wdec | ex2_cpcr3_wdec | ex2_cpcr4_wdec | ex2_cpcr5_wdec |ex2_pid_wdec | ex2_lpidr_wdec | ex2_mmucr1_wdec | ex2_xucr0_wdec | ex2_iucr2_wdec | ex2_mmucsr0_wdec)) | ex2_is_mtmsr_q; - - assign ex4_np1_flush_d = ex3_spr_we & ex3_np1_flush_q; - assign ex4_wait_flush_d = ex3_spr_we & ex3_wait_flush_q; - - assign ex2_msr_pr = |(ex2_tid & tspr_msr_pr); - assign ex2_msr_gs = |(ex2_tid & tspr_msr_gs); - - assign ex3_hypv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (~ex2_msr_pr) & ex2_msr_gs & (ex2_hypv_mfspr | ex2_hypv_mtspr | ex2_hypv_instr_q); - - assign ex3_illeg_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & (((ex2_illeg_mfspr | ex2_illeg_mtspr | ex2_illeg_mftb) & ~(ex2_instr_q[11] & ex2_msr_pr)) | (ex2_hypv_instr_q & ~spr_ccr2_en_pc)); - - assign ex3_priv_spr_d = (ex2_val_rd_q | ex2_val_wr_q) & ex2_msr_pr & ((ex2_instr_q[11] & (ex2_is_mtspr_q | ex2_is_mfspr_q)) | ex2_priv_instr_q); - - assign spr_ccr0_pme = ccr0_q[62:63]; - assign spr_ccr0_we = ccr0_we; - assign spr_ccr2_en_dcr = spr_ccr2_en_dcr_int; - assign spr_ccr2_en_dcr_int = ccr2_q[32]; - assign spr_ccr2_en_trace = ccr2_q[33]; - assign spr_ccr2_en_pc = ccr2_q[34]; - assign spr_ccr2_ifratsc = ccr2_q[35:43]; - assign spr_ccr2_ifrat = ccr2_q[44]; - assign spr_ccr2_dfratsc = ccr2_q[45:53]; - assign spr_ccr2_dfrat = ccr2_q[54]; - assign spr_ccr2_ucode_dis = ccr2_q[55]; - assign spr_ccr2_ap = ccr2_q[56:59]; - assign spr_ccr2_en_attn = ccr2_q[60]; - assign spr_ccr2_en_ditc = ccr2_q[61]; - assign spr_ccr2_en_icswx = ccr2_q[62]; - assign spr_ccr2_notlb = ccr2_q[63]; - assign spr_ccr4_en_dnh = ccr4_q[63]; - assign spr_tens_ten = tens_q[64-(`THREADS):63]; - assign spr_xucr0_clkg_ctl = xucr0_q[38:42]; - assign spr_xucr0_trace_um = xucr0_q[43:46]; - assign xu_lsu_spr_xucr0_mbar_ack = xucr0_q[47]; - assign xu_lsu_spr_xucr0_tlbsync = xucr0_q[48]; - assign spr_xucr0_cls = xucr0_q[49]; - assign xu_lsu_spr_xucr0_aflsta = xucr0_q[50]; - assign spr_xucr0_mddp = xucr0_q[51]; - assign xu_lsu_spr_xucr0_cred = xucr0_q[52]; - assign xu_lsu_spr_xucr0_rel = xucr0_q[53]; - assign spr_xucr0_mdcp = xucr0_q[54]; - assign spr_xucr0_tcs = xucr0_q[55]; - assign xu_lsu_spr_xucr0_flsta = xucr0_q[56]; - assign xu_lsu_spr_xucr0_l2siw = xucr0_q[57]; - assign xu_lsu_spr_xucr0_flh2l2 = xucr0_q[58]; - assign xu_lsu_spr_xucr0_dcdis = xucr0_q[59]; - assign xu_lsu_spr_xucr0_wlk = xucr0_q[60]; - assign spr_xucr4_mmu_mchk = xucr4_q[60]; - assign spr_xucr4_mddmh = xucr4_q[61]; - assign spr_xucr4_tcd = xucr4_q[62:63]; - assign xucr0_clfc_d = ex3_xucr0_we & ex3_spr_wd[63]; - assign xu_lsu_spr_xucr0_clfc = xucr0_clfc_q; - assign cspr_ccr2_en_pc = spr_ccr2_en_pc; - assign cspr_ccr4_en_dnh = spr_ccr4_en_dnh; - - // CCR0 - assign ex3_ccr0_di = { ex3_spr_wd[32:33] }; //PME - - assign ccr0_do = { tidn[0:0] , - tidn[0:31] , ///// - ccr0_q[62:63] , //PME - tidn[34:51] , ///// - 4'b0000 , //WEM - tidn[56:59] , ///// - ccr0_we }; //WE - // CCR1 - assign ex3_ccr1_di = { ex3_spr_wd[34:39] , //WC3 - ex3_spr_wd[42:47] , //WC2 - ex3_spr_wd[50:55] , //WC1 - ex3_spr_wd[58:63] }; //WC0 - - assign ccr1_do = { tidn[0:0] , - tidn[0:31] , ///// - tidn[32:33] , ///// - ccr1_q[40:45] , //WC3 - tidn[40:41] , ///// - ccr1_q[46:51] , //WC2 - tidn[48:49] , ///// - ccr1_q[52:57] , //WC1 - tidn[56:57] , ///// - ccr1_q[58:63] }; //WC0 - // CCR2 - assign ex3_ccr2_di = { ex3_spr_wd[32:32] , //EN_DCR - ex3_spr_wd[33:33] , //EN_TRACE - ex3_spr_wd[34:34] , //EN_PC - ex3_spr_wd[35:43] , //IFRATSC - ex3_spr_wd[44:44] , //IFRAT - ex3_spr_wd[45:53] , //DFRATSC - ex3_spr_wd[54:54] , //DFRAT - ex3_spr_wd[55:55] , //UCODE_DIS - ex3_spr_wd[56:59] , //AP - ex3_spr_wd[60:60] , //EN_ATTN - ex3_spr_wd[61:61] , //EN_DITC - ex3_spr_wd[62:62] , //EN_ICSWX - ex3_spr_wd[63:63] }; //NOTLB - - assign ccr2_do = { tidn[0:0] , - tidn[0:31] , ///// - ccr2_q[32:32] , //EN_DCR - ccr2_q[33:33] , //EN_TRACE - ccr2_q[34:34] , //EN_PC - ccr2_q[35:43] , //IFRATSC - ccr2_q[44:44] , //IFRAT - ccr2_q[45:53] , //DFRATSC - ccr2_q[54:54] , //DFRAT - ccr2_q[55:55] , //UCODE_DIS - ccr2_q[56:59] , //AP - ccr2_q[60:60] , //EN_ATTN - ccr2_q[61:61] , //EN_DITC - ccr2_q[62:62] , //EN_ICSWX - ccr2_q[63:63] }; //NOTLB - // CCR4 - assign ex3_ccr4_di = { ex3_spr_wd[63:63] }; //EN_DNH - - assign ccr4_do = { tidn[0:0] , - tidn[0:31] , ///// - tidn[32:62] , ///// - ccr4_q[63:63] }; //EN_DNH - // CIR - assign cir_do = { tidn[0:0] , - tidn[0:31] , ///// - an_ac_chipid_dc[32:35] , //ID - tidn[36:63] }; ///// - // PIR - assign pir_do = { tidn[0:0] , - tidn[0:31] , ///// - tidn[32:53] , ///// - an_ac_coreid_q[54:61] , //CID - ex2_tid_q[0:1] }; //TID - // PVR - assign pvr_do = { tidn[0:0] , - tidn[0:31] , ///// - version[32:47] , //VERSION - revision[48:63] }; //REVISION - // TB - assign tb_do = { tidn[0:0] , - tbu_q[32:63] , //TBU - tbl_q[32:63] }; //TBL - // TBL - assign ex3_tbl_di = { ex3_spr_wd[32:63] }; //TBL - - assign tbl_do = { tidn[0:0] , - tidn[0:31] , ///// - tbl_q[32:63] }; //TBL - // TBU - assign ex3_tbu_di = { ex3_spr_wd[32:63] }; //TBU - - assign tbu_do = { tidn[0:0] , - tidn[0:31] , ///// - tbu_q[32:63] }; //TBU - // TENC - assign tenc_do = { tidn[0:64-`THREADS] , - tens_q[64-`THREADS:63] }; //TEN - // TENS - assign ex3_tens_di = { ex3_spr_wd[64-(`THREADS):63] }; //TEN - - assign tens_do = { tidn[0:64-(`THREADS)] , - tens_q[64-(`THREADS):63] }; //TEN - // TENSR - assign tensr_do = { tidn[0:64-`THREADS] , - spr_tensr[0:`THREADS-1] }; //TENSR - // TIR - assign tir_do = { tidn[0:0] , - tidn[0:31] , ///// - tidn[32:61] , ///// - ex2_tid_q[0:1] }; //TID - // XESR1 - assign ex3_xesr1_di = { ex3_spr_wd[32:35] , //MUXSELEB0 - ex3_spr_wd[36:39] , //MUXSELEB1 - ex3_spr_wd[40:43] , //MUXSELEB2 - ex3_spr_wd[44:47] , //MUXSELEB3 - ex3_spr_wd[48:51] , //MUXSELEB4 - ex3_spr_wd[52:55] , //MUXSELEB5 - ex3_spr_wd[56:59] , //MUXSELEB6 - ex3_spr_wd[60:63] }; //MUXSELEB7 - - assign xesr1_do = { tidn[0:0] , - tidn[0:31] , ///// - xesr1_q[32:35] , //MUXSELEB0 - xesr1_q[36:39] , //MUXSELEB1 - xesr1_q[40:43] , //MUXSELEB2 - xesr1_q[44:47] , //MUXSELEB3 - xesr1_q[48:51] , //MUXSELEB4 - xesr1_q[52:55] , //MUXSELEB5 - xesr1_q[56:59] , //MUXSELEB6 - xesr1_q[60:63] }; //MUXSELEB7 - // XESR2 - assign ex3_xesr2_di = { ex3_spr_wd[32:35] , //MUXSELEB0 - ex3_spr_wd[36:39] , //MUXSELEB1 - ex3_spr_wd[40:43] , //MUXSELEB2 - ex3_spr_wd[44:47] , //MUXSELEB3 - ex3_spr_wd[48:51] , //MUXSELEB4 - ex3_spr_wd[52:55] , //MUXSELEB5 - ex3_spr_wd[56:59] , //MUXSELEB6 - ex3_spr_wd[60:63] }; //MUXSELEB7 - - assign xesr2_do = { tidn[0:0] , - tidn[0:31] , ///// - xesr2_q[32:35] , //MUXSELEB0 - xesr2_q[36:39] , //MUXSELEB1 - xesr2_q[40:43] , //MUXSELEB2 - xesr2_q[44:47] , //MUXSELEB3 - xesr2_q[48:51] , //MUXSELEB4 - xesr2_q[52:55] , //MUXSELEB5 - xesr2_q[56:59] , //MUXSELEB6 - xesr2_q[60:63] }; //MUXSELEB7 - // XUCR0 - assign ex3_xucr0_di = { ex3_spr_wd[32:36] , //CLKG_CTL - ex3_spr_wd[37:40] , //TRACE_UM - ex3_spr_wd[41:41] , //MBAR_ACK - ex3_spr_wd[42:42] , //TLBSYNC - xucr0_q[49:49] , //CLS - ex3_spr_wd[49:49] , //AFLSTA - ex3_spr_wd[50:50] , //MDDP - ex3_spr_wd[51:51] , //CRED - xucr0_q[53:53] , //REL - ex3_spr_wd[53:53] , //MDCP - ex3_spr_wd[54:54] , //TCS - ex3_spr_wd[55:55] , //FLSTA - xucr0_q[57:57] , //L2SIW - xucr0_q[58:58] , //FLH2L2 - ex3_spr_wd[58:58] , //DCDIS - ex3_spr_wd[59:59] , //WLK - ex3_spr_wd[60:60] , //CSLC - ex3_spr_wd[61:61] , //CUL - ex3_spr_wd[62:62] }; //CLO - - assign xucr0_do = { tidn[0:0] , - tidn[0:31] , ///// - xucr0_q[38:42] , //CLKG_CTL - xucr0_q[43:46] , //TRACE_UM - xucr0_q[47:47] , //MBAR_ACK - xucr0_q[48:48] , //TLBSYNC - tidn[43:47] , ///// - xucr0_q[49:49] , //CLS - xucr0_q[50:50] , //AFLSTA - xucr0_q[51:51] , //MDDP - xucr0_q[52:52] , //CRED - xucr0_q[53:53] , //REL - xucr0_q[54:54] , //MDCP - xucr0_q[55:55] , //TCS - xucr0_q[56:56] , //FLSTA - xucr0_q[57:57] , //L2SIW - xucr0_q[58:58] , //FLH2L2 - xucr0_q[59:59] , //DCDIS - xucr0_q[60:60] , //WLK - xucr0_q[61:61] , //CSLC - xucr0_q[62:62] , //CUL - xucr0_q[63:63] , //CLO - 1'b0 }; //CLFC - // XUCR4 - assign ex3_xucr4_di = { ex3_spr_wd[46:46] , //MMU_MCHK - ex3_spr_wd[47:47] , //MDDMH - ex3_spr_wd[56:57] }; //TCD - - assign xucr4_do = { tidn[0:0] , - tidn[0:31] , ///// - tidn[32:45] , ///// - xucr4_q[60:60] , //MMU_MCHK - xucr4_q[61:61] , //MDDMH - tidn[48:55] , ///// - xucr4_q[62:63] , //TCD - tidn[58:63] }; ///// - - // Unused Signals - assign unused_do_bits = |{ - ccr0_do[0:64-`GPR_WIDTH] - ,ccr1_do[0:64-`GPR_WIDTH] - ,ccr2_do[0:64-`GPR_WIDTH] - ,ccr4_do[0:64-`GPR_WIDTH] - ,cir_do[0:64-`GPR_WIDTH] - ,pir_do[0:64-`GPR_WIDTH] - ,pvr_do[0:64-`GPR_WIDTH] - ,tb_do[0:64-`GPR_WIDTH] - ,tbl_do[0:64-`GPR_WIDTH] - ,tbu_do[0:64-`GPR_WIDTH] - ,tenc_do[0:64-`GPR_WIDTH] - ,tens_do[0:64-`GPR_WIDTH] - ,tensr_do[0:64-`GPR_WIDTH] - ,tir_do[0:64-`GPR_WIDTH] - ,xesr1_do[0:64-`GPR_WIDTH] - ,xesr2_do[0:64-`GPR_WIDTH] - ,xucr0_do[0:64-`GPR_WIDTH] - ,xucr4_do[0:64-`GPR_WIDTH] - }; - - tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(ccr0_act), - .force_t(bcfg_slp_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(bcfg_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), - .scout(sov_bcfg[ccr0_offset_bcfg:ccr0_offset_bcfg + 2 - 1]), - .din(ccr0_d), - .dout(ccr0_q) - ); - tri_ser_rlmreg_p #(.WIDTH(24), .INIT(3994575), .NEEDS_SRESET(1)) ccr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(ccr1_act), - .force_t(func_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ccr1_offset:ccr1_offset + 24 - 1]), - .scout(sov[ccr1_offset:ccr1_offset + 24 - 1]), - .din(ccr1_d), - .dout(ccr1_q) - ); - tri_ser_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) ccr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(ccr2_act), - .force_t(ccfg_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(ccfg_sl_thold_0_b), - .sg(sg_0), - .scin(siv_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), - .scout(sov_ccfg[ccr2_offset_ccfg:ccr2_offset_ccfg + 32 - 1]), - .din(ccr2_d), - .dout(ccr2_q) - ); - tri_ser_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccr4_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(ccr4_act), - .force_t(ccfg_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(ccfg_sl_thold_0_b), - .sg(sg_0), - .scin(siv_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), - .scout(sov_ccfg[ccr4_offset_ccfg:ccr4_offset_ccfg + 1 - 1]), - .din(ccr4_d), - .dout(ccr4_q) - ); - tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbl_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(tbl_act), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tbl_offset:tbl_offset + 32 - 1]), - .scout(sov[tbl_offset:tbl_offset + 32 - 1]), - .din(tbl_d), - .dout(tbl_q) - ); - tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbu_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(tbu_act), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tbu_offset:tbu_offset + 32 - 1]), - .scout(sov[tbu_offset:tbu_offset + 32 - 1]), - .din(tbu_d), - .dout(tbu_q) - ); - tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) tens_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(tens_act), - .force_t(bcfg_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(bcfg_sl_thold_0_b), - .sg(sg_0), - .scin(siv_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), - .scout(sov_bcfg[tens_offset_bcfg:tens_offset_bcfg + `THREADS - 1]), - .din(tens_d), - .dout(tens_q) - ); - tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(xesr1_act), - .force_t(func_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[xesr1_offset:xesr1_offset + 32 - 1]), - .scout(sov[xesr1_offset:xesr1_offset + 32 - 1]), - .din(xesr1_d), - .dout(xesr1_q) - ); - tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(xesr2_act), - .force_t(func_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[xesr2_offset:xesr2_offset + 32 - 1]), - .scout(sov[xesr2_offset:xesr2_offset + 32 - 1]), - .din(xesr2_d), - .dout(xesr2_q) - ); - tri_ser_rlmreg_p #(.WIDTH(26), .INIT((spr_xucr0_init)), .NEEDS_SRESET(1)) xucr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(xucr0_act), - .force_t(ccfg_slp_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(ccfg_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), - .scout(sov_ccfg[xucr0_offset_ccfg:xucr0_offset_ccfg + 26 - 1]), - .din(xucr0_d), - .dout(xucr0_q) - ); - tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xucr4_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), - .act(xucr4_act), - .force_t(dcfg_sl_force), - .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), - .mpw1_b(mpw1_dc_b[DWR]),.mpw2_b(mpw2_dc_b), - .thold_b(dcfg_sl_thold_0_b), - .sg(sg_0), - .scin(siv_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), - .scout(sov_dcfg[xucr4_offset_dcfg:xucr4_offset_dcfg + 4 - 1]), - .din(xucr4_d), - .dout(xucr4_q) - ); - - - - // Latch Instances - tri_rlmreg_p #(.WIDTH(4), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[exx_act_offset : exx_act_offset + 4-1]), - .scout(sov[exx_act_offset : exx_act_offset + 4-1]), - .din(exx_act_d), - .dout(exx_act_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), - .mpw1_b(mpw1_dc_b[DEX0]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex0_val_offset : ex0_val_offset + `THREADS-1]), - .scout(sov[ex0_val_offset : ex0_val_offset + `THREADS-1]), - .din(rv2_val), - .dout(ex0_val_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex1_val_offset : ex1_val_offset + `THREADS-1]), - .scout(sov[ex1_val_offset : ex1_val_offset + `THREADS-1]), - .din(ex0_val), - .dout(ex1_val_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex1_aspr_act_offset]), - .scout(sov[ex1_aspr_act_offset]), - .din(ex1_aspr_act_d), - .dout(ex1_aspr_act_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[0]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), - .scout(sov[ex1_aspr_tid_offset : ex1_aspr_tid_offset + 2-1]), - .din(ex1_aspr_tid_d), - .dout(ex1_aspr_tid_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[0]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex1_tid_offset : ex1_tid_offset + 2-1]), - .scout(sov[ex1_tid_offset : ex1_tid_offset + 2-1]), - .din(ex0_tid), - .dout(ex1_tid_q) - ); - tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[0]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex1_instr_offset : ex1_instr_offset + 32-1]), - .scout(sov[ex1_instr_offset : ex1_instr_offset + 32-1]), - .din(rv_xu_ex0_instr), - .dout(ex1_instr_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex1_msr_gs_offset]), - .scout(sov[ex1_msr_gs_offset]), - .din(ex1_msr_gs_d), - .dout(ex1_msr_gs_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_val_offset : ex2_val_offset + `THREADS-1]), - .scout(sov[ex2_val_offset : ex2_val_offset + `THREADS-1]), - .din(ex1_val), - .dout(ex2_val_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_rd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_val_rd_offset]), - .scout(sov[ex2_val_rd_offset]), - .din(ex2_val_rd_d), - .dout(ex2_val_rd_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_wr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_val_wr_offset]), - .scout(sov[ex2_val_wr_offset]), - .din(ex2_val_wr_d), - .dout(ex2_val_wr_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_tid_offset : ex2_tid_offset + 2-1]), - .scout(sov[ex2_tid_offset : ex2_tid_offset + 2-1]), - .din(ex1_tid_q), - .dout(ex2_tid_q) - ); - tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), - .scout(sov[ex2_aspr_addr_offset : ex2_aspr_addr_offset + 4-1]), - .din(ex1_aspr_addr), - .dout(ex2_aspr_addr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_mfspr_offset]), - .scout(sov[ex2_is_mfspr_offset]), - .din(ex1_is_mfspr), - .dout(ex2_is_mfspr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mftb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_mftb_offset]), - .scout(sov[ex2_is_mftb_offset]), - .din(ex1_is_mftb), - .dout(ex2_is_mftb_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_mtmsr_offset]), - .scout(sov[ex2_is_mtmsr_offset]), - .din(ex2_is_mtmsr_d), - .dout(ex2_is_mtmsr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_mtspr_offset]), - .scout(sov[ex2_is_mtspr_offset]), - .din(ex1_is_mtspr), - .dout(ex2_is_mtspr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_wait_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_wait_offset]), - .scout(sov[ex2_is_wait_offset]), - .din(ex1_is_wait), - .dout(ex2_is_wait_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_priv_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_priv_instr_offset]), - .scout(sov[ex2_priv_instr_offset]), - .din(ex1_priv_instr), - .dout(ex2_priv_instr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_hypv_instr_offset]), - .scout(sov[ex2_hypv_instr_offset]), - .din(ex1_hypv_instr), - .dout(ex2_hypv_instr_q) - ); - tri_regk #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex2_wait_wc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), - .scout(sov[ex2_wait_wc_offset : ex2_wait_wc_offset + 2-1]), - .din(ex1_instr_q[9:10]), - .dout(ex2_wait_wc_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_msgclr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_is_msgclr_offset]), - .scout(sov[ex2_is_msgclr_offset]), - .din(ex1_is_msgclr), - .dout(ex2_is_msgclr_q) - ); - tri_regk #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_instr_offset : ex2_instr_offset + 10-1]), - .scout(sov[ex2_instr_offset : ex2_instr_offset + 10-1]), - .din(ex2_instr_d), - .dout(ex2_instr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_msr_gs_offset]), - .scout(sov[ex2_msr_gs_offset]), - .din(ex1_msr_gs_q), - .dout(ex2_msr_gs_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tenc_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_tenc_we_offset]), - .scout(sov[ex2_tenc_we_offset]), - .din(ex1_tenc_we), - .dout(ex2_tenc_we_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ccr0_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_ccr0_we_offset]), - .scout(sov[ex2_ccr0_we_offset]), - .din(ex1_ccr0_we), - .dout(ex2_ccr0_we_q) - ); - tri_regk #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), - .scout(sov[ex2_aspr_re_offset : ex2_aspr_re_offset + `GPR_WIDTH/32-1]), - .din(ex1_aspr_re), - .dout(ex2_aspr_re_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex2_dnh_offset]), - .scout(sov[ex2_dnh_offset]), - .din(ex1_dnh), - .dout(ex2_dnh_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_val_offset : ex3_val_offset + `THREADS-1]), - .scout(sov[ex3_val_offset : ex3_val_offset + `THREADS-1]), - .din(ex2_val), - .dout(ex3_val_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_rd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_val_rd_offset]), - .scout(sov[ex3_val_rd_offset]), - .din(ex3_val_rd_d), - .dout(ex3_val_rd_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_wr_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_sspr_wr_val_offset]), - .scout(sov[ex3_sspr_wr_val_offset]), - .din(ex2_sspr_wr_val), - .dout(ex3_sspr_wr_val_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_rd_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_sspr_rd_val_offset]), - .scout(sov[ex3_sspr_rd_val_offset]), - .din(ex2_sspr_rd_val), - .dout(ex3_sspr_rd_val_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_spr_we_offset]), - .scout(sov[ex3_spr_we_offset]), - .din(ex3_spr_we_d), - .dout(ex3_spr_we_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_aspr_we_offset]), - .scout(sov[ex3_aspr_we_offset]), - .din(ex3_aspr_we_d), - .dout(ex3_aspr_we_q) - ); - tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(ex2_aspr_addr_act), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), - .scout(sov[ex3_aspr_addr_offset : ex3_aspr_addr_offset + 4-1]), - .din(ex3_aspr_addr_d), - .dout(ex3_aspr_addr_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_tid_offset : ex3_tid_offset + 2-1]), - .scout(sov[ex3_tid_offset : ex3_tid_offset + 2-1]), - .din(ex2_tid_q), - .dout(ex3_tid_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_rdata_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act_data[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), - .scout(sov[ex3_aspr_rdata_offset : ex3_aspr_rdata_offset + `GPR_WIDTH+8-1]), - .din(ex3_aspr_rdata_d), - .dout(ex3_aspr_rdata_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_is_mtspr_offset]), - .scout(sov[ex3_is_mtspr_offset]), - .din(ex2_is_mtspr_q), - .dout(ex3_is_mtspr_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex3_wait_wc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), - .scout(sov[ex3_wait_wc_offset : ex3_wait_wc_offset + 2-1]), - .din(ex2_wait_wc_q), - .dout(ex3_wait_wc_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_msgclr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_is_msgclr_offset]), - .scout(sov[ex3_is_msgclr_offset]), - .din(ex2_is_msgclr_q), - .dout(ex3_is_msgclr_q) - ); - tri_rlmreg_p #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_instr_offset : ex3_instr_offset + 10-1]), - .scout(sov[ex3_instr_offset : ex3_instr_offset + 10-1]), - .din(ex3_instr_d), - .dout(ex3_instr_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_cspr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act_data[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), - .scout(sov[ex3_cspr_rt_offset : ex3_cspr_rt_offset + `GPR_WIDTH-1]), - .din(ex2_cspr_rt), - .dout(ex3_cspr_rt_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_hypv_spr_offset]), - .scout(sov[ex3_hypv_spr_offset]), - .din(ex3_hypv_spr_d), - .dout(ex3_hypv_spr_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_illeg_spr_offset]), - .scout(sov[ex3_illeg_spr_offset]), - .din(ex3_illeg_spr_d), - .dout(ex3_illeg_spr_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_priv_spr_offset]), - .scout(sov[ex3_priv_spr_offset]), - .din(ex3_priv_spr_d), - .dout(ex3_priv_spr_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(ex3_rt_act), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), - .scout(sov[ex3_rt_offset : ex3_rt_offset + `GPR_WIDTH+8-1]), - .din(ex3_rt_d), - .dout(ex3_rt_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_wait_offset]), - .scout(sov[ex3_wait_offset]), - .din(ex2_is_wait_q), - .dout(ex3_wait_q) - ); - tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_ce_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), - .scout(sov[ex3_aspr_ce_addr_offset : ex3_aspr_ce_addr_offset + 4-1]), - .din(ex2_aspr_addr_q), - .dout(ex3_aspr_ce_addr_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), - .scout(sov[ex3_aspr_re_offset : ex3_aspr_re_offset + `GPR_WIDTH/32-1]), - .din(ex2_aspr_re_q), - .dout(ex3_aspr_re_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_val_offset : ex4_val_offset + `THREADS-1]), - .scout(sov[ex4_val_offset : ex4_val_offset + `THREADS-1]), - .din(ex3_val), - .dout(ex4_val_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[3]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), - .scout(sov[ex4_aspr_re_offset : ex4_aspr_re_offset + `GPR_WIDTH/32-1]), - .din(ex3_aspr_re_q), - .dout(ex4_aspr_re_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_spr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act_data[3]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), - .scout(sov[ex4_spr_rt_offset : ex4_spr_rt_offset + `GPR_WIDTH-1]), - .din(ex3_spr_rt), - .dout(ex4_spr_rt_q) - ); - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_corr_rdata_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act_data[3]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), - .scout(sov[ex4_corr_rdata_offset : ex4_corr_rdata_offset + `GPR_WIDTH-1]), - .din(ex3_corr_rdata), - .dout(ex4_corr_rdata_q) - ); - tri_regk #(.WIDTH(`GPR_WIDTH/8+1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), - .scout(sov[ex4_sprg_ce_offset : ex4_sprg_ce_offset + `GPR_WIDTH/8+1-1]), - .din(ex4_sprg_ce_d), - .dout(ex4_sprg_ce_q) - ); - tri_regk #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_ce_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(ex3_sprg_ce), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), - .scout(sov[ex4_aspr_ce_addr_offset : ex4_aspr_ce_addr_offset + 4-1]), - .din(ex3_aspr_ce_addr_q), - .dout(ex4_aspr_ce_addr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[3]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_hypv_spr_offset]), - .scout(sov[ex4_hypv_spr_offset]), - .din(ex3_hypv_spr_q), - .dout(ex4_hypv_spr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[3]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_illeg_spr_offset]), - .scout(sov[ex4_illeg_spr_offset]), - .din(ex3_illeg_spr_q), - .dout(ex4_illeg_spr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_priv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[3]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_priv_spr_offset]), - .scout(sov[ex4_priv_spr_offset]), - .din(ex3_priv_spr_q), - .dout(ex4_priv_spr_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[3]), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_np1_flush_offset]), - .scout(sov[ex4_np1_flush_offset]), - .din(ex4_np1_flush_d), - .dout(ex4_np1_flush_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), - .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), - .scout(sov[ex5_sprg_ce_offset : ex5_sprg_ce_offset + `THREADS-1]), - .din(ex4_sprg_ce), - .dout(ex5_sprg_ce_q) - ); - tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ue_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_nsl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_nsl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_sprg_ue_offset]), - .scout(sov[ex4_sprg_ue_offset]), - .din(ex4_sprg_ue_d), - .dout(ex4_sprg_ue_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ue_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), - .mpw1_b(mpw1_dc_b[DEX5]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), - .scout(sov[ex5_sprg_ue_offset : ex5_sprg_ue_offset + `THREADS-1]), - .din(ex4_sprg_ue), - .dout(ex5_sprg_ue_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_dbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), - .scout(sov[cpl_dbell_taken_offset : cpl_dbell_taken_offset + `THREADS-1]), - .din(iu_xu_dbell_taken), - .dout(cpl_dbell_taken_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_cdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), - .scout(sov[cpl_cdbell_taken_offset : cpl_cdbell_taken_offset + `THREADS-1]), - .din(iu_xu_cdbell_taken), - .dout(cpl_cdbell_taken_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), - .scout(sov[cpl_gdbell_taken_offset : cpl_gdbell_taken_offset + `THREADS-1]), - .din(iu_xu_gdbell_taken), - .dout(cpl_gdbell_taken_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gcdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), - .scout(sov[cpl_gcdbell_taken_offset : cpl_gcdbell_taken_offset + `THREADS-1]), - .din(iu_xu_gcdbell_taken), - .dout(cpl_gcdbell_taken_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gmcdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), - .scout(sov[cpl_gmcdbell_taken_offset : cpl_gmcdbell_taken_offset + `THREADS-1]), - .din(iu_xu_gmcdbell_taken), - .dout(cpl_gmcdbell_taken_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cslc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[set_xucr0_cslc_offset]), - .scout(sov[set_xucr0_cslc_offset]), - .din(set_xucr0_cslc_d), - .dout(set_xucr0_cslc_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cul_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[set_xucr0_cul_offset]), - .scout(sov[set_xucr0_cul_offset]), - .din(set_xucr0_cul_d), - .dout(set_xucr0_cul_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_clo_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[set_xucr0_clo_offset]), - .scout(sov[set_xucr0_clo_offset]), - .din(set_xucr0_clo_d), - .dout(set_xucr0_clo_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[2]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex3_np1_flush_offset]), - .scout(sov[ex3_np1_flush_offset]), - .din(ex3_np1_flush_d), - .dout(ex3_np1_flush_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) running_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[running_offset : running_offset + `THREADS-1]), - .scout(sov[running_offset : running_offset + `THREADS-1]), - .din(running_d), - .dout(running_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(2**(`THREADS-1)), .NEEDS_SRESET(1)) llpri_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(llpri_inc), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[llpri_offset : llpri_offset + `THREADS-1]), - .scout(sov[llpri_offset : llpri_offset + `THREADS-1]), - .din(llpri_d), - .dout(llpri_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dec_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), - .scout(sov[dec_dbg_dis_offset : dec_dbg_dis_offset + `THREADS-1]), - .din(dec_dbg_dis_d), - .dout(dec_dbg_dis_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tb_dbg_dis_offset]), - .scout(sov[tb_dbg_dis_offset]), - .din(tb_dbg_dis_d), - .dout(tb_dbg_dis_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tb_act_offset]), - .scout(sov[tb_act_offset]), - .din(tb_act_d), - .dout(tb_act_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ext_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), - .scout(sov[ext_dbg_dis_offset : ext_dbg_dis_offset + `THREADS-1]), - .din(ext_dbg_dis_d), - .dout(ext_dbg_dis_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[msrovride_enab_offset]), - .scout(sov[msrovride_enab_offset]), - .din(pc_xu_msrovride_enab), - .dout(msrovride_enab_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitimpl_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), - .scout(sov[waitimpl_val_offset : waitimpl_val_offset + `THREADS-1]), - .din(waitimpl_val_d), - .dout(waitimpl_val_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitrsv_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), - .scout(sov[waitrsv_val_offset : waitrsv_val_offset + `THREADS-1]), - .din(waitrsv_val_d), - .dout(waitrsv_val_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_reservation_vld_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), - .scout(sov[an_ac_reservation_vld_offset : an_ac_reservation_vld_offset + `THREADS-1]), - .din(an_ac_reservation_vld), - .dout(an_ac_reservation_vld_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_sleep_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), - .scout(sov[an_ac_sleep_en_offset : an_ac_sleep_en_offset + `THREADS-1]), - .din(an_ac_sleep_en), - .dout(an_ac_sleep_en_q) - ); - tri_rlmreg_p #(.WIDTH(8), .OFFSET(54),.INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), - .scout(sov[an_ac_coreid_offset : an_ac_coreid_offset + 8-1]), - .din(an_ac_coreid), - .dout(an_ac_coreid_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_enable_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tb_update_enable_offset]), - .scout(sov[tb_update_enable_offset]), - .din(an_ac_tb_update_enable), - .dout(tb_update_enable_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tb_update_pulse_offset]), - .scout(sov[tb_update_pulse_offset]), - .din(an_ac_tb_update_pulse), - .dout(tb_update_pulse_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[tb_update_pulse_1_offset]), - .scout(sov[tb_update_pulse_1_offset]), - .din(tb_update_pulse_q), - .dout(tb_update_pulse_1_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_wd_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[pc_xu_reset_wd_complete_offset]), - .scout(sov[pc_xu_reset_wd_complete_offset]), - .din(pc_xu_reset_wd_complete), - .dout(pc_xu_reset_wd_complete_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_3_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[pc_xu_reset_3_complete_offset]), - .scout(sov[pc_xu_reset_3_complete_offset]), - .din(pc_xu_reset_3_complete), - .dout(pc_xu_reset_3_complete_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_2_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[pc_xu_reset_2_complete_offset]), - .scout(sov[pc_xu_reset_2_complete_offset]), - .din(pc_xu_reset_2_complete), - .dout(pc_xu_reset_2_complete_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_1_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[pc_xu_reset_1_complete_offset]), - .scout(sov[pc_xu_reset_1_complete_offset]), - .din(pc_xu_reset_1_complete), - .dout(pc_xu_reset_1_complete_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[lq_xu_dbell_val_offset]), - .scout(sov[lq_xu_dbell_val_offset]), - .din(lq_xu_dbell_val), - .dout(lq_xu_dbell_val_q) - ); - tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_type_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), - .scout(sov[lq_xu_dbell_type_offset : lq_xu_dbell_type_offset + 5-1]), - .din(lq_xu_dbell_type), - .dout(lq_xu_dbell_type_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_brdcast_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[lq_xu_dbell_brdcast_offset]), - .scout(sov[lq_xu_dbell_brdcast_offset]), - .din(lq_xu_dbell_brdcast), - .dout(lq_xu_dbell_brdcast_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_lpid_match_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[lq_xu_dbell_lpid_match_offset]), - .scout(sov[lq_xu_dbell_lpid_match_offset]), - .din(lq_xu_dbell_lpid_match), - .dout(lq_xu_dbell_lpid_match_q) - ); - tri_rlmreg_p #(.WIDTH(14), .OFFSET(50),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_pirtag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), - .scout(sov[lq_xu_dbell_pirtag_offset : lq_xu_dbell_pirtag_offset + 14-1]), - .din(lq_xu_dbell_pirtag), - .dout(lq_xu_dbell_pirtag_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[dbell_present_offset : dbell_present_offset + `THREADS-1]), - .scout(sov[dbell_present_offset : dbell_present_offset + `THREADS-1]), - .din(dbell_present_d), - .dout(dbell_present_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), - .scout(sov[cdbell_present_offset : cdbell_present_offset + `THREADS-1]), - .din(cdbell_present_d), - .dout(cdbell_present_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), - .scout(sov[gdbell_present_offset : gdbell_present_offset + `THREADS-1]), - .din(gdbell_present_d), - .dout(gdbell_present_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), - .scout(sov[gcdbell_present_offset : gcdbell_present_offset + `THREADS-1]), - .din(gcdbell_present_d), - .dout(gcdbell_present_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), - .scout(sov[gmcdbell_present_offset : gmcdbell_present_offset + `THREADS-1]), - .din(gmcdbell_present_d), - .dout(gmcdbell_present_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clfc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[xucr0_clfc_offset]), - .scout(sov[xucr0_clfc_offset]), - .din(xucr0_clfc_d), - .dout(xucr0_clfc_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_run_thread_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), - .scout(sov[iu_run_thread_offset : iu_run_thread_offset + `THREADS-1]), - .din(iu_run_thread_d), - .dout(iu_run_thread_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) inj_sprg_ecc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), - .scout(sov[inj_sprg_ecc_offset : inj_sprg_ecc_offset + `THREADS-1]), - .din(pc_xu_inj_sprg_ecc), - .dout(inj_sprg_ecc_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), - .scout(sov[dbell_interrupt_offset : dbell_interrupt_offset + `THREADS-1]), - .din(dbell_interrupt), - .dout(dbell_interrupt_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), - .scout(sov[cdbell_interrupt_offset : cdbell_interrupt_offset + `THREADS-1]), - .din(cdbell_interrupt), - .dout(cdbell_interrupt_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), - .scout(sov[gdbell_interrupt_offset : gdbell_interrupt_offset + `THREADS-1]), - .din(gdbell_interrupt), - .dout(gdbell_interrupt_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), - .scout(sov[gcdbell_interrupt_offset : gcdbell_interrupt_offset + `THREADS-1]), - .din(gcdbell_interrupt), - .dout(gcdbell_interrupt_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), - .scout(sov[gmcdbell_interrupt_offset : gmcdbell_interrupt_offset + `THREADS-1]), - .din(gmcdbell_interrupt), - .dout(gmcdbell_interrupt_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), - .scout(sov[iu_quiesce_offset : iu_quiesce_offset + `THREADS-1]), - .din(iu_xu_quiesce), - .dout(iu_quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_icache_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), - .scout(sov[iu_icache_quiesce_offset : iu_icache_quiesce_offset + `THREADS-1]), - .din(iu_xu_icache_quiesce), - .dout(iu_icache_quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lsu_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), - .scout(sov[lsu_quiesce_offset : lsu_quiesce_offset + `THREADS-1]), - .din(lq_xu_quiesce), - .dout(lsu_quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), - .scout(sov[mm_quiesce_offset : mm_quiesce_offset + `THREADS-1]), - .din(mm_xu_quiesce), - .dout(mm_quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) bx_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), - .scout(sov[bx_quiesce_offset : bx_quiesce_offset + `THREADS-1]), - .din(bx_xu_quiesce), - .dout(bx_quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[quiesce_offset : quiesce_offset + `THREADS-1]), - .scout(sov[quiesce_offset : quiesce_offset + `THREADS-1]), - .din(quiesce_d), - .dout(quiesce_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesced_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[quiesced_offset : quiesced_offset + `THREADS-1]), - .scout(sov[quiesced_offset : quiesced_offset + `THREADS-1]), - .din(quiesced_d), - .dout(quiesced_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) instr_trace_mode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[instr_trace_mode_offset]), - .scout(sov[instr_trace_mode_offset]), - .din(pc_xu_instr_trace_mode), - .dout(instr_trace_mode_q) - ); - tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) instr_trace_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), - .scout(sov[instr_trace_tid_offset : instr_trace_tid_offset + 2-1]), - .din(pc_xu_instr_trace_tid), - .dout(instr_trace_tid_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) timer_update_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[timer_update_offset]), - .scout(sov[timer_update_offset]), - .din(timer_update_int), - .dout(timer_update_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_read_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[spr_xu_ord_read_done_offset]), - .scout(sov[spr_xu_ord_read_done_offset]), - .din(spr_xu_ord_read_done_d), - .dout(spr_xu_ord_read_done_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_write_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[spr_xu_ord_write_done_offset]), - .scout(sov[spr_xu_ord_write_done_offset]), - .din(spr_xu_ord_write_done_d), - .dout(spr_xu_ord_write_done_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_spr_ord_ready_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[xu_spr_ord_ready_offset]), - .scout(sov[xu_spr_ord_ready_offset]), - .din(xu_spr_ord_ready), - .dout(xu_spr_ord_ready_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sspr_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[ex4_sspr_val_offset]), - .scout(sov[ex4_sspr_val_offset]), - .din(ex3_sspr_val), - .dout(ex4_sspr_val_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[flush_offset : flush_offset + `THREADS-1]), - .scout(sov[flush_offset : flush_offset + `THREADS-1]), - .din(flush), - .dout(flush_q) - ); - tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex1_ifar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[0]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), - .mpw1_b(mpw1_dc_b[DEX1]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), - .scout(sov[ex1_ifar_offset : ex1_ifar_offset + `EFF_IFAR_WIDTH-1]), - .din(rv_xu_ex0_ifar), - .dout(ex1_ifar_q) - ); - tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ifar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(exx_act[1]), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), - .mpw1_b(mpw1_dc_b[DEX2]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), - .scout(sov[ex2_ifar_offset : ex2_ifar_offset + `EFF_IFAR_WIDTH-1]), - .din(ex1_ifar_q), - .dout(ex2_ifar_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ram_active_offset : ram_active_offset + `THREADS-1]), - .scout(sov[ram_active_offset : ram_active_offset + `THREADS-1]), - .din(pc_xu_ram_active), - .dout(ram_active_q) - ); - tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timer_div_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(timer_div_act), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[timer_div_offset : timer_div_offset + 5-1]), - .scout(sov[timer_div_offset : timer_div_offset + 5-1]), - .din(timer_div_d), - .dout(timer_div_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), - .scout(sov[msrovride_enab_2_offset : msrovride_enab_2_offset + `THREADS-1]), - .din(msrovride_enab), - .dout(msrovride_enab_2_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), - .scout(sov[msrovride_enab_3_offset : msrovride_enab_3_offset + `THREADS-1]), - .din(msrovride_enab_2_q), - .dout(msrovride_enab_3_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), - .mpw1_b(mpw1_dc_b[DEX3]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex3_wait_flush_offset]), - .scout(sov[ex3_wait_flush_offset]), - .din(ex3_wait_flush_d), - .dout(ex3_wait_flush_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wait_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), - .mpw1_b(mpw1_dc_b[DEX4]), .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin (siv[ex4_wait_flush_offset]), - .scout(sov[ex4_wait_flush_offset]), - .din(ex4_wait_flush_d), - .dout(ex4_wait_flush_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_pm_hold_thread_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[pc_xu_pm_hold_thread_offset]), - .scout(sov[pc_xu_pm_hold_thread_offset]), - .din(pc_xu_pm_hold_thread), - .dout(pc_xu_pm_hold_thread_q) - ); - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) power_savings_on_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin(siv[power_savings_on_offset]), - .scout(sov[power_savings_on_offset]), - .din(power_savings_on_d), - .dout(power_savings_on_q) - ); - tri_rlmreg_p #(.WIDTH(4*`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_bus_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(pc_xu_event_bus_enable), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), - .scout(sov[perf_event_bus_offset : perf_event_bus_offset + 4*`THREADS-1]), - .din(perf_event_bus_d), - .dout(perf_event_bus_q) - ); - tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(pc_xu_event_bus_enable), - .force_t(func_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(func_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), - .scout(sov[perf_event_en_offset : perf_event_en_offset + `THREADS-1]), - .din(perf_event_en_d), - .dout(perf_event_en_q) - ); - - - tri_lcbnd spare_0_lcb( - .vd(vdd), - .gd(gnd), - .act(1'b1), - .nclk(nclk), - .force_t(func_sl_force), - .thold_b(func_sl_thold_0_b), - .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), - .mpw2_b(mpw2_dc_b), - .sg(sg_0), - .lclk(spare_0_lclk), - .d1clk(spare_0_d1clk), - .d2clk(spare_0_d2clk) - ); - - tri_inv_nlats #(.WIDTH(16), .BTR("NLI0001_X2_A12TH"), .INIT(0)) spare_0_latch( - .vd(vdd), - .gd(gnd), - .lclk(spare_0_lclk), - .d1clk(spare_0_d1clk), - .d2clk(spare_0_d2clk), - .scanin(siv[spare_0_offset:spare_0_offset + 16 - 1]), - .scanout(sov[spare_0_offset:spare_0_offset + 16 - 1]), - .d(spare_0_d), - .qb(spare_0_q) - ); - assign spare_0_d = (~spare_0_q); - - xu_fctr #(.WIDTH(`THREADS), .PASSTHRU(0), .DELAY_WIDTH(4), .CLOCKGATE(1)) quiesced_fctr( - .nclk(nclk), - .vdd(vdd), - .gnd(gnd), - .force_t(func_sl_force), - .d_mode(d_mode_dc), - .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .sg(sg_0), - .scin(siv[quiesced_ctr_offset]), - .scout(sov[quiesced_ctr_offset]), - .delay(4'b1111), - .din(quiesce_b_q), - .dout(quiesce_ctr_zero_b) - ); - - - tri_ser_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ccr0_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), - .act(1'b1), - .force_t(bcfg_slp_sl_force), - .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), - .mpw1_b(mpw1_dc_b[DX]), .mpw2_b(mpw2_dc_b), - .thold_b(bcfg_slp_sl_thold_0_b), - .sg(sg_0), - .scin (siv_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), - .scout(sov_bcfg[ccr0_we_offset_bcfg : ccr0_we_offset_bcfg + `THREADS-1]), - .din(ccr0_we_d), - .dout(ccr0_we_q) - ); - - - - assign siv[0:399] = {sov[1:399], scan_in[0]}; - assign scan_out[0] = sov[0]; - - assign siv[400:scan_right-1] = {sov[401:scan_right-1], scan_in[1]}; - assign scan_out[1] = sov[400]; - - generate - // BCFG - if (scan_right_bcfg > 1) - begin : bcfg_l - assign siv_bcfg[0:scan_right_bcfg - 1] = {sov_bcfg[1:scan_right_bcfg-1], bcfg_scan_in}; - assign bcfg_scan_out = sov_bcfg[0]; - end - if (scan_right_bcfg == 1) - begin : bcfg_s - assign siv_bcfg[0] = bcfg_scan_in; - assign bcfg_scan_out = sov_bcfg[0]; - end - if (scan_right_bcfg == 0) - begin : bcfg_z - assign bcfg_scan_out = bcfg_scan_in; - end - // CCFG - if (scan_right_ccfg > 1) - begin : ccfg_l - assign siv_ccfg[0:scan_right_ccfg - 1] = {sov_ccfg[1:scan_right_ccfg - 1], ccfg_scan_in}; - assign ccfg_scan_out = sov_ccfg[0]; - end - if (scan_right_ccfg == 1) - begin : ccfg_s - assign siv_ccfg[0] = ccfg_scan_in; - assign ccfg_scan_out = sov_ccfg[0]; - end - if (scan_right_ccfg == 0) - begin : ccfg_z - assign ccfg_scan_out = ccfg_scan_in; - end - // DCFG - if (scan_right_dcfg > 1) - begin : dcfg_l - assign siv_dcfg[0:scan_right_dcfg - 1] = {sov_dcfg[1:scan_right_dcfg - 1], dcfg_scan_in}; - assign dcfg_scan_out = sov_dcfg[0]; - end - if (scan_right_dcfg == 1) - begin : dcfg_s - assign siv_dcfg[0] = dcfg_scan_in; - assign dcfg_scan_out = sov_dcfg[0]; - end - if (scan_right_dcfg == 0) - begin : dcfg_z - assign dcfg_scan_out = dcfg_scan_in; - end - endgenerate - - - function [0:`THREADS-1] reverse_threads; - input [0:`THREADS-1] a; - integer t; - begin - for (t=0;t<`THREADS;t=t+1) - begin : threads_loop - reverse_threads[t] = a[`THREADS-1-t]; - end - end - endfunction - - -endmodule diff --git a/dev/verilog/readme.md b/dev/verilog/readme.md index 090fb76..5b128d3 100644 --- a/dev/verilog/readme.md +++ b/dev/verilog/readme.md @@ -1,10 +1,8 @@ # RTL - ## fpga/sim arrays -* created sim-only (not fpga?) clk1x versions in trilib_clk1x to eliminate any possible problems with iverilog -and verilator dealing with multiple clocks +* arrays that had 2x/4x clks ``` trilib/tri_144x78_2r4w.v @@ -19,6 +17,18 @@ trilib/tri_512x16_1r1w_1.v trilib/tri_128x16_1r1w_1.v ``` +* also got rid of reset_q usages (clk and reset in same nclk vector) +***i doubt reset is needed in any of the array components*** + +``` +trilib/tri_128x16_1r1w_1.v: reg reset_q; +trilib/tri_512x16_1r1w_1.v: reg reset_q; +trilib/tri_64x72_1r1w.v: reg reset_q; +trilib/tri_cam_16x143_1r1w1c.v: reg sreset_q; +trilib/tri_cam_32x143_1r1w1c.v: reg sreset_q; +trilib/tri_iuq_cpl_arr.v: reg reset_q; +``` + ### arrays using clk4x * 4W was done with clk4x @@ -27,7 +37,6 @@ trilib/tri_128x16_1r1w_1.v ``` grep "nclk\[3\]" trilib/* trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x -trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x ``` ### arrays using clk2x diff --git a/dev/verilog/smt2/tri_a2o.vh b/dev/verilog/smt/tri_a2o.vh similarity index 87% rename from dev/verilog/smt2/tri_a2o.vh rename to dev/verilog/smt/tri_a2o.vh index 74b7210..218e32d 100755 --- a/dev/verilog/smt2/tri_a2o.vh +++ b/dev/verilog/smt/tri_a2o.vh @@ -1,4 +1,4 @@ -// © IBM Corp. 2022 +// © IBM Corp. 2020 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -33,6 +33,10 @@ // Use this line for 1 thread. Comment out for 2 thread design. //`define THREADS1 +`define RESET_VECTOR 32'h00000000 + +// 0: none 1: DP +`define FLOAT_TYPE 1 `define gpr_t 3'b000 `define cr_t 3'b001 @@ -111,7 +115,7 @@ `define IBUFF_INSTR_WIDTH 70 `define IBUFF_IFAR_WIDTH 20 `define IBUFF_DEPTH 16 -`define PF_IAR_BITS 12 // number of IAR bits used by prefetch +`define PF_IAR_BITS 12 // number of IAR bits used by prefetch `define FXU0_PIPE_START 1 `define FXU0_PIPE_END 8 `define FXU1_PIPE_START 1 @@ -121,7 +125,7 @@ `define LQ_REL_PIPE_START 2 `define LQ_REL_PIPE_END 4 `define LOAD_CREDITS 8 -`define STORE_CREDITS 4 +`define STORE_CREDITS 4 //wtf 32 is normal; fpga bug needed 4 `define IUQ_ENTRIES 4 // Instruction Fetch Queue Size `define MMQ_ENTRIES 2 // MMU Queue Size `define CR_WIDTH 4 @@ -133,16 +137,32 @@ `define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) `define XER_WIDTH 10 -`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT -`define INIT_IUCR0 16'h00FA // BP enabled +//wtf: change for verilatorsim - didnt help +//`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT +`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT + +//`define INIT_IUCR0 16'h0000 // BP disabled +`define INIT_IUCR0 16'h00FA // BP enabled +`define INIT_XUCR0 32'h00000460 // normal + `define INIT_MASK 2'b10 `define RELQ_INCLUDE 0 // Reload Queue Included `define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 +//wtf: add completion stuff +/* + assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39]; + assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47]; + assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55]; + assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63]; +*/ `define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 //`define INIT_CPCR0 32'h01010201 // 1/1/2/1 - +/* + assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47]; + assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55]; +*/ `define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 //`define INIT_CPCR1 32'h00010100 // 1/1 diff --git a/dev/verilog/trilib/tri_128x168_1w_0.v b/dev/verilog/trilib/tri_128x168_1w_0.v index 13f585b..f701e30 100755 --- a/dev/verilog/trilib/tri_128x168_1w_0.v +++ b/dev/verilog/trilib/tri_128x168_1w_0.v @@ -36,11 +36,12 @@ `include "tri_a2o.vh" -module tri_128x168_1w_0( +module tri_128x168_1w_0 ( gnd, vdd, vcs, - nclk, + clk, + rst, act, ccflush_dc, scan_dis_dc_b, @@ -102,7 +103,8 @@ module tri_128x168_1w_0( inout vcs; // CLOCK and CLOCKCONTROL ports - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; input ccflush_dc; input scan_dis_dc_b; @@ -227,7 +229,7 @@ module tri_128x168_1w_0( .DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]), .ADDRA(ramb_addr), .ADDRB(ramb_addr), - .CLKA(nclk[0]), + .CLKA(clk), .CLKB(tidn), .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), @@ -235,7 +237,7 @@ module tri_128x168_1w_0( .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), .ENA(act), .ENB(tidn), - .SSRA(nclk[1]), + .SSRA(rst), .SSRB(tidn), .WEA(write[w]), .WEB(tidn) @@ -252,5 +254,5 @@ module tri_128x168_1w_0( assign bo_pc_failout = 1'b0; assign bo_pc_diagloop = 1'b0; - assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob}); + assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, unused_dob}); endmodule diff --git a/dev/verilog/trilib/tri_128x16_1r1w_1.v b/dev/verilog/trilib/tri_128x16_1r1w_1.v index 4b35c1f..01c202a 100755 --- a/dev/verilog/trilib/tri_128x16_1r1w_1.v +++ b/dev/verilog/trilib/tri_128x16_1r1w_1.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -33,13 +33,16 @@ // //***************************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" -module tri_128x16_1r1w_1( +module tri_128x16_1r1w_1 ( vdd, vcs, gnd, - nclk, + clk, + rst, rd_act, wr_act, lcb_d_mode_dc, @@ -106,7 +109,8 @@ module tri_128x16_1r1w_1( inout vcs; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input rd_act; input wr_act; @@ -179,67 +183,38 @@ module tri_128x16_1r1w_1( //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36; wire clk; - wire clk2x; wire [0:8] b0addra; wire [0:8] b0addrb; wire wea; wire web; wire wren_a; - // Latches - reg reset_q; - reg gate_fq; - wire gate_d; - wire [0:35] r_data_out_1_d; - reg [0:35] r_data_out_1_fq; - wire [0:35] w_data_in_0; + wire [0:15] w_data_in_0; + wire [0:15] r_data_out_0_bram; - wire [0:35] r_data_out_0_bram; - wire [0:35] r_data_out_1_bram; + // Latches + reg [0:15] r_data_out_1_q; - wire toggle_d; - reg toggle_q; - wire toggle2x_d; - reg toggle2x_q; (* analysis_not_referenced="true" *) wire unused; - assign clk = nclk[0]; - assign clk2x = nclk[2]; - + // sim array + reg [0:15] mem[0:127]; - always @(posedge clk) - begin: rlatch - reset_q <= nclk[1]; - end - - // - // NEW clk2x gate logic start - // - - always @(posedge nclk[0]) - begin: tlatch - if (reset_q == 1'b1) - toggle_q <= 1'b1; - else - toggle_q <= toggle_d; - end + integer i; + initial begin + for (i = 0; i < 128; i = i + 1) + mem[i] = 0; + end - - always @(posedge nclk[2]) - begin: flatch - toggle2x_q <= toggle2x_d; - gate_fq <= gate_d; - r_data_out_1_fq <= r_data_out_1_d; - end - - assign toggle_d = (~toggle_q); - assign toggle2x_d = toggle_q; - - // should force gate_fq to be on during odd 2x clock (second half of 1x clock). - //gate_d <= toggle_q xor toggle2x_q; - // if you want the first half do the following - assign gate_d = (~(toggle_q ^ toggle2x_q)); + //wtf:icarus $dumpvars cannot dump a vpiMemory + generate + genvar j; + for (j = 0; j < 128; j=j+1) begin: loc + wire [0:15] dat; + assign dat = mem[j][0:15]; + end + endgenerate assign b0addra[2:8] = wr_adr; assign b0addrb[2:8] = rd_adr; @@ -249,72 +224,37 @@ module tri_128x16_1r1w_1( assign b0addrb[0:1] = 2'b00; // port a is a read-modify-write port - assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 : - 1'b0; - assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign wren_a = (bw != 0) & wr_act; + assign wea = wren_a; assign web = 1'b0; - assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : - r_data_out_0_bram[0]; - assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : - r_data_out_0_bram[1]; - assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : - r_data_out_0_bram[2]; - assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : - r_data_out_0_bram[3]; - assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : - r_data_out_0_bram[4]; - assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : - r_data_out_0_bram[5]; - assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : - r_data_out_0_bram[6]; - assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : - r_data_out_0_bram[7]; - assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : - r_data_out_0_bram[8]; - assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : - r_data_out_0_bram[9]; - assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : - r_data_out_0_bram[10]; - assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : - r_data_out_0_bram[11]; - assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : - r_data_out_0_bram[12]; - assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : - r_data_out_0_bram[13]; - assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : - r_data_out_0_bram[14]; - assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : - r_data_out_0_bram[15]; - assign w_data_in_0[16:35] = {20{1'b0}}; - - assign r_data_out_1_d = r_data_out_1_bram; - - - - RAMB16_S36_S36 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram0a( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(reset_q), - .SSRB(reset_q), - .ADDRA(b0addra), - .ADDRB(b0addrb), - .DIA(w_data_in_0[0:31]), - .DIB({32{1'b0}}), - .DOA(r_data_out_0_bram[0:31]), - .DOB(r_data_out_1_bram[0:31]), - .DOPA(r_data_out_0_bram[32:35]), - .DOPB(r_data_out_1_bram[32:35]), - .DIPA(w_data_in_0[32:35]), - .DIPB(4'b0000), - .ENA(1'b1), - .ENB(1'b1), - .WEA(wea), - .WEB(web) - ); - - assign dout = r_data_out_1_fq[0:15]; + assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0]; + assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1]; + assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2]; + assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3]; + assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4]; + assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5]; + assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6]; + assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7]; + assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8]; + assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9]; + assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10]; + assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11]; + assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12]; + assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13]; + assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14]; + assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15]; + + always @(posedge clk) begin + + r_data_out_1_q <= mem[b0addrb]; + if (wea) begin + mem[b0addra] <= w_data_in_0; + end + + end + + assign r_data_out_0_bram = mem[b0addra]; + assign dout = r_data_out_1_q[0:15]; assign func_scan_out = func_scan_in; assign time_scan_out = time_scan_in; @@ -324,12 +264,12 @@ module tri_128x16_1r1w_1( assign bo_pc_failout = 1'b0; assign bo_pc_diagloop = 1'b0; - assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + assign unused = |{vdd, vcs, gnd, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]}; + tri_lcb_act_dis_dc, rd_act}; endmodule diff --git a/dev/verilog/trilib/tri_128x34_4w_1r1w.v b/dev/verilog/trilib/tri_128x34_4w_1r1w.v index dfd3d82..c6f00f3 100755 --- a/dev/verilog/trilib/tri_128x34_4w_1r1w.v +++ b/dev/verilog/trilib/tri_128x34_4w_1r1w.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -37,11 +37,12 @@ `include "tri_a2o.vh" -module tri_128x34_4w_1r1w( +module tri_128x34_4w_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, rd_act, wr_act, sg_0, @@ -110,7 +111,8 @@ module tri_128x34_4w_1r1w( (* analysis_not_referenced="true" *) inout vcs; // CLOCK and CLOCKCONTROL ports - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input rd_act; input wr_act; input sg_0; @@ -254,16 +256,16 @@ module tri_128x34_4w_1r1w( .DOPB(dopb), .ADDRA(ramb_rd_addr), .ADDRB(ramb_wr_addr), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), .DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), .DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), .ENA(rd_act), .ENB(wr_act), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(tidn), .WEB(wr_way[w]) ); @@ -278,7 +280,8 @@ module tri_128x34_4w_1r1w( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(1'b1), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -296,7 +299,8 @@ module tri_128x34_4w_1r1w( tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_l2), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -319,6 +323,6 @@ module tri_128x34_4w_1r1w( assign bo_pc_failout = {tidn, tidn}; assign bo_pc_diagloop = {tidn, tidn}; - assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]}); + assign unused = | ({sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]}); endmodule diff --git a/dev/verilog/trilib/tri_144x78_2r4w.v b/dev/verilog/trilib/tri_144x78_2r4w.v old mode 100755 new mode 100644 index ef0660e..31de62e --- a/dev/verilog/trilib/tri_144x78_2r4w.v +++ b/dev/verilog/trilib/tri_144x78_2r4w.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -26,22 +26,25 @@ // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // obtained (along with the Power ISA) here: https://openpowerfoundation.org. -`timescale 1 ps / 1 ps +`timescale 1 ns / 1 ns //***************************************************************************** // Description: Tri-Lam Array Wrapper // //***************************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" -module tri_144x78_2r4w( +module tri_144x78_2r4w ( // Inputs // Power inout vdd, inout gnd, // Clock & Scan - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -84,554 +87,72 @@ module tri_144x78_2r4w( input [64-`GPR_WIDTH:77] w_data_in_4 ); - // Configuration Statement for NCsim - //for all:RAM64X1D use entity unisim.RAM64X1D; - - parameter tiup = 1'b1; - parameter tidn = 1'b0; + wire unused; - //------------------------------------------------------------------- - // Signals - //------------------------------------------------------------------- - //reg write_en; - //reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr; - //reg [64-`GPR_WIDTH:77] write_data; - wire write_en; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr; - wire [64-`GPR_WIDTH:77] write_data; + // sim array + reg [64-`GPR_WIDTH:77] mem[0:143]; - wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr; - wire [0:5] write_addr_arr; - wire [0:1] wr_mux_ctrl; - - //------------------------------------------------------------------- - // Latch Signals - //------------------------------------------------------------------- - wire w1e_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q; - wire [64-`GPR_WIDTH:77] w1d_q; - wire w2e_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q; - wire [64-`GPR_WIDTH:77] w2d_q; - wire w3e_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q; - wire [64-`GPR_WIDTH:77] w3d_q; - wire w4e_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q; - wire [64-`GPR_WIDTH:77] w4d_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; - wire [0:5] read1_addr_arr; - wire [0:5] read2_addr_arr; - wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr; - wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr; - reg [64-`GPR_WIDTH:77] read1_data; - reg [64-`GPR_WIDTH:77] read2_data; - wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64]; - wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64]; - wire [64-`GPR_WIDTH:77] r1d_d; - wire [64-`GPR_WIDTH:77] r2d_d; - wire [64-`GPR_WIDTH:77] r1d_q; - wire [64-`GPR_WIDTH:77] r2d_q; + reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d; + reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; + wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d; - (* analysis_not_referenced="true" *) - wire unused; - wire [64-`GPR_WIDTH:77] unused_port; - wire [64-`GPR_WIDTH:77] unused_port2; + reg [64-`GPR_WIDTH:77] r1d_q; + wire [64-`GPR_WIDTH:77] r1d_d; + reg [64-`GPR_WIDTH:77] r2d_q; + wire [64-`GPR_WIDTH:77] r2d_d; - //------------------------------------------------------------------- - // Scanchain - //------------------------------------------------------------------- - parameter w1e_offset = 0; - parameter w1a_offset = w1e_offset + 1; - parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14); - parameter w2a_offset = w2e_offset + 1; - parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14); - parameter w3a_offset = w3e_offset + 1; - parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14); - parameter w4a_offset = w4e_offset + 1; - parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14); - parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC; - parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14); - parameter scan_right = r2d_offset + (`GPR_WIDTH+14); - wire [0:scan_right-1] siv; - wire [0:scan_right-1] sov; + integer i; + initial begin + for (i = 0; i < 144; i = i + 1) + mem[i] = 0; + end + //wtf:icarus $dumpvars cannot dump a vpiMemory generate - begin - - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - // Read Control - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - // BYPASS - - assign r1d_d = read1_data; - - assign r2d_d = read2_data; - - assign r_data_out_1 = r1d_q; - assign r_data_out_2 = r2d_q; - - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - // Write Control - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - assign wr_mux_ctrl = {nclk[0], nclk[2]}; - - //wtf moved these here to try to get them to work in icarus - they seem to now - assign write_en = ((wr_mux_ctrl == 2'b00) ? w_late_en_1 : - (wr_mux_ctrl == 2'b01) ? w_late_en_2 : - (wr_mux_ctrl == 2'b10) ? w_late_en_3 : - w_late_en_4); - - assign write_addr = ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 : - (wr_mux_ctrl == 2'b01) ? w_addr_in_2 : - (wr_mux_ctrl == 2'b10) ? w_addr_in_3 : - w_addr_in_4); - - assign write_data = ((wr_mux_ctrl == 2'b00) ? w_data_in_1 : - (wr_mux_ctrl == 2'b01) ? w_data_in_2 : - (wr_mux_ctrl == 2'b10) ? w_data_in_3 : - w_data_in_4); - - - //always @ ( * ) - //begin - //write_addr = #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 : - // (wr_mux_ctrl == 2'b01) ? w_addr_in_2 : - // (wr_mux_ctrl == 2'b10) ? w_addr_in_3 : - // w_addr_in_4); - - //write_en = #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 : - // (wr_mux_ctrl == 2'b01) ? w_late_en_2 : - // (wr_mux_ctrl == 2'b10) ? w_late_en_3 : - // w_late_en_4); - - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - // Depth Control - // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX - - //write_data = #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 : - // (wr_mux_ctrl == 2'b01) ? w_data_in_2 : - // (wr_mux_ctrl == 2'b10) ? w_data_in_3 : - // w_data_in_4); - //end - - if (((`GPR_POOL*`THREADS - 1)/64) == 0) - begin : depth1 - if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6) - begin - assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; - assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; - assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}}; - end - - assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr; - assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q; - assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q; - assign write_en_arr[0] = write_en; - assign read1_en_arr[0] = 1'b1; - assign read2_en_arr[0] = 1'b1; - end - - if (((`GPR_POOL*`THREADS - 1)/64) != 0) - begin : depthMulti - assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; - assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; - assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1]; - - genvar wen; - for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1) - begin : wrenGen - wire wen_match = wen; - assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match); - assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; - assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match; - end - end - - always @( * ) - begin: rdDataMux - reg [64-`GPR_WIDTH:77] rd1_data; - reg [64-`GPR_WIDTH:77] rd2_data; - //(* analysis_not_referenced="true" *) - integer rdArr; - rd1_data = {`GPR_WIDTH+14{1'b0}}; - rd2_data = {`GPR_WIDTH+14{1'b0}}; - - for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1) - begin - rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data; - rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data; - end - read1_data = rd1_data; - read2_data = rd2_data; - end - - genvar depth; - for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1) - begin : depth_loop - genvar i; - for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) - begin : r1 - RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1( - .SPO(unused_port[i]), - .DPO(r1d_array[depth][i]), // Port A 1-bit data output - - .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) - .A1(write_addr_arr[4]), - .A2(write_addr_arr[3]), - .A3(write_addr_arr[2]), - .A4(write_addr_arr[1]), - .A5(write_addr_arr[0]), - - //.A(write_addr_arr), - .D(write_data[i]), // Port A 1-bit data input - - .DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) - .DPRA1(read1_addr_arr[4]), - .DPRA2(read1_addr_arr[3]), - .DPRA3(read1_addr_arr[2]), - .DPRA4(read1_addr_arr[1]), - .DPRA5(read1_addr_arr[0]), - - //.DPRA(read1_addr_arr), - .WCLK(nclk[3]), // Port A write clock input : clk4x - .WE(write_en_arr[depth]) // Port A write enable input - ); + genvar j; + for (j = 0; j < 144; j=j+1) begin: loc + wire [64-`GPR_WIDTH:63] dat; + wire [0:7] par; + // 4b0 + assign dat = mem[j][64-`GPR_WIDTH:63]; + assign par = mem[j][64:63 + `GPR_WIDTH/8]; end - - //genvar i; - for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1) - begin : r2 - RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2( - .SPO(unused_port2[i]), - .DPO(r2d_array[depth][i]), // Port A 1-bit data output - - .A0(write_addr_arr[5]), // Port A - Write Address (A0-A5) - .A1(write_addr_arr[4]), - .A2(write_addr_arr[3]), - .A3(write_addr_arr[2]), - .A4(write_addr_arr[1]), - .A5(write_addr_arr[0]), - - //.A(write_addr_arr), - .D(write_data[i]), // Port A 1-bit data input - - .DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5) - .DPRA1(read2_addr_arr[4]), - .DPRA2(read2_addr_arr[3]), - .DPRA3(read2_addr_arr[2]), - .DPRA4(read2_addr_arr[1]), - .DPRA5(read2_addr_arr[0]), - - //.DPRA(read2_addr_arr), - .WCLK(nclk[3]), // Port A write clock input : clk4x - .WE(write_en_arr[depth]) // Port A write enable input - ); - end - end - end endgenerate - //---------------------------------------------------------------------------------------------------------------------------------------- - // Latches - //---------------------------------------------------------------------------------------------------------------------------------------- - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w1e_offset]), - .scout(sov[w1e_offset]), - .din(w_late_en_1), - .dout(w1e_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(w_addr_in_1), - .dout(w1a_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]), - .din(w_data_in_1[64 - `GPR_WIDTH:77]), - .dout(w1d_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w2e_offset]), - .scout(sov[w2e_offset]), - .din(w_late_en_2), - .dout(w2e_q) - ); + assign r1a_d = r_addr_in_1; + assign r2a_d = r_addr_in_2; - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(w_addr_in_2), - .dout(w2a_q) - ); + always @(posedge clk) begin - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]), - .din(w_data_in_2[64 - `GPR_WIDTH:77]), - .dout(w2d_q) - ); + r1a_q <= r1a_d; + r2a_q <= r2a_d; - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w3e_offset]), - .scout(sov[w3e_offset]), - .din(w_late_en_3), - .dout(w3e_q) - ); + r1d_q <= r1d_d; + r2d_q <= r2d_d; - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(w_addr_in_3), - .dout(w3a_q) - ); + if (w_late_en_1) begin + mem[w_addr_in_1] <= w_data_in_1; + end + if (w_late_en_2) begin + mem[w_addr_in_2] <= w_data_in_2; + end + if (w_late_en_3) begin + mem[w_addr_in_3] <= w_data_in_3; + end + if (w_late_en_4) begin + mem[w_addr_in_4] <= w_data_in_4; + end - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]), - .din(w_data_in_3[64 - `GPR_WIDTH:77]), - .dout(w3d_q) - ); - - tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w4e_offset]), - .scout(sov[w4e_offset]), - .din(w_late_en_4), - .dout(w4e_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(w_addr_in_4), - .dout(w4a_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]), - .din(w_data_in_4[64 - `GPR_WIDTH:77]), - .dout(w4d_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(r_addr_in_1), - .dout(r1a_q) - ); - - tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]), - .din(r_addr_in_2), - .dout(r2a_q) - ); + end - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]), - .din(r1d_d), - .dout(r1d_q) - ); + // r_late_en_x are unused in original also + assign r1d_d = mem[r1a_q]; + assign r2d_d = mem[r2a_q]; - tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( - .nclk(nclk), - .vd(vdd), - .gd(gnd), - .act(tiup), - .force_t(func_sl_force), - .delay_lclkr(delay_lclkr_dc), - .mpw1_b(mpw1_dc_b), - .mpw2_b(mpw2_dc_b), - .thold_b(func_sl_thold_0_b), - .d_mode(1'b0), - .sg(sg_0), - .scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), - .scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]), - .din(r2d_d), - .dout(r2d_q) - ); + assign r_data_out_1 = r1d_q; + assign r_data_out_2 = r2d_q; - assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; - assign scan_out = sov[0]; + assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b}; - assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b}; endmodule diff --git a/dev/verilog/trilib/tri_256x144_8w_1r1w.v b/dev/verilog/trilib/tri_256x144_8w_1r1w.v index 61829b2..505fba1 100755 --- a/dev/verilog/trilib/tri_256x144_8w_1r1w.v +++ b/dev/verilog/trilib/tri_256x144_8w_1r1w.v @@ -36,11 +36,12 @@ `include "tri_a2o.vh" -module tri_256x144_8w_1r1w( +module tri_256x144_8w_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, rd_act, wr_act, sg_0, @@ -115,7 +116,8 @@ inout vdd; inout vcs; // CLOCK and CLOCKCONTROL ports -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input [0:7] rd_act; input [0:7] wr_act; input sg_0; @@ -362,8 +364,8 @@ generate .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), .DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), .DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), @@ -372,8 +374,8 @@ generate .ENB(wr_act[way]), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), //sreset - .SSRB(nclk[1]), //sreset + .SSRA(rst), + .SSRB(rst), .WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]), .WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]) ); @@ -392,7 +394,6 @@ assign unused = |({ cascadeoutlatb , cascadeoutrega , cascadeoutregb , - nclk[0:`NCLK_WIDTH-1] , gnd , vdd , vcs , @@ -445,7 +446,8 @@ assign unused = |({ tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -471,7 +473,8 @@ generate .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), .force_t(func_sl_force), - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rd_act_q[way]), diff --git a/dev/verilog/trilib/tri_32x70_2w_1r1w.v b/dev/verilog/trilib/tri_32x70_2w_1r1w.v index fc8c8e7..4de4aaa 100755 --- a/dev/verilog/trilib/tri_32x70_2w_1r1w.v +++ b/dev/verilog/trilib/tri_32x70_2w_1r1w.v @@ -37,11 +37,12 @@ `include "tri_a2o.vh" -module tri_32x70_2w_1r1w( +module tri_32x70_2w_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, rd_act, wr_act, sg_0, @@ -113,7 +114,8 @@ inout gnd; inout vdd; inout vcs; // CLOCK and CLOCKCONTROL ports -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input [0:1] rd_act; input [0:1] wr_act; input sg_0; @@ -333,7 +335,8 @@ assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0; tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(write_enable_AB), .force_t(tidn[0]), .d_mode(tidn[0]), @@ -351,7 +354,8 @@ tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latc tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(write_enable_CD), .force_t(tidn[0]), .d_mode(tidn[0]), @@ -369,7 +373,8 @@ tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latc tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(tidn[0]), .d_mode(tidn[0]), @@ -387,7 +392,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(tidn[0]), .d_mode(tidn[0]), @@ -412,16 +418,16 @@ arr0_A( .DOPB(ramb_data_p1_outA[32:35]), .ADDRA(ramb_addr_wr_rd0), .ADDRB(ramb_addr_rd1), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in_l[0:31]), .DIB(tidn[0:31]), .DIPA(ramb_data_in_l[32:35]), .DIPB(tidn[32:35]), .ENA(act[0]), .ENB(act[0]), - .SSRA(nclk[1]), //sreset - .SSRB(nclk[1]), //sreset + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_AB), .WEB(tidn[0]) ); @@ -435,16 +441,16 @@ arr1_B( .DOPB(ramb_data_p1_outB[32:35]), .ADDRA(ramb_addr_wr_rd0), .ADDRB(ramb_addr_rd1), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in_r[0:31]), .DIB(tidn[0:31]), .DIPA(ramb_data_in_r[32:35]), .DIPB(tidn[32:35]), .ENA(act[0]), .ENB(act[0]), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_AB), .WEB(tidn[0]) ); @@ -458,16 +464,16 @@ arr2_C( .DOPB(ramb_data_p1_outC[32:35]), .ADDRA(ramb_addr_wr_rd0), .ADDRB(ramb_addr_rd1), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in_l[0:31]), .DIB(tidn[0:31]), .DIPA(ramb_data_in_l[32:35]), .DIPB(tidn[32:35]), .ENA(act[1]), .ENB(act[1]), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_CD), .WEB(tidn[0]) ); @@ -481,16 +487,16 @@ arr3_D( .DOPB(ramb_data_p1_outD[32:35]), .ADDRA(ramb_addr_wr_rd0), .ADDRB(ramb_addr_rd1), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in_r[0:31]), .DIB(tidn[0:31]), .DIPA(ramb_data_in_r[32:35]), .DIPB(tidn[32:35]), .ENA(act[1]), .ENB(act[1]), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_CD), .WEB(tidn[0]) ); @@ -502,7 +508,8 @@ arr3_D( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -520,7 +527,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_q[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -538,7 +546,8 @@ tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_q[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/trilib/tri_512x162_4w_0.v b/dev/verilog/trilib/tri_512x162_4w_0.v index 439dd57..77d3001 100755 --- a/dev/verilog/trilib/tri_512x162_4w_0.v +++ b/dev/verilog/trilib/tri_512x162_4w_0.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -36,11 +36,12 @@ `include "tri_a2o.vh" -module tri_512x162_4w_0( +module tri_512x162_4w_0 ( gnd, vdd, vcs, - nclk, + clk, + rst, ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, @@ -116,7 +117,8 @@ module tri_512x162_4w_0( (* analysis_not_referenced="true" *) inout vcs; // CLOCK and CLOCKCONTROL ports - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input ccflush_dc; input lcb_clkoff_dc_b; input lcb_d_mode_dc; @@ -257,7 +259,7 @@ module tri_512x162_4w_0( .DOPB(dopb), .ADDRA(ramb_addr), .ADDRB(ramb_addr), - .CLKA(nclk[0]), + .CLKA(clk), .CLKB(tidn), .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), @@ -265,7 +267,7 @@ module tri_512x162_4w_0( .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), .ENA(act[w]), .ENB(tidn), - .SSRA(nclk[1]), + .SSRA(rst), .SSRB(tidn), .WEA(write[w]), .WEB(tidn) @@ -283,7 +285,8 @@ module tri_512x162_4w_0( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(1'b1), .thold_b(lcb_func_sl_thold_0_b), .sg(lcb_sg_0), @@ -301,7 +304,8 @@ module tri_512x162_4w_0( tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_l2), .thold_b(lcb_func_sl_thold_0_b), .sg(lcb_sg_0), @@ -319,7 +323,8 @@ module tri_512x162_4w_0( tri_plat #(.WIDTH(1)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din(lcb_sg_1), .q(lcb_sg_0) @@ -332,7 +337,7 @@ module tri_512x162_4w_0( assign bo_pc_failout = 2'b00; assign bo_pc_diagloop = 2'b00; - assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout}); + assign unused = | ({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout}); end endgenerate endmodule diff --git a/dev/verilog/trilib/tri_512x16_1r1w_1.v b/dev/verilog/trilib/tri_512x16_1r1w_1.v old mode 100755 new mode 100644 index b8c643a..11c157a --- a/dev/verilog/trilib/tri_512x16_1r1w_1.v +++ b/dev/verilog/trilib/tri_512x16_1r1w_1.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -33,13 +33,16 @@ // //***************************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" -module tri_512x16_1r1w_1( +module tri_512x16_1r1w_1 ( vdd, vcs, gnd, - nclk, + clk, + rst, rd_act, wr_act, lcb_d_mode_dc, @@ -106,7 +109,8 @@ module tri_512x16_1r1w_1( inout vcs; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input rd_act; input wr_act; @@ -173,146 +177,76 @@ module tri_512x16_1r1w_1( output [0:15] dout; - // Configuration Statement for NCsim - //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; - wire clk; - wire clk2x; wire [0:8] b0addra; wire [0:8] b0addrb; wire wea; wire web; wire wren_a; - // Latches - reg reset_q; - reg gate_fq; - wire gate_d; - wire [0:35] r_data_out_1_d; - reg [0:35] r_data_out_1_fq; - wire [0:35] w_data_in_0; + wire [0:15] w_data_in_0; + wire [0:15] r_data_out_0_bram; - wire [0:35] r_data_out_0_bram; - wire [0:35] r_data_out_1_bram; + // Latches + reg [0:15] r_data_out_1_q; - wire toggle_d; - reg toggle_q; - wire toggle2x_d; - reg toggle2x_q; (* analysis_not_referenced="true" *) wire unused; - assign clk = nclk[0]; - assign clk2x = nclk[2]; - - always @(posedge clk) - begin: rlatch - reset_q <= nclk[1]; - end - - // - // NEW clk2x gate logic start - // - - always @(posedge clk) - begin: tlatch - if (reset_q == 1'b1) - toggle_q <= 1'b1; - else - toggle_q <= toggle_d; - end - - always @(posedge clk2x) - begin: flatch - toggle2x_q <= toggle2x_d; - gate_fq <= gate_d; - r_data_out_1_fq <= r_data_out_1_d; - end - - assign toggle_d = (~toggle_q); - assign toggle2x_d = toggle_q; - - // should force gate_fq to be on during odd 2x clock (second half of 1x clock). - //gate_d <= toggle_q xor toggle2x_q; - // if you want the first half do the following - assign gate_d = (~(toggle_q ^ toggle2x_q)); - - // - // NEW clk2x gate logic end - // - + // sim array + reg [0:15] mem[0:511]; + + integer i; + initial begin + for (i = 0; i < 512; i = i + 1) + mem[i] = 0; + end + + //wtf:icarus $dumpvars cannot dump a vpiMemory + generate + genvar j; + for (j = 0; j < 512; j=j+1) begin: loc + wire [0:15] dat; + assign dat = mem[j][0:15]; + end + endgenerate + + //wtf do they use diff addresses? assign b0addra[0:8] = wr_adr; assign b0addrb[0:8] = rd_adr; - // Unused Address Bits - //b0addra(0 to 1) <= "00"; - //b0addrb(0 to 1) <= "00"; - // port a is a read-modify-write port - assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 : - 1'b0; - assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk + assign wren_a = (bw != 0) & wr_act; + assign wea = wren_a; assign web = 1'b0; - assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : - r_data_out_0_bram[0]; - assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : - r_data_out_0_bram[1]; - assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : - r_data_out_0_bram[2]; - assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : - r_data_out_0_bram[3]; - assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : - r_data_out_0_bram[4]; - assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : - r_data_out_0_bram[5]; - assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : - r_data_out_0_bram[6]; - assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : - r_data_out_0_bram[7]; - assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] : - r_data_out_0_bram[8]; - assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] : - r_data_out_0_bram[9]; - assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : - r_data_out_0_bram[10]; - assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : - r_data_out_0_bram[11]; - assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : - r_data_out_0_bram[12]; - assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : - r_data_out_0_bram[13]; - assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] : - r_data_out_0_bram[14]; - assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] : - r_data_out_0_bram[15]; - assign w_data_in_0[16:35] = 20'b0; + assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0]; + assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1]; + assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2]; + assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3]; + assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4]; + assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5]; + assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6]; + assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7]; + assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8]; + assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9]; + assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10]; + assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11]; + assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12]; + assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13]; + assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14]; + assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15]; + + always @(posedge clk) begin + + r_data_out_1_q <= mem[b0addrb]; + if (wea) begin + mem[b0addra] <= w_data_in_0; + end - assign r_data_out_1_d = r_data_out_1_bram; - - RAMB16_S36_S36 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram0a( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(reset_q), - .SSRB(reset_q), - .ADDRA(b0addra), - .ADDRB(b0addrb), - .DIA(w_data_in_0[0:31]), - .DIB(32'b0), - .DOA(r_data_out_0_bram[0:31]), - .DOB(r_data_out_1_bram[0:31]), - .DOPA(r_data_out_0_bram[32:35]), - .DOPB(r_data_out_1_bram[32:35]), - .DIPA(w_data_in_0[32:35]), - .DIPB(4'h0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(wea), - .WEB(web) - ); + end - assign dout = r_data_out_1_fq[0:15]; + assign r_data_out_0_bram = mem[b0addra]; + assign dout = r_data_out_1_q[0:15]; assign func_scan_out = func_scan_in; assign time_scan_out = time_scan_in; @@ -322,12 +256,12 @@ module tri_512x16_1r1w_1( assign bo_pc_failout = 1'b0; assign bo_pc_diagloop = 1'b0; - assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, + assign unused = |{vdd, vcs, gnd, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]}; + tri_lcb_act_dis_dc, rd_act}; endmodule diff --git a/dev/verilog/trilib/tri_64x144_1r1w.v b/dev/verilog/trilib/tri_64x144_1r1w.v old mode 100755 new mode 100644 index 4144333..922cae9 --- a/dev/verilog/trilib/tri_64x144_1r1w.v +++ b/dev/verilog/trilib/tri_64x144_1r1w.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -36,11 +36,12 @@ `include "tri_a2o.vh" -module tri_64x144_1r1w( +module tri_64x144_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, rd_act, wr_act, sg_0, @@ -114,7 +115,8 @@ inout vdd; inout vcs; // CLOCK and CLOCKCONTROL ports -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input rd_act; input wr_act; input sg_0; @@ -302,8 +304,8 @@ generate begin .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]), .DIB(32'b0), .DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]), @@ -312,8 +314,8 @@ generate begin .ENB(act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), //sreset - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(wrt_en[anum * 4:anum * 4 + 3]), .WEB(4'b0) //' ); @@ -336,7 +338,6 @@ assign unused = | { cascadeoutregb , ramb_data_dummy , ramb_par_dummy , - nclk[2:`NCLK_WIDTH-1] , gnd , vdd , vcs , @@ -387,7 +388,8 @@ assign unused = | { tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -405,7 +407,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/trilib/tri_64x34_8w_1r1w.v b/dev/verilog/trilib/tri_64x34_8w_1r1w.v old mode 100755 new mode 100644 index b7efe3e..3c46ab4 --- a/dev/verilog/trilib/tri_64x34_8w_1r1w.v +++ b/dev/verilog/trilib/tri_64x34_8w_1r1w.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -36,11 +36,12 @@ `include "tri_a2o.vh" -module tri_64x34_8w_1r1w( +module tri_64x34_8w_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, rd_act, wr_act, sg_0, @@ -116,7 +117,8 @@ inout vdd; inout vcs; // CLOCK and CLOCKCONTROL ports -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input rd_act; input wr_act; input sg_0; @@ -319,8 +321,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -329,8 +331,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), //sreset - .SSRB(nclk[1]), //sreset + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[0]), .WEB(tidn[0:3]) ); @@ -351,8 +353,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -361,8 +363,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[1]), .WEB(tidn[0:3]) ); @@ -383,8 +385,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -393,8 +395,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[2]), .WEB(tidn[0:3]) ); @@ -415,8 +417,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -425,8 +427,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[3]), .WEB(tidn[0:3]) ); @@ -447,8 +449,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -457,8 +459,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[4]), .WEB(tidn[0:3]) ); @@ -479,8 +481,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -489,8 +491,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[5]), .WEB(tidn[0:3]) ); @@ -511,8 +513,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -521,8 +523,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[6]), .WEB(tidn[0:3]) ); @@ -543,8 +545,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .CASCADEINLATB(1'b0), .CASCADEINREGA(1'b0), .CASCADEINREGB(1'b0), - .CLKA(nclk[0]), - .CLKB(nclk[0]), + .CLKA(clk), + .CLKB(clk), .DIA(arr_data_in), .DIB(tidn[0:31]), .DIPA(arr_par_in), @@ -553,8 +555,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR .ENB(rd_act), .REGCEA(1'b0), .REGCEB(1'b0), - .SSRA(nclk[1]), - .SSRB(nclk[1]), + .SSRA(rst), + .SSRB(rst), .WEA(write_enable_way[7]), .WEB(tidn[0:3]) ); @@ -566,7 +568,7 @@ assign bo_pc_failout = tidn[0:3]; assign bo_pc_diagloop = tidn[0:3]; assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutregb, tiup, wr_act, - ramb_data_p0_concat, nclk[2:`NCLK_WIDTH-1], gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0, + ramb_data_p0_concat, gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, @@ -582,7 +584,8 @@ assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutreg tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -600,7 +603,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmreg_p #(.WIDTH((ways*port_bitwidth)), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rd_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/trilib/tri_64x72_1r1w.v b/dev/verilog/trilib/tri_64x72_1r1w.v old mode 100755 new mode 100644 index f99ea6b..44385bd --- a/dev/verilog/trilib/tri_64x72_1r1w.v +++ b/dev/verilog/trilib/tri_64x72_1r1w.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -26,20 +26,23 @@ // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // obtained (along with the Power ISA) here: https://openpowerfoundation.org. -`timescale 1 ps / 1 ps +`timescale 1 ns / 1 ns //***************************************************************************** // Description: Tri-Lam Array Wrapper // //***************************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" -module tri_64x72_1r1w( +module tri_64x72_1r1w ( vdd, vcs, gnd, - nclk, + clk, + rst, sg_0, abst_sl_thold_0, ary_nsl_thold_0, @@ -102,7 +105,8 @@ module tri_64x72_1r1w( inout gnd; // Clock Pervasive - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input abst_sl_thold_0; input ary_nsl_thold_0; @@ -167,150 +171,75 @@ module tri_64x72_1r1w( input abist_raw_dc_b; input [0:3] obs0_abist_cmp; - // Configuration Statement for NCsim - //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; - wire clk; - wire clk2x; - reg [0:8] addra; - reg [0:8] addrb; - reg wea; - reg web; - wire [0:71] bdo; - wire [0:71] bdi; wire sreset; wire [0:71] tidn; - // Latches - reg reset_q; - reg gate_fq; - wire gate_d; - wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_d; - reg [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_fq; - - wire toggle_d; - reg toggle_q; - wire toggle2x_d; - reg toggle2x_q; (* analysis_not_referenced="true" *) wire unused; + // sim array + reg [0:63] mem[0:71]; + + reg r0_e_q; + wire r0_e_d; + reg [0:5] r0_a_q; + wire [0:5] r0_a_d; + reg [0:71] r0_d_q; + wire [0:71] r0_d_d; + + reg w0_e_q; + wire w0_e_d; + reg [0:5] w0_a_q; + wire [0:5] w0_a_d; + reg [0:71] w0_d_q; + wire [0:71] w0_d_d; + + integer i; + initial begin + for (i = 0; i < 64; i = i + 1) + mem[i] = 0; + end + + //wtf:icarus $dumpvars cannot dump a vpiMemory generate - assign tidn = 72'b0; - assign clk = nclk[0]; - assign clk2x = nclk[2]; - assign sreset = nclk[1]; - - always @(posedge clk) - begin: rlatch - // reset_q <= #10 sreset; - reset_q <= sreset; //wtf try for icarus - end - - // - // NEW clk2x gate logic start - // - - always @(posedge clk) - begin: tlatch - if (reset_q == 1'b1) - toggle_q <= 1'b1; - else - toggle_q <= toggle_d; - end - - always @(posedge clk2x) - begin: flatch - toggle2x_q <= toggle2x_d; - gate_fq <= gate_d; - bdo_fq <= bdo_d; - end - - assign toggle_d = (~toggle_q); - assign toggle2x_d = toggle_q; + genvar j; + for (j = 0; j < 63; j=j+1) begin: loc + wire [0:63] dat; + wire [0:7] par; + assign dat = mem[j][0:63]; + assign par = mem[j][0:7]; + end + endgenerate - // should force gate_fq to be on during odd 2x clock (second half of 1x clock). - //gate_d <= toggle_q xor toggle2x_q; - // if you want the first half do the following - assign gate_d = (~(toggle_q ^ toggle2x_q)); - - // - // NEW clk2x gate logic end - // - - if (`GPR_WIDTH == 32) - begin - assign bdi = {tidn[0:31], di[32:63], di[64:70], tidn[71]}; - end - if (`GPR_WIDTH == 64) - begin - assign bdi = di[0:71]; - end - - assign bdo_d = bdo[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)]; - assign do0 = bdo_fq; - - - always @ (*) - begin - /* - wea = #10 (wr_act & gate_fq); - web = #10 (wr_act & gate_fq); + generate - addra = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : - {2'b00, rd0_adr, 1'b0}); + always @(posedge clk) begin - addrb = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : - {2'b00, rd0_adr, 1'b1}); - wea = #10 (wr_act & gate_fq); - */ - wea = wr_act & gate_fq; - web = wr_act & gate_fq; + r0_e_q <= rd0_act; + r0_a_q <= rd0_adr; + r0_d_q <= r0_e_q ? mem[r0_a_q] : 0; - addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : - {2'b00, rd0_adr, 1'b0}); + if (w0_e_q) begin + mem[w0_a_q] <= w0_d_q; + end + w0_e_q <= wr_act; + w0_a_q <= wr_adr; + w0_d_q <= di; - addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : - {2'b00, rd0_adr, 1'b1}); - end - /* make wires? - assign wea = wr_act & gate_fq; - assign web = wr_act & gate_fq; - assign addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : {2'b00, rd0_adr, 1'b0}); - assign addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : {2'b00, rd0_adr, 1'b1}); - */ + end - RAMB16_S36_S36 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram0a( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset), - .SSRB(sreset), - .ADDRA(addra), - .ADDRB(addrb), - .DIA(bdi[00:31]), - .DIB(bdi[32:63]), - .DIPA(bdi[64:67]), - .DIPB(bdi[68:71]), - .DOA(bdo[00:31]), - .DOB(bdo[32:63]), - .DOPA(bdo[64:67]), - .DOPB(bdo[68:71]), - .ENA(1'b1), - .ENB(1'b1), - .WEA(wea), - .WEB(web) - ); + assign do0 = r0_d_q; - assign abst_scan_out = abst_scan_in; - assign time_scan_out = time_scan_in; - assign repr_scan_out = repr_scan_in; + assign abst_scan_out = abst_scan_in; + assign time_scan_out = time_scan_in; + assign repr_scan_out = repr_scan_in; - assign bo_pc_failout = 1'b0; - assign bo_pc_diagloop = 1'b0; + assign bo_pc_failout = 1'b0; + assign bo_pc_diagloop = 1'b0; - assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc}); + assign unused = | ({sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc}); endgenerate + endmodule diff --git a/dev/verilog/trilib/tri_a2o.vh b/dev/verilog/trilib/tri_a2o.vh index 0624eee..6caa225 100755 --- a/dev/verilog/trilib/tri_a2o.vh +++ b/dev/verilog/trilib/tri_a2o.vh @@ -34,6 +34,9 @@ // Use this line for 1 thread. Comment out for 2 thread design. `define THREADS1 +// 0: none 1: DP +`define FLOAT_TYPE 1 + `define gpr_t 3'b000 `define cr_t 3'b001 `define lr_t 3'b010 diff --git a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v index 45ee359..e2bebd6 100755 --- a/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v +++ b/dev/verilog/trilib/tri_aoi22_nlats_wlcb.v @@ -36,10 +36,11 @@ `include "tri_a2o.vh" -module tri_aoi22_nlats_wlcb( +module tri_aoi22_nlats_wlcb ( vd, gd, - nclk, + clk, + rst, act, force_t, thold_b, @@ -71,7 +72,8 @@ module tri_aoi22_nlats_wlcb( inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; // 1: functional, 0: no clock input force_t; // 1: force LCB active input thold_b; // 1: functional, 0: no clock @@ -107,12 +109,9 @@ module tri_aoi22_nlats_wlcb( (* analysis_not_referenced="true" *) wire unused; - if (NEEDS_SRESET == 1) - begin : rst - assign sreset = nclk[1]; - end - if (NEEDS_SRESET != 1) - begin : no_rst + if (NEEDS_SRESET == 1) begin + assign sreset = rst; + end else begin assign sreset = 1'b0; end @@ -128,7 +127,7 @@ module tri_aoi22_nlats_wlcb( assign vthold_b = {WIDTH{thold_b}}; assign vthold = {WIDTH{~thold_b}}; - always @(posedge nclk[0]) begin: l + always @(posedge clk) begin: l //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); if (sreset) int_dout <= int_din; @@ -140,6 +139,6 @@ module tri_aoi22_nlats_wlcb( assign scout = ZEROS; - assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin); + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|scin); endgenerate endmodule diff --git a/dev/verilog/trilib/tri_bht_1024x8_1r1w.v b/dev/verilog/trilib/tri_bht_1024x8_1r1w.v index 68fd3f1..0588aeb 100755 --- a/dev/verilog/trilib/tri_bht_1024x8_1r1w.v +++ b/dev/verilog/trilib/tri_bht_1024x8_1r1w.v @@ -41,11 +41,12 @@ `include "tri_a2o.vh" -module tri_bht_1024x8_1r1w( +module tri_bht_1024x8_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, @@ -112,7 +113,8 @@ module tri_bht_1024x8_1r1w( inout vcs; // clock and clockcontrol ports - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_2; input pc_iu_sg_2; input pc_iu_time_sl_thold_2; @@ -331,7 +333,8 @@ module tri_bht_1024x8_1r1w( .gnd(gnd), .vdd(vdd), .vcs(vcs), - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(ary_r_en), .wr_act(ary_w_en), @@ -404,7 +407,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -423,7 +427,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -442,7 +447,8 @@ module tri_bht_1024x8_1r1w( tri_rlmlatch_p #(.INIT(0)) r_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -461,7 +467,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -480,7 +487,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ri_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -499,7 +507,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ro_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -517,7 +526,8 @@ module tri_bht_1024x8_1r1w( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reset_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -540,7 +550,8 @@ module tri_bht_1024x8_1r1w( tri_plat #(.WIDTH(7)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) @@ -550,7 +561,8 @@ module tri_bht_1024x8_1r1w( tri_plat #(.WIDTH(7)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) diff --git a/dev/verilog/trilib/tri_bht_512x4_1r1w.v b/dev/verilog/trilib/tri_bht_512x4_1r1w.v index b25f25c..87258a6 100755 --- a/dev/verilog/trilib/tri_bht_512x4_1r1w.v +++ b/dev/verilog/trilib/tri_bht_512x4_1r1w.v @@ -41,11 +41,12 @@ `include "tri_a2o.vh" -module tri_bht_512x4_1r1w( +module tri_bht_512x4_1r1w ( gnd, vdd, vcs, - nclk, + clk, + rst, pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, @@ -112,7 +113,8 @@ module tri_bht_512x4_1r1w( inout vcs; // clock and clockcontrol ports - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_2; input pc_iu_sg_2; input pc_iu_time_sl_thold_2; @@ -331,7 +333,8 @@ module tri_bht_512x4_1r1w( .gnd(gnd), .vdd(vdd), .vcs(vcs), - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(ary_r_en), .wr_act(ary_w_en), @@ -404,7 +407,8 @@ module tri_bht_512x4_1r1w( tri_rlmlatch_p #(.INIT(0)) data_in_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -423,7 +427,8 @@ module tri_bht_512x4_1r1w( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -442,7 +447,8 @@ module tri_bht_512x4_1r1w( tri_rlmlatch_p #(.INIT(0)) r_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -461,7 +467,8 @@ module tri_bht_512x4_1r1w( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -480,7 +487,8 @@ module tri_bht_512x4_1r1w( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ri_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -499,7 +507,8 @@ module tri_bht_512x4_1r1w( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ro_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -517,7 +526,8 @@ module tri_bht_512x4_1r1w( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reset_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -540,7 +550,8 @@ module tri_bht_512x4_1r1w( tri_plat #(.WIDTH(7)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) @@ -550,7 +561,8 @@ module tri_bht_512x4_1r1w( tri_plat #(.WIDTH(7)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) diff --git a/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v b/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v index 6f22617..a3a064f 100755 --- a/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v +++ b/dev/verilog/trilib/tri_cam_16x143_1r1w1c.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -14,35 +14,35 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns -// VHDL 1076 Macro Expander C version 07/11/00 -// job was run on Fri Mar 19 10:58:26 2010 - //******************************************************************** //* TITLE: I-ERAT CAM Tri-Library Model //* NAME: tri_cam_16x143_1r1w1c //******************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" -module tri_cam_16x143_1r1w1c( +module tri_cam_16x143_1r1w1c ( gnd, vdd, vcs, - nclk, + clk, + rst, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, @@ -116,7 +116,8 @@ module tri_cam_16x143_1r1w1c( inout vcs; // Clocks and Scan Cntls - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input tc_ccflush_dc; input tc_scan_dis_dc_b; input tc_scan_diag_dc; @@ -195,15 +196,8 @@ module tri_cam_16x143_1r1w1c( output [22:51] rpn_np2; - // tri_cam_16x143_1r1w1c - - // Configuration Statement for NCsim - //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; - //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; - //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; - wire clk; - wire clk2x; + wire rst; wire [0:8] bram0_addra; wire [0:8] bram0_addrb; wire [0:10] bram1_addra; @@ -217,9 +211,6 @@ module tri_cam_16x143_1r1w1c( wire [66:72] array_cmp_data_bramp; // Latches - reg sreset_q; - reg gate_fq; - wire gate_d; wire [52-RPN_WIDTH:51] comp_addr_np1_d; reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input wire [52-RPN_WIDTH:51] rpn_np2_d; @@ -708,51 +699,26 @@ module tri_cam_16x143_1r1w1c( (* analysis_not_referenced="true" *) wire unused; + // sim array + reg [0:62] mem[0:15]; - - assign clk = (~nclk[0]); - assign clk2x = nclk[2]; - - always @(posedge clk) - begin: rlatch - sreset_q <= nclk[1]; - end - - // - // NEW clk2x gate logic start - // - - always @(posedge nclk[0]) - begin: tlatch - if (sreset_q == 1'b1) - toggle_q <= 1'b1; - else - toggle_q <= toggle_d; - end - - always @(posedge nclk[2]) - begin: flatch - toggle2x_q <= toggle2x_d; - gate_fq <= gate_d; + integer i; + initial begin + for (i = 0; i < 16; i = i + 1) + mem[i] = 0; end - assign toggle_d = (~toggle_q); - assign toggle2x_d = toggle_q; - - // should force gate_fq to be on during odd 2x clock (second half of 1x clock). - assign gate_d = toggle_q ^ toggle2x_q; - // if you want the first half do the following - //assign gate_d <= ~(toggle_q ^ toggle2x_q); - - // - // NEW clk2x gate logic end - // - - // Slow Latches (nclk) - always @(posedge nclk[0]) - begin: slatch - if (sreset_q == 1'b1) - begin + //wtf:icarus $dumpvars cannot dump a vpiMemory + generate + genvar j; + for (j = 0; j < 16; j=j+1) begin: loc + wire [0:62] dat; + assign dat = mem[j][0:62]; //wtf split into fields someday + end + endgenerate + + always @(posedge clk) begin: slatch + if (rst) begin cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; cam_cmp_parity_q <= 10'b0; rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; @@ -2539,9 +2505,9 @@ module tri_cam_16x143_1r1w1c( //--------------------------------------------------------------------- // BRAM signal assignments //--------------------------------------------------------------------- - assign bram0_wea = wr_array_val[0] & gate_fq; - assign bram1_wea = wr_array_val[1] & gate_fq; - assign bram2_wea = wr_array_val[1] & gate_fq; + assign bram0_wea = wr_array_val[0]; + assign bram1_wea = wr_array_val[1]; + assign bram2_wea = wr_array_val[1];; assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; @@ -2559,8 +2525,24 @@ module tri_cam_16x143_1r1w1c( assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; - // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) - // uses wr_array_val(0), parity is wr_array_data_bram(66:69) + // was 3 brams using clk2x w/wea on 2of2; matchline is combinational + always @(posedge clk) begin + + if (bram0_wea) begin + mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; + end + if (bram1_wea) begin + mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; + end + + end + + assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; + assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; + assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; + assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; + +/* RAMB16_S36_S36 #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only bram0( @@ -2633,6 +2615,7 @@ module tri_cam_16x143_1r1w1c( .WEA(bram2_wea), .WEB(1'b0) ); +*/ // array write data swizzle -> convert 68-bit data to 73-bit bram data // 32x143 version, 42b RA @@ -2695,7 +2678,7 @@ module tri_cam_16x143_1r1w1c( assign regfile_scan_out = regfile_scan_in; assign time_scan_out = time_scan_in; - assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + assign unused = |{gnd, vdd, vcs, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, diff --git a/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v b/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v index 71457cf..02baaf1 100755 --- a/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v +++ b/dev/verilog/trilib/tri_cam_32x143_1r1w1c.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -28,21 +28,21 @@ `timescale 1 ns / 1 ns -// VHDL 1076 Macro Expander C version 07/11/00 -// job was run on Mon Nov 8 10:36:46 2010 - //******************************************************************** //* TITLE: I-ERAT CAM Tri-Library Model //* NAME: tri_cam_32x143_1r1w1c //******************************************************************** +// sim version, clk1x + `include "tri_a2o.vh" module tri_cam_32x143_1r1w1c( gnd, vdd, vcs, - nclk, + clk, + rst, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, @@ -116,7 +116,8 @@ module tri_cam_32x143_1r1w1c( inout vcs; // Clocks and Scan Cntls - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input tc_ccflush_dc; input tc_scan_dis_dc_b; input tc_scan_diag_dc; @@ -195,15 +196,8 @@ module tri_cam_32x143_1r1w1c( output [22:51] rpn_np2; - // tri_cam_32x143_1r1w1c - - // Configuration Statement for NCsim - //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; - //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; - //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; - wire clk; - wire clk2x; + wire reset; wire [0:8] bram0_addra; wire [0:8] bram0_addrb; wire [0:10] bram1_addra; @@ -217,9 +211,6 @@ module tri_cam_32x143_1r1w1c( wire [66:72] array_cmp_data_bramp; // Latches - reg sreset_q; - reg gate_fq; - wire gate_d; wire [52-RPN_WIDTH:51] comp_addr_np1_d; reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input wire [52-RPN_WIDTH:51] rpn_np2_d; @@ -1156,51 +1147,26 @@ module tri_cam_32x143_1r1w1c( (* analysis_not_referenced="true" *) wire unused; + // sim array + reg [0:62] mem[0:31]; - - assign clk = (~nclk[0]); - assign clk2x = nclk[2]; - - always @(posedge clk) - begin: rlatch - sreset_q <= nclk[1]; - end - - // - // NEW clk2x gate logic start - // - - always @(posedge nclk[0]) - begin: tlatch - if (sreset_q == 1'b1) - toggle_q <= 1'b1; - else - toggle_q <= toggle_d; - end - - always @(posedge nclk[2]) - begin: flatch - toggle2x_q <= toggle2x_d; - gate_fq <= gate_d; + integer i; + initial begin + for (i = 0; i < 32; i = i + 1) + mem[i] = 0; end - assign toggle_d = (~toggle_q); - assign toggle2x_d = toggle_q; - - // should force gate_fq to be on during odd 2x clock (second half of 1x clock). - assign gate_d = toggle_q ^ toggle2x_q; - // if you want the first half do the following - //assign gate_d <= ~(toggle_q ^ toggle2x_q); - - // - // NEW clk2x gate logic end - // - - // Slow Latches (nclk) - always @(posedge nclk[0]) - begin: slatch - if (sreset_q == 1'b1) - begin + //wtf:icarus $dumpvars cannot dump a vpiMemory + generate + genvar j; + for (j = 0; j < 32; j=j+1) begin: loc + wire [0:62] dat; + assign dat = mem[j][0:62]; //wtf split into fields someday + end + endgenerate + + always @(posedge clk) begin: slatch + if (rst) begin cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; cam_cmp_parity_q <= 10'b0; rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; @@ -4663,13 +4629,12 @@ module tri_cam_32x143_1r1w1c( .match(match_vec[31]) ); - //--------------------------------------------------------------------- // BRAM signal assignments //--------------------------------------------------------------------- - assign bram0_wea = wr_array_val[0] & gate_fq; - assign bram1_wea = wr_array_val[1] & gate_fq; - assign bram2_wea = wr_array_val[1] & gate_fq; + assign bram0_wea = wr_array_val[0]; + assign bram1_wea = wr_array_val[1]; + assign bram2_wea = wr_array_val[1]; assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; @@ -4687,6 +4652,24 @@ module tri_cam_32x143_1r1w1c( assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; +// was 3 brams using clk2x w/wea on 2of2; matchline is combinational + always @(posedge clk) begin + + if (bram0_wea) begin + mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; + end + if (bram1_wea) begin + mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; + end + + end + + assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; + assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; + assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; + assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; + +/* // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) // uses wr_array_val(0), parity is wr_array_data_bram(66:69) RAMB16_S36_S36 @@ -4761,6 +4744,7 @@ module tri_cam_32x143_1r1w1c( .WEA(bram2_wea), .WEB(1'b0) ); + */ // array write data swizzle -> convert 68-bit data to 73-bit bram data // 32x143 version, 42b RA @@ -4839,7 +4823,7 @@ module tri_cam_32x143_1r1w1c( assign regfile_scan_out = regfile_scan_in; assign time_scan_out = time_scan_in; - assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, + assign unused = |{gnd, vdd, vcs, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, diff --git a/dev/verilog/trilib/tri_fu_mul.v b/dev/verilog/trilib/tri_fu_mul.v index ad35260..6b07f3e 100755 --- a/dev/verilog/trilib/tri_fu_mul.v +++ b/dev/verilog/trilib/tri_fu_mul.v @@ -33,6 +33,8 @@ module tri_fu_mul( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module tri_fu_mul( sg_1, thold_1, fpu_enable, - nclk, f_mul_si, f_mul_so, ex2_act, @@ -56,6 +57,8 @@ module tri_fu_mul( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -65,7 +68,6 @@ module tri_fu_mul( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_mul_si; //perv output f_mul_so; //perv @@ -120,7 +122,8 @@ module tri_fu_mul( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -130,7 +133,8 @@ module tri_fu_mul( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -159,7 +163,8 @@ module tri_fu_mul( .mpw2_b(mpw2_b), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -224,7 +229,8 @@ module tri_fu_mul( tri_fu_mul_92 #(.inst(2)) m92_2( .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .force_t(force_t), //i-- .lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 @@ -247,7 +253,8 @@ module tri_fu_mul( tri_fu_mul_92 #(.inst(1)) m92_1( .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .force_t(force_t), //i-- .lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 @@ -270,7 +277,8 @@ module tri_fu_mul( tri_fu_mul_92 #(.inst(0)) m92_0( .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .force_t(force_t), //i-- .lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 diff --git a/dev/verilog/trilib/tri_fu_mul_92.v b/dev/verilog/trilib/tri_fu_mul_92.v index d345e7e..d7d5f4d 100755 --- a/dev/verilog/trilib/tri_fu_mul_92.v +++ b/dev/verilog/trilib/tri_fu_mul_92.v @@ -39,7 +39,8 @@ module tri_fu_mul_92( vdd, gnd, - nclk, + clk, + rst, si, so, ex2_act, @@ -58,7 +59,8 @@ module tri_fu_mul_92( parameter inst = 0; inout vdd; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; //perv + input clk; + input rst; input si; //perv output so; //perv input ex2_act; //act @@ -4385,7 +4387,8 @@ module tri_fu_mul_92( .mpw1_b(lcb_mpw1_b), //in -- tidn , .mpw2_b(lcb_mpw2_b), //in -- tidn , .force_t(force_t), //in -- tidn , - .nclk(nclk), //in + .clk(clk), //in + .rst(rst), .vd(vdd), //inout .gd(gnd), //inout .act(ex2_act), //in diff --git a/dev/verilog/trilib/tri_iuq_cpl_arr.v b/dev/verilog/trilib/tri_iuq_cpl_arr.v index baf3bc1..1cbb5ae 100755 --- a/dev/verilog/trilib/tri_iuq_cpl_arr.v +++ b/dev/verilog/trilib/tri_iuq_cpl_arr.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -26,16 +26,18 @@ // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // obtained (along with the Power ISA) here: https://openpowerfoundation.org. -`timescale 1 fs / 1 fs +`timescale 1 ns / 1 ns // *!**************************************************************** // *! FILENAME : tri_iuq_cpl_arr.v // *! DESCRIPTION : iuq completion array (fpga model) // *!**************************************************************** +// sim model - get rid of latched reset and other junk + `include "tri_a2o.vh" -module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr); +module tri_iuq_cpl_arr (gnd, vdd, clk, rst, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr); parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports) parameter PORT_BITWIDTH = 64; // bitwidth of ports @@ -49,7 +51,8 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for (* power_pin=1 *) inout vdd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; //------------------------------------------------------------------- // Pervasive @@ -100,10 +103,8 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for wire [0:PORT_BITWIDTH-1] do1_d; reg [0:PORT_BITWIDTH-1] di1_q; - wire correct_clk; + wire clk; wire reset; - wire reset_hi; - reg reset_q; wire [0:PORT_BITWIDTH-1] dout0; //std wire wen0; //std @@ -129,36 +130,18 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for generate - assign reset = nclk[1]; - assign correct_clk = nclk[0]; - - assign reset_hi = reset; - - - // Slow Latches (nclk) - always @(posedge correct_clk or posedge reset) - begin: slatch - begin - if (reset == 1'b1) - we1_latch_q <= 1'b0; - else - begin - we1_latch_q <= we1_q; - wa1_latch_q <= wa1_q; - di1_latch_q <= di1_q; - end + always @(posedge clk) begin + if (rst) + we1_latch_q <= 1'b0; + else begin + we1_latch_q <= we1_q; + wa1_latch_q <= wa1_q; + di1_latch_q <= di1_q; end end - - // repower latches for resets - always @(posedge correct_clk) - begin: rlatch - reset_q <= reset_hi; - end - - // need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag + // need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag // when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order // bit of wa1 assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; @@ -199,7 +182,7 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for .DPRA5(addr_r0[5]), //.DPRA(addr_r0), - .WCLK(correct_clk), + .WCLK(clk), .WE(wen0) ); @@ -225,7 +208,7 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for .DPRA5(addr_r1[5]), //.DPRA(addr_r1), - .WCLK(correct_clk), + .WCLK(clk), .WE(wen1) ); @@ -238,44 +221,31 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for assign do0 = do0_q; assign do1 = do1_q; - if (LATCHED_READ == 1'b0) - begin : read_latched_false - always @(*) - begin + if (LATCHED_READ == 1'b0) begin : read_latched_false + always @(*) begin re0_q <= re0; ra0_q <= ra0; re1_q <= re1; ra1_q <= ra1; end - end - if (LATCHED_READ == 1'b1) - begin : read_latched_true - always @(posedge correct_clk) - begin: read_latches - if (correct_clk == 1'b1) - begin - if (reset_q == 1'b1) - begin - re0_q <= 1'b0; - ra0_q <= {ADDRESSBUS_WIDTH{1'b0}}; - re1_q <= 1'b0; - ra1_q <= {ADDRESSBUS_WIDTH{1'b0}}; - end - else - begin - re0_q <= re0; - ra0_q <= ra0; - re1_q <= re1; - ra1_q <= ra1; - end + end else begin : read_latched_true + always @(posedge clk) begin: read_latches + if (reset) begin + re0_q <= 1'b0; + ra0_q <= {ADDRESSBUS_WIDTH{1'b0}}; + re1_q <= 1'b0; + ra1_q <= {ADDRESSBUS_WIDTH{1'b0}}; + end else begin + re0_q <= re0; + ra0_q <= ra0; + re1_q <= re1; + ra1_q <= ra1; end end end - if (LATCHED_WRITE == 1'b0) - begin : write_latched_false - always @(*) - begin + if (LATCHED_WRITE == 1'b0) begin : write_latched_false + always @(*) begin we0_q <= we0; wa0_q <= wa0; di0_q <= di0; @@ -283,61 +253,43 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for wa1_q <= wa1; di1_q <= di1; end - end - if (LATCHED_WRITE == 1'b1) - begin : write_latched_true - always @(posedge correct_clk) - begin: write_latches - if (correct_clk == 1'b1) - begin - if (reset_q == 1'b1) - begin - we0_q <= 1'b0; - wa0_q <= {ADDRESSBUS_WIDTH{1'b0}}; - di0_q <= {PORT_BITWIDTH{1'b0}}; - we1_q <= 1'b0; - wa1_q <= {ADDRESSBUS_WIDTH{1'b0}}; - di1_q <= {PORT_BITWIDTH{1'b0}}; - end - else - begin - we0_q <= we0; - wa0_q <= wa0; - di0_q <= di0; - we1_q <= we1; - wa1_q <= wa1; - di1_q <= di1; - end + end else begin : write_latched_true + always @(posedge clk) begin: write_latches + if (reset) begin + we0_q <= 1'b0; + wa0_q <= {ADDRESSBUS_WIDTH{1'b0}}; + di0_q <= {PORT_BITWIDTH{1'b0}}; + we1_q <= 1'b0; + wa1_q <= {ADDRESSBUS_WIDTH{1'b0}}; + di1_q <= {PORT_BITWIDTH{1'b0}}; + end else begin + we0_q <= we0; + wa0_q <= wa0; + di0_q <= di0; + we1_q <= we1; + wa1_q <= wa1; + di1_q <= di1; end - end + end end - if (LATCHED_READ_DATA == 1'b0) - begin : read_data_latched_false - always @(*) - begin + if (LATCHED_READ_DATA == 1'b0) begin : read_data_latched_false + always @(*) begin do0_q <= do0_d; do1_q <= do1_d; end - end - if (LATCHED_READ_DATA == 1'b1) - begin : read_data_latched_true - always @(posedge correct_clk) - begin: read_data_latches - if (correct_clk == 1'b1) - begin - if (reset_q == 1'b1) - begin - do0_q <= {PORT_BITWIDTH{1'b0}}; - do1_q <= {PORT_BITWIDTH{1'b0}}; - end - else - begin - do0_q <= do0_d; - do1_q <= do1_d; - end + end else begin : read_data_latched_true + always @(posedge clk) begin: read_data_latches + if (reset) begin + do0_q <= 0; + do1_q <= 0; + end else begin + do0_q <= do0_d; + do1_q <= do1_d; end end end + endgenerate + endmodule diff --git a/dev/verilog/trilib/tri_lcbcntl_array_mac.v b/dev/verilog/trilib/tri_lcbcntl_array_mac.v index c9c39e7..ef7ab6a 100755 --- a/dev/verilog/trilib/tri_lcbcntl_array_mac.v +++ b/dev/verilog/trilib/tri_lcbcntl_array_mac.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,11 +35,12 @@ `include "tri_a2o.vh" -module tri_lcbcntl_array_mac( +module tri_lcbcntl_array_mac ( vdd, gnd, sg, - nclk, + clk, + rst, scan_in, scan_diag_dc, thold, @@ -54,7 +55,8 @@ module tri_lcbcntl_array_mac( inout vdd; inout gnd; input sg; - input [0:`NCLK_WIDTH-1] nclk; + input rst; + input clk; input scan_in; input scan_diag_dc; input thold; @@ -79,5 +81,5 @@ module tri_lcbcntl_array_mac( assign mpw2_dc_b = 1'b1; assign scan_out = 1'b0; - assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; + assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold; endmodule diff --git a/dev/verilog/trilib/tri_lcbcntl_mac.v b/dev/verilog/trilib/tri_lcbcntl_mac.v old mode 100755 new mode 100644 index 7e55632..40c684c --- a/dev/verilog/trilib/tri_lcbcntl_mac.v +++ b/dev/verilog/trilib/tri_lcbcntl_mac.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,11 +35,12 @@ `include "tri_a2o.vh" -module tri_lcbcntl_mac( +module tri_lcbcntl_mac ( vdd, gnd, sg, - nclk, + clk, + rst, scan_in, scan_diag_dc, thold, @@ -54,7 +55,8 @@ module tri_lcbcntl_mac( inout vdd; inout gnd; input sg; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input scan_in; input scan_diag_dc; input thold; @@ -79,5 +81,5 @@ module tri_lcbcntl_mac( assign mpw2_dc_b = 1'b1; assign scan_out = 1'b0; - assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; + assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold; endmodule diff --git a/dev/verilog/trilib/tri_lcbnd.v b/dev/verilog/trilib/tri_lcbnd.v index 5d11dce..a02a512 100755 --- a/dev/verilog/trilib/tri_lcbnd.v +++ b/dev/verilog/trilib/tri_lcbnd.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,14 +35,15 @@ `include "tri_a2o.vh" -module tri_lcbnd( +module tri_lcbnd ( vd, gd, act, delay_lclkr, mpw1_b, mpw2_b, - nclk, + clk, + rst, force_t, sg, thold_b, @@ -58,7 +59,8 @@ module tri_lcbnd( input delay_lclkr; input mpw1_b; input mpw2_b; - input[0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input force_t; input sg; input thold_b; @@ -77,5 +79,5 @@ module tri_lcbnd( assign d1clk = gate_b; assign d2clk = thold_b; - assign lclk = nclk; + assign lclk = {clk,rst,{`NCLK_WIDTH-2{1'b0}}}; endmodule diff --git a/dev/verilog/trilib/tri_lcbs.v b/dev/verilog/trilib/tri_lcbs.v old mode 100755 new mode 100644 index 4c2b576..29b752f --- a/dev/verilog/trilib/tri_lcbs.v +++ b/dev/verilog/trilib/tri_lcbs.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,11 +35,13 @@ `include "tri_a2o.vh" -module tri_lcbs( +//wtf this should be changed to output clk,rst instead of lclk; think it's only for alternate ring lats? +module tri_lcbs ( vd, gd, delay_lclkr, - nclk, + clk, + rst, force_t, thold_b, dclk, @@ -48,7 +50,8 @@ module tri_lcbs( inout vd; inout gd; input delay_lclkr; - input[0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input force_t; input thold_b; output dclk; @@ -63,5 +66,5 @@ module tri_lcbs( // No scan chain in this methodology assign dclk = thold_b; - assign lclk = nclk; + assign lclk = {clk, rst, {`NCLK_WIDTH-2{1'b0}}}; endmodule diff --git a/dev/verilog/trilib/tri_lq_rmw.v b/dev/verilog/trilib/tri_lq_rmw.v index d06fa97..7709679 100755 --- a/dev/verilog/trilib/tri_lq_rmw.v +++ b/dev/verilog/trilib/tri_lq_rmw.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -72,7 +72,8 @@ module tri_lq_rmw( dcarr_wr_addr, dcarr_wr_data_wabcd, dcarr_wr_data_wefgh, - nclk, + clk, + rst, vdd, gnd, d_mode_dc, @@ -126,8 +127,8 @@ output [52:59] dcarr_wr_addr; output [0:143] dcarr_wr_data_wabcd; output [0:143] dcarr_wr_data_wefgh; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; inout vdd; inout gnd; input d_mode_dc; @@ -352,7 +353,8 @@ assign stq_byp_val_wefgh = stq_byp_val_wefgh_q; // Registers // ############################################################################################# tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -370,7 +372,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -390,7 +393,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -408,7 +412,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -426,7 +431,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -444,7 +450,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -462,7 +469,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq6_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -480,7 +488,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -498,7 +507,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq6_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -516,7 +526,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq6_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -534,7 +545,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq6_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -552,7 +564,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq7_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -570,7 +583,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq7_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -588,7 +602,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -606,7 +621,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -624,7 +640,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -642,7 +659,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_r tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -660,7 +678,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_r tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -678,7 +697,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -696,7 +716,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -714,7 +735,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/trilib/tri_parity_recovery.v b/dev/verilog/trilib/tri_parity_recovery.v index acec4cf..1028b0e 100755 --- a/dev/verilog/trilib/tri_parity_recovery.v +++ b/dev/verilog/trilib/tri_parity_recovery.v @@ -38,13 +38,14 @@ `include "tri_a2o.vh" -module tri_parity_recovery( +module tri_parity_recovery ( perr_si, perr_so, delay_lclkr, mpw1_b, mpw2_b, - nclk, + clk, + rst, force_t, thold_0_b, sg_0, @@ -132,7 +133,8 @@ module tri_parity_recovery( input [0:9] mpw1_b; input [0:1] mpw2_b; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input force_t; input thold_0_b; input sg_0; @@ -380,7 +382,8 @@ module tri_parity_recovery( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -412,7 +415,8 @@ module tri_parity_recovery( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -440,7 +444,8 @@ module tri_parity_recovery( tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -468,7 +473,8 @@ module tri_parity_recovery( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -537,7 +543,8 @@ module tri_parity_recovery( tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -557,7 +564,8 @@ module tri_parity_recovery( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -770,7 +778,8 @@ module tri_parity_recovery( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), diff --git a/dev/verilog/trilib/tri_plat.v b/dev/verilog/trilib/tri_plat.v index 5db3514..a718abd 100755 --- a/dev/verilog/trilib/tri_plat.v +++ b/dev/verilog/trilib/tri_plat.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,7 +35,7 @@ `include "tri_a2o.vh" -module tri_plat(vd, gd, nclk, flush, din, q); +module tri_plat (vd, gd, clk, rst, flush, din, q); parameter WIDTH = 1; parameter OFFSET = 0; parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v @@ -43,7 +43,8 @@ module tri_plat(vd, gd, nclk, flush, din, q); inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input flush; input [OFFSET:OFFSET+WIDTH-1] din; output [OFFSET:OFFSET+WIDTH-1] q; @@ -53,10 +54,10 @@ module tri_plat(vd, gd, nclk, flush, din, q); (* analysis_not_referenced="true" *) wire unused; - assign unused = | {vd, gd, nclk[1:`NCLK_WIDTH-1]}; + assign unused = | {vd, gd}; - always @ (posedge nclk[0]) + always @ (posedge clk) begin int_dout <= din; end diff --git a/dev/verilog/trilib/tri_regk.v b/dev/verilog/trilib/tri_regk.v old mode 100755 new mode 100644 index 851feec..c0ce819 --- a/dev/verilog/trilib/tri_regk.v +++ b/dev/verilog/trilib/tri_regk.v @@ -35,10 +35,11 @@ `include "tri_a2o.vh" -module tri_regk( +module tri_regk ( vd, gd, - nclk, + clk, + rst, act, force_t, thold_b, @@ -62,7 +63,8 @@ module tri_regk( inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; // 1: functional, 0: no clock input force_t; // 1: force LCB active input thold_b; // 1: functional, 0: no clock @@ -85,9 +87,9 @@ module tri_regk( (* analysis_not_referenced="true" *) wire unused; - assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; + assign sreset = (NEEDS_SRESET == 1) ? rst : 0; - always @(posedge nclk[0]) begin: l + always @(posedge clk) begin: l if (sreset) int_dout <= init_v; else if (act & thold_b) @@ -98,7 +100,8 @@ module tri_regk( assign scout = {WIDTH{1'b0}}; - assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); + assign unused = | {vd, gd, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin}; + endgenerate endmodule diff --git a/dev/verilog/trilib/tri_regs.v b/dev/verilog/trilib/tri_regs.v index 5e9eac2..9094fe7 100644 --- a/dev/verilog/trilib/tri_regs.v +++ b/dev/verilog/trilib/tri_regs.v @@ -35,10 +35,11 @@ `include "tri_a2o.vh" -module tri_regs( +module tri_regs ( vd, gd, - nclk, + clk, + rst, force_t, thold_b, delay_lclkr, @@ -57,7 +58,8 @@ module tri_regs( inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input force_t; // 1: force LCB active input thold_b; // 1: functional, 0: no clock input delay_lclkr; // 0: functional @@ -73,9 +75,9 @@ module tri_regs( (* analysis_not_referenced="true" *) wire unused; - assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; + assign sreset = (NEEDS_SRESET == 1) ? rst : 0; - always @(posedge nclk[0]) begin: l + always @(posedge clk) begin: l if (sreset) int_dout <= init_v; end @@ -84,7 +86,7 @@ module tri_regs( assign scout = {WIDTH{1'b0}}; - assign unused = |{vd, gd, delay_lclkr, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); + assign unused = |{vd, gd, delay_lclkr, scin}; endgenerate diff --git a/dev/verilog/trilib/tri_rlmlatch_p.v b/dev/verilog/trilib/tri_rlmlatch_p.v index ff3acd6..f4a5447 100755 --- a/dev/verilog/trilib/tri_rlmlatch_p.v +++ b/dev/verilog/trilib/tri_rlmlatch_p.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -35,7 +35,7 @@ `include "tri_a2o.vh" -module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); +module tri_rlmlatch_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); parameter INIT = 0; // will be converted to the least signficant // 31 bits of init_v parameter IBUF = 1'b0; //inverted latch IOs, if set to true. @@ -45,7 +45,8 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; // 1: functional, 0: no clock input force_t; // 1: force LCB active input thold_b; // 1: functional, 0: no clock @@ -62,8 +63,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl parameter WIDTH = 1; parameter [0:WIDTH-1] init_v = INIT; - // tri_rlmlatch_p - generate wire sreset; wire int_din; @@ -71,11 +70,11 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl (* analysis_not_referenced="true" *) wire unused; - assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; + assign sreset = (NEEDS_SRESET == 1) ? rst : 0; assign int_din = IBUF ? ~din : din; - always @(posedge nclk[0]) begin: l + always @(posedge clk) begin: l if (sreset) // reset value int_dout <= init_v[0]; else if ((act | force_t) & thold_b) // activate or force, and not clk off @@ -84,9 +83,9 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl assign dout = IBUF ? ~int_dout : int_dout; - assign scout = 1'b0; + assign scout = 0; - assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); + assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd; endgenerate endmodule diff --git a/dev/verilog/trilib/tri_rlmreg_p.v b/dev/verilog/trilib/tri_rlmreg_p.v index def1426..bd83078 100755 --- a/dev/verilog/trilib/tri_rlmreg_p.v +++ b/dev/verilog/trilib/tri_rlmreg_p.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -35,7 +35,7 @@ `include "tri_a2o.vh" -module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); +module tri_rlmreg_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); parameter WIDTH = 4; parameter OFFSET = 0; //starting bit parameter INIT = 0; // will be converted to the least signficant @@ -50,7 +50,8 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; // 1: functional, 0: no clock input force_t; // 1: force LCB active input thold_b; // 1: functional, 0: no clock @@ -76,11 +77,11 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr (* analysis_not_referenced="true" *) wire [0:WIDTH] unused; - assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; + assign sreset = (NEEDS_SRESET == 1) ? rst : 0; assign int_din = sreset ? init_v : (IBUF == 1'b1) ? ~din : din; //wtf why is sreset needed here??? sim fails w/o it. - always @(posedge nclk[0]) begin: l + always @(posedge clk) begin: l if (sreset) // reset value int_dout <= init_v; else if ((act | force_t) & thold_b) // activate or force, and not clk off @@ -91,7 +92,7 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr assign scout = {WIDTH{1'b0}}; - assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); + assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd; assign unused[1:WIDTH] = scin; endgenerate diff --git a/dev/verilog/trilib/tri_rot16_ru.v b/dev/verilog/trilib/tri_rot16_ru.v index 3c316e6..3928012 100755 --- a/dev/verilog/trilib/tri_rot16_ru.v +++ b/dev/verilog/trilib/tri_rot16_ru.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -52,7 +52,8 @@ module tri_rot16_ru( stq8_rmw_data, data_latched, data_rot, - nclk, + clk, + rst, vdd, gnd, delay_lclkr_dc, @@ -81,7 +82,8 @@ output [0:15] data_latched; // latched data, not rotated output [0:15] data_rot; // rotated data out (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; inout vdd; inout gnd; @@ -453,7 +455,8 @@ tri_lcbnd my_lcb( .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), .force_t(func_sl_force), - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(act), diff --git a/dev/verilog/trilib/tri_rot16s_ru.v b/dev/verilog/trilib/tri_rot16s_ru.v index bb9e90c..db1f3f5 100755 --- a/dev/verilog/trilib/tri_rot16s_ru.v +++ b/dev/verilog/trilib/tri_rot16s_ru.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -57,7 +57,8 @@ module tri_rot16s_ru( data_latched, data_rot, algebraic_bit, - nclk, + clk, + rst, vdd, gnd, delay_lclkr_dc, @@ -91,10 +92,10 @@ output [0:15] data_rot; // rotated data out output [0:5] algebraic_bit; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; inout vdd; - inout gnd; input delay_lclkr_dc; input mpw1_dc_b; @@ -613,7 +614,8 @@ tri_lcbnd my_lcb( .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), .force_t(func_sl_force), - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(act), diff --git a/dev/verilog/trilib/tri_ser_rlmreg_p.v b/dev/verilog/trilib/tri_ser_rlmreg_p.v index df16bc7..46546f4 100755 --- a/dev/verilog/trilib/tri_ser_rlmreg_p.v +++ b/dev/verilog/trilib/tri_ser_rlmreg_p.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,10 +35,11 @@ `include "tri_a2o.vh" -module tri_ser_rlmreg_p( +module tri_ser_rlmreg_p ( vd, gd, - nclk, + clk, + rst, act, force_t, thold_b, @@ -62,7 +63,8 @@ module tri_ser_rlmreg_p( inout vd; inout gd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input act; input force_t; input thold_b; @@ -89,7 +91,8 @@ module tri_ser_rlmreg_p( assign dout = dout_buf; tri_aoi22_nlats_wlcb #(.WIDTH(WIDTH), .OFFSET(OFFSET), .INIT(INIT), .IBUF(IBUF), .DUALSCAN(DUALSCAN), .NEEDS_SRESET(NEEDS_SRESET)) tri_ser_rlmreg_p( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vd), .gd(gd), .act(act), diff --git a/dev/verilog/trilib/tri_serial_scom2.v b/dev/verilog/trilib/tri_serial_scom2.v index a34e660..aabcdc5 100755 --- a/dev/verilog/trilib/tri_serial_scom2.v +++ b/dev/verilog/trilib/tri_serial_scom2.v @@ -37,8 +37,9 @@ `include "tri_a2o.vh" -module tri_serial_scom2( - nclk, +module tri_serial_scom2 ( + clk, + rst, vdd, gnd, scom_func_thold, @@ -94,17 +95,18 @@ module tri_serial_scom2( parameter RINGID_NOBITS = 3; // clock, scan and misc interfaces - input [0:`NCLK_WIDTH-1] nclk; inout vdd; - inout gnd; - input scom_func_thold; + inout gnd; + input clk; + input rst; + input scom_func_thold; input sg; input act_dis_dc; input clkoff_dc_b; input mpw1_dc_b; input mpw2_dc_b; input d_mode_dc; - input delay_lclkr_dc; + input delay_lclkr_dc; //lcb_align_0 : in std_ulogic; @@ -336,14 +338,15 @@ module tri_serial_scom2( .thold_b(func_thold_b) ); - tri_lcbnd lcb_func( + tri_lcbnd lcb_func( .vd(vdd), .gd(gnd), .act(local_act_int), .delay_lclkr(delay_lclkr_dc), .mpw1_b(mpw1_dc_b), .mpw2_b(mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_force), .sg(sg), .thold_b(func_thold_b), diff --git a/dev/verilog/trilib/tri_st_mult.v b/dev/verilog/trilib/tri_st_mult.v index 0bd1dbb..d6f50a7 100755 --- a/dev/verilog/trilib/tri_st_mult.v +++ b/dev/verilog/trilib/tri_st_mult.v @@ -35,7 +35,8 @@ `include "tri_a2o.vh" module tri_st_mult( - nclk, + clk, + rst, vdd, gnd, d_mode_dc, @@ -72,10 +73,10 @@ module tri_st_mult( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk; inout vdd; inout gnd; + input clk; + input rst; //------------------------------------------------------------------- // Pervasive @@ -499,7 +500,8 @@ module tri_st_mult( //------------------------------------------------------------------- tri_st_mult_core mcore( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .delay_lclkr_dc(delay_lclkr_dc), @@ -746,7 +748,8 @@ module tri_st_mult( //------------------------------------------------------------------- tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -764,7 +767,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mul_val_q), @@ -782,7 +786,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -800,7 +805,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -818,7 +824,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_is_ord_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -836,7 +843,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_is_ord_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mul_val_q), @@ -854,7 +862,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_is_ord_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -872,7 +881,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_is_ord_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -890,7 +900,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_src_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mul_val_q), @@ -908,7 +919,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex4_xer_src_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -926,7 +938,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex5_xer_src_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -944,7 +957,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex6_xer_src_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_act), @@ -962,7 +976,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -980,7 +995,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex3_mulstage_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -998,7 +1014,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_mulstage_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1016,7 +1033,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_mulstage_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1034,7 +1052,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_mulstage_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1052,7 +1071,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_retsel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -1070,7 +1090,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_retsel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mul_val_q), @@ -1088,7 +1109,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_retsel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1106,7 +1128,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_retsel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1124,7 +1147,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) exx_mul_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1142,7 +1166,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1160,7 +1185,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1178,7 +1204,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -1196,7 +1223,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1214,7 +1242,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1232,7 +1261,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_is_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1250,7 +1280,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_is_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1268,7 +1299,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -1286,7 +1318,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1304,7 +1337,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1322,7 +1356,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1340,7 +1375,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1358,7 +1394,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_size_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -1376,7 +1413,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_mul_val), @@ -1394,7 +1432,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bs_lo_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1412,7 +1451,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bd_lo_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1430,7 +1470,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1448,7 +1489,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1466,7 +1508,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1484,7 +1527,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1502,7 +1546,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1520,7 +1565,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1538,7 +1584,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex6_res_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_act), @@ -1556,7 +1603,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) carry_32_dly1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1574,7 +1622,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1592,7 +1641,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1610,7 +1660,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1628,7 +1679,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rslt_lo_act), @@ -1646,7 +1698,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_dly_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rslt_lo_act_q), @@ -1664,7 +1717,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mulsrc0_act), @@ -1682,7 +1736,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mulsrc1_act), @@ -1700,7 +1755,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_hw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1718,7 +1774,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ld_li_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1736,7 +1793,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ldo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1754,7 +1812,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_lw_hd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1772,7 +1831,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reshi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1790,7 +1850,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1808,7 +1869,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1826,7 +1888,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1844,7 +1907,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1862,7 +1926,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1880,7 +1945,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_hi_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1898,7 +1964,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo1_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1916,7 +1983,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo2_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1934,7 +2002,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo3_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1952,7 +2021,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mullw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1970,7 +2040,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mulldo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -1988,7 +2059,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_undef_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_mul_done_q), @@ -2006,7 +2078,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -2024,7 +2097,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_mul_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -2042,7 +2116,8 @@ module tri_st_mult( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_mul_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mul_val_q), @@ -2059,7 +2134,8 @@ module tri_st_mult( .dout(ex3_mul_tid_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_mul_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -2072,7 +2148,8 @@ module tri_st_mult( .dout(ex4_mul_tid_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_mul_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -2086,7 +2163,8 @@ module tri_st_mult( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rslt_lo_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), diff --git a/dev/verilog/trilib/tri_st_mult_core.v b/dev/verilog/trilib/tri_st_mult_core.v index 08e467c..8cf8998 100755 --- a/dev/verilog/trilib/tri_st_mult_core.v +++ b/dev/verilog/trilib/tri_st_mult_core.v @@ -40,7 +40,8 @@ `include "tri_a2o.vh" module tri_st_mult_core( - nclk, + clk, + rst, vdd, gnd, delay_lclkr_dc, @@ -63,9 +64,10 @@ module tri_st_mult_core( ex5_pp5_0c_out ); // Pervasive --------------------------------------- - input [0:`NCLK_WIDTH-1] nclk; inout vdd; inout gnd; + input clk; + input rst; input delay_lclkr_dc; input mpw1_dc_b; input mpw2_dc_b; @@ -7231,7 +7233,8 @@ module tri_st_mult_core( .mpw1_b(mpw1_dc_b), //in -- 0 , .mpw2_b(mpw2_dc_b), //in -- 0 , .force_t(func_sl_force), //in -- 0 , - .nclk(nclk), //in + .clk(clk), + .rst(rst), .vd(vdd), //inout .gd(gnd), //inout .act(ex3_act), //in @@ -7248,7 +7251,8 @@ module tri_st_mult_core( .mpw1_b(mpw1_dc_b), //in -- 0 , .mpw2_b(mpw2_dc_b), //in -- 0 , .force_t(func_sl_force), //in -- 0 , - .nclk(nclk), //in + .clk(clk), + .rst(rst), .vd(vdd), //inout .gd(gnd), //inout .act(ex4_act), //in diff --git a/dev/verilog/trilib/tri_st_popcnt.v b/dev/verilog/trilib/tri_st_popcnt.v index a6f3cb3..356dbfe 100755 --- a/dev/verilog/trilib/tri_st_popcnt.v +++ b/dev/verilog/trilib/tri_st_popcnt.v @@ -36,7 +36,8 @@ `include "tri_a2o.vh" module tri_st_popcnt( - nclk, + clk, + rst, vdd, gnd, delay_lclkr_dc, @@ -56,7 +57,8 @@ module tri_st_popcnt( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; inout vdd; inout gnd; @@ -193,7 +195,8 @@ module tri_st_popcnt( //------------------------------------------------------------------- tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -211,7 +214,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -229,7 +233,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_popcnt_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -247,7 +252,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -265,7 +271,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -283,7 +290,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -301,7 +309,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -319,7 +328,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -337,7 +347,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -355,7 +366,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -373,7 +385,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -391,7 +404,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -409,7 +423,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -427,7 +442,8 @@ module tri_st_popcnt( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_popcnt_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), diff --git a/dev/verilog/trilib/tri_st_rot.v b/dev/verilog/trilib/tri_st_rot.v index 3bbd2eb..c90e001 100755 --- a/dev/verilog/trilib/tri_st_rot.v +++ b/dev/verilog/trilib/tri_st_rot.v @@ -35,7 +35,8 @@ `include "tri_a2o.vh" module tri_st_rot( - nclk, + clk, + rst, vdd, gnd, d_mode_dc, @@ -59,7 +60,8 @@ module tri_st_rot( ex3_xer_ca, ex3_cr_eq ); - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; inout vdd; inout gnd; input d_mode_dc; @@ -430,7 +432,8 @@ module tri_st_rot( //------------------------------------------------------------------- tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -448,7 +451,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_mb_ins_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -466,7 +470,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_me_ins_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -484,7 +489,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_amt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -502,7 +508,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_right_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -520,7 +527,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_word_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -538,7 +546,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_zm_ins_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -556,7 +565,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -574,7 +584,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_dw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -592,7 +603,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -610,7 +622,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -628,7 +641,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -646,7 +660,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -664,7 +679,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -682,7 +698,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -700,7 +717,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -718,7 +736,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -736,7 +755,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -754,7 +774,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -772,7 +793,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_hi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -790,7 +812,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_lo_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -808,7 +831,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -826,7 +850,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -844,7 +869,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mb_gt_me_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -862,7 +888,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cmp_byte_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -880,7 +907,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_byte_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -898,7 +926,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_half_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -916,7 +945,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -934,7 +964,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -952,7 +983,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_dw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -970,7 +1002,8 @@ module tri_st_rot( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_log_fcn_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -988,7 +1021,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_rot_log_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1006,7 +1040,8 @@ module tri_st_rot( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sh_word_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -1030,7 +1065,8 @@ module tri_st_rot( .vd(vdd), .gd(gnd), .act(ex2_act_unqiue), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_sl_force), .thold_b(func_sl_thold_0_b), .delay_lclkr(delay_lclkr_dc), @@ -1083,7 +1119,8 @@ module tri_st_rot( //------------------------------------------------------------------- tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sra_se_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -1102,7 +1139,8 @@ module tri_st_rot( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dummy_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b0), diff --git a/dev/verilog/trilib_clk1x/tri_128x16_1r1w_1.v b/dev/verilog/trilib_clk1x/tri_128x16_1r1w_1.v deleted file mode 100755 index a789a67..0000000 --- a/dev/verilog/trilib_clk1x/tri_128x16_1r1w_1.v +++ /dev/null @@ -1,281 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//***************************************************************************** -// Description: Tri Array Wrapper -// -//***************************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_128x16_1r1w_1( - vdd, - vcs, - gnd, - nclk, - rd_act, - wr_act, - lcb_d_mode_dc, - lcb_clkoff_dc_b, - lcb_mpw1_dc_b, - lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, - ccflush_dc, - scan_dis_dc_b, - scan_diag_dc, - func_scan_in, - func_scan_out, - lcb_sg_0, - lcb_sl_thold_0_b, - lcb_time_sl_thold_0, - lcb_abst_sl_thold_0, - lcb_ary_nsl_thold_0, - lcb_repr_sl_thold_0, - time_scan_in, - time_scan_out, - abst_scan_in, - abst_scan_out, - repr_scan_in, - repr_scan_out, - abist_di, - abist_bw_odd, - abist_bw_even, - abist_wr_adr, - wr_abst_act, - abist_rd0_adr, - rd0_abst_act, - tc_lbist_ary_wrt_thru_dc, - abist_ena_1, - abist_g8t_rd0_comp_ena, - abist_raw_dc_b, - obs0_abist_cmp, - lcb_bolt_sl_thold_0, - pc_bo_enable_2, - pc_bo_reset, - pc_bo_unload, - pc_bo_repair, - pc_bo_shdata, - pc_bo_select, - bo_pc_failout, - bo_pc_diagloop, - tri_lcb_mpw1_dc_b, - tri_lcb_mpw2_dc_b, - tri_lcb_delay_lclkr_dc, - tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, - bw, - wr_adr, - rd_adr, - di, - dout -); - parameter addressable_ports = 128; // number of addressable register in this array - parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) - parameter port_bitwidth = 16; // bitwidth of ports - parameter ways = 1; // number of ways - - // POWER PINS - inout vdd; - inout vcs; - inout gnd; - - input [0:`NCLK_WIDTH-1] nclk; - - input rd_act; - input wr_act; - - // DC TEST PINS - input lcb_d_mode_dc; - input lcb_clkoff_dc_b; - input [0:4] lcb_mpw1_dc_b; - input lcb_mpw2_dc_b; - input [0:4] lcb_delay_lclkr_dc; - - input ccflush_dc; - input scan_dis_dc_b; - input scan_diag_dc; - input func_scan_in; - output func_scan_out; - - input lcb_sg_0; - input lcb_sl_thold_0_b; - input lcb_time_sl_thold_0; - input lcb_abst_sl_thold_0; - input lcb_ary_nsl_thold_0; - input lcb_repr_sl_thold_0; - input time_scan_in; - output time_scan_out; - input abst_scan_in; - output abst_scan_out; - input repr_scan_in; - output repr_scan_out; - - input [0:3] abist_di; - input abist_bw_odd; - input abist_bw_even; - input [0:6] abist_wr_adr; - input wr_abst_act; - input [0:6] abist_rd0_adr; - input rd0_abst_act; - input tc_lbist_ary_wrt_thru_dc; - input abist_ena_1; - input abist_g8t_rd0_comp_ena; - input abist_raw_dc_b; - input [0:3] obs0_abist_cmp; - - // BOLT-ON - input lcb_bolt_sl_thold_0; - input pc_bo_enable_2; // general bolt-on enable - input pc_bo_reset; // reset - input pc_bo_unload; // unload sticky bits - input pc_bo_repair; // execute sticky bit decode - input pc_bo_shdata; // shift data for timing write and diag loop - input pc_bo_select; // select for mask and hier writes - output bo_pc_failout; // fail/no-fix reg - output bo_pc_diagloop; - input tri_lcb_mpw1_dc_b; - input tri_lcb_mpw2_dc_b; - input tri_lcb_delay_lclkr_dc; - input tri_lcb_clkoff_dc_b; - input tri_lcb_act_dis_dc; - - input [0:15] bw; - input [0:6] wr_adr; - input [0:6] rd_adr; - input [0:15] di; - - output [0:15] dout; - - // tri_128x16_1r1w_1 - - // Configuration Statement for NCsim - //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36; - - wire clk; - wire [0:8] b0addra; - wire [0:8] b0addrb; - wire wea; - wire web; - wire wren_a; - wire [0:15] w_data_in_0; - wire [0:15] r_data_out_0_bram; - - // Latches - reg reset_q; - reg [0:15] r_data_out_1_q; - - - (* analysis_not_referenced="true" *) - wire unused; - - // sim array - reg [0:15] mem[0:127]; - - integer i; - initial begin - for (i = 0; i < 128; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 128; j=j+1) begin: loc - wire [0:15] dat; - assign dat = mem[j][0:15]; - end - endgenerate - - assign clk = nclk[0]; - - always @(posedge clk) - begin: rlatch - reset_q <= nclk[1]; - end - - assign b0addra[2:8] = wr_adr; - assign b0addrb[2:8] = rd_adr; - - // Unused Address Bits - assign b0addra[0:1] = 2'b00; - assign b0addrb[0:1] = 2'b00; - - // port a is a read-modify-write port - assign wren_a = (bw != 0) & wr_act; - assign wea = wren_a; - assign web = 1'b0; - assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0]; - assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1]; - assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2]; - assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3]; - assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4]; - assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5]; - assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6]; - assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7]; - assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8]; - assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9]; - assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10]; - assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11]; - assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12]; - assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13]; - assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14]; - assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15]; - - always @(posedge clk) begin - - r_data_out_1_q <= mem[b0addrb]; - if (wea) begin - mem[b0addra] <= w_data_in_0; - end - - end - - assign r_data_out_0_bram = mem[b0addra]; - assign dout = r_data_out_1_q[0:15]; - - assign func_scan_out = func_scan_in; - assign time_scan_out = time_scan_in; - assign abst_scan_out = abst_scan_in; - assign repr_scan_out = repr_scan_in; - - assign bo_pc_failout = 1'b0; - assign bo_pc_diagloop = 1'b0; - - assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, - lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, - abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, - tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, - lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, - pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, rd_act}; -endmodule diff --git a/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v b/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v deleted file mode 100755 index 4bc0f5e..0000000 --- a/dev/verilog/trilib_clk1x/tri_144x78_2r4w.v +++ /dev/null @@ -1,157 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//***************************************************************************** -// Description: Tri-Lam Array Wrapper -// -//***************************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_144x78_2r4w( - // Inputs - // Power - inout vdd, - inout gnd, - // Clock & Scan - input [0:`NCLK_WIDTH-1] nclk, - - //------------------------------------------------------------------- - // Pervasive - //------------------------------------------------------------------- - input delay_lclkr_dc, - input mpw1_dc_b, - input mpw2_dc_b, - input func_sl_force, - input func_sl_thold_0_b, - input func_slp_sl_force, - input func_slp_sl_thold_0_b, - input sg_0, - input scan_in, - output scan_out, - - //------------------------------------------------------------------- - // Read Port - //------------------------------------------------------------------- - input r_late_en_1, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1, - output [64-`GPR_WIDTH:77] r_data_out_1, - input r_late_en_2, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2, - output [64-`GPR_WIDTH:77] r_data_out_2, - - //------------------------------------------------------------------- - // Write Port - //------------------------------------------------------------------- - input w_late_en_1, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1, - input [64-`GPR_WIDTH:77] w_data_in_1, - input w_late_en_2, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2, - input [64-`GPR_WIDTH:77] w_data_in_2, - input w_late_en_3, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3, - input [64-`GPR_WIDTH:77] w_data_in_3, - input w_late_en_4, - input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4, - input [64-`GPR_WIDTH:77] w_data_in_4 -); - - wire unused; - - // sim array - reg [64-`GPR_WIDTH:77] mem[0:143]; - - reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d; - reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q; - wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d; - - reg [64-`GPR_WIDTH:77] r1d_q; - wire [64-`GPR_WIDTH:77] r1d_d; - reg [64-`GPR_WIDTH:77] r2d_q; - wire [64-`GPR_WIDTH:77] r2d_d; - - integer i; - initial begin - for (i = 0; i < 144; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 144; j=j+1) begin: loc - wire [64-`GPR_WIDTH:63] dat; - wire [0:7] par; - // 4b0 - assign dat = mem[j][64-`GPR_WIDTH:63]; - assign par = mem[j][64:63 + `GPR_WIDTH/8]; - end - endgenerate - - assign r1a_d = r_addr_in_1; - assign r2a_d = r_addr_in_2; - - always @(posedge nclk[0]) begin - - r1a_q <= r1a_d; - r2a_q <= r2a_d; - - r1d_q <= r1d_d; - r2d_q <= r2d_d; - - if (w_late_en_1) begin - mem[w_addr_in_1] <= w_data_in_1; - end - if (w_late_en_2) begin - mem[w_addr_in_2] <= w_data_in_2; - end - if (w_late_en_3) begin - mem[w_addr_in_3] <= w_data_in_3; - end - if (w_late_en_4) begin - mem[w_addr_in_4] <= w_data_in_4; - end - - end - - // r_late_en_x are unused in original also - assign r1d_d = mem[r1a_q]; - assign r2d_d = mem[r2a_q]; - - assign r_data_out_1 = r1d_q; - assign r_data_out_2 = r2d_q; - - assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b}; - -endmodule diff --git a/dev/verilog/trilib_clk1x/tri_512x16_1r1w_1.v b/dev/verilog/trilib_clk1x/tri_512x16_1r1w_1.v deleted file mode 100755 index e79b054..0000000 --- a/dev/verilog/trilib_clk1x/tri_512x16_1r1w_1.v +++ /dev/null @@ -1,273 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//***************************************************************************** -// Description: Tri Array Wrapper -// -//***************************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_512x16_1r1w_1( - vdd, - vcs, - gnd, - nclk, - rd_act, - wr_act, - lcb_d_mode_dc, - lcb_clkoff_dc_b, - lcb_mpw1_dc_b, - lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, - ccflush_dc, - scan_dis_dc_b, - scan_diag_dc, - func_scan_in, - func_scan_out, - lcb_sg_0, - lcb_sl_thold_0_b, - lcb_time_sl_thold_0, - lcb_abst_sl_thold_0, - lcb_ary_nsl_thold_0, - lcb_repr_sl_thold_0, - time_scan_in, - time_scan_out, - abst_scan_in, - abst_scan_out, - repr_scan_in, - repr_scan_out, - abist_di, - abist_bw_odd, - abist_bw_even, - abist_wr_adr, - wr_abst_act, - abist_rd0_adr, - rd0_abst_act, - tc_lbist_ary_wrt_thru_dc, - abist_ena_1, - abist_g8t_rd0_comp_ena, - abist_raw_dc_b, - obs0_abist_cmp, - lcb_bolt_sl_thold_0, - pc_bo_enable_2, - pc_bo_reset, - pc_bo_unload, - pc_bo_repair, - pc_bo_shdata, - pc_bo_select, - bo_pc_failout, - bo_pc_diagloop, - tri_lcb_mpw1_dc_b, - tri_lcb_mpw2_dc_b, - tri_lcb_delay_lclkr_dc, - tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, - bw, - wr_adr, - rd_adr, - di, - dout -); - parameter addressable_ports = 128; // number of addressable register in this array - parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports) - parameter port_bitwidth = 16; // bitwidth of ports - parameter ways = 1; // number of ways - - // POWER PINS - inout vdd; - inout vcs; - inout gnd; - - input [0:`NCLK_WIDTH-1] nclk; - - input rd_act; - input wr_act; - - // DC TEST PINS - input lcb_d_mode_dc; - input lcb_clkoff_dc_b; - input [0:4] lcb_mpw1_dc_b; - input lcb_mpw2_dc_b; - input [0:4] lcb_delay_lclkr_dc; - - input ccflush_dc; - input scan_dis_dc_b; - input scan_diag_dc; - input func_scan_in; - output func_scan_out; - - input lcb_sg_0; - input lcb_sl_thold_0_b; - input lcb_time_sl_thold_0; - input lcb_abst_sl_thold_0; - input lcb_ary_nsl_thold_0; - input lcb_repr_sl_thold_0; - input time_scan_in; - output time_scan_out; - input abst_scan_in; - output abst_scan_out; - input repr_scan_in; - output repr_scan_out; - - input [0:3] abist_di; - input abist_bw_odd; - input abist_bw_even; - input [0:6] abist_wr_adr; - input wr_abst_act; - input [0:6] abist_rd0_adr; - input rd0_abst_act; - input tc_lbist_ary_wrt_thru_dc; - input abist_ena_1; - input abist_g8t_rd0_comp_ena; - input abist_raw_dc_b; - input [0:3] obs0_abist_cmp; - - // BOLT-ON - input lcb_bolt_sl_thold_0; - input pc_bo_enable_2; // general bolt-on enable - input pc_bo_reset; // reset - input pc_bo_unload; // unload sticky bits - input pc_bo_repair; // execute sticky bit decode - input pc_bo_shdata; // shift data for timing write and diag loop - input pc_bo_select; // select for mask and hier writes - output bo_pc_failout; // fail/no-fix reg - output bo_pc_diagloop; - input tri_lcb_mpw1_dc_b; - input tri_lcb_mpw2_dc_b; - input tri_lcb_delay_lclkr_dc; - input tri_lcb_clkoff_dc_b; - input tri_lcb_act_dis_dc; - - input [0:15] bw; - input [0:8] wr_adr; - input [0:8] rd_adr; - input [0:15] di; - - output [0:15] dout; - - wire clk; - wire [0:8] b0addra; - wire [0:8] b0addrb; - wire wea; - wire web; - wire wren_a; - wire [0:15] w_data_in_0; - wire [0:15] r_data_out_0_bram; - - // Latches - reg reset_q; - reg [0:15] r_data_out_1_q; - - - (* analysis_not_referenced="true" *) - wire unused; - - // sim array - reg [0:15] mem[0:511]; - - integer i; - initial begin - for (i = 0; i < 512; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 512; j=j+1) begin: loc - wire [0:15] dat; - assign dat = mem[j][0:15]; - end - endgenerate - - assign clk = nclk[0]; - - always @(posedge clk) - begin: rlatch - reset_q <= nclk[1]; - end - - //wtf do they use diff addresses? - assign b0addra[0:8] = wr_adr; - assign b0addrb[0:8] = rd_adr; - - // port a is a read-modify-write port - assign wren_a = (bw != 0) & wr_act; - assign wea = wren_a; - assign web = 1'b0; - assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0]; - assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1]; - assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2]; - assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3]; - assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4]; - assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5]; - assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6]; - assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7]; - assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8]; - assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9]; - assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10]; - assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11]; - assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12]; - assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13]; - assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14]; - assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15]; - - always @(posedge clk) begin - - r_data_out_1_q <= mem[b0addrb]; - if (wea) begin - mem[b0addra] <= w_data_in_0; - end - - end - - assign r_data_out_0_bram = mem[b0addra]; - assign dout = r_data_out_1_q[0:15]; - - assign func_scan_out = func_scan_in; - assign time_scan_out = time_scan_in; - assign abst_scan_out = abst_scan_in; - assign repr_scan_out = repr_scan_in; - - assign bo_pc_failout = 1'b0; - assign bo_pc_diagloop = 1'b0; - - assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, - lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, - abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, - tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, - lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, - pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, rd_act}; -endmodule diff --git a/dev/verilog/trilib_clk1x/tri_64x72_1r1w.v b/dev/verilog/trilib_clk1x/tri_64x72_1r1w.v deleted file mode 100755 index 3add00e..0000000 --- a/dev/verilog/trilib_clk1x/tri_64x72_1r1w.v +++ /dev/null @@ -1,245 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//***************************************************************************** -// Description: Tri-Lam Array Wrapper -// -//***************************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_64x72_1r1w( - vdd, - vcs, - gnd, - nclk, - sg_0, - abst_sl_thold_0, - ary_nsl_thold_0, - time_sl_thold_0, - repr_sl_thold_0, - rd0_act, - rd0_adr, - do0, - wr_act, - wr_adr, - di, - abst_scan_in, - abst_scan_out, - time_scan_in, - time_scan_out, - repr_scan_in, - repr_scan_out, - scan_dis_dc_b, - scan_diag_dc, - ccflush_dc, - clkoff_dc_b, - d_mode_dc, - mpw1_dc_b, - mpw2_dc_b, - delay_lclkr_dc, - lcb_bolt_sl_thold_0, - pc_bo_enable_2, - pc_bo_reset, - pc_bo_unload, - pc_bo_repair, - pc_bo_shdata, - pc_bo_select, - bo_pc_failout, - bo_pc_diagloop, - tri_lcb_mpw1_dc_b, - tri_lcb_mpw2_dc_b, - tri_lcb_delay_lclkr_dc, - tri_lcb_clkoff_dc_b, - tri_lcb_act_dis_dc, - abist_di, - abist_bw_odd, - abist_bw_even, - abist_wr_adr, - wr_abst_act, - abist_rd0_adr, - rd0_abst_act, - tc_lbist_ary_wrt_thru_dc, - abist_ena_1, - abist_g8t_rd0_comp_ena, - abist_raw_dc_b, - obs0_abist_cmp -); - - // Power - (* analysis_not_referenced="true" *) - inout vdd; - (* analysis_not_referenced="true" *) - inout vcs; - (* analysis_not_referenced="true" *) - inout gnd; - - // Clock Pervasive - input [0:`NCLK_WIDTH-1] nclk; - input sg_0; - input abst_sl_thold_0; - input ary_nsl_thold_0; - input time_sl_thold_0; - input repr_sl_thold_0; - - // Reads - input rd0_act; - input [0:5] rd0_adr; - output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0; - - // Writes - input wr_act; - input [0:5] wr_adr; - input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di; - - // Scan - input abst_scan_in; - output abst_scan_out; - input time_scan_in; - output time_scan_out; - input repr_scan_in; - output repr_scan_out; - - // Misc Pervasive - input scan_dis_dc_b; - input scan_diag_dc; - input ccflush_dc; - input clkoff_dc_b; - input d_mode_dc; - input [0:4] mpw1_dc_b; - input mpw2_dc_b; - input [0:4] delay_lclkr_dc; - - // BOLT-ON - input lcb_bolt_sl_thold_0; - input pc_bo_enable_2; // general bolt-on enable - input pc_bo_reset; // reset - input pc_bo_unload; // unload sticky bits - input pc_bo_repair; // execute sticky bit decode - input pc_bo_shdata; // shift data for timing write and diag loop - input pc_bo_select; // select for mask and hier writes - output bo_pc_failout; // fail/no-fix reg - output bo_pc_diagloop; - input tri_lcb_mpw1_dc_b; - input tri_lcb_mpw2_dc_b; - input tri_lcb_delay_lclkr_dc; - input tri_lcb_clkoff_dc_b; - input tri_lcb_act_dis_dc; - - // ABIST - input [0:3] abist_di; - input abist_bw_odd; - input abist_bw_even; - input [0:5] abist_wr_adr; - input wr_abst_act; - input [0:5] abist_rd0_adr; - input rd0_abst_act; - input tc_lbist_ary_wrt_thru_dc; - input abist_ena_1; - input abist_g8t_rd0_comp_ena; - input abist_raw_dc_b; - input [0:3] obs0_abist_cmp; - - wire sreset; - wire [0:71] tidn; - - (* analysis_not_referenced="true" *) - wire unused; - - // sim array - reg [0:63] mem[0:71]; - - reg r0_e_q; - wire r0_e_d; - reg [0:5] r0_a_q; - wire [0:5] r0_a_d; - reg [0:71] r0_d_q; - wire [0:71] r0_d_d; - - reg w0_e_q; - wire w0_e_d; - reg [0:5] w0_a_q; - wire [0:5] w0_a_d; - reg [0:71] w0_d_q; - wire [0:71] w0_d_d; - - integer i; - initial begin - for (i = 0; i < 64; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 63; j=j+1) begin: loc - wire [0:63] dat; - wire [0:7] par; - assign dat = mem[j][0:63]; - assign par = mem[j][0:7]; - end - endgenerate - - generate - - assign clk = nclk[0]; - assign sreset = nclk[1]; - - always @(posedge clk) begin - - r0_e_q <= rd0_act; - r0_a_q <= rd0_adr; - r0_d_q <= r0_e_q ? mem[r0_a_q] : 0; - - if (w0_e_q) begin - mem[w0_a_q] <= w0_d_q; - end - w0_e_q <= wr_act; - w0_a_q <= wr_adr; - w0_d_q <= di; - - end - - assign do0 = r0_d_q; - - assign abst_scan_out = abst_scan_in; - assign time_scan_out = time_scan_in; - assign repr_scan_out = repr_scan_in; - - assign bo_pc_failout = 1'b0; - assign bo_pc_diagloop = 1'b0; - - assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc}); - - endgenerate - -endmodule diff --git a/dev/verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v b/dev/verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v deleted file mode 100755 index 959f0ec..0000000 --- a/dev/verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v +++ /dev/null @@ -1,2695 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//******************************************************************** -//* TITLE: I-ERAT CAM Tri-Library Model -//* NAME: tri_cam_16x143_1r1w1c -//******************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_cam_16x143_1r1w1c( - gnd, - vdd, - vcs, - nclk, - tc_ccflush_dc, - tc_scan_dis_dc_b, - tc_scan_diag_dc, - tc_lbist_en_dc, - an_ac_atpg_en_dc, - lcb_d_mode_dc, - lcb_clkoff_dc_b, - lcb_act_dis_dc, - lcb_mpw1_dc_b, - lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, - pc_sg_2, - pc_func_slp_sl_thold_2, - pc_func_slp_nsl_thold_2, - pc_regf_slp_sl_thold_2, - pc_time_sl_thold_2, - pc_fce_2, - func_scan_in, - func_scan_out, - regfile_scan_in, - regfile_scan_out, - time_scan_in, - time_scan_out, - rd_val, - rd_val_late, - rw_entry, - wr_array_data, - wr_cam_data, - wr_array_val, - wr_cam_val, - wr_val_early, - comp_request, - comp_addr, - addr_enable, - comp_pgsize, - pgsize_enable, - comp_class, - class_enable, - comp_extclass, - extclass_enable, - comp_state, - state_enable, - comp_thdid, - thdid_enable, - comp_pid, - pid_enable, - comp_invalidate, - flash_invalidate, - array_cmp_data, - rd_array_data, - cam_cmp_data, - cam_hit, - cam_hit_entry, - entry_match, - entry_valid, - rd_cam_data, - bypass_mux_enab_np1, - bypass_attr_np1, - attr_np2, - rpn_np2 -); - parameter CAM_DATA_WIDTH = 84; - parameter ARRAY_DATA_WIDTH = 68; - parameter RPN_WIDTH = 30; - parameter NUM_ENTRY = 16; - parameter NUM_ENTRY_LOG2 = 4; - - // Power Pins - inout gnd; - inout vdd; - inout vcs; - - // Clocks and Scan Cntls - input [0:`NCLK_WIDTH-1] nclk; - input tc_ccflush_dc; - input tc_scan_dis_dc_b; - input tc_scan_diag_dc; - input tc_lbist_en_dc; - input an_ac_atpg_en_dc; - - input lcb_d_mode_dc; - input lcb_clkoff_dc_b; - input lcb_act_dis_dc; - input [0:3] lcb_mpw1_dc_b; - input lcb_mpw2_dc_b; - input [0:3] lcb_delay_lclkr_dc; - - input pc_sg_2; - input pc_func_slp_sl_thold_2; - input pc_func_slp_nsl_thold_2; - input pc_regf_slp_sl_thold_2; - input pc_time_sl_thold_2; - input pc_fce_2; - - input func_scan_in; - output func_scan_out; - input [0:4] regfile_scan_in; // 0:2 -> CAM, 3:4 -> RAM - output [0:4] regfile_scan_out; - input time_scan_in; - output time_scan_out; - - // Read Port - input rd_val; - input rd_val_late; - input [0:NUM_ENTRY_LOG2-1] rw_entry; - - // Write Port - input [0:ARRAY_DATA_WIDTH-1] wr_array_data; - input [0:CAM_DATA_WIDTH-1] wr_cam_data; - input [0:1] wr_array_val; - input [0:1] wr_cam_val; - input wr_val_early; - - // CAM Port - input comp_request; - input [0:51] comp_addr; - input [0:1] addr_enable; - input [0:2] comp_pgsize; - input pgsize_enable; - input [0:1] comp_class; - input [0:2] class_enable; - input [0:1] comp_extclass; - input [0:1] extclass_enable; - input [0:1] comp_state; - input [0:1] state_enable; - input [0:3] comp_thdid; - input [0:1] thdid_enable; - input [0:7] comp_pid; - input pid_enable; - input comp_invalidate; - input flash_invalidate; - - // Outputs - // Data Out - output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; - output [0:ARRAY_DATA_WIDTH-1] rd_array_data; - - // CAM Output - output [0:CAM_DATA_WIDTH-1] cam_cmp_data; - output cam_hit; - output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; - output [0:NUM_ENTRY-1] entry_match; - output [0:NUM_ENTRY-1] entry_valid; - output [0:CAM_DATA_WIDTH-1] rd_cam_data; - - //--- new ports for IO plus ----------------------- - input bypass_mux_enab_np1; - input [0:20] bypass_attr_np1; - output [0:20] attr_np2; - - output [22:51] rpn_np2; - - wire clk; - wire [0:8] bram0_addra; - wire [0:8] bram0_addrb; - wire [0:10] bram1_addra; - wire [0:10] bram1_addrb; - wire [0:9] bram2_addra; - wire [0:9] bram2_addrb; - wire bram0_wea; - wire bram1_wea; - wire bram2_wea; - wire [0:55] array_cmp_data_bram; - wire [66:72] array_cmp_data_bramp; - - // Latches - reg sreset_q; - wire [52-RPN_WIDTH:51] comp_addr_np1_d; - reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input - wire [52-RPN_WIDTH:51] rpn_np2_d; - reg [52-RPN_WIDTH:51] rpn_np2_q; - wire [0:20] attr_np2_d; - reg [0:20] attr_np2_q; - - // CAM entry signals - wire [0:51] entry0_epn_d; - reg [0:51] entry0_epn_q; - wire entry0_xbit_d; - reg entry0_xbit_q; - wire [0:2] entry0_size_d; - reg [0:2] entry0_size_q; - wire entry0_v_d; - reg entry0_v_q; - wire [0:3] entry0_thdid_d; - reg [0:3] entry0_thdid_q; - wire [0:1] entry0_class_d; - reg [0:1] entry0_class_q; - wire [0:1] entry0_extclass_d; - reg [0:1] entry0_extclass_q; - wire entry0_hv_d; - reg entry0_hv_q; - wire entry0_ds_d; - reg entry0_ds_q; - wire [0:7] entry0_pid_d; - reg [0:7] entry0_pid_q; - wire [0:8] entry0_cmpmask_d; - reg [0:8] entry0_cmpmask_q; - wire [0:9] entry0_parity_d; - reg [0:9] entry0_parity_q; - wire [0:1] wr_entry0_sel; - wire entry0_inval; - wire [0:1] entry0_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; - wire [0:51] entry1_epn_d; - reg [0:51] entry1_epn_q; - wire entry1_xbit_d; - reg entry1_xbit_q; - wire [0:2] entry1_size_d; - reg [0:2] entry1_size_q; - wire entry1_v_d; - reg entry1_v_q; - wire [0:3] entry1_thdid_d; - reg [0:3] entry1_thdid_q; - wire [0:1] entry1_class_d; - reg [0:1] entry1_class_q; - wire [0:1] entry1_extclass_d; - reg [0:1] entry1_extclass_q; - wire entry1_hv_d; - reg entry1_hv_q; - wire entry1_ds_d; - reg entry1_ds_q; - wire [0:7] entry1_pid_d; - reg [0:7] entry1_pid_q; - wire [0:8] entry1_cmpmask_d; - reg [0:8] entry1_cmpmask_q; - wire [0:9] entry1_parity_d; - reg [0:9] entry1_parity_q; - wire [0:1] wr_entry1_sel; - wire entry1_inval; - wire [0:1] entry1_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; - wire [0:51] entry2_epn_d; - reg [0:51] entry2_epn_q; - wire entry2_xbit_d; - reg entry2_xbit_q; - wire [0:2] entry2_size_d; - reg [0:2] entry2_size_q; - wire entry2_v_d; - reg entry2_v_q; - wire [0:3] entry2_thdid_d; - reg [0:3] entry2_thdid_q; - wire [0:1] entry2_class_d; - reg [0:1] entry2_class_q; - wire [0:1] entry2_extclass_d; - reg [0:1] entry2_extclass_q; - wire entry2_hv_d; - reg entry2_hv_q; - wire entry2_ds_d; - reg entry2_ds_q; - wire [0:7] entry2_pid_d; - reg [0:7] entry2_pid_q; - wire [0:8] entry2_cmpmask_d; - reg [0:8] entry2_cmpmask_q; - wire [0:9] entry2_parity_d; - reg [0:9] entry2_parity_q; - wire [0:1] wr_entry2_sel; - wire entry2_inval; - wire [0:1] entry2_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; - wire [0:51] entry3_epn_d; - reg [0:51] entry3_epn_q; - wire entry3_xbit_d; - reg entry3_xbit_q; - wire [0:2] entry3_size_d; - reg [0:2] entry3_size_q; - wire entry3_v_d; - reg entry3_v_q; - wire [0:3] entry3_thdid_d; - reg [0:3] entry3_thdid_q; - wire [0:1] entry3_class_d; - reg [0:1] entry3_class_q; - wire [0:1] entry3_extclass_d; - reg [0:1] entry3_extclass_q; - wire entry3_hv_d; - reg entry3_hv_q; - wire entry3_ds_d; - reg entry3_ds_q; - wire [0:7] entry3_pid_d; - reg [0:7] entry3_pid_q; - wire [0:8] entry3_cmpmask_d; - reg [0:8] entry3_cmpmask_q; - wire [0:9] entry3_parity_d; - reg [0:9] entry3_parity_q; - wire [0:1] wr_entry3_sel; - wire entry3_inval; - wire [0:1] entry3_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; - wire [0:51] entry4_epn_d; - reg [0:51] entry4_epn_q; - wire entry4_xbit_d; - reg entry4_xbit_q; - wire [0:2] entry4_size_d; - reg [0:2] entry4_size_q; - wire entry4_v_d; - reg entry4_v_q; - wire [0:3] entry4_thdid_d; - reg [0:3] entry4_thdid_q; - wire [0:1] entry4_class_d; - reg [0:1] entry4_class_q; - wire [0:1] entry4_extclass_d; - reg [0:1] entry4_extclass_q; - wire entry4_hv_d; - reg entry4_hv_q; - wire entry4_ds_d; - reg entry4_ds_q; - wire [0:7] entry4_pid_d; - reg [0:7] entry4_pid_q; - wire [0:8] entry4_cmpmask_d; - reg [0:8] entry4_cmpmask_q; - wire [0:9] entry4_parity_d; - reg [0:9] entry4_parity_q; - wire [0:1] wr_entry4_sel; - wire entry4_inval; - wire [0:1] entry4_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; - wire [0:51] entry5_epn_d; - reg [0:51] entry5_epn_q; - wire entry5_xbit_d; - reg entry5_xbit_q; - wire [0:2] entry5_size_d; - reg [0:2] entry5_size_q; - wire entry5_v_d; - reg entry5_v_q; - wire [0:3] entry5_thdid_d; - reg [0:3] entry5_thdid_q; - wire [0:1] entry5_class_d; - reg [0:1] entry5_class_q; - wire [0:1] entry5_extclass_d; - reg [0:1] entry5_extclass_q; - wire entry5_hv_d; - reg entry5_hv_q; - wire entry5_ds_d; - reg entry5_ds_q; - wire [0:7] entry5_pid_d; - reg [0:7] entry5_pid_q; - wire [0:8] entry5_cmpmask_d; - reg [0:8] entry5_cmpmask_q; - wire [0:9] entry5_parity_d; - reg [0:9] entry5_parity_q; - wire [0:1] wr_entry5_sel; - wire entry5_inval; - wire [0:1] entry5_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; - wire [0:51] entry6_epn_d; - reg [0:51] entry6_epn_q; - wire entry6_xbit_d; - reg entry6_xbit_q; - wire [0:2] entry6_size_d; - reg [0:2] entry6_size_q; - wire entry6_v_d; - reg entry6_v_q; - wire [0:3] entry6_thdid_d; - reg [0:3] entry6_thdid_q; - wire [0:1] entry6_class_d; - reg [0:1] entry6_class_q; - wire [0:1] entry6_extclass_d; - reg [0:1] entry6_extclass_q; - wire entry6_hv_d; - reg entry6_hv_q; - wire entry6_ds_d; - reg entry6_ds_q; - wire [0:7] entry6_pid_d; - reg [0:7] entry6_pid_q; - wire [0:8] entry6_cmpmask_d; - reg [0:8] entry6_cmpmask_q; - wire [0:9] entry6_parity_d; - reg [0:9] entry6_parity_q; - wire [0:1] wr_entry6_sel; - wire entry6_inval; - wire [0:1] entry6_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; - wire [0:51] entry7_epn_d; - reg [0:51] entry7_epn_q; - wire entry7_xbit_d; - reg entry7_xbit_q; - wire [0:2] entry7_size_d; - reg [0:2] entry7_size_q; - wire entry7_v_d; - reg entry7_v_q; - wire [0:3] entry7_thdid_d; - reg [0:3] entry7_thdid_q; - wire [0:1] entry7_class_d; - reg [0:1] entry7_class_q; - wire [0:1] entry7_extclass_d; - reg [0:1] entry7_extclass_q; - wire entry7_hv_d; - reg entry7_hv_q; - wire entry7_ds_d; - reg entry7_ds_q; - wire [0:7] entry7_pid_d; - reg [0:7] entry7_pid_q; - wire [0:8] entry7_cmpmask_d; - reg [0:8] entry7_cmpmask_q; - wire [0:9] entry7_parity_d; - reg [0:9] entry7_parity_q; - wire [0:1] wr_entry7_sel; - wire entry7_inval; - wire [0:1] entry7_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; - wire [0:51] entry8_epn_d; - reg [0:51] entry8_epn_q; - wire entry8_xbit_d; - reg entry8_xbit_q; - wire [0:2] entry8_size_d; - reg [0:2] entry8_size_q; - wire entry8_v_d; - reg entry8_v_q; - wire [0:3] entry8_thdid_d; - reg [0:3] entry8_thdid_q; - wire [0:1] entry8_class_d; - reg [0:1] entry8_class_q; - wire [0:1] entry8_extclass_d; - reg [0:1] entry8_extclass_q; - wire entry8_hv_d; - reg entry8_hv_q; - wire entry8_ds_d; - reg entry8_ds_q; - wire [0:7] entry8_pid_d; - reg [0:7] entry8_pid_q; - wire [0:8] entry8_cmpmask_d; - reg [0:8] entry8_cmpmask_q; - wire [0:9] entry8_parity_d; - reg [0:9] entry8_parity_q; - wire [0:1] wr_entry8_sel; - wire entry8_inval; - wire [0:1] entry8_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; - wire [0:51] entry9_epn_d; - reg [0:51] entry9_epn_q; - wire entry9_xbit_d; - reg entry9_xbit_q; - wire [0:2] entry9_size_d; - reg [0:2] entry9_size_q; - wire entry9_v_d; - reg entry9_v_q; - wire [0:3] entry9_thdid_d; - reg [0:3] entry9_thdid_q; - wire [0:1] entry9_class_d; - reg [0:1] entry9_class_q; - wire [0:1] entry9_extclass_d; - reg [0:1] entry9_extclass_q; - wire entry9_hv_d; - reg entry9_hv_q; - wire entry9_ds_d; - reg entry9_ds_q; - wire [0:7] entry9_pid_d; - reg [0:7] entry9_pid_q; - wire [0:8] entry9_cmpmask_d; - reg [0:8] entry9_cmpmask_q; - wire [0:9] entry9_parity_d; - reg [0:9] entry9_parity_q; - wire [0:1] wr_entry9_sel; - wire entry9_inval; - wire [0:1] entry9_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; - wire [0:51] entry10_epn_d; - reg [0:51] entry10_epn_q; - wire entry10_xbit_d; - reg entry10_xbit_q; - wire [0:2] entry10_size_d; - reg [0:2] entry10_size_q; - wire entry10_v_d; - reg entry10_v_q; - wire [0:3] entry10_thdid_d; - reg [0:3] entry10_thdid_q; - wire [0:1] entry10_class_d; - reg [0:1] entry10_class_q; - wire [0:1] entry10_extclass_d; - reg [0:1] entry10_extclass_q; - wire entry10_hv_d; - reg entry10_hv_q; - wire entry10_ds_d; - reg entry10_ds_q; - wire [0:7] entry10_pid_d; - reg [0:7] entry10_pid_q; - wire [0:8] entry10_cmpmask_d; - reg [0:8] entry10_cmpmask_q; - wire [0:9] entry10_parity_d; - reg [0:9] entry10_parity_q; - wire [0:1] wr_entry10_sel; - wire entry10_inval; - wire [0:1] entry10_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; - wire [0:51] entry11_epn_d; - reg [0:51] entry11_epn_q; - wire entry11_xbit_d; - reg entry11_xbit_q; - wire [0:2] entry11_size_d; - reg [0:2] entry11_size_q; - wire entry11_v_d; - reg entry11_v_q; - wire [0:3] entry11_thdid_d; - reg [0:3] entry11_thdid_q; - wire [0:1] entry11_class_d; - reg [0:1] entry11_class_q; - wire [0:1] entry11_extclass_d; - reg [0:1] entry11_extclass_q; - wire entry11_hv_d; - reg entry11_hv_q; - wire entry11_ds_d; - reg entry11_ds_q; - wire [0:7] entry11_pid_d; - reg [0:7] entry11_pid_q; - wire [0:8] entry11_cmpmask_d; - reg [0:8] entry11_cmpmask_q; - wire [0:9] entry11_parity_d; - reg [0:9] entry11_parity_q; - wire [0:1] wr_entry11_sel; - wire entry11_inval; - wire [0:1] entry11_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; - wire [0:51] entry12_epn_d; - reg [0:51] entry12_epn_q; - wire entry12_xbit_d; - reg entry12_xbit_q; - wire [0:2] entry12_size_d; - reg [0:2] entry12_size_q; - wire entry12_v_d; - reg entry12_v_q; - wire [0:3] entry12_thdid_d; - reg [0:3] entry12_thdid_q; - wire [0:1] entry12_class_d; - reg [0:1] entry12_class_q; - wire [0:1] entry12_extclass_d; - reg [0:1] entry12_extclass_q; - wire entry12_hv_d; - reg entry12_hv_q; - wire entry12_ds_d; - reg entry12_ds_q; - wire [0:7] entry12_pid_d; - reg [0:7] entry12_pid_q; - wire [0:8] entry12_cmpmask_d; - reg [0:8] entry12_cmpmask_q; - wire [0:9] entry12_parity_d; - reg [0:9] entry12_parity_q; - wire [0:1] wr_entry12_sel; - wire entry12_inval; - wire [0:1] entry12_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; - wire [0:51] entry13_epn_d; - reg [0:51] entry13_epn_q; - wire entry13_xbit_d; - reg entry13_xbit_q; - wire [0:2] entry13_size_d; - reg [0:2] entry13_size_q; - wire entry13_v_d; - reg entry13_v_q; - wire [0:3] entry13_thdid_d; - reg [0:3] entry13_thdid_q; - wire [0:1] entry13_class_d; - reg [0:1] entry13_class_q; - wire [0:1] entry13_extclass_d; - reg [0:1] entry13_extclass_q; - wire entry13_hv_d; - reg entry13_hv_q; - wire entry13_ds_d; - reg entry13_ds_q; - wire [0:7] entry13_pid_d; - reg [0:7] entry13_pid_q; - wire [0:8] entry13_cmpmask_d; - reg [0:8] entry13_cmpmask_q; - wire [0:9] entry13_parity_d; - reg [0:9] entry13_parity_q; - wire [0:1] wr_entry13_sel; - wire entry13_inval; - wire [0:1] entry13_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; - wire [0:51] entry14_epn_d; - reg [0:51] entry14_epn_q; - wire entry14_xbit_d; - reg entry14_xbit_q; - wire [0:2] entry14_size_d; - reg [0:2] entry14_size_q; - wire entry14_v_d; - reg entry14_v_q; - wire [0:3] entry14_thdid_d; - reg [0:3] entry14_thdid_q; - wire [0:1] entry14_class_d; - reg [0:1] entry14_class_q; - wire [0:1] entry14_extclass_d; - reg [0:1] entry14_extclass_q; - wire entry14_hv_d; - reg entry14_hv_q; - wire entry14_ds_d; - reg entry14_ds_q; - wire [0:7] entry14_pid_d; - reg [0:7] entry14_pid_q; - wire [0:8] entry14_cmpmask_d; - reg [0:8] entry14_cmpmask_q; - wire [0:9] entry14_parity_d; - reg [0:9] entry14_parity_q; - wire [0:1] wr_entry14_sel; - wire entry14_inval; - wire [0:1] entry14_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; - wire [0:51] entry15_epn_d; - reg [0:51] entry15_epn_q; - wire entry15_xbit_d; - reg entry15_xbit_q; - wire [0:2] entry15_size_d; - reg [0:2] entry15_size_q; - wire entry15_v_d; - reg entry15_v_q; - wire [0:3] entry15_thdid_d; - reg [0:3] entry15_thdid_q; - wire [0:1] entry15_class_d; - reg [0:1] entry15_class_q; - wire [0:1] entry15_extclass_d; - reg [0:1] entry15_extclass_q; - wire entry15_hv_d; - reg entry15_hv_q; - wire entry15_ds_d; - reg entry15_ds_q; - wire [0:7] entry15_pid_d; - reg [0:7] entry15_pid_q; - wire [0:8] entry15_cmpmask_d; - reg [0:8] entry15_cmpmask_q; - wire [0:9] entry15_parity_d; - reg [0:9] entry15_parity_q; - wire [0:1] wr_entry15_sel; - wire entry15_inval; - wire [0:1] entry15_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; - wire [0:4] cam_cmp_data_muxsel; - wire [0:4] rd_cam_data_muxsel; - wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; - wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; - wire [0:72] wr_array_data_bram; - wire [0:72] rd_array_data_d_std; - wire [0:55] array_cmp_data_bram_std; - wire [66:72] array_cmp_data_bramp_std; - - // latch signals - wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; - reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; - wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; - reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; - wire [0:9] cam_cmp_parity_d; - reg [0:9] cam_cmp_parity_q; - wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; - reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; - wire [0:NUM_ENTRY-1] entry_match_d; - reg [0:NUM_ENTRY-1] entry_match_q; - wire [0:NUM_ENTRY-1] match_vec; - wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; - reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; - wire cam_hit_d; - reg cam_hit_q; - wire toggle_d; - reg toggle_q; - wire toggle2x_d; - reg toggle2x_q; - (* analysis_not_referenced="true" *) - wire unused; - - // sim array - reg [0:62] mem[0:15]; - - integer i; - initial begin - for (i = 0; i < 16; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 16; j=j+1) begin: loc - wire [0:62] dat; - assign dat = mem[j][0:62]; //wtf split into fields someday - end - endgenerate - - assign clk = nclk[0]; - - always @(posedge clk) - begin: rlatch - sreset_q <= nclk[1]; - end - - always @(posedge clk) begin: slatch - if (sreset_q == 1'b1) begin - cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; - cam_cmp_parity_q <= 10'b0; - rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; - rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; - entry_match_q <= {NUM_ENTRY{1'b0}}; - cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; - cam_hit_q <= 1'b0; - comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; - rpn_np2_q <= {RPN_WIDTH{1'b0}}; - attr_np2_q <= 21'b0; - entry0_size_q <= 3'b0; - entry0_xbit_q <= 1'b0; - entry0_epn_q <= 52'b0; - entry0_class_q <= 2'b0; - entry0_extclass_q <= 2'b0; - entry0_hv_q <= 1'b0; - entry0_ds_q <= 1'b0; - entry0_thdid_q <= 4'b0; - entry0_pid_q <= 8'b0; - entry0_v_q <= 1'b0; - entry0_parity_q <= 10'b0; - entry0_cmpmask_q <= 9'b0; - entry1_size_q <= 3'b0; - entry1_xbit_q <= 1'b0; - entry1_epn_q <= 52'b0; - entry1_class_q <= 2'b0; - entry1_extclass_q <= 2'b0; - entry1_hv_q <= 1'b0; - entry1_ds_q <= 1'b0; - entry1_thdid_q <= 4'b0; - entry1_pid_q <= 8'b0; - entry1_v_q <= 1'b0; - entry1_parity_q <= 10'b0; - entry1_cmpmask_q <= 9'b0; - entry2_size_q <= 3'b0; - entry2_xbit_q <= 1'b0; - entry2_epn_q <= 52'b0; - entry2_class_q <= 2'b0; - entry2_extclass_q <= 2'b0; - entry2_hv_q <= 1'b0; - entry2_ds_q <= 1'b0; - entry2_thdid_q <= 4'b0; - entry2_pid_q <= 8'b0; - entry2_v_q <= 1'b0; - entry2_parity_q <= 10'b0; - entry2_cmpmask_q <= 9'b0; - entry3_size_q <= 3'b0; - entry3_xbit_q <= 1'b0; - entry3_epn_q <= 52'b0; - entry3_class_q <= 2'b0; - entry3_extclass_q <= 2'b0; - entry3_hv_q <= 1'b0; - entry3_ds_q <= 1'b0; - entry3_thdid_q <= 4'b0; - entry3_pid_q <= 8'b0; - entry3_v_q <= 1'b0; - entry3_parity_q <= 10'b0; - entry3_cmpmask_q <= 9'b0; - entry4_size_q <= 3'b0; - entry4_xbit_q <= 1'b0; - entry4_epn_q <= 52'b0; - entry4_class_q <= 2'b0; - entry4_extclass_q <= 2'b0; - entry4_hv_q <= 1'b0; - entry4_ds_q <= 1'b0; - entry4_thdid_q <= 4'b0; - entry4_pid_q <= 8'b0; - entry4_v_q <= 1'b0; - entry4_parity_q <= 10'b0; - entry4_cmpmask_q <= 9'b0; - entry5_size_q <= 3'b0; - entry5_xbit_q <= 1'b0; - entry5_epn_q <= 52'b0; - entry5_class_q <= 2'b0; - entry5_extclass_q <= 2'b0; - entry5_hv_q <= 1'b0; - entry5_ds_q <= 1'b0; - entry5_thdid_q <= 4'b0; - entry5_pid_q <= 8'b0; - entry5_v_q <= 1'b0; - entry5_parity_q <= 10'b0; - entry5_cmpmask_q <= 9'b0; - entry6_size_q <= 3'b0; - entry6_xbit_q <= 1'b0; - entry6_epn_q <= 52'b0; - entry6_class_q <= 2'b0; - entry6_extclass_q <= 2'b0; - entry6_hv_q <= 1'b0; - entry6_ds_q <= 1'b0; - entry6_thdid_q <= 4'b0; - entry6_pid_q <= 8'b0; - entry6_v_q <= 1'b0; - entry6_parity_q <= 10'b0; - entry6_cmpmask_q <= 9'b0; - entry7_size_q <= 3'b0; - entry7_xbit_q <= 1'b0; - entry7_epn_q <= 52'b0; - entry7_class_q <= 2'b0; - entry7_extclass_q <= 2'b0; - entry7_hv_q <= 1'b0; - entry7_ds_q <= 1'b0; - entry7_thdid_q <= 4'b0; - entry7_pid_q <= 8'b0; - entry7_v_q <= 1'b0; - entry7_parity_q <= 10'b0; - entry7_cmpmask_q <= 9'b0; - entry8_size_q <= 3'b0; - entry8_xbit_q <= 1'b0; - entry8_epn_q <= 52'b0; - entry8_class_q <= 2'b0; - entry8_extclass_q <= 2'b0; - entry8_hv_q <= 1'b0; - entry8_ds_q <= 1'b0; - entry8_thdid_q <= 4'b0; - entry8_pid_q <= 8'b0; - entry8_v_q <= 1'b0; - entry8_parity_q <= 10'b0; - entry8_cmpmask_q <= 9'b0; - entry9_size_q <= 3'b0; - entry9_xbit_q <= 1'b0; - entry9_epn_q <= 52'b0; - entry9_class_q <= 2'b0; - entry9_extclass_q <= 2'b0; - entry9_hv_q <= 1'b0; - entry9_ds_q <= 1'b0; - entry9_thdid_q <= 4'b0; - entry9_pid_q <= 8'b0; - entry9_v_q <= 1'b0; - entry9_parity_q <= 10'b0; - entry9_cmpmask_q <= 9'b0; - entry10_size_q <= 3'b0; - entry10_xbit_q <= 1'b0; - entry10_epn_q <= 52'b0; - entry10_class_q <= 2'b0; - entry10_extclass_q <= 2'b0; - entry10_hv_q <= 1'b0; - entry10_ds_q <= 1'b0; - entry10_thdid_q <= 4'b0; - entry10_pid_q <= 8'b0; - entry10_v_q <= 1'b0; - entry10_parity_q <= 10'b0; - entry10_cmpmask_q <= 9'b0; - entry11_size_q <= 3'b0; - entry11_xbit_q <= 1'b0; - entry11_epn_q <= 52'b0; - entry11_class_q <= 2'b0; - entry11_extclass_q <= 2'b0; - entry11_hv_q <= 1'b0; - entry11_ds_q <= 1'b0; - entry11_thdid_q <= 4'b0; - entry11_pid_q <= 8'b0; - entry11_v_q <= 1'b0; - entry11_parity_q <= 10'b0; - entry11_cmpmask_q <= 9'b0; - entry12_size_q <= 3'b0; - entry12_xbit_q <= 1'b0; - entry12_epn_q <= 52'b0; - entry12_class_q <= 2'b0; - entry12_extclass_q <= 2'b0; - entry12_hv_q <= 1'b0; - entry12_ds_q <= 1'b0; - entry12_thdid_q <= 4'b0; - entry12_pid_q <= 8'b0; - entry12_v_q <= 1'b0; - entry12_parity_q <= 10'b0; - entry12_cmpmask_q <= 9'b0; - entry13_size_q <= 3'b0; - entry13_xbit_q <= 1'b0; - entry13_epn_q <= 52'b0; - entry13_class_q <= 2'b0; - entry13_extclass_q <= 2'b0; - entry13_hv_q <= 1'b0; - entry13_ds_q <= 1'b0; - entry13_thdid_q <= 4'b0; - entry13_pid_q <= 8'b0; - entry13_v_q <= 1'b0; - entry13_parity_q <= 10'b0; - entry13_cmpmask_q <= 9'b0; - entry14_size_q <= 3'b0; - entry14_xbit_q <= 1'b0; - entry14_epn_q <= 52'b0; - entry14_class_q <= 2'b0; - entry14_extclass_q <= 2'b0; - entry14_hv_q <= 1'b0; - entry14_ds_q <= 1'b0; - entry14_thdid_q <= 4'b0; - entry14_pid_q <= 8'b0; - entry14_v_q <= 1'b0; - entry14_parity_q <= 10'b0; - entry14_cmpmask_q <= 9'b0; - entry15_size_q <= 3'b0; - entry15_xbit_q <= 1'b0; - entry15_epn_q <= 52'b0; - entry15_class_q <= 2'b0; - entry15_extclass_q <= 2'b0; - entry15_hv_q <= 1'b0; - entry15_ds_q <= 1'b0; - entry15_thdid_q <= 4'b0; - entry15_pid_q <= 8'b0; - entry15_v_q <= 1'b0; - entry15_parity_q <= 10'b0; - entry15_cmpmask_q <= 9'b0; - end - else - begin - cam_cmp_data_q <= cam_cmp_data_d; - rd_cam_data_q <= rd_cam_data_d; - rd_array_data_q <= rd_array_data_d; - entry_match_q <= entry_match_d; - cam_hit_entry_q <= cam_hit_entry_d; - cam_hit_q <= cam_hit_d; - cam_cmp_parity_q <= cam_cmp_parity_d; - comp_addr_np1_q <= comp_addr_np1_d; - rpn_np2_q <= rpn_np2_d; - attr_np2_q <= attr_np2_d; - entry0_size_q <= entry0_size_d; - entry0_xbit_q <= entry0_xbit_d; - entry0_epn_q <= entry0_epn_d; - entry0_class_q <= entry0_class_d; - entry0_extclass_q <= entry0_extclass_d; - entry0_hv_q <= entry0_hv_d; - entry0_ds_q <= entry0_ds_d; - entry0_thdid_q <= entry0_thdid_d; - entry0_pid_q <= entry0_pid_d; - entry0_v_q <= entry0_v_d; - entry0_parity_q <= entry0_parity_d; - entry0_cmpmask_q <= entry0_cmpmask_d; - entry1_size_q <= entry1_size_d; - entry1_xbit_q <= entry1_xbit_d; - entry1_epn_q <= entry1_epn_d; - entry1_class_q <= entry1_class_d; - entry1_extclass_q <= entry1_extclass_d; - entry1_hv_q <= entry1_hv_d; - entry1_ds_q <= entry1_ds_d; - entry1_thdid_q <= entry1_thdid_d; - entry1_pid_q <= entry1_pid_d; - entry1_v_q <= entry1_v_d; - entry1_parity_q <= entry1_parity_d; - entry1_cmpmask_q <= entry1_cmpmask_d; - entry2_size_q <= entry2_size_d; - entry2_xbit_q <= entry2_xbit_d; - entry2_epn_q <= entry2_epn_d; - entry2_class_q <= entry2_class_d; - entry2_extclass_q <= entry2_extclass_d; - entry2_hv_q <= entry2_hv_d; - entry2_ds_q <= entry2_ds_d; - entry2_thdid_q <= entry2_thdid_d; - entry2_pid_q <= entry2_pid_d; - entry2_v_q <= entry2_v_d; - entry2_parity_q <= entry2_parity_d; - entry2_cmpmask_q <= entry2_cmpmask_d; - entry3_size_q <= entry3_size_d; - entry3_xbit_q <= entry3_xbit_d; - entry3_epn_q <= entry3_epn_d; - entry3_class_q <= entry3_class_d; - entry3_extclass_q <= entry3_extclass_d; - entry3_hv_q <= entry3_hv_d; - entry3_ds_q <= entry3_ds_d; - entry3_thdid_q <= entry3_thdid_d; - entry3_pid_q <= entry3_pid_d; - entry3_v_q <= entry3_v_d; - entry3_parity_q <= entry3_parity_d; - entry3_cmpmask_q <= entry3_cmpmask_d; - entry4_size_q <= entry4_size_d; - entry4_xbit_q <= entry4_xbit_d; - entry4_epn_q <= entry4_epn_d; - entry4_class_q <= entry4_class_d; - entry4_extclass_q <= entry4_extclass_d; - entry4_hv_q <= entry4_hv_d; - entry4_ds_q <= entry4_ds_d; - entry4_thdid_q <= entry4_thdid_d; - entry4_pid_q <= entry4_pid_d; - entry4_v_q <= entry4_v_d; - entry4_parity_q <= entry4_parity_d; - entry4_cmpmask_q <= entry4_cmpmask_d; - entry5_size_q <= entry5_size_d; - entry5_xbit_q <= entry5_xbit_d; - entry5_epn_q <= entry5_epn_d; - entry5_class_q <= entry5_class_d; - entry5_extclass_q <= entry5_extclass_d; - entry5_hv_q <= entry5_hv_d; - entry5_ds_q <= entry5_ds_d; - entry5_thdid_q <= entry5_thdid_d; - entry5_pid_q <= entry5_pid_d; - entry5_v_q <= entry5_v_d; - entry5_parity_q <= entry5_parity_d; - entry5_cmpmask_q <= entry5_cmpmask_d; - entry6_size_q <= entry6_size_d; - entry6_xbit_q <= entry6_xbit_d; - entry6_epn_q <= entry6_epn_d; - entry6_class_q <= entry6_class_d; - entry6_extclass_q <= entry6_extclass_d; - entry6_hv_q <= entry6_hv_d; - entry6_ds_q <= entry6_ds_d; - entry6_thdid_q <= entry6_thdid_d; - entry6_pid_q <= entry6_pid_d; - entry6_v_q <= entry6_v_d; - entry6_parity_q <= entry6_parity_d; - entry6_cmpmask_q <= entry6_cmpmask_d; - entry7_size_q <= entry7_size_d; - entry7_xbit_q <= entry7_xbit_d; - entry7_epn_q <= entry7_epn_d; - entry7_class_q <= entry7_class_d; - entry7_extclass_q <= entry7_extclass_d; - entry7_hv_q <= entry7_hv_d; - entry7_ds_q <= entry7_ds_d; - entry7_thdid_q <= entry7_thdid_d; - entry7_pid_q <= entry7_pid_d; - entry7_v_q <= entry7_v_d; - entry7_parity_q <= entry7_parity_d; - entry7_cmpmask_q <= entry7_cmpmask_d; - entry8_size_q <= entry8_size_d; - entry8_xbit_q <= entry8_xbit_d; - entry8_epn_q <= entry8_epn_d; - entry8_class_q <= entry8_class_d; - entry8_extclass_q <= entry8_extclass_d; - entry8_hv_q <= entry8_hv_d; - entry8_ds_q <= entry8_ds_d; - entry8_thdid_q <= entry8_thdid_d; - entry8_pid_q <= entry8_pid_d; - entry8_v_q <= entry8_v_d; - entry8_parity_q <= entry8_parity_d; - entry8_cmpmask_q <= entry8_cmpmask_d; - entry9_size_q <= entry9_size_d; - entry9_xbit_q <= entry9_xbit_d; - entry9_epn_q <= entry9_epn_d; - entry9_class_q <= entry9_class_d; - entry9_extclass_q <= entry9_extclass_d; - entry9_hv_q <= entry9_hv_d; - entry9_ds_q <= entry9_ds_d; - entry9_thdid_q <= entry9_thdid_d; - entry9_pid_q <= entry9_pid_d; - entry9_v_q <= entry9_v_d; - entry9_parity_q <= entry9_parity_d; - entry9_cmpmask_q <= entry9_cmpmask_d; - entry10_size_q <= entry10_size_d; - entry10_xbit_q <= entry10_xbit_d; - entry10_epn_q <= entry10_epn_d; - entry10_class_q <= entry10_class_d; - entry10_extclass_q <= entry10_extclass_d; - entry10_hv_q <= entry10_hv_d; - entry10_ds_q <= entry10_ds_d; - entry10_thdid_q <= entry10_thdid_d; - entry10_pid_q <= entry10_pid_d; - entry10_v_q <= entry10_v_d; - entry10_parity_q <= entry10_parity_d; - entry10_cmpmask_q <= entry10_cmpmask_d; - entry11_size_q <= entry11_size_d; - entry11_xbit_q <= entry11_xbit_d; - entry11_epn_q <= entry11_epn_d; - entry11_class_q <= entry11_class_d; - entry11_extclass_q <= entry11_extclass_d; - entry11_hv_q <= entry11_hv_d; - entry11_ds_q <= entry11_ds_d; - entry11_thdid_q <= entry11_thdid_d; - entry11_pid_q <= entry11_pid_d; - entry11_v_q <= entry11_v_d; - entry11_parity_q <= entry11_parity_d; - entry11_cmpmask_q <= entry11_cmpmask_d; - entry12_size_q <= entry12_size_d; - entry12_xbit_q <= entry12_xbit_d; - entry12_epn_q <= entry12_epn_d; - entry12_class_q <= entry12_class_d; - entry12_extclass_q <= entry12_extclass_d; - entry12_hv_q <= entry12_hv_d; - entry12_ds_q <= entry12_ds_d; - entry12_thdid_q <= entry12_thdid_d; - entry12_pid_q <= entry12_pid_d; - entry12_v_q <= entry12_v_d; - entry12_parity_q <= entry12_parity_d; - entry12_cmpmask_q <= entry12_cmpmask_d; - entry13_size_q <= entry13_size_d; - entry13_xbit_q <= entry13_xbit_d; - entry13_epn_q <= entry13_epn_d; - entry13_class_q <= entry13_class_d; - entry13_extclass_q <= entry13_extclass_d; - entry13_hv_q <= entry13_hv_d; - entry13_ds_q <= entry13_ds_d; - entry13_thdid_q <= entry13_thdid_d; - entry13_pid_q <= entry13_pid_d; - entry13_v_q <= entry13_v_d; - entry13_parity_q <= entry13_parity_d; - entry13_cmpmask_q <= entry13_cmpmask_d; - entry14_size_q <= entry14_size_d; - entry14_xbit_q <= entry14_xbit_d; - entry14_epn_q <= entry14_epn_d; - entry14_class_q <= entry14_class_d; - entry14_extclass_q <= entry14_extclass_d; - entry14_hv_q <= entry14_hv_d; - entry14_ds_q <= entry14_ds_d; - entry14_thdid_q <= entry14_thdid_d; - entry14_pid_q <= entry14_pid_d; - entry14_v_q <= entry14_v_d; - entry14_parity_q <= entry14_parity_d; - entry14_cmpmask_q <= entry14_cmpmask_d; - entry15_size_q <= entry15_size_d; - entry15_xbit_q <= entry15_xbit_d; - entry15_epn_q <= entry15_epn_d; - entry15_class_q <= entry15_class_d; - entry15_extclass_q <= entry15_extclass_d; - entry15_hv_q <= entry15_hv_d; - entry15_ds_q <= entry15_ds_d; - entry15_thdid_q <= entry15_thdid_d; - entry15_pid_q <= entry15_pid_d; - entry15_v_q <= entry15_v_d; - entry15_parity_q <= entry15_parity_d; - entry15_cmpmask_q <= entry15_cmpmask_d; - end - end - - //--------------------------------------------------------------------- - // latch input logic - //--------------------------------------------------------------------- - assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; - - assign cam_hit_d = ((match_vec != 16'b0000000000000000) & (comp_request == 1'b1)) ? 1'b1 : - 1'b0; - - assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 4'b0001 : - (match_vec[0:2] == 3'b001) ? 4'b0010 : - (match_vec[0:3] == 4'b0001) ? 4'b0011 : - (match_vec[0:4] == 5'b00001) ? 4'b0100 : - (match_vec[0:5] == 6'b000001) ? 4'b0101 : - (match_vec[0:6] == 7'b0000001) ? 4'b0110 : - (match_vec[0:7] == 8'b00000001) ? 4'b0111 : - (match_vec[0:8] == 9'b000000001) ? 4'b1000 : - (match_vec[0:9] == 10'b0000000001) ? 4'b1001 : - (match_vec[0:10] == 11'b00000000001) ? 4'b1010 : - (match_vec[0:11] == 12'b000000000001) ? 4'b1011 : - (match_vec[0:12] == 13'b0000000000001) ? 4'b1100 : - (match_vec[0:13] == 14'b00000000000001) ? 4'b1101 : - (match_vec[0:14] == 15'b000000000000001) ? 4'b1110 : - (match_vec[0:15] == 16'b0000000000000001) ? 4'b1111 : - 4'b0000; - - assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : - {NUM_ENTRY{1'b0}}; - - // entry write next state logic - assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : - 1'b0; - assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0000)) ? 1'b1 : - 1'b0; - assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry0_epn_q[0:31]; - assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry0_epn_q[32:51]; - assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : - entry0_xbit_q; - assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry0_size_q[0:2]; - assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry0_class_q[0:1]; - assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry0_extclass_q[0:1]; - assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : - entry0_hv_q; - assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : - entry0_ds_q; - assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry0_pid_q[0:7]; - assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry0_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry0_parity_q[0:3]; - assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry0_parity_q[4:6]; - assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry0_parity_q[7]; - assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry0_parity_q[8]; - assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry0_parity_q[9]; - assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : - 1'b0; - assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0001)) ? 1'b1 : - 1'b0; - assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry1_epn_q[0:31]; - assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry1_epn_q[32:51]; - assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : - entry1_xbit_q; - assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry1_size_q[0:2]; - assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry1_class_q[0:1]; - assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry1_extclass_q[0:1]; - assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : - entry1_hv_q; - assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : - entry1_ds_q; - assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry1_pid_q[0:7]; - assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry1_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry1_parity_q[0:3]; - assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry1_parity_q[4:6]; - assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry1_parity_q[7]; - assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry1_parity_q[8]; - assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry1_parity_q[9]; - assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : - 1'b0; - assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0010)) ? 1'b1 : - 1'b0; - assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry2_epn_q[0:31]; - assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry2_epn_q[32:51]; - assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : - entry2_xbit_q; - assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry2_size_q[0:2]; - assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry2_class_q[0:1]; - assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry2_extclass_q[0:1]; - assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : - entry2_hv_q; - assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : - entry2_ds_q; - assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry2_pid_q[0:7]; - assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry2_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry2_parity_q[0:3]; - assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry2_parity_q[4:6]; - assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry2_parity_q[7]; - assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry2_parity_q[8]; - assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry2_parity_q[9]; - assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : - 1'b0; - assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0011)) ? 1'b1 : - 1'b0; - assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry3_epn_q[0:31]; - assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry3_epn_q[32:51]; - assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : - entry3_xbit_q; - assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry3_size_q[0:2]; - assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry3_class_q[0:1]; - assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry3_extclass_q[0:1]; - assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : - entry3_hv_q; - assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : - entry3_ds_q; - assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry3_pid_q[0:7]; - assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry3_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry3_parity_q[0:3]; - assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry3_parity_q[4:6]; - assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry3_parity_q[7]; - assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry3_parity_q[8]; - assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry3_parity_q[9]; - assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : - 1'b0; - assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0100)) ? 1'b1 : - 1'b0; - assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry4_epn_q[0:31]; - assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry4_epn_q[32:51]; - assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : - entry4_xbit_q; - assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry4_size_q[0:2]; - assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry4_class_q[0:1]; - assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry4_extclass_q[0:1]; - assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : - entry4_hv_q; - assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : - entry4_ds_q; - assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry4_pid_q[0:7]; - assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry4_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry4_parity_q[0:3]; - assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry4_parity_q[4:6]; - assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry4_parity_q[7]; - assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry4_parity_q[8]; - assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry4_parity_q[9]; - assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : - 1'b0; - assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0101)) ? 1'b1 : - 1'b0; - assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry5_epn_q[0:31]; - assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry5_epn_q[32:51]; - assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : - entry5_xbit_q; - assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry5_size_q[0:2]; - assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry5_class_q[0:1]; - assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry5_extclass_q[0:1]; - assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : - entry5_hv_q; - assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : - entry5_ds_q; - assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry5_pid_q[0:7]; - assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry5_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry5_parity_q[0:3]; - assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry5_parity_q[4:6]; - assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry5_parity_q[7]; - assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry5_parity_q[8]; - assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry5_parity_q[9]; - assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : - 1'b0; - assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0110)) ? 1'b1 : - 1'b0; - assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry6_epn_q[0:31]; - assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry6_epn_q[32:51]; - assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : - entry6_xbit_q; - assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry6_size_q[0:2]; - assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry6_class_q[0:1]; - assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry6_extclass_q[0:1]; - assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : - entry6_hv_q; - assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : - entry6_ds_q; - assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry6_pid_q[0:7]; - assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry6_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry6_parity_q[0:3]; - assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry6_parity_q[4:6]; - assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry6_parity_q[7]; - assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry6_parity_q[8]; - assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry6_parity_q[9]; - assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : - 1'b0; - assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b0111)) ? 1'b1 : - 1'b0; - assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry7_epn_q[0:31]; - assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry7_epn_q[32:51]; - assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : - entry7_xbit_q; - assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry7_size_q[0:2]; - assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry7_class_q[0:1]; - assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry7_extclass_q[0:1]; - assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : - entry7_hv_q; - assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : - entry7_ds_q; - assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry7_pid_q[0:7]; - assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry7_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry7_parity_q[0:3]; - assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry7_parity_q[4:6]; - assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry7_parity_q[7]; - assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry7_parity_q[8]; - assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry7_parity_q[9]; - assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : - 1'b0; - assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1000)) ? 1'b1 : - 1'b0; - assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry8_epn_q[0:31]; - assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry8_epn_q[32:51]; - assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : - entry8_xbit_q; - assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry8_size_q[0:2]; - assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry8_class_q[0:1]; - assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry8_extclass_q[0:1]; - assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : - entry8_hv_q; - assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : - entry8_ds_q; - assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry8_pid_q[0:7]; - assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry8_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry8_parity_q[0:3]; - assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry8_parity_q[4:6]; - assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry8_parity_q[7]; - assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry8_parity_q[8]; - assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry8_parity_q[9]; - assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : - 1'b0; - assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1001)) ? 1'b1 : - 1'b0; - assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry9_epn_q[0:31]; - assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry9_epn_q[32:51]; - assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : - entry9_xbit_q; - assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry9_size_q[0:2]; - assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry9_class_q[0:1]; - assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry9_extclass_q[0:1]; - assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : - entry9_hv_q; - assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : - entry9_ds_q; - assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry9_pid_q[0:7]; - assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry9_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry9_parity_q[0:3]; - assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry9_parity_q[4:6]; - assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry9_parity_q[7]; - assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry9_parity_q[8]; - assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry9_parity_q[9]; - assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : - 1'b0; - assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1010)) ? 1'b1 : - 1'b0; - assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry10_epn_q[0:31]; - assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry10_epn_q[32:51]; - assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : - entry10_xbit_q; - assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry10_size_q[0:2]; - assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry10_class_q[0:1]; - assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry10_extclass_q[0:1]; - assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : - entry10_hv_q; - assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : - entry10_ds_q; - assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry10_pid_q[0:7]; - assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry10_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry10_parity_q[0:3]; - assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry10_parity_q[4:6]; - assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry10_parity_q[7]; - assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry10_parity_q[8]; - assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry10_parity_q[9]; - assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : - 1'b0; - assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1011)) ? 1'b1 : - 1'b0; - assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry11_epn_q[0:31]; - assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry11_epn_q[32:51]; - assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : - entry11_xbit_q; - assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry11_size_q[0:2]; - assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry11_class_q[0:1]; - assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry11_extclass_q[0:1]; - assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : - entry11_hv_q; - assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : - entry11_ds_q; - assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry11_pid_q[0:7]; - assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry11_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry11_parity_q[0:3]; - assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry11_parity_q[4:6]; - assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry11_parity_q[7]; - assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry11_parity_q[8]; - assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry11_parity_q[9]; - assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : - 1'b0; - assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1100)) ? 1'b1 : - 1'b0; - assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry12_epn_q[0:31]; - assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry12_epn_q[32:51]; - assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : - entry12_xbit_q; - assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry12_size_q[0:2]; - assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry12_class_q[0:1]; - assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry12_extclass_q[0:1]; - assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : - entry12_hv_q; - assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : - entry12_ds_q; - assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry12_pid_q[0:7]; - assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry12_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry12_parity_q[0:3]; - assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry12_parity_q[4:6]; - assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry12_parity_q[7]; - assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry12_parity_q[8]; - assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry12_parity_q[9]; - assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : - 1'b0; - assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1101)) ? 1'b1 : - 1'b0; - assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry13_epn_q[0:31]; - assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry13_epn_q[32:51]; - assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : - entry13_xbit_q; - assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry13_size_q[0:2]; - assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry13_class_q[0:1]; - assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry13_extclass_q[0:1]; - assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : - entry13_hv_q; - assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : - entry13_ds_q; - assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry13_pid_q[0:7]; - assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry13_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry13_parity_q[0:3]; - assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry13_parity_q[4:6]; - assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry13_parity_q[7]; - assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry13_parity_q[8]; - assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry13_parity_q[9]; - assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : - 1'b0; - assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1110)) ? 1'b1 : - 1'b0; - assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry14_epn_q[0:31]; - assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry14_epn_q[32:51]; - assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : - entry14_xbit_q; - assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry14_size_q[0:2]; - assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry14_class_q[0:1]; - assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry14_extclass_q[0:1]; - assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : - entry14_hv_q; - assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : - entry14_ds_q; - assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry14_pid_q[0:7]; - assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry14_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry14_parity_q[0:3]; - assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry14_parity_q[4:6]; - assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry14_parity_q[7]; - assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry14_parity_q[8]; - assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry14_parity_q[9]; - assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : - 1'b0; - assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 4'b1111)) ? 1'b1 : - 1'b0; - assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry15_epn_q[0:31]; - assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry15_epn_q[32:51]; - assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : - entry15_xbit_q; - assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry15_size_q[0:2]; - assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry15_class_q[0:1]; - assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry15_extclass_q[0:1]; - assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : - entry15_hv_q; - assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : - entry15_ds_q; - assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry15_pid_q[0:7]; - assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry15_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry15_parity_q[0:3]; - assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry15_parity_q[4:6]; - assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry15_parity_q[7]; - assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry15_parity_q[8]; - assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry15_parity_q[9]; - - - // entry valid and thdid next state logic - assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; - assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); - assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry0_v_q; - assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry0_thdid_q[0:3]; - assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; - assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); - assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry1_v_q; - assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry1_thdid_q[0:3]; - assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; - assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); - assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry2_v_q; - assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry2_thdid_q[0:3]; - assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; - assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); - assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry3_v_q; - assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry3_thdid_q[0:3]; - assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; - assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); - assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry4_v_q; - assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry4_thdid_q[0:3]; - assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; - assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); - assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry5_v_q; - assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry5_thdid_q[0:3]; - assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; - assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); - assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry6_v_q; - assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry6_thdid_q[0:3]; - assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; - assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); - assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry7_v_q; - assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry7_thdid_q[0:3]; - assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; - assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); - assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry8_v_q; - assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry8_thdid_q[0:3]; - assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; - assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); - assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry9_v_q; - assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry9_thdid_q[0:3]; - assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; - assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); - assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry10_v_q; - assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry10_thdid_q[0:3]; - assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; - assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); - assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry11_v_q; - assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry11_thdid_q[0:3]; - assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; - assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); - assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry12_v_q; - assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry12_thdid_q[0:3]; - assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; - assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); - assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry13_v_q; - assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry13_thdid_q[0:3]; - assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; - assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); - assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry14_v_q; - assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry14_thdid_q[0:3]; - assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; - assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); - assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry15_v_q; - assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry15_thdid_q[0:3]; - - - // CAM compare data out mux - assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; - assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; - assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; - assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; - assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; - assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; - assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; - assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; - assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; - assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; - assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; - assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; - assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; - assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; - assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; - assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; - - - assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; - assign cam_cmp_data_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_cam_vec : - (cam_cmp_data_muxsel == 5'b00001) ? entry1_cam_vec : - (cam_cmp_data_muxsel == 5'b00010) ? entry2_cam_vec : - (cam_cmp_data_muxsel == 5'b00011) ? entry3_cam_vec : - (cam_cmp_data_muxsel == 5'b00100) ? entry4_cam_vec : - (cam_cmp_data_muxsel == 5'b00101) ? entry5_cam_vec : - (cam_cmp_data_muxsel == 5'b00110) ? entry6_cam_vec : - (cam_cmp_data_muxsel == 5'b00111) ? entry7_cam_vec : - (cam_cmp_data_muxsel == 5'b01000) ? entry8_cam_vec : - (cam_cmp_data_muxsel == 5'b01001) ? entry9_cam_vec : - (cam_cmp_data_muxsel == 5'b01010) ? entry10_cam_vec : - (cam_cmp_data_muxsel == 5'b01011) ? entry11_cam_vec : - (cam_cmp_data_muxsel == 5'b01100) ? entry12_cam_vec : - (cam_cmp_data_muxsel == 5'b01101) ? entry13_cam_vec : - (cam_cmp_data_muxsel == 5'b01110) ? entry14_cam_vec : - (cam_cmp_data_muxsel == 5'b01111) ? entry15_cam_vec : - cam_cmp_data_q; - - assign cam_cmp_data_np1 = cam_cmp_data_q; - - // CAM read data out mux - assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; - - assign rd_cam_data_d = (rd_cam_data_muxsel == 5'b00000) ? entry0_cam_vec : - (rd_cam_data_muxsel == 5'b00001) ? entry1_cam_vec : - (rd_cam_data_muxsel == 5'b00010) ? entry2_cam_vec : - (rd_cam_data_muxsel == 5'b00011) ? entry3_cam_vec : - (rd_cam_data_muxsel == 5'b00100) ? entry4_cam_vec : - (rd_cam_data_muxsel == 5'b00101) ? entry5_cam_vec : - (rd_cam_data_muxsel == 5'b00110) ? entry6_cam_vec : - (rd_cam_data_muxsel == 5'b00111) ? entry7_cam_vec : - (rd_cam_data_muxsel == 5'b01000) ? entry8_cam_vec : - (rd_cam_data_muxsel == 5'b01001) ? entry9_cam_vec : - (rd_cam_data_muxsel == 5'b01010) ? entry10_cam_vec : - (rd_cam_data_muxsel == 5'b01011) ? entry11_cam_vec : - (rd_cam_data_muxsel == 5'b01100) ? entry12_cam_vec : - (rd_cam_data_muxsel == 5'b01101) ? entry13_cam_vec : - (rd_cam_data_muxsel == 5'b01110) ? entry14_cam_vec : - (rd_cam_data_muxsel == 5'b01111) ? entry15_cam_vec : - rd_cam_data_q; - - // CAM compare parity out mux - assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 5'b00000) ? entry0_parity_q : - (cam_cmp_data_muxsel == 5'b00001) ? entry1_parity_q : - (cam_cmp_data_muxsel == 5'b00010) ? entry2_parity_q : - (cam_cmp_data_muxsel == 5'b00011) ? entry3_parity_q : - (cam_cmp_data_muxsel == 5'b00100) ? entry4_parity_q : - (cam_cmp_data_muxsel == 5'b00101) ? entry5_parity_q : - (cam_cmp_data_muxsel == 5'b00110) ? entry6_parity_q : - (cam_cmp_data_muxsel == 5'b00111) ? entry7_parity_q : - (cam_cmp_data_muxsel == 5'b01000) ? entry8_parity_q : - (cam_cmp_data_muxsel == 5'b01001) ? entry9_parity_q : - (cam_cmp_data_muxsel == 5'b01010) ? entry10_parity_q : - (cam_cmp_data_muxsel == 5'b01011) ? entry11_parity_q : - (cam_cmp_data_muxsel == 5'b01100) ? entry12_parity_q : - (cam_cmp_data_muxsel == 5'b01101) ? entry13_parity_q : - (cam_cmp_data_muxsel == 5'b01110) ? entry14_parity_q : - (cam_cmp_data_muxsel == 5'b01111) ? entry15_parity_q : - cam_cmp_parity_q; - - assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; - assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; - assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; - - assign array_cmp_data = array_cmp_data_np1; - - // CAM read parity out mux - assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 5'b00000) ? entry0_parity_q : - (rd_cam_data_muxsel == 5'b00001) ? entry1_parity_q : - (rd_cam_data_muxsel == 5'b00010) ? entry2_parity_q : - (rd_cam_data_muxsel == 5'b00011) ? entry3_parity_q : - (rd_cam_data_muxsel == 5'b00100) ? entry4_parity_q : - (rd_cam_data_muxsel == 5'b00101) ? entry5_parity_q : - (rd_cam_data_muxsel == 5'b00110) ? entry6_parity_q : - (rd_cam_data_muxsel == 5'b00111) ? entry7_parity_q : - (rd_cam_data_muxsel == 5'b01000) ? entry8_parity_q : - (rd_cam_data_muxsel == 5'b01001) ? entry9_parity_q : - (rd_cam_data_muxsel == 5'b01010) ? entry10_parity_q : - (rd_cam_data_muxsel == 5'b01011) ? entry11_parity_q : - (rd_cam_data_muxsel == 5'b01100) ? entry12_parity_q : - (rd_cam_data_muxsel == 5'b01101) ? entry13_parity_q : - (rd_cam_data_muxsel == 5'b01110) ? entry14_parity_q : - (rd_cam_data_muxsel == 5'b01111) ? entry15_parity_q : - rd_array_data_q[51:60]; - - // internal bypass latch input for rpn - // using cam_cmp_data(75:78) cmpmask bits for mux selects - assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | - (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array - - //CAM_PgSize_1GB - assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_1GB or CAM_PgSize_16MB - assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB - assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_Larger_than_4K - assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); - - // internal bypass latch input for attributes - assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | - (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); - - // new port output assignments - assign rpn_np2[22:51] = rpn_np2_q[22:51]; - assign attr_np2[0:20] = attr_np2_q[0:20]; - - //--------------------------------------------------------------------- - // matchline component instantiations - //--------------------------------------------------------------------- - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry0_size_q), - .entry_cmpmask(entry0_cmpmask_q[0:3]), - .entry_xbit(entry0_xbit_q), - .entry_xbitmask(entry0_cmpmask_q[4:7]), - .entry_epn(entry0_epn_q), - .comp_class(comp_class), - .entry_class(entry0_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry0_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry0_hv_q), - .entry_ds(entry0_ds_q), - .state_enable(state_enable), - .entry_thdid(entry0_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry0_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry0_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[0]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry1_size_q), - .entry_cmpmask(entry1_cmpmask_q[0:3]), - .entry_xbit(entry1_xbit_q), - .entry_xbitmask(entry1_cmpmask_q[4:7]), - .entry_epn(entry1_epn_q), - .comp_class(comp_class), - .entry_class(entry1_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry1_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry1_hv_q), - .entry_ds(entry1_ds_q), - .state_enable(state_enable), - .entry_thdid(entry1_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry1_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry1_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[1]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry2_size_q), - .entry_cmpmask(entry2_cmpmask_q[0:3]), - .entry_xbit(entry2_xbit_q), - .entry_xbitmask(entry2_cmpmask_q[4:7]), - .entry_epn(entry2_epn_q), - .comp_class(comp_class), - .entry_class(entry2_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry2_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry2_hv_q), - .entry_ds(entry2_ds_q), - .state_enable(state_enable), - .entry_thdid(entry2_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry2_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry2_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[2]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry3_size_q), - .entry_cmpmask(entry3_cmpmask_q[0:3]), - .entry_xbit(entry3_xbit_q), - .entry_xbitmask(entry3_cmpmask_q[4:7]), - .entry_epn(entry3_epn_q), - .comp_class(comp_class), - .entry_class(entry3_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry3_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry3_hv_q), - .entry_ds(entry3_ds_q), - .state_enable(state_enable), - .entry_thdid(entry3_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry3_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry3_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[3]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry4_size_q), - .entry_cmpmask(entry4_cmpmask_q[0:3]), - .entry_xbit(entry4_xbit_q), - .entry_xbitmask(entry4_cmpmask_q[4:7]), - .entry_epn(entry4_epn_q), - .comp_class(comp_class), - .entry_class(entry4_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry4_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry4_hv_q), - .entry_ds(entry4_ds_q), - .state_enable(state_enable), - .entry_thdid(entry4_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry4_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry4_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[4]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry5_size_q), - .entry_cmpmask(entry5_cmpmask_q[0:3]), - .entry_xbit(entry5_xbit_q), - .entry_xbitmask(entry5_cmpmask_q[4:7]), - .entry_epn(entry5_epn_q), - .comp_class(comp_class), - .entry_class(entry5_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry5_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry5_hv_q), - .entry_ds(entry5_ds_q), - .state_enable(state_enable), - .entry_thdid(entry5_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry5_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry5_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[5]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry6_size_q), - .entry_cmpmask(entry6_cmpmask_q[0:3]), - .entry_xbit(entry6_xbit_q), - .entry_xbitmask(entry6_cmpmask_q[4:7]), - .entry_epn(entry6_epn_q), - .comp_class(comp_class), - .entry_class(entry6_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry6_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry6_hv_q), - .entry_ds(entry6_ds_q), - .state_enable(state_enable), - .entry_thdid(entry6_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry6_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry6_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[6]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry7_size_q), - .entry_cmpmask(entry7_cmpmask_q[0:3]), - .entry_xbit(entry7_xbit_q), - .entry_xbitmask(entry7_cmpmask_q[4:7]), - .entry_epn(entry7_epn_q), - .comp_class(comp_class), - .entry_class(entry7_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry7_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry7_hv_q), - .entry_ds(entry7_ds_q), - .state_enable(state_enable), - .entry_thdid(entry7_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry7_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry7_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[7]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry8_size_q), - .entry_cmpmask(entry8_cmpmask_q[0:3]), - .entry_xbit(entry8_xbit_q), - .entry_xbitmask(entry8_cmpmask_q[4:7]), - .entry_epn(entry8_epn_q), - .comp_class(comp_class), - .entry_class(entry8_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry8_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry8_hv_q), - .entry_ds(entry8_ds_q), - .state_enable(state_enable), - .entry_thdid(entry8_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry8_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry8_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[8]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry9_size_q), - .entry_cmpmask(entry9_cmpmask_q[0:3]), - .entry_xbit(entry9_xbit_q), - .entry_xbitmask(entry9_cmpmask_q[4:7]), - .entry_epn(entry9_epn_q), - .comp_class(comp_class), - .entry_class(entry9_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry9_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry9_hv_q), - .entry_ds(entry9_ds_q), - .state_enable(state_enable), - .entry_thdid(entry9_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry9_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry9_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[9]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry10_size_q), - .entry_cmpmask(entry10_cmpmask_q[0:3]), - .entry_xbit(entry10_xbit_q), - .entry_xbitmask(entry10_cmpmask_q[4:7]), - .entry_epn(entry10_epn_q), - .comp_class(comp_class), - .entry_class(entry10_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry10_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry10_hv_q), - .entry_ds(entry10_ds_q), - .state_enable(state_enable), - .entry_thdid(entry10_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry10_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry10_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[10]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry11_size_q), - .entry_cmpmask(entry11_cmpmask_q[0:3]), - .entry_xbit(entry11_xbit_q), - .entry_xbitmask(entry11_cmpmask_q[4:7]), - .entry_epn(entry11_epn_q), - .comp_class(comp_class), - .entry_class(entry11_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry11_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry11_hv_q), - .entry_ds(entry11_ds_q), - .state_enable(state_enable), - .entry_thdid(entry11_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry11_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry11_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[11]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry12_size_q), - .entry_cmpmask(entry12_cmpmask_q[0:3]), - .entry_xbit(entry12_xbit_q), - .entry_xbitmask(entry12_cmpmask_q[4:7]), - .entry_epn(entry12_epn_q), - .comp_class(comp_class), - .entry_class(entry12_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry12_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry12_hv_q), - .entry_ds(entry12_ds_q), - .state_enable(state_enable), - .entry_thdid(entry12_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry12_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry12_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[12]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry13_size_q), - .entry_cmpmask(entry13_cmpmask_q[0:3]), - .entry_xbit(entry13_xbit_q), - .entry_xbitmask(entry13_cmpmask_q[4:7]), - .entry_epn(entry13_epn_q), - .comp_class(comp_class), - .entry_class(entry13_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry13_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry13_hv_q), - .entry_ds(entry13_ds_q), - .state_enable(state_enable), - .entry_thdid(entry13_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry13_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry13_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[13]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry14_size_q), - .entry_cmpmask(entry14_cmpmask_q[0:3]), - .entry_xbit(entry14_xbit_q), - .entry_xbitmask(entry14_cmpmask_q[4:7]), - .entry_epn(entry14_epn_q), - .comp_class(comp_class), - .entry_class(entry14_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry14_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry14_hv_q), - .entry_ds(entry14_ds_q), - .state_enable(state_enable), - .entry_thdid(entry14_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry14_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry14_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[14]) - ); - - tri_cam_16x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry15_size_q), - .entry_cmpmask(entry15_cmpmask_q[0:3]), - .entry_xbit(entry15_xbit_q), - .entry_xbitmask(entry15_cmpmask_q[4:7]), - .entry_epn(entry15_epn_q), - .comp_class(comp_class), - .entry_class(entry15_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry15_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry15_hv_q), - .entry_ds(entry15_ds_q), - .state_enable(state_enable), - .entry_thdid(entry15_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry15_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry15_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[15]) - ); - - - //--------------------------------------------------------------------- - // BRAM signal assignments - //--------------------------------------------------------------------- - assign bram0_wea = wr_array_val[0]; - assign bram1_wea = wr_array_val[1]; - assign bram2_wea = wr_array_val[1];; - - assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - - assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; - assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; - assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; - - // Unused Address Bits - assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; - assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; - assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; - assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; - assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; - assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; - - // was 3 brams using clk2x w/wea on 2of2; matchline is combinational - always @(posedge clk) begin - - if (bram0_wea) begin - mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; - end - if (bram1_wea) begin - mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; - end - - end - - assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; - assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; - assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; - assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; - -/* - RAMB16_S36_S36 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram0( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram0_addra), - .ADDRB(bram0_addrb), - .DIA(wr_array_data_bram[0:31]), - .DIB(32'b0), - .DOA(rd_array_data_d_std[0:31]), - .DOB(array_cmp_data_bram_std[0:31]), - .DOPA(rd_array_data_d_std[66:69]), - .DOPB(array_cmp_data_bramp_std[66:69]), - .DIPA(wr_array_data_bram[66:69]), - .DIPB(4'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram0_wea), - .WEB(1'b0) - ); - - // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) - // uses wr_array_val(1), parity is wr_array_data_bram(70) - RAMB16_S9_S9 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram1( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram1_addra), - .ADDRB(bram1_addrb), - .DIA(wr_array_data_bram[32:39]), - .DIB(8'b0), - .DOA(rd_array_data_d_std[32:39]), - .DOB(array_cmp_data_bram_std[32:39]), - .DOPA(rd_array_data_d_std[70:70]), - .DOPB(array_cmp_data_bramp_std[70:70]), - .DIPA(wr_array_data_bram[70:70]), - .DIPB(1'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram1_wea), - .WEB(1'b0) - ); - - // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) - // uses wr_array_val(1), parity is wr_array_data_bram(71:72) - RAMB16_S18_S18 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram2( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram2_addra), - .ADDRB(bram2_addrb), - .DIA(wr_array_data_bram[40:55]), - .DIB(16'b0), - .DOA(rd_array_data_d_std[40:55]), - .DOB(array_cmp_data_bram_std[40:55]), - .DOPA(rd_array_data_d_std[71:72]), - .DOPB(array_cmp_data_bramp_std[71:72]), - .DIPA(wr_array_data_bram[71:72]), - .DIPB(2'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram2_wea), - .WEB(1'b0) - ); -*/ - - // array write data swizzle -> convert 68-bit data to 73-bit bram data - // 32x143 version, 42b RA - // wr_array_data - // 0:29 - RPN - // 30:31 - R,C - // 32:35 - ResvAttr - // 36:39 - U0-U3 - // 40:44 - WIMGE - // 45:47 - UX,UW,UR - // 48:50 - SX,SW,SR - // 51:60 - CAM parity - // 61:67 - Array parity - // - // RTX layout in A2_AvpEratHelper.C - // ram0(0:31): 00 & RPN(0:29) - // ram1(0:7) : 00 & R,C,ResvAttr(0:3) - // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR - assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; - - assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits - - assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; - assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; - assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; - assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; - assign array_cmp_data_bram = array_cmp_data_bram_std; - assign array_cmp_data_bramp = array_cmp_data_bramp_std; - - //--------------------------------------------------------------------- - // entity output assignments - //--------------------------------------------------------------------- - assign rd_array_data = rd_array_data_q; - assign cam_cmp_data = cam_cmp_data_q; - assign rd_cam_data = rd_cam_data_q; - - assign entry_valid[0] = entry0_v_q; - assign entry_valid[1] = entry1_v_q; - assign entry_valid[2] = entry2_v_q; - assign entry_valid[3] = entry3_v_q; - assign entry_valid[4] = entry4_v_q; - assign entry_valid[5] = entry5_v_q; - assign entry_valid[6] = entry6_v_q; - assign entry_valid[7] = entry7_v_q; - assign entry_valid[8] = entry8_v_q; - assign entry_valid[9] = entry9_v_q; - assign entry_valid[10] = entry10_v_q; - assign entry_valid[11] = entry11_v_q; - assign entry_valid[12] = entry12_v_q; - assign entry_valid[13] = entry13_v_q; - assign entry_valid[14] = entry14_v_q; - assign entry_valid[15] = entry15_v_q; - - assign entry_match = entry_match_q; - - assign cam_hit_entry = cam_hit_entry_q; - assign cam_hit = cam_hit_q; - - assign func_scan_out = func_scan_in; - assign regfile_scan_out = regfile_scan_in; - assign time_scan_out = time_scan_in; - - assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, - tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, - lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, - pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, - pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], - array_cmp_data_bram[40], wr_array_data_bram[56:65], - cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], - rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], - rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; -endmodule diff --git a/dev/verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v b/dev/verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v deleted file mode 100755 index 92ffeed..0000000 --- a/dev/verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v +++ /dev/null @@ -1,4847 +0,0 @@ -// © IBM Corp. 2022 -// Licensed under the Apache License, Version 2.0 (the "License"), as modified by -// the terms below; you may not use the files in this repository except in -// compliance with the License as modified. -// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 -// -// Modified Terms: -// -// 1) For the purpose of the patent license granted to you in Section 3 of the -// License, the "Work" hereby includes implementations of the work of authorship -// in physical form. -// -// 2) Notwithstanding any terms to the contrary in the License, any licenses -// necessary for implementation of the Work that are available from OpenPOWER -// via the Power ISA End User License Agreement (EULA) are explicitly excluded -// hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. -// -// Unless required by applicable law or agreed to in writing, the reference design -// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT -// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License -// for the specific language governing permissions and limitations under the License. -// -// Additional rights, including the ability to physically implement a softcore that -// is compliant with the required sections of the Power ISA Specification, are -// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. - -`timescale 1 ns / 1 ns - -//******************************************************************** -//* TITLE: I-ERAT CAM Tri-Library Model -//* NAME: tri_cam_32x143_1r1w1c -//******************************************************************** - -// sim version, clk1x - -`include "tri_a2o.vh" - -module tri_cam_32x143_1r1w1c( - gnd, - vdd, - vcs, - nclk, - tc_ccflush_dc, - tc_scan_dis_dc_b, - tc_scan_diag_dc, - tc_lbist_en_dc, - an_ac_atpg_en_dc, - lcb_d_mode_dc, - lcb_clkoff_dc_b, - lcb_act_dis_dc, - lcb_mpw1_dc_b, - lcb_mpw2_dc_b, - lcb_delay_lclkr_dc, - pc_sg_2, - pc_func_slp_sl_thold_2, - pc_func_slp_nsl_thold_2, - pc_regf_slp_sl_thold_2, - pc_time_sl_thold_2, - pc_fce_2, - func_scan_in, - func_scan_out, - regfile_scan_in, - regfile_scan_out, - time_scan_in, - time_scan_out, - rd_val, - rd_val_late, - rw_entry, - wr_array_data, - wr_cam_data, - wr_array_val, - wr_cam_val, - wr_val_early, - comp_request, - comp_addr, - addr_enable, - comp_pgsize, - pgsize_enable, - comp_class, - class_enable, - comp_extclass, - extclass_enable, - comp_state, - state_enable, - comp_thdid, - thdid_enable, - comp_pid, - pid_enable, - comp_invalidate, - flash_invalidate, - array_cmp_data, - rd_array_data, - cam_cmp_data, - cam_hit, - cam_hit_entry, - entry_match, - entry_valid, - rd_cam_data, - bypass_mux_enab_np1, - bypass_attr_np1, - attr_np2, - rpn_np2 -); - parameter CAM_DATA_WIDTH = 84; - parameter ARRAY_DATA_WIDTH = 68; - parameter RPN_WIDTH = 30; - parameter NUM_ENTRY = 32; - parameter NUM_ENTRY_LOG2 = 5; - - // Power Pins - inout gnd; - inout vdd; - inout vcs; - - // Clocks and Scan Cntls - input [0:`NCLK_WIDTH-1] nclk; - input tc_ccflush_dc; - input tc_scan_dis_dc_b; - input tc_scan_diag_dc; - input tc_lbist_en_dc; - input an_ac_atpg_en_dc; - - input lcb_d_mode_dc; - input lcb_clkoff_dc_b; - input lcb_act_dis_dc; - input [0:3] lcb_mpw1_dc_b; - input lcb_mpw2_dc_b; - input [0:3] lcb_delay_lclkr_dc; - - input pc_sg_2; - input pc_func_slp_sl_thold_2; - input pc_func_slp_nsl_thold_2; - input pc_regf_slp_sl_thold_2; - input pc_time_sl_thold_2; - input pc_fce_2; - - input func_scan_in; - output func_scan_out; - input [0:6] regfile_scan_in; // 0:2 -> CAM, 3:6 -> RAM - output [0:6] regfile_scan_out; - input time_scan_in; - output time_scan_out; - - // Read Port - input rd_val; - input rd_val_late; - input [0:NUM_ENTRY_LOG2-1] rw_entry; - - // Write Port - input [0:ARRAY_DATA_WIDTH-1] wr_array_data; - input [0:CAM_DATA_WIDTH-1] wr_cam_data; - input [0:1] wr_array_val; - input [0:1] wr_cam_val; - input wr_val_early; - - // CAM Port - input comp_request; - input [0:51] comp_addr; - input [0:1] addr_enable; - input [0:2] comp_pgsize; - input pgsize_enable; - input [0:1] comp_class; - input [0:2] class_enable; - input [0:1] comp_extclass; - input [0:1] extclass_enable; - input [0:1] comp_state; - input [0:1] state_enable; - input [0:3] comp_thdid; - input [0:1] thdid_enable; - input [0:7] comp_pid; - input pid_enable; - input comp_invalidate; - input flash_invalidate; - - // Outputs - // Data Out - output [0:ARRAY_DATA_WIDTH-1] array_cmp_data; - output [0:ARRAY_DATA_WIDTH-1] rd_array_data; - - // CAM Output - output [0:CAM_DATA_WIDTH-1] cam_cmp_data; - output cam_hit; - output [0:NUM_ENTRY_LOG2-1] cam_hit_entry; - output [0:NUM_ENTRY-1] entry_match; - output [0:NUM_ENTRY-1] entry_valid; - output [0:CAM_DATA_WIDTH-1] rd_cam_data; - - //--- new ports for IO plus ----------------------- - input bypass_mux_enab_np1; - input [0:20] bypass_attr_np1; - output [0:20] attr_np2; - - output [22:51] rpn_np2; - - // tri_cam_32x143_1r1w1c - - // Configuration Statement for NCsim - //for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9; - //for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18; - //for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36; - - wire clk; - wire [0:8] bram0_addra; - wire [0:8] bram0_addrb; - wire [0:10] bram1_addra; - wire [0:10] bram1_addrb; - wire [0:9] bram2_addra; - wire [0:9] bram2_addrb; - wire bram0_wea; - wire bram1_wea; - wire bram2_wea; - wire [0:55] array_cmp_data_bram; - wire [66:72] array_cmp_data_bramp; - - // Latches - reg sreset_q; - wire [52-RPN_WIDTH:51] comp_addr_np1_d; - reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input - wire [52-RPN_WIDTH:51] rpn_np2_d; - reg [52-RPN_WIDTH:51] rpn_np2_q; - wire [0:20] attr_np2_d; - reg [0:20] attr_np2_q; - - // CAM entry signals - wire [0:51] entry0_epn_d; - reg [0:51] entry0_epn_q; - wire entry0_xbit_d; - reg entry0_xbit_q; - wire [0:2] entry0_size_d; - reg [0:2] entry0_size_q; - wire entry0_v_d; - reg entry0_v_q; - wire [0:3] entry0_thdid_d; - reg [0:3] entry0_thdid_q; - wire [0:1] entry0_class_d; - reg [0:1] entry0_class_q; - wire [0:1] entry0_extclass_d; - reg [0:1] entry0_extclass_q; - wire entry0_hv_d; - reg entry0_hv_q; - wire entry0_ds_d; - reg entry0_ds_q; - wire [0:7] entry0_pid_d; - reg [0:7] entry0_pid_q; - wire [0:8] entry0_cmpmask_d; - reg [0:8] entry0_cmpmask_q; - wire [0:9] entry0_parity_d; - reg [0:9] entry0_parity_q; - wire [0:1] wr_entry0_sel; - wire entry0_inval; - wire [0:1] entry0_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry0_cam_vec; - wire [0:51] entry1_epn_d; - reg [0:51] entry1_epn_q; - wire entry1_xbit_d; - reg entry1_xbit_q; - wire [0:2] entry1_size_d; - reg [0:2] entry1_size_q; - wire entry1_v_d; - reg entry1_v_q; - wire [0:3] entry1_thdid_d; - reg [0:3] entry1_thdid_q; - wire [0:1] entry1_class_d; - reg [0:1] entry1_class_q; - wire [0:1] entry1_extclass_d; - reg [0:1] entry1_extclass_q; - wire entry1_hv_d; - reg entry1_hv_q; - wire entry1_ds_d; - reg entry1_ds_q; - wire [0:7] entry1_pid_d; - reg [0:7] entry1_pid_q; - wire [0:8] entry1_cmpmask_d; - reg [0:8] entry1_cmpmask_q; - wire [0:9] entry1_parity_d; - reg [0:9] entry1_parity_q; - wire [0:1] wr_entry1_sel; - wire entry1_inval; - wire [0:1] entry1_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry1_cam_vec; - wire [0:51] entry2_epn_d; - reg [0:51] entry2_epn_q; - wire entry2_xbit_d; - reg entry2_xbit_q; - wire [0:2] entry2_size_d; - reg [0:2] entry2_size_q; - wire entry2_v_d; - reg entry2_v_q; - wire [0:3] entry2_thdid_d; - reg [0:3] entry2_thdid_q; - wire [0:1] entry2_class_d; - reg [0:1] entry2_class_q; - wire [0:1] entry2_extclass_d; - reg [0:1] entry2_extclass_q; - wire entry2_hv_d; - reg entry2_hv_q; - wire entry2_ds_d; - reg entry2_ds_q; - wire [0:7] entry2_pid_d; - reg [0:7] entry2_pid_q; - wire [0:8] entry2_cmpmask_d; - reg [0:8] entry2_cmpmask_q; - wire [0:9] entry2_parity_d; - reg [0:9] entry2_parity_q; - wire [0:1] wr_entry2_sel; - wire entry2_inval; - wire [0:1] entry2_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry2_cam_vec; - wire [0:51] entry3_epn_d; - reg [0:51] entry3_epn_q; - wire entry3_xbit_d; - reg entry3_xbit_q; - wire [0:2] entry3_size_d; - reg [0:2] entry3_size_q; - wire entry3_v_d; - reg entry3_v_q; - wire [0:3] entry3_thdid_d; - reg [0:3] entry3_thdid_q; - wire [0:1] entry3_class_d; - reg [0:1] entry3_class_q; - wire [0:1] entry3_extclass_d; - reg [0:1] entry3_extclass_q; - wire entry3_hv_d; - reg entry3_hv_q; - wire entry3_ds_d; - reg entry3_ds_q; - wire [0:7] entry3_pid_d; - reg [0:7] entry3_pid_q; - wire [0:8] entry3_cmpmask_d; - reg [0:8] entry3_cmpmask_q; - wire [0:9] entry3_parity_d; - reg [0:9] entry3_parity_q; - wire [0:1] wr_entry3_sel; - wire entry3_inval; - wire [0:1] entry3_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry3_cam_vec; - wire [0:51] entry4_epn_d; - reg [0:51] entry4_epn_q; - wire entry4_xbit_d; - reg entry4_xbit_q; - wire [0:2] entry4_size_d; - reg [0:2] entry4_size_q; - wire entry4_v_d; - reg entry4_v_q; - wire [0:3] entry4_thdid_d; - reg [0:3] entry4_thdid_q; - wire [0:1] entry4_class_d; - reg [0:1] entry4_class_q; - wire [0:1] entry4_extclass_d; - reg [0:1] entry4_extclass_q; - wire entry4_hv_d; - reg entry4_hv_q; - wire entry4_ds_d; - reg entry4_ds_q; - wire [0:7] entry4_pid_d; - reg [0:7] entry4_pid_q; - wire [0:8] entry4_cmpmask_d; - reg [0:8] entry4_cmpmask_q; - wire [0:9] entry4_parity_d; - reg [0:9] entry4_parity_q; - wire [0:1] wr_entry4_sel; - wire entry4_inval; - wire [0:1] entry4_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry4_cam_vec; - wire [0:51] entry5_epn_d; - reg [0:51] entry5_epn_q; - wire entry5_xbit_d; - reg entry5_xbit_q; - wire [0:2] entry5_size_d; - reg [0:2] entry5_size_q; - wire entry5_v_d; - reg entry5_v_q; - wire [0:3] entry5_thdid_d; - reg [0:3] entry5_thdid_q; - wire [0:1] entry5_class_d; - reg [0:1] entry5_class_q; - wire [0:1] entry5_extclass_d; - reg [0:1] entry5_extclass_q; - wire entry5_hv_d; - reg entry5_hv_q; - wire entry5_ds_d; - reg entry5_ds_q; - wire [0:7] entry5_pid_d; - reg [0:7] entry5_pid_q; - wire [0:8] entry5_cmpmask_d; - reg [0:8] entry5_cmpmask_q; - wire [0:9] entry5_parity_d; - reg [0:9] entry5_parity_q; - wire [0:1] wr_entry5_sel; - wire entry5_inval; - wire [0:1] entry5_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry5_cam_vec; - wire [0:51] entry6_epn_d; - reg [0:51] entry6_epn_q; - wire entry6_xbit_d; - reg entry6_xbit_q; - wire [0:2] entry6_size_d; - reg [0:2] entry6_size_q; - wire entry6_v_d; - reg entry6_v_q; - wire [0:3] entry6_thdid_d; - reg [0:3] entry6_thdid_q; - wire [0:1] entry6_class_d; - reg [0:1] entry6_class_q; - wire [0:1] entry6_extclass_d; - reg [0:1] entry6_extclass_q; - wire entry6_hv_d; - reg entry6_hv_q; - wire entry6_ds_d; - reg entry6_ds_q; - wire [0:7] entry6_pid_d; - reg [0:7] entry6_pid_q; - wire [0:8] entry6_cmpmask_d; - reg [0:8] entry6_cmpmask_q; - wire [0:9] entry6_parity_d; - reg [0:9] entry6_parity_q; - wire [0:1] wr_entry6_sel; - wire entry6_inval; - wire [0:1] entry6_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry6_cam_vec; - wire [0:51] entry7_epn_d; - reg [0:51] entry7_epn_q; - wire entry7_xbit_d; - reg entry7_xbit_q; - wire [0:2] entry7_size_d; - reg [0:2] entry7_size_q; - wire entry7_v_d; - reg entry7_v_q; - wire [0:3] entry7_thdid_d; - reg [0:3] entry7_thdid_q; - wire [0:1] entry7_class_d; - reg [0:1] entry7_class_q; - wire [0:1] entry7_extclass_d; - reg [0:1] entry7_extclass_q; - wire entry7_hv_d; - reg entry7_hv_q; - wire entry7_ds_d; - reg entry7_ds_q; - wire [0:7] entry7_pid_d; - reg [0:7] entry7_pid_q; - wire [0:8] entry7_cmpmask_d; - reg [0:8] entry7_cmpmask_q; - wire [0:9] entry7_parity_d; - reg [0:9] entry7_parity_q; - wire [0:1] wr_entry7_sel; - wire entry7_inval; - wire [0:1] entry7_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry7_cam_vec; - wire [0:51] entry8_epn_d; - reg [0:51] entry8_epn_q; - wire entry8_xbit_d; - reg entry8_xbit_q; - wire [0:2] entry8_size_d; - reg [0:2] entry8_size_q; - wire entry8_v_d; - reg entry8_v_q; - wire [0:3] entry8_thdid_d; - reg [0:3] entry8_thdid_q; - wire [0:1] entry8_class_d; - reg [0:1] entry8_class_q; - wire [0:1] entry8_extclass_d; - reg [0:1] entry8_extclass_q; - wire entry8_hv_d; - reg entry8_hv_q; - wire entry8_ds_d; - reg entry8_ds_q; - wire [0:7] entry8_pid_d; - reg [0:7] entry8_pid_q; - wire [0:8] entry8_cmpmask_d; - reg [0:8] entry8_cmpmask_q; - wire [0:9] entry8_parity_d; - reg [0:9] entry8_parity_q; - wire [0:1] wr_entry8_sel; - wire entry8_inval; - wire [0:1] entry8_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry8_cam_vec; - wire [0:51] entry9_epn_d; - reg [0:51] entry9_epn_q; - wire entry9_xbit_d; - reg entry9_xbit_q; - wire [0:2] entry9_size_d; - reg [0:2] entry9_size_q; - wire entry9_v_d; - reg entry9_v_q; - wire [0:3] entry9_thdid_d; - reg [0:3] entry9_thdid_q; - wire [0:1] entry9_class_d; - reg [0:1] entry9_class_q; - wire [0:1] entry9_extclass_d; - reg [0:1] entry9_extclass_q; - wire entry9_hv_d; - reg entry9_hv_q; - wire entry9_ds_d; - reg entry9_ds_q; - wire [0:7] entry9_pid_d; - reg [0:7] entry9_pid_q; - wire [0:8] entry9_cmpmask_d; - reg [0:8] entry9_cmpmask_q; - wire [0:9] entry9_parity_d; - reg [0:9] entry9_parity_q; - wire [0:1] wr_entry9_sel; - wire entry9_inval; - wire [0:1] entry9_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry9_cam_vec; - wire [0:51] entry10_epn_d; - reg [0:51] entry10_epn_q; - wire entry10_xbit_d; - reg entry10_xbit_q; - wire [0:2] entry10_size_d; - reg [0:2] entry10_size_q; - wire entry10_v_d; - reg entry10_v_q; - wire [0:3] entry10_thdid_d; - reg [0:3] entry10_thdid_q; - wire [0:1] entry10_class_d; - reg [0:1] entry10_class_q; - wire [0:1] entry10_extclass_d; - reg [0:1] entry10_extclass_q; - wire entry10_hv_d; - reg entry10_hv_q; - wire entry10_ds_d; - reg entry10_ds_q; - wire [0:7] entry10_pid_d; - reg [0:7] entry10_pid_q; - wire [0:8] entry10_cmpmask_d; - reg [0:8] entry10_cmpmask_q; - wire [0:9] entry10_parity_d; - reg [0:9] entry10_parity_q; - wire [0:1] wr_entry10_sel; - wire entry10_inval; - wire [0:1] entry10_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry10_cam_vec; - wire [0:51] entry11_epn_d; - reg [0:51] entry11_epn_q; - wire entry11_xbit_d; - reg entry11_xbit_q; - wire [0:2] entry11_size_d; - reg [0:2] entry11_size_q; - wire entry11_v_d; - reg entry11_v_q; - wire [0:3] entry11_thdid_d; - reg [0:3] entry11_thdid_q; - wire [0:1] entry11_class_d; - reg [0:1] entry11_class_q; - wire [0:1] entry11_extclass_d; - reg [0:1] entry11_extclass_q; - wire entry11_hv_d; - reg entry11_hv_q; - wire entry11_ds_d; - reg entry11_ds_q; - wire [0:7] entry11_pid_d; - reg [0:7] entry11_pid_q; - wire [0:8] entry11_cmpmask_d; - reg [0:8] entry11_cmpmask_q; - wire [0:9] entry11_parity_d; - reg [0:9] entry11_parity_q; - wire [0:1] wr_entry11_sel; - wire entry11_inval; - wire [0:1] entry11_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry11_cam_vec; - wire [0:51] entry12_epn_d; - reg [0:51] entry12_epn_q; - wire entry12_xbit_d; - reg entry12_xbit_q; - wire [0:2] entry12_size_d; - reg [0:2] entry12_size_q; - wire entry12_v_d; - reg entry12_v_q; - wire [0:3] entry12_thdid_d; - reg [0:3] entry12_thdid_q; - wire [0:1] entry12_class_d; - reg [0:1] entry12_class_q; - wire [0:1] entry12_extclass_d; - reg [0:1] entry12_extclass_q; - wire entry12_hv_d; - reg entry12_hv_q; - wire entry12_ds_d; - reg entry12_ds_q; - wire [0:7] entry12_pid_d; - reg [0:7] entry12_pid_q; - wire [0:8] entry12_cmpmask_d; - reg [0:8] entry12_cmpmask_q; - wire [0:9] entry12_parity_d; - reg [0:9] entry12_parity_q; - wire [0:1] wr_entry12_sel; - wire entry12_inval; - wire [0:1] entry12_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry12_cam_vec; - wire [0:51] entry13_epn_d; - reg [0:51] entry13_epn_q; - wire entry13_xbit_d; - reg entry13_xbit_q; - wire [0:2] entry13_size_d; - reg [0:2] entry13_size_q; - wire entry13_v_d; - reg entry13_v_q; - wire [0:3] entry13_thdid_d; - reg [0:3] entry13_thdid_q; - wire [0:1] entry13_class_d; - reg [0:1] entry13_class_q; - wire [0:1] entry13_extclass_d; - reg [0:1] entry13_extclass_q; - wire entry13_hv_d; - reg entry13_hv_q; - wire entry13_ds_d; - reg entry13_ds_q; - wire [0:7] entry13_pid_d; - reg [0:7] entry13_pid_q; - wire [0:8] entry13_cmpmask_d; - reg [0:8] entry13_cmpmask_q; - wire [0:9] entry13_parity_d; - reg [0:9] entry13_parity_q; - wire [0:1] wr_entry13_sel; - wire entry13_inval; - wire [0:1] entry13_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry13_cam_vec; - wire [0:51] entry14_epn_d; - reg [0:51] entry14_epn_q; - wire entry14_xbit_d; - reg entry14_xbit_q; - wire [0:2] entry14_size_d; - reg [0:2] entry14_size_q; - wire entry14_v_d; - reg entry14_v_q; - wire [0:3] entry14_thdid_d; - reg [0:3] entry14_thdid_q; - wire [0:1] entry14_class_d; - reg [0:1] entry14_class_q; - wire [0:1] entry14_extclass_d; - reg [0:1] entry14_extclass_q; - wire entry14_hv_d; - reg entry14_hv_q; - wire entry14_ds_d; - reg entry14_ds_q; - wire [0:7] entry14_pid_d; - reg [0:7] entry14_pid_q; - wire [0:8] entry14_cmpmask_d; - reg [0:8] entry14_cmpmask_q; - wire [0:9] entry14_parity_d; - reg [0:9] entry14_parity_q; - wire [0:1] wr_entry14_sel; - wire entry14_inval; - wire [0:1] entry14_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry14_cam_vec; - wire [0:51] entry15_epn_d; - reg [0:51] entry15_epn_q; - wire entry15_xbit_d; - reg entry15_xbit_q; - wire [0:2] entry15_size_d; - reg [0:2] entry15_size_q; - wire entry15_v_d; - reg entry15_v_q; - wire [0:3] entry15_thdid_d; - reg [0:3] entry15_thdid_q; - wire [0:1] entry15_class_d; - reg [0:1] entry15_class_q; - wire [0:1] entry15_extclass_d; - reg [0:1] entry15_extclass_q; - wire entry15_hv_d; - reg entry15_hv_q; - wire entry15_ds_d; - reg entry15_ds_q; - wire [0:7] entry15_pid_d; - reg [0:7] entry15_pid_q; - wire [0:8] entry15_cmpmask_d; - reg [0:8] entry15_cmpmask_q; - wire [0:9] entry15_parity_d; - reg [0:9] entry15_parity_q; - wire [0:1] wr_entry15_sel; - wire entry15_inval; - wire [0:1] entry15_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry15_cam_vec; - wire [0:51] entry16_epn_d; - reg [0:51] entry16_epn_q; - wire entry16_xbit_d; - reg entry16_xbit_q; - wire [0:2] entry16_size_d; - reg [0:2] entry16_size_q; - wire entry16_v_d; - reg entry16_v_q; - wire [0:3] entry16_thdid_d; - reg [0:3] entry16_thdid_q; - wire [0:1] entry16_class_d; - reg [0:1] entry16_class_q; - wire [0:1] entry16_extclass_d; - reg [0:1] entry16_extclass_q; - wire entry16_hv_d; - reg entry16_hv_q; - wire entry16_ds_d; - reg entry16_ds_q; - wire [0:7] entry16_pid_d; - reg [0:7] entry16_pid_q; - wire [0:8] entry16_cmpmask_d; - reg [0:8] entry16_cmpmask_q; - wire [0:9] entry16_parity_d; - reg [0:9] entry16_parity_q; - wire [0:1] wr_entry16_sel; - wire entry16_inval; - wire [0:1] entry16_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry16_cam_vec; - wire [0:51] entry17_epn_d; - reg [0:51] entry17_epn_q; - wire entry17_xbit_d; - reg entry17_xbit_q; - wire [0:2] entry17_size_d; - reg [0:2] entry17_size_q; - wire entry17_v_d; - reg entry17_v_q; - wire [0:3] entry17_thdid_d; - reg [0:3] entry17_thdid_q; - wire [0:1] entry17_class_d; - reg [0:1] entry17_class_q; - wire [0:1] entry17_extclass_d; - reg [0:1] entry17_extclass_q; - wire entry17_hv_d; - reg entry17_hv_q; - wire entry17_ds_d; - reg entry17_ds_q; - wire [0:7] entry17_pid_d; - reg [0:7] entry17_pid_q; - wire [0:8] entry17_cmpmask_d; - reg [0:8] entry17_cmpmask_q; - wire [0:9] entry17_parity_d; - reg [0:9] entry17_parity_q; - wire [0:1] wr_entry17_sel; - wire entry17_inval; - wire [0:1] entry17_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry17_cam_vec; - wire [0:51] entry18_epn_d; - reg [0:51] entry18_epn_q; - wire entry18_xbit_d; - reg entry18_xbit_q; - wire [0:2] entry18_size_d; - reg [0:2] entry18_size_q; - wire entry18_v_d; - reg entry18_v_q; - wire [0:3] entry18_thdid_d; - reg [0:3] entry18_thdid_q; - wire [0:1] entry18_class_d; - reg [0:1] entry18_class_q; - wire [0:1] entry18_extclass_d; - reg [0:1] entry18_extclass_q; - wire entry18_hv_d; - reg entry18_hv_q; - wire entry18_ds_d; - reg entry18_ds_q; - wire [0:7] entry18_pid_d; - reg [0:7] entry18_pid_q; - wire [0:8] entry18_cmpmask_d; - reg [0:8] entry18_cmpmask_q; - wire [0:9] entry18_parity_d; - reg [0:9] entry18_parity_q; - wire [0:1] wr_entry18_sel; - wire entry18_inval; - wire [0:1] entry18_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry18_cam_vec; - wire [0:51] entry19_epn_d; - reg [0:51] entry19_epn_q; - wire entry19_xbit_d; - reg entry19_xbit_q; - wire [0:2] entry19_size_d; - reg [0:2] entry19_size_q; - wire entry19_v_d; - reg entry19_v_q; - wire [0:3] entry19_thdid_d; - reg [0:3] entry19_thdid_q; - wire [0:1] entry19_class_d; - reg [0:1] entry19_class_q; - wire [0:1] entry19_extclass_d; - reg [0:1] entry19_extclass_q; - wire entry19_hv_d; - reg entry19_hv_q; - wire entry19_ds_d; - reg entry19_ds_q; - wire [0:7] entry19_pid_d; - reg [0:7] entry19_pid_q; - wire [0:8] entry19_cmpmask_d; - reg [0:8] entry19_cmpmask_q; - wire [0:9] entry19_parity_d; - reg [0:9] entry19_parity_q; - wire [0:1] wr_entry19_sel; - wire entry19_inval; - wire [0:1] entry19_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry19_cam_vec; - wire [0:51] entry20_epn_d; - reg [0:51] entry20_epn_q; - wire entry20_xbit_d; - reg entry20_xbit_q; - wire [0:2] entry20_size_d; - reg [0:2] entry20_size_q; - wire entry20_v_d; - reg entry20_v_q; - wire [0:3] entry20_thdid_d; - reg [0:3] entry20_thdid_q; - wire [0:1] entry20_class_d; - reg [0:1] entry20_class_q; - wire [0:1] entry20_extclass_d; - reg [0:1] entry20_extclass_q; - wire entry20_hv_d; - reg entry20_hv_q; - wire entry20_ds_d; - reg entry20_ds_q; - wire [0:7] entry20_pid_d; - reg [0:7] entry20_pid_q; - wire [0:8] entry20_cmpmask_d; - reg [0:8] entry20_cmpmask_q; - wire [0:9] entry20_parity_d; - reg [0:9] entry20_parity_q; - wire [0:1] wr_entry20_sel; - wire entry20_inval; - wire [0:1] entry20_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry20_cam_vec; - wire [0:51] entry21_epn_d; - reg [0:51] entry21_epn_q; - wire entry21_xbit_d; - reg entry21_xbit_q; - wire [0:2] entry21_size_d; - reg [0:2] entry21_size_q; - wire entry21_v_d; - reg entry21_v_q; - wire [0:3] entry21_thdid_d; - reg [0:3] entry21_thdid_q; - wire [0:1] entry21_class_d; - reg [0:1] entry21_class_q; - wire [0:1] entry21_extclass_d; - reg [0:1] entry21_extclass_q; - wire entry21_hv_d; - reg entry21_hv_q; - wire entry21_ds_d; - reg entry21_ds_q; - wire [0:7] entry21_pid_d; - reg [0:7] entry21_pid_q; - wire [0:8] entry21_cmpmask_d; - reg [0:8] entry21_cmpmask_q; - wire [0:9] entry21_parity_d; - reg [0:9] entry21_parity_q; - wire [0:1] wr_entry21_sel; - wire entry21_inval; - wire [0:1] entry21_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry21_cam_vec; - wire [0:51] entry22_epn_d; - reg [0:51] entry22_epn_q; - wire entry22_xbit_d; - reg entry22_xbit_q; - wire [0:2] entry22_size_d; - reg [0:2] entry22_size_q; - wire entry22_v_d; - reg entry22_v_q; - wire [0:3] entry22_thdid_d; - reg [0:3] entry22_thdid_q; - wire [0:1] entry22_class_d; - reg [0:1] entry22_class_q; - wire [0:1] entry22_extclass_d; - reg [0:1] entry22_extclass_q; - wire entry22_hv_d; - reg entry22_hv_q; - wire entry22_ds_d; - reg entry22_ds_q; - wire [0:7] entry22_pid_d; - reg [0:7] entry22_pid_q; - wire [0:8] entry22_cmpmask_d; - reg [0:8] entry22_cmpmask_q; - wire [0:9] entry22_parity_d; - reg [0:9] entry22_parity_q; - wire [0:1] wr_entry22_sel; - wire entry22_inval; - wire [0:1] entry22_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry22_cam_vec; - wire [0:51] entry23_epn_d; - reg [0:51] entry23_epn_q; - wire entry23_xbit_d; - reg entry23_xbit_q; - wire [0:2] entry23_size_d; - reg [0:2] entry23_size_q; - wire entry23_v_d; - reg entry23_v_q; - wire [0:3] entry23_thdid_d; - reg [0:3] entry23_thdid_q; - wire [0:1] entry23_class_d; - reg [0:1] entry23_class_q; - wire [0:1] entry23_extclass_d; - reg [0:1] entry23_extclass_q; - wire entry23_hv_d; - reg entry23_hv_q; - wire entry23_ds_d; - reg entry23_ds_q; - wire [0:7] entry23_pid_d; - reg [0:7] entry23_pid_q; - wire [0:8] entry23_cmpmask_d; - reg [0:8] entry23_cmpmask_q; - wire [0:9] entry23_parity_d; - reg [0:9] entry23_parity_q; - wire [0:1] wr_entry23_sel; - wire entry23_inval; - wire [0:1] entry23_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry23_cam_vec; - wire [0:51] entry24_epn_d; - reg [0:51] entry24_epn_q; - wire entry24_xbit_d; - reg entry24_xbit_q; - wire [0:2] entry24_size_d; - reg [0:2] entry24_size_q; - wire entry24_v_d; - reg entry24_v_q; - wire [0:3] entry24_thdid_d; - reg [0:3] entry24_thdid_q; - wire [0:1] entry24_class_d; - reg [0:1] entry24_class_q; - wire [0:1] entry24_extclass_d; - reg [0:1] entry24_extclass_q; - wire entry24_hv_d; - reg entry24_hv_q; - wire entry24_ds_d; - reg entry24_ds_q; - wire [0:7] entry24_pid_d; - reg [0:7] entry24_pid_q; - wire [0:8] entry24_cmpmask_d; - reg [0:8] entry24_cmpmask_q; - wire [0:9] entry24_parity_d; - reg [0:9] entry24_parity_q; - wire [0:1] wr_entry24_sel; - wire entry24_inval; - wire [0:1] entry24_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry24_cam_vec; - wire [0:51] entry25_epn_d; - reg [0:51] entry25_epn_q; - wire entry25_xbit_d; - reg entry25_xbit_q; - wire [0:2] entry25_size_d; - reg [0:2] entry25_size_q; - wire entry25_v_d; - reg entry25_v_q; - wire [0:3] entry25_thdid_d; - reg [0:3] entry25_thdid_q; - wire [0:1] entry25_class_d; - reg [0:1] entry25_class_q; - wire [0:1] entry25_extclass_d; - reg [0:1] entry25_extclass_q; - wire entry25_hv_d; - reg entry25_hv_q; - wire entry25_ds_d; - reg entry25_ds_q; - wire [0:7] entry25_pid_d; - reg [0:7] entry25_pid_q; - wire [0:8] entry25_cmpmask_d; - reg [0:8] entry25_cmpmask_q; - wire [0:9] entry25_parity_d; - reg [0:9] entry25_parity_q; - wire [0:1] wr_entry25_sel; - wire entry25_inval; - wire [0:1] entry25_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry25_cam_vec; - wire [0:51] entry26_epn_d; - reg [0:51] entry26_epn_q; - wire entry26_xbit_d; - reg entry26_xbit_q; - wire [0:2] entry26_size_d; - reg [0:2] entry26_size_q; - wire entry26_v_d; - reg entry26_v_q; - wire [0:3] entry26_thdid_d; - reg [0:3] entry26_thdid_q; - wire [0:1] entry26_class_d; - reg [0:1] entry26_class_q; - wire [0:1] entry26_extclass_d; - reg [0:1] entry26_extclass_q; - wire entry26_hv_d; - reg entry26_hv_q; - wire entry26_ds_d; - reg entry26_ds_q; - wire [0:7] entry26_pid_d; - reg [0:7] entry26_pid_q; - wire [0:8] entry26_cmpmask_d; - reg [0:8] entry26_cmpmask_q; - wire [0:9] entry26_parity_d; - reg [0:9] entry26_parity_q; - wire [0:1] wr_entry26_sel; - wire entry26_inval; - wire [0:1] entry26_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry26_cam_vec; - wire [0:51] entry27_epn_d; - reg [0:51] entry27_epn_q; - wire entry27_xbit_d; - reg entry27_xbit_q; - wire [0:2] entry27_size_d; - reg [0:2] entry27_size_q; - wire entry27_v_d; - reg entry27_v_q; - wire [0:3] entry27_thdid_d; - reg [0:3] entry27_thdid_q; - wire [0:1] entry27_class_d; - reg [0:1] entry27_class_q; - wire [0:1] entry27_extclass_d; - reg [0:1] entry27_extclass_q; - wire entry27_hv_d; - reg entry27_hv_q; - wire entry27_ds_d; - reg entry27_ds_q; - wire [0:7] entry27_pid_d; - reg [0:7] entry27_pid_q; - wire [0:8] entry27_cmpmask_d; - reg [0:8] entry27_cmpmask_q; - wire [0:9] entry27_parity_d; - reg [0:9] entry27_parity_q; - wire [0:1] wr_entry27_sel; - wire entry27_inval; - wire [0:1] entry27_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry27_cam_vec; - wire [0:51] entry28_epn_d; - reg [0:51] entry28_epn_q; - wire entry28_xbit_d; - reg entry28_xbit_q; - wire [0:2] entry28_size_d; - reg [0:2] entry28_size_q; - wire entry28_v_d; - reg entry28_v_q; - wire [0:3] entry28_thdid_d; - reg [0:3] entry28_thdid_q; - wire [0:1] entry28_class_d; - reg [0:1] entry28_class_q; - wire [0:1] entry28_extclass_d; - reg [0:1] entry28_extclass_q; - wire entry28_hv_d; - reg entry28_hv_q; - wire entry28_ds_d; - reg entry28_ds_q; - wire [0:7] entry28_pid_d; - reg [0:7] entry28_pid_q; - wire [0:8] entry28_cmpmask_d; - reg [0:8] entry28_cmpmask_q; - wire [0:9] entry28_parity_d; - reg [0:9] entry28_parity_q; - wire [0:1] wr_entry28_sel; - wire entry28_inval; - wire [0:1] entry28_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry28_cam_vec; - wire [0:51] entry29_epn_d; - reg [0:51] entry29_epn_q; - wire entry29_xbit_d; - reg entry29_xbit_q; - wire [0:2] entry29_size_d; - reg [0:2] entry29_size_q; - wire entry29_v_d; - reg entry29_v_q; - wire [0:3] entry29_thdid_d; - reg [0:3] entry29_thdid_q; - wire [0:1] entry29_class_d; - reg [0:1] entry29_class_q; - wire [0:1] entry29_extclass_d; - reg [0:1] entry29_extclass_q; - wire entry29_hv_d; - reg entry29_hv_q; - wire entry29_ds_d; - reg entry29_ds_q; - wire [0:7] entry29_pid_d; - reg [0:7] entry29_pid_q; - wire [0:8] entry29_cmpmask_d; - reg [0:8] entry29_cmpmask_q; - wire [0:9] entry29_parity_d; - reg [0:9] entry29_parity_q; - wire [0:1] wr_entry29_sel; - wire entry29_inval; - wire [0:1] entry29_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry29_cam_vec; - wire [0:51] entry30_epn_d; - reg [0:51] entry30_epn_q; - wire entry30_xbit_d; - reg entry30_xbit_q; - wire [0:2] entry30_size_d; - reg [0:2] entry30_size_q; - wire entry30_v_d; - reg entry30_v_q; - wire [0:3] entry30_thdid_d; - reg [0:3] entry30_thdid_q; - wire [0:1] entry30_class_d; - reg [0:1] entry30_class_q; - wire [0:1] entry30_extclass_d; - reg [0:1] entry30_extclass_q; - wire entry30_hv_d; - reg entry30_hv_q; - wire entry30_ds_d; - reg entry30_ds_q; - wire [0:7] entry30_pid_d; - reg [0:7] entry30_pid_q; - wire [0:8] entry30_cmpmask_d; - reg [0:8] entry30_cmpmask_q; - wire [0:9] entry30_parity_d; - reg [0:9] entry30_parity_q; - wire [0:1] wr_entry30_sel; - wire entry30_inval; - wire [0:1] entry30_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry30_cam_vec; - wire [0:51] entry31_epn_d; - reg [0:51] entry31_epn_q; - wire entry31_xbit_d; - reg entry31_xbit_q; - wire [0:2] entry31_size_d; - reg [0:2] entry31_size_q; - wire entry31_v_d; - reg entry31_v_q; - wire [0:3] entry31_thdid_d; - reg [0:3] entry31_thdid_q; - wire [0:1] entry31_class_d; - reg [0:1] entry31_class_q; - wire [0:1] entry31_extclass_d; - reg [0:1] entry31_extclass_q; - wire entry31_hv_d; - reg entry31_hv_q; - wire entry31_ds_d; - reg entry31_ds_q; - wire [0:7] entry31_pid_d; - reg [0:7] entry31_pid_q; - wire [0:8] entry31_cmpmask_d; - reg [0:8] entry31_cmpmask_q; - wire [0:9] entry31_parity_d; - reg [0:9] entry31_parity_q; - wire [0:1] wr_entry31_sel; - wire entry31_inval; - wire [0:1] entry31_v_muxsel; - wire [0:CAM_DATA_WIDTH-1] entry31_cam_vec; - wire [0:5] cam_cmp_data_muxsel; - wire [0:5] rd_cam_data_muxsel; - wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_np1; - wire [0:ARRAY_DATA_WIDTH-1] array_cmp_data_np1; - wire [0:72] wr_array_data_bram; - wire [0:72] rd_array_data_d_std; - wire [0:55] array_cmp_data_bram_std; - wire [66:72] array_cmp_data_bramp_std; - - // latch signals - wire [0:ARRAY_DATA_WIDTH-1] rd_array_data_d; - reg [0:ARRAY_DATA_WIDTH-1] rd_array_data_q; - wire [0:CAM_DATA_WIDTH-1] cam_cmp_data_d; - reg [0:CAM_DATA_WIDTH-1] cam_cmp_data_q; - wire [0:9] cam_cmp_parity_d; - reg [0:9] cam_cmp_parity_q; - wire [0:CAM_DATA_WIDTH-1] rd_cam_data_d; - reg [0:CAM_DATA_WIDTH-1] rd_cam_data_q; - wire [0:NUM_ENTRY-1] entry_match_d; - reg [0:NUM_ENTRY-1] entry_match_q; - wire [0:NUM_ENTRY-1] match_vec; - wire [0:NUM_ENTRY_LOG2-1] cam_hit_entry_d; - reg [0:NUM_ENTRY_LOG2-1] cam_hit_entry_q; - wire cam_hit_d; - reg cam_hit_q; - wire toggle_d; - reg toggle_q; - wire toggle2x_d; - reg toggle2x_q; - (* analysis_not_referenced="true" *) - wire unused; - - // sim array - reg [0:62] mem[0:31]; - - integer i; - initial begin - for (i = 0; i < 32; i = i + 1) - mem[i] = 0; - end - - //wtf:icarus $dumpvars cannot dump a vpiMemory - generate - genvar j; - for (j = 0; j < 32; j=j+1) begin: loc - wire [0:62] dat; - assign dat = mem[j][0:62]; //wtf split into fields someday - end - endgenerate - - assign clk = nclk[0]; - - always @(posedge clk) - begin: rlatch - sreset_q <= nclk[1]; - end - - always @(posedge clk) begin: slatch - if (sreset_q == 1'b1) begin - cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; - cam_cmp_parity_q <= 10'b0; - rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; - rd_array_data_q <= {ARRAY_DATA_WIDTH{1'b0}}; - entry_match_q <= {NUM_ENTRY{1'b0}}; - cam_hit_entry_q <= {NUM_ENTRY_LOG2{1'b0}}; - cam_hit_q <= 1'b0; - comp_addr_np1_q <= {RPN_WIDTH{1'b0}}; - rpn_np2_q <= {RPN_WIDTH{1'b0}}; - attr_np2_q <= 21'b0; - entry0_size_q <= 3'b0; - entry0_xbit_q <= 1'b0; - entry0_epn_q <= 52'b0; - entry0_class_q <= 2'b0; - entry0_extclass_q <= 2'b0; - entry0_hv_q <= 1'b0; - entry0_ds_q <= 1'b0; - entry0_thdid_q <= 4'b0; - entry0_pid_q <= 8'b0; - entry0_v_q <= 1'b0; - entry0_parity_q <= 10'b0; - entry0_cmpmask_q <= 9'b0; - entry1_size_q <= 3'b0; - entry1_xbit_q <= 1'b0; - entry1_epn_q <= 52'b0; - entry1_class_q <= 2'b0; - entry1_extclass_q <= 2'b0; - entry1_hv_q <= 1'b0; - entry1_ds_q <= 1'b0; - entry1_thdid_q <= 4'b0; - entry1_pid_q <= 8'b0; - entry1_v_q <= 1'b0; - entry1_parity_q <= 10'b0; - entry1_cmpmask_q <= 9'b0; - entry2_size_q <= 3'b0; - entry2_xbit_q <= 1'b0; - entry2_epn_q <= 52'b0; - entry2_class_q <= 2'b0; - entry2_extclass_q <= 2'b0; - entry2_hv_q <= 1'b0; - entry2_ds_q <= 1'b0; - entry2_thdid_q <= 4'b0; - entry2_pid_q <= 8'b0; - entry2_v_q <= 1'b0; - entry2_parity_q <= 10'b0; - entry2_cmpmask_q <= 9'b0; - entry3_size_q <= 3'b0; - entry3_xbit_q <= 1'b0; - entry3_epn_q <= 52'b0; - entry3_class_q <= 2'b0; - entry3_extclass_q <= 2'b0; - entry3_hv_q <= 1'b0; - entry3_ds_q <= 1'b0; - entry3_thdid_q <= 4'b0; - entry3_pid_q <= 8'b0; - entry3_v_q <= 1'b0; - entry3_parity_q <= 10'b0; - entry3_cmpmask_q <= 9'b0; - entry4_size_q <= 3'b0; - entry4_xbit_q <= 1'b0; - entry4_epn_q <= 52'b0; - entry4_class_q <= 2'b0; - entry4_extclass_q <= 2'b0; - entry4_hv_q <= 1'b0; - entry4_ds_q <= 1'b0; - entry4_thdid_q <= 4'b0; - entry4_pid_q <= 8'b0; - entry4_v_q <= 1'b0; - entry4_parity_q <= 10'b0; - entry4_cmpmask_q <= 9'b0; - entry5_size_q <= 3'b0; - entry5_xbit_q <= 1'b0; - entry5_epn_q <= 52'b0; - entry5_class_q <= 2'b0; - entry5_extclass_q <= 2'b0; - entry5_hv_q <= 1'b0; - entry5_ds_q <= 1'b0; - entry5_thdid_q <= 4'b0; - entry5_pid_q <= 8'b0; - entry5_v_q <= 1'b0; - entry5_parity_q <= 10'b0; - entry5_cmpmask_q <= 9'b0; - entry6_size_q <= 3'b0; - entry6_xbit_q <= 1'b0; - entry6_epn_q <= 52'b0; - entry6_class_q <= 2'b0; - entry6_extclass_q <= 2'b0; - entry6_hv_q <= 1'b0; - entry6_ds_q <= 1'b0; - entry6_thdid_q <= 4'b0; - entry6_pid_q <= 8'b0; - entry6_v_q <= 1'b0; - entry6_parity_q <= 10'b0; - entry6_cmpmask_q <= 9'b0; - entry7_size_q <= 3'b0; - entry7_xbit_q <= 1'b0; - entry7_epn_q <= 52'b0; - entry7_class_q <= 2'b0; - entry7_extclass_q <= 2'b0; - entry7_hv_q <= 1'b0; - entry7_ds_q <= 1'b0; - entry7_thdid_q <= 4'b0; - entry7_pid_q <= 8'b0; - entry7_v_q <= 1'b0; - entry7_parity_q <= 10'b0; - entry7_cmpmask_q <= 9'b0; - entry8_size_q <= 3'b0; - entry8_xbit_q <= 1'b0; - entry8_epn_q <= 52'b0; - entry8_class_q <= 2'b0; - entry8_extclass_q <= 2'b0; - entry8_hv_q <= 1'b0; - entry8_ds_q <= 1'b0; - entry8_thdid_q <= 4'b0; - entry8_pid_q <= 8'b0; - entry8_v_q <= 1'b0; - entry8_parity_q <= 10'b0; - entry8_cmpmask_q <= 9'b0; - entry9_size_q <= 3'b0; - entry9_xbit_q <= 1'b0; - entry9_epn_q <= 52'b0; - entry9_class_q <= 2'b0; - entry9_extclass_q <= 2'b0; - entry9_hv_q <= 1'b0; - entry9_ds_q <= 1'b0; - entry9_thdid_q <= 4'b0; - entry9_pid_q <= 8'b0; - entry9_v_q <= 1'b0; - entry9_parity_q <= 10'b0; - entry9_cmpmask_q <= 9'b0; - entry10_size_q <= 3'b0; - entry10_xbit_q <= 1'b0; - entry10_epn_q <= 52'b0; - entry10_class_q <= 2'b0; - entry10_extclass_q <= 2'b0; - entry10_hv_q <= 1'b0; - entry10_ds_q <= 1'b0; - entry10_thdid_q <= 4'b0; - entry10_pid_q <= 8'b0; - entry10_v_q <= 1'b0; - entry10_parity_q <= 10'b0; - entry10_cmpmask_q <= 9'b0; - entry11_size_q <= 3'b0; - entry11_xbit_q <= 1'b0; - entry11_epn_q <= 52'b0; - entry11_class_q <= 2'b0; - entry11_extclass_q <= 2'b0; - entry11_hv_q <= 1'b0; - entry11_ds_q <= 1'b0; - entry11_thdid_q <= 4'b0; - entry11_pid_q <= 8'b0; - entry11_v_q <= 1'b0; - entry11_parity_q <= 10'b0; - entry11_cmpmask_q <= 9'b0; - entry12_size_q <= 3'b0; - entry12_xbit_q <= 1'b0; - entry12_epn_q <= 52'b0; - entry12_class_q <= 2'b0; - entry12_extclass_q <= 2'b0; - entry12_hv_q <= 1'b0; - entry12_ds_q <= 1'b0; - entry12_thdid_q <= 4'b0; - entry12_pid_q <= 8'b0; - entry12_v_q <= 1'b0; - entry12_parity_q <= 10'b0; - entry12_cmpmask_q <= 9'b0; - entry13_size_q <= 3'b0; - entry13_xbit_q <= 1'b0; - entry13_epn_q <= 52'b0; - entry13_class_q <= 2'b0; - entry13_extclass_q <= 2'b0; - entry13_hv_q <= 1'b0; - entry13_ds_q <= 1'b0; - entry13_thdid_q <= 4'b0; - entry13_pid_q <= 8'b0; - entry13_v_q <= 1'b0; - entry13_parity_q <= 10'b0; - entry13_cmpmask_q <= 9'b0; - entry14_size_q <= 3'b0; - entry14_xbit_q <= 1'b0; - entry14_epn_q <= 52'b0; - entry14_class_q <= 2'b0; - entry14_extclass_q <= 2'b0; - entry14_hv_q <= 1'b0; - entry14_ds_q <= 1'b0; - entry14_thdid_q <= 4'b0; - entry14_pid_q <= 8'b0; - entry14_v_q <= 1'b0; - entry14_parity_q <= 10'b0; - entry14_cmpmask_q <= 9'b0; - entry15_size_q <= 3'b0; - entry15_xbit_q <= 1'b0; - entry15_epn_q <= 52'b0; - entry15_class_q <= 2'b0; - entry15_extclass_q <= 2'b0; - entry15_hv_q <= 1'b0; - entry15_ds_q <= 1'b0; - entry15_thdid_q <= 4'b0; - entry15_pid_q <= 8'b0; - entry15_v_q <= 1'b0; - entry15_parity_q <= 10'b0; - entry15_cmpmask_q <= 9'b0; - entry16_size_q <= 3'b0; - entry16_xbit_q <= 1'b0; - entry16_epn_q <= 52'b0; - entry16_class_q <= 2'b0; - entry16_extclass_q <= 2'b0; - entry16_hv_q <= 1'b0; - entry16_ds_q <= 1'b0; - entry16_thdid_q <= 4'b0; - entry16_pid_q <= 8'b0; - entry16_v_q <= 1'b0; - entry16_parity_q <= 10'b0; - entry16_cmpmask_q <= 9'b0; - entry17_size_q <= 3'b0; - entry17_xbit_q <= 1'b0; - entry17_epn_q <= 52'b0; - entry17_class_q <= 2'b0; - entry17_extclass_q <= 2'b0; - entry17_hv_q <= 1'b0; - entry17_ds_q <= 1'b0; - entry17_thdid_q <= 4'b0; - entry17_pid_q <= 8'b0; - entry17_v_q <= 1'b0; - entry17_parity_q <= 10'b0; - entry17_cmpmask_q <= 9'b0; - entry18_size_q <= 3'b0; - entry18_xbit_q <= 1'b0; - entry18_epn_q <= 52'b0; - entry18_class_q <= 2'b0; - entry18_extclass_q <= 2'b0; - entry18_hv_q <= 1'b0; - entry18_ds_q <= 1'b0; - entry18_thdid_q <= 4'b0; - entry18_pid_q <= 8'b0; - entry18_v_q <= 1'b0; - entry18_parity_q <= 10'b0; - entry18_cmpmask_q <= 9'b0; - entry19_size_q <= 3'b0; - entry19_xbit_q <= 1'b0; - entry19_epn_q <= 52'b0; - entry19_class_q <= 2'b0; - entry19_extclass_q <= 2'b0; - entry19_hv_q <= 1'b0; - entry19_ds_q <= 1'b0; - entry19_thdid_q <= 4'b0; - entry19_pid_q <= 8'b0; - entry19_v_q <= 1'b0; - entry19_parity_q <= 10'b0; - entry19_cmpmask_q <= 9'b0; - entry20_size_q <= 3'b0; - entry20_xbit_q <= 1'b0; - entry20_epn_q <= 52'b0; - entry20_class_q <= 2'b0; - entry20_extclass_q <= 2'b0; - entry20_hv_q <= 1'b0; - entry20_ds_q <= 1'b0; - entry20_thdid_q <= 4'b0; - entry20_pid_q <= 8'b0; - entry20_v_q <= 1'b0; - entry20_parity_q <= 10'b0; - entry20_cmpmask_q <= 9'b0; - entry21_size_q <= 3'b0; - entry21_xbit_q <= 1'b0; - entry21_epn_q <= 52'b0; - entry21_class_q <= 2'b0; - entry21_extclass_q <= 2'b0; - entry21_hv_q <= 1'b0; - entry21_ds_q <= 1'b0; - entry21_thdid_q <= 4'b0; - entry21_pid_q <= 8'b0; - entry21_v_q <= 1'b0; - entry21_parity_q <= 10'b0; - entry21_cmpmask_q <= 9'b0; - entry22_size_q <= 3'b0; - entry22_xbit_q <= 1'b0; - entry22_epn_q <= 52'b0; - entry22_class_q <= 2'b0; - entry22_extclass_q <= 2'b0; - entry22_hv_q <= 1'b0; - entry22_ds_q <= 1'b0; - entry22_thdid_q <= 4'b0; - entry22_pid_q <= 8'b0; - entry22_v_q <= 1'b0; - entry22_parity_q <= 10'b0; - entry22_cmpmask_q <= 9'b0; - entry23_size_q <= 3'b0; - entry23_xbit_q <= 1'b0; - entry23_epn_q <= 52'b0; - entry23_class_q <= 2'b0; - entry23_extclass_q <= 2'b0; - entry23_hv_q <= 1'b0; - entry23_ds_q <= 1'b0; - entry23_thdid_q <= 4'b0; - entry23_pid_q <= 8'b0; - entry23_v_q <= 1'b0; - entry23_parity_q <= 10'b0; - entry23_cmpmask_q <= 9'b0; - entry24_size_q <= 3'b0; - entry24_xbit_q <= 1'b0; - entry24_epn_q <= 52'b0; - entry24_class_q <= 2'b0; - entry24_extclass_q <= 2'b0; - entry24_hv_q <= 1'b0; - entry24_ds_q <= 1'b0; - entry24_thdid_q <= 4'b0; - entry24_pid_q <= 8'b0; - entry24_v_q <= 1'b0; - entry24_parity_q <= 10'b0; - entry24_cmpmask_q <= 9'b0; - entry25_size_q <= 3'b0; - entry25_xbit_q <= 1'b0; - entry25_epn_q <= 52'b0; - entry25_class_q <= 2'b0; - entry25_extclass_q <= 2'b0; - entry25_hv_q <= 1'b0; - entry25_ds_q <= 1'b0; - entry25_thdid_q <= 4'b0; - entry25_pid_q <= 8'b0; - entry25_v_q <= 1'b0; - entry25_parity_q <= 10'b0; - entry25_cmpmask_q <= 9'b0; - entry26_size_q <= 3'b0; - entry26_xbit_q <= 1'b0; - entry26_epn_q <= 52'b0; - entry26_class_q <= 2'b0; - entry26_extclass_q <= 2'b0; - entry26_hv_q <= 1'b0; - entry26_ds_q <= 1'b0; - entry26_thdid_q <= 4'b0; - entry26_pid_q <= 8'b0; - entry26_v_q <= 1'b0; - entry26_parity_q <= 10'b0; - entry26_cmpmask_q <= 9'b0; - entry27_size_q <= 3'b0; - entry27_xbit_q <= 1'b0; - entry27_epn_q <= 52'b0; - entry27_class_q <= 2'b0; - entry27_extclass_q <= 2'b0; - entry27_hv_q <= 1'b0; - entry27_ds_q <= 1'b0; - entry27_thdid_q <= 4'b0; - entry27_pid_q <= 8'b0; - entry27_v_q <= 1'b0; - entry27_parity_q <= 10'b0; - entry27_cmpmask_q <= 9'b0; - entry28_size_q <= 3'b0; - entry28_xbit_q <= 1'b0; - entry28_epn_q <= 52'b0; - entry28_class_q <= 2'b0; - entry28_extclass_q <= 2'b0; - entry28_hv_q <= 1'b0; - entry28_ds_q <= 1'b0; - entry28_thdid_q <= 4'b0; - entry28_pid_q <= 8'b0; - entry28_v_q <= 1'b0; - entry28_parity_q <= 10'b0; - entry28_cmpmask_q <= 9'b0; - entry29_size_q <= 3'b0; - entry29_xbit_q <= 1'b0; - entry29_epn_q <= 52'b0; - entry29_class_q <= 2'b0; - entry29_extclass_q <= 2'b0; - entry29_hv_q <= 1'b0; - entry29_ds_q <= 1'b0; - entry29_thdid_q <= 4'b0; - entry29_pid_q <= 8'b0; - entry29_v_q <= 1'b0; - entry29_parity_q <= 10'b0; - entry29_cmpmask_q <= 9'b0; - entry30_size_q <= 3'b0; - entry30_xbit_q <= 1'b0; - entry30_epn_q <= 52'b0; - entry30_class_q <= 2'b0; - entry30_extclass_q <= 2'b0; - entry30_hv_q <= 1'b0; - entry30_ds_q <= 1'b0; - entry30_thdid_q <= 4'b0; - entry30_pid_q <= 8'b0; - entry30_v_q <= 1'b0; - entry30_parity_q <= 10'b0; - entry30_cmpmask_q <= 9'b0; - entry31_size_q <= 3'b0; - entry31_xbit_q <= 1'b0; - entry31_epn_q <= 52'b0; - entry31_class_q <= 2'b0; - entry31_extclass_q <= 2'b0; - entry31_hv_q <= 1'b0; - entry31_ds_q <= 1'b0; - entry31_thdid_q <= 4'b0; - entry31_pid_q <= 8'b0; - entry31_v_q <= 1'b0; - entry31_parity_q <= 10'b0; - entry31_cmpmask_q <= 9'b0; - end - else - begin - cam_cmp_data_q <= cam_cmp_data_d; - rd_cam_data_q <= rd_cam_data_d; - rd_array_data_q <= rd_array_data_d; - entry_match_q <= entry_match_d; - cam_hit_entry_q <= cam_hit_entry_d; - cam_hit_q <= cam_hit_d; - cam_cmp_parity_q <= cam_cmp_parity_d; - comp_addr_np1_q <= comp_addr_np1_d; - rpn_np2_q <= rpn_np2_d; - attr_np2_q <= attr_np2_d; - entry0_size_q <= entry0_size_d; - entry0_xbit_q <= entry0_xbit_d; - entry0_epn_q <= entry0_epn_d; - entry0_class_q <= entry0_class_d; - entry0_extclass_q <= entry0_extclass_d; - entry0_hv_q <= entry0_hv_d; - entry0_ds_q <= entry0_ds_d; - entry0_thdid_q <= entry0_thdid_d; - entry0_pid_q <= entry0_pid_d; - entry0_v_q <= entry0_v_d; - entry0_parity_q <= entry0_parity_d; - entry0_cmpmask_q <= entry0_cmpmask_d; - entry1_size_q <= entry1_size_d; - entry1_xbit_q <= entry1_xbit_d; - entry1_epn_q <= entry1_epn_d; - entry1_class_q <= entry1_class_d; - entry1_extclass_q <= entry1_extclass_d; - entry1_hv_q <= entry1_hv_d; - entry1_ds_q <= entry1_ds_d; - entry1_thdid_q <= entry1_thdid_d; - entry1_pid_q <= entry1_pid_d; - entry1_v_q <= entry1_v_d; - entry1_parity_q <= entry1_parity_d; - entry1_cmpmask_q <= entry1_cmpmask_d; - entry2_size_q <= entry2_size_d; - entry2_xbit_q <= entry2_xbit_d; - entry2_epn_q <= entry2_epn_d; - entry2_class_q <= entry2_class_d; - entry2_extclass_q <= entry2_extclass_d; - entry2_hv_q <= entry2_hv_d; - entry2_ds_q <= entry2_ds_d; - entry2_thdid_q <= entry2_thdid_d; - entry2_pid_q <= entry2_pid_d; - entry2_v_q <= entry2_v_d; - entry2_parity_q <= entry2_parity_d; - entry2_cmpmask_q <= entry2_cmpmask_d; - entry3_size_q <= entry3_size_d; - entry3_xbit_q <= entry3_xbit_d; - entry3_epn_q <= entry3_epn_d; - entry3_class_q <= entry3_class_d; - entry3_extclass_q <= entry3_extclass_d; - entry3_hv_q <= entry3_hv_d; - entry3_ds_q <= entry3_ds_d; - entry3_thdid_q <= entry3_thdid_d; - entry3_pid_q <= entry3_pid_d; - entry3_v_q <= entry3_v_d; - entry3_parity_q <= entry3_parity_d; - entry3_cmpmask_q <= entry3_cmpmask_d; - entry4_size_q <= entry4_size_d; - entry4_xbit_q <= entry4_xbit_d; - entry4_epn_q <= entry4_epn_d; - entry4_class_q <= entry4_class_d; - entry4_extclass_q <= entry4_extclass_d; - entry4_hv_q <= entry4_hv_d; - entry4_ds_q <= entry4_ds_d; - entry4_thdid_q <= entry4_thdid_d; - entry4_pid_q <= entry4_pid_d; - entry4_v_q <= entry4_v_d; - entry4_parity_q <= entry4_parity_d; - entry4_cmpmask_q <= entry4_cmpmask_d; - entry5_size_q <= entry5_size_d; - entry5_xbit_q <= entry5_xbit_d; - entry5_epn_q <= entry5_epn_d; - entry5_class_q <= entry5_class_d; - entry5_extclass_q <= entry5_extclass_d; - entry5_hv_q <= entry5_hv_d; - entry5_ds_q <= entry5_ds_d; - entry5_thdid_q <= entry5_thdid_d; - entry5_pid_q <= entry5_pid_d; - entry5_v_q <= entry5_v_d; - entry5_parity_q <= entry5_parity_d; - entry5_cmpmask_q <= entry5_cmpmask_d; - entry6_size_q <= entry6_size_d; - entry6_xbit_q <= entry6_xbit_d; - entry6_epn_q <= entry6_epn_d; - entry6_class_q <= entry6_class_d; - entry6_extclass_q <= entry6_extclass_d; - entry6_hv_q <= entry6_hv_d; - entry6_ds_q <= entry6_ds_d; - entry6_thdid_q <= entry6_thdid_d; - entry6_pid_q <= entry6_pid_d; - entry6_v_q <= entry6_v_d; - entry6_parity_q <= entry6_parity_d; - entry6_cmpmask_q <= entry6_cmpmask_d; - entry7_size_q <= entry7_size_d; - entry7_xbit_q <= entry7_xbit_d; - entry7_epn_q <= entry7_epn_d; - entry7_class_q <= entry7_class_d; - entry7_extclass_q <= entry7_extclass_d; - entry7_hv_q <= entry7_hv_d; - entry7_ds_q <= entry7_ds_d; - entry7_thdid_q <= entry7_thdid_d; - entry7_pid_q <= entry7_pid_d; - entry7_v_q <= entry7_v_d; - entry7_parity_q <= entry7_parity_d; - entry7_cmpmask_q <= entry7_cmpmask_d; - entry8_size_q <= entry8_size_d; - entry8_xbit_q <= entry8_xbit_d; - entry8_epn_q <= entry8_epn_d; - entry8_class_q <= entry8_class_d; - entry8_extclass_q <= entry8_extclass_d; - entry8_hv_q <= entry8_hv_d; - entry8_ds_q <= entry8_ds_d; - entry8_thdid_q <= entry8_thdid_d; - entry8_pid_q <= entry8_pid_d; - entry8_v_q <= entry8_v_d; - entry8_parity_q <= entry8_parity_d; - entry8_cmpmask_q <= entry8_cmpmask_d; - entry9_size_q <= entry9_size_d; - entry9_xbit_q <= entry9_xbit_d; - entry9_epn_q <= entry9_epn_d; - entry9_class_q <= entry9_class_d; - entry9_extclass_q <= entry9_extclass_d; - entry9_hv_q <= entry9_hv_d; - entry9_ds_q <= entry9_ds_d; - entry9_thdid_q <= entry9_thdid_d; - entry9_pid_q <= entry9_pid_d; - entry9_v_q <= entry9_v_d; - entry9_parity_q <= entry9_parity_d; - entry9_cmpmask_q <= entry9_cmpmask_d; - entry10_size_q <= entry10_size_d; - entry10_xbit_q <= entry10_xbit_d; - entry10_epn_q <= entry10_epn_d; - entry10_class_q <= entry10_class_d; - entry10_extclass_q <= entry10_extclass_d; - entry10_hv_q <= entry10_hv_d; - entry10_ds_q <= entry10_ds_d; - entry10_thdid_q <= entry10_thdid_d; - entry10_pid_q <= entry10_pid_d; - entry10_v_q <= entry10_v_d; - entry10_parity_q <= entry10_parity_d; - entry10_cmpmask_q <= entry10_cmpmask_d; - entry11_size_q <= entry11_size_d; - entry11_xbit_q <= entry11_xbit_d; - entry11_epn_q <= entry11_epn_d; - entry11_class_q <= entry11_class_d; - entry11_extclass_q <= entry11_extclass_d; - entry11_hv_q <= entry11_hv_d; - entry11_ds_q <= entry11_ds_d; - entry11_thdid_q <= entry11_thdid_d; - entry11_pid_q <= entry11_pid_d; - entry11_v_q <= entry11_v_d; - entry11_parity_q <= entry11_parity_d; - entry11_cmpmask_q <= entry11_cmpmask_d; - entry12_size_q <= entry12_size_d; - entry12_xbit_q <= entry12_xbit_d; - entry12_epn_q <= entry12_epn_d; - entry12_class_q <= entry12_class_d; - entry12_extclass_q <= entry12_extclass_d; - entry12_hv_q <= entry12_hv_d; - entry12_ds_q <= entry12_ds_d; - entry12_thdid_q <= entry12_thdid_d; - entry12_pid_q <= entry12_pid_d; - entry12_v_q <= entry12_v_d; - entry12_parity_q <= entry12_parity_d; - entry12_cmpmask_q <= entry12_cmpmask_d; - entry13_size_q <= entry13_size_d; - entry13_xbit_q <= entry13_xbit_d; - entry13_epn_q <= entry13_epn_d; - entry13_class_q <= entry13_class_d; - entry13_extclass_q <= entry13_extclass_d; - entry13_hv_q <= entry13_hv_d; - entry13_ds_q <= entry13_ds_d; - entry13_thdid_q <= entry13_thdid_d; - entry13_pid_q <= entry13_pid_d; - entry13_v_q <= entry13_v_d; - entry13_parity_q <= entry13_parity_d; - entry13_cmpmask_q <= entry13_cmpmask_d; - entry14_size_q <= entry14_size_d; - entry14_xbit_q <= entry14_xbit_d; - entry14_epn_q <= entry14_epn_d; - entry14_class_q <= entry14_class_d; - entry14_extclass_q <= entry14_extclass_d; - entry14_hv_q <= entry14_hv_d; - entry14_ds_q <= entry14_ds_d; - entry14_thdid_q <= entry14_thdid_d; - entry14_pid_q <= entry14_pid_d; - entry14_v_q <= entry14_v_d; - entry14_parity_q <= entry14_parity_d; - entry14_cmpmask_q <= entry14_cmpmask_d; - entry15_size_q <= entry15_size_d; - entry15_xbit_q <= entry15_xbit_d; - entry15_epn_q <= entry15_epn_d; - entry15_class_q <= entry15_class_d; - entry15_extclass_q <= entry15_extclass_d; - entry15_hv_q <= entry15_hv_d; - entry15_ds_q <= entry15_ds_d; - entry15_thdid_q <= entry15_thdid_d; - entry15_pid_q <= entry15_pid_d; - entry15_v_q <= entry15_v_d; - entry15_parity_q <= entry15_parity_d; - entry15_cmpmask_q <= entry15_cmpmask_d; - entry16_size_q <= entry16_size_d; - entry16_xbit_q <= entry16_xbit_d; - entry16_epn_q <= entry16_epn_d; - entry16_class_q <= entry16_class_d; - entry16_extclass_q <= entry16_extclass_d; - entry16_hv_q <= entry16_hv_d; - entry16_ds_q <= entry16_ds_d; - entry16_thdid_q <= entry16_thdid_d; - entry16_pid_q <= entry16_pid_d; - entry16_v_q <= entry16_v_d; - entry16_parity_q <= entry16_parity_d; - entry16_cmpmask_q <= entry16_cmpmask_d; - entry17_size_q <= entry17_size_d; - entry17_xbit_q <= entry17_xbit_d; - entry17_epn_q <= entry17_epn_d; - entry17_class_q <= entry17_class_d; - entry17_extclass_q <= entry17_extclass_d; - entry17_hv_q <= entry17_hv_d; - entry17_ds_q <= entry17_ds_d; - entry17_thdid_q <= entry17_thdid_d; - entry17_pid_q <= entry17_pid_d; - entry17_v_q <= entry17_v_d; - entry17_parity_q <= entry17_parity_d; - entry17_cmpmask_q <= entry17_cmpmask_d; - entry18_size_q <= entry18_size_d; - entry18_xbit_q <= entry18_xbit_d; - entry18_epn_q <= entry18_epn_d; - entry18_class_q <= entry18_class_d; - entry18_extclass_q <= entry18_extclass_d; - entry18_hv_q <= entry18_hv_d; - entry18_ds_q <= entry18_ds_d; - entry18_thdid_q <= entry18_thdid_d; - entry18_pid_q <= entry18_pid_d; - entry18_v_q <= entry18_v_d; - entry18_parity_q <= entry18_parity_d; - entry18_cmpmask_q <= entry18_cmpmask_d; - entry19_size_q <= entry19_size_d; - entry19_xbit_q <= entry19_xbit_d; - entry19_epn_q <= entry19_epn_d; - entry19_class_q <= entry19_class_d; - entry19_extclass_q <= entry19_extclass_d; - entry19_hv_q <= entry19_hv_d; - entry19_ds_q <= entry19_ds_d; - entry19_thdid_q <= entry19_thdid_d; - entry19_pid_q <= entry19_pid_d; - entry19_v_q <= entry19_v_d; - entry19_parity_q <= entry19_parity_d; - entry19_cmpmask_q <= entry19_cmpmask_d; - entry20_size_q <= entry20_size_d; - entry20_xbit_q <= entry20_xbit_d; - entry20_epn_q <= entry20_epn_d; - entry20_class_q <= entry20_class_d; - entry20_extclass_q <= entry20_extclass_d; - entry20_hv_q <= entry20_hv_d; - entry20_ds_q <= entry20_ds_d; - entry20_thdid_q <= entry20_thdid_d; - entry20_pid_q <= entry20_pid_d; - entry20_v_q <= entry20_v_d; - entry20_parity_q <= entry20_parity_d; - entry20_cmpmask_q <= entry20_cmpmask_d; - entry21_size_q <= entry21_size_d; - entry21_xbit_q <= entry21_xbit_d; - entry21_epn_q <= entry21_epn_d; - entry21_class_q <= entry21_class_d; - entry21_extclass_q <= entry21_extclass_d; - entry21_hv_q <= entry21_hv_d; - entry21_ds_q <= entry21_ds_d; - entry21_thdid_q <= entry21_thdid_d; - entry21_pid_q <= entry21_pid_d; - entry21_v_q <= entry21_v_d; - entry21_parity_q <= entry21_parity_d; - entry21_cmpmask_q <= entry21_cmpmask_d; - entry22_size_q <= entry22_size_d; - entry22_xbit_q <= entry22_xbit_d; - entry22_epn_q <= entry22_epn_d; - entry22_class_q <= entry22_class_d; - entry22_extclass_q <= entry22_extclass_d; - entry22_hv_q <= entry22_hv_d; - entry22_ds_q <= entry22_ds_d; - entry22_thdid_q <= entry22_thdid_d; - entry22_pid_q <= entry22_pid_d; - entry22_v_q <= entry22_v_d; - entry22_parity_q <= entry22_parity_d; - entry22_cmpmask_q <= entry22_cmpmask_d; - entry23_size_q <= entry23_size_d; - entry23_xbit_q <= entry23_xbit_d; - entry23_epn_q <= entry23_epn_d; - entry23_class_q <= entry23_class_d; - entry23_extclass_q <= entry23_extclass_d; - entry23_hv_q <= entry23_hv_d; - entry23_ds_q <= entry23_ds_d; - entry23_thdid_q <= entry23_thdid_d; - entry23_pid_q <= entry23_pid_d; - entry23_v_q <= entry23_v_d; - entry23_parity_q <= entry23_parity_d; - entry23_cmpmask_q <= entry23_cmpmask_d; - entry24_size_q <= entry24_size_d; - entry24_xbit_q <= entry24_xbit_d; - entry24_epn_q <= entry24_epn_d; - entry24_class_q <= entry24_class_d; - entry24_extclass_q <= entry24_extclass_d; - entry24_hv_q <= entry24_hv_d; - entry24_ds_q <= entry24_ds_d; - entry24_thdid_q <= entry24_thdid_d; - entry24_pid_q <= entry24_pid_d; - entry24_v_q <= entry24_v_d; - entry24_parity_q <= entry24_parity_d; - entry24_cmpmask_q <= entry24_cmpmask_d; - entry25_size_q <= entry25_size_d; - entry25_xbit_q <= entry25_xbit_d; - entry25_epn_q <= entry25_epn_d; - entry25_class_q <= entry25_class_d; - entry25_extclass_q <= entry25_extclass_d; - entry25_hv_q <= entry25_hv_d; - entry25_ds_q <= entry25_ds_d; - entry25_thdid_q <= entry25_thdid_d; - entry25_pid_q <= entry25_pid_d; - entry25_v_q <= entry25_v_d; - entry25_parity_q <= entry25_parity_d; - entry25_cmpmask_q <= entry25_cmpmask_d; - entry26_size_q <= entry26_size_d; - entry26_xbit_q <= entry26_xbit_d; - entry26_epn_q <= entry26_epn_d; - entry26_class_q <= entry26_class_d; - entry26_extclass_q <= entry26_extclass_d; - entry26_hv_q <= entry26_hv_d; - entry26_ds_q <= entry26_ds_d; - entry26_thdid_q <= entry26_thdid_d; - entry26_pid_q <= entry26_pid_d; - entry26_v_q <= entry26_v_d; - entry26_parity_q <= entry26_parity_d; - entry26_cmpmask_q <= entry26_cmpmask_d; - entry27_size_q <= entry27_size_d; - entry27_xbit_q <= entry27_xbit_d; - entry27_epn_q <= entry27_epn_d; - entry27_class_q <= entry27_class_d; - entry27_extclass_q <= entry27_extclass_d; - entry27_hv_q <= entry27_hv_d; - entry27_ds_q <= entry27_ds_d; - entry27_thdid_q <= entry27_thdid_d; - entry27_pid_q <= entry27_pid_d; - entry27_v_q <= entry27_v_d; - entry27_parity_q <= entry27_parity_d; - entry27_cmpmask_q <= entry27_cmpmask_d; - entry28_size_q <= entry28_size_d; - entry28_xbit_q <= entry28_xbit_d; - entry28_epn_q <= entry28_epn_d; - entry28_class_q <= entry28_class_d; - entry28_extclass_q <= entry28_extclass_d; - entry28_hv_q <= entry28_hv_d; - entry28_ds_q <= entry28_ds_d; - entry28_thdid_q <= entry28_thdid_d; - entry28_pid_q <= entry28_pid_d; - entry28_v_q <= entry28_v_d; - entry28_parity_q <= entry28_parity_d; - entry28_cmpmask_q <= entry28_cmpmask_d; - entry29_size_q <= entry29_size_d; - entry29_xbit_q <= entry29_xbit_d; - entry29_epn_q <= entry29_epn_d; - entry29_class_q <= entry29_class_d; - entry29_extclass_q <= entry29_extclass_d; - entry29_hv_q <= entry29_hv_d; - entry29_ds_q <= entry29_ds_d; - entry29_thdid_q <= entry29_thdid_d; - entry29_pid_q <= entry29_pid_d; - entry29_v_q <= entry29_v_d; - entry29_parity_q <= entry29_parity_d; - entry29_cmpmask_q <= entry29_cmpmask_d; - entry30_size_q <= entry30_size_d; - entry30_xbit_q <= entry30_xbit_d; - entry30_epn_q <= entry30_epn_d; - entry30_class_q <= entry30_class_d; - entry30_extclass_q <= entry30_extclass_d; - entry30_hv_q <= entry30_hv_d; - entry30_ds_q <= entry30_ds_d; - entry30_thdid_q <= entry30_thdid_d; - entry30_pid_q <= entry30_pid_d; - entry30_v_q <= entry30_v_d; - entry30_parity_q <= entry30_parity_d; - entry30_cmpmask_q <= entry30_cmpmask_d; - entry31_size_q <= entry31_size_d; - entry31_xbit_q <= entry31_xbit_d; - entry31_epn_q <= entry31_epn_d; - entry31_class_q <= entry31_class_d; - entry31_extclass_q <= entry31_extclass_d; - entry31_hv_q <= entry31_hv_d; - entry31_ds_q <= entry31_ds_d; - entry31_thdid_q <= entry31_thdid_d; - entry31_pid_q <= entry31_pid_d; - entry31_v_q <= entry31_v_d; - entry31_parity_q <= entry31_parity_d; - entry31_cmpmask_q <= entry31_cmpmask_d; - end - end - - //--------------------------------------------------------------------- - // latch input logic - //--------------------------------------------------------------------- - assign comp_addr_np1_d = comp_addr[52 - RPN_WIDTH:51]; - - assign cam_hit_d = ((match_vec != 32'b00000000000000000000000000000000) & (comp_request == 1'b1)) ? 1'b1 : - 1'b0; - - assign cam_hit_entry_d = (match_vec[0:1] == 2'b01) ? 5'b00001 : - (match_vec[0:2] == 3'b001) ? 5'b00010 : - (match_vec[0:3] == 4'b0001) ? 5'b00011 : - (match_vec[0:4] == 5'b00001) ? 5'b00100 : - (match_vec[0:5] == 6'b000001) ? 5'b00101 : - (match_vec[0:6] == 7'b0000001) ? 5'b00110 : - (match_vec[0:7] == 8'b00000001) ? 5'b00111 : - (match_vec[0:8] == 9'b000000001) ? 5'b01000 : - (match_vec[0:9] == 10'b0000000001) ? 5'b01001 : - (match_vec[0:10] == 11'b00000000001) ? 5'b01010 : - (match_vec[0:11] == 12'b000000000001) ? 5'b01011 : - (match_vec[0:12] == 13'b0000000000001) ? 5'b01100 : - (match_vec[0:13] == 14'b00000000000001) ? 5'b01101 : - (match_vec[0:14] == 15'b000000000000001) ? 5'b01110 : - (match_vec[0:15] == 16'b0000000000000001) ? 5'b01111 : - (match_vec[0:16] == 17'b00000000000000001) ? 5'b10000 : - (match_vec[0:17] == 18'b000000000000000001) ? 5'b10001 : - (match_vec[0:18] == 19'b0000000000000000001) ? 5'b10010 : - (match_vec[0:19] == 20'b00000000000000000001) ? 5'b10011 : - (match_vec[0:20] == 21'b000000000000000000001) ? 5'b10100 : - (match_vec[0:21] == 22'b0000000000000000000001) ? 5'b10101 : - (match_vec[0:22] == 23'b00000000000000000000001) ? 5'b10110 : - (match_vec[0:23] == 24'b000000000000000000000001) ? 5'b10111 : - (match_vec[0:24] == 25'b0000000000000000000000001) ? 5'b11000 : - (match_vec[0:25] == 26'b00000000000000000000000001) ? 5'b11001 : - (match_vec[0:26] == 27'b000000000000000000000000001) ? 5'b11010 : - (match_vec[0:27] == 28'b0000000000000000000000000001) ? 5'b11011 : - (match_vec[0:28] == 29'b00000000000000000000000000001) ? 5'b11100 : - (match_vec[0:29] == 30'b000000000000000000000000000001) ? 5'b11101 : - (match_vec[0:30] == 31'b0000000000000000000000000000001) ? 5'b11110 : - (match_vec[0:31] == 32'b00000000000000000000000000000001) ? 5'b11111 : - 5'b00000; - - assign entry_match_d = ((comp_request == 1'b1)) ? match_vec : - {NUM_ENTRY{1'b0}}; - - // entry write next state logic - assign wr_entry0_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : - 1'b0; - assign wr_entry0_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00000)) ? 1'b1 : - 1'b0; - assign entry0_epn_d[0:31] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry0_epn_q[0:31]; - assign entry0_epn_d[32:51] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry0_epn_q[32:51]; - assign entry0_xbit_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[52] : - entry0_xbit_q; - assign entry0_size_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry0_size_q[0:2]; - assign entry0_class_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry0_class_q[0:1]; - assign entry0_extclass_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry0_extclass_q[0:1]; - assign entry0_hv_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[65] : - entry0_hv_q; - assign entry0_ds_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[66] : - entry0_ds_q; - assign entry0_pid_d = (wr_entry0_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry0_pid_q[0:7]; - assign entry0_cmpmask_d = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry0_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry0_parity_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry0_parity_q[0:3]; - assign entry0_parity_d[4:6] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry0_parity_q[4:6]; - assign entry0_parity_d[7] = (wr_entry0_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry0_parity_q[7]; - assign entry0_parity_d[8] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry0_parity_q[8]; - assign entry0_parity_d[9] = (wr_entry0_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry0_parity_q[9]; - assign wr_entry1_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : - 1'b0; - assign wr_entry1_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00001)) ? 1'b1 : - 1'b0; - assign entry1_epn_d[0:31] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry1_epn_q[0:31]; - assign entry1_epn_d[32:51] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry1_epn_q[32:51]; - assign entry1_xbit_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[52] : - entry1_xbit_q; - assign entry1_size_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry1_size_q[0:2]; - assign entry1_class_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry1_class_q[0:1]; - assign entry1_extclass_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry1_extclass_q[0:1]; - assign entry1_hv_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[65] : - entry1_hv_q; - assign entry1_ds_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[66] : - entry1_ds_q; - assign entry1_pid_d = (wr_entry1_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry1_pid_q[0:7]; - assign entry1_cmpmask_d = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry1_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry1_parity_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry1_parity_q[0:3]; - assign entry1_parity_d[4:6] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry1_parity_q[4:6]; - assign entry1_parity_d[7] = (wr_entry1_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry1_parity_q[7]; - assign entry1_parity_d[8] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry1_parity_q[8]; - assign entry1_parity_d[9] = (wr_entry1_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry1_parity_q[9]; - assign wr_entry2_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : - 1'b0; - assign wr_entry2_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00010)) ? 1'b1 : - 1'b0; - assign entry2_epn_d[0:31] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry2_epn_q[0:31]; - assign entry2_epn_d[32:51] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry2_epn_q[32:51]; - assign entry2_xbit_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[52] : - entry2_xbit_q; - assign entry2_size_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry2_size_q[0:2]; - assign entry2_class_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry2_class_q[0:1]; - assign entry2_extclass_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry2_extclass_q[0:1]; - assign entry2_hv_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[65] : - entry2_hv_q; - assign entry2_ds_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[66] : - entry2_ds_q; - assign entry2_pid_d = (wr_entry2_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry2_pid_q[0:7]; - assign entry2_cmpmask_d = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry2_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry2_parity_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry2_parity_q[0:3]; - assign entry2_parity_d[4:6] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry2_parity_q[4:6]; - assign entry2_parity_d[7] = (wr_entry2_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry2_parity_q[7]; - assign entry2_parity_d[8] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry2_parity_q[8]; - assign entry2_parity_d[9] = (wr_entry2_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry2_parity_q[9]; - assign wr_entry3_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : - 1'b0; - assign wr_entry3_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00011)) ? 1'b1 : - 1'b0; - assign entry3_epn_d[0:31] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry3_epn_q[0:31]; - assign entry3_epn_d[32:51] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry3_epn_q[32:51]; - assign entry3_xbit_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[52] : - entry3_xbit_q; - assign entry3_size_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry3_size_q[0:2]; - assign entry3_class_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry3_class_q[0:1]; - assign entry3_extclass_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry3_extclass_q[0:1]; - assign entry3_hv_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[65] : - entry3_hv_q; - assign entry3_ds_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[66] : - entry3_ds_q; - assign entry3_pid_d = (wr_entry3_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry3_pid_q[0:7]; - assign entry3_cmpmask_d = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry3_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry3_parity_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry3_parity_q[0:3]; - assign entry3_parity_d[4:6] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry3_parity_q[4:6]; - assign entry3_parity_d[7] = (wr_entry3_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry3_parity_q[7]; - assign entry3_parity_d[8] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry3_parity_q[8]; - assign entry3_parity_d[9] = (wr_entry3_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry3_parity_q[9]; - assign wr_entry4_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : - 1'b0; - assign wr_entry4_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00100)) ? 1'b1 : - 1'b0; - assign entry4_epn_d[0:31] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry4_epn_q[0:31]; - assign entry4_epn_d[32:51] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry4_epn_q[32:51]; - assign entry4_xbit_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[52] : - entry4_xbit_q; - assign entry4_size_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry4_size_q[0:2]; - assign entry4_class_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry4_class_q[0:1]; - assign entry4_extclass_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry4_extclass_q[0:1]; - assign entry4_hv_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[65] : - entry4_hv_q; - assign entry4_ds_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[66] : - entry4_ds_q; - assign entry4_pid_d = (wr_entry4_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry4_pid_q[0:7]; - assign entry4_cmpmask_d = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry4_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry4_parity_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry4_parity_q[0:3]; - assign entry4_parity_d[4:6] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry4_parity_q[4:6]; - assign entry4_parity_d[7] = (wr_entry4_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry4_parity_q[7]; - assign entry4_parity_d[8] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry4_parity_q[8]; - assign entry4_parity_d[9] = (wr_entry4_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry4_parity_q[9]; - assign wr_entry5_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : - 1'b0; - assign wr_entry5_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00101)) ? 1'b1 : - 1'b0; - assign entry5_epn_d[0:31] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry5_epn_q[0:31]; - assign entry5_epn_d[32:51] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry5_epn_q[32:51]; - assign entry5_xbit_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[52] : - entry5_xbit_q; - assign entry5_size_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry5_size_q[0:2]; - assign entry5_class_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry5_class_q[0:1]; - assign entry5_extclass_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry5_extclass_q[0:1]; - assign entry5_hv_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[65] : - entry5_hv_q; - assign entry5_ds_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[66] : - entry5_ds_q; - assign entry5_pid_d = (wr_entry5_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry5_pid_q[0:7]; - assign entry5_cmpmask_d = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry5_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry5_parity_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry5_parity_q[0:3]; - assign entry5_parity_d[4:6] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry5_parity_q[4:6]; - assign entry5_parity_d[7] = (wr_entry5_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry5_parity_q[7]; - assign entry5_parity_d[8] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry5_parity_q[8]; - assign entry5_parity_d[9] = (wr_entry5_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry5_parity_q[9]; - assign wr_entry6_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : - 1'b0; - assign wr_entry6_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00110)) ? 1'b1 : - 1'b0; - assign entry6_epn_d[0:31] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry6_epn_q[0:31]; - assign entry6_epn_d[32:51] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry6_epn_q[32:51]; - assign entry6_xbit_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[52] : - entry6_xbit_q; - assign entry6_size_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry6_size_q[0:2]; - assign entry6_class_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry6_class_q[0:1]; - assign entry6_extclass_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry6_extclass_q[0:1]; - assign entry6_hv_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[65] : - entry6_hv_q; - assign entry6_ds_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[66] : - entry6_ds_q; - assign entry6_pid_d = (wr_entry6_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry6_pid_q[0:7]; - assign entry6_cmpmask_d = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry6_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry6_parity_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry6_parity_q[0:3]; - assign entry6_parity_d[4:6] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry6_parity_q[4:6]; - assign entry6_parity_d[7] = (wr_entry6_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry6_parity_q[7]; - assign entry6_parity_d[8] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry6_parity_q[8]; - assign entry6_parity_d[9] = (wr_entry6_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry6_parity_q[9]; - assign wr_entry7_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : - 1'b0; - assign wr_entry7_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b00111)) ? 1'b1 : - 1'b0; - assign entry7_epn_d[0:31] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry7_epn_q[0:31]; - assign entry7_epn_d[32:51] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry7_epn_q[32:51]; - assign entry7_xbit_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[52] : - entry7_xbit_q; - assign entry7_size_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry7_size_q[0:2]; - assign entry7_class_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry7_class_q[0:1]; - assign entry7_extclass_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry7_extclass_q[0:1]; - assign entry7_hv_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[65] : - entry7_hv_q; - assign entry7_ds_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[66] : - entry7_ds_q; - assign entry7_pid_d = (wr_entry7_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry7_pid_q[0:7]; - assign entry7_cmpmask_d = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry7_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry7_parity_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry7_parity_q[0:3]; - assign entry7_parity_d[4:6] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry7_parity_q[4:6]; - assign entry7_parity_d[7] = (wr_entry7_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry7_parity_q[7]; - assign entry7_parity_d[8] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry7_parity_q[8]; - assign entry7_parity_d[9] = (wr_entry7_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry7_parity_q[9]; - assign wr_entry8_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : - 1'b0; - assign wr_entry8_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01000)) ? 1'b1 : - 1'b0; - assign entry8_epn_d[0:31] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry8_epn_q[0:31]; - assign entry8_epn_d[32:51] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry8_epn_q[32:51]; - assign entry8_xbit_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[52] : - entry8_xbit_q; - assign entry8_size_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry8_size_q[0:2]; - assign entry8_class_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry8_class_q[0:1]; - assign entry8_extclass_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry8_extclass_q[0:1]; - assign entry8_hv_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[65] : - entry8_hv_q; - assign entry8_ds_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[66] : - entry8_ds_q; - assign entry8_pid_d = (wr_entry8_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry8_pid_q[0:7]; - assign entry8_cmpmask_d = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry8_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry8_parity_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry8_parity_q[0:3]; - assign entry8_parity_d[4:6] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry8_parity_q[4:6]; - assign entry8_parity_d[7] = (wr_entry8_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry8_parity_q[7]; - assign entry8_parity_d[8] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry8_parity_q[8]; - assign entry8_parity_d[9] = (wr_entry8_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry8_parity_q[9]; - assign wr_entry9_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : - 1'b0; - assign wr_entry9_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01001)) ? 1'b1 : - 1'b0; - assign entry9_epn_d[0:31] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry9_epn_q[0:31]; - assign entry9_epn_d[32:51] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry9_epn_q[32:51]; - assign entry9_xbit_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[52] : - entry9_xbit_q; - assign entry9_size_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry9_size_q[0:2]; - assign entry9_class_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry9_class_q[0:1]; - assign entry9_extclass_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry9_extclass_q[0:1]; - assign entry9_hv_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[65] : - entry9_hv_q; - assign entry9_ds_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[66] : - entry9_ds_q; - assign entry9_pid_d = (wr_entry9_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry9_pid_q[0:7]; - assign entry9_cmpmask_d = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry9_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry9_parity_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry9_parity_q[0:3]; - assign entry9_parity_d[4:6] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry9_parity_q[4:6]; - assign entry9_parity_d[7] = (wr_entry9_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry9_parity_q[7]; - assign entry9_parity_d[8] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry9_parity_q[8]; - assign entry9_parity_d[9] = (wr_entry9_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry9_parity_q[9]; - assign wr_entry10_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : - 1'b0; - assign wr_entry10_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01010)) ? 1'b1 : - 1'b0; - assign entry10_epn_d[0:31] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry10_epn_q[0:31]; - assign entry10_epn_d[32:51] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry10_epn_q[32:51]; - assign entry10_xbit_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[52] : - entry10_xbit_q; - assign entry10_size_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry10_size_q[0:2]; - assign entry10_class_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry10_class_q[0:1]; - assign entry10_extclass_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry10_extclass_q[0:1]; - assign entry10_hv_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[65] : - entry10_hv_q; - assign entry10_ds_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[66] : - entry10_ds_q; - assign entry10_pid_d = (wr_entry10_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry10_pid_q[0:7]; - assign entry10_cmpmask_d = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry10_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry10_parity_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry10_parity_q[0:3]; - assign entry10_parity_d[4:6] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry10_parity_q[4:6]; - assign entry10_parity_d[7] = (wr_entry10_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry10_parity_q[7]; - assign entry10_parity_d[8] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry10_parity_q[8]; - assign entry10_parity_d[9] = (wr_entry10_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry10_parity_q[9]; - assign wr_entry11_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : - 1'b0; - assign wr_entry11_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01011)) ? 1'b1 : - 1'b0; - assign entry11_epn_d[0:31] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry11_epn_q[0:31]; - assign entry11_epn_d[32:51] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry11_epn_q[32:51]; - assign entry11_xbit_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[52] : - entry11_xbit_q; - assign entry11_size_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry11_size_q[0:2]; - assign entry11_class_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry11_class_q[0:1]; - assign entry11_extclass_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry11_extclass_q[0:1]; - assign entry11_hv_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[65] : - entry11_hv_q; - assign entry11_ds_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[66] : - entry11_ds_q; - assign entry11_pid_d = (wr_entry11_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry11_pid_q[0:7]; - assign entry11_cmpmask_d = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry11_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry11_parity_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry11_parity_q[0:3]; - assign entry11_parity_d[4:6] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry11_parity_q[4:6]; - assign entry11_parity_d[7] = (wr_entry11_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry11_parity_q[7]; - assign entry11_parity_d[8] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry11_parity_q[8]; - assign entry11_parity_d[9] = (wr_entry11_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry11_parity_q[9]; - assign wr_entry12_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : - 1'b0; - assign wr_entry12_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01100)) ? 1'b1 : - 1'b0; - assign entry12_epn_d[0:31] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry12_epn_q[0:31]; - assign entry12_epn_d[32:51] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry12_epn_q[32:51]; - assign entry12_xbit_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[52] : - entry12_xbit_q; - assign entry12_size_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry12_size_q[0:2]; - assign entry12_class_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry12_class_q[0:1]; - assign entry12_extclass_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry12_extclass_q[0:1]; - assign entry12_hv_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[65] : - entry12_hv_q; - assign entry12_ds_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[66] : - entry12_ds_q; - assign entry12_pid_d = (wr_entry12_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry12_pid_q[0:7]; - assign entry12_cmpmask_d = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry12_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry12_parity_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry12_parity_q[0:3]; - assign entry12_parity_d[4:6] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry12_parity_q[4:6]; - assign entry12_parity_d[7] = (wr_entry12_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry12_parity_q[7]; - assign entry12_parity_d[8] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry12_parity_q[8]; - assign entry12_parity_d[9] = (wr_entry12_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry12_parity_q[9]; - assign wr_entry13_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : - 1'b0; - assign wr_entry13_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01101)) ? 1'b1 : - 1'b0; - assign entry13_epn_d[0:31] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry13_epn_q[0:31]; - assign entry13_epn_d[32:51] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry13_epn_q[32:51]; - assign entry13_xbit_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[52] : - entry13_xbit_q; - assign entry13_size_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry13_size_q[0:2]; - assign entry13_class_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry13_class_q[0:1]; - assign entry13_extclass_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry13_extclass_q[0:1]; - assign entry13_hv_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[65] : - entry13_hv_q; - assign entry13_ds_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[66] : - entry13_ds_q; - assign entry13_pid_d = (wr_entry13_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry13_pid_q[0:7]; - assign entry13_cmpmask_d = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry13_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry13_parity_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry13_parity_q[0:3]; - assign entry13_parity_d[4:6] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry13_parity_q[4:6]; - assign entry13_parity_d[7] = (wr_entry13_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry13_parity_q[7]; - assign entry13_parity_d[8] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry13_parity_q[8]; - assign entry13_parity_d[9] = (wr_entry13_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry13_parity_q[9]; - assign wr_entry14_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : - 1'b0; - assign wr_entry14_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01110)) ? 1'b1 : - 1'b0; - assign entry14_epn_d[0:31] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry14_epn_q[0:31]; - assign entry14_epn_d[32:51] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry14_epn_q[32:51]; - assign entry14_xbit_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[52] : - entry14_xbit_q; - assign entry14_size_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry14_size_q[0:2]; - assign entry14_class_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry14_class_q[0:1]; - assign entry14_extclass_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry14_extclass_q[0:1]; - assign entry14_hv_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[65] : - entry14_hv_q; - assign entry14_ds_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[66] : - entry14_ds_q; - assign entry14_pid_d = (wr_entry14_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry14_pid_q[0:7]; - assign entry14_cmpmask_d = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry14_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry14_parity_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry14_parity_q[0:3]; - assign entry14_parity_d[4:6] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry14_parity_q[4:6]; - assign entry14_parity_d[7] = (wr_entry14_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry14_parity_q[7]; - assign entry14_parity_d[8] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry14_parity_q[8]; - assign entry14_parity_d[9] = (wr_entry14_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry14_parity_q[9]; - assign wr_entry15_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : - 1'b0; - assign wr_entry15_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b01111)) ? 1'b1 : - 1'b0; - assign entry15_epn_d[0:31] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry15_epn_q[0:31]; - assign entry15_epn_d[32:51] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry15_epn_q[32:51]; - assign entry15_xbit_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[52] : - entry15_xbit_q; - assign entry15_size_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry15_size_q[0:2]; - assign entry15_class_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry15_class_q[0:1]; - assign entry15_extclass_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry15_extclass_q[0:1]; - assign entry15_hv_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[65] : - entry15_hv_q; - assign entry15_ds_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[66] : - entry15_ds_q; - assign entry15_pid_d = (wr_entry15_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry15_pid_q[0:7]; - assign entry15_cmpmask_d = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry15_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry15_parity_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry15_parity_q[0:3]; - assign entry15_parity_d[4:6] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry15_parity_q[4:6]; - assign entry15_parity_d[7] = (wr_entry15_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry15_parity_q[7]; - assign entry15_parity_d[8] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry15_parity_q[8]; - assign entry15_parity_d[9] = (wr_entry15_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry15_parity_q[9]; - assign wr_entry16_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : - 1'b0; - assign wr_entry16_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10000)) ? 1'b1 : - 1'b0; - assign entry16_epn_d[0:31] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry16_epn_q[0:31]; - assign entry16_epn_d[32:51] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry16_epn_q[32:51]; - assign entry16_xbit_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[52] : - entry16_xbit_q; - assign entry16_size_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry16_size_q[0:2]; - assign entry16_class_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry16_class_q[0:1]; - assign entry16_extclass_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry16_extclass_q[0:1]; - assign entry16_hv_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[65] : - entry16_hv_q; - assign entry16_ds_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[66] : - entry16_ds_q; - assign entry16_pid_d = (wr_entry16_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry16_pid_q[0:7]; - assign entry16_cmpmask_d = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry16_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry16_parity_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry16_parity_q[0:3]; - assign entry16_parity_d[4:6] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry16_parity_q[4:6]; - assign entry16_parity_d[7] = (wr_entry16_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry16_parity_q[7]; - assign entry16_parity_d[8] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry16_parity_q[8]; - assign entry16_parity_d[9] = (wr_entry16_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry16_parity_q[9]; - assign wr_entry17_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : - 1'b0; - assign wr_entry17_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10001)) ? 1'b1 : - 1'b0; - assign entry17_epn_d[0:31] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry17_epn_q[0:31]; - assign entry17_epn_d[32:51] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry17_epn_q[32:51]; - assign entry17_xbit_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[52] : - entry17_xbit_q; - assign entry17_size_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry17_size_q[0:2]; - assign entry17_class_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry17_class_q[0:1]; - assign entry17_extclass_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry17_extclass_q[0:1]; - assign entry17_hv_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[65] : - entry17_hv_q; - assign entry17_ds_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[66] : - entry17_ds_q; - assign entry17_pid_d = (wr_entry17_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry17_pid_q[0:7]; - assign entry17_cmpmask_d = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry17_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry17_parity_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry17_parity_q[0:3]; - assign entry17_parity_d[4:6] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry17_parity_q[4:6]; - assign entry17_parity_d[7] = (wr_entry17_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry17_parity_q[7]; - assign entry17_parity_d[8] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry17_parity_q[8]; - assign entry17_parity_d[9] = (wr_entry17_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry17_parity_q[9]; - assign wr_entry18_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : - 1'b0; - assign wr_entry18_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10010)) ? 1'b1 : - 1'b0; - assign entry18_epn_d[0:31] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry18_epn_q[0:31]; - assign entry18_epn_d[32:51] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry18_epn_q[32:51]; - assign entry18_xbit_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[52] : - entry18_xbit_q; - assign entry18_size_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry18_size_q[0:2]; - assign entry18_class_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry18_class_q[0:1]; - assign entry18_extclass_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry18_extclass_q[0:1]; - assign entry18_hv_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[65] : - entry18_hv_q; - assign entry18_ds_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[66] : - entry18_ds_q; - assign entry18_pid_d = (wr_entry18_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry18_pid_q[0:7]; - assign entry18_cmpmask_d = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry18_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry18_parity_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry18_parity_q[0:3]; - assign entry18_parity_d[4:6] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry18_parity_q[4:6]; - assign entry18_parity_d[7] = (wr_entry18_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry18_parity_q[7]; - assign entry18_parity_d[8] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry18_parity_q[8]; - assign entry18_parity_d[9] = (wr_entry18_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry18_parity_q[9]; - assign wr_entry19_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : - 1'b0; - assign wr_entry19_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10011)) ? 1'b1 : - 1'b0; - assign entry19_epn_d[0:31] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry19_epn_q[0:31]; - assign entry19_epn_d[32:51] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry19_epn_q[32:51]; - assign entry19_xbit_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[52] : - entry19_xbit_q; - assign entry19_size_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry19_size_q[0:2]; - assign entry19_class_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry19_class_q[0:1]; - assign entry19_extclass_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry19_extclass_q[0:1]; - assign entry19_hv_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[65] : - entry19_hv_q; - assign entry19_ds_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[66] : - entry19_ds_q; - assign entry19_pid_d = (wr_entry19_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry19_pid_q[0:7]; - assign entry19_cmpmask_d = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry19_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry19_parity_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry19_parity_q[0:3]; - assign entry19_parity_d[4:6] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry19_parity_q[4:6]; - assign entry19_parity_d[7] = (wr_entry19_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry19_parity_q[7]; - assign entry19_parity_d[8] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry19_parity_q[8]; - assign entry19_parity_d[9] = (wr_entry19_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry19_parity_q[9]; - assign wr_entry20_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : - 1'b0; - assign wr_entry20_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10100)) ? 1'b1 : - 1'b0; - assign entry20_epn_d[0:31] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry20_epn_q[0:31]; - assign entry20_epn_d[32:51] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry20_epn_q[32:51]; - assign entry20_xbit_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[52] : - entry20_xbit_q; - assign entry20_size_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry20_size_q[0:2]; - assign entry20_class_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry20_class_q[0:1]; - assign entry20_extclass_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry20_extclass_q[0:1]; - assign entry20_hv_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[65] : - entry20_hv_q; - assign entry20_ds_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[66] : - entry20_ds_q; - assign entry20_pid_d = (wr_entry20_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry20_pid_q[0:7]; - assign entry20_cmpmask_d = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry20_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry20_parity_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry20_parity_q[0:3]; - assign entry20_parity_d[4:6] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry20_parity_q[4:6]; - assign entry20_parity_d[7] = (wr_entry20_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry20_parity_q[7]; - assign entry20_parity_d[8] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry20_parity_q[8]; - assign entry20_parity_d[9] = (wr_entry20_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry20_parity_q[9]; - assign wr_entry21_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : - 1'b0; - assign wr_entry21_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10101)) ? 1'b1 : - 1'b0; - assign entry21_epn_d[0:31] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry21_epn_q[0:31]; - assign entry21_epn_d[32:51] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry21_epn_q[32:51]; - assign entry21_xbit_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[52] : - entry21_xbit_q; - assign entry21_size_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry21_size_q[0:2]; - assign entry21_class_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry21_class_q[0:1]; - assign entry21_extclass_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry21_extclass_q[0:1]; - assign entry21_hv_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[65] : - entry21_hv_q; - assign entry21_ds_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[66] : - entry21_ds_q; - assign entry21_pid_d = (wr_entry21_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry21_pid_q[0:7]; - assign entry21_cmpmask_d = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry21_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry21_parity_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry21_parity_q[0:3]; - assign entry21_parity_d[4:6] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry21_parity_q[4:6]; - assign entry21_parity_d[7] = (wr_entry21_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry21_parity_q[7]; - assign entry21_parity_d[8] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry21_parity_q[8]; - assign entry21_parity_d[9] = (wr_entry21_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry21_parity_q[9]; - assign wr_entry22_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : - 1'b0; - assign wr_entry22_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10110)) ? 1'b1 : - 1'b0; - assign entry22_epn_d[0:31] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry22_epn_q[0:31]; - assign entry22_epn_d[32:51] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry22_epn_q[32:51]; - assign entry22_xbit_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[52] : - entry22_xbit_q; - assign entry22_size_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry22_size_q[0:2]; - assign entry22_class_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry22_class_q[0:1]; - assign entry22_extclass_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry22_extclass_q[0:1]; - assign entry22_hv_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[65] : - entry22_hv_q; - assign entry22_ds_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[66] : - entry22_ds_q; - assign entry22_pid_d = (wr_entry22_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry22_pid_q[0:7]; - assign entry22_cmpmask_d = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry22_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry22_parity_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry22_parity_q[0:3]; - assign entry22_parity_d[4:6] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry22_parity_q[4:6]; - assign entry22_parity_d[7] = (wr_entry22_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry22_parity_q[7]; - assign entry22_parity_d[8] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry22_parity_q[8]; - assign entry22_parity_d[9] = (wr_entry22_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry22_parity_q[9]; - assign wr_entry23_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : - 1'b0; - assign wr_entry23_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b10111)) ? 1'b1 : - 1'b0; - assign entry23_epn_d[0:31] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry23_epn_q[0:31]; - assign entry23_epn_d[32:51] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry23_epn_q[32:51]; - assign entry23_xbit_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[52] : - entry23_xbit_q; - assign entry23_size_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry23_size_q[0:2]; - assign entry23_class_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry23_class_q[0:1]; - assign entry23_extclass_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry23_extclass_q[0:1]; - assign entry23_hv_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[65] : - entry23_hv_q; - assign entry23_ds_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[66] : - entry23_ds_q; - assign entry23_pid_d = (wr_entry23_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry23_pid_q[0:7]; - assign entry23_cmpmask_d = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry23_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry23_parity_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry23_parity_q[0:3]; - assign entry23_parity_d[4:6] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry23_parity_q[4:6]; - assign entry23_parity_d[7] = (wr_entry23_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry23_parity_q[7]; - assign entry23_parity_d[8] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry23_parity_q[8]; - assign entry23_parity_d[9] = (wr_entry23_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry23_parity_q[9]; - assign wr_entry24_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : - 1'b0; - assign wr_entry24_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11000)) ? 1'b1 : - 1'b0; - assign entry24_epn_d[0:31] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry24_epn_q[0:31]; - assign entry24_epn_d[32:51] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry24_epn_q[32:51]; - assign entry24_xbit_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[52] : - entry24_xbit_q; - assign entry24_size_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry24_size_q[0:2]; - assign entry24_class_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry24_class_q[0:1]; - assign entry24_extclass_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry24_extclass_q[0:1]; - assign entry24_hv_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[65] : - entry24_hv_q; - assign entry24_ds_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[66] : - entry24_ds_q; - assign entry24_pid_d = (wr_entry24_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry24_pid_q[0:7]; - assign entry24_cmpmask_d = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry24_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry24_parity_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry24_parity_q[0:3]; - assign entry24_parity_d[4:6] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry24_parity_q[4:6]; - assign entry24_parity_d[7] = (wr_entry24_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry24_parity_q[7]; - assign entry24_parity_d[8] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry24_parity_q[8]; - assign entry24_parity_d[9] = (wr_entry24_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry24_parity_q[9]; - assign wr_entry25_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : - 1'b0; - assign wr_entry25_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11001)) ? 1'b1 : - 1'b0; - assign entry25_epn_d[0:31] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry25_epn_q[0:31]; - assign entry25_epn_d[32:51] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry25_epn_q[32:51]; - assign entry25_xbit_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[52] : - entry25_xbit_q; - assign entry25_size_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry25_size_q[0:2]; - assign entry25_class_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry25_class_q[0:1]; - assign entry25_extclass_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry25_extclass_q[0:1]; - assign entry25_hv_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[65] : - entry25_hv_q; - assign entry25_ds_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[66] : - entry25_ds_q; - assign entry25_pid_d = (wr_entry25_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry25_pid_q[0:7]; - assign entry25_cmpmask_d = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry25_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry25_parity_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry25_parity_q[0:3]; - assign entry25_parity_d[4:6] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry25_parity_q[4:6]; - assign entry25_parity_d[7] = (wr_entry25_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry25_parity_q[7]; - assign entry25_parity_d[8] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry25_parity_q[8]; - assign entry25_parity_d[9] = (wr_entry25_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry25_parity_q[9]; - assign wr_entry26_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : - 1'b0; - assign wr_entry26_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11010)) ? 1'b1 : - 1'b0; - assign entry26_epn_d[0:31] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry26_epn_q[0:31]; - assign entry26_epn_d[32:51] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry26_epn_q[32:51]; - assign entry26_xbit_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[52] : - entry26_xbit_q; - assign entry26_size_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry26_size_q[0:2]; - assign entry26_class_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry26_class_q[0:1]; - assign entry26_extclass_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry26_extclass_q[0:1]; - assign entry26_hv_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[65] : - entry26_hv_q; - assign entry26_ds_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[66] : - entry26_ds_q; - assign entry26_pid_d = (wr_entry26_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry26_pid_q[0:7]; - assign entry26_cmpmask_d = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry26_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry26_parity_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry26_parity_q[0:3]; - assign entry26_parity_d[4:6] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry26_parity_q[4:6]; - assign entry26_parity_d[7] = (wr_entry26_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry26_parity_q[7]; - assign entry26_parity_d[8] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry26_parity_q[8]; - assign entry26_parity_d[9] = (wr_entry26_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry26_parity_q[9]; - assign wr_entry27_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : - 1'b0; - assign wr_entry27_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11011)) ? 1'b1 : - 1'b0; - assign entry27_epn_d[0:31] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry27_epn_q[0:31]; - assign entry27_epn_d[32:51] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry27_epn_q[32:51]; - assign entry27_xbit_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[52] : - entry27_xbit_q; - assign entry27_size_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry27_size_q[0:2]; - assign entry27_class_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry27_class_q[0:1]; - assign entry27_extclass_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry27_extclass_q[0:1]; - assign entry27_hv_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[65] : - entry27_hv_q; - assign entry27_ds_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[66] : - entry27_ds_q; - assign entry27_pid_d = (wr_entry27_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry27_pid_q[0:7]; - assign entry27_cmpmask_d = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry27_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry27_parity_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry27_parity_q[0:3]; - assign entry27_parity_d[4:6] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry27_parity_q[4:6]; - assign entry27_parity_d[7] = (wr_entry27_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry27_parity_q[7]; - assign entry27_parity_d[8] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry27_parity_q[8]; - assign entry27_parity_d[9] = (wr_entry27_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry27_parity_q[9]; - assign wr_entry28_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : - 1'b0; - assign wr_entry28_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11100)) ? 1'b1 : - 1'b0; - assign entry28_epn_d[0:31] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry28_epn_q[0:31]; - assign entry28_epn_d[32:51] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry28_epn_q[32:51]; - assign entry28_xbit_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[52] : - entry28_xbit_q; - assign entry28_size_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry28_size_q[0:2]; - assign entry28_class_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry28_class_q[0:1]; - assign entry28_extclass_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry28_extclass_q[0:1]; - assign entry28_hv_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[65] : - entry28_hv_q; - assign entry28_ds_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[66] : - entry28_ds_q; - assign entry28_pid_d = (wr_entry28_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry28_pid_q[0:7]; - assign entry28_cmpmask_d = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry28_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry28_parity_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry28_parity_q[0:3]; - assign entry28_parity_d[4:6] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry28_parity_q[4:6]; - assign entry28_parity_d[7] = (wr_entry28_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry28_parity_q[7]; - assign entry28_parity_d[8] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry28_parity_q[8]; - assign entry28_parity_d[9] = (wr_entry28_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry28_parity_q[9]; - assign wr_entry29_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : - 1'b0; - assign wr_entry29_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11101)) ? 1'b1 : - 1'b0; - assign entry29_epn_d[0:31] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry29_epn_q[0:31]; - assign entry29_epn_d[32:51] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry29_epn_q[32:51]; - assign entry29_xbit_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[52] : - entry29_xbit_q; - assign entry29_size_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry29_size_q[0:2]; - assign entry29_class_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry29_class_q[0:1]; - assign entry29_extclass_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry29_extclass_q[0:1]; - assign entry29_hv_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[65] : - entry29_hv_q; - assign entry29_ds_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[66] : - entry29_ds_q; - assign entry29_pid_d = (wr_entry29_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry29_pid_q[0:7]; - assign entry29_cmpmask_d = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry29_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry29_parity_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry29_parity_q[0:3]; - assign entry29_parity_d[4:6] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry29_parity_q[4:6]; - assign entry29_parity_d[7] = (wr_entry29_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry29_parity_q[7]; - assign entry29_parity_d[8] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry29_parity_q[8]; - assign entry29_parity_d[9] = (wr_entry29_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry29_parity_q[9]; - assign wr_entry30_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : - 1'b0; - assign wr_entry30_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11110)) ? 1'b1 : - 1'b0; - assign entry30_epn_d[0:31] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry30_epn_q[0:31]; - assign entry30_epn_d[32:51] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry30_epn_q[32:51]; - assign entry30_xbit_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[52] : - entry30_xbit_q; - assign entry30_size_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry30_size_q[0:2]; - assign entry30_class_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry30_class_q[0:1]; - assign entry30_extclass_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry30_extclass_q[0:1]; - assign entry30_hv_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[65] : - entry30_hv_q; - assign entry30_ds_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[66] : - entry30_ds_q; - assign entry30_pid_d = (wr_entry30_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry30_pid_q[0:7]; - assign entry30_cmpmask_d = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry30_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry30_parity_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry30_parity_q[0:3]; - assign entry30_parity_d[4:6] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry30_parity_q[4:6]; - assign entry30_parity_d[7] = (wr_entry30_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry30_parity_q[7]; - assign entry30_parity_d[8] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry30_parity_q[8]; - assign entry30_parity_d[9] = (wr_entry30_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry30_parity_q[9]; - assign wr_entry31_sel[0] = ((wr_cam_val[0] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : - 1'b0; - assign wr_entry31_sel[1] = ((wr_cam_val[1] == 1'b1) & (rw_entry == 5'b11111)) ? 1'b1 : - 1'b0; - assign entry31_epn_d[0:31] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[0:31] : - entry31_epn_q[0:31]; - assign entry31_epn_d[32:51] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[32:51] : - entry31_epn_q[32:51]; - assign entry31_xbit_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[52] : - entry31_xbit_q; - assign entry31_size_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[53:55] : - entry31_size_q[0:2]; - assign entry31_class_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[61:62] : - entry31_class_q[0:1]; - assign entry31_extclass_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[63:64] : - entry31_extclass_q[0:1]; - assign entry31_hv_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[65] : - entry31_hv_q; - assign entry31_ds_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[66] : - entry31_ds_q; - assign entry31_pid_d = (wr_entry31_sel[1] == 1'b1) ? wr_cam_data[67:74] : - entry31_pid_q[0:7]; - assign entry31_cmpmask_d = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[75:83] : - entry31_cmpmask_q; - // the cam parity bits.. some wr_array_data bits contain parity for cam - assign entry31_parity_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 21:RPN_WIDTH + 24] : - entry31_parity_q[0:3]; - assign entry31_parity_d[4:6] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 25:RPN_WIDTH + 27] : - entry31_parity_q[4:6]; - assign entry31_parity_d[7] = (wr_entry31_sel[0] == 1'b1) ? wr_array_data[RPN_WIDTH + 28] : - entry31_parity_q[7]; - assign entry31_parity_d[8] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 29] : - entry31_parity_q[8]; - assign entry31_parity_d[9] = (wr_entry31_sel[1] == 1'b1) ? wr_array_data[RPN_WIDTH + 30] : - entry31_parity_q[9]; - - - // entry valid and thdid next state logic - assign entry0_inval = (comp_invalidate & match_vec[0]) | flash_invalidate; - assign entry0_v_muxsel[0:1] = ({entry0_inval, wr_entry0_sel[0]}); - assign entry0_v_d = (entry0_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry0_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry0_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry0_v_q; - assign entry0_thdid_d[0:3] = (wr_entry0_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry0_thdid_q[0:3]; - assign entry1_inval = (comp_invalidate & match_vec[1]) | flash_invalidate; - assign entry1_v_muxsel[0:1] = ({entry1_inval, wr_entry1_sel[0]}); - assign entry1_v_d = (entry1_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry1_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry1_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry1_v_q; - assign entry1_thdid_d[0:3] = (wr_entry1_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry1_thdid_q[0:3]; - assign entry2_inval = (comp_invalidate & match_vec[2]) | flash_invalidate; - assign entry2_v_muxsel[0:1] = ({entry2_inval, wr_entry2_sel[0]}); - assign entry2_v_d = (entry2_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry2_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry2_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry2_v_q; - assign entry2_thdid_d[0:3] = (wr_entry2_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry2_thdid_q[0:3]; - assign entry3_inval = (comp_invalidate & match_vec[3]) | flash_invalidate; - assign entry3_v_muxsel[0:1] = ({entry3_inval, wr_entry3_sel[0]}); - assign entry3_v_d = (entry3_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry3_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry3_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry3_v_q; - assign entry3_thdid_d[0:3] = (wr_entry3_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry3_thdid_q[0:3]; - assign entry4_inval = (comp_invalidate & match_vec[4]) | flash_invalidate; - assign entry4_v_muxsel[0:1] = ({entry4_inval, wr_entry4_sel[0]}); - assign entry4_v_d = (entry4_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry4_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry4_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry4_v_q; - assign entry4_thdid_d[0:3] = (wr_entry4_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry4_thdid_q[0:3]; - assign entry5_inval = (comp_invalidate & match_vec[5]) | flash_invalidate; - assign entry5_v_muxsel[0:1] = ({entry5_inval, wr_entry5_sel[0]}); - assign entry5_v_d = (entry5_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry5_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry5_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry5_v_q; - assign entry5_thdid_d[0:3] = (wr_entry5_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry5_thdid_q[0:3]; - assign entry6_inval = (comp_invalidate & match_vec[6]) | flash_invalidate; - assign entry6_v_muxsel[0:1] = ({entry6_inval, wr_entry6_sel[0]}); - assign entry6_v_d = (entry6_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry6_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry6_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry6_v_q; - assign entry6_thdid_d[0:3] = (wr_entry6_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry6_thdid_q[0:3]; - assign entry7_inval = (comp_invalidate & match_vec[7]) | flash_invalidate; - assign entry7_v_muxsel[0:1] = ({entry7_inval, wr_entry7_sel[0]}); - assign entry7_v_d = (entry7_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry7_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry7_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry7_v_q; - assign entry7_thdid_d[0:3] = (wr_entry7_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry7_thdid_q[0:3]; - assign entry8_inval = (comp_invalidate & match_vec[8]) | flash_invalidate; - assign entry8_v_muxsel[0:1] = ({entry8_inval, wr_entry8_sel[0]}); - assign entry8_v_d = (entry8_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry8_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry8_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry8_v_q; - assign entry8_thdid_d[0:3] = (wr_entry8_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry8_thdid_q[0:3]; - assign entry9_inval = (comp_invalidate & match_vec[9]) | flash_invalidate; - assign entry9_v_muxsel[0:1] = ({entry9_inval, wr_entry9_sel[0]}); - assign entry9_v_d = (entry9_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry9_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry9_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry9_v_q; - assign entry9_thdid_d[0:3] = (wr_entry9_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry9_thdid_q[0:3]; - assign entry10_inval = (comp_invalidate & match_vec[10]) | flash_invalidate; - assign entry10_v_muxsel[0:1] = ({entry10_inval, wr_entry10_sel[0]}); - assign entry10_v_d = (entry10_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry10_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry10_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry10_v_q; - assign entry10_thdid_d[0:3] = (wr_entry10_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry10_thdid_q[0:3]; - assign entry11_inval = (comp_invalidate & match_vec[11]) | flash_invalidate; - assign entry11_v_muxsel[0:1] = ({entry11_inval, wr_entry11_sel[0]}); - assign entry11_v_d = (entry11_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry11_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry11_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry11_v_q; - assign entry11_thdid_d[0:3] = (wr_entry11_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry11_thdid_q[0:3]; - assign entry12_inval = (comp_invalidate & match_vec[12]) | flash_invalidate; - assign entry12_v_muxsel[0:1] = ({entry12_inval, wr_entry12_sel[0]}); - assign entry12_v_d = (entry12_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry12_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry12_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry12_v_q; - assign entry12_thdid_d[0:3] = (wr_entry12_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry12_thdid_q[0:3]; - assign entry13_inval = (comp_invalidate & match_vec[13]) | flash_invalidate; - assign entry13_v_muxsel[0:1] = ({entry13_inval, wr_entry13_sel[0]}); - assign entry13_v_d = (entry13_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry13_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry13_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry13_v_q; - assign entry13_thdid_d[0:3] = (wr_entry13_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry13_thdid_q[0:3]; - assign entry14_inval = (comp_invalidate & match_vec[14]) | flash_invalidate; - assign entry14_v_muxsel[0:1] = ({entry14_inval, wr_entry14_sel[0]}); - assign entry14_v_d = (entry14_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry14_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry14_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry14_v_q; - assign entry14_thdid_d[0:3] = (wr_entry14_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry14_thdid_q[0:3]; - assign entry15_inval = (comp_invalidate & match_vec[15]) | flash_invalidate; - assign entry15_v_muxsel[0:1] = ({entry15_inval, wr_entry15_sel[0]}); - assign entry15_v_d = (entry15_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry15_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry15_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry15_v_q; - assign entry15_thdid_d[0:3] = (wr_entry15_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry15_thdid_q[0:3]; - assign entry16_inval = (comp_invalidate & match_vec[16]) | flash_invalidate; - assign entry16_v_muxsel[0:1] = ({entry16_inval, wr_entry16_sel[0]}); - assign entry16_v_d = (entry16_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry16_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry16_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry16_v_q; - assign entry16_thdid_d[0:3] = (wr_entry16_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry16_thdid_q[0:3]; - assign entry17_inval = (comp_invalidate & match_vec[17]) | flash_invalidate; - assign entry17_v_muxsel[0:1] = ({entry17_inval, wr_entry17_sel[0]}); - assign entry17_v_d = (entry17_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry17_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry17_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry17_v_q; - assign entry17_thdid_d[0:3] = (wr_entry17_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry17_thdid_q[0:3]; - assign entry18_inval = (comp_invalidate & match_vec[18]) | flash_invalidate; - assign entry18_v_muxsel[0:1] = ({entry18_inval, wr_entry18_sel[0]}); - assign entry18_v_d = (entry18_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry18_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry18_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry18_v_q; - assign entry18_thdid_d[0:3] = (wr_entry18_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry18_thdid_q[0:3]; - assign entry19_inval = (comp_invalidate & match_vec[19]) | flash_invalidate; - assign entry19_v_muxsel[0:1] = ({entry19_inval, wr_entry19_sel[0]}); - assign entry19_v_d = (entry19_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry19_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry19_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry19_v_q; - assign entry19_thdid_d[0:3] = (wr_entry19_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry19_thdid_q[0:3]; - assign entry20_inval = (comp_invalidate & match_vec[20]) | flash_invalidate; - assign entry20_v_muxsel[0:1] = ({entry20_inval, wr_entry20_sel[0]}); - assign entry20_v_d = (entry20_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry20_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry20_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry20_v_q; - assign entry20_thdid_d[0:3] = (wr_entry20_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry20_thdid_q[0:3]; - assign entry21_inval = (comp_invalidate & match_vec[21]) | flash_invalidate; - assign entry21_v_muxsel[0:1] = ({entry21_inval, wr_entry21_sel[0]}); - assign entry21_v_d = (entry21_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry21_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry21_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry21_v_q; - assign entry21_thdid_d[0:3] = (wr_entry21_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry21_thdid_q[0:3]; - assign entry22_inval = (comp_invalidate & match_vec[22]) | flash_invalidate; - assign entry22_v_muxsel[0:1] = ({entry22_inval, wr_entry22_sel[0]}); - assign entry22_v_d = (entry22_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry22_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry22_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry22_v_q; - assign entry22_thdid_d[0:3] = (wr_entry22_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry22_thdid_q[0:3]; - assign entry23_inval = (comp_invalidate & match_vec[23]) | flash_invalidate; - assign entry23_v_muxsel[0:1] = ({entry23_inval, wr_entry23_sel[0]}); - assign entry23_v_d = (entry23_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry23_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry23_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry23_v_q; - assign entry23_thdid_d[0:3] = (wr_entry23_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry23_thdid_q[0:3]; - assign entry24_inval = (comp_invalidate & match_vec[24]) | flash_invalidate; - assign entry24_v_muxsel[0:1] = ({entry24_inval, wr_entry24_sel[0]}); - assign entry24_v_d = (entry24_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry24_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry24_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry24_v_q; - assign entry24_thdid_d[0:3] = (wr_entry24_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry24_thdid_q[0:3]; - assign entry25_inval = (comp_invalidate & match_vec[25]) | flash_invalidate; - assign entry25_v_muxsel[0:1] = ({entry25_inval, wr_entry25_sel[0]}); - assign entry25_v_d = (entry25_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry25_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry25_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry25_v_q; - assign entry25_thdid_d[0:3] = (wr_entry25_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry25_thdid_q[0:3]; - assign entry26_inval = (comp_invalidate & match_vec[26]) | flash_invalidate; - assign entry26_v_muxsel[0:1] = ({entry26_inval, wr_entry26_sel[0]}); - assign entry26_v_d = (entry26_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry26_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry26_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry26_v_q; - assign entry26_thdid_d[0:3] = (wr_entry26_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry26_thdid_q[0:3]; - assign entry27_inval = (comp_invalidate & match_vec[27]) | flash_invalidate; - assign entry27_v_muxsel[0:1] = ({entry27_inval, wr_entry27_sel[0]}); - assign entry27_v_d = (entry27_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry27_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry27_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry27_v_q; - assign entry27_thdid_d[0:3] = (wr_entry27_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry27_thdid_q[0:3]; - assign entry28_inval = (comp_invalidate & match_vec[28]) | flash_invalidate; - assign entry28_v_muxsel[0:1] = ({entry28_inval, wr_entry28_sel[0]}); - assign entry28_v_d = (entry28_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry28_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry28_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry28_v_q; - assign entry28_thdid_d[0:3] = (wr_entry28_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry28_thdid_q[0:3]; - assign entry29_inval = (comp_invalidate & match_vec[29]) | flash_invalidate; - assign entry29_v_muxsel[0:1] = ({entry29_inval, wr_entry29_sel[0]}); - assign entry29_v_d = (entry29_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry29_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry29_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry29_v_q; - assign entry29_thdid_d[0:3] = (wr_entry29_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry29_thdid_q[0:3]; - assign entry30_inval = (comp_invalidate & match_vec[30]) | flash_invalidate; - assign entry30_v_muxsel[0:1] = ({entry30_inval, wr_entry30_sel[0]}); - assign entry30_v_d = (entry30_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry30_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry30_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry30_v_q; - assign entry30_thdid_d[0:3] = (wr_entry30_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry30_thdid_q[0:3]; - assign entry31_inval = (comp_invalidate & match_vec[31]) | flash_invalidate; - assign entry31_v_muxsel[0:1] = ({entry31_inval, wr_entry31_sel[0]}); - assign entry31_v_d = (entry31_v_muxsel[0:1] == 2'b10) ? 1'b0 : - (entry31_v_muxsel[0:1] == 2'b11) ? 1'b0 : - (entry31_v_muxsel[0:1] == 2'b01) ? wr_cam_data[56] : - entry31_v_q; - assign entry31_thdid_d[0:3] = (wr_entry31_sel[0] == 1'b1) ? wr_cam_data[57:60] : - entry31_thdid_q[0:3]; - - - // CAM compare data out mux - assign entry0_cam_vec = {entry0_epn_q, entry0_xbit_q, entry0_size_q, entry0_v_q, entry0_thdid_q, entry0_class_q, entry0_extclass_q, entry0_hv_q, entry0_ds_q, entry0_pid_q, entry0_cmpmask_q}; - assign entry1_cam_vec = {entry1_epn_q, entry1_xbit_q, entry1_size_q, entry1_v_q, entry1_thdid_q, entry1_class_q, entry1_extclass_q, entry1_hv_q, entry1_ds_q, entry1_pid_q, entry1_cmpmask_q}; - assign entry2_cam_vec = {entry2_epn_q, entry2_xbit_q, entry2_size_q, entry2_v_q, entry2_thdid_q, entry2_class_q, entry2_extclass_q, entry2_hv_q, entry2_ds_q, entry2_pid_q, entry2_cmpmask_q}; - assign entry3_cam_vec = {entry3_epn_q, entry3_xbit_q, entry3_size_q, entry3_v_q, entry3_thdid_q, entry3_class_q, entry3_extclass_q, entry3_hv_q, entry3_ds_q, entry3_pid_q, entry3_cmpmask_q}; - assign entry4_cam_vec = {entry4_epn_q, entry4_xbit_q, entry4_size_q, entry4_v_q, entry4_thdid_q, entry4_class_q, entry4_extclass_q, entry4_hv_q, entry4_ds_q, entry4_pid_q, entry4_cmpmask_q}; - assign entry5_cam_vec = {entry5_epn_q, entry5_xbit_q, entry5_size_q, entry5_v_q, entry5_thdid_q, entry5_class_q, entry5_extclass_q, entry5_hv_q, entry5_ds_q, entry5_pid_q, entry5_cmpmask_q}; - assign entry6_cam_vec = {entry6_epn_q, entry6_xbit_q, entry6_size_q, entry6_v_q, entry6_thdid_q, entry6_class_q, entry6_extclass_q, entry6_hv_q, entry6_ds_q, entry6_pid_q, entry6_cmpmask_q}; - assign entry7_cam_vec = {entry7_epn_q, entry7_xbit_q, entry7_size_q, entry7_v_q, entry7_thdid_q, entry7_class_q, entry7_extclass_q, entry7_hv_q, entry7_ds_q, entry7_pid_q, entry7_cmpmask_q}; - assign entry8_cam_vec = {entry8_epn_q, entry8_xbit_q, entry8_size_q, entry8_v_q, entry8_thdid_q, entry8_class_q, entry8_extclass_q, entry8_hv_q, entry8_ds_q, entry8_pid_q, entry8_cmpmask_q}; - assign entry9_cam_vec = {entry9_epn_q, entry9_xbit_q, entry9_size_q, entry9_v_q, entry9_thdid_q, entry9_class_q, entry9_extclass_q, entry9_hv_q, entry9_ds_q, entry9_pid_q, entry9_cmpmask_q}; - assign entry10_cam_vec = {entry10_epn_q, entry10_xbit_q, entry10_size_q, entry10_v_q, entry10_thdid_q, entry10_class_q, entry10_extclass_q, entry10_hv_q, entry10_ds_q, entry10_pid_q, entry10_cmpmask_q}; - assign entry11_cam_vec = {entry11_epn_q, entry11_xbit_q, entry11_size_q, entry11_v_q, entry11_thdid_q, entry11_class_q, entry11_extclass_q, entry11_hv_q, entry11_ds_q, entry11_pid_q, entry11_cmpmask_q}; - assign entry12_cam_vec = {entry12_epn_q, entry12_xbit_q, entry12_size_q, entry12_v_q, entry12_thdid_q, entry12_class_q, entry12_extclass_q, entry12_hv_q, entry12_ds_q, entry12_pid_q, entry12_cmpmask_q}; - assign entry13_cam_vec = {entry13_epn_q, entry13_xbit_q, entry13_size_q, entry13_v_q, entry13_thdid_q, entry13_class_q, entry13_extclass_q, entry13_hv_q, entry13_ds_q, entry13_pid_q, entry13_cmpmask_q}; - assign entry14_cam_vec = {entry14_epn_q, entry14_xbit_q, entry14_size_q, entry14_v_q, entry14_thdid_q, entry14_class_q, entry14_extclass_q, entry14_hv_q, entry14_ds_q, entry14_pid_q, entry14_cmpmask_q}; - assign entry15_cam_vec = {entry15_epn_q, entry15_xbit_q, entry15_size_q, entry15_v_q, entry15_thdid_q, entry15_class_q, entry15_extclass_q, entry15_hv_q, entry15_ds_q, entry15_pid_q, entry15_cmpmask_q}; - assign entry16_cam_vec = {entry16_epn_q, entry16_xbit_q, entry16_size_q, entry16_v_q, entry16_thdid_q, entry16_class_q, entry16_extclass_q, entry16_hv_q, entry16_ds_q, entry16_pid_q, entry16_cmpmask_q}; - assign entry17_cam_vec = {entry17_epn_q, entry17_xbit_q, entry17_size_q, entry17_v_q, entry17_thdid_q, entry17_class_q, entry17_extclass_q, entry17_hv_q, entry17_ds_q, entry17_pid_q, entry17_cmpmask_q}; - assign entry18_cam_vec = {entry18_epn_q, entry18_xbit_q, entry18_size_q, entry18_v_q, entry18_thdid_q, entry18_class_q, entry18_extclass_q, entry18_hv_q, entry18_ds_q, entry18_pid_q, entry18_cmpmask_q}; - assign entry19_cam_vec = {entry19_epn_q, entry19_xbit_q, entry19_size_q, entry19_v_q, entry19_thdid_q, entry19_class_q, entry19_extclass_q, entry19_hv_q, entry19_ds_q, entry19_pid_q, entry19_cmpmask_q}; - assign entry20_cam_vec = {entry20_epn_q, entry20_xbit_q, entry20_size_q, entry20_v_q, entry20_thdid_q, entry20_class_q, entry20_extclass_q, entry20_hv_q, entry20_ds_q, entry20_pid_q, entry20_cmpmask_q}; - assign entry21_cam_vec = {entry21_epn_q, entry21_xbit_q, entry21_size_q, entry21_v_q, entry21_thdid_q, entry21_class_q, entry21_extclass_q, entry21_hv_q, entry21_ds_q, entry21_pid_q, entry21_cmpmask_q}; - assign entry22_cam_vec = {entry22_epn_q, entry22_xbit_q, entry22_size_q, entry22_v_q, entry22_thdid_q, entry22_class_q, entry22_extclass_q, entry22_hv_q, entry22_ds_q, entry22_pid_q, entry22_cmpmask_q}; - assign entry23_cam_vec = {entry23_epn_q, entry23_xbit_q, entry23_size_q, entry23_v_q, entry23_thdid_q, entry23_class_q, entry23_extclass_q, entry23_hv_q, entry23_ds_q, entry23_pid_q, entry23_cmpmask_q}; - assign entry24_cam_vec = {entry24_epn_q, entry24_xbit_q, entry24_size_q, entry24_v_q, entry24_thdid_q, entry24_class_q, entry24_extclass_q, entry24_hv_q, entry24_ds_q, entry24_pid_q, entry24_cmpmask_q}; - assign entry25_cam_vec = {entry25_epn_q, entry25_xbit_q, entry25_size_q, entry25_v_q, entry25_thdid_q, entry25_class_q, entry25_extclass_q, entry25_hv_q, entry25_ds_q, entry25_pid_q, entry25_cmpmask_q}; - assign entry26_cam_vec = {entry26_epn_q, entry26_xbit_q, entry26_size_q, entry26_v_q, entry26_thdid_q, entry26_class_q, entry26_extclass_q, entry26_hv_q, entry26_ds_q, entry26_pid_q, entry26_cmpmask_q}; - assign entry27_cam_vec = {entry27_epn_q, entry27_xbit_q, entry27_size_q, entry27_v_q, entry27_thdid_q, entry27_class_q, entry27_extclass_q, entry27_hv_q, entry27_ds_q, entry27_pid_q, entry27_cmpmask_q}; - assign entry28_cam_vec = {entry28_epn_q, entry28_xbit_q, entry28_size_q, entry28_v_q, entry28_thdid_q, entry28_class_q, entry28_extclass_q, entry28_hv_q, entry28_ds_q, entry28_pid_q, entry28_cmpmask_q}; - assign entry29_cam_vec = {entry29_epn_q, entry29_xbit_q, entry29_size_q, entry29_v_q, entry29_thdid_q, entry29_class_q, entry29_extclass_q, entry29_hv_q, entry29_ds_q, entry29_pid_q, entry29_cmpmask_q}; - assign entry30_cam_vec = {entry30_epn_q, entry30_xbit_q, entry30_size_q, entry30_v_q, entry30_thdid_q, entry30_class_q, entry30_extclass_q, entry30_hv_q, entry30_ds_q, entry30_pid_q, entry30_cmpmask_q}; - assign entry31_cam_vec = {entry31_epn_q, entry31_xbit_q, entry31_size_q, entry31_v_q, entry31_thdid_q, entry31_class_q, entry31_extclass_q, entry31_hv_q, entry31_ds_q, entry31_pid_q, entry31_cmpmask_q}; - - - assign cam_cmp_data_muxsel = {(~(comp_request)), cam_hit_entry_d}; - assign cam_cmp_data_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_cam_vec : - (cam_cmp_data_muxsel == 6'b000001) ? entry1_cam_vec : - (cam_cmp_data_muxsel == 6'b000010) ? entry2_cam_vec : - (cam_cmp_data_muxsel == 6'b000011) ? entry3_cam_vec : - (cam_cmp_data_muxsel == 6'b000100) ? entry4_cam_vec : - (cam_cmp_data_muxsel == 6'b000101) ? entry5_cam_vec : - (cam_cmp_data_muxsel == 6'b000110) ? entry6_cam_vec : - (cam_cmp_data_muxsel == 6'b000111) ? entry7_cam_vec : - (cam_cmp_data_muxsel == 6'b001000) ? entry8_cam_vec : - (cam_cmp_data_muxsel == 6'b001001) ? entry9_cam_vec : - (cam_cmp_data_muxsel == 6'b001010) ? entry10_cam_vec : - (cam_cmp_data_muxsel == 6'b001011) ? entry11_cam_vec : - (cam_cmp_data_muxsel == 6'b001100) ? entry12_cam_vec : - (cam_cmp_data_muxsel == 6'b001101) ? entry13_cam_vec : - (cam_cmp_data_muxsel == 6'b001110) ? entry14_cam_vec : - (cam_cmp_data_muxsel == 6'b001111) ? entry15_cam_vec : - (cam_cmp_data_muxsel == 6'b010000) ? entry16_cam_vec : - (cam_cmp_data_muxsel == 6'b010001) ? entry17_cam_vec : - (cam_cmp_data_muxsel == 6'b010010) ? entry18_cam_vec : - (cam_cmp_data_muxsel == 6'b010011) ? entry19_cam_vec : - (cam_cmp_data_muxsel == 6'b010100) ? entry20_cam_vec : - (cam_cmp_data_muxsel == 6'b010101) ? entry21_cam_vec : - (cam_cmp_data_muxsel == 6'b010110) ? entry22_cam_vec : - (cam_cmp_data_muxsel == 6'b010111) ? entry23_cam_vec : - (cam_cmp_data_muxsel == 6'b011000) ? entry24_cam_vec : - (cam_cmp_data_muxsel == 6'b011001) ? entry25_cam_vec : - (cam_cmp_data_muxsel == 6'b011010) ? entry26_cam_vec : - (cam_cmp_data_muxsel == 6'b011011) ? entry27_cam_vec : - (cam_cmp_data_muxsel == 6'b011100) ? entry28_cam_vec : - (cam_cmp_data_muxsel == 6'b011101) ? entry29_cam_vec : - (cam_cmp_data_muxsel == 6'b011110) ? entry30_cam_vec : - (cam_cmp_data_muxsel == 6'b011111) ? entry31_cam_vec : - cam_cmp_data_q; - - assign cam_cmp_data_np1 = cam_cmp_data_q; - - // CAM read data out mux - assign rd_cam_data_muxsel = {(~(rd_val)), rw_entry}; - - assign rd_cam_data_d = (rd_cam_data_muxsel == 6'b000000) ? entry0_cam_vec : - (rd_cam_data_muxsel == 6'b000001) ? entry1_cam_vec : - (rd_cam_data_muxsel == 6'b000010) ? entry2_cam_vec : - (rd_cam_data_muxsel == 6'b000011) ? entry3_cam_vec : - (rd_cam_data_muxsel == 6'b000100) ? entry4_cam_vec : - (rd_cam_data_muxsel == 6'b000101) ? entry5_cam_vec : - (rd_cam_data_muxsel == 6'b000110) ? entry6_cam_vec : - (rd_cam_data_muxsel == 6'b000111) ? entry7_cam_vec : - (rd_cam_data_muxsel == 6'b001000) ? entry8_cam_vec : - (rd_cam_data_muxsel == 6'b001001) ? entry9_cam_vec : - (rd_cam_data_muxsel == 6'b001010) ? entry10_cam_vec : - (rd_cam_data_muxsel == 6'b001011) ? entry11_cam_vec : - (rd_cam_data_muxsel == 6'b001100) ? entry12_cam_vec : - (rd_cam_data_muxsel == 6'b001101) ? entry13_cam_vec : - (rd_cam_data_muxsel == 6'b001110) ? entry14_cam_vec : - (rd_cam_data_muxsel == 6'b001111) ? entry15_cam_vec : - (rd_cam_data_muxsel == 6'b010000) ? entry16_cam_vec : - (rd_cam_data_muxsel == 6'b010001) ? entry17_cam_vec : - (rd_cam_data_muxsel == 6'b010010) ? entry18_cam_vec : - (rd_cam_data_muxsel == 6'b010011) ? entry19_cam_vec : - (rd_cam_data_muxsel == 6'b010100) ? entry20_cam_vec : - (rd_cam_data_muxsel == 6'b010101) ? entry21_cam_vec : - (rd_cam_data_muxsel == 6'b010110) ? entry22_cam_vec : - (rd_cam_data_muxsel == 6'b010111) ? entry23_cam_vec : - (rd_cam_data_muxsel == 6'b011000) ? entry24_cam_vec : - (rd_cam_data_muxsel == 6'b011001) ? entry25_cam_vec : - (rd_cam_data_muxsel == 6'b011010) ? entry26_cam_vec : - (rd_cam_data_muxsel == 6'b011011) ? entry27_cam_vec : - (rd_cam_data_muxsel == 6'b011100) ? entry28_cam_vec : - (rd_cam_data_muxsel == 6'b011101) ? entry29_cam_vec : - (rd_cam_data_muxsel == 6'b011110) ? entry30_cam_vec : - (rd_cam_data_muxsel == 6'b011111) ? entry31_cam_vec : - rd_cam_data_q; - - // CAM compare parity out mux - assign cam_cmp_parity_d = (cam_cmp_data_muxsel == 6'b000000) ? entry0_parity_q : - (cam_cmp_data_muxsel == 6'b000001) ? entry1_parity_q : - (cam_cmp_data_muxsel == 6'b000010) ? entry2_parity_q : - (cam_cmp_data_muxsel == 6'b000011) ? entry3_parity_q : - (cam_cmp_data_muxsel == 6'b000100) ? entry4_parity_q : - (cam_cmp_data_muxsel == 6'b000101) ? entry5_parity_q : - (cam_cmp_data_muxsel == 6'b000110) ? entry6_parity_q : - (cam_cmp_data_muxsel == 6'b000111) ? entry7_parity_q : - (cam_cmp_data_muxsel == 6'b001000) ? entry8_parity_q : - (cam_cmp_data_muxsel == 6'b001001) ? entry9_parity_q : - (cam_cmp_data_muxsel == 6'b001010) ? entry10_parity_q : - (cam_cmp_data_muxsel == 6'b001011) ? entry11_parity_q : - (cam_cmp_data_muxsel == 6'b001100) ? entry12_parity_q : - (cam_cmp_data_muxsel == 6'b001101) ? entry13_parity_q : - (cam_cmp_data_muxsel == 6'b001110) ? entry14_parity_q : - (cam_cmp_data_muxsel == 6'b001111) ? entry15_parity_q : - (cam_cmp_data_muxsel == 6'b010000) ? entry16_parity_q : - (cam_cmp_data_muxsel == 6'b010001) ? entry17_parity_q : - (cam_cmp_data_muxsel == 6'b010010) ? entry18_parity_q : - (cam_cmp_data_muxsel == 6'b010011) ? entry19_parity_q : - (cam_cmp_data_muxsel == 6'b010100) ? entry20_parity_q : - (cam_cmp_data_muxsel == 6'b010101) ? entry21_parity_q : - (cam_cmp_data_muxsel == 6'b010110) ? entry22_parity_q : - (cam_cmp_data_muxsel == 6'b010111) ? entry23_parity_q : - (cam_cmp_data_muxsel == 6'b011000) ? entry24_parity_q : - (cam_cmp_data_muxsel == 6'b011001) ? entry25_parity_q : - (cam_cmp_data_muxsel == 6'b011010) ? entry26_parity_q : - (cam_cmp_data_muxsel == 6'b011011) ? entry27_parity_q : - (cam_cmp_data_muxsel == 6'b011100) ? entry28_parity_q : - (cam_cmp_data_muxsel == 6'b011101) ? entry29_parity_q : - (cam_cmp_data_muxsel == 6'b011110) ? entry30_parity_q : - (cam_cmp_data_muxsel == 6'b011111) ? entry31_parity_q : - cam_cmp_parity_q; - - assign array_cmp_data_np1[0:50] = {array_cmp_data_bram[2:31], array_cmp_data_bram[34:39], array_cmp_data_bram[41:55]}; - assign array_cmp_data_np1[51:60] = cam_cmp_parity_q; - assign array_cmp_data_np1[61:67] = array_cmp_data_bramp[66:72]; - - assign array_cmp_data = array_cmp_data_np1; - - // CAM read parity out mux - assign rd_array_data_d[51:60] = (rd_cam_data_muxsel == 6'b000000) ? entry0_parity_q : - (rd_cam_data_muxsel == 6'b000001) ? entry1_parity_q : - (rd_cam_data_muxsel == 6'b000010) ? entry2_parity_q : - (rd_cam_data_muxsel == 6'b000011) ? entry3_parity_q : - (rd_cam_data_muxsel == 6'b000100) ? entry4_parity_q : - (rd_cam_data_muxsel == 6'b000101) ? entry5_parity_q : - (rd_cam_data_muxsel == 6'b000110) ? entry6_parity_q : - (rd_cam_data_muxsel == 6'b000111) ? entry7_parity_q : - (rd_cam_data_muxsel == 6'b001000) ? entry8_parity_q : - (rd_cam_data_muxsel == 6'b001001) ? entry9_parity_q : - (rd_cam_data_muxsel == 6'b001010) ? entry10_parity_q : - (rd_cam_data_muxsel == 6'b001011) ? entry11_parity_q : - (rd_cam_data_muxsel == 6'b001100) ? entry12_parity_q : - (rd_cam_data_muxsel == 6'b001101) ? entry13_parity_q : - (rd_cam_data_muxsel == 6'b001110) ? entry14_parity_q : - (rd_cam_data_muxsel == 6'b001111) ? entry15_parity_q : - (rd_cam_data_muxsel == 6'b010000) ? entry16_parity_q : - (rd_cam_data_muxsel == 6'b010001) ? entry17_parity_q : - (rd_cam_data_muxsel == 6'b010010) ? entry18_parity_q : - (rd_cam_data_muxsel == 6'b010011) ? entry19_parity_q : - (rd_cam_data_muxsel == 6'b010100) ? entry20_parity_q : - (rd_cam_data_muxsel == 6'b010101) ? entry21_parity_q : - (rd_cam_data_muxsel == 6'b010110) ? entry22_parity_q : - (rd_cam_data_muxsel == 6'b010111) ? entry23_parity_q : - (rd_cam_data_muxsel == 6'b011000) ? entry24_parity_q : - (rd_cam_data_muxsel == 6'b011001) ? entry25_parity_q : - (rd_cam_data_muxsel == 6'b011010) ? entry26_parity_q : - (rd_cam_data_muxsel == 6'b011011) ? entry27_parity_q : - (rd_cam_data_muxsel == 6'b011100) ? entry28_parity_q : - (rd_cam_data_muxsel == 6'b011101) ? entry29_parity_q : - (rd_cam_data_muxsel == 6'b011110) ? entry30_parity_q : - (rd_cam_data_muxsel == 6'b011111) ? entry31_parity_q : - rd_array_data_q[51:60]; - - // internal bypass latch input for rpn - // using cam_cmp_data(75:78) cmpmask bits for mux selects - assign rpn_np2_d[22:33] = (comp_addr_np1_q[22:33] & {12{bypass_mux_enab_np1}}) | - (array_cmp_data_np1[0:11] & {12{~(bypass_mux_enab_np1)}}); // real page from cam-array - - //CAM_PgSize_1GB - assign rpn_np2_d[34:39] = (comp_addr_np1_q[34:39] & {6{(~(cam_cmp_data_np1[75])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[12:17] & {6{cam_cmp_data_np1[75] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_1GB or CAM_PgSize_16MB - assign rpn_np2_d[40:43] = (comp_addr_np1_q[40:43] & {4{(~(cam_cmp_data_np1[76])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[18:21] & {4{cam_cmp_data_np1[76] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_1GB or CAM_PgSize_16MB or CAM_PgSize_1MB - assign rpn_np2_d[44:47] = (comp_addr_np1_q[44:47] & {4{(~(cam_cmp_data_np1[77])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[22:25] & {4{cam_cmp_data_np1[77] & (~bypass_mux_enab_np1)}}); - - //CAM_PgSize_Larger_than_4K - assign rpn_np2_d[48:51] = (comp_addr_np1_q[48:51] & {4{(~(cam_cmp_data_np1[78])) | bypass_mux_enab_np1}}) | - (array_cmp_data_np1[26:29] & {4{cam_cmp_data_np1[78] & (~bypass_mux_enab_np1)}}); - - // internal bypass latch input for attributes - assign attr_np2_d[0:20] = (bypass_attr_np1[0:20] & {21{bypass_mux_enab_np1}}) | - (array_cmp_data_np1[30:50] & {21{~bypass_mux_enab_np1}}); - - // new port output assignments - assign rpn_np2[22:51] = rpn_np2_q[22:51]; - assign attr_np2[0:20] = attr_np2_q[0:20]; - - //--------------------------------------------------------------------- - // matchline component instantiations - //--------------------------------------------------------------------- - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb0( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry0_size_q), - .entry_cmpmask(entry0_cmpmask_q[0:3]), - .entry_xbit(entry0_xbit_q), - .entry_xbitmask(entry0_cmpmask_q[4:7]), - .entry_epn(entry0_epn_q), - .comp_class(comp_class), - .entry_class(entry0_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry0_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry0_hv_q), - .entry_ds(entry0_ds_q), - .state_enable(state_enable), - .entry_thdid(entry0_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry0_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry0_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[0]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb1( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry1_size_q), - .entry_cmpmask(entry1_cmpmask_q[0:3]), - .entry_xbit(entry1_xbit_q), - .entry_xbitmask(entry1_cmpmask_q[4:7]), - .entry_epn(entry1_epn_q), - .comp_class(comp_class), - .entry_class(entry1_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry1_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry1_hv_q), - .entry_ds(entry1_ds_q), - .state_enable(state_enable), - .entry_thdid(entry1_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry1_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry1_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[1]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb2( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry2_size_q), - .entry_cmpmask(entry2_cmpmask_q[0:3]), - .entry_xbit(entry2_xbit_q), - .entry_xbitmask(entry2_cmpmask_q[4:7]), - .entry_epn(entry2_epn_q), - .comp_class(comp_class), - .entry_class(entry2_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry2_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry2_hv_q), - .entry_ds(entry2_ds_q), - .state_enable(state_enable), - .entry_thdid(entry2_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry2_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry2_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[2]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb3( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry3_size_q), - .entry_cmpmask(entry3_cmpmask_q[0:3]), - .entry_xbit(entry3_xbit_q), - .entry_xbitmask(entry3_cmpmask_q[4:7]), - .entry_epn(entry3_epn_q), - .comp_class(comp_class), - .entry_class(entry3_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry3_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry3_hv_q), - .entry_ds(entry3_ds_q), - .state_enable(state_enable), - .entry_thdid(entry3_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry3_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry3_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[3]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb4( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry4_size_q), - .entry_cmpmask(entry4_cmpmask_q[0:3]), - .entry_xbit(entry4_xbit_q), - .entry_xbitmask(entry4_cmpmask_q[4:7]), - .entry_epn(entry4_epn_q), - .comp_class(comp_class), - .entry_class(entry4_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry4_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry4_hv_q), - .entry_ds(entry4_ds_q), - .state_enable(state_enable), - .entry_thdid(entry4_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry4_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry4_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[4]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb5( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry5_size_q), - .entry_cmpmask(entry5_cmpmask_q[0:3]), - .entry_xbit(entry5_xbit_q), - .entry_xbitmask(entry5_cmpmask_q[4:7]), - .entry_epn(entry5_epn_q), - .comp_class(comp_class), - .entry_class(entry5_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry5_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry5_hv_q), - .entry_ds(entry5_ds_q), - .state_enable(state_enable), - .entry_thdid(entry5_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry5_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry5_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[5]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb6( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry6_size_q), - .entry_cmpmask(entry6_cmpmask_q[0:3]), - .entry_xbit(entry6_xbit_q), - .entry_xbitmask(entry6_cmpmask_q[4:7]), - .entry_epn(entry6_epn_q), - .comp_class(comp_class), - .entry_class(entry6_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry6_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry6_hv_q), - .entry_ds(entry6_ds_q), - .state_enable(state_enable), - .entry_thdid(entry6_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry6_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry6_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[6]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb7( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry7_size_q), - .entry_cmpmask(entry7_cmpmask_q[0:3]), - .entry_xbit(entry7_xbit_q), - .entry_xbitmask(entry7_cmpmask_q[4:7]), - .entry_epn(entry7_epn_q), - .comp_class(comp_class), - .entry_class(entry7_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry7_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry7_hv_q), - .entry_ds(entry7_ds_q), - .state_enable(state_enable), - .entry_thdid(entry7_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry7_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry7_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[7]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb8( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry8_size_q), - .entry_cmpmask(entry8_cmpmask_q[0:3]), - .entry_xbit(entry8_xbit_q), - .entry_xbitmask(entry8_cmpmask_q[4:7]), - .entry_epn(entry8_epn_q), - .comp_class(comp_class), - .entry_class(entry8_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry8_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry8_hv_q), - .entry_ds(entry8_ds_q), - .state_enable(state_enable), - .entry_thdid(entry8_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry8_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry8_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[8]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb9( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry9_size_q), - .entry_cmpmask(entry9_cmpmask_q[0:3]), - .entry_xbit(entry9_xbit_q), - .entry_xbitmask(entry9_cmpmask_q[4:7]), - .entry_epn(entry9_epn_q), - .comp_class(comp_class), - .entry_class(entry9_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry9_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry9_hv_q), - .entry_ds(entry9_ds_q), - .state_enable(state_enable), - .entry_thdid(entry9_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry9_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry9_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[9]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb10( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry10_size_q), - .entry_cmpmask(entry10_cmpmask_q[0:3]), - .entry_xbit(entry10_xbit_q), - .entry_xbitmask(entry10_cmpmask_q[4:7]), - .entry_epn(entry10_epn_q), - .comp_class(comp_class), - .entry_class(entry10_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry10_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry10_hv_q), - .entry_ds(entry10_ds_q), - .state_enable(state_enable), - .entry_thdid(entry10_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry10_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry10_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[10]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb11( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry11_size_q), - .entry_cmpmask(entry11_cmpmask_q[0:3]), - .entry_xbit(entry11_xbit_q), - .entry_xbitmask(entry11_cmpmask_q[4:7]), - .entry_epn(entry11_epn_q), - .comp_class(comp_class), - .entry_class(entry11_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry11_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry11_hv_q), - .entry_ds(entry11_ds_q), - .state_enable(state_enable), - .entry_thdid(entry11_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry11_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry11_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[11]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb12( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry12_size_q), - .entry_cmpmask(entry12_cmpmask_q[0:3]), - .entry_xbit(entry12_xbit_q), - .entry_xbitmask(entry12_cmpmask_q[4:7]), - .entry_epn(entry12_epn_q), - .comp_class(comp_class), - .entry_class(entry12_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry12_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry12_hv_q), - .entry_ds(entry12_ds_q), - .state_enable(state_enable), - .entry_thdid(entry12_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry12_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry12_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[12]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb13( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry13_size_q), - .entry_cmpmask(entry13_cmpmask_q[0:3]), - .entry_xbit(entry13_xbit_q), - .entry_xbitmask(entry13_cmpmask_q[4:7]), - .entry_epn(entry13_epn_q), - .comp_class(comp_class), - .entry_class(entry13_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry13_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry13_hv_q), - .entry_ds(entry13_ds_q), - .state_enable(state_enable), - .entry_thdid(entry13_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry13_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry13_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[13]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb14( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry14_size_q), - .entry_cmpmask(entry14_cmpmask_q[0:3]), - .entry_xbit(entry14_xbit_q), - .entry_xbitmask(entry14_cmpmask_q[4:7]), - .entry_epn(entry14_epn_q), - .comp_class(comp_class), - .entry_class(entry14_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry14_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry14_hv_q), - .entry_ds(entry14_ds_q), - .state_enable(state_enable), - .entry_thdid(entry14_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry14_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry14_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[14]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb15( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry15_size_q), - .entry_cmpmask(entry15_cmpmask_q[0:3]), - .entry_xbit(entry15_xbit_q), - .entry_xbitmask(entry15_cmpmask_q[4:7]), - .entry_epn(entry15_epn_q), - .comp_class(comp_class), - .entry_class(entry15_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry15_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry15_hv_q), - .entry_ds(entry15_ds_q), - .state_enable(state_enable), - .entry_thdid(entry15_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry15_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry15_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[15]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb16( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry16_size_q), - .entry_cmpmask(entry16_cmpmask_q[0:3]), - .entry_xbit(entry16_xbit_q), - .entry_xbitmask(entry16_cmpmask_q[4:7]), - .entry_epn(entry16_epn_q), - .comp_class(comp_class), - .entry_class(entry16_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry16_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry16_hv_q), - .entry_ds(entry16_ds_q), - .state_enable(state_enable), - .entry_thdid(entry16_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry16_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry16_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[16]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb17( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry17_size_q), - .entry_cmpmask(entry17_cmpmask_q[0:3]), - .entry_xbit(entry17_xbit_q), - .entry_xbitmask(entry17_cmpmask_q[4:7]), - .entry_epn(entry17_epn_q), - .comp_class(comp_class), - .entry_class(entry17_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry17_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry17_hv_q), - .entry_ds(entry17_ds_q), - .state_enable(state_enable), - .entry_thdid(entry17_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry17_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry17_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[17]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb18( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry18_size_q), - .entry_cmpmask(entry18_cmpmask_q[0:3]), - .entry_xbit(entry18_xbit_q), - .entry_xbitmask(entry18_cmpmask_q[4:7]), - .entry_epn(entry18_epn_q), - .comp_class(comp_class), - .entry_class(entry18_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry18_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry18_hv_q), - .entry_ds(entry18_ds_q), - .state_enable(state_enable), - .entry_thdid(entry18_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry18_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry18_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[18]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb19( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry19_size_q), - .entry_cmpmask(entry19_cmpmask_q[0:3]), - .entry_xbit(entry19_xbit_q), - .entry_xbitmask(entry19_cmpmask_q[4:7]), - .entry_epn(entry19_epn_q), - .comp_class(comp_class), - .entry_class(entry19_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry19_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry19_hv_q), - .entry_ds(entry19_ds_q), - .state_enable(state_enable), - .entry_thdid(entry19_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry19_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry19_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[19]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb20( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry20_size_q), - .entry_cmpmask(entry20_cmpmask_q[0:3]), - .entry_xbit(entry20_xbit_q), - .entry_xbitmask(entry20_cmpmask_q[4:7]), - .entry_epn(entry20_epn_q), - .comp_class(comp_class), - .entry_class(entry20_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry20_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry20_hv_q), - .entry_ds(entry20_ds_q), - .state_enable(state_enable), - .entry_thdid(entry20_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry20_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry20_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[20]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb21( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry21_size_q), - .entry_cmpmask(entry21_cmpmask_q[0:3]), - .entry_xbit(entry21_xbit_q), - .entry_xbitmask(entry21_cmpmask_q[4:7]), - .entry_epn(entry21_epn_q), - .comp_class(comp_class), - .entry_class(entry21_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry21_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry21_hv_q), - .entry_ds(entry21_ds_q), - .state_enable(state_enable), - .entry_thdid(entry21_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry21_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry21_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[21]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb22( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry22_size_q), - .entry_cmpmask(entry22_cmpmask_q[0:3]), - .entry_xbit(entry22_xbit_q), - .entry_xbitmask(entry22_cmpmask_q[4:7]), - .entry_epn(entry22_epn_q), - .comp_class(comp_class), - .entry_class(entry22_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry22_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry22_hv_q), - .entry_ds(entry22_ds_q), - .state_enable(state_enable), - .entry_thdid(entry22_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry22_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry22_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[22]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb23( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry23_size_q), - .entry_cmpmask(entry23_cmpmask_q[0:3]), - .entry_xbit(entry23_xbit_q), - .entry_xbitmask(entry23_cmpmask_q[4:7]), - .entry_epn(entry23_epn_q), - .comp_class(comp_class), - .entry_class(entry23_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry23_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry23_hv_q), - .entry_ds(entry23_ds_q), - .state_enable(state_enable), - .entry_thdid(entry23_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry23_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry23_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[23]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb24( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry24_size_q), - .entry_cmpmask(entry24_cmpmask_q[0:3]), - .entry_xbit(entry24_xbit_q), - .entry_xbitmask(entry24_cmpmask_q[4:7]), - .entry_epn(entry24_epn_q), - .comp_class(comp_class), - .entry_class(entry24_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry24_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry24_hv_q), - .entry_ds(entry24_ds_q), - .state_enable(state_enable), - .entry_thdid(entry24_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry24_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry24_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[24]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb25( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry25_size_q), - .entry_cmpmask(entry25_cmpmask_q[0:3]), - .entry_xbit(entry25_xbit_q), - .entry_xbitmask(entry25_cmpmask_q[4:7]), - .entry_epn(entry25_epn_q), - .comp_class(comp_class), - .entry_class(entry25_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry25_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry25_hv_q), - .entry_ds(entry25_ds_q), - .state_enable(state_enable), - .entry_thdid(entry25_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry25_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry25_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[25]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb26( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry26_size_q), - .entry_cmpmask(entry26_cmpmask_q[0:3]), - .entry_xbit(entry26_xbit_q), - .entry_xbitmask(entry26_cmpmask_q[4:7]), - .entry_epn(entry26_epn_q), - .comp_class(comp_class), - .entry_class(entry26_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry26_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry26_hv_q), - .entry_ds(entry26_ds_q), - .state_enable(state_enable), - .entry_thdid(entry26_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry26_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry26_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[26]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb27( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry27_size_q), - .entry_cmpmask(entry27_cmpmask_q[0:3]), - .entry_xbit(entry27_xbit_q), - .entry_xbitmask(entry27_cmpmask_q[4:7]), - .entry_epn(entry27_epn_q), - .comp_class(comp_class), - .entry_class(entry27_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry27_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry27_hv_q), - .entry_ds(entry27_ds_q), - .state_enable(state_enable), - .entry_thdid(entry27_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry27_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry27_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[27]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb28( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry28_size_q), - .entry_cmpmask(entry28_cmpmask_q[0:3]), - .entry_xbit(entry28_xbit_q), - .entry_xbitmask(entry28_cmpmask_q[4:7]), - .entry_epn(entry28_epn_q), - .comp_class(comp_class), - .entry_class(entry28_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry28_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry28_hv_q), - .entry_ds(entry28_ds_q), - .state_enable(state_enable), - .entry_thdid(entry28_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry28_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry28_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[28]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb29( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry29_size_q), - .entry_cmpmask(entry29_cmpmask_q[0:3]), - .entry_xbit(entry29_xbit_q), - .entry_xbitmask(entry29_cmpmask_q[4:7]), - .entry_epn(entry29_epn_q), - .comp_class(comp_class), - .entry_class(entry29_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry29_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry29_hv_q), - .entry_ds(entry29_ds_q), - .state_enable(state_enable), - .entry_thdid(entry29_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry29_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry29_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[29]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb30( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry30_size_q), - .entry_cmpmask(entry30_cmpmask_q[0:3]), - .entry_xbit(entry30_xbit_q), - .entry_xbitmask(entry30_cmpmask_q[4:7]), - .entry_epn(entry30_epn_q), - .comp_class(comp_class), - .entry_class(entry30_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry30_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry30_hv_q), - .entry_ds(entry30_ds_q), - .state_enable(state_enable), - .entry_thdid(entry30_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry30_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry30_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[30]) - ); - - tri_cam_32x143_1r1w1c_matchline #(.HAVE_XBIT(1), .NUM_PGSIZES(5), .HAVE_CMPMASK(1), .CMPMASK_WIDTH(4)) matchline_comb31( - .addr_in(comp_addr), - .addr_enable(addr_enable), - .comp_pgsize(comp_pgsize), - .pgsize_enable(pgsize_enable), - .entry_size(entry31_size_q), - .entry_cmpmask(entry31_cmpmask_q[0:3]), - .entry_xbit(entry31_xbit_q), - .entry_xbitmask(entry31_cmpmask_q[4:7]), - .entry_epn(entry31_epn_q), - .comp_class(comp_class), - .entry_class(entry31_class_q), - .class_enable(class_enable), - .comp_extclass(comp_extclass), - .entry_extclass(entry31_extclass_q), - .extclass_enable(extclass_enable), - .comp_state(comp_state), - .entry_hv(entry31_hv_q), - .entry_ds(entry31_ds_q), - .state_enable(state_enable), - .entry_thdid(entry31_thdid_q), - .comp_thdid(comp_thdid), - .thdid_enable(thdid_enable), - .entry_pid(entry31_pid_q), - .comp_pid(comp_pid), - .pid_enable(pid_enable), - .entry_v(entry31_v_q), - .comp_invalidate(comp_invalidate), - - .match(match_vec[31]) - ); - - //--------------------------------------------------------------------- - // BRAM signal assignments - //--------------------------------------------------------------------- - assign bram0_wea = wr_array_val[0]; - assign bram1_wea = wr_array_val[1]; - assign bram2_wea = wr_array_val[1]; - - assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - assign bram2_addra[10 - NUM_ENTRY_LOG2:9] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; - - assign bram0_addrb[9 - NUM_ENTRY_LOG2:8] = cam_hit_entry_q; - assign bram1_addrb[11 - NUM_ENTRY_LOG2:10] = cam_hit_entry_q; - assign bram2_addrb[10 - NUM_ENTRY_LOG2:9] = cam_hit_entry_q; - - // Unused Address Bits - assign bram0_addra[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; - assign bram0_addrb[0:8 - NUM_ENTRY_LOG2] = {9-NUM_ENTRY_LOG2{1'b0}}; - assign bram1_addra[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; - assign bram1_addrb[0:10 - NUM_ENTRY_LOG2] = {11-NUM_ENTRY_LOG2{1'b0}}; - assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; - assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; - -// was 3 brams using clk2x w/wea on 2of2; matchline is combinational - always @(posedge clk) begin - - if (bram0_wea) begin - mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; - end - if (bram1_wea) begin - mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; - end - - end - - assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; - assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; - assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; - assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; - -/* - // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) - // uses wr_array_val(0), parity is wr_array_data_bram(66:69) - RAMB16_S36_S36 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram0( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram0_addra), - .ADDRB(bram0_addrb), - .DIA(wr_array_data_bram[0:31]), - .DIB(32'b0), - .DOA(rd_array_data_d_std[0:31]), - .DOB(array_cmp_data_bram_std[0:31]), - .DOPA(rd_array_data_d_std[66:69]), - .DOPB(array_cmp_data_bramp_std[66:69]), - .DIPA(wr_array_data_bram[66:69]), - .DIPB(4'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram0_wea), - .WEB(1'b0) - ); - - // This ram houses the RPN(18:19),R,C,4xResv bits, wr_array_data_bram(32:39) - // uses wr_array_val(1), parity is wr_array_data_bram(70) - RAMB16_S9_S9 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram1( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram1_addra), - .ADDRB(bram1_addrb), - .DIA(wr_array_data_bram[32:39]), - .DIB(8'b0), - .DOA(rd_array_data_d_std[32:39]), - .DOB(array_cmp_data_bram_std[32:39]), - .DOPA(rd_array_data_d_std[70:70]), - .DOPB(array_cmp_data_bramp_std[70:70]), - .DIPA(wr_array_data_bram[70:70]), - .DIPB(1'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram1_wea), - .WEB(1'b0) - ); - - // This ram houses the 1xResv,U0-U3,WIMGE,UX,UW,UR,SX,SW,SR bits, wr_array_data_bram(40:55) - // uses wr_array_val(2), parity is wr_array_data_bram(71:72) - RAMB16_S18_S18 - #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only - bram2( - .CLKA(clk2x), - .CLKB(clk2x), - .SSRA(sreset_q), - .SSRB(sreset_q), - .ADDRA(bram2_addra), - .ADDRB(bram2_addrb), - .DIA(wr_array_data_bram[40:55]), - .DIB(16'b0), - .DOA(rd_array_data_d_std[40:55]), - .DOB(array_cmp_data_bram_std[40:55]), - .DOPA(rd_array_data_d_std[71:72]), - .DOPB(array_cmp_data_bramp_std[71:72]), - .DIPA(wr_array_data_bram[71:72]), - .DIPB(2'b0), - .ENA(1'b1), - .ENB(1'b1), - .WEA(bram2_wea), - .WEB(1'b0) - ); - */ - - // array write data swizzle -> convert 68-bit data to 73-bit bram data - // 32x143 version, 42b RA - // wr_array_data - // 0:29 - RPN - // 30:31 - R,C - // 32:35 - ResvAttr - // 36:39 - U0-U3 - // 40:44 - WIMGE - // 45:47 - UX,UW,UR - // 48:50 - SX,SW,SR - // 51:60 - CAM parity - // 61:67 - Array parity - // - // RTX layout in A2_AvpEratHelper.C - // ram0(0:31): 00 & RPN(0:29) - // ram1(0:7) : 00 & R,C,ResvAttr(0:3) - // ram2(0:15): '0' & U(0:3),WIMGE,UX,UW,UR,SX,SW,SR - assign wr_array_data_bram[0:72] = {2'b00, wr_array_data[0:29], 2'b00, wr_array_data[30:35], 1'b0, wr_array_data[36:50], wr_array_data[51:60], wr_array_data[61:67]}; - - assign rd_array_data_d_std[56:65] = 10'b0; // tie off unused bits - - assign rd_array_data_d[0:29] = rd_array_data_d_std[2:31]; - assign rd_array_data_d[30:35] = rd_array_data_d_std[34:39]; - assign rd_array_data_d[36:50] = rd_array_data_d_std[41:55]; - assign rd_array_data_d[61:67] = rd_array_data_d_std[66:72]; - assign array_cmp_data_bram = array_cmp_data_bram_std; - assign array_cmp_data_bramp = array_cmp_data_bramp_std; - - //--------------------------------------------------------------------- - // entity output assignments - //--------------------------------------------------------------------- - assign rd_array_data = rd_array_data_q; - assign cam_cmp_data = cam_cmp_data_q; - assign rd_cam_data = rd_cam_data_q; - - assign entry_valid[0] = entry0_v_q; - assign entry_valid[1] = entry1_v_q; - assign entry_valid[2] = entry2_v_q; - assign entry_valid[3] = entry3_v_q; - assign entry_valid[4] = entry4_v_q; - assign entry_valid[5] = entry5_v_q; - assign entry_valid[6] = entry6_v_q; - assign entry_valid[7] = entry7_v_q; - assign entry_valid[8] = entry8_v_q; - assign entry_valid[9] = entry9_v_q; - assign entry_valid[10] = entry10_v_q; - assign entry_valid[11] = entry11_v_q; - assign entry_valid[12] = entry12_v_q; - assign entry_valid[13] = entry13_v_q; - assign entry_valid[14] = entry14_v_q; - assign entry_valid[15] = entry15_v_q; - assign entry_valid[16] = entry16_v_q; - assign entry_valid[17] = entry17_v_q; - assign entry_valid[18] = entry18_v_q; - assign entry_valid[19] = entry19_v_q; - assign entry_valid[20] = entry20_v_q; - assign entry_valid[21] = entry21_v_q; - assign entry_valid[22] = entry22_v_q; - assign entry_valid[23] = entry23_v_q; - assign entry_valid[24] = entry24_v_q; - assign entry_valid[25] = entry25_v_q; - assign entry_valid[26] = entry26_v_q; - assign entry_valid[27] = entry27_v_q; - assign entry_valid[28] = entry28_v_q; - assign entry_valid[29] = entry29_v_q; - assign entry_valid[30] = entry30_v_q; - assign entry_valid[31] = entry31_v_q; - - assign entry_match = entry_match_q; - - assign cam_hit_entry = cam_hit_entry_q; - assign cam_hit = cam_hit_q; - - assign func_scan_out = func_scan_in; - assign regfile_scan_out = regfile_scan_in; - assign time_scan_out = time_scan_in; - - assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, - tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, - lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, - pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, - pc_time_sl_thold_2, pc_fce_2, array_cmp_data_bram[0:1], array_cmp_data_bram[32:33], - array_cmp_data_bram[40], wr_array_data_bram[56:65], - cam_cmp_data_np1[0:74], cam_cmp_data_np1[79:CAM_DATA_WIDTH-1], - rd_array_data_d_std[0:1], rd_array_data_d_std[32:33], - rd_array_data_d_std[40], rd_array_data_d_std[56:65], rd_val_late, wr_val_early}; -endmodule diff --git a/dev/verilog/work/c.v b/dev/verilog/work/c.v index 9c70447..d52d152 100755 --- a/dev/verilog/work/c.v +++ b/dev/verilog/work/c.v @@ -44,7 +44,8 @@ module c( // inout vcs, // inout vdd, // inout gnd, - input[0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_in, output scan_out, @@ -191,8 +192,11 @@ module c( ); - + `ifndef FLOAT_TYPE parameter float_type = 1; + `else + parameter float_type = `FLOAT_TYPE; + `endif // I$ // Cache inject @@ -1816,7 +1820,8 @@ module c( //.vcs(vcs), //.vdd(vdd), //.gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_3(rp_iu_sg_3), .pc_iu_fce_3(rp_iu_fce_3), .pc_iu_func_slp_sl_thold_3(rp_iu_func_slp_sl_thold_3), @@ -2514,7 +2519,8 @@ module c( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - .nclk(nclk), + .clk(clk), + .rst(rst), // .vcs(vcs), // .vdd(vdd), // .gnd(gnd), @@ -3159,6 +3165,8 @@ module c( rv rv0( + .clk(clk), + .rst(rst), //------------------------------------------------------------------- // Instructions from IU @@ -3637,7 +3645,6 @@ module c( //------------------------------------------------------------------- //.vdd(vdd), //.gnd(gnd), - .nclk(nclk), .rp_rv_ccflush_dc(rp_rv_ccflush_dc), .rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3), @@ -3654,6 +3661,9 @@ module c( lq lq0( + .clk(clk), + .rst(rst), + //-------------------------------------------------------------- // SPR Interface //-------------------------------------------------------------- @@ -4088,7 +4098,6 @@ module c( //.vcs(vcs), //.vdd(vdd), //.gnd(gnd), - .nclk(nclk), //--Thold inputs .pc_lq_init_reset(pc_lq_init_reset), @@ -4166,13 +4175,13 @@ module c( .func_scan_out(scan_out_lq) ); - // 6=64-bit model, 5=32-bit model mmq mmu0( // .vcs(vcs), // .vdd(vdd), // .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(rp_mm_ccflush_dc), .tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), @@ -4456,12 +4465,12 @@ module c( ); - c_fu_pc #(.float_type(float_type)) fupc( // .vdd(vdd), // .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .fu_debug_bus_in(fu_debug_bus_in), .fu_debug_bus_out(fu_debug_bus_out), @@ -4853,7 +4862,8 @@ module c( perv_rp( // .vdd(vdd), // .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), //CLOCK CONTROLS //Top level clock controls diff --git a/dev/verilog/work/c_fu_pc.v b/dev/verilog/work/c_fu_pc.v index 6e28f77..b8e0e6d 100755 --- a/dev/verilog/work/c_fu_pc.v +++ b/dev/verilog/work/c_fu_pc.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -36,30 +36,35 @@ //* //***************************************************************************** -(* recursive_synthesis=0 *) +//wtf: move pcq to top-level? keep this as c_fu to do the float_type generate + +`include "tri_a2o.vh" +`ifndef FLOAT_TYPE +`define FLOAT_TYPE 1 +`endif module c_fu_pc( - `include "tri_a2o.vh" + // ---------------------------------------------------------------------- // Common I/O Ports // ---------------------------------------------------------------------- // inout vdd, // inout gnd, - (* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, - input [0:31] fu_debug_bus_in, - output [0:31] fu_debug_bus_out, - input [0:3] fu_coretrace_ctrls_in, - output [0:3] fu_coretrace_ctrls_out, - input [0:4*`THREADS-1] fu_event_bus_in, - output [0:4*`THREADS-1] fu_event_bus_out, + input [0:31] fu_debug_bus_in, + output [0:31] fu_debug_bus_out, + input [0:3] fu_coretrace_ctrls_in, + output [0:3] fu_coretrace_ctrls_out, + input [0:4*`THREADS-1] fu_event_bus_in, + output [0:4*`THREADS-1] fu_event_bus_out, - input [0:31] pc_debug_bus_in, - output [0:31] pc_debug_bus_out, - input [0:3] pc_coretrace_ctrls_in, - output [0:3] pc_coretrace_ctrls_out, + input [0:31] pc_debug_bus_in, + output [0:31] pc_debug_bus_out, + input [0:3] pc_coretrace_ctrls_in, + output [0:3] pc_coretrace_ctrls_out, (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in input fu_gptr_scan_in, @@ -466,8 +471,7 @@ module c_fu_pc( // ###################### CONSTANTS ###################### -- - parameter float_type = 1; - + parameter float_type = `FLOAT_TYPE; // ####################### SIGNALS ####################### -- @@ -516,7 +520,8 @@ module c_fu_pc( pc0( // .vdd(vdd), // .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), //SCOM Satellite .an_ac_scom_sat_id(an_ac_scom_sat_id), .an_ac_scom_dch(an_ac_scom_dch), @@ -795,7 +800,8 @@ module c_fu_pc( //.gnd(gnd), //.vcs(vcs), //.vdd(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .debug_bus_in(fu_debug_bus_in), .debug_bus_out(fu_debug_bus_out), @@ -1009,17 +1015,17 @@ module c_fu_pc( assign axu0_rv_itag_vld = {`THREADS{1'b0}}; assign axu1_rv_itag_vld = {`THREADS{1'b0}}; - assign fu_slowspr_val_out = fu_slowspr_val_in; - assign fu_slowspr_rw_out = fu_slowspr_rw_in; - assign fu_slowspr_etid_out = fu_slowspr_etid_in; - assign fu_slowspr_addr_out = fu_slowspr_addr_in; - assign fu_slowspr_data_out = fu_slowspr_data_in; - assign fu_slowspr_done_out = fu_slowspr_done_in; + assign fu_slowspr_val_out = fu_slowspr_val_in; + assign fu_slowspr_rw_out = fu_slowspr_rw_in; + assign fu_slowspr_etid_out = fu_slowspr_etid_in; + assign fu_slowspr_addr_out = fu_slowspr_addr_in; + assign fu_slowspr_data_out = fu_slowspr_data_in; + assign fu_slowspr_done_out = fu_slowspr_done_in; - assign fu_debug_bus_out = fu_debug_bus_in; + assign fu_debug_bus_out = fu_debug_bus_in; assign fu_coretrace_ctrls_out = fu_coretrace_ctrls_in; - assign fu_event_bus_out = fu_event_bus_in; + assign fu_event_bus_out = fu_event_bus_in; assign fu_pc_err_regfile_parity = {`THREADS{1'b0}}; assign fu_pc_err_regfile_ue = {`THREADS{1'b0}}; diff --git a/dev/verilog/work/c_perv_rp.v b/dev/verilog/work/c_perv_rp.v index 3a59c5a..e5c2c0a 100755 --- a/dev/verilog/work/c_perv_rp.v +++ b/dev/verilog/work/c_perv_rp.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -37,7 +37,8 @@ module c_perv_rp( // inout vdd, // inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, //CLOCK CONTROLS //Top level clock controls input an_ac_ccflush_dc, @@ -327,7 +328,8 @@ module c_perv_rp( tri_plat #(.WIDTH(6)) perv_4to3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4, @@ -340,7 +342,8 @@ module c_perv_rp( tri_plat #(.WIDTH(6)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int, @@ -353,7 +356,8 @@ module c_perv_rp( tri_plat #(.WIDTH(6)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2, @@ -366,7 +370,8 @@ module c_perv_rp( tri_plat #(.WIDTH(6)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1, @@ -381,7 +386,8 @@ module c_perv_rp( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_in), .scan_diag_dc(scan_diag_dc), .thold(gptr_sl_thold_0), @@ -432,7 +438,8 @@ module c_perv_rp( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(func_slat_thold_b), .dclk(func_slat_d2clk), @@ -443,7 +450,8 @@ module c_perv_rp( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(abst_slat_thold_b), .dclk(abst_slat_d2clk), @@ -454,7 +462,8 @@ module c_perv_rp( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(cfg_slat_thold_b), .dclk(cfg_slat_d2clk), @@ -468,7 +477,8 @@ module c_perv_rp( tri_plat #(.WIDTH(6)) pcq_lvl8to7( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(an_ac_ccflush_dc), .din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8, @@ -489,7 +499,8 @@ module c_perv_rp( tri_plat #(.WIDTH(16)) iu_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, @@ -508,7 +519,8 @@ module c_perv_rp( tri_plat #(.WIDTH(15)) rv_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, @@ -527,7 +539,8 @@ module c_perv_rp( tri_plat #(.WIDTH(16)) xu_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, @@ -546,7 +559,8 @@ module c_perv_rp( tri_plat #(.WIDTH(16)) lq_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, @@ -565,7 +579,8 @@ module c_perv_rp( tri_plat #(.WIDTH(15)) mm_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_rp_ccflush_out_dc), .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, @@ -642,7 +657,8 @@ module c_perv_rp( tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(1'b1), .thold_b(func_slp_sl_thold_0_b), .sg(sg_0), @@ -674,7 +690,8 @@ module c_perv_rp( tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(1'b1), .thold_b(func_slp_sl_thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/fu.v b/dev/verilog/work/fu.v index fbe68be..de84276 100755 --- a/dev/verilog/work/fu.v +++ b/dev/verilog/work/fu.v @@ -90,7 +90,8 @@ module fu( lq_rv_itag0_spec, lq_rv_itag0_vld, lq_rv_itag1_restart, - nclk, + clk, + rst, pc_fu_abist_di_0, pc_fu_abist_di_1, pc_fu_abist_ena_dc, @@ -238,6 +239,8 @@ module fu( // parameter UCODE_ENTRIES_ENC = 3; // parameter REGMODE = 6; //32 or 64 bit mode //INPUTS + input clk; + input rst; input abst_scan_in; input an_ac_lbist_en_dc; input bcfg_scan_in; @@ -300,8 +303,6 @@ module fu( input lq_rv_itag0_spec; input lq_rv_itag0_vld; input lq_rv_itag1_restart; - (* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk; input [0:3] pc_fu_abist_di_0; input [0:3] pc_fu_abist_di_1; input pc_fu_abist_ena_dc; @@ -766,7 +767,8 @@ module fu( fu_perv prv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_fu_sg_3(pc_fu_sg_3), .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), @@ -803,7 +805,8 @@ module fu( // Floating Point Register, ex0 fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC)) fpr( - .nclk(nclk), + .clk(clk), + .rst(rst), .clkoff_b(clkoff_dc_b), .act_dis(act_dis), .flush(pc_fu_ccflush_dc), @@ -924,6 +927,8 @@ module fu( fu_sto sto( .vdd(vdd), .gnd(gnd), + .clk(clk), + .rst(rst), .clkoff_b(clkoff_dc_b), .act_dis(act_dis), .flush(pc_fu_ccflush_dc), @@ -933,7 +938,6 @@ module fu( .sg_1(sg_1[1]), .thold_1(func_sl_thold_1[1]), .fpu_enable(fpu_enable), - .nclk(nclk), .f_sto_si(f_sto_si), .f_sto_so(f_sto_so), .f_dcd_ex1_sto_act(f_dcd_ex1_sto_act), @@ -955,10 +959,9 @@ module fu( assign fpu_enable = f_dcd_msr_fp_act; - - - fu_mad #( .THREADS(`THREADS)) mad( + .clk(clk), + .rst(rst), .f_dcd_ex7_cancel(f_dcd_ex7_cancel), .f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0), .f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1), @@ -1203,8 +1206,7 @@ module fu( .sg_1(sg_1[0]), .thold_1(func_sl_thold_1[0]), .fpu_enable(fpu_enable), - .f_dcd_ex1_act(f_dcd_ex1_mad_act), - .nclk(nclk) + .f_dcd_ex1_act(f_dcd_ex1_mad_act) ); //Needed for RTX @@ -1221,6 +1223,8 @@ module fu( fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC)) dcd( // INPUTS + .clk(clk), + .rst(rst), .act_dis(act_dis), .bcfg_scan_in(bcfg_scan_in), .ccfg_scan_in(ccfg_scan_in), @@ -1301,7 +1305,6 @@ module fu( .iu_fu_rf0_instr_match(iu_fu_rf0_instr_match), .mpw1_b(mpw1_dc_b[0:9]), .mpw2_b(mpw2_dc_b[0:1]), - .nclk(nclk), .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), .pc_fu_event_count_mode(pc_fu_event_count_mode), .pc_fu_ram_active(pc_fu_ram_active), diff --git a/dev/verilog/work/fu_add.v b/dev/verilog/work/fu_add.v index d0bccf3..b74a41e 100755 --- a/dev/verilog/work/fu_add.v +++ b/dev/verilog/work/fu_add.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_add( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_add( sg_1, thold_1, fpu_enable, - nclk, f_add_si, f_add_so, ex2_act_b, @@ -74,6 +75,9 @@ module fu_add( inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -83,7 +87,6 @@ module fu_add( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_add_si; //perv output f_add_so; //perv @@ -226,7 +229,8 @@ module fu_add( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -236,7 +240,8 @@ module fu_add( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -268,7 +273,8 @@ module fu_add( .delay_lclkr(delay_lclkr[3]), //i-- tidn, .mpw1_b(mpw1_b[3]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn, - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -304,7 +310,8 @@ module fu_add( .mpw1_b(mpw1_b[4]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex4_act), //in diff --git a/dev/verilog/work/fu_alg.v b/dev/verilog/work/fu_alg.v index c143664..41f4761 100755 --- a/dev/verilog/work/fu_alg.v +++ b/dev/verilog/work/fu_alg.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -33,6 +33,8 @@ module fu_alg( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module fu_alg( sg_1, thold_1, fpu_enable, - nclk, f_alg_si, f_alg_so, ex1_act, @@ -86,6 +87,8 @@ module fu_alg( // parameter expand_type = 2; // 0 - ibm tech, 1 - other ); inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -95,7 +98,6 @@ module fu_alg( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_alg_si; //perv output f_alg_so; //perv @@ -410,7 +412,8 @@ module fu_alg( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -420,7 +423,8 @@ module fu_alg( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -450,7 +454,8 @@ module fu_alg( .delay_lclkr(delay_lclkr[2]), //i-- tidn, .mpw1_b(mpw1_b[2]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn, - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -476,7 +481,8 @@ module fu_alg( .mpw1_b(mpw1_b[2]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex2_act), //in @@ -514,7 +520,8 @@ module fu_alg( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex1_act), @@ -1014,7 +1021,8 @@ module fu_alg( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex3_act), diff --git a/dev/verilog/work/fu_byp.v b/dev/verilog/work/fu_byp.v index c412c9f..b9dd8f6 100755 --- a/dev/verilog/work/fu_byp.v +++ b/dev/verilog/work/fu_byp.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_byp( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_byp( sg_1, thold_1, fpu_enable, - nclk, f_byp_si, f_byp_so, ex1_act, @@ -177,6 +178,9 @@ module fu_byp( ); inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -186,7 +190,6 @@ module fu_byp( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_byp_si; //perv output f_byp_so; //perv @@ -639,7 +642,6 @@ module fu_byp( wire temp_ex1_a_frac_mul_17; wire temp_ex1_a_frac_mul_35; - // REPOWER_MODE=/SERIAL/ //AOI22_e5n_sn08b SP/UNDEF @@ -683,7 +685,8 @@ module fu_byp( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -693,7 +696,8 @@ module fu_byp( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -722,7 +726,8 @@ module fu_byp( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -746,7 +751,8 @@ module fu_byp( .mpw1_b(mpw1_b), // tidn ,--in .mpw2_b(mpw2_b), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex1_act), //in diff --git a/dev/verilog/work/fu_cr2.v b/dev/verilog/work/fu_cr2.v index 9118640..2eeeb31 100755 --- a/dev/verilog/work/fu_cr2.v +++ b/dev/verilog/work/fu_cr2.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -50,6 +50,8 @@ module fu_cr2( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -59,7 +61,6 @@ module fu_cr2( sg_1, thold_1, fpu_enable, - nclk, f_cr2_si, f_cr2_so, ex1_act, @@ -89,6 +90,8 @@ module fu_cr2( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -98,7 +101,6 @@ module fu_cr2( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_cr2_si; // perv output f_cr2_so; // perv @@ -287,7 +289,8 @@ module fu_cr2( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -297,7 +300,8 @@ module fu_cr2( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -327,7 +331,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -376,7 +381,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), //ex1_act @@ -433,7 +439,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable),//ex2_act @@ -472,7 +479,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable),//ex3_act @@ -516,7 +524,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable),//ex4_act @@ -538,7 +547,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable),//ex5_act @@ -561,7 +571,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable),//ex6_act @@ -670,7 +681,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex2_act), @@ -690,7 +702,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex3_act), @@ -710,7 +723,8 @@ module fu_cr2( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex4_act), @@ -730,7 +744,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex5_act), @@ -749,7 +764,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex6_act), @@ -773,7 +789,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_th0_act), @@ -793,7 +810,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_th1_act), @@ -813,7 +831,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_th2_act), @@ -833,7 +852,8 @@ module fu_cr2( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_th3_act), diff --git a/dev/verilog/work/fu_dcd.v b/dev/verilog/work/fu_dcd.v index 2defdf9..d2ce501 100755 --- a/dev/verilog/work/fu_dcd.v +++ b/dev/verilog/work/fu_dcd.v @@ -41,6 +41,8 @@ `include "tri_a2o.vh" module fu_dcd( + clk, + rst, act_dis, bcfg_scan_in, ccfg_scan_in, @@ -117,7 +119,6 @@ module fu_dcd( iu_fu_rf0_instr_match, mpw1_b, mpw2_b, - nclk, pc_fu_debug_mux_ctrls, pc_fu_event_count_mode, pc_fu_instr_trace_mode, @@ -447,7 +448,8 @@ module fu_dcd( input iu_fu_rf0_instr_match; input [0:9] mpw1_b; input [0:1] mpw2_b; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input [0:10] pc_fu_debug_mux_ctrls; input [0:2] pc_fu_event_count_mode; input pc_fu_instr_trace_mode; @@ -1558,7 +1560,8 @@ module fu_dcd( // Latches tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg0( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .delay_lclkr(delay_lclkr[9]), @@ -1581,7 +1584,8 @@ module fu_dcd( // Latches tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg1( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .delay_lclkr(delay_lclkr[9]), @@ -1664,7 +1668,8 @@ module fu_dcd( tri_plat #( .WIDTH(3)) thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din({thold_1, cfg_sl_thold_1, @@ -1678,7 +1683,8 @@ module fu_dcd( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -1717,7 +1723,8 @@ module fu_dcd( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr[9]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(cfg_sl_force), .thold_b(cfg_sl_thold_0_b), .dclk(cfg_slat_d2clk), @@ -1759,7 +1766,8 @@ module fu_dcd( endgenerate tri_rlmreg_p #(.INIT(0), .WIDTH(8)) act_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -1849,7 +1857,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(1)) ex0_iu( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .delay_lclkr(delay_lclkr[0]), @@ -1880,7 +1889,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex0_frt( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(msr_fp_act), .force_t(force_t), .d_mode(tiup), @@ -1920,7 +1930,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(15), .NEEDS_SRESET(1)) ex1_iu( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -1970,7 +1981,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex1_frt( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(force_t), .d_mode(tiup), @@ -2001,7 +2013,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex1_instl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(force_t), .d_mode(tiup), @@ -2020,7 +2033,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex1_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2051,7 +2065,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex1_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2528,7 +2543,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex2_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -2582,7 +2598,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(6)) ex2_frt( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_v), .force_t(force_t), .d_mode(tiup), @@ -2609,7 +2626,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex2_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2638,7 +2656,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex2_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2712,7 +2731,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(7)) ex3_ctlng_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -2737,7 +2757,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_ctl_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_axu_v), .force_t(force_t), .d_mode(tiup), @@ -2792,7 +2813,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex3_stdv_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2814,7 +2836,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex3_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2844,7 +2867,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex3_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2890,7 +2914,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex4_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2942,7 +2967,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex4_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -2972,7 +2998,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex4_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3006,7 +3033,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(22)) ex5_ctl_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3052,7 +3080,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex5_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3084,7 +3113,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex5_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3139,7 +3169,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex6_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3183,7 +3214,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex6_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3215,7 +3247,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex6_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3297,7 +3330,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(23)) ex7_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3347,7 +3381,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3381,7 +3416,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_la( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3409,7 +3445,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex7_crbf( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3471,7 +3508,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex8_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3526,7 +3564,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(8)) ex8_itagl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3549,7 +3588,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex8_la( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3586,7 +3626,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex9_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3620,7 +3661,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex9_la( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3839,7 +3881,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axu_ex( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -3892,10 +3935,12 @@ module fu_dcd( .perr_so(perr_so), .mpw1_b(mpw1_b), .mpw2_b(mpw2_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(force_t), .thold_0_b(thold_0_b), .sg_0(sg_0), + .delay_lclkr(10'b0), .gnd(gnd), .vdd(vdd), @@ -4010,7 +4055,8 @@ module fu_dcd( // Latches tri_rlmreg_p #(.INIT(0), .WIDTH(15)) spr_ctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -4039,7 +4085,8 @@ module fu_dcd( //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(2 ** REGMODE)) spr_data( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -4061,7 +4108,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axucr0_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(cfg_sl_force), .d_mode(tiup), @@ -4083,7 +4131,8 @@ module fu_dcd( tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) a0esr_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(a0esr_wr), .force_t(cfg_sl_force), .delay_lclkr(delay_lclkr[9]), @@ -4190,7 +4239,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(65)) ex8_ram_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_instr_valid), .force_t(force_t), .d_mode(tiup), @@ -4216,7 +4266,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex8_ramv_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -4323,7 +4374,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(8)) event_bus_out_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_act), .force_t(force_t), .d_mode(tiup), @@ -4346,7 +4398,8 @@ module fu_dcd( tri_rlmreg_p #(.INIT(0), .WIDTH(35)) perf_data( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_act), .force_t(force_t), .d_mode(tiup), @@ -4390,7 +4443,8 @@ module fu_dcd( // Debug Bus tri_rlmreg_p #(.INIT(0), .WIDTH(32)) dbg_group3_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .d_mode(tiup), @@ -4531,7 +4585,8 @@ module fu_dcd( // Trace Bus latches, using pc_fu_trace_bus_enable for act tri_rlmreg_p #(.INIT(0), .WIDTH(68)) dbg0_data( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dbg0_act), .force_t(func_slp_sl_force), .d_mode(tiup), @@ -4563,7 +4618,8 @@ module fu_dcd( //Another set, closer to the I/O on the bottom tri_rlmreg_p #(.INIT(0), .WIDTH(5)) dbg1_data( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), diff --git a/dev/verilog/work/fu_divsqrt.v b/dev/verilog/work/fu_divsqrt.v index 604cf35..0a9c908 100755 --- a/dev/verilog/work/fu_divsqrt.v +++ b/dev/verilog/work/fu_divsqrt.v @@ -38,6 +38,8 @@ module fu_divsqrt( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -47,7 +49,6 @@ module fu_divsqrt( sg_1, thold_1, fpu_enable, - nclk, f_dsq_si, f_dsq_so, ex0_act_b, @@ -103,6 +104,8 @@ module fu_divsqrt( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? @@ -114,8 +117,6 @@ module fu_divsqrt( input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; - //-------------------------------------------------------------------------- input f_dsq_si; //perv scan output f_dsq_so; //perv scan @@ -968,7 +969,8 @@ module fu_divsqrt( tri_plat #(.WIDTH(1)) thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -978,7 +980,8 @@ module fu_divsqrt( tri_plat #(.WIDTH(1)) sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -1012,7 +1015,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -1089,7 +1093,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1136,7 +1141,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1178,7 +1184,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1228,7 +1235,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1295,7 +1303,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1361,7 +1370,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1407,7 +1417,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1487,7 +1498,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1508,7 +1520,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1590,7 +1603,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1611,7 +1625,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1632,7 +1647,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1653,7 +1669,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1674,7 +1691,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1699,7 +1717,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -2351,7 +2370,8 @@ module fu_divsqrt( .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -2725,7 +2745,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -2956,7 +2977,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -3001,7 +3023,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -3062,7 +3085,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -3136,7 +3160,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] & .mpw2_b(mpw2_b), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- diff --git a/dev/verilog/work/fu_eie.v b/dev/verilog/work/fu_eie.v index 139b34b..38a0a8b 100755 --- a/dev/verilog/work/fu_eie.v +++ b/dev/verilog/work/fu_eie.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_eie( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_eie( sg_1, thold_1, fpu_enable, - nclk, f_eie_si, f_eie_so, ex2_act, @@ -73,6 +74,9 @@ module fu_eie( inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -82,7 +86,6 @@ module fu_eie( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_eie_si; // perv output f_eie_so; // perv @@ -202,7 +205,8 @@ module fu_eie( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -212,7 +216,8 @@ module fu_eie( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -240,7 +245,8 @@ module fu_eie( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -533,7 +539,8 @@ module fu_eie( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex2_act), @@ -553,7 +560,8 @@ module fu_eie( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex2_act), @@ -573,7 +581,8 @@ module fu_eie( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex2_act), @@ -705,7 +714,8 @@ module fu_eie( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex3_act), diff --git a/dev/verilog/work/fu_eov.v b/dev/verilog/work/fu_eov.v index 703fb22..5a5c938 100755 --- a/dev/verilog/work/fu_eov.v +++ b/dev/verilog/work/fu_eov.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -33,6 +33,8 @@ module fu_eov( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module fu_eov( sg_1, thold_1, fpu_enable, - nclk, f_eov_si, f_eov_so, ex3_act_b, @@ -81,6 +82,9 @@ module fu_eov( inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -90,7 +94,6 @@ module fu_eov( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_eov_si; // perv output f_eov_so; // perv @@ -348,7 +351,8 @@ module fu_eov( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -358,7 +362,8 @@ module fu_eov( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -379,7 +384,8 @@ module fu_eov( .mpw1_b(mpw1_b[5]), // tidn .mpw2_b(mpw2_b[1]), // tidn .force_t(force_t), // tidn - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex5_act), //in @@ -405,7 +411,8 @@ module fu_eov( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -468,7 +475,8 @@ module fu_eov( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex4_act), @@ -1011,7 +1019,8 @@ module fu_eov( .mpw2_b(mpw2_b[1]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex5_act), diff --git a/dev/verilog/work/fu_fmt.v b/dev/verilog/work/fu_fmt.v index 4696baa..1745f0a 100755 --- a/dev/verilog/work/fu_fmt.v +++ b/dev/verilog/work/fu_fmt.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -39,6 +39,8 @@ module fu_fmt( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -48,7 +50,6 @@ module fu_fmt( sg_1, thold_1, fpu_enable, - nclk, f_fmt_si, f_fmt_so, ex1_act, @@ -139,6 +140,9 @@ module fu_fmt( ); inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -148,7 +152,6 @@ module fu_fmt( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_fmt_si; //perv output f_fmt_so; //perv @@ -510,7 +513,8 @@ module fu_fmt( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -520,7 +524,8 @@ module fu_fmt( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -550,7 +555,8 @@ module fu_fmt( .mpw2_b(mpw2_b[0]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -618,7 +624,8 @@ module fu_fmt( .mpw2_b(mpw2_b[0]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1343,7 +1350,8 @@ module fu_fmt( .mpw2_b(mpw2_b[0]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_act), .thold_b(thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/fu_fpr.v b/dev/verilog/work/fu_fpr.v index ff3f46e..10dff80 100755 --- a/dev/verilog/work/fu_fpr.v +++ b/dev/verilog/work/fu_fpr.v @@ -41,7 +41,8 @@ `include "tri_a2o.vh" module fu_fpr( - nclk, + clk, + rst, clkoff_b, act_dis, flush, @@ -165,7 +166,8 @@ module fu_fpr( //parameter threads = 2; parameter axu_spare_enc = 3; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -541,7 +543,8 @@ module fu_fpr( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -551,7 +554,8 @@ module fu_fpr( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -571,7 +575,8 @@ module fu_fpr( tri_plat #(.WIDTH(4)) ab_thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din({abst_sl_thold_1, time_sl_thold_1, @@ -620,7 +625,8 @@ module fu_fpr( endgenerate tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex6_lctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -689,7 +695,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(2)) ex6_ldv( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -710,7 +717,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(12)) ex7_lctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -732,7 +740,8 @@ module fu_fpr( ); tri_rlmreg_p #(.INIT(0), .WIDTH(10)) ex7_rlctl( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_reload_v), .force_t(force_t), .d_mode(tiup), @@ -751,7 +760,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_ldat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_load_v), .force_t(force_t), .d_mode(tiup), @@ -770,7 +780,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_rldat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_reload_v), .force_t(force_t), .d_mode(tiup), @@ -1313,7 +1324,8 @@ module fu_fpr( tri_144x78_2r4w fpr0( // .regsize(64), #( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .delay_lclkr_dc(delay_lclkra[0]), .mpw1_dc_b(mpw1_ba[0]), .mpw2_dc_b(mpw2_b[0]), @@ -1347,11 +1359,11 @@ module fu_fpr( .w_data_in_4(zeros[0:77]) ); - tri_144x78_2r4w fpr1(// .regsize(64),#( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .delay_lclkr_dc(delay_lclkra[0]), .mpw1_dc_b(mpw1_ba[0]), .mpw2_dc_b(mpw2_b[0]), @@ -1388,7 +1400,8 @@ module fu_fpr( // ABIST timing latches tri_rlmreg_p #(.INIT(0), .WIDTH(53), .NEEDS_SRESET(0)) ab_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(ab_force), .d_mode(tiup), @@ -1430,7 +1443,8 @@ module fu_fpr( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(time_scan_in), // Connects to time scan ring .scan_diag_dc(scan_diag_dc), .thold(time_sl_thold_0), //Connects to time thold @@ -1469,7 +1483,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(34), .NEEDS_SRESET(0)) ex1_par( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -1533,7 +1548,8 @@ module fu_fpr( tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) ldwt_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -1555,7 +1571,8 @@ module fu_fpr( ); //------------------------------------------- tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) reldwt_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), @@ -1614,7 +1631,8 @@ module fu_fpr( // Target Bypass tri_rlmreg_p #(.INIT(0), .WIDTH(134), .NEEDS_SRESET(0)) tgwt_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(force_t), .d_mode(tiup), diff --git a/dev/verilog/work/fu_gst.v b/dev/verilog/work/fu_gst.v index 9a154b7..3817fb2 100755 --- a/dev/verilog/work/fu_gst.v +++ b/dev/verilog/work/fu_gst.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -38,6 +38,8 @@ module fu_gst( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -47,7 +49,6 @@ module fu_gst( sg_1, thold_1, fpu_enable, - nclk, f_gst_si, f_gst_so, ex1_act, @@ -65,6 +66,8 @@ module fu_gst( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? @@ -75,7 +78,6 @@ module fu_gst( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; //-------------------------------------------------------------------------- // input f_gst_si; //perv scan @@ -464,7 +466,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -474,7 +477,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -502,7 +506,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -545,7 +550,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -577,7 +583,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -895,7 +902,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -921,7 +929,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -979,7 +988,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1008,7 +1018,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1312,7 +1323,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- @@ -1337,7 +1349,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), //----------------- diff --git a/dev/verilog/work/fu_lza.v b/dev/verilog/work/fu_lza.v index d2e9fe3..f51f0b1 100755 --- a/dev/verilog/work/fu_lza.v +++ b/dev/verilog/work/fu_lza.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -33,6 +33,8 @@ module fu_lza( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module fu_lza( sg_1, thold_1, fpu_enable, - nclk, f_lza_si, f_lza_so, ex2_act_b, @@ -64,6 +65,8 @@ module fu_lza( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -73,7 +76,6 @@ module fu_lza( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_lza_si; //perv output f_lza_so; //perv @@ -173,7 +175,8 @@ module fu_lza( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -183,7 +186,8 @@ module fu_lza( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -214,7 +218,8 @@ module fu_lza( .mpw2_b(mpw2_b[0]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -242,7 +247,8 @@ module fu_lza( .mpw1_b(mpw1_b[3]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex3_act), //in @@ -259,7 +265,8 @@ module fu_lza( .mpw1_b(mpw1_b[4]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex4_act), //in diff --git a/dev/verilog/work/fu_lze.v b/dev/verilog/work/fu_lze.v index 9c92fcd..8e77638 100755 --- a/dev/verilog/work/fu_lze.v +++ b/dev/verilog/work/fu_lze.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_lze( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_lze( sg_1, thold_1, fpu_enable, - nclk, f_lze_si, f_lze_so, ex2_act_b, @@ -67,6 +68,8 @@ module fu_lze( ); inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -76,7 +79,6 @@ module fu_lze( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_lze_si; //perv output f_lze_so; //perv @@ -184,7 +186,8 @@ module fu_lze( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -194,7 +197,8 @@ module fu_lze( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -225,7 +229,8 @@ module fu_lze( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -889,7 +894,8 @@ module fu_lze( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_act), .thold_b(thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/fu_mad.v b/dev/verilog/work/fu_mad.v index b88251a..8c452e4 100755 --- a/dev/verilog/work/fu_mad.v +++ b/dev/verilog/work/fu_mad.v @@ -14,23 +14,25 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns `include "tri_a2o.vh" module fu_mad( + clk, + rst, f_dcd_ex7_cancel, f_dcd_ex1_bypsel_a_res0, f_dcd_ex1_bypsel_a_res1, @@ -267,8 +269,7 @@ module fu_mad( mpw2_b, thold_1, sg_1, - fpu_enable, - nclk + fpu_enable ); parameter THREADS = 2; input f_dcd_ex7_cancel; @@ -537,6 +538,9 @@ module fu_mad( //-------------------------------------------------------------------------- inout vdd; inout gnd; + input clk; + input rst; + input [0:18] scan_in; output [0:18] scan_out; input clkoff_b; // tiup @@ -548,9 +552,6 @@ module fu_mad( input thold_1; input sg_1; input fpu_enable; - input [0:`NCLK_WIDTH-1] nclk; - // This entity contains macros - parameter tiup = 1'b1; parameter tidn = 1'b0; @@ -944,7 +945,8 @@ module fu_mad( //--------------------------------------------------------- -- fuq_byp.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1102,7 +1104,8 @@ module fu_mad( //----------------------------------------------------------- fu_fmt.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1217,7 +1220,8 @@ module fu_mad( //----------------------------------------------------------- fu_eie.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1261,7 +1265,8 @@ module fu_mad( //----------------------------------------------------------- fu_eov.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1317,7 +1322,8 @@ module fu_mad( //----------------------------------------------------------- fu_mul.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1345,7 +1351,8 @@ module fu_mad( //----------------------------------------------------------- fu_alg.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1406,7 +1413,8 @@ module fu_mad( //----------------------------------------------------------- fuq_sa3.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1435,7 +1443,8 @@ module fu_mad( //----------------------------------------------------------- fu_add.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1479,7 +1488,8 @@ module fu_mad( //----------------------------------------------------------- fu_lze.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1520,7 +1530,8 @@ module fu_mad( //----------------------------------------------------------- fu_lza.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1559,7 +1570,8 @@ module fu_mad( //----------------------------------------------------------- fu_nrm.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1604,7 +1616,8 @@ module fu_mad( //----------------------------------------------------------- fu_rnd.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1712,7 +1725,8 @@ module fu_mad( //----------------------------------------------------------- fu_gst.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1743,7 +1757,8 @@ module fu_mad( //----------------------------------------------------------- fu_divsqrt.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -1836,7 +1851,8 @@ module fu_mad( //----------------------------------------------------------- fu_pic.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -2090,7 +2106,8 @@ module fu_mad( //----------------------------------------------------------- fu_cr2.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -2136,7 +2153,8 @@ module fu_mad( //----------------------------------------------------------- fuq_scr.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -2249,7 +2267,8 @@ module fu_mad( //----------------------------------------------------------- fuq_tblexp.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- @@ -2286,7 +2305,8 @@ module fu_mad( //----------------------------------------------------------- fuq_tbllut.vhdl .vdd(vdd), //i-- .gnd(gnd), //i-- - .nclk(nclk), //i-- + .clk(clk), + .rst(rst), //i-- .clkoff_b(clkoff_b), //i-- .act_dis(act_dis), //i-- .flush(flush), //i-- diff --git a/dev/verilog/work/fu_nrm.v b/dev/verilog/work/fu_nrm.v index 7758205..3a5fec9 100755 --- a/dev/verilog/work/fu_nrm.v +++ b/dev/verilog/work/fu_nrm.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_nrm( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_nrm( sg_1, thold_1, fpu_enable, - nclk, f_nrm_si, f_nrm_so, ex4_act_b, @@ -72,6 +73,9 @@ module fu_nrm( inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -81,7 +85,6 @@ module fu_nrm( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_nrm_si; // perv output f_nrm_so; // perv @@ -214,7 +217,8 @@ module fu_nrm( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -224,7 +228,8 @@ module fu_nrm( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -245,7 +250,8 @@ module fu_nrm( .mpw1_b(mpw1_b[5]), // tidn .mpw2_b(mpw2_b[1]), // tidn .force_t(force_t), // tidn - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex5_act), //in @@ -271,7 +277,8 @@ module fu_nrm( .mpw2_b(mpw2_b[0]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -545,7 +552,8 @@ module fu_nrm( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex5_act), @@ -568,7 +576,8 @@ module fu_nrm( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex5_act), diff --git a/dev/verilog/work/fu_oscr.v b/dev/verilog/work/fu_oscr.v index 1aaa155..90884d1 100755 --- a/dev/verilog/work/fu_oscr.v +++ b/dev/verilog/work/fu_oscr.v @@ -92,6 +92,8 @@ module fu_oscr( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -101,7 +103,6 @@ module fu_oscr( sg_1, thold_1, fpu_enable, - nclk, f_scr_si, f_scr_so, ex3_act_b, @@ -189,6 +190,8 @@ module fu_oscr( inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -198,7 +201,6 @@ module fu_oscr( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_scr_si; // perv output f_scr_so; // perv @@ -640,7 +642,8 @@ module fu_oscr( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -650,7 +653,8 @@ module fu_oscr( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -690,7 +694,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -766,7 +771,8 @@ module fu_oscr( .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -805,7 +811,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -849,7 +856,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -884,7 +892,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -943,7 +952,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), // ex6_act, -- todo: act pin .thold_b(thold_0_b), .sg(sg_0), @@ -1008,7 +1018,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1269,7 +1280,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_act), @@ -1291,7 +1303,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex7_act), //ex7_th1_act, todo: act pin @@ -1312,7 +1325,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1587,7 +1601,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -1838,7 +1853,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -2014,7 +2030,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -2572,7 +2589,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -2592,7 +2610,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -2626,7 +2645,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), @@ -2646,7 +2666,8 @@ module fu_oscr( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/fu_perv.v b/dev/verilog/work/fu_perv.v index 4a21030..597fc12 100755 --- a/dev/verilog/work/fu_perv.v +++ b/dev/verilog/work/fu_perv.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -39,7 +39,8 @@ module fu_perv( vdd, gnd, - nclk, + clk, + rst, pc_fu_sg_3, pc_fu_abst_sl_thold_3, pc_fu_func_sl_thold_3, @@ -74,7 +75,8 @@ module fu_perv( inout vdd; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input [0:1] pc_fu_sg_3; input pc_fu_abst_sl_thold_3; input [0:1] pc_fu_func_sl_thold_3; @@ -158,7 +160,8 @@ module fu_perv( tri_plat #(.WIDTH(12)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({ @@ -190,7 +193,8 @@ module fu_perv( tri_plat #(.WIDTH(12)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({ @@ -224,7 +228,8 @@ module fu_perv( tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({ gptr_sl_thold_1, sg_1_int[0], @@ -253,7 +258,8 @@ module fu_perv( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_in), .scan_diag_dc(tc_ac_scan_diag_dc), .thold(gptr_sl_thold_0_int), @@ -270,7 +276,8 @@ module fu_perv( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_sio), .scan_diag_dc(tc_ac_scan_diag_dc), .thold(gptr_sl_thold_0_int), @@ -306,7 +313,8 @@ module fu_perv( assign repr_in = 1'b0; tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tihi), .force_t(repr_sl_force), .d_mode(tiup), diff --git a/dev/verilog/work/fu_pic.v b/dev/verilog/work/fu_pic.v index 24b1d48..286958d 100755 --- a/dev/verilog/work/fu_pic.v +++ b/dev/verilog/work/fu_pic.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -33,6 +33,8 @@ module fu_pic( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module fu_pic( sg_1, thold_1, fpu_enable, - nclk, f_pic_si, f_pic_so, f_dcd_ex1_act, @@ -276,6 +277,8 @@ module fu_pic( ); inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -285,7 +288,6 @@ module fu_pic( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_pic_si; //perv output f_pic_so; //perv @@ -1166,7 +1168,8 @@ module fu_pic( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -1176,7 +1179,8 @@ module fu_pic( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -1201,7 +1205,8 @@ module fu_pic( tri_rlmreg_p #(.WIDTH(21)) act_lat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(force_t), .d_mode(tiup), .delay_lclkr(delay_lclkr[4]), @@ -1324,7 +1329,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[1]), .mpw1_b(mpw1_b[1]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(f_dcd_ex1_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1534,7 +1540,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[2]), .mpw1_b(mpw1_b[2]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1677,7 +1684,8 @@ module fu_pic( .delay_lclkr(tidn), .mpw1_b(tidn), .mpw2_b(tidn), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_act), .thold_b(thold_0_b), .sg(sg_0), @@ -1987,7 +1995,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[3]), .mpw1_b(mpw1_b[3]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2029,7 +2038,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[3]), .mpw1_b(mpw1_b[3]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2126,7 +2136,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[3]), .mpw1_b(mpw1_b[3]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2337,7 +2348,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[4]), .mpw1_b(mpw1_b[4]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2374,7 +2386,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[4]), .mpw1_b(mpw1_b[4]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2452,7 +2465,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[4]), .mpw1_b(mpw1_b[4]), .mpw2_b(mpw2_b[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_act), .thold_b(thold_0_b), .sg(sg_0), @@ -2774,7 +2788,8 @@ module fu_pic( .delay_lclkr(delay_lclkr[5]), .mpw1_b(mpw1_b[5]), .mpw2_b(mpw2_b[1]), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_act), .thold_b(thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/fu_rnd.v b/dev/verilog/work/fu_rnd.v index 22e49b3..ba53a4e 100755 --- a/dev/verilog/work/fu_rnd.v +++ b/dev/verilog/work/fu_rnd.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_rnd( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_rnd( sg_1, thold_1, fpu_enable, - nclk, f_rnd_si, f_rnd_so, ex4_act_b, @@ -131,6 +132,9 @@ module fu_rnd( parameter expand_type = 2; // 0 - ibm tech, 1 - other ); inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -140,7 +144,6 @@ module fu_rnd( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_rnd_si; // perv output f_rnd_so; // perv @@ -428,7 +431,8 @@ module fu_rnd( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -438,7 +442,8 @@ module fu_rnd( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -469,7 +474,8 @@ module fu_rnd( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -521,7 +527,8 @@ module fu_rnd( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex5_act), @@ -1145,7 +1152,8 @@ module fu_rnd( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex6_act), @@ -1166,7 +1174,8 @@ module fu_rnd( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex6_act), @@ -1189,7 +1198,8 @@ module fu_rnd( .mpw2_b(mpw2_b[1]), //i-- tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex6_act), diff --git a/dev/verilog/work/fu_sa3.v b/dev/verilog/work/fu_sa3.v index f56e225..59963a8 100755 --- a/dev/verilog/work/fu_sa3.v +++ b/dev/verilog/work/fu_sa3.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -34,6 +34,8 @@ module fu_sa3( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -43,7 +45,6 @@ module fu_sa3( sg_1, thold_1, fpu_enable, - nclk, f_sa3_si, f_sa3_so, ex2_act_b, @@ -57,6 +58,9 @@ module fu_sa3( ); inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -66,7 +70,6 @@ module fu_sa3( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_sa3_si; //perv output f_sa3_so; //perv @@ -1306,7 +1309,8 @@ module fu_sa3( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -1316,7 +1320,8 @@ module fu_sa3( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -1347,7 +1352,8 @@ module fu_sa3( .mpw2_b(mpw2_b[0]), // tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -1373,7 +1379,8 @@ module fu_sa3( .mpw1_b(mpw1_b[3]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex3_act), //in diff --git a/dev/verilog/work/fu_sto.v b/dev/verilog/work/fu_sto.v index 10ca111..c0a2981 100755 --- a/dev/verilog/work/fu_sto.v +++ b/dev/verilog/work/fu_sto.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -59,6 +59,8 @@ module fu_sto( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -68,7 +70,6 @@ module fu_sto( sg_1, thold_1, fpu_enable, - nclk, f_sto_si, f_sto_so, f_dcd_ex1_sto_act, @@ -86,6 +87,8 @@ module fu_sto( ); inout vdd; inout gnd; + input clk; + input rst; input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -95,7 +98,6 @@ module fu_sto( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input f_sto_si; output f_sto_so; @@ -243,7 +245,8 @@ module fu_sto( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -253,7 +256,8 @@ module fu_sto( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -278,7 +282,8 @@ module fu_sto( tri_rlmreg_p #(.WIDTH(4)) act_lat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(force_t), // tidn .d_mode(tiup), .delay_lclkr(delay_lclkr[1]), // tidn, @@ -314,7 +319,8 @@ module fu_sto( .delay_lclkr(delay_lclkr[1]), //tidn, .mpw1_b(mpw1_b[1]), //tidn, .mpw2_b(mpw2_b[0]), //tidn, - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex1_act), @@ -339,7 +345,8 @@ module fu_sto( .delay_lclkr(delay_lclkr[1]), //tidn, .mpw1_b(mpw1_b[1]), //tidn, .mpw2_b(mpw2_b[0]), //tidn, - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex1_act), @@ -663,7 +670,8 @@ module fu_sto( .delay_lclkr(delay_lclkr[2]), //tidn, .mpw1_b(mpw1_b[2]), //tidn, .mpw2_b(mpw2_b[0]), //tidn, - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex2_act), diff --git a/dev/verilog/work/fu_tblexp.v b/dev/verilog/work/fu_tblexp.v index 62c7832..163e3b6 100755 --- a/dev/verilog/work/fu_tblexp.v +++ b/dev/verilog/work/fu_tblexp.v @@ -14,23 +14,25 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns module fu_tblexp( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -40,7 +42,6 @@ module fu_tblexp( sg_1, thold_1, fpu_enable, - nclk, si, so, ex2_act_b, @@ -65,6 +66,9 @@ module fu_tblexp( inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -74,7 +78,6 @@ module fu_tblexp( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input si; // perv output so; // perv @@ -188,7 +191,8 @@ module fu_tblexp( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -198,7 +202,8 @@ module fu_tblexp( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -229,7 +234,8 @@ module fu_tblexp( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(fpu_enable), @@ -559,7 +565,8 @@ module fu_tblexp( .mpw2_b(mpw2_b[0]), //tidn, .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_b(thold_0_b), .sg(sg_0), .act(ex3_act), diff --git a/dev/verilog/work/fu_tbllut.v b/dev/verilog/work/fu_tbllut.v index c7572f9..8fc37d4 100755 --- a/dev/verilog/work/fu_tbllut.v +++ b/dev/verilog/work/fu_tbllut.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -33,6 +33,8 @@ module fu_tbllut( vdd, gnd, + clk, + rst, clkoff_b, act_dis, flush, @@ -42,7 +44,6 @@ module fu_tbllut( sg_1, thold_1, fpu_enable, - nclk, si, so, ex2_act, @@ -64,6 +65,9 @@ module fu_tbllut( ); inout vdd; inout gnd; + input clk; + input rst; + input clkoff_b; // tiup input act_dis; // ??tidn?? input flush; // ??tidn?? @@ -73,7 +77,6 @@ module fu_tbllut( input sg_1; input thold_1; input fpu_enable; //dc_act - input [0:`NCLK_WIDTH-1] nclk; input si; //perv output so; //perv @@ -236,7 +239,8 @@ module fu_tbllut( .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_act), .thold_b(thold_0_b), .sg(sg_0), @@ -792,7 +796,8 @@ module fu_tbllut( .mpw2_b(mpw2_b[1]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_act), .thold_b(thold_0_b), .sg(sg_0), @@ -816,7 +821,8 @@ module fu_tbllut( tri_plat thold_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(thold_1), .q(thold_0) @@ -826,7 +832,8 @@ module fu_tbllut( tri_plat sg_reg_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(flush), .din(sg_1), .q(sg_0) @@ -855,7 +862,8 @@ module fu_tbllut( .mpw2_b(mpw2_b[0]), .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fpu_enable), .thold_b(thold_0_b), .sg(sg_0), @@ -885,7 +893,8 @@ module fu_tbllut( .mpw1_b(mpw1_b[3]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex3_act), //in @@ -902,7 +911,8 @@ module fu_tbllut( .mpw1_b(mpw1_b[4]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in .force_t(force_t), // tidn ,--in - .nclk(nclk), //in + .clk(clk), + .rst(rst), //in .vd(vdd), //inout .gd(gnd), //inout .act(ex4_act), //in diff --git a/dev/verilog/work/iuq.v b/dev/verilog/work/iuq.v index bb91e02..92bdbbc 100755 --- a/dev/verilog/work/iuq.v +++ b/dev/verilog/work/iuq.v @@ -40,8 +40,8 @@ `include "tri_a2o.vh" module iuq( - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_3, input pc_iu_fce_3, input pc_iu_func_slp_sl_thold_3, // was: chip_b_sl_2_thold_3_b @@ -1375,7 +1375,8 @@ module iuq( .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_fce_2(pc_iu_fce_2), @@ -1402,7 +1403,8 @@ module iuq( //.vcs(vdd), //.vdd(vdd), //.gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), @@ -1830,7 +1832,8 @@ module iuq( .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), @@ -1898,7 +1901,8 @@ module iuq( .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), @@ -1965,7 +1969,8 @@ module iuq( .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), @@ -2031,7 +2036,8 @@ module iuq( iuq_slice_top iuq_slice_top0( //.vdd(vdd), //.gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), @@ -2717,7 +2723,8 @@ module iuq( iuq_cpl_top iuq_cpl_top0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), .clkoff_dc_b(clkoff_b), .d_mode_dc(d_mode), @@ -3319,7 +3326,8 @@ module iuq( tri_plat #(.WIDTH(15)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_slp_sl_thold_3, pc_iu_func_nsl_thold_3, diff --git a/dev/verilog/work/iuq_axu_fu_dec.v b/dev/verilog/work/iuq_axu_fu_dec.v index dd24614..84694f3 100755 --- a/dev/verilog/work/iuq_axu_fu_dec.v +++ b/dev/verilog/work/iuq_axu_fu_dec.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -35,7 +35,8 @@ `include "tri_a2o.vh" module iuq_axu_fu_dec( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, //------------------------------------------------------------------- inout vdd, inout gnd, @@ -216,7 +217,8 @@ module iuq_axu_fu_dec( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -226,7 +228,8 @@ module iuq_axu_fu_dec( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) @@ -1230,7 +1233,8 @@ assign only_graphics_mode = ( pri_is0[0] & pri_is0[1] & pri_is0[2] .gd(gnd), .force_t(force_t), .delay_lclkr(delay_lclkr), - .nclk(nclk), + .clk(clk), + .rst(rst), .mpw1_b(mpw1_b), .act(tiup), .mpw2_b(mpw2_b), diff --git a/dev/verilog/work/iuq_axu_fu_rn.v b/dev/verilog/work/iuq_axu_fu_rn.v index a52d175..4351676 100755 --- a/dev/verilog/work/iuq_axu_fu_rn.v +++ b/dev/verilog/work/iuq_axu_fu_rn.v @@ -48,7 +48,8 @@ module iuq_axu_fu_rn #( ( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types input pc_iu_sg_2, input clkoff_b, @@ -416,7 +417,8 @@ module iuq_axu_fu_rn #( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + FPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(FPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) fpr_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -511,7 +513,8 @@ module iuq_axu_fu_rn #( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(24), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -582,7 +585,8 @@ module iuq_axu_fu_rn #( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(32), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -654,7 +658,8 @@ module iuq_axu_fu_rn #( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -673,7 +678,8 @@ module iuq_axu_fu_rn #( tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -696,7 +702,8 @@ module iuq_axu_fu_rn #( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -706,7 +713,8 @@ module iuq_axu_fu_rn #( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_bp.v b/dev/verilog/work/iuq_bp.v index 0994840..ee35a96 100755 --- a/dev/verilog/work/iuq_bp.v +++ b/dev/verilog/work/iuq_bp.v @@ -129,7 +129,8 @@ module iuq_bp( spr_single_issue, vdd, gnd, - nclk, + clk, + rst, pc_iu_sg_2, pc_iu_func_sl_thold_2, clkoff_b, @@ -277,8 +278,8 @@ module iuq_bp( //pervasive inout vdd; inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_sg_2; input pc_iu_func_sl_thold_2; input clkoff_b; @@ -1807,7 +1808,8 @@ generate tri_rlmreg_p #(.WIDTH(128), .INIT(0)) iu0_btb_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu0_btb_hist_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1826,7 +1828,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu1_btb_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1845,7 +1848,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu2_btb_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1864,7 +1868,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(gshare_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1882,7 +1887,8 @@ generate tri_rlmreg_p #(.WIDTH(5), .INIT(0)) gshare_shift0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1900,7 +1906,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) cp_gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1918,7 +1925,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_gs_count_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1936,7 +1944,8 @@ generate tri_rlmlatch_p #(.INIT(0)) cp_gs_taken_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1954,7 +1963,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu1_gs_pos_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1972,7 +1982,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_gs_pos_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1990,7 +2001,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu3_gs_pos_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2008,7 +2020,8 @@ generate tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu1_gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2027,7 +2040,8 @@ generate tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu2_gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2046,7 +2060,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_bh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2065,7 +2080,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_lk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2084,7 +2100,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_aa_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2103,7 +2120,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_b_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2122,7 +2140,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_bclr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2141,7 +2160,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_bcctr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2160,7 +2180,8 @@ generate tri_rlmreg_p #(.WIDTH(6), .INIT(0)) iu3_opcode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2179,7 +2200,8 @@ generate tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bo_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2198,7 +2220,8 @@ generate tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bi_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2217,7 +2240,8 @@ generate tri_rlmreg_p #(.WIDTH(24), .INIT(0)) iu3_tar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2236,7 +2260,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2255,7 +2280,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_ifar_pri_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2274,7 +2300,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_pr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2292,7 +2319,8 @@ generate tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_lnk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2311,7 +2339,8 @@ generate tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_btb_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2330,7 +2359,8 @@ generate tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2349,7 +2379,8 @@ generate tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_0_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_instr_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2368,7 +2399,8 @@ generate tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_1_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_instr_act[1]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2387,7 +2419,8 @@ generate tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_instr_act[2]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2406,7 +2439,8 @@ generate tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_3_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_instr_act[3]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2425,7 +2459,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_btb_redirect_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2444,7 +2479,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_btb_misdirect_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2463,7 +2499,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu3_btb_link_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2482,7 +2519,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_nfg_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2501,7 +2539,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_redirect_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_redirect_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2520,7 +2559,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu4_redirect_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2539,7 +2579,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu4_ls_push_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2558,7 +2599,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu4_ls_pop_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2577,7 +2619,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2597,7 +2640,8 @@ generate tri_rlmreg_p #(.WIDTH(8), .INIT(128)) iu5_ls_t0_ptr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_ptr_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2615,7 +2659,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t00_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2634,7 +2679,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t01_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[1]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2653,7 +2699,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t02_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[2]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2672,7 +2719,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t03_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[3]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2691,7 +2739,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t04_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[4]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2710,7 +2759,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t05_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[5]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2729,7 +2779,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t06_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[6]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2748,7 +2799,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t07_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_ls_t0_act[7]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2767,7 +2819,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t00_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2786,7 +2839,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t01_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[1]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2805,7 +2859,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t02_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[2]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2824,7 +2879,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t03_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[3]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2843,7 +2899,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t04_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[4]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2862,7 +2919,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t05_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[5]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2881,7 +2939,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t06_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[6]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2900,7 +2959,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t07_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_t0_act[7]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2918,7 +2978,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2937,7 +2998,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2956,7 +3018,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_bh_update_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2975,7 +3038,8 @@ generate tri_rlmreg_p #(.WIDTH(10), .INIT(0)) ex5_gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2994,7 +3058,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh0_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3013,7 +3078,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh1_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3032,7 +3098,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh2_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3051,7 +3118,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_br_pred_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3070,7 +3138,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_br_taken_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3089,7 +3158,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_bcctr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3108,7 +3178,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_bclr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3127,7 +3198,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_getNIA_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3146,7 +3218,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_lk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3165,7 +3238,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3184,7 +3258,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_bta_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3203,7 +3278,8 @@ generate tri_rlmreg_p #(.WIDTH(8), .INIT(0)) ex5_ls_ptr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3222,7 +3298,8 @@ generate tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_btb_hist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3241,7 +3318,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_btb_entry_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3260,7 +3338,8 @@ generate tri_rlmreg_p #(.WIDTH(128), .INIT(0)) ex5_btb_repl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_val_q), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3279,7 +3358,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_ls_push_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3298,7 +3378,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_ls_pop_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3317,7 +3398,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_group_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3335,7 +3417,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex5_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3354,7 +3437,8 @@ generate tri_rlmreg_p #(.WIDTH(8), .INIT(128)) ex6_ls_t0_ptr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_ls_ptr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3373,7 +3457,8 @@ generate tri_rlmreg_p #(.WIDTH(7), .INIT(0)) bp_config_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3392,7 +3477,8 @@ generate tri_rlmreg_p #(.WIDTH(18), .INIT(0)) br_iu_gshare_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3411,7 +3497,8 @@ generate tri_rlmreg_p #(.WIDTH(8), .INIT(0)) br_iu_ls_ptr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3430,7 +3517,8 @@ generate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) br_iu_ls_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3449,7 +3537,8 @@ generate tri_rlmlatch_p #(.INIT(0)) br_iu_ls_update_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3468,7 +3557,8 @@ generate tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3487,7 +3577,8 @@ generate tri_rlmlatch_p #(.INIT(0)) cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3506,7 +3597,8 @@ generate tri_rlmlatch_p #(.INIT(0)) iu_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3524,7 +3616,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3542,7 +3635,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[1]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3560,7 +3654,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[2]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3578,7 +3673,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[3]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3596,7 +3692,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[4]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3614,7 +3711,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data5_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[5]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3633,7 +3731,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data6_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[6]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3651,7 +3750,8 @@ generate tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data7_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(bcache_shift[7]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3675,23 +3775,23 @@ generate tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) ); - tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) ); - tri_lcbor perv_lcbor( .clkoff_b(clkoff_b), .thold(pc_iu_func_sl_thold_0), diff --git a/dev/verilog/work/iuq_btb.v b/dev/verilog/work/iuq_btb.v index 713cbf9..87ba3c1 100755 --- a/dev/verilog/work/iuq_btb.v +++ b/dev/verilog/work/iuq_btb.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -43,7 +43,8 @@ module iuq_btb( inout vcs, // clock and clockcontrol ports - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_2, input pc_iu_sg_2, input pc_iu_fce_2, @@ -169,7 +170,8 @@ module iuq_btb( .vdd(vdd), .vcs(vcs), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(pc_iu_sg_0), .abst_sl_thold_0(tidn), .ary_nsl_thold_0(tidn), @@ -257,7 +259,8 @@ module iuq_btb( tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -276,7 +279,8 @@ module iuq_btb( tri_rlmlatch_p #(.INIT(0)) w_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -295,7 +299,8 @@ module iuq_btb( tri_rlmlatch_p #(.INIT(0)) r_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -314,7 +319,8 @@ module iuq_btb( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_wi_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -333,7 +339,8 @@ module iuq_btb( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ri_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -352,7 +359,8 @@ module iuq_btb( tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lat_ro_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -370,7 +378,8 @@ module iuq_btb( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reset_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -389,27 +398,26 @@ module iuq_btb( // pervasive //----------------------------------------------- - tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}), .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}) ); - tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}), .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0}) ); - tri_lcbor perv_lcbor( .clkoff_b(clkoff_b), .thold(pc_iu_func_sl_thold_0), diff --git a/dev/verilog/work/iuq_cpl.v b/dev/verilog/work/iuq_cpl.v index 4e268be..fda935c 100755 --- a/dev/verilog/work/iuq_cpl.v +++ b/dev/verilog/work/iuq_cpl.v @@ -36,7 +36,8 @@ module iuq_cpl( // Clocks - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Pervasive input tc_ac_ccflush_dc, @@ -977,7 +978,8 @@ module iuq_cpl( iuq_cpl_ctrl iuq_cpl_ctrl( - .nclk(nclk), + .clk(clk), + .rst(rst), .d_mode_dc(d_mode_dc), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), @@ -1527,7 +1529,8 @@ module iuq_cpl( iuq_cpl_arr( // bitwidth of ports .gnd(gnd), .vdd(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), .mpw2_dc_b(mpw2_dc_b), @@ -1554,7 +1557,8 @@ module iuq_cpl( // Latch Instances tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) xer_cp_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1578,7 +1582,8 @@ module iuq_cpl( tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({func_sl_thold_2, func_slp_sl_thold_2, sg_2}), .q({func_sl_thold_1, func_slp_sl_thold_1, sg_1}) @@ -1587,7 +1592,8 @@ module iuq_cpl( tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({func_sl_thold_1, func_slp_sl_thold_1, sg_1}), .q({func_sl_thold_0, func_slp_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/iuq_cpl_ctrl.v b/dev/verilog/work/iuq_cpl_ctrl.v index c689dd0..068795e 100755 --- a/dev/verilog/work/iuq_cpl_ctrl.v +++ b/dev/verilog/work/iuq_cpl_ctrl.v @@ -36,7 +36,8 @@ module iuq_cpl_ctrl( // Clocks - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Pervasive input d_mode_dc, @@ -3255,7 +3256,8 @@ assign select_lq = // Latch Instances //----------------------------------------------- tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-1), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3273,7 +3275,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-1), .INIT(1), .NEEDS_SRESET(1)) iu6_i1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3291,7 +3294,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3309,7 +3313,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(1), .INIT(1), .NEEDS_SRESET(1)) cp1_i0_ptr0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3327,7 +3332,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH - 1)), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_ptr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3345,7 +3351,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_i0_complete_q), @@ -3363,7 +3370,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) cp1_i1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3381,7 +3389,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(1), .NEEDS_SRESET(1)) cp1_i1_ptr0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3399,7 +3408,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH - 2)), .INIT(0), .NEEDS_SRESET(1)) cp1_i1_ptr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_complete), @@ -3417,7 +3427,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) cp2_i1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_i0_complete_q), @@ -3435,7 +3446,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_async_int_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3453,7 +3465,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) cp2_async_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_async_int_val), @@ -3471,7 +3484,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_completed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3489,7 +3503,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_completed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3507,7 +3522,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3525,7 +3541,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3543,7 +3560,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_n_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3561,7 +3579,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_n_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3579,7 +3598,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_bp_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3597,7 +3617,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_bp_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3615,7 +3636,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_br_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3633,7 +3655,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_br_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3651,7 +3674,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_br_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3669,7 +3693,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_br_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3687,7 +3712,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_db_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3705,7 +3731,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_db_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_db_val), @@ -3723,7 +3750,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_db_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3741,7 +3769,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_db_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i1_db_val), @@ -3759,7 +3788,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3777,7 +3807,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3795,7 +3826,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3813,7 +3845,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3831,7 +3864,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3849,7 +3883,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3867,7 +3902,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp2_i_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3885,7 +3921,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_iu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3903,7 +3940,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_iu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_iu_excvec_val), @@ -3921,7 +3959,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_iu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3939,7 +3978,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_iu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i1_iu_excvec_val), @@ -3957,7 +3997,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_lq_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3975,7 +4016,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_lq_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_lq_excvec_val), @@ -3993,7 +4035,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_lq_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4011,7 +4054,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_lq_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i1_lq_excvec_val), @@ -4029,7 +4073,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_xu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4047,7 +4092,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_xu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i0_xu_excvec_val), @@ -4065,7 +4111,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_xu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4083,7 +4130,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_xu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp1_i1_xu_excvec_val), @@ -4101,7 +4149,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i0_axu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4119,7 +4168,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i0_axu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), // Has to be tiup because axu doesn't need a valid to have a exception @@ -4137,7 +4187,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_i1_axu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4155,7 +4206,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp2_i1_axu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), // Has to be tiup because axu doesn't need a valid to have a exception @@ -4173,7 +4225,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_executed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4191,7 +4244,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_dispatched_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4209,7 +4263,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4227,7 +4282,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4245,7 +4301,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_n_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4263,7 +4320,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4281,7 +4339,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4304,7 +4363,8 @@ assign select_lq = for (i = 0; i <= `CPL_Q_DEPTH - 1; i = i + 1) begin : q_depth_gen tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act), @@ -4322,7 +4382,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_iu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4340,7 +4401,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_iu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4358,7 +4420,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_lq_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4376,7 +4439,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp1_lq_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4394,7 +4458,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_xu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4412,7 +4477,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp1_xu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4430,7 +4496,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_axu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4448,7 +4515,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp1_axu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4466,7 +4534,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp1_db_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4484,7 +4553,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_recirc_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4502,7 +4572,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_async_block_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4520,7 +4591,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_is_br_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4538,7 +4610,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_add_chk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4556,7 +4629,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_bp_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4574,7 +4648,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4592,7 +4667,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(excvec_act_v[i]), @@ -4613,7 +4689,8 @@ assign select_lq = endgenerate tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp0_br_bta_act), @@ -4631,7 +4708,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_v_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4649,7 +4727,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp1_br_bta_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp0_br_bta_act), @@ -4667,7 +4746,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_dispatched_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4685,7 +4765,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_dispatched_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -4703,7 +4784,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4721,7 +4803,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4739,7 +4822,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_fuse_nop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4757,7 +4841,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i0_error_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4775,7 +4860,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_valop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4793,7 +4879,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4811,7 +4898,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfgi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4829,7 +4917,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4847,7 +4936,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_rfmci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4865,7 +4955,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_isync_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4883,7 +4974,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4901,7 +4993,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4919,7 +5012,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_hyp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4937,7 +5031,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_sc_ill_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4955,7 +5050,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_dcr_ill_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4973,7 +5069,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_attn_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -4991,7 +5088,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_ehpriv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5009,7 +5107,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_folded_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5027,7 +5126,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_async_block_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5045,7 +5145,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_is_br_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5063,7 +5164,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_br_add_chk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5081,7 +5183,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_bp_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5099,7 +5202,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_rollover_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5117,7 +5221,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_isram_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5135,7 +5240,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i0_match_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i0_act), @@ -5153,7 +5259,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5171,7 +5278,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5189,7 +5297,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_fuse_nop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5207,7 +5316,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iu6_i1_error_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5225,7 +5335,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_valop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5243,7 +5354,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5261,7 +5373,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfgi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5279,7 +5392,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5297,7 +5411,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_rfmci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5315,7 +5430,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_isync_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5333,7 +5449,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5351,7 +5468,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5369,7 +5487,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_hyp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5387,7 +5506,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_sc_ill_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5405,7 +5525,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_dcr_ill_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5423,7 +5544,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_attn_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5441,7 +5563,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_ehpriv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5459,7 +5582,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_folded_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5477,7 +5601,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_async_block_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5495,7 +5620,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_is_br_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5513,7 +5639,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_br_add_chk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5531,7 +5658,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_bp_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5549,7 +5677,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_rollover_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5567,7 +5696,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_isram_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5585,7 +5715,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_i1_match_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rn_cp_iu6_i1_act), @@ -5603,7 +5734,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu6_uc_hold_rollover_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5621,7 +5753,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5639,7 +5772,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), // can gate if I use lq0_iu_execute_vld or lq0_iu_recirc_val @@ -5657,7 +5791,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5675,7 +5810,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5693,7 +5829,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_dacr_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5711,7 +5848,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq0_dacrw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5729,7 +5867,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq0_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5747,7 +5886,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lq0_eff_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_dear_val), @@ -5767,7 +5907,8 @@ assign select_lq = assign lq0_exception_val_d = lq0_iu_execute_vld & lq0_iu_exception_val; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_exception_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5785,7 +5926,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq0_exception_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5803,7 +5945,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5821,7 +5964,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq0_iu_execute_vld), @@ -5839,7 +5983,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_recirc_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5857,7 +6002,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5875,7 +6021,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5893,7 +6040,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5911,7 +6059,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5929,7 +6078,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_exception_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5947,7 +6097,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq1_exception_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5965,7 +6116,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_dacr_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -5983,7 +6135,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_dacrw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -6001,7 +6154,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq1_iu_execute_vld), @@ -6019,7 +6173,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) br_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(br_iu_execute_vld), @@ -6037,7 +6192,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu0_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6055,7 +6211,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu1_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6073,7 +6230,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6091,7 +6249,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) br_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(br_iu_execute_vld), @@ -6109,7 +6268,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(br_iu_execute_vld), @@ -6128,7 +6288,8 @@ assign select_lq = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_redirect_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), // removed br_iu_execute_vld @@ -6148,7 +6309,8 @@ assign select_lq = assign br_bta_d = {({`EFF_IFAR_ARCH-30{msr_cm_q}} & br_iu_bta[62 - `EFF_IFAR_ARCH:31]), br_iu_bta[32:61]}; tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) br_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(br_iu_execute_vld), @@ -6166,7 +6328,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6184,7 +6347,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) xu_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6202,7 +6366,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6220,7 +6385,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6238,7 +6404,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6258,7 +6425,8 @@ assign select_lq = assign xu_exception_val_d = xu_iu_execute_vld & xu_iu_exception_val; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_exception_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6276,7 +6444,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xu_exception_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6294,7 +6463,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mtiar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), // removed xu_iu_execute_vld because used in branches @@ -6312,7 +6482,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) xu_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6330,7 +6501,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xu_perf_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_iu_execute_vld), @@ -6348,7 +6520,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu1_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6366,7 +6539,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) xu1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu1_iu_execute_vld), @@ -6384,7 +6558,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6402,7 +6577,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) axu0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6420,7 +6596,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6438,7 +6615,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6456,7 +6634,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_n_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6474,7 +6653,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6492,7 +6672,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6510,7 +6691,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu0_exception_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6528,7 +6710,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu0_exception_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu0_iu_execute_vld), @@ -6546,7 +6729,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_execute_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6564,7 +6748,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) axu1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6582,7 +6767,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_n_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6600,7 +6786,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6618,7 +6805,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_n_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6636,7 +6824,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6654,7 +6843,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6672,7 +6862,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) axu1_exception_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6690,7 +6881,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) axu1_exception_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(axu1_iu_execute_vld), @@ -6708,7 +6900,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6726,7 +6919,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfgi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6744,7 +6938,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6762,7 +6957,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp3_rfmci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6780,7 +6976,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6798,7 +6995,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfgi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6816,7 +7014,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6834,7 +7033,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_cp4_rfmci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6852,7 +7052,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ld_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6870,7 +7071,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_st_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6888,7 +7090,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_fp_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6906,7 +7109,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ap_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6924,7 +7128,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_spv_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6942,7 +7147,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_epid_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6960,7 +7166,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_async_hold_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6978,7 +7185,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp2_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6996,7 +7204,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7014,7 +7223,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7032,7 +7242,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7050,7 +7261,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_attn_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7068,7 +7280,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_sc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7086,7 +7299,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_icmp_block_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7104,7 +7318,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush2ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7122,7 +7337,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush2ucode_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7140,7 +7356,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_flush_nonspec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7158,7 +7375,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_mispredict_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7176,7 +7394,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_async_int_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7194,7 +7413,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) cp3_async_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7212,7 +7432,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_iu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7230,7 +7451,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp3_iu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7248,7 +7470,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_lq_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7266,7 +7489,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp3_lq_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7284,7 +7508,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_xu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7302,7 +7527,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) cp3_xu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7320,7 +7546,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_axu_excvec_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7338,7 +7565,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp3_axu_excvec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7356,7 +7584,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_db_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7374,7 +7603,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp3_db_events_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7392,7 +7622,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7410,7 +7641,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_st_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7428,7 +7660,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_fp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7446,7 +7679,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ap_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7464,7 +7698,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_spv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7482,7 +7717,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_epid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7500,7 +7736,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp3_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7518,7 +7755,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_np1_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7536,7 +7774,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7555,7 +7794,8 @@ assign select_lq = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_preissue_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7584,7 +7824,8 @@ assign select_lq = begin : q_depth_gen if ((62-`EFF_IFAR_ARCH+i) > 31) tri_rlmlatch_p #(.INIT(`RESET_VECTOR>>(63-(62-`EFF_IFAR_ARCH+i))), .NEEDS_SRESET(1)) cp3_nia_a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp3_nia_act), @@ -7602,7 +7843,8 @@ assign select_lq = ); else tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp3_nia_a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp3_nia_act), @@ -7623,7 +7865,8 @@ assign select_lq = endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7641,7 +7884,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp5_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7659,7 +7903,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp6_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7677,7 +7922,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp7_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7695,7 +7941,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp8_rfi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7713,7 +7960,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_exc_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7731,7 +7979,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) flush_hold_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7749,7 +7998,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dp_cp_async_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7767,7 +8017,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dp_cp_async_bus_snoop_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7785,7 +8036,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_async_np1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7803,7 +8055,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_async_n_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7821,7 +8074,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_pc_stop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7839,7 +8093,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_stop_hold_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7857,7 +8112,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_mchk_disabled_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7875,7 +8131,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_mc_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7893,7 +8150,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_g_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7911,7 +8169,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_c_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7929,7 +8188,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7947,7 +8207,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_cdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7965,7 +8226,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7983,7 +8245,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gcdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8001,7 +8264,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_gmcdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8019,7 +8283,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dbsr_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8037,7 +8302,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(1)) cp4_dbsr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8055,7 +8321,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_eheir_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8073,7 +8340,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_esr_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8091,7 +8359,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_esr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8109,7 +8378,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_mcsr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8127,7 +8397,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_asyn_irpt_needed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8145,7 +8416,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_asyn_icmp_needed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8163,7 +8435,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) cp4_exc_nia_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp3_excvec_val), @@ -8181,7 +8454,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp4_dear_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8199,7 +8473,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8217,7 +8492,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_init_reset_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8235,7 +8511,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_np1_async_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8253,7 +8530,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dp_cp_hold_req_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8271,7 +8549,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dp_cp_bus_snoop_hold_req_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8289,7 +8568,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_de_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_msr_act), @@ -8307,7 +8587,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_pr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_msr_act), @@ -8325,7 +8606,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_msr_act), @@ -8343,7 +8625,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_cm_noact_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8361,7 +8644,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_gs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_msr_act), @@ -8379,7 +8663,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msr_me_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_msr_act), @@ -8397,7 +8682,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_edm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8415,7 +8701,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_idm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8433,7 +8720,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_icmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8451,7 +8739,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_brt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8469,7 +8758,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_irpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8487,7 +8777,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_trap_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8505,7 +8796,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac1_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8523,7 +8815,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac2_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8541,7 +8834,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac3_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8559,7 +8853,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac4_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8577,7 +8872,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8595,7 +8891,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8613,7 +8910,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8631,7 +8929,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac4_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8649,7 +8948,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr0_ret_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8667,7 +8967,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr1_iac12m_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8685,7 +8986,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr1_iac34m_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8703,7 +9005,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbcr3_ivc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8721,7 +9024,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_extgs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8739,7 +9043,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_dtlbgs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8757,7 +9062,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_itlbgs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8775,7 +9081,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_dsigs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8793,7 +9100,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_isigs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8811,7 +9119,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_duvd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8829,7 +9138,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_icm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8847,7 +9157,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epcr_gicm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8865,7 +9176,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ccr2_ucode_dis_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8883,7 +9195,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmu_mode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8901,7 +9214,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_xucr4_mmu_mchk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -8919,7 +9233,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_ram_active_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8937,7 +9252,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_ram_flush_thread_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8955,7 +9271,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_msrovride_enab_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8973,7 +9290,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) pc_iu_stop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -8991,7 +9309,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_iu_step_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9009,7 +9328,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spr_perf_mux_ctrls_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9027,7 +9347,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pc_iu_dbg_action_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9045,7 +9366,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_single_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9063,7 +9385,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_single_issue_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9081,7 +9404,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) spr_ivpr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9099,7 +9423,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) spr_givpr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9117,7 +9442,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9135,7 +9461,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9153,7 +9480,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9171,7 +9499,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) spr_iac4_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cp2_complete_act), @@ -9189,7 +9518,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_step_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9207,7 +9537,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uncond_dbg_event_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9225,7 +9556,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) external_mchk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9243,7 +9575,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9261,7 +9594,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dec_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9279,7 +9613,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) udec_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9297,7 +9632,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) perf_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9315,7 +9651,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9333,7 +9670,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) crit_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9351,7 +9689,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9369,7 +9708,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9387,7 +9727,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9405,7 +9746,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdec_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9423,7 +9765,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9441,7 +9784,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9459,7 +9803,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9477,7 +9822,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gcdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9495,7 +9841,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gmcdbell_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9513,7 +9860,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbsr_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9531,7 +9879,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fex_int_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9549,7 +9898,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) async_delay_cnt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9567,7 +9917,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_lq_recirc_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9585,7 +9936,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_stop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9603,7 +9955,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_stop_other_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9621,7 +9974,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_act_err_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9639,7 +9993,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_dbg_act_ext_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9657,7 +10012,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbg_int_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9675,7 +10031,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dbg_event_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9693,7 +10050,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_i0_dispatched_delay_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9711,7 +10069,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`CPL_Q_DEPTH), .INIT(0), .NEEDS_SRESET(1)) cp1_i1_dispatched_delay_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9729,7 +10088,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu7_i0_is_folded_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9747,7 +10107,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu7_i1_is_folded_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9765,7 +10126,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) select_reset_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9783,7 +10145,8 @@ assign select_lq = ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) xu_iu_rest_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(select_reset), @@ -9801,7 +10164,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) attn_hold_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9820,7 +10184,8 @@ assign select_lq = assign flush_delay_d = {flush_cond, flush_delay_q[0]}; tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) flush_delay_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9838,7 +10203,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_nonspec_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9856,7 +10222,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_pt_fault_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9874,7 +10241,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_lrat_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9892,7 +10260,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_tlb_inelig_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9910,7 +10279,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_multihit_err_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9928,7 +10298,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_par_err_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9946,7 +10317,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lru_par_err_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9964,7 +10336,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -9982,7 +10355,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reload_hit_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -10000,7 +10374,8 @@ assign select_lq = ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) nonspec_hit_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -10019,7 +10394,8 @@ assign select_lq = tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -10038,7 +10414,8 @@ assign select_lq = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eheir_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -10059,7 +10436,8 @@ assign select_lq = tri_rlmreg_p #(.WIDTH(4), .INIT(0)) perf_bus_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(func_sl_thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/iuq_cpl_top.v b/dev/verilog/work/iuq_cpl_top.v index 421a209..43ff8f8 100755 --- a/dev/verilog/work/iuq_cpl_top.v +++ b/dev/verilog/work/iuq_cpl_top.v @@ -36,8 +36,8 @@ module iuq_cpl_top( // Clocks - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Pervasive input tc_ac_ccflush_dc, @@ -757,7 +757,8 @@ module iuq_cpl_top( iuq_cpl iuq_cpl0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), .clkoff_dc_b(clkoff_dc_b), .d_mode_dc(d_mode_dc), @@ -1129,7 +1130,8 @@ module iuq_cpl_top( iuq_cpl iuq_cpl1( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), .clkoff_dc_b(clkoff_dc_b), .d_mode_dc(d_mode_dc), @@ -1499,7 +1501,8 @@ module iuq_cpl_top( iuq_dbg iuq_cpl_dbg( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .clkoff_b(clkoff_b), diff --git a/dev/verilog/work/iuq_dbg.v b/dev/verilog/work/iuq_dbg.v index 3abd9a0..6a8f7bc 100755 --- a/dev/verilog/work/iuq_dbg.v +++ b/dev/verilog/work/iuq_dbg.v @@ -42,8 +42,8 @@ module iuq_dbg( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input thold_2, // Connect to slp if unit uses slp input pc_iu_sg_2, input clkoff_b, @@ -156,7 +156,8 @@ module iuq_dbg( tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(thold_0_b), .sg(pc_iu_sg_0), @@ -174,7 +175,8 @@ module iuq_dbg( tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trace_bus_enable_q), .thold_b(thold_0_b), .sg(pc_iu_sg_0), @@ -192,7 +194,8 @@ module iuq_dbg( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trace_bus_enable_q), .thold_b(thold_0_b), .sg(pc_iu_sg_0), @@ -210,7 +213,8 @@ module iuq_dbg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trace_bus_enable_q), .thold_b(thold_0_b), .sg(pc_iu_sg_0), @@ -231,7 +235,8 @@ module iuq_dbg( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({thold_2, pc_iu_sg_2}), .q( {thold_1, pc_iu_sg_1}) @@ -240,7 +245,8 @@ module iuq_dbg( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({thold_1, pc_iu_sg_1}), .q( {thold_0, pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_dec_top.v b/dev/verilog/work/iuq_dec_top.v index 319acfc..6027a6a 100755 --- a/dev/verilog/work/iuq_dec_top.v +++ b/dev/verilog/work/iuq_dec_top.v @@ -42,7 +42,8 @@ module iuq_dec_top( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input clkoff_b, @@ -301,7 +302,8 @@ module iuq_dec_top( iuq_idec fx_dec0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -444,7 +446,8 @@ module iuq_dec_top( iuq_idec fx_dec1( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -587,7 +590,8 @@ module iuq_dec_top( iuq_axu_fu_dec axu_dec0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .i_dec_si(scan_in[2]), .i_dec_so(scan_out[2]), .pc_iu_sg_2(pc_iu_sg_2), @@ -649,7 +653,8 @@ module iuq_dec_top( iuq_axu_fu_dec axu_dec1( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .i_dec_si(scan_in[3]), .i_dec_so(scan_out[3]), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), diff --git a/dev/verilog/work/iuq_dispatch.v b/dev/verilog/work/iuq_dispatch.v index 3c63a7d..a031553 100755 --- a/dev/verilog/work/iuq_dispatch.v +++ b/dev/verilog/work/iuq_dispatch.v @@ -40,7 +40,8 @@ module iuq_dispatch( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input pc_iu_func_slp_sl_thold_2, @@ -2965,7 +2966,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES - 2)) fx0_high_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -2983,7 +2985,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES - 2)) fx1_high_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3001,7 +3004,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES - 2)) lq_cmdq_high_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3019,7 +3023,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES - 2)) sq_cmdq_high_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3037,7 +3042,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES - 2)) fu0_high_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3055,7 +3061,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES - 2)) fu1_high_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3073,7 +3080,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES / 2)) fx0_med_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3091,7 +3099,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES / 2)) fx1_med_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3109,7 +3118,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES / 2)) lq_cmdq_med_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3127,7 +3137,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES / 2)) sq_cmdq_med_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3145,7 +3156,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES / 2)) fu0_med_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3163,7 +3175,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES / 2)) fu1_med_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3184,7 +3197,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES)) fx0_total_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3202,7 +3216,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES)) fx1_total_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3220,7 +3235,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES)) lq_cmdq_total_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3238,7 +3254,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES)) sq_cmdq_total_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3256,7 +3273,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES)) fu0_total_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3274,7 +3292,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES)) fu1_total_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3292,7 +3311,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3310,7 +3330,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3328,7 +3349,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmlatch_p #(.INIT(0)) iu_xu_credits_returned_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3347,7 +3369,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) dual_issue_use_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3365,7 +3388,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1)) last_thread_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(last_thread_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3383,7 +3407,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3401,7 +3426,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3419,7 +3445,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3437,7 +3464,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3455,7 +3483,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3473,7 +3502,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3491,7 +3521,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ivax_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3509,7 +3540,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3527,7 +3559,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_flush_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3545,7 +3578,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3563,7 +3597,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3581,7 +3616,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(funcslp_force), .thold_b(pc_iu_func_slp_sl_thold_0_b), @@ -3599,7 +3635,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3617,7 +3654,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_fusion_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3635,7 +3673,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) total_pri_mask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3653,7 +3692,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) high_pri_mask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3671,7 +3711,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) med_pri_mask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3689,7 +3730,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) low_pri_mask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3712,7 +3754,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(8), .INIT(0)) low_pri_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(low_pri_cnt_act[i]), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3730,7 +3773,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(6), .INIT(0)) low_pri_max_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3751,7 +3795,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3774,7 +3819,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3792,7 +3838,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3810,7 +3857,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3828,7 +3876,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3846,7 +3895,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3867,7 +3917,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx0_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3885,7 +3936,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx1_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3903,7 +3955,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_lq_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3921,7 +3974,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_sq_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3939,7 +3993,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu0_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3957,7 +4012,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu1_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3975,7 +4031,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx0_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3993,7 +4050,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx1_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4011,7 +4069,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_lq_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4029,7 +4088,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_sq_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4047,7 +4107,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu0_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4065,7 +4126,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu1_credit_ok_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4089,7 +4151,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}) @@ -4098,7 +4161,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2; tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0, pc_iu_func_slp_sl_thold_0, pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_ibuf.v b/dev/verilog/work/iuq_ibuf.v index 0a8a3d5..c70a114 100755 --- a/dev/verilog/work/iuq_ibuf.v +++ b/dev/verilog/work/iuq_ibuf.v @@ -41,7 +41,8 @@ module iuq_ibuf( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input clkoff_b, @@ -805,7 +806,8 @@ assign ib_id_iu4_1_fuse_data = iu4_1_fuse_data_q; tri_rlmlatch_p #(.INIT(0)) uc_select_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -824,7 +826,8 @@ tri_rlmlatch_p #(.INIT(0)) uc_select_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(buffer_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -843,7 +846,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(buffer_head_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -862,7 +866,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(buffer_tail_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -881,7 +886,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch( tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu3_val[0]), //tiup, .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -900,7 +906,8 @@ tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_la tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_buffer_act[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -919,7 +926,8 @@ tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch( tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_buffer_act[1]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -938,7 +946,8 @@ tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -957,7 +966,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -976,7 +986,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -995,7 +1006,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1014,7 +1026,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1033,7 +1046,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1052,7 +1066,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1071,7 +1086,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1090,7 +1106,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1109,7 +1126,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1128,7 +1146,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_0_fuse_val_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1147,7 +1166,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1166,7 +1186,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1185,7 +1206,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1204,7 +1226,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1223,7 +1246,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1242,7 +1266,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1261,7 +1286,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_valid_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1280,7 +1306,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1299,7 +1326,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_1_fuse_val_din), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1318,7 +1346,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1337,7 +1366,8 @@ tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1356,7 +1386,8 @@ tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1380,7 +1411,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -1390,7 +1422,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_ic.v b/dev/verilog/work/iuq_ic.v index 78ea244..57f79de 100755 --- a/dev/verilog/work/iuq_ic.v +++ b/dev/verilog/work/iuq_ic.v @@ -42,8 +42,8 @@ module iuq_ic( inout vcs, inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ac_ccflush_dc, input tc_ac_scan_dis_dc_b, @@ -527,9 +527,8 @@ module iuq_ic( .gnd(gnd), .vdd(vdd), .vcs(vdd), - - // CLOCK and CLOCKCONTROL ports - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_init_reset(pc_iu_init_reset), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), @@ -697,7 +696,8 @@ module iuq_ic( iuq_ic_select iuq_ic_select0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), @@ -828,7 +828,8 @@ module iuq_ic( .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), .pc_iu_time_sl_thold_0(pc_iu_time_sl_thold_0), @@ -1013,11 +1014,11 @@ module iuq_ic( .event_bus_enable(pc_iu_event_bus_enable) ); - iuq_ic_miss iuq_ic_miss0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -1153,7 +1154,8 @@ module iuq_ic( tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0)) perf_bus_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1177,7 +1179,8 @@ module iuq_ic( tri_plat #(.WIDTH(1)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din(pc_iu_bo_enable_3), .q(pc_iu_bo_enable_2) @@ -1186,7 +1189,8 @@ module iuq_ic( tri_plat #(.WIDTH(11)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, @@ -1215,7 +1219,8 @@ module iuq_ic( tri_plat #(.WIDTH(11)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, diff --git a/dev/verilog/work/iuq_ic_dir.v b/dev/verilog/work/iuq_ic_dir.v index c75f531..61f4b7b 100755 --- a/dev/verilog/work/iuq_ic_dir.v +++ b/dev/verilog/work/iuq_ic_dir.v @@ -42,8 +42,8 @@ module iuq_ic_dir( inout vcs, inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_0_b, input pc_iu_func_slp_sl_thold_0_b, input pc_iu_time_sl_thold_0, @@ -718,8 +718,9 @@ module iuq_ic_dir( tri_128x34_4w_1r1w idir( .gnd(gnd), .vdd(vdd), - .vcs(vdd), - .nclk(nclk), + .vcs(), + .clk(clk), + .rst(rst), .rd_act(dir_rd_act), .wr_act(dir_write), .sg_0(pc_iu_sg_0), @@ -866,8 +867,9 @@ module iuq_ic_dir( tri_512x162_4w_0 idata( .gnd(gnd), .vdd(vdd), - .vcs(vdd), - .nclk(nclk), + .vcs(), + .clk(clk), + .rst(rst), .ccflush_dc(tc_ac_ccflush_dc), .lcb_clkoff_dc_b(g6t_clkoff_b), .lcb_d_mode_dc(g6t_d_mode), @@ -1436,7 +1438,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1466,7 +1469,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), // ??? Is this act worth it? Only tid, 2ucode, & 2ucode_type use for non-slp .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1487,7 +1491,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(0)) iu1_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1505,7 +1510,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_index51_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1523,7 +1529,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_inval_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1541,7 +1548,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1570,7 +1578,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_read_erat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1590,7 +1599,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1608,7 +1618,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_rd_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1627,7 +1638,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1656,7 +1668,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1676,7 +1689,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH-10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1695,7 +1709,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_slp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1713,7 +1728,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_valid_l2), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1731,7 +1747,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_valid_l2), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1749,7 +1766,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_index51_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1767,7 +1785,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_inval_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1785,7 +1804,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1816,7 +1836,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_read_erat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1834,7 +1855,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_cam_change_etc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1854,7 +1876,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0), .NEEDS_SRESET(0)) iu2_stored_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1872,7 +1895,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu2_dir_rd_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1890,7 +1914,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_dir_parity_err_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1915,7 +1940,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) dir_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_val_act), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1933,7 +1959,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) dir_lru_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_lru_act[a/8]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1954,7 +1981,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu3_miss_flush( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1984,7 +2012,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu3_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2004,7 +2033,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu2_valid_l2), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2022,7 +2052,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu2_valid_l2), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2040,7 +2071,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu2_valid_l2), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2058,7 +2090,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) iu3_erat_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2076,7 +2109,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_multihit_err_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2094,7 +2128,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu3_multihit_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2112,7 +2147,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_data_parity_err_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2130,7 +2166,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu3_parity_needs_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2148,7 +2185,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) iu3_parity_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2166,7 +2204,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) ici_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2184,7 +2223,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2202,7 +2242,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) spr_ic_idir_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2220,7 +2261,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu1_spr_idir_read_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2238,7 +2280,8 @@ module iuq_ic_dir( tri_rlmlatch_p #(.INIT(0)) iu2_spr_idir_read_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2256,7 +2299,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_spr_idir_lru_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dir_dataout_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2294,7 +2338,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0)) stored_erat_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stored_erat_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2312,7 +2357,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) stored_erat_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stored_erat_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2330,7 +2376,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stored_erat_u_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stored_erat_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2357,7 +2404,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_instr_count_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2375,7 +2423,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_t_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2396,7 +2445,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2414,7 +2464,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_iu_inj_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2439,7 +2490,8 @@ module iuq_ic_dir( tri_rlmreg_p #(.INIT(0), .WIDTH(41), .NEEDS_SRESET(0)) ab_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_abist_ena_dc), .thold_b(pc_iu_abst_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_ic_ierat.v b/dev/verilog/work/iuq_ic_ierat.v index a267c90..1e0501d 100755 --- a/dev/verilog/work/iuq_ic_ierat.v +++ b/dev/verilog/work/iuq_ic_ierat.v @@ -42,8 +42,8 @@ module iuq_ic_ierat( inout vcs, // CLOCK and CLOCKCONTROL ports - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_init_reset, input tc_ccflush_dc, input tc_scan_dis_dc_b, @@ -4470,7 +4470,8 @@ assign ex6_data_maskpar = .gnd(gnd), .vdd(vdd), .vcs(vcs), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ccflush_dc), .tc_scan_dis_dc_b(tc_scan_dis_dc_b), @@ -4677,7 +4678,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4695,7 +4697,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4713,7 +4716,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4731,7 +4735,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex1_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4749,7 +4754,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4767,7 +4773,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4785,7 +4792,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex1_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4803,7 +4811,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex1_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4822,7 +4831,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4840,7 +4850,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4858,7 +4869,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4876,7 +4888,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4894,7 +4907,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4912,7 +4926,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4930,7 +4945,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex2_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4948,7 +4964,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex2_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4968,7 +4985,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4986,7 +5004,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5004,7 +5023,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5022,7 +5042,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5040,7 +5061,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5058,7 +5080,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5076,7 +5099,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex3_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5094,7 +5118,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5112,7 +5137,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(2+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex3_eratsx_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(eratsx_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5131,7 +5157,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5149,7 +5176,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5167,7 +5195,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5185,7 +5214,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5203,7 +5233,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5221,7 +5252,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5239,7 +5271,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex4_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5257,7 +5290,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex4_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5276,7 +5310,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(data_out_width), .INIT(0), .NEEDS_SRESET(1)) ex4_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_data_out_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5295,7 +5330,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5313,7 +5349,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5331,7 +5368,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5349,7 +5387,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5367,7 +5406,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5385,7 +5425,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5403,7 +5444,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex5_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5421,7 +5463,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5440,7 +5483,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(rs_data_width), .INIT(0), .NEEDS_SRESET(1)) ex5_data_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5459,7 +5503,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5477,7 +5522,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5495,7 +5541,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5513,7 +5560,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ra_entry_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5531,7 +5579,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5549,7 +5598,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5567,7 +5617,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex6_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5585,7 +5636,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex6_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5605,7 +5657,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(rs_data_width), .INIT(0), .NEEDS_SRESET(1)) ex6_data_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5625,7 +5678,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5643,7 +5697,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5661,7 +5716,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex7_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5679,7 +5735,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_flush_enab_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5697,7 +5754,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_n_flush_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_or_iu2_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5715,7 +5773,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(not_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5733,7 +5792,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5751,7 +5811,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_flushed_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5769,7 +5830,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_req_inprogress_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5787,7 +5849,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5805,7 +5868,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) iu1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5823,7 +5887,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) iu1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5841,7 +5906,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5859,7 +5925,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5877,7 +5944,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5895,7 +5963,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu2_perf_itlb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5913,7 +5982,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) iu2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5931,7 +6001,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) iu2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5949,7 +6020,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5967,7 +6039,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5985,7 +6058,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_or_iu2_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6003,7 +6077,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_or_iu2_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6021,7 +6096,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu2_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_or_iu2_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6039,7 +6115,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) iu2_isi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(not_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6057,7 +6134,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_tlbreq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(notlb_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6075,7 +6153,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(num_entry), .INIT(0), .NEEDS_SRESET(1)) iu2_multihit_b_pt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6093,7 +6172,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(num_entry-1), .INIT(0), .NEEDS_SRESET(1)) iu2_first_hit_entry_pt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6111,7 +6191,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) iu2_cam_cmp_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_cmp_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6129,7 +6210,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) iu2_array_cmp_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu1_cmp_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6147,7 +6229,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_cam_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_rd_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6165,7 +6248,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_array_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_rd_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6183,7 +6267,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS+1), .INIT(0), .NEEDS_SRESET(1)) ex3_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(not_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6201,7 +6286,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS+3), .INIT(0), .NEEDS_SRESET(1)) ex4_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6219,7 +6305,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex4_ieen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6237,7 +6324,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex5_ieen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6255,7 +6343,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS+num_entry_log2), .INIT(0), .NEEDS_SRESET(1)) ex6_ieen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6273,7 +6362,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6296,7 +6386,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6317,7 +6408,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) entry_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_valid_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6335,7 +6427,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) entry_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6353,7 +6446,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(watermark_width), .INIT(13), .NEEDS_SRESET(1)) watermark_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6371,7 +6465,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(eptr_width), .INIT(0), .NEEDS_SRESET(1)) eptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mmucr1_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6389,7 +6484,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(lru_width), .INIT(0), .NEEDS_SRESET(1)) lru_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lru_update_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6407,7 +6503,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lru_update_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(not_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6425,7 +6522,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lru_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(debug_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6443,7 +6541,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_write_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6461,7 +6560,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_read_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6479,7 +6579,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_ord_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6498,7 +6599,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cp_ic_csinv_comp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6516,7 +6618,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), // keep this as tiup, bit(1) is I$ backinv .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6534,7 +6637,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6552,7 +6656,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(epn_width), .INIT(0), .NEEDS_SRESET(1)) snoop_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6570,7 +6675,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) por_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6589,7 +6695,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6607,7 +6714,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6625,7 +6733,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_mm_ierat_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6643,7 +6752,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_xu_ierat_ex2_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6661,7 +6771,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ccr2_frat_paranoia_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6679,7 +6790,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) ccr2_notlb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6697,7 +6809,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mchk_flash_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu2_or_iu3_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6715,7 +6828,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6733,7 +6847,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) iu1_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trace_bus_enable_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6751,7 +6866,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) iu2_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(debug_grffence_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6769,7 +6885,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu1_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6787,7 +6904,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu2_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6805,7 +6923,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu3_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6823,7 +6942,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6841,7 +6961,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6859,7 +6980,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6877,7 +6999,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6895,7 +7018,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6913,7 +7037,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6931,7 +7056,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6949,7 +7075,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_rel_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6967,7 +7094,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoop_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6985,7 +7113,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_err_ierat_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7003,7 +7132,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_pc_err_ierat_parity_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7022,7 +7152,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) trace_bus_enable_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7040,7 +7171,8 @@ assign ex6_data_maskpar = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_grffence_en_dc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7058,7 +7190,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7076,7 +7209,8 @@ assign ex6_data_maskpar = tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7229,7 +7363,8 @@ assign ex6_data_maskpar = tri_plat #(.WIDTH(4)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, @@ -7244,7 +7379,8 @@ assign ex6_data_maskpar = tri_plat #(.WIDTH(4)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din({pc_func_sl_thold_1, pc_func_slp_sl_thold_1, @@ -7282,7 +7418,8 @@ assign ex6_data_maskpar = .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(pc_cfg_slp_sl_force), .thold_b(pc_cfg_slp_sl_thold_0_b), .dclk(lcb_dclk), diff --git a/dev/verilog/work/iuq_ic_miss.v b/dev/verilog/work/iuq_ic_miss.v index 2ae0891..ce3fc2b 100755 --- a/dev/verilog/work/iuq_ic_miss.v +++ b/dev/verilog/work/iuq_ic_miss.v @@ -42,7 +42,8 @@ module iuq_ic_miss( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -133,11 +134,10 @@ module iuq_ic_miss( inout vdd; - inout gnd; - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -1438,7 +1438,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1456,7 +1457,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(4), .INIT(0)) bp_config_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1474,7 +1476,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) an_ac_reld_data_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1492,7 +1495,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(5), .INIT(0)) an_ac_reld_core_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1510,7 +1514,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) an_ac_reld_qw_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1528,7 +1533,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r1_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1546,7 +1552,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r1_qw_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1564,7 +1571,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(128), .INIT(0)) reld_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_r2_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1582,7 +1590,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r2_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1600,7 +1609,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r2_qw_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_r2_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1618,7 +1628,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) r2_crit_qw_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1636,7 +1647,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r3_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1654,7 +1666,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) r3_loaded_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1672,7 +1685,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1690,7 +1704,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_ue_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1708,7 +1723,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) request_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_or_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1726,7 +1742,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) req_ctag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(icd_icm_any_iu2_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1744,7 +1761,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0)) req_ra_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(icd_icm_any_iu2_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1762,7 +1780,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(5), .INIT(0)) req_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(icd_icm_any_iu2_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1780,7 +1799,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(4), .INIT(0)) req_userdef_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(icd_icm_any_iu2_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1798,7 +1818,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) iu3_miss_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(icd_icm_any_iu2_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1822,7 +1843,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(CHECK_ECC+1), .INIT({1'b1, {CHECK_ECC{1'b0}} })) miss_tid_sm_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_or_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1840,7 +1862,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) miss_count_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_or_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1861,7 +1884,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flush_occurred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1879,7 +1903,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flushed_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1897,7 +1922,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_inval_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1915,7 +1941,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_block_fp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_or_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1933,7 +1960,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1951,7 +1979,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_ue_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1969,7 +1998,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_wrote_dir_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1987,7 +2017,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_need_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_or_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2010,7 +2041,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH - 2), .INIT(0)) miss_addr_real_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2028,7 +2060,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH - 10), .INIT(0)) miss_addr_eff_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2046,7 +2079,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) miss_ci_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2064,7 +2098,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) miss_endian_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2082,7 +2117,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) miss_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2100,7 +2136,8 @@ assign next_lru_way[3] = tri_rlmlatch_p #(.INIT(0)) miss_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(miss_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2118,7 +2155,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(4), .INIT(0)) miss_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_r2_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2139,7 +2177,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_next_cycle_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2157,7 +2196,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(default_reld_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2180,7 +2220,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2201,7 +2242,8 @@ assign next_lru_way[3] = tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) miss_prefetch_perf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_ic_select.v b/dev/verilog/work/iuq_ic_select.v index ddca4cd..6be58d2 100755 --- a/dev/verilog/work/iuq_ic_select.v +++ b/dev/verilog/work/iuq_ic_select.v @@ -42,8 +42,8 @@ module iuq_ic_select( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_0_b, input pc_iu_func_slp_sl_thold_0_b, input pc_iu_sg_0, @@ -1055,7 +1055,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1073,7 +1074,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_target_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1091,7 +1093,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) an_ac_back_inv_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(back_inv_addr_act), //back_inv_d, .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1109,7 +1112,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_idir_read_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1127,7 +1131,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) spr_idir_row_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1154,7 +1159,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) oldest_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1175,7 +1181,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_need_prefetch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1198,7 +1205,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-4), .INIT(0)) iu0_prefetch_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu0_prefetch_ifar_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1219,7 +1227,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH((`THREADS*`THREADS-1+1)), .INIT(0)) lq_iu_icbi_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1242,7 +1251,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) lq_iu_icbi_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq_iu_icbi_val[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1263,7 +1273,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0)) back_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1281,7 +1292,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) back_inv_icbi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1299,7 +1311,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1317,7 +1330,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1335,7 +1349,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1353,7 +1368,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1371,7 +1387,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_ic_stop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1389,7 +1406,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) pc_iu_pm_fetch_halt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1407,7 +1425,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ierat_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1425,7 +1444,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1443,7 +1463,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1461,7 +1482,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_flip_index51_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1488,7 +1510,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0)) iu0_last_tid_sent_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1517,7 +1540,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu0_sent_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1549,7 +1573,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) iu0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1567,7 +1592,8 @@ module iuq_ic_select( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1608,7 +1634,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-10), .INIT(0)) stored_erat_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stored_erat_act[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1628,7 +1655,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) stored_erat_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1648,7 +1676,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1666,7 +1695,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1684,7 +1714,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1702,7 +1733,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_into_uc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1725,7 +1757,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) cp_flush_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1746,7 +1779,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1764,7 +1798,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1782,7 +1817,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_slp_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1800,7 +1836,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) br_iu_redirect_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1818,7 +1855,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) br_iu_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1836,7 +1874,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) next_fetch_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1854,7 +1893,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1872,7 +1912,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1895,7 +1936,8 @@ module iuq_ic_select( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) perf_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_idec.v b/dev/verilog/work/iuq_idec.v index 352c5e9..0a9e05d 100755 --- a/dev/verilog/work/iuq_idec.v +++ b/dev/verilog/work/iuq_idec.v @@ -42,7 +42,8 @@ module iuq_idec( vdd, gnd, - nclk, + clk, + rst, pc_iu_sg_2, pc_iu_func_sl_thold_2, clkoff_b, @@ -179,7 +180,8 @@ module iuq_idec( `include "tri_a2o.vh" inout vdd; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_sg_2; input pc_iu_func_sl_thold_2; input clkoff_b; @@ -5570,7 +5572,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_vld( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5588,7 +5591,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ucode( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5606,7 +5610,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_2ucode( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5624,7 +5629,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_fuse_nop( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5642,7 +5648,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_error( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5660,7 +5667,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_btb_entry( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5678,7 +5686,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_btb_hist( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5696,7 +5705,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_bta_val( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5714,7 +5724,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(20), .INIT(0)) iu5_fusion( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5732,7 +5743,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_lq( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5750,7 +5762,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_sq( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5768,7 +5781,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5786,7 +5800,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5804,7 +5819,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5822,7 +5838,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5840,7 +5857,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_valop( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5858,7 +5876,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_ord( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5876,7 +5895,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_cord( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5894,7 +5914,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_spec( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5912,7 +5933,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_type_fp( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5930,7 +5952,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_type_ap( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5948,7 +5971,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_type_spv( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5966,7 +5990,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_type_st( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5984,7 +6009,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_async_block( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6002,7 +6028,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_np1_flush( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6020,7 +6047,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_core_block( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6038,7 +6066,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_isram( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6056,7 +6085,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_isload( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6074,7 +6104,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_isstore( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6092,7 +6123,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu5_instr( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6110,7 +6142,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_ifar( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6128,7 +6161,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_bta( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6146,7 +6180,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu5_ilat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6164,7 +6199,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_t1_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6182,7 +6218,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t1_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6200,7 +6237,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t1_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6218,7 +6256,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_t2_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6236,7 +6275,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t2_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6254,7 +6294,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t2_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6272,7 +6313,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_t3_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_valid_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6290,7 +6332,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t3_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6308,7 +6351,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t3_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6326,7 +6370,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_s1_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6344,7 +6389,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s1_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6362,7 +6408,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s1_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6380,7 +6427,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_s2_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6398,7 +6446,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s2_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6416,7 +6465,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s2_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6434,7 +6484,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_s3_v( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6452,7 +6503,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s3_a( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6470,7 +6522,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s3_t( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6488,7 +6541,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_br_pred( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6506,7 +6560,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_bh_update( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6524,7 +6579,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh0_hist( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6542,7 +6598,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh1_hist( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6560,7 +6617,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh2_hist( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6578,7 +6636,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(18), .INIT(0)) iu5_gshare( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6596,7 +6655,8 @@ assign no_pre = tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ls_ptr( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6614,7 +6674,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) iu5_match( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu5_instr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6632,7 +6693,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_epcr_dgtmi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6650,7 +6712,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_msrp_uclep_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6668,7 +6731,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_msr_pr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6686,7 +6750,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_msr_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6704,7 +6769,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_msr_ucle_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6722,7 +6788,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) spr_ccr2_ucode_dis_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6740,7 +6807,8 @@ assign no_pre = tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6821,7 +6889,8 @@ assign no_pre = tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -6831,7 +6900,8 @@ assign no_pre = tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_ifetch.v b/dev/verilog/work/iuq_ifetch.v index 9fad2bb..164234c 100755 --- a/dev/verilog/work/iuq_ifetch.v +++ b/dev/verilog/work/iuq_ifetch.v @@ -39,8 +39,8 @@ `include "tri_a2o.vh" module iuq_ifetch( - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ac_ccflush_dc, input tc_ac_scan_dis_dc_b, @@ -790,7 +790,8 @@ module iuq_ifetch( .spr_ic_prefetch_dis(spr_ic_prefetch_dis), .spr_perf_event_mux_ctrls(spr_perf_event_mux_ctrls), .spr_cp_perf_event_mux_ctrls(spr_cp_perf_event_mux_ctrls), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -809,7 +810,8 @@ module iuq_ifetch( .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), @@ -1158,7 +1160,8 @@ module iuq_ifetch( .spr_single_issue(spr_single_issue_int[i]), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -1340,7 +1343,8 @@ module iuq_ifetch( .rm_ib_iu3_instr(rm_ib_iu3_instr), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -1362,7 +1366,8 @@ module iuq_ifetch( iuq_uc iuq_uc0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .tc_ac_ccflush_dc(tc_ac_ccflush_dc), @@ -1437,7 +1442,8 @@ module iuq_ifetch( iuq_dbg iuq_dbg0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .thold_2(pc_iu_func_slp_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .clkoff_b(clkoff_b), diff --git a/dev/verilog/work/iuq_ram.v b/dev/verilog/work/iuq_ram.v index f1839f3..8f18dde 100755 --- a/dev/verilog/work/iuq_ram.v +++ b/dev/verilog/work/iuq_ram.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -46,7 +46,8 @@ module iuq_ram( rm_ib_iu3_instr, vdd, gnd, - nclk, + clk, + rst, pc_iu_sg_2, pc_iu_func_sl_thold_2, clkoff_b, @@ -78,8 +79,8 @@ module iuq_ram( //pervasive inout vdd; inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_sg_2; input pc_iu_func_sl_thold_2; input clkoff_b; @@ -179,7 +180,8 @@ module iuq_ram( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -198,7 +200,8 @@ module iuq_ram( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -217,7 +220,8 @@ module iuq_ram( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ram_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -236,7 +240,8 @@ module iuq_ram( tri_rlmreg_p #(.WIDTH(36), .INIT(0)) ram_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ram_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -255,7 +260,8 @@ module iuq_ram( tri_rlmlatch_p #(.INIT(0)) ram_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -278,7 +284,8 @@ module iuq_ram( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -288,7 +295,8 @@ module iuq_ram( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_rn.v b/dev/verilog/work/iuq_rn.v index e37e92b..05215ab 100755 --- a/dev/verilog/work/iuq_rn.v +++ b/dev/verilog/work/iuq_rn.v @@ -42,7 +42,8 @@ module iuq_rn( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types input pc_iu_sg_2, input clkoff_b, @@ -2659,7 +2660,8 @@ module iuq_rn( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + `GPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`GPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) gpr_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -2763,7 +2765,8 @@ module iuq_rn( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((8 + `CR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`CR_POOL), .STORAGE_WIDTH(`CR_POOL_ENC)) cr_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -2860,7 +2863,8 @@ module iuq_rn( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((2 + `LR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`LR_POOL), .STORAGE_WIDTH(`LR_POOL_ENC)) lr_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -2957,7 +2961,8 @@ module iuq_rn( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((1 + `CTR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`CTR_POOL), .STORAGE_WIDTH(`CTR_POOL_ENC)) ctr_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -3054,7 +3059,8 @@ module iuq_rn( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((1 + `XER_UCODE_POOL)), .REGISTER_RENAME_DEPTH(`XER_POOL), .STORAGE_WIDTH(`XER_POOL_ENC)) xer_rn_map( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -3150,7 +3156,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(`CPL_Q_DEPTH)) next_itag_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3169,7 +3176,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(`CPL_Q_DEPTH)) next_itag_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3188,7 +3196,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH_ENC+1)), .INIT(`CPL_Q_DEPTH)) cp_high_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3207,7 +3216,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`CPL_Q_DEPTH_ENC+1)), .INIT(`CPL_Q_DEPTH/2)) cp_med_credit_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3226,7 +3236,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) ucode_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3245,7 +3256,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) ucode_cnt_save_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cp_rn_uc_credit_free), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3264,7 +3276,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3283,7 +3296,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) cp_flush_into_uc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3302,7 +3316,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3320,7 +3335,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3338,7 +3354,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) cp_rn_empty_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3356,7 +3373,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) high_pri_mask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3374,7 +3392,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(19), .INIT(0)) fdis_frn_iu6_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3393,7 +3412,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3412,7 +3432,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3431,7 +3452,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3450,7 +3472,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) frn_fdis_iu6_i0_ucode_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3469,7 +3492,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3488,7 +3512,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_fuse_nop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3507,7 +3532,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3526,7 +3552,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_sq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3545,7 +3572,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3564,7 +3592,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_fx1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3583,7 +3612,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_axu0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3602,7 +3632,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_rte_axu1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3621,7 +3652,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_valop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3640,7 +3672,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_ord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3659,7 +3692,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_cord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3678,7 +3712,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3697,7 +3732,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_btb_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3716,7 +3752,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_btb_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3735,7 +3772,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_bta_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3754,7 +3792,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(20), .INIT(0)) frn_fdis_iu6_i0_fusion_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -3773,7 +3812,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_spec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3792,7 +3832,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_fp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3811,7 +3852,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_ap_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3830,7 +3872,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_spv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3849,7 +3892,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_type_st_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3868,7 +3912,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_async_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3887,7 +3932,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3906,7 +3952,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_core_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3925,7 +3972,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3944,7 +3992,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isload_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3963,7 +4012,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_isstore_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -3982,7 +4032,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) frn_fdis_iu6_i0_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4001,7 +4052,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4020,7 +4072,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i0_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4039,7 +4092,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_br_pred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4058,7 +4112,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_bh_update_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4077,7 +4132,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh0_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4096,7 +4152,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh1_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4115,7 +4172,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i0_bh2_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4134,7 +4192,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) frn_fdis_iu6_i0_gshare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4153,7 +4212,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_ls_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4172,7 +4232,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4191,7 +4252,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) frn_fdis_iu6_i0_ilat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4209,7 +4271,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4228,7 +4291,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4247,7 +4311,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4266,7 +4331,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4285,7 +4351,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4304,7 +4371,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4323,7 +4391,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4342,7 +4411,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4361,7 +4431,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_t3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4380,7 +4451,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4399,7 +4471,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_t3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4418,7 +4491,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_t3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4437,7 +4511,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4456,7 +4531,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4475,7 +4551,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4494,7 +4571,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4513,7 +4591,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4532,7 +4611,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4551,7 +4631,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4570,7 +4651,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4589,7 +4671,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4608,7 +4691,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4627,7 +4711,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i0_s3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4646,7 +4731,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4665,7 +4751,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4684,7 +4771,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i0_s3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4703,7 +4791,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i0_s3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4722,7 +4811,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4741,7 +4831,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4760,7 +4851,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4779,7 +4871,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) frn_fdis_iu6_i1_ucode_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -4798,7 +4891,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_fuse_nop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4817,7 +4911,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4836,7 +4931,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_sq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4855,7 +4951,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4874,7 +4971,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_fx1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4893,7 +4991,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_axu0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4912,7 +5011,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_rte_axu1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4931,7 +5031,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_valop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4950,7 +5051,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_ord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4969,7 +5071,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_cord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -4988,7 +5091,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5007,7 +5111,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_btb_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5026,7 +5131,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_btb_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5045,7 +5151,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_bta_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5064,7 +5171,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(20), .INIT(0)) frn_fdis_iu6_i1_fusion_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5083,7 +5191,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_spec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5102,7 +5211,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_fp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5121,7 +5231,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_ap_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5140,7 +5251,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_spv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5159,7 +5271,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_type_st_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5178,7 +5291,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_async_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5197,7 +5311,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5216,7 +5331,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_core_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5235,7 +5351,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5254,7 +5371,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isload_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5273,7 +5391,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_isstore_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5292,7 +5411,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) frn_fdis_iu6_i1_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5311,7 +5431,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i1_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5330,7 +5451,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) frn_fdis_iu6_i1_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5349,7 +5471,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_br_pred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5368,7 +5491,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_bh_update_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5387,7 +5511,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh0_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5406,7 +5531,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh1_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5425,7 +5551,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) frn_fdis_iu6_i1_bh2_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5444,7 +5571,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) frn_fdis_iu6_i1_gshare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5463,7 +5591,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_ls_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5482,7 +5611,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5501,7 +5631,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) frn_fdis_iu6_i1_ilat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5519,7 +5650,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5538,7 +5670,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5557,7 +5690,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5576,7 +5710,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5595,7 +5730,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5614,7 +5750,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5633,7 +5770,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5652,7 +5790,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5671,7 +5810,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_t3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5690,7 +5830,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5709,7 +5850,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_t3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5728,7 +5870,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_t3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5747,7 +5890,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5766,7 +5910,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5785,7 +5930,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5804,7 +5950,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5823,7 +5970,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5841,7 +5989,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s1_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5859,7 +6008,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5878,7 +6028,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5897,7 +6048,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5916,7 +6068,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5935,7 +6088,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -5953,7 +6107,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s2_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5971,7 +6126,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -5990,7 +6146,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6009,7 +6166,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6028,7 +6186,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) frn_fdis_iu6_i1_s3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6047,7 +6206,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) frn_fdis_iu6_i1_s3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6065,7 +6225,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) frn_fdis_iu6_i1_s3_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6083,7 +6244,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6102,7 +6264,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6121,7 +6284,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6140,7 +6304,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_ucode_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6159,7 +6324,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6178,7 +6344,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_fuse_nop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6197,7 +6364,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6216,7 +6384,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_sq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6235,7 +6404,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6254,7 +6424,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_fx1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6273,7 +6444,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_axu0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6292,7 +6464,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_rte_axu1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6311,7 +6484,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_valop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6330,7 +6504,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_ord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6349,7 +6524,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_cord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6368,7 +6544,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6387,7 +6564,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_btb_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6406,7 +6584,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_btb_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6425,7 +6604,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_bta_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6444,7 +6624,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(20), .INIT(0)) stall_frn_fdis_iu6_i0_fusion_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6463,7 +6644,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_spec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6482,7 +6664,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_fp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6501,7 +6684,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_ap_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6520,7 +6704,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_spv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6539,7 +6724,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_type_st_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6558,7 +6744,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_async_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6577,7 +6764,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6596,7 +6784,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_core_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6615,7 +6804,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6634,7 +6824,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isload_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6653,7 +6844,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_isstore_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6672,7 +6864,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) stall_frn_fdis_iu6_i0_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6691,7 +6884,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6710,7 +6904,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i0_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6729,7 +6924,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_br_pred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6748,7 +6944,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_bh_update_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6767,7 +6964,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh0_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6786,7 +6984,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh1_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6805,7 +7004,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i0_bh2_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6824,7 +7024,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) stall_frn_fdis_iu6_i0_gshare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6843,7 +7044,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_ls_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6862,7 +7064,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6881,7 +7084,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stall_frn_fdis_iu6_i0_ilat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6899,7 +7103,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6918,7 +7123,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6937,7 +7143,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6956,7 +7163,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -6975,7 +7183,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -6994,7 +7203,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7013,7 +7223,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7032,7 +7243,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7051,7 +7263,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_t3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7070,7 +7283,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7089,7 +7303,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_t3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7108,7 +7323,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_t3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7127,7 +7343,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7146,7 +7363,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7165,7 +7383,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7184,7 +7403,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7203,7 +7423,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7222,7 +7443,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7241,7 +7463,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7260,7 +7483,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7279,7 +7503,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7298,7 +7523,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7317,7 +7543,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i0_s3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7336,7 +7563,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7355,7 +7583,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7374,7 +7603,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i0_s3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7393,7 +7623,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i0_s3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i0_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7412,7 +7643,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7431,7 +7663,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7450,7 +7683,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7469,7 +7703,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_ucode_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7488,7 +7723,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_fuse_nop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7507,7 +7743,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7526,7 +7763,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_sq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7545,7 +7783,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_fx0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7564,7 +7803,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_fx1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7583,7 +7823,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_axu0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7602,7 +7843,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_rte_axu1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7621,7 +7863,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_valop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7640,7 +7883,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_ord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7659,7 +7903,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_cord_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7678,7 +7923,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7697,7 +7943,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_btb_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7716,7 +7963,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_btb_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7735,7 +7983,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_bta_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7754,7 +8003,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(20), .INIT(0)) stall_frn_fdis_iu6_i1_fusion_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -7773,7 +8023,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_spec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7792,7 +8043,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_fp_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7811,7 +8063,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_ap_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7830,7 +8083,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_spv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7849,7 +8103,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_type_st_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7868,7 +8123,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_async_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7887,7 +8143,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7906,7 +8163,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_core_block_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7925,7 +8183,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isram_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7944,7 +8203,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isload_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7963,7 +8223,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_isstore_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -7982,7 +8243,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) stall_frn_fdis_iu6_i1_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8001,7 +8263,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i1_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8020,7 +8283,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) stall_frn_fdis_iu6_i1_bta_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8039,7 +8303,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_br_pred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8058,7 +8323,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_bh_update_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8077,7 +8343,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh0_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8096,7 +8363,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh1_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8115,7 +8383,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_frn_fdis_iu6_i1_bh2_hist_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8134,7 +8403,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) stall_frn_fdis_iu6_i1_gshare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8153,7 +8423,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_ls_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8172,7 +8443,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8191,7 +8463,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stall_frn_fdis_iu6_i1_ilat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8209,7 +8482,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8228,7 +8502,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8247,7 +8522,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8266,7 +8542,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8285,7 +8562,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8304,7 +8582,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8323,7 +8602,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8342,7 +8622,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8361,7 +8642,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_t3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8380,7 +8662,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8399,7 +8682,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_t3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8418,7 +8702,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_t3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8437,7 +8722,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8456,7 +8742,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8475,7 +8762,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8494,7 +8782,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8513,7 +8802,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8531,7 +8821,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s1_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8549,7 +8840,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s2_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8568,7 +8860,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8587,7 +8880,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8606,7 +8900,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8625,7 +8920,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8643,7 +8939,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s2_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8661,7 +8958,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s3_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8680,7 +8978,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8699,7 +8998,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_p_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8718,7 +9018,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) stall_frn_fdis_iu6_i1_s3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8737,7 +9038,8 @@ module iuq_rn( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) stall_frn_fdis_iu6_i1_s3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -8755,7 +9057,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) stall_frn_fdis_iu6_i1_s3_dep_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stall_frn_fdis_iu6_i1_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8776,7 +9079,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8794,7 +9098,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_cpl_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8812,7 +9117,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_gpr_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8830,7 +9136,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_cr_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8848,7 +9155,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_lr_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8866,7 +9174,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_ctr_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8884,7 +9193,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_xer_credit_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8902,7 +9212,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_br_hold_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8920,7 +9231,8 @@ module iuq_rn( tri_rlmlatch_p #(.INIT(0)) perf_iu5_axu_hold_stall_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_iu_event_bus_enable), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -8943,7 +9255,8 @@ module iuq_rn( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) @@ -8953,7 +9266,8 @@ module iuq_rn( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_rn_map.v b/dev/verilog/work/iuq_rn_map.v index 30e067d..b6c9556 100755 --- a/dev/verilog/work/iuq_rn_map.v +++ b/dev/verilog/work/iuq_rn_map.v @@ -46,7 +46,8 @@ module iuq_rn_map #( ( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_0_b, // acts as reset for non-ibm types input pc_iu_sg_0, input force_t, @@ -451,7 +452,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) comp_map_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(comp_map_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -478,7 +480,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(i)) spec_map_arc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spec_map_arc_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -497,7 +500,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(i)) spec_map_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spec_map_itag_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -524,7 +528,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT((i + ARCHITECTED_REGISTER_DEPTH))) buffer_pool_latch0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(buffer_pool_act[i]), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -546,7 +551,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) read_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(read_ptr_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -565,7 +571,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) write_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(write_ptr_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -584,7 +591,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH)) free_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(free_cnt_act), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -603,7 +611,8 @@ module iuq_rn_map #( tri_rlmlatch_p #(.INIT(0)) pool_free_0_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -622,7 +631,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), @@ -641,7 +651,8 @@ module iuq_rn_map #( tri_rlmlatch_p #(.INIT(0)) pool_free_1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -660,7 +671,8 @@ module iuq_rn_map #( tri_rlmreg_p #(.WIDTH(STORAGE_WIDTH), .INIT(0)) pool_free_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(force_t), .thold_b(pc_iu_func_sl_thold_0_b), diff --git a/dev/verilog/work/iuq_rn_top.v b/dev/verilog/work/iuq_rn_top.v index 4ca0ab6..69c152c 100755 --- a/dev/verilog/work/iuq_rn_top.v +++ b/dev/verilog/work/iuq_rn_top.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -42,7 +42,8 @@ module iuq_rn_top( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types input pc_iu_sg_2, input clkoff_b, @@ -435,7 +436,8 @@ module iuq_rn_top( iuq_rn fx_rn0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .clkoff_b(clkoff_b), @@ -831,7 +833,8 @@ module iuq_rn_top( iuq_axu_fu_rn #(.FPR_POOL(`GPR_POOL), .FPR_UCODE_POOL(4), .FPSCR_POOL_ENC(5)) axu_rn0( .vdd(vdd), // inout power_logic; .gnd(gnd), // inout power_logic; - .nclk(nclk), // in clk_logic; + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), // in std_ulogic; acts as reset for non-ibm types .pc_iu_sg_2(pc_iu_sg_2), // in std_ulogic; .clkoff_b(clkoff_b), // in std_ulogic; todo diff --git a/dev/verilog/work/iuq_slice.v b/dev/verilog/work/iuq_slice.v index 5ed5f69..07b5d34 100755 --- a/dev/verilog/work/iuq_slice.v +++ b/dev/verilog/work/iuq_slice.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -42,7 +42,8 @@ module iuq_slice( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input clkoff_b, @@ -469,7 +470,8 @@ module iuq_slice( iuq_ibuf iuq_ibuf0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -531,7 +533,8 @@ module iuq_slice( iuq_dec_top dec_top0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -709,7 +712,8 @@ module iuq_slice( iuq_rn_top rn_top0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), .clkoff_b(clkoff_b), diff --git a/dev/verilog/work/iuq_slice_top.v b/dev/verilog/work/iuq_slice_top.v index bf7c958..110c94b 100755 --- a/dev/verilog/work/iuq_slice_top.v +++ b/dev/verilog/work/iuq_slice_top.v @@ -38,8 +38,8 @@ module iuq_slice_top( - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input pc_iu_func_slp_sl_thold_2, @@ -959,7 +959,8 @@ module iuq_slice_top( iuq_slice slice0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -1242,7 +1243,8 @@ module iuq_slice_top( iuq_slice slice1( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_sg_2(pc_iu_sg_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .clkoff_b(clkoff_b), @@ -1525,7 +1527,8 @@ module iuq_slice_top( iuq_dispatch dispatch( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), .pc_iu_sg_2(pc_iu_sg_2), diff --git a/dev/verilog/work/iuq_spr.v b/dev/verilog/work/iuq_spr.v index 26a810f..e100a6a 100755 --- a/dev/verilog/work/iuq_spr.v +++ b/dev/verilog/work/iuq_spr.v @@ -163,8 +163,8 @@ module iuq_spr( output [0:31] spr_cp_perf_event_mux_ctrls, //pervasive - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_iu_sg_2, input pc_iu_func_sl_thold_2, input clkoff_b, @@ -489,7 +489,8 @@ module iuq_spr( tri_rlmlatch_p #(.INIT(0)) slowspr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -507,7 +508,8 @@ module iuq_spr( tri_rlmlatch_p #(.INIT(0)) slowspr_rw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -525,7 +527,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) slowspr_etid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -543,7 +546,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) slowspr_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -561,7 +565,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0)) slowspr_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -579,7 +584,8 @@ module iuq_spr( tri_rlmlatch_p #(.INIT(0)) slowspr_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -597,7 +603,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0)) ivpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ivpr_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -615,7 +622,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`GPR_WIDTH-12), .INIT(0)) givpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(givpr_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -633,7 +641,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(16), .INIT(65535)) immr0a_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(immr0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -651,7 +660,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(16), .INIT(65535)) immr0b_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(immr0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -669,7 +679,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) imr0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(imr0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -689,7 +700,8 @@ module iuq_spr( // generic map (width => iucr0_l2'length, init => 249, `EXPAND_TYPE => `EXPAND_TYPE) .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iucr0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -714,7 +726,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) eheir_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(eheir_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -733,7 +746,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(14), .INIT(4096)) iucr1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iucr1_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -752,7 +766,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) iucr2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iucr2_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -771,7 +786,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(3), .INIT(3)) ppr32_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ppr32_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -791,7 +807,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(168431114)) cpcr2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr2_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -810,7 +827,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(655392)) cpcr3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr3_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -829,7 +847,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(101058566)) cpcr4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr4_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -848,7 +867,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(393232)) cpcr5_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr5_wren[i]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -869,7 +889,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cpcr_we_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -888,7 +909,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(`INIT_CPCR0)) cpcr0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -907,7 +929,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(32), .INIT(`INIT_CPCR1)) cpcr1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cpcr1_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -926,7 +949,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iac1_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -945,7 +969,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iac2_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -964,7 +989,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iac3_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -983,7 +1009,8 @@ module iuq_spr( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) iac4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iac4_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1001,7 +1028,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(32), .INIT(26)) iulfsr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iulfsr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1019,7 +1047,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(9), .INIT(0)) iudbg0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iudbg0_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1037,7 +1066,8 @@ module iuq_spr( tri_rlmlatch_p #(.INIT(0)) iudbg0_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iudbg0_done_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1055,7 +1085,8 @@ module iuq_spr( tri_rlmlatch_p #(.INIT(0)) iudbg0_exec_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iudbg0_exec_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1073,7 +1104,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(11), .INIT(0)) iudbg1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iudbg1_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1091,7 +1123,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(29), .INIT(0)) iudbg2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iudbg2_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1110,7 +1143,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(18), .INIT(131136)) iullcr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iullcr_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1128,7 +1162,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1146,7 +1181,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1164,7 +1200,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_pr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1182,7 +1219,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(3), .INIT(0)) xu_iu_pri_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1200,7 +1238,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_pri_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1218,7 +1257,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) iesr3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iesr3_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1236,7 +1276,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0)) iesr1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iesr1_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1254,7 +1295,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0)) iesr2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iesr2_wren), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1272,7 +1314,8 @@ module iuq_spr( tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) raise_iss_pri_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1714,7 +1757,8 @@ module iuq_spr( tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2}), .q({pc_iu_func_sl_thold_1, pc_iu_sg_1}) @@ -1723,7 +1767,8 @@ module iuq_spr( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1}), .q({pc_iu_func_sl_thold_0, pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_uc.v b/dev/verilog/work/iuq_uc.v index 6813b3e..72dfa5f 100755 --- a/dev/verilog/work/iuq_uc.v +++ b/dev/verilog/work/iuq_uc.v @@ -42,7 +42,8 @@ module iuq_uc( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_2, pc_iu_sg_2, tc_ac_ccflush_dc, @@ -95,11 +96,9 @@ module iuq_uc( inout vdd; - inout gnd; - - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_2; input pc_iu_sg_2; input tc_ac_ccflush_dc; @@ -357,7 +356,8 @@ module iuq_uc( iuq_uc_buffer iuq_uc_buffer0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -1360,7 +1360,8 @@ assign uc_legal = iuq_uc_control uc_control( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -1429,7 +1430,8 @@ assign uc_legal = iuq_uc_rom_even uc_rom_even( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -1448,7 +1450,8 @@ assign uc_legal = iuq_uc_rom_odd uc_rom_odd( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -1564,7 +1567,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) iu3_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1582,7 +1586,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ic_bp_iu2_val[0]), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1600,7 +1605,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu3_2ucode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1618,7 +1624,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu3_2ucode_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1636,7 +1643,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(34 * 4), .INIT(0), .NEEDS_SRESET(0)) iu3_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ic_bp_iu2_val[0]), // ??? Could create act for 0:31 when buffers full? .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1654,7 +1662,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu_pc_err_ucode_illegal_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1672,7 +1681,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1690,7 +1700,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1708,7 +1719,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) flush_into_uc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1726,7 +1738,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cp_flush_into_uc), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1744,7 +1757,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(19), .INIT(0), .NEEDS_SRESET(0)) flush_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cp_flush_into_uc), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1762,7 +1776,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1780,7 +1795,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_iu_redirect_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1798,7 +1814,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) advance_buffers_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1817,7 +1834,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) romvalid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1835,7 +1853,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) rom_data_even_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1853,7 +1872,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) rom_data_odd_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1872,7 +1892,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1890,7 +1911,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(uc_ifar), .INIT(0), .NEEDS_SRESET(0)) iu4_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1908,7 +1930,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ext0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1926,7 +1949,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ext1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1944,7 +1968,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu4_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1963,7 +1988,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu4_ov_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1981,7 +2007,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(uc_ifar), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1999,7 +2026,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_instr0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2017,7 +2045,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_instr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2035,7 +2064,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) u4_ov_ext0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2053,7 +2083,8 @@ assign uc_legal = tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu4_ov_ext1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2071,7 +2102,8 @@ assign uc_legal = tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) iu4_ov_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu4_ov_stage_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -2093,7 +2125,8 @@ assign uc_legal = tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2}), .q( {pc_iu_func_sl_thold_1, pc_iu_sg_1}) @@ -2102,7 +2135,8 @@ assign uc_legal = tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1}), .q( {pc_iu_func_sl_thold_0, pc_iu_sg_0}) diff --git a/dev/verilog/work/iuq_uc_buffer.v b/dev/verilog/work/iuq_uc_buffer.v index a7778e0..4b5de06 100755 --- a/dev/verilog/work/iuq_uc_buffer.v +++ b/dev/verilog/work/iuq_uc_buffer.v @@ -42,7 +42,8 @@ module iuq_uc_buffer( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -83,12 +84,10 @@ module iuq_uc_buffer( inout vdd; - inout gnd; - - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -468,7 +467,8 @@ module iuq_uc_buffer( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_ic_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -487,7 +487,8 @@ module iuq_uc_buffer( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) uc_iu4_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -506,7 +507,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) uc_iu4_flush_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_iu4_flush_d), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -525,7 +527,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) buffer_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -543,7 +546,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -562,7 +566,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -581,7 +586,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -600,7 +606,8 @@ module iuq_uc_buffer( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) buffer4_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_buffer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_uc_control.v b/dev/verilog/work/iuq_uc_control.v index eaeee51..73363b3 100755 --- a/dev/verilog/work/iuq_uc_control.v +++ b/dev/verilog/work/iuq_uc_control.v @@ -38,11 +38,11 @@ `include "tri_a2o.vh" - module iuq_uc_control( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -94,11 +94,10 @@ module iuq_uc_control( inout vdd; - inout gnd; - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -776,7 +775,8 @@ module iuq_uc_control( iuq_uc_cplbuffer iuq_uc_cplbuffer0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_sg_0(pc_iu_sg_0), .force_t(force_t), @@ -811,7 +811,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) xu_iu_ucode_xer_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xer_act), // ??? If change, make sure xer bugspray is still accurate .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -829,7 +830,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) xu_iu_ucode_xer_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -847,7 +849,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) wait_for_xer_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -865,7 +868,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) xer_val_occurred_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -883,7 +887,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_default_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -901,7 +906,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -919,7 +925,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_even_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -937,7 +944,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) instr_odd_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -955,7 +963,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(0)) sel_even_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -973,7 +982,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) sel_odd_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -991,7 +1001,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) early_end_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1009,7 +1020,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cond_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1027,7 +1039,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1045,7 +1058,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) flush_to_odd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1063,7 +1077,8 @@ module iuq_uc_control( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) count_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1081,7 +1096,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inloop_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1099,7 +1115,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) skip_zero_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1117,7 +1134,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) skip_to_np1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1135,7 +1153,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) force_ep_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1153,7 +1172,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fxm_type_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(uc_control_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1171,7 +1191,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ep_force_even_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -1189,7 +1210,8 @@ module iuq_uc_control( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ep_force_odd_late_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(data_valid), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_uc_cplbuffer.v b/dev/verilog/work/iuq_uc_cplbuffer.v index 5b13870..a9e08ac 100755 --- a/dev/verilog/work/iuq_uc_cplbuffer.v +++ b/dev/verilog/work/iuq_uc_cplbuffer.v @@ -42,7 +42,8 @@ module iuq_uc_cplbuffer( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -70,11 +71,10 @@ module iuq_uc_cplbuffer( inout vdd; - inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -222,7 +222,8 @@ module iuq_uc_cplbuffer( tri_rlmreg_p #(.WIDTH(buffer_depth_log+1), .INIT(0)) buffer_count_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ptr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -245,7 +246,8 @@ module iuq_uc_cplbuffer( tri_rlmreg_p #(.WIDTH(buffer_width), .INIT(0)) buffer_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(buffer_act[i/(buffer_depth/2)]), // only clock half of buffers at a time .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -263,7 +265,8 @@ module iuq_uc_cplbuffer( tri_rlmreg_p #(.WIDTH(xer_width), .INIT(0)) xer_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cplbuffer_xer_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -284,7 +287,8 @@ module iuq_uc_cplbuffer( tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) read_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ptr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -302,7 +306,8 @@ module iuq_uc_cplbuffer( tri_rlmreg_p #(.WIDTH(buffer_depth_log), .INIT(0)) write_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ptr_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), @@ -320,7 +325,8 @@ module iuq_uc_cplbuffer( tri_rlmlatch_p #(.INIT(0)) new_command_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_uc_rom_even.v b/dev/verilog/work/iuq_uc_rom_even.v index 324d7ea..2ae2469 100755 --- a/dev/verilog/work/iuq_uc_rom_even.v +++ b/dev/verilog/work/iuq_uc_rom_even.v @@ -42,7 +42,8 @@ module iuq_uc_rom_even( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -60,11 +61,10 @@ module iuq_uc_rom_even( inout vdd; - inout gnd; + input clk; + input rst; - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -2207,7 +2207,8 @@ assign ep = tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rom_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/iuq_uc_rom_odd.v b/dev/verilog/work/iuq_uc_rom_odd.v index 6eb1fab..01cf99e 100755 --- a/dev/verilog/work/iuq_uc_rom_odd.v +++ b/dev/verilog/work/iuq_uc_rom_odd.v @@ -42,7 +42,8 @@ module iuq_uc_rom_odd( vdd, gnd, - nclk, + clk, + rst, pc_iu_func_sl_thold_0_b, pc_iu_sg_0, force_t, @@ -60,11 +61,9 @@ module iuq_uc_rom_odd( inout vdd; - inout gnd; - - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_iu_func_sl_thold_0_b; input pc_iu_sg_0; input force_t; @@ -2015,7 +2014,8 @@ assign ep = tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) rom_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rom_act), .thold_b(pc_iu_func_sl_thold_0_b), .sg(pc_iu_sg_0), diff --git a/dev/verilog/work/lq.v b/dev/verilog/work/lq.v index 8ed07c5..d74964f 100755 --- a/dev/verilog/work/lq.v +++ b/dev/verilog/work/lq.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -407,7 +407,8 @@ module lq( // vcs, // vdd, // gnd, - nclk, + clk, + rst, pc_lq_init_reset, pc_lq_ccflush_dc, pc_lq_gptr_sl_thold_3, @@ -969,9 +970,8 @@ output ac_an_req_endian; output ac_an_st_data_pwr_token; // Pervasive - -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; // Thold inputs input pc_lq_init_reset; @@ -1865,7 +1865,8 @@ lq_ctl #(.XU0_PIPE_START(XU0_PIPE_START), .XU0_PIPE_END(XU0_PIPE_END), .XU1_PIPE .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_2(sg_2), .fce_2(fce_2), .func_sl_thold_2(func_sl_thold_2), @@ -1955,6 +1956,8 @@ lq_ctl #(.XU0_PIPE_START(XU0_PIPE_START), .XU0_PIPE_END(XU0_PIPE_END), .XU1_PIPE // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX lq_data dat( + .clk(clk), + .rst(rst), // Execution Pipe .ctl_dat_ex1_data_act(ctl_dat_ex1_data_act), @@ -2006,7 +2009,6 @@ lq_data dat( .vdd(vdd), .gnd(gnd), .vcs(vdd), - .nclk(nclk), .pc_lq_ccflush_dc(pc_lq_ccflush_dc), .sg_2(sg_2), .fce_2(fce_2), @@ -2493,7 +2495,8 @@ lq_lsq lsq( .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_lq_ccflush_dc(pc_lq_ccflush_dc), .sg_2(sg_2), .fce_2(fce_2), @@ -2560,7 +2563,8 @@ assign lq_debug_bus0 = 32'h00000000; lq_perv lq_perv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_lq_trace_bus_enable(pc_lq_trace_bus_enable), .pc_lq_debug_mux1_ctrls(pc_lq_debug_mux1_ctrls), .pc_lq_debug_mux2_ctrls(pc_lq_debug_mux2_ctrls), diff --git a/dev/verilog/work/lq_arb.v b/dev/verilog/work/lq_arb.v index 3954926..7924923 100755 --- a/dev/verilog/work/lq_arb.v +++ b/dev/verilog/work/lq_arb.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -154,7 +154,8 @@ module lq_arb( lq_pc_err_l2credit_overrun, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -303,13 +304,10 @@ module lq_arb( inout vdd; - - inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -871,7 +869,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) req_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -890,7 +889,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) req_l2_ld_sent_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -909,7 +909,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) req_sel_usrDef_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -928,7 +929,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) req_sel_byteEn_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -947,7 +949,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) req_sel_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -966,7 +969,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) req_sel_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -985,7 +989,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) req_sel_ttype_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1004,7 +1009,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) req_sel_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1023,7 +1029,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) req_sel_opSize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1042,7 +1049,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) req_sel_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1061,7 +1069,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) unit_last_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1080,7 +1089,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(5), .INIT(`LOAD_CREDITS), .NEEDS_SRESET(1)) load_cred_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1099,7 +1109,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_cred_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1117,7 +1128,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_st_noCred_flp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1135,7 +1147,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) st_rej_hold_cred_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1153,7 +1166,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_noCred_hold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1171,7 +1185,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ld_pop_rcvd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1189,7 +1204,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ld_cred_blk_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1207,7 +1223,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(6), .INIT(`STORE_CREDITS), .NEEDS_SRESET(1)) store_cred_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1226,7 +1243,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) st_cred_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1245,7 +1263,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_b2b_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1263,7 +1282,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cred_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1281,7 +1301,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1299,7 +1320,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_req_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1318,7 +1340,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmq2_req_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1337,7 +1360,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmq3_req_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1356,7 +1380,8 @@ module lq_arb( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_data_override_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1375,7 +1400,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(27), .INIT(0), .NEEDS_SRESET(1)) stq4_req_st_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(req_l2_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1394,7 +1420,8 @@ module lq_arb( tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq2_store_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_byp.v b/dev/verilog/work/lq_byp.v index ba097f5..63fe97e 100755 --- a/dev/verilog/work/lq_byp.v +++ b/dev/verilog/work/lq_byp.v @@ -37,7 +37,8 @@ module lq_byp( - nclk, + clk, + rst, vdd, gnd, d_mode_dc, @@ -142,14 +143,10 @@ module lq_byp( inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; - +input clk; +input rst; //------------------------------------------------------------------- // Pervasive //------------------------------------------------------------------- @@ -942,7 +939,8 @@ assign byp_dec_ex1_s2_abort = ex1_s2_abort; //---------------------------------------------------------------------------------------------------------------------------------------- tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex1_stg_act), @@ -959,7 +957,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs1_la .dout(ex2_rs1_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex1_stg_act), @@ -976,7 +975,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_rs2_la .dout(ex2_rs2_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s1_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -993,7 +993,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s1_abort_latch( .dout(ex2_s1_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s2_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1010,7 +1011,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_s2_abort_latch( .dout(ex2_s2_abort_q)); tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu0_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1027,7 +1029,8 @@ tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu0_sel_latch( .dout(ex1_s1_xu0_sel_q)); tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu0_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1044,7 +1047,8 @@ tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu0_sel_latch( .dout(ex1_s2_xu0_sel_q)); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu1_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1061,7 +1065,8 @@ tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_xu1_sel_latch( .dout(ex1_s1_xu1_sel_q)); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu1_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1078,7 +1083,8 @@ tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_xu1_sel_latch( .dout(ex1_s2_xu1_sel_q)); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_lq_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1095,7 +1101,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_lq_sel_latch( .dout(ex1_s1_lq_sel_q)); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_lq_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1112,7 +1119,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_lq_sel_latch( .dout(ex1_s2_lq_sel_q)); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_rel_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1129,7 +1137,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s1_rel_sel_latch( .dout(ex1_s1_rel_sel_q)); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_rel_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex0_stg_act), @@ -1146,7 +1155,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_s2_rel_sel_latch( .dout(ex1_s2_rel_sel_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu0_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_xu0_stg_act_q), @@ -1163,7 +1173,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu0_rt .dout(ex5_xu0_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_xu0_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_xu0_stg_act_q), @@ -1180,7 +1191,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_xu0_rt .dout(ex6_xu0_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_xu0_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex6_xu0_stg_act), @@ -1197,7 +1209,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_xu0_rt .dout(ex7_xu0_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_xu0_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex7_xu0_stg_act_q), @@ -1214,7 +1227,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_xu0_rt .dout(ex8_xu0_rt_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1231,7 +1245,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_req_abort_latch( .dout(ex4_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1248,7 +1263,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_req_abort_latch( .dout(ex5_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1265,7 +1281,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_req_abort_latch( .dout(ex6_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1282,7 +1299,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_req_abort_latch( .dout(ex7_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1299,7 +1317,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu0_req_abort_latch( .dout(ex8_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1316,7 +1335,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_xu0_req_abort_latch( .dout(ex9_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex10_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1333,7 +1353,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex10_xu0_req_abort_latch( .dout(ex10_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex11_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1350,7 +1371,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex11_xu0_req_abort_latch( .dout(ex11_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex12_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1367,7 +1389,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex12_xu0_req_abort_latch( .dout(ex12_xu0_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex13_xu0_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1384,7 +1407,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex13_xu0_req_abort_latch( .dout(ex13_xu0_req_abort_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_xu1_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_xu1_stg_act), @@ -1401,7 +1425,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_xu1_rt .dout(ex4_xu1_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu1_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_xu1_stg_act_q), @@ -1418,7 +1443,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_xu1_rt .dout(ex5_xu1_rt_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1435,7 +1461,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_req_abort_latch( .dout(ex4_xu1_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu1_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1452,7 +1479,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu1_req_abort_latch( .dout(ex5_xu1_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu1_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1469,7 +1497,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu1_req_abort_latch( .dout(ex6_xu1_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu1_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1486,7 +1515,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu1_req_abort_latch( .dout(ex7_xu1_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu1_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1503,7 +1533,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_xu1_req_abort_latch( .dout(ex8_xu1_req_abort_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel3_rel_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dcc_byp_rel2_stg_act), @@ -1520,7 +1551,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel3_rel_r .dout(rel3_rel_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel4_rel_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dcc_byp_rel3_stg_act), @@ -1537,7 +1569,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) rel4_rel_r .dout(rel4_rel_rt_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_fx_ld_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex5_stg_act), @@ -1554,7 +1587,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_fx_ld_ .dout(ex6_fx_ld_data_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_fx_ld_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex6_stg_act), @@ -1571,7 +1605,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex7_fx_ld_ .dout(ex7_fx_ld_data_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_fx_ld_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex7_stg_act), @@ -1588,7 +1623,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex8_fx_ld_ .dout(ex8_fx_ld_data_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_aborted_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1605,7 +1641,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_aborted_latch( .dout(ex3_req_aborted_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_aborted_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1622,7 +1659,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_aborted_latch( .dout(ex4_req_aborted_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_aborted_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1639,7 +1677,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_aborted_latch( .dout(ex5_req_aborted_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1656,7 +1695,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_req_abort_latch( .dout(ex6_lq_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_lq_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1673,7 +1713,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_lq_req_abort_latch( .dout(ex7_lq_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_lq_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1690,7 +1731,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex8_lq_req_abort_latch( .dout(ex8_lq_req_abort_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_lq_req_abort_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1707,7 +1749,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex9_lq_req_abort_latch( .dout(ex9_lq_req_abort_q)); tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)+(2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_gpr_wd0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex5_stg_act), @@ -1724,7 +1767,8 @@ tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)+(2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEE .dout(ex6_gpr_wd0_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_move_data_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1741,7 +1785,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_move_data_sel_latch( .dout(ex5_move_data_sel_q)); tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex5_mv_rel_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_move_data_sel), @@ -1758,7 +1803,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex5_mv_rel_da .dout(ex5_mv_rel_data_q)); tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc1_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex5_stg_act), @@ -1775,7 +1821,8 @@ tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dv .dout(ex6_dvc1_cmp_q)); tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc2_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_byp_ex5_stg_act), @@ -1792,7 +1839,8 @@ tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) ex6_dv .dout(ex6_dvc2_cmp_q)); tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dcc_byp_ram_act), @@ -1813,7 +1861,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_ //------------------------------------ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1830,7 +1879,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_stg_act_latch( .dout(ex4_xu0_stg_act_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1847,7 +1897,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_stg_act_latch( .dout(ex5_xu0_stg_act_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1864,7 +1915,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_stg_act_latch( .dout(ex6_xu0_stg_act_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1881,7 +1933,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_stg_act_latch( .dout(ex7_xu0_stg_act_q)); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), diff --git a/dev/verilog/work/lq_ctl.v b/dev/verilog/work/lq_ctl.v index f786126..d9c7dd3 100755 --- a/dev/verilog/work/lq_ctl.v +++ b/dev/verilog/work/lq_ctl.v @@ -438,7 +438,8 @@ module lq_ctl( vcs, vdd, gnd, - nclk, + clk, + rst, sg_2, fce_2, func_sl_thold_2, @@ -1032,16 +1033,11 @@ output lq_pc_err_prefetche inout vcs; - - inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_2; input fce_2; input func_sl_thold_2; @@ -1624,7 +1620,8 @@ lq_dec dec( //-------------------------------------------------------------- // Clocks & Power //-------------------------------------------------------------- - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), @@ -1874,7 +1871,8 @@ lq_byp byp( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), @@ -2536,7 +2534,8 @@ lq_dcc #(.PARBITS(PARBITS)) dcc( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2559,7 +2558,8 @@ lq_dcc #(.PARBITS(PARBITS)) dcc( // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX lq_spr spr( - .nclk(nclk), + .clk(clk), + .rst(rst), .d_mode_dc(d_mode_dc), .delay_lclkr_dc(delay_lclkr_dc[5]), @@ -2860,7 +2860,8 @@ lq_dir #(.WAYDATASIZE(WAYDATASIZE), .PARBITS(PARBITS)) dir( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2897,7 +2898,8 @@ generate .gnd(gnd), // CLOCK AND CLOCKCONTROL PORTS - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(dec_dir_ex2_dir_rd_act), .wr_act(tiup), .sg_0(sg_0), @@ -2987,7 +2989,8 @@ lq_derat derat( .vcs(vdd), // CLOCK and CLOCK CONTROL ports - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_xu_init_reset(pc_lq_init_reset), .pc_xu_ccflush_dc(pc_lq_ccflush_dc), .tc_scan_dis_dc_b(an_ac_scan_dis_dc_b), @@ -3264,7 +3267,8 @@ generate .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -3374,7 +3378,8 @@ assign ccfg_scan_out = ccfg_scan_out_int & an_ac_scan_dis_dc_b; tri_rlmreg_p #(.INIT(0), .WIDTH(25), .NEEDS_SRESET(1)) abist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_abist_ena_dc), .thold_b(abst_sl_thold_0_b), .sg(sg_0), @@ -3412,7 +3417,8 @@ tri_rlmreg_p #(.INIT(0), .WIDTH(25), .NEEDS_SRESET(1)) abist_reg( tri_plat #(.WIDTH(15)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_2, func_sl_thold_2, @@ -3449,7 +3455,8 @@ tri_plat #(.WIDTH(15)) perv_2to1_reg( tri_plat #(.WIDTH(15)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_1, func_sl_thold_1, @@ -3556,7 +3563,8 @@ tri_lcbs perv_lcbs_abst( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc[5]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(abst_slat_thold_b), .dclk(abst_slat_d2clk), @@ -3584,7 +3592,8 @@ tri_lcbs perv_lcbs_time( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc[5]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(time_slat_thold_b), .dclk(time_slat_d2clk), @@ -3613,7 +3622,8 @@ tri_lcbs perv_lcbs_repr( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc[5]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(repr_slat_thold_b), .dclk(repr_slat_d2clk), @@ -3640,7 +3650,8 @@ tri_lcbs perv_lcbs_func( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc[5]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(func_slat_thold_b), .dclk(func_slat_d2clk), @@ -3704,7 +3715,8 @@ tri_lcbs perv_lcbs_regf( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc[5]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(regf_slat_thold_b), .dclk(regf_slat_d2clk), diff --git a/dev/verilog/work/lq_data.v b/dev/verilog/work/lq_data.v index ad91d56..39c5baa 100755 --- a/dev/verilog/work/lq_data.v +++ b/dev/verilog/work/lq_data.v @@ -77,7 +77,8 @@ module lq_data( vdd, gnd, vcs, - nclk, + clk, + rst, pc_lq_ccflush_dc, sg_2, fce_2, @@ -188,7 +189,8 @@ inout vcs; inout vdd; inout gnd; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input pc_lq_ccflush_dc; input sg_2; input fce_2; @@ -493,7 +495,8 @@ lq_data_st l1dcst( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -527,7 +530,8 @@ generate if ((2 ** `DC_SIZE) == 32768) begin : dc32K .gnd(gnd), // CLOCK AND CLOCKCONTROL PORTS - .nclk(nclk), + .clk(clk), + .rst(rst), .wr_act(dcarr_wr_stg_act), .rd_act(dcarr_rd_stg_act), .sg_0(sg_0), @@ -656,7 +660,8 @@ lq_data_ld l1dcld( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -697,7 +702,8 @@ assign func_scan_out = func_scan_out_q & {7{an_ac_scan_dis_dc_b}}; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dcache_parity_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -716,7 +722,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dcache_parity_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -734,7 +741,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( tri_regk #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq5_rot_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -753,7 +761,8 @@ tri_regk #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq5_rot_data_reg tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq6_rot_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -775,7 +784,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq6_rot_data tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -794,7 +804,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -813,7 +824,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -832,7 +844,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -851,7 +864,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -870,7 +884,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -889,7 +904,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -910,7 +926,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_reg( tri_rlmreg_p #(.INIT(0), .WIDTH(29), .NEEDS_SRESET(1)) abist0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_abist_ena_dc), .thold_b(abst_sl_thold_0_b), .sg(sg_0), @@ -948,7 +965,8 @@ tri_rlmreg_p #(.INIT(0), .WIDTH(29), .NEEDS_SRESET(1)) abist0_reg( tri_plat #(.WIDTH(9)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_2, func_sl_thold_2, @@ -974,7 +992,8 @@ tri_plat #(.WIDTH(9)) perv_2to1_reg( tri_plat #(.WIDTH(9)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_1, func_sl_thold_1, @@ -1038,7 +1057,8 @@ tri_lcbs perv_lcbs_abst( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(abst_slat_thold_b), .dclk(abst_slat_d2clk), @@ -1062,7 +1082,8 @@ tri_lcbs perv_lcbs_time( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(time_slat_thold_b), .dclk(time_slat_d2clk), @@ -1086,7 +1107,8 @@ tri_lcbs perv_lcbs_repr( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(repr_slat_thold_b), .dclk(repr_slat_d2clk), @@ -1110,7 +1132,8 @@ tri_lcbs perv_lcbs_func( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(func_slat_thold_b), .dclk(func_slat_d2clk), diff --git a/dev/verilog/work/lq_data_ld.v b/dev/verilog/work/lq_data_ld.v index 4951734..10e9fda 100755 --- a/dev/verilog/work/lq_data_ld.v +++ b/dev/verilog/work/lq_data_ld.v @@ -76,7 +76,8 @@ module lq_data_ld( stq6_rd_data_wh, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -146,7 +147,8 @@ output [0:143] stq6_rd_data_wh; inout vdd; inout gnd; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -341,7 +343,8 @@ generate begin : l1dcrotrWA .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -370,7 +373,8 @@ generate begin : l1dcrotrWA .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -414,7 +418,8 @@ generate begin : l1dcrotrWB .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -443,7 +448,8 @@ generate begin : l1dcrotrWB .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -487,7 +493,8 @@ generate begin : l1dcrotrWC .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -516,7 +523,8 @@ generate begin : l1dcrotrWC .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -560,7 +568,8 @@ generate begin : l1dcrotrWD .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -589,7 +598,8 @@ generate begin : l1dcrotrWD .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -633,7 +643,8 @@ generate begin : l1dcrotrWE .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -662,7 +673,8 @@ generate begin : l1dcrotrWE .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -706,7 +718,8 @@ generate begin : l1dcrotrWF .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -735,7 +748,8 @@ generate begin : l1dcrotrWF .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -779,7 +793,8 @@ generate begin : l1dcrotrWG .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -808,7 +823,8 @@ generate begin : l1dcrotrWG .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -852,7 +868,8 @@ generate begin : l1dcrotrWH .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -881,7 +898,8 @@ generate begin : l1dcrotrWH .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .func_sl_force(func_sl_force), .delay_lclkr_dc(delay_lclkr_dc), @@ -1126,7 +1144,8 @@ assign stq6_rd_data_wh = {dcarr_rd_data_wh, dcarr_rd_parity_wh}; tri_regk #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex5_ld_hit_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_data_st.v b/dev/verilog/work/lq_data_st.v index f00c69f..1b4bf4e 100755 --- a/dev/verilog/work/lq_data_st.v +++ b/dev/verilog/work/lq_data_st.v @@ -87,7 +87,8 @@ module lq_data_st( dcarr_wr_data_wefgh, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -172,7 +173,8 @@ output [0:143] dcarr_wr_data_wefgh; // D$ Array Write Data for inout vdd; inout gnd; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -548,7 +550,8 @@ tri_lq_rmw rmw( .dcarr_wr_addr(dcarr_wr_addr), .dcarr_wr_data_wabcd(dcarr_wr_data_wabcd), .dcarr_wr_data_wefgh(dcarr_wr_data_wefgh), - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -624,7 +627,8 @@ assign stq4_rot_data = stq4_rot_data_q; tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_opsize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -642,7 +646,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_opsize_reg( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq3_opsize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -660,7 +665,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq3_opsize_reg( tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq4_rot_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -678,7 +684,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stq4_rot_data tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_le_mode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -696,7 +703,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_le_mode_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -714,7 +722,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -732,7 +741,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -750,7 +760,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -768,7 +779,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_arr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -786,7 +798,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_arr_wren_reg( tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq5_arr_way_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -804,7 +817,8 @@ tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq5_arr_way_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_blk_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -822,7 +836,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_blk_req_reg( tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq3_rot_sel1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -840,7 +855,8 @@ tri_regk #(.WIDTH(8), .INIT(170), .NEEDS_SRESET(1)) stq3_rot_sel1_reg( tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -858,7 +874,8 @@ tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel2_reg( tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -876,7 +893,8 @@ tri_regk #(.WIDTH(8), .INIT(136), .NEEDS_SRESET(1)) stq3_rot_sel3_reg( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_rot_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -894,7 +912,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stq2_rot_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq2_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -912,7 +931,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq2_addr_reg( tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq3_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -930,7 +950,8 @@ tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq3_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq4_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -948,7 +969,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq4_addr_reg( tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq5_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -966,7 +988,8 @@ tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq5_addr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_data_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -984,7 +1007,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_data_val_reg( tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1002,7 +1026,8 @@ tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_data_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_par_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1020,7 +1045,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_par_reg( tri_regk #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq5_dcarr_wrt_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -1038,7 +1064,8 @@ tri_regk #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq5_dcarr_wrt_data_reg( tri_regk #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -1056,7 +1083,8 @@ tri_regk #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_data_reg( tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_par_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -1074,7 +1102,8 @@ tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_store_rel_par_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq2_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1092,7 +1121,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq2_byte_en_reg( tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -1110,7 +1140,8 @@ tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq3_byte_en_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1128,7 +1159,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq4_byte_en_reg( tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq5_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -1149,7 +1181,8 @@ tri_regk #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq5_byte_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1168,7 +1201,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1186,7 +1220,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1204,7 +1239,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), diff --git a/dev/verilog/work/lq_dcc.v b/dev/verilog/work/lq_dcc.v index a342067..279b377 100755 --- a/dev/verilog/work/lq_dcc.v +++ b/dev/verilog/work/lq_dcc.v @@ -486,7 +486,8 @@ module lq_dcc( dcc_dir_binv6_ex6_stg_act, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -1058,13 +1059,10 @@ output dcc_dir_binv6_ex6_stg_ac inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -4422,7 +4420,8 @@ lq_fgen fgen( //pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -4662,7 +4661,8 @@ assign dcc_dir_binv6_ex6_stg_act = ex6_binv6_stg_act; tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_recirc_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4683,7 +4683,8 @@ generate begin : iu_lq_cp_next_itag_tid tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4704,7 +4705,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4722,7 +4724,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) xer_lq_cp_rd_so_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4740,7 +4743,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) xer_lq_cp_rd_so_reg tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4758,7 +4762,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_preissue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4776,7 +4781,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_preissue_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4794,7 +4800,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_2ucode_reg( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4812,7 +4819,8 @@ tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_uc tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4830,7 +4838,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_preissue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4848,7 +4857,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_preissue_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4866,7 +4876,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_2ucode_reg( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4884,7 +4895,8 @@ tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_uc tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4902,7 +4914,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype1_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4920,7 +4933,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype2_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4938,7 +4952,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype4_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype8_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4956,7 +4971,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype8_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype16_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4974,7 +4990,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_optype16_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4992,7 +5009,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype1_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5010,7 +5028,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype2_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5028,7 +5047,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype4_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype8_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5046,7 +5066,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype8_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype16_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5064,7 +5085,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_optype16_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dacr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5082,7 +5104,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dacr_type_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dacr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5100,7 +5123,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dacr_type_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_dacr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5118,7 +5142,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_dacr_type_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5136,7 +5161,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cache_acc_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5154,7 +5180,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_cache_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5172,7 +5199,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5190,7 +5218,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cache_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5208,7 +5237,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cache_acc_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5226,7 +5256,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_thrd_id_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5244,7 +5275,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5262,7 +5294,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5280,7 +5313,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5298,7 +5332,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_id_reg( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5316,7 +5351,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_reg( tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5334,7 +5370,8 @@ tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_reg( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex4_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5352,7 +5389,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex4_instr_reg( tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex5_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5370,7 +5408,8 @@ tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex5_instr_reg( tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_target_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5388,7 +5427,8 @@ tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_target_gp tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_target_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5406,7 +5446,8 @@ tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_target_gpr_re tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_target_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5424,7 +5465,8 @@ tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_target_gp tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_target_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5442,7 +5484,8 @@ tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_target_gpr_re tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbt_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5460,7 +5503,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbt_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbt_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5478,7 +5522,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbt_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbt_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5496,7 +5541,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbt_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5514,7 +5560,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5532,7 +5579,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5550,7 +5598,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5568,7 +5617,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5586,7 +5636,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5604,7 +5655,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtst_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5622,7 +5674,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtst_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5640,7 +5693,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtst_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wchk_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5658,7 +5712,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wchk_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wchk_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5676,7 +5731,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wchk_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wchk_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5694,7 +5750,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wchk_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5712,7 +5769,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbst_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5730,7 +5788,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbst_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbst_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5748,7 +5807,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbst_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbf_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5766,7 +5826,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbf_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbf_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5784,7 +5845,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbf_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbf_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5802,7 +5864,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbf_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mtspr_trace_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5820,7 +5883,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mtspr_trace_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mtspr_trace_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5838,7 +5902,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mtspr_trace_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mtspr_trace_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5856,7 +5921,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mtspr_trace_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5874,7 +5940,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sync_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5892,7 +5959,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sync_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5910,7 +5978,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sync_instr_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_l_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5928,7 +5997,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_l_fld_reg( tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex3_l_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5946,7 +6016,8 @@ tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex3_l_fld_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_l_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5964,7 +6035,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_l_fld_reg( tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_l_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5982,7 +6054,8 @@ tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_l_fld_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6000,7 +6073,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbi_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6018,7 +6092,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbi_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6036,7 +6111,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbi_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbz_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6054,7 +6130,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbz_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbz_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6072,7 +6149,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbz_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbz_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6090,7 +6168,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbz_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6108,7 +6187,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbi_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6126,7 +6206,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbi_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbi_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6144,7 +6225,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbi_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mbar_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6162,7 +6244,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mbar_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mbar_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6180,7 +6263,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mbar_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mbar_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6198,7 +6282,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mbar_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_makeitso_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6216,7 +6301,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_makeitso_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_makeitso_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6234,7 +6320,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_makeitso_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_makeitso_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6252,7 +6339,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_makeitso_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dci_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6270,7 +6358,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dci_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dci_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6288,7 +6377,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dci_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dci_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6306,7 +6396,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dci_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ici_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6324,7 +6415,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ici_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ici_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6342,7 +6434,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ici_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ici_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6360,7 +6453,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ici_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6378,7 +6472,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_algebraic_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6396,7 +6491,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_algebraic_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_strg_index_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6414,7 +6510,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_strg_index_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_strg_index_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6432,7 +6529,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_strg_index_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_index_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6450,7 +6548,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_index_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_resv_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6468,7 +6567,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_resv_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_resv_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6486,7 +6586,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_resv_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_resv_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6504,7 +6605,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_resv_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mutex_hint_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6522,7 +6624,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mutex_hint_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mutex_hint_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6540,7 +6643,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mutex_hint_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mutex_hint_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6558,7 +6662,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mutex_hint_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_load_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6576,7 +6681,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_load_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_load_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6594,7 +6700,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_load_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6612,7 +6719,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_store_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6630,7 +6738,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_store_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_store_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6648,7 +6757,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_store_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_store_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6666,7 +6776,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_store_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_le_mode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6684,7 +6795,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_le_mode_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_i_bits_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6702,7 +6814,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_i_bits_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_op_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6720,7 +6833,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_op_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_op_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6738,7 +6852,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_op_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_op_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6756,7 +6871,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_op_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_op_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6774,7 +6890,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_op_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_upd_form_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6792,7 +6909,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_upd_form_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_upd_form_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6810,7 +6928,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_upd_form_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_axu_instr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6828,7 +6947,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_axu_instr_type_reg( tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_instr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6846,7 +6966,8 @@ tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_instr_type_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6864,7 +6985,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_load_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6882,7 +7004,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_load_hit_reg( tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_usr_bits_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6900,7 +7023,8 @@ tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_usr_bits_reg( tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_classid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6918,7 +7042,8 @@ tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_classid_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_derat_setHold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6936,7 +7061,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_derat_setHold_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6954,7 +7080,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_axu_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_axu_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6972,7 +7099,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_axu_wren_reg( tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_ta_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -6990,7 +7118,8 @@ tri_regk #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_ta_gpr_reg tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_lq_ta_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7008,7 +7137,8 @@ tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_le_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7026,7 +7156,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_le_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_c_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7044,7 +7175,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_c_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_c_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7062,7 +7194,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_c_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_c_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7080,7 +7213,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_c_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_l2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7098,7 +7232,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_th_fld_l2_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_l2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7116,7 +7251,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_th_fld_l2_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_l2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7134,7 +7270,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_th_fld_l2_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7152,7 +7289,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtls_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7170,7 +7308,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtls_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7188,7 +7327,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtls_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtstls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7206,7 +7346,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcbtstls_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtstls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7224,7 +7365,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcbtstls_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtstls_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7242,7 +7384,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcbtstls_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcblc_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7260,7 +7403,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dcblc_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcblc_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7278,7 +7422,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_dcblc_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcblc_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7296,7 +7441,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dcblc_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icblc_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7314,7 +7460,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icblc_l2_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icblc_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7332,7 +7479,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icblc_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icblc_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7350,7 +7498,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icblc_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbt_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7368,7 +7517,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbt_l2_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbt_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7386,7 +7536,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbt_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbt_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7404,7 +7555,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbt_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbtls_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7422,7 +7574,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icbtls_l2_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbtls_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7440,7 +7593,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icbtls_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbtls_l2_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7458,7 +7612,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icbtls_l2_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tlbsync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7476,7 +7631,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tlbsync_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7494,7 +7650,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsync_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbsync_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7512,7 +7669,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbsync_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_falign_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7530,7 +7688,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_falign_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_fexcpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7548,7 +7707,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldst_fexcpt_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldst_fexcpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7566,7 +7726,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldst_fexcpt_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_miss_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7584,7 +7745,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_miss_reg( tri_ser_rlmreg_p #(.WIDTH((8+`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) xudbg1_dir_reg_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_darr_rd_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7602,7 +7764,8 @@ tri_ser_rlmreg_p #(.WIDTH((8+`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) xudbg1_di tri_ser_rlmreg_p #(.WIDTH(PARBITS), .INIT(0), .NEEDS_SRESET(1)) xudbg1_parity_reg_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_darr_rd_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7620,7 +7783,8 @@ tri_ser_rlmreg_p #(.WIDTH(PARBITS), .INIT(0), .NEEDS_SRESET(1)) xudbg1_parity_re tri_ser_rlmreg_p #(.WIDTH((63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH)+1), .INIT(0), .NEEDS_SRESET(1)) xudbg2_tag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_darr_rd_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7638,7 +7802,8 @@ tri_ser_rlmreg_p #(.WIDTH((63-(`DC_SIZE-3))-(64-`REAL_IFAR_WIDTH)+1), .INIT(0), tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7656,7 +7821,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7674,7 +7840,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgpr_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_saxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7692,7 +7859,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_saxu_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7710,7 +7878,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sdp_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7728,7 +7897,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tgpr_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_taxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7746,7 +7916,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_taxu_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7764,7 +7935,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tdp_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7782,7 +7954,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sgpr_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_saxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7800,7 +7973,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_saxu_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7818,7 +7992,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sdp_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7836,7 +8011,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tgpr_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_taxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7854,7 +8030,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_taxu_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7872,7 +8049,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_tdp_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7890,7 +8068,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sgpr_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_saxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7908,7 +8087,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_saxu_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7926,7 +8106,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sdp_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tgpr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7944,7 +8125,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tgpr_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_taxu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7962,7 +8144,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_taxu_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tdp_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7980,7 +8163,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tdp_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -7998,7 +8182,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_moveOp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8016,7 +8201,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_moveOp_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_moveOp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8034,7 +8220,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_moveOp_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_touch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8052,7 +8239,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_touch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_touch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8070,7 +8258,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_touch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_blkable_touch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8088,7 +8277,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_blkable_touch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_blk_touch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8106,7 +8296,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_blk_touch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_blk_touch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8124,7 +8315,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_blk_touch_reg( tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_eff_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_binv2_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -8142,7 +8334,8 @@ tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_eff_addr_r tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_eff_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_binv3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -8160,7 +8353,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_eff_ad tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_eff_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8178,7 +8372,8 @@ tri_regk #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_eff_addr_r tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_lockset_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8196,7 +8391,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_undef_lockset_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_lockset_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8214,7 +8410,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_undef_lockset_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_unable_2lock_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8232,7 +8429,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_unable_2lock_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq5_unable_2lock_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8250,7 +8448,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq5_unable_2lock_reg( tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_dacrw_cmpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8268,7 +8467,8 @@ tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_dacrw_cmpr_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_dacrw_cmpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8286,7 +8486,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_dacrw_cmpr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_stq_val_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8304,7 +8505,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_stq_val_req_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq_val_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8322,7 +8524,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq_val_req_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8340,7 +8543,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_load_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mword_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8358,7 +8562,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mword_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mword_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8376,7 +8581,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_mword_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_miss_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8394,7 +8600,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_miss_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_perf_dcbt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8412,7 +8619,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_perf_dcbt_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ap_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8430,7 +8638,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ap_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_trace_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8448,7 +8657,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_trace_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ucode_dis_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8466,7 +8676,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_ucode_dis_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8484,7 +8695,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) clkg_ctl_override_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8502,7 +8714,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) clkg_ctl_override_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_wlk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8520,7 +8733,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_wlk_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mbar_ack_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8538,7 +8752,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mbar_ack_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_tlbsync_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8556,7 +8771,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_tlbsync_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8574,7 +8790,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_aflsta_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8592,7 +8809,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_aflsta_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_flsta_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8610,7 +8828,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_flsta_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mddp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8628,7 +8847,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mddp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mdcp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8646,7 +8866,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_mdcp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mmu_mchk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8664,7 +8885,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mmu_mchk_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mddmh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8682,7 +8904,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr4_mddmh_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_xucr0_en_trace_um_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8700,7 +8923,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_xucr0_en_trace_ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_lsu_64bit_mode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8718,7 +8942,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_lsu_64bit_mode_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_lsu_64bit_agen_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -8736,7 +8961,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_lsu_64bit_agen_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_lsu_64bit_agen_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8754,7 +8980,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_lsu_64bit_agen_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lsu_64bit_agen_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -8772,7 +8999,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lsu_64bit_agen_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_local_dcbf_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8790,7 +9018,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_local_dcbf_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msgsnd_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8808,7 +9037,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msgsnd_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_msgsnd_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8826,7 +9056,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_msgsnd_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_msgsnd_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8844,7 +9075,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_msgsnd_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8862,7 +9094,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_load_type_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_gath_load_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8880,7 +9113,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_gath_load_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l2load_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8898,7 +9132,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l2load_type_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8916,7 +9151,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8934,7 +9170,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldawx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8952,7 +9189,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ldawx_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldawx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -8970,7 +9208,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ldawx_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldawx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8988,7 +9227,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldawx_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_ldawx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9006,7 +9246,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_ldawx_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wclr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9024,7 +9265,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_wclr_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wclr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9042,7 +9284,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_wclr_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wclr_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9060,7 +9303,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wclr_instr_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_opsize_enc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9078,7 +9322,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_opsize_enc_reg( tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_opsize_enc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9096,7 +9341,8 @@ tri_regk #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_opsize_enc_reg( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9114,7 +9360,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_reg( tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9132,7 +9379,8 @@ tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_reg( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9150,7 +9398,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_reg( tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9168,7 +9417,8 @@ tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_reg( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9186,7 +9436,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_drop_rel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9204,7 +9455,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_drop_rel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9222,7 +9474,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9240,7 +9493,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9258,7 +9512,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswxdot_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9276,7 +9531,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswxdot_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswxdot_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9294,7 +9550,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswxdot_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswxdot_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9312,7 +9569,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswxdot_instr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_epid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9330,7 +9588,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_icswx_epid_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_epid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9348,7 +9607,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_icswx_epid_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_epid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9366,7 +9626,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_epid_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_icswx_epid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9384,7 +9645,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_icswx_epid_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_c_inh_drop_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9402,7 +9664,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_c_inh_drop_op_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_axu_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9420,7 +9683,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_axu_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_axu_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9438,7 +9702,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_axu_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_axu_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9456,7 +9721,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_axu_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_axu_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9474,7 +9740,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_axu_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9492,7 +9759,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_store_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9510,7 +9778,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_store_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_store_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9528,7 +9797,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_store_hit_reg( tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) rel2_ta_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9546,7 +9816,8 @@ tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) rel2_ta_gpr_r tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -9564,7 +9835,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -9582,7 +9854,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -9600,7 +9873,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -9618,7 +9892,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -9636,7 +9911,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -9654,7 +9930,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9672,7 +9949,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_derat_snoop_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9690,7 +9968,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_derat_snoop_val_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_fp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9708,7 +9987,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_fp_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_spv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9726,7 +10006,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_spv_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9744,7 +10025,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9762,7 +10044,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ds_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9780,7 +10063,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ds_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_de_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9798,7 +10082,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_de_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_dbcr0_idm_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9816,7 +10101,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_dbcr0_idm_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_epcr_duvd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9834,7 +10120,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_epcr_duvd_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) spr_lpidr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9855,7 +10142,8 @@ generate begin : spr_pid_reg tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) spr_pid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9876,7 +10164,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9894,7 +10183,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_gs_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_pr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9912,7 +10202,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_icswx_pr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9930,7 +10221,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_val_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9948,7 +10240,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex4_icswx_ct_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -9966,7 +10259,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( tri_regk #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -9984,7 +10278,8 @@ tri_regk #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_rcvd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10002,7 +10297,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_rcvd_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10020,7 +10316,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wNComp_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10038,7 +10335,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_cr_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10056,7 +10354,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_cr_upd_reg( tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_dvc_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10074,7 +10373,8 @@ tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_dvc_en_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10092,7 +10392,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_dvc_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_inval_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10110,7 +10411,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_inval_op_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l1_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10128,7 +10430,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_l1_lock_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_l1_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10146,7 +10449,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_l1_lock_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lock_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10164,7 +10468,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lock_clr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lock_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10182,7 +10487,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lock_clr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10200,7 +10506,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sfx_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10218,7 +10525,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sfx_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10236,7 +10544,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10254,7 +10563,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10272,7 +10582,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10290,7 +10601,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10308,7 +10620,8 @@ tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_ucode tri_regk #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10326,7 +10639,8 @@ tri_regk #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_cnt tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10344,7 +10658,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_op_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10362,7 +10677,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_ucode_op_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10380,7 +10696,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_op_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_comp_rpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10398,7 +10715,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_comp_rpt_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_execute_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10416,7 +10734,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_execute_vld_ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10434,7 +10753,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_itag_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10452,7 +10772,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_type_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_recirc_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10470,7 +10791,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_recirc_val_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10488,7 +10810,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_flush2ucode_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dear_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10506,7 +10829,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dear_val_reg tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_eff_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10524,7 +10848,8 @@ tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_eff tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_n_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10542,7 +10867,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_n_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_np1_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10560,7 +10886,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_np1_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10578,7 +10905,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_val_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10596,7 +10924,8 @@ tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_exception_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacr_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10614,7 +10943,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacr_type_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacrw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10632,7 +10962,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_dacrw_reg( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_instr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq0_iu_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10650,7 +10981,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq0_iu_instr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_load_miss_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10668,7 +11000,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_load_miss_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10686,7 +11019,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_vld_reg( tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10704,7 +11038,8 @@ tri_regk #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_itag_reg tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10722,7 +11057,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_spec_tid_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_blk_pf_load_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10740,7 +11076,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_blk_pf_load_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wNComp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10758,7 +11095,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lq_wNComp_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wNComp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10776,7 +11114,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lq_wNComp_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_ord_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10794,7 +11133,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_ord_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_restart_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10812,7 +11152,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_restart_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10830,7 +11171,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_derat_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10848,7 +11190,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_derat_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10866,7 +11209,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dir_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10884,7 +11228,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dir_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dec_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10902,7 +11247,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dec_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dec_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10921,7 +11267,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_dec_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_derat_itagHit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10939,7 +11286,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_derat_itagHit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq_restart_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10956,7 +11304,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stq_restart_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_restart_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -10974,7 +11323,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_restart_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_execute_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -10992,7 +11342,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_execute_vld_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_flush2ucode_type_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11010,7 +11361,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_flush2ucode_type_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_recirc_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11028,7 +11380,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_recirc_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wchkall_cplt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11046,7 +11399,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_wchkall_cplt_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_misalign_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11064,7 +11418,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_misalign_flush_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_idle_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11082,7 +11437,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_idle_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_gate_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11100,7 +11456,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_strg_gate_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lswx_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11118,7 +11475,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lswx_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11136,7 +11494,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_icswx_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_sync_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11154,7 +11513,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_sync_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_xu_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11172,7 +11532,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_xu_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_store_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11190,7 +11551,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_store_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_store_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11208,7 +11570,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_store_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11226,7 +11589,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_store_val_reg( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11244,7 +11608,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_itag_reg tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_tgpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11262,7 +11627,8 @@ tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) stq6_tgpr_reg tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11280,7 +11646,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq3_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11298,7 +11665,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq3_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11316,7 +11684,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq5_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11334,7 +11703,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq5_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq6_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11352,7 +11722,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq6_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq7_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11370,7 +11741,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq7_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq8_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11388,7 +11760,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq8_thrd_id_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11406,7 +11779,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11424,7 +11798,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11442,7 +11817,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mftgpr_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11460,7 +11836,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11478,7 +11855,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11496,7 +11874,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq8_mftgpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11514,7 +11893,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq8_mftgpr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpf_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11532,7 +11912,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpf_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpf_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11550,7 +11931,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpf_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpf_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11568,7 +11950,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpf_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpf_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11586,7 +11969,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpf_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpa_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11604,7 +11988,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mfdpa_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpa_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11622,7 +12007,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_mfdpa_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpa_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11640,7 +12026,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_mfdpa_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpa_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11658,7 +12045,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq5_mfdpa_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mfdpa_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11676,7 +12064,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mfdpa_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ci_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11694,7 +12083,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ci_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_ci_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11712,7 +12102,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_ci_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_resv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11730,7 +12121,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_resv_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_resv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11748,7 +12140,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_resv_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11766,7 +12159,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_wclr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11784,7 +12178,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_wclr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11802,7 +12197,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_all_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11820,7 +12216,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_wclr_all_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_wclr_all_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11838,7 +12235,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_wclr_all_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_all_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11856,7 +12254,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_wclr_all_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_epid_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11874,7 +12273,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_epid_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_rec_stcx_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11892,7 +12292,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_rec_stcx_reg( tri_regk #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) stq3_icswx_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(stq2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11910,7 +12311,8 @@ tri_regk #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) stq3_icswx_data_reg( tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_cr_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_instr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11928,7 +12330,8 @@ tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_cr_fld_reg( tri_regk #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_cr_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11946,7 +12349,8 @@ tri_regk #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_cr_fld_reg( tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_cr_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -11964,7 +12368,8 @@ tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_cr_fld_reg( tri_regk #(.WIDTH(`CR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_cr_fld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -11982,7 +12387,8 @@ tri_regk #(.WIDTH(`CR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) e tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12000,7 +12406,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_val_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12018,7 +12425,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_tid_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_rv1_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12036,7 +12444,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_rv1_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex0_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12054,7 +12463,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex0_done_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex1_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -12072,7 +12482,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex1_done_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex2_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12090,7 +12501,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex2_done_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex3_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -12108,7 +12520,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex3_done_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex4_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12126,7 +12539,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex4_done_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex5_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -12144,7 +12558,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex5_done_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex6_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12162,7 +12577,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dir_arr_rd_ex6_done_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_ram_active_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12180,7 +12596,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_ram_active_re tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_data_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12201,7 +12618,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_pc_ram_data_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12219,7 +12637,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12237,7 +12656,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12255,7 +12675,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12273,7 +12694,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12291,7 +12713,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12309,7 +12732,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv2_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -12327,7 +12751,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv2_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv3_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -12345,7 +12770,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv3_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -12363,7 +12789,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv5_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -12381,7 +12808,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv5_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv6_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -12399,7 +12827,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv6_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12417,7 +12846,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12435,7 +12865,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -12453,7 +12884,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_dec.v b/dev/verilog/work/lq_dec.v index 37c831d..356601a 100755 --- a/dev/verilog/work/lq_dec.v +++ b/dev/verilog/work/lq_dec.v @@ -36,7 +36,8 @@ module lq_dec( - nclk, + clk, + rst, vdd, gnd, d_mode_dc, @@ -228,14 +229,9 @@ module lq_dec( inout vdd; - - inout gnd; - -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; - +input clk; +input rst; input d_mode_dc; input delay_lclkr_dc; input mpw1_dc_b; @@ -2161,7 +2157,8 @@ assign ex0_is_icswxdot = (rv_lq_ex0_instr[0:5] == 6'b011111) & (rv_lq_ex0_instr //---------------------------------------------------------------------------------------------------------------------------------------- tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2179,7 +2176,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2197,7 +2195,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ucle_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2215,7 +2214,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ucle_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msrp_uclep_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2233,7 +2233,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msrp_uclep_latc ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_pc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2251,7 +2252,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_pc_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_ditc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2269,7 +2271,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_ditc_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_icswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2287,7 +2290,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_icswx_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2305,7 +2309,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2323,7 +2328,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2341,7 +2347,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2359,7 +2366,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2377,7 +2385,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2395,7 +2404,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2413,7 +2423,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2431,7 +2442,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2449,7 +2461,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2467,7 +2480,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2485,7 +2499,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2503,7 +2518,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2521,7 +2537,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_stg_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2539,7 +2556,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_stg_act_latch( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2557,7 +2575,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( ); tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_cnt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2575,7 +2594,8 @@ tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2593,7 +2613,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_load_dac_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_stg_act_q), @@ -2611,7 +2632,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_load_dac_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_store_dac_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_stg_act_q), @@ -2629,7 +2651,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_any_store_dac_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dir_rd_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2647,7 +2670,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dir_rd_act_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2665,7 +2689,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_tid_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stq2_stg_act), @@ -2683,7 +2708,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_stg_act_d), @@ -2701,7 +2727,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_stg_act_q), @@ -2719,7 +2746,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_stg_act_q), @@ -2737,7 +2765,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_tid_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2755,7 +2784,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2773,7 +2803,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2791,7 +2822,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2809,7 +2841,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2827,7 +2860,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2845,7 +2879,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2863,7 +2898,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_t1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2881,7 +2917,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_t1_we_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ex5_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2899,7 +2936,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ex5_act_latch( ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t1_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2917,7 +2955,8 @@ tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t1_wa_latc ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t3_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stg_act_q), @@ -2935,7 +2974,8 @@ tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t3_wa_latc ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_stq2_stg_act), @@ -2953,7 +2993,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latc ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_stq3_stg_act), @@ -2971,7 +3012,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latc ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) release_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2989,7 +3031,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) release_itag_ ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) release_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3007,7 +3050,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) release_tid_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) release_itag_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3025,7 +3069,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) release_itag_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_needs_release_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3043,7 +3088,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_needs_release_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_needs_release_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3061,7 +3107,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_needs_release_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_needs_release_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3079,7 +3126,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_needs_release_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_physical_upd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3097,7 +3145,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_physical_upd_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3115,7 +3164,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_req_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3133,7 +3183,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3151,7 +3202,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_req_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_physical_upd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3169,7 +3221,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_axu_physical_upd_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_axu_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3187,7 +3240,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_axu_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3205,7 +3259,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_axu_abort_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3223,7 +3278,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_axu_abort_rpt_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_release_attmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3241,7 +3297,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_release_attmp_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_attmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3259,7 +3316,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_attmp_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_needs_release_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3277,7 +3335,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_needs_release_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3295,7 +3354,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3313,7 +3373,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3331,7 +3392,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3349,7 +3411,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3367,7 +3430,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_release_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3385,7 +3449,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_release_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_hold_req_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3403,7 +3468,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_hold_req_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_req_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3421,7 +3487,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_req_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3439,7 +3506,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_hold_done_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_hold_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3457,7 +3525,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_hold_taken_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_hold_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3475,7 +3544,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_hold_taken_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_hold_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3493,7 +3563,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_hold_taken_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_back_inv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3511,7 +3582,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_back_inv_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_back_inv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3529,7 +3601,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_back_inv_latch( ); tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-`CL_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex0_back_inv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rv1_back_inv_q), @@ -3547,7 +3620,8 @@ tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-`CL_SIZE), .INIT(0), .NEEDS_SRESET(1)) ex ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_selimm_addr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3565,7 +3639,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_selimm_addr_val_latch( ); tri_rlmreg_p #(.WIDTH((64-`CL_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex1_selimm_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_selimm_addr_val), @@ -3583,7 +3658,8 @@ tri_rlmreg_p #(.WIDTH((64-`CL_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex1_selimm_add ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3601,7 +3677,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_val_latch( ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_congr_cl_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3619,7 +3696,8 @@ tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex0_arr_rd_congr_cl_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3637,7 +3715,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_val_latch( ); tri_rlmreg_p #(.WIDTH(52), .INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(derat_rv1_snoop_val), @@ -3655,7 +3734,8 @@ tri_rlmreg_p #(.WIDTH(52), .INIT(0), .NEEDS_SRESET(1)) ex0_derat_snoop_addr_latc ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3673,7 +3753,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_latc ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3691,7 +3772,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_mftgpr_val_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3709,7 +3791,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_mftgpr_val_latch( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq2_release_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3727,7 +3810,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stq2_release_ ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_release_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), diff --git a/dev/verilog/work/lq_derat.v b/dev/verilog/work/lq_derat.v index e6eebdb..281cf58 100755 --- a/dev/verilog/work/lq_derat.v +++ b/dev/verilog/work/lq_derat.v @@ -35,15 +35,12 @@ `include "tri_a2o.vh" - - - - module lq_derat( gnd, vdd, vcs, - nclk, + clk, + rst, pc_xu_init_reset, pc_xu_ccflush_dc, tc_scan_dis_dc_b, @@ -225,17 +222,11 @@ module lq_derat( inout gnd; - - inout vdd; - - inout vcs; - - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_xu_init_reset; input pc_xu_ccflush_dc; input tc_scan_dis_dc_b; @@ -4345,7 +4336,8 @@ module lq_derat( .gnd(gnd), .vdd(vdd), .vcs(vcs), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(pc_xu_ccflush_dc), .tc_scan_dis_dc_b(tc_scan_dis_dc_b), @@ -4867,7 +4859,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_hv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4885,7 +4878,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4903,7 +4897,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_ds_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4921,7 +4916,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_cm_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4939,7 +4935,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4957,7 +4954,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mchk_flash_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mchk_flash_inv_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4975,7 +4973,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4993,7 +4992,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_next_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5017,7 +5017,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5039,7 +5040,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5060,7 +5062,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_byte_rev_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5078,7 +5081,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_byte_rev_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5096,7 +5100,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5114,7 +5119,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5132,7 +5138,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5150,7 +5157,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5168,7 +5176,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5186,7 +5195,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5204,7 +5214,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex2_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5223,7 +5234,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex2_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5241,7 +5253,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5259,7 +5272,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5277,7 +5291,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5295,7 +5310,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex2_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5313,7 +5329,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex2_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5332,7 +5349,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_data_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex1_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5351,7 +5369,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5369,7 +5388,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5387,7 +5407,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5405,7 +5426,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5423,7 +5445,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex3_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5441,7 +5464,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex3_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5459,7 +5483,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex3_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5477,7 +5502,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5495,7 +5521,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5513,7 +5540,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex3_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5531,7 +5559,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex3_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5550,7 +5579,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5568,7 +5598,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5586,7 +5617,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5604,7 +5636,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5622,7 +5655,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex4_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5640,7 +5674,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5658,7 +5693,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex4_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5676,7 +5712,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5694,7 +5731,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5712,7 +5750,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(lpid_width), .INIT(0), .NEEDS_SRESET(1)) ex4_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5730,7 +5769,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex4_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5748,7 +5788,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex4_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5767,7 +5808,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5785,7 +5827,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5803,7 +5846,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5821,7 +5865,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5839,7 +5884,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex5_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5857,7 +5903,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex5_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5875,7 +5922,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex5_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5893,7 +5941,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5911,7 +5960,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5929,7 +5979,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(lpid_width), .INIT(0), .NEEDS_SRESET(1)) ex5_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5947,7 +5998,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex5_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5965,7 +6017,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5984,7 +6037,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6002,7 +6056,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6020,7 +6075,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6038,7 +6094,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6056,7 +6113,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex6_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6074,7 +6132,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex6_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6092,7 +6151,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex6_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6110,7 +6170,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6128,7 +6189,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6146,7 +6208,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex6_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6164,7 +6227,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex6_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6183,7 +6247,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6201,7 +6266,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6219,7 +6285,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6237,7 +6304,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ex7_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6255,7 +6323,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(rs_is_width), .INIT(0), .NEEDS_SRESET(1)) ex7_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6273,7 +6342,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex7_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6291,7 +6361,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(state_width), .INIT(0), .NEEDS_SRESET(1)) ex7_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6309,7 +6380,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(pid_width), .INIT(0), .NEEDS_SRESET(1)) ex7_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6327,7 +6399,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(extclass_width), .INIT(0), .NEEDS_SRESET(1)) ex7_extclass_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6345,7 +6418,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex7_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6364,7 +6438,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6382,7 +6457,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_pfetch_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6400,7 +6476,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ttype_width), .INIT(0), .NEEDS_SRESET(1)) ex8_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6418,7 +6495,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(tlbsel_width), .INIT(0), .NEEDS_SRESET(1)) ex8_tlbsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6437,7 +6515,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6455,7 +6534,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_req_inprogress_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6473,7 +6553,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_dsi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6491,7 +6572,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_noop_touch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6509,7 +6591,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6527,7 +6610,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_dsi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6545,7 +6629,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((7+(2*`THREADS)+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_noop_touch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6563,7 +6648,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6581,7 +6667,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(num_entry), .INIT(0), .NEEDS_SRESET(1)) ex4_multihit_b_pt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6599,7 +6686,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((num_entry-1)), .INIT(0), .NEEDS_SRESET(1)) ex4_first_hit_entry_pt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6617,7 +6705,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) ex4_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6635,7 +6724,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6653,7 +6743,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cam_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6671,7 +6762,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6689,7 +6781,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) ex3_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6707,7 +6800,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) ex4_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6725,7 +6819,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) rw_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6743,7 +6838,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rw_entry_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6761,7 +6857,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rw_entry_le_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6779,7 +6876,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) cam_entry_le_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rw_entry_val_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6797,7 +6895,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(30), .INIT(0), .NEEDS_SRESET(1)) ex3_comp_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6815,7 +6914,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(30), .INIT(0), .NEEDS_SRESET(1)) ex4_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6833,7 +6933,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex4_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6851,7 +6952,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_cam_cmp_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_cmp_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6869,7 +6971,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_array_cmp_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_cmp_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6887,7 +6990,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(array_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_array_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_rd_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6905,7 +7009,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(cam_data_width), .INIT(0), .NEEDS_SRESET(1)) ex4_rd_cam_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_rd_data_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6923,7 +7028,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+5)), .INIT(0), .NEEDS_SRESET(1)) ex5_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6941,7 +7047,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+3)), .INIT(0), .NEEDS_SRESET(1)) ex5_fir_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6959,7 +7066,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_fir_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6977,7 +7085,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2-1+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_deen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6995,7 +7104,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7013,7 +7123,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2)), .INIT(0), .NEEDS_SRESET(1)) ex6_deen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7031,7 +7142,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7049,7 +7161,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((`THREADS+num_entry_log2)), .INIT(0), .NEEDS_SRESET(1)) ex7_deen_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7067,7 +7180,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7085,7 +7199,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) barrier_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7103,7 +7218,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7127,7 +7243,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) rpn_holdreg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7149,7 +7266,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) entry_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_valid_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7167,7 +7285,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) entry_match_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7185,7 +7304,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(watermark_width), .INIT(29), .NEEDS_SRESET(1)) watermark_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7203,7 +7323,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucr1_b0_cpy_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7221,7 +7342,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((lru_width+1)), .INIT(0), .NEEDS_SRESET(1)) lru_rmt_vec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7239,7 +7361,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(eptr_width), .INIT(0), .NEEDS_SRESET(1)) eptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7257,7 +7380,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(lru_width), .INIT(0), .NEEDS_SRESET(1)) lru_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7275,7 +7399,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lru_update_event_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7294,7 +7419,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(41), .INIT(0), .NEEDS_SRESET(1)) lru_debug_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7312,7 +7438,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7330,7 +7457,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7348,7 +7476,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((epn_width)), .INIT(0), .NEEDS_SRESET(1)) snoop_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7366,7 +7495,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex2_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7384,7 +7514,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7402,7 +7533,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7420,7 +7552,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) por_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7438,7 +7571,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_init_reset_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7457,7 +7591,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7475,7 +7610,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7493,7 +7629,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) tlb_rel_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7511,7 +7648,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((2*`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) eplc_wr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7529,7 +7667,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((2*`THREADS+1)), .INIT(0), .NEEDS_SRESET(1)) epsc_wr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7547,7 +7686,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(1)) ccr2_frat_paranoia_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7565,7 +7705,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) clkg_ctl_override_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7583,7 +7724,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7601,7 +7743,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7619,7 +7762,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7637,7 +7781,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7655,7 +7800,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7673,7 +7819,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_stg_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7691,7 +7838,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_rel_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7709,7 +7857,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoopp_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7727,7 +7876,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_grffence_en_dc_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7745,7 +7895,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7763,7 +7914,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7781,7 +7933,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) csync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7799,7 +7952,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) isync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7817,7 +7971,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7835,7 +7990,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7853,7 +8009,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(132), .INIT(0), .NEEDS_SRESET(1)) rel_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7871,7 +8028,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) rel_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7889,7 +8047,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) rel_int_upd_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_rel_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7907,7 +8066,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) epsc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7925,7 +8085,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eplc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7943,7 +8104,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7961,7 +8123,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) snoopp_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7979,7 +8142,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoopp_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoopp_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -7997,7 +8161,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((epn_width)), .INIT(0), .NEEDS_SRESET(1)) snoopp_vpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoopp_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8015,7 +8180,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ttype_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8033,7 +8199,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8051,7 +8218,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(ws_width), .INIT(0), .NEEDS_SRESET(1)) ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8069,7 +8237,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8087,7 +8256,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rs_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8105,7 +8275,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) eratre_hole_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8123,7 +8294,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) eratwe_hole_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8141,7 +8313,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_csync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8159,7 +8332,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_csync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8177,7 +8351,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_isync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8195,7 +8370,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_isync_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8213,7 +8389,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rv1_rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8231,7 +8408,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex0_rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8249,7 +8427,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex1_rel_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8267,7 +8446,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_epsc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8285,7 +8465,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_epsc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8303,7 +8484,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_eplc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8321,7 +8503,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_eplc_wr_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8339,7 +8522,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8357,7 +8541,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8375,7 +8560,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8393,7 +8579,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8411,7 +8598,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8429,7 +8617,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_ttype_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8447,7 +8636,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_ttype_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8465,7 +8655,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rv1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8483,7 +8674,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex0_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8501,7 +8693,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype03_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8519,7 +8712,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype67_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8537,7 +8731,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8555,7 +8750,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8573,7 +8769,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8591,7 +8788,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8609,7 +8807,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8627,7 +8826,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8645,7 +8845,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8663,7 +8864,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_valid_op_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8681,7 +8883,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ord_write_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8699,7 +8902,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_ord_read_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8717,7 +8921,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8735,7 +8940,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) xu_lq_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8753,7 +8959,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratre_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8771,7 +8978,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratwe_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8789,7 +8997,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratsx_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8807,7 +9016,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_is_eratilx_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8825,7 +9035,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) xu_lq_ws_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8843,7 +9054,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xu_lq_ra_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8861,7 +9073,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2**`GPR_WIDTH_ENC), .INIT(0), .NEEDS_SRESET(1)) xu_lq_rs_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_lq_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8879,7 +9092,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8897,7 +9111,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_oldest_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8915,7 +9130,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_nonspec_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8933,7 +9149,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8951,7 +9168,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlbinelig_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8969,7 +9187,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ptfault_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -8987,7 +9206,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lratmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9005,7 +9225,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9023,7 +9244,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9041,7 +9263,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lru_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9059,7 +9282,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_tlb_excp_det_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9077,7 +9301,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex3_eratm_itag_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9095,7 +9320,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_emq_excp_rpt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9113,7 +9339,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_emq_excp_rpt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9131,7 +9358,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex6_emq_excp_rpt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9149,7 +9377,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_tlb_excp_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9167,7 +9396,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_tlb_excp_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9185,7 +9415,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_gate_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9203,7 +9434,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_full_restart_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9221,7 +9453,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_itag_hit_restart_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9239,7 +9472,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_epn_hit_restart_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9257,7 +9491,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_setHold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9275,7 +9510,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9293,7 +9529,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9311,7 +9548,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9329,7 +9567,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9347,7 +9586,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_tlbreq_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9365,7 +9605,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_perf_dtlb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9383,7 +9624,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_dcc_clr_hold_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9408,7 +9650,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9430,7 +9673,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9452,7 +9696,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9474,7 +9719,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((51-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9501,7 +9747,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9529,7 +9776,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9557,7 +9805,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH((51-(64-(2**GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_entry_wrt_val[emq]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9579,7 +9828,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_nonspec_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9597,7 +9847,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_mkill_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9615,7 +9866,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) eratm_hold_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9633,7 +9885,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9651,7 +9904,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlbmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9669,7 +9923,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlbinelig_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9687,7 +9942,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_ptfault_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9705,7 +9961,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_lratmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9723,7 +9980,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlb_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9741,7 +9999,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_tlb_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9759,7 +10018,8 @@ module lq_derat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_int_rpt_lru_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9777,7 +10037,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlbmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9795,7 +10056,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlbinelig_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9813,7 +10075,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_ptfault_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9831,7 +10094,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_lratmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9849,7 +10113,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlb_multihit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9867,7 +10132,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_tlb_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -9885,7 +10151,8 @@ module lq_derat( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) eratm_entry_lru_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -10033,7 +10300,8 @@ module lq_derat( tri_plat #(.WIDTH(4)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_xu_ccflush_dc), .din({pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_sg_2}), .q({pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_sg_1}) @@ -10042,7 +10310,8 @@ module lq_derat( tri_plat #(.WIDTH(4)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_xu_ccflush_dc), .din({pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_sg_1}), .q({pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_sg_0}) @@ -10074,7 +10343,8 @@ module lq_derat( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(pc_cfg_slp_sl_force), .thold_b(pc_cfg_slp_sl_thold_0_b), .dclk(lcb_dclk), diff --git a/dev/verilog/work/lq_dir.v b/dev/verilog/work/lq_dir.v index fd1d9e7..d6d9355 100755 --- a/dev/verilog/work/lq_dir.v +++ b/dev/verilog/work/lq_dir.v @@ -185,7 +185,8 @@ module lq_dir( dir_dcc_ex5_stp_flush, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -397,7 +398,8 @@ inout gnd; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -822,7 +824,8 @@ lq_dir_val l1dcdv( //pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -975,7 +978,8 @@ lq_dir_lru l1dcdl( //pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -1083,7 +1087,8 @@ lq_dir_tag #(.WAYDATASIZE(WAYDATASIZE), .PARBITS(PARBITS)) l1dcdt( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -1123,7 +1128,8 @@ assign dir_dec_rel3_dir_wr_addr = rel3_dir_wr_addr; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_dir_wr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1141,7 +1147,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_dir_wr_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1159,7 +1166,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_dcdis_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_dir_lru.v b/dev/verilog/work/lq_dir_lru.v index d2d44cb..10285b6 100755 --- a/dev/verilog/work/lq_dir_lru.v +++ b/dev/verilog/work/lq_dir_lru.v @@ -133,7 +133,8 @@ module lq_dir_lru( lq_xu_spr_xucr0_clo, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -292,7 +293,8 @@ inout gnd; (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -1231,7 +1233,8 @@ generate begin : congr_cl_lru tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_lru_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1253,7 +1256,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rel2_xucr2_rmt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1272,7 +1276,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rel2_xucr2_rmt_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_wlk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1291,7 +1296,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_wlk_reg( tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) lq_congr_cl_lru_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex4_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1310,7 +1316,8 @@ tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) lq_congr_cl_lru_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ldst_hit_vector_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex4_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1329,7 +1336,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ldst_hit_vector_reg( tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) rel_congr_cl_lru_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1348,7 +1356,8 @@ tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) rel_congr_cl_lru_re tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex3_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1367,7 +1376,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex3_congr_cl_ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex4_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1386,7 +1396,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex4_congr_cl_ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex5_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex4_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1405,7 +1416,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex5_congr_cl_ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex6_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1424,7 +1436,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) ex6_congr_cl_ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq2_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1443,7 +1456,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq2_congr_cl tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq3_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1462,7 +1476,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq3_congr_cl tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq4_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1481,7 +1496,8 @@ tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) stq4_congr_cl tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1500,7 +1516,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1519,7 +1536,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq3_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1538,7 +1556,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq3_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1557,7 +1576,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq4_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1576,7 +1596,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1595,7 +1616,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_stq3_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1614,7 +1636,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_stq3_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_stq4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1633,7 +1656,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_stq4_cmp_reg( tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) ex6_lru_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1652,7 +1676,8 @@ tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) ex6_lru_upd_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1671,7 +1696,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1690,7 +1716,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_data_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1709,7 +1736,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_data_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_data_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1728,7 +1756,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_data_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_c_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1747,7 +1776,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_c_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_c_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1766,7 +1796,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_c_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_c_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1785,7 +1816,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_c_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_val_wen_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1804,7 +1836,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_val_wen_reg( tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) stq4_lru_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1823,7 +1856,8 @@ tri_rlmreg_p #(.WIDTH(lruState), .INIT(0), .NEEDS_SRESET(1)) stq4_lru_upd_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel2_rel_tag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1842,7 +1876,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel2_rel_tag_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel3_rel_tag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1861,7 +1896,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) rel3_rel_tag_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_set_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1880,7 +1916,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_set_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1899,7 +1936,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_stg_val_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel3_wlock_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1918,7 +1956,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel3_wlock_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1937,7 +1976,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_sel_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel_way_qsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1956,7 +1996,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel_way_qsel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel_val_qsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1975,7 +2016,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel_val_qsel_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel4_dir_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1996,7 +2038,8 @@ generate begin : reld_q_congr_cl tri_rlmreg_p #(.WIDTH(numCClassWidth), .INIT(0), .NEEDS_SRESET(1)) reld_q_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_q_set[lmq0]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2020,7 +2063,8 @@ generate begin : reld_q_way tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) reld_q_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_q_set[lmq1]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2042,7 +2086,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2061,7 +2106,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_val_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_lock_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2080,7 +2126,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) reld_q_lock_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel3_m_q_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2099,7 +2146,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) rel3_m_q_way_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lru_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2118,7 +2166,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lru_upd_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_lock_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2137,7 +2186,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_lock_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_lock_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2156,7 +2206,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_lock_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clo_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2175,7 +2226,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clo_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_way_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2194,7 +2246,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_dcarr_way_en_re tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stq2_class_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2213,7 +2266,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stq2_class_id_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2232,7 +2286,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2251,7 +2306,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_dir_tag.v b/dev/verilog/work/lq_dir_tag.v index f9a4512..cc6fe1a 100755 --- a/dev/verilog/work/lq_dir_tag.v +++ b/dev/verilog/work/lq_dir_tag.v @@ -103,7 +103,8 @@ module lq_dir_tag( stq3_tag_way_perr, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -213,13 +214,10 @@ output [0:7] stq3_tag_way_perr inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -576,7 +574,8 @@ assign stq3_tag_way_perr = {stq3_perr_det_a, stq3_perr_det_b, stq3_perr_det_c, s tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -595,7 +594,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_ldp_parity_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -614,7 +614,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_ldp_parity_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_stp_parity_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -632,7 +633,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_ddir_stp_parity_reg( tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq2_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -651,7 +653,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1 tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq3_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -670,7 +673,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1 tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1)) stq4_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -688,7 +692,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit - uprTagBit) + 1), .INIT(0), .NEEDS_SRESET(1 tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_en_par_chk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -707,7 +712,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_en_par_chk_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq3_en_par_chk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_dir_val.v b/dev/verilog/work/lq_dir_val.v index 38e75ff..00bd237 100755 --- a/dev/verilog/work/lq_dir_val.v +++ b/dev/verilog/work/lq_dir_val.v @@ -205,7 +205,8 @@ module lq_dir_val( rel_way_lock_h, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -426,13 +427,10 @@ output rel_way_lock_h; // Way inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -2579,7 +2577,8 @@ generate begin : congr_cl_wA tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wA_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassA]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2604,7 +2603,8 @@ generate begin : congr_cl_wB tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wB_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassB]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2629,7 +2629,8 @@ generate begin : congr_cl_wC tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wC_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassC]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2654,7 +2655,8 @@ generate begin : congr_cl_wD tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wD_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassD]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2679,7 +2681,8 @@ generate begin : congr_cl_wE tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wE_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassE]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2704,7 +2707,8 @@ generate begin : congr_cl_wF tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wF_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassF]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2729,7 +2733,8 @@ generate begin : congr_cl_wG tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wG_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassG]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2754,7 +2759,8 @@ generate begin : congr_cl_wH tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) congr_cl_wH_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(congr_cl_act[cclassH]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2775,7 +2781,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(numCClass), .INIT(0), .NEEDS_SRESET(1)) p0_congr_cl_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv5_ex5_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2793,7 +2800,8 @@ tri_rlmreg_p #(.WIDTH(numCClass), .INIT(0), .NEEDS_SRESET(1)) p0_congr_cl_act_re tri_rlmreg_p #(.WIDTH(numCClass), .INIT(0), .NEEDS_SRESET(1)) p1_congr_cl_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2814,7 +2822,8 @@ generate begin : ex4_way_val tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex4_way_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv3_ex3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2838,7 +2847,8 @@ generate begin : ex5_way_val tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex5_way_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -2859,7 +2869,8 @@ endgenerate tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_clr_lck_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -2877,7 +2888,8 @@ tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_clr_lck_way_reg( tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -2895,7 +2907,8 @@ tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_way_upd_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex6_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2913,7 +2926,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex6_way_upd_reg( tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex7_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -2934,7 +2948,8 @@ generate begin : ex5_dir_way tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) ex5_dir_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -2958,7 +2973,8 @@ generate begin : ex6_dir_way tri_rlmreg_p #(.WIDTH(2 + `THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_dir_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv5_ex5_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2982,7 +2998,8 @@ generate begin : ex7_dir_way tri_regk #(.WIDTH(dirState-2), .INIT(0), .NEEDS_SRESET(1)) ex7_dir_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv6_ex6_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3006,7 +3023,8 @@ generate begin : stq3_way_val tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq3_way_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -3030,7 +3048,8 @@ generate begin : stq4_way_val tri_rlmreg_p #(.WIDTH(dirState-2), .INIT(0), .NEEDS_SRESET(1)) stq4_way_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3054,7 +3073,8 @@ generate begin : stq4_dir_way tri_rlmreg_p #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq4_dir_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3078,7 +3098,8 @@ generate begin : stq5_dir_way tri_regk #(.WIDTH(dirState), .INIT(0), .NEEDS_SRESET(1)) stq5_dir_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq4_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -3099,7 +3120,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq3_ex6_ldp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3117,7 +3139,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq3_ex6_ldp_err_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_ex7_ldp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3135,7 +3158,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_ex7_ldp_err_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_ex6_ldp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3153,7 +3177,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_ex6_ldp_err_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq3_stq5_stp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3171,7 +3196,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq3_stq5_stp_err_re tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_stq6_stp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3189,7 +3215,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_stq6_stp_err_re tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_stq5_stp_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3207,7 +3234,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_stq5_stp_err_re tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_clr_lck_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3226,7 +3254,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_clr_lck_way_reg tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3245,7 +3274,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_way_upd_reg( tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq5_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -3264,7 +3294,8 @@ tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq5_way_upd_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq6_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3283,7 +3314,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq6_way_upd_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq7_way_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3302,7 +3334,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq7_way_upd_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_rel_way_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3321,7 +3354,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_rel_way_clr_reg tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3340,7 +3374,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3358,7 +3393,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_cache_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mhit_cacc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3376,7 +3412,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mhit_cacc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3394,7 +3431,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3413,7 +3451,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3431,7 +3470,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_binv_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_binv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3449,7 +3489,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_binv_val_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -3467,7 +3508,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3485,7 +3527,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_ex4_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -3503,7 +3546,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3521,7 +3565,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lock_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3539,7 +3584,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lock_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3557,7 +3603,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_watch_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3575,7 +3622,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_watch_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3593,7 +3641,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_watch_set_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_larx_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3611,7 +3660,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_larx_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_watch_set_inval_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3629,7 +3679,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex7_watch_set_inval_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lose_watch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3647,7 +3698,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_lose_watch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xuop_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3665,7 +3717,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xuop_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xuop_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3683,7 +3736,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xuop_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv5_ex5_dir_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3701,7 +3755,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) binv5_ex5_dir_val_reg( tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_way_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3719,7 +3774,8 @@ tri_regk #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) ex5_way_hit_reg( tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3737,7 +3793,8 @@ tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) ex tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv3_ex3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3755,7 +3812,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1) tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3773,7 +3831,8 @@ tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) ex tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cr_watch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -3791,7 +3850,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cr_watch_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3809,7 +3869,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex4_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3827,7 +3888,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3845,7 +3907,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_stq4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3863,7 +3926,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_stq4_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_stq5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv2_ex2_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3881,7 +3945,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex3_stq5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv3_ex3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3899,7 +3964,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv3_ex3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3917,7 +3983,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3935,7 +4002,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_ex7_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3953,7 +4021,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_ex7_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3971,7 +4040,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3989,7 +4059,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq7_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4007,7 +4078,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex5_stq7_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_rest_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv3_ex3_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4025,7 +4097,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_ex4_ex6_rest_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cClass_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -4043,7 +4116,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex5_cClass_lock_set_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_cClass_thrd_watch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv4_ex4_stg_act), .force_t(func_slp_nsl_force), .d_mode(d_mode_dc), @@ -4061,7 +4135,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_cClass_thrd_watch_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_multihit_val_b_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4079,7 +4154,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_multihit_val_b_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex5_err_det_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4097,7 +4173,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex5_err_det_way_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_perr_lock_lost_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4115,7 +4192,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_perr_lock_lost_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_perr_watchlost_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4134,7 +4212,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_perr_watchlost_ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_perr_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4153,7 +4232,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_perr_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dc_perr_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4172,7 +4252,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dc_perr_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_perr_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4191,7 +4272,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dir_perr_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dc_perr_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4210,7 +4292,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dc_perr_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_way_perr_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4229,7 +4312,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_way_perr_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq2_congr_cl_m_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4248,7 +4332,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq2_congr_cl_m_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq3_set_rel_coll_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4267,7 +4352,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq3_set_rel_coll_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq4_set_rel_coll_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4286,7 +4372,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stq4_set_rel_coll_reg( tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) binv6_ex6_dir_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv5_ex5_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4305,7 +4392,8 @@ tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) binv6_ex6_dir_d tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) binv7_ex7_dir_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_binv6_ex6_stg_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -4324,7 +4412,8 @@ tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) binv7_ex7_dir_d tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) stq6_dir_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4343,7 +4432,8 @@ tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) stq6_dir_data_r tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) stq7_dir_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4362,7 +4452,8 @@ tri_rlmreg_p #(.WIDTH((dirState-1)), .INIT(0), .NEEDS_SRESET(1)) stq7_dir_data_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ci_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4381,7 +4472,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ci_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cen_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4400,7 +4492,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cen_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4418,7 +4511,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4436,7 +4530,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4455,7 +4550,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_dci_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4474,7 +4570,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_dci_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_dci_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4493,7 +4590,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_dci_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dci_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4512,7 +4610,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dci_val_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4531,7 +4630,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq2_thrd_id_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq3_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4550,7 +4650,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq3_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4569,7 +4670,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_thrd_id_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel2_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4588,7 +4690,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel2_thrd_id_reg( tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel3_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4607,7 +4710,8 @@ tri_regk #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel3_thrd_id_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_lock_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4626,7 +4730,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_lock_clr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_lock_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4645,7 +4750,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_lock_clr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_watch_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4664,7 +4770,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_watch_clr_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_watch_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4683,7 +4790,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_watch_clr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_store_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4702,7 +4810,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_store_val_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_store_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4721,7 +4830,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_store_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_l_fld_b1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4740,7 +4850,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_l_fld_b1_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_l_fld_b1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4759,7 +4870,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_l_fld_b1_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_l_fld_b1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4778,7 +4890,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_l_fld_b1_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_inval_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4797,7 +4910,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_inval_op_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_inval_op_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4816,7 +4930,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_inval_op_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_watch_clr_all_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4835,7 +4950,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_watch_clr_all_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_watch_clr_all_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4854,7 +4970,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stq3_watch_clr_all_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_watch_clr_all_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4873,7 +4990,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_watch_clr_all_reg( tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) stq2_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4892,7 +5010,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1) tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) stq3_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4911,7 +5030,8 @@ tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) st tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) stq4_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4930,7 +5050,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1) tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) stq5_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq4_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -4949,7 +5070,8 @@ tri_regk #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) st tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1)) stq6_congr_cl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq5_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4968,7 +5090,8 @@ tri_rlmreg_p #(.WIDTH((lwrCClassBit-uprCClassBit+1)), .INIT(0), .NEEDS_SRESET(1) tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4986,7 +5109,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5004,7 +5128,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5022,7 +5147,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel5_clr_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5040,7 +5166,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel5_clr_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_dir_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5058,7 +5185,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_dir_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_set_dir_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5076,7 +5204,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel4_set_dir_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_set_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5094,7 +5223,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_set_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_stg_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5113,7 +5243,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel3_set_stg_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_back_inv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5131,7 +5262,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_back_inv_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_back_inv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5149,7 +5281,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_back_inv_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5167,7 +5300,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5186,7 +5320,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_lock_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5204,7 +5339,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_lock_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_lock_pipe_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5222,7 +5358,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_lock_pipe_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5241,7 +5378,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_watch_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5260,7 +5398,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_watch_set_reg( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_watch_pipe_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_nsl_force), .d_mode(d_mode_dc), @@ -5278,7 +5417,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rel3_watch_pipe_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_dir_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5296,7 +5436,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_dir_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_upd_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5314,7 +5455,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_upd_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_rel3_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5332,7 +5474,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_rel3_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_rel4_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5350,7 +5493,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_rel4_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_lose_watch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5368,7 +5512,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_lose_watch_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_way_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5387,7 +5532,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_way_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq3_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5406,7 +5552,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq3_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5425,7 +5572,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq4_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5443,7 +5591,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_stq5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_stq4_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5461,7 +5610,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_stq4_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5480,7 +5630,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5499,7 +5650,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq2_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_ex6_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5517,7 +5669,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_ex6_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq2_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5535,7 +5688,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq3_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq4_ex5_cmp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5553,7 +5707,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_stq4_ex5_cmp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cClass_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5572,7 +5727,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cClass_lock_set_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_cClass_thrd_watch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(dcc_dir_stq3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5590,7 +5746,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_cClass_thrd_wa tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel4_all_watch_lost_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5608,7 +5765,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel4_all_watch_lost tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_evict_ovl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5627,7 +5785,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_evict_ov tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_multihit_val_b_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5646,7 +5805,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_multihit_val_b_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_err_det_way_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5665,7 +5825,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq4_err_det_way_reg tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_perr_lock_lost_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5684,7 +5845,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_perr_lock_lost_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_perr_watchlost_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5703,7 +5865,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stq4_perr_watchlost tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_perr_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5721,7 +5884,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_dir_perr_det_reg( tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq5_way_perr_inval_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5739,7 +5903,8 @@ tri_rlmreg_p #(.WIDTH(numWays), .INIT(0), .NEEDS_SRESET(1)) stq5_way_perr_inval_ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_dir_err_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5757,7 +5922,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_dir_err_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stp_perr_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5775,7 +5941,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stp_perr_flush_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stm_watchlost_state_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -5794,7 +5961,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stm_watchlost_state tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -5813,7 +5981,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_cpy_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -5832,7 +6001,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_cpy_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_stg_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -5851,7 +6021,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p0_wren_stg_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p1_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5870,7 +6041,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p1_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p1_wren_cpy_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5889,7 +6061,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) p1_wren_cpy_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5908,7 +6081,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5926,7 +6100,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_all_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5944,7 +6119,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) congr_cl_all_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_clfc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5963,7 +6139,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_clfc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lock_finval_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5982,7 +6159,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lock_finval_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) val_finval_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6001,7 +6179,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) val_finval_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) watch_finval_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6020,7 +6199,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) watch_finval_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dirmultihit_ldp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6039,7 +6219,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dirmultihit_ldp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dirmultihit_stp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6058,7 +6239,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_dirmultihit_stp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_cslc_xuop_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6077,7 +6259,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_cslc_xuop_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_cslc_binv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -6096,7 +6279,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_cslc_binv_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_inter_thrd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6115,7 +6299,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_inter_th tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_evict_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -6134,7 +6319,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_evict_va tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lost_watch_binv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_fgen.v b/dev/verilog/work/lq_fgen.v index 3e1fa91..7081eb2 100755 --- a/dev/verilog/work/lq_fgen.v +++ b/dev/verilog/work/lq_fgen.v @@ -164,7 +164,8 @@ module lq_fgen( lq_pc_err_dir_stp_multihit, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -329,16 +330,11 @@ output lq_pc_err_dir_ldp_multihit; output lq_pc_err_dir_stp_multihit; //pervasive - - inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -1131,7 +1127,8 @@ assign ex5_misalign_flush = ex5_misalign_flush_q; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_valid_resv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1149,7 +1146,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_valid_resv_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_prealign_int_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1167,7 +1165,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_prealign_int_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_flush_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1185,7 +1184,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_flush_2ucode_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_flush_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1203,7 +1203,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_flush_2ucode_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_dis_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1221,7 +1222,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_dis_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_dcbz_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1239,7 +1241,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_dcbz_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_misalign_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1257,7 +1260,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_misalign_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_ap_unavail_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1275,7 +1279,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_ap_unavail_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_fp_unavail_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1293,7 +1298,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_fp_unavail_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_spv_unavail_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1311,7 +1317,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_axu_spv_unavail_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_local_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1329,7 +1336,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_local_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_flush_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1347,7 +1355,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_flush_req_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_mchk_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1365,7 +1374,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_tlb_mchk_req_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_low_pri_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1383,7 +1393,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_low_pri_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_high_pri_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1401,7 +1412,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_high_pri_excp_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_exception_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1419,7 +1431,8 @@ tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex5_exception_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_dear_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1437,7 +1450,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_dear_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1455,7 +1469,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1473,7 +1488,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_multihit_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1491,7 +1507,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1509,7 +1526,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_derat_perr_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_excpt_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1527,7 +1545,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sfx_excpt_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sfx_excpt_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1545,7 +1564,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sfx_excpt_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_excpt_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1563,7 +1583,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sfx_excpt_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_priv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1581,7 +1602,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_priv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1599,7 +1621,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_priv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1617,7 +1640,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_priv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1635,7 +1659,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1653,7 +1678,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1671,7 +1697,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_illeg_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1689,7 +1716,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_illeg_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1707,7 +1735,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_prog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1725,7 +1754,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_prog_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dlock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1743,7 +1773,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dlock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dlock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1761,7 +1792,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dlock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dlock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1779,7 +1811,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_dlock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ilock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1797,7 +1830,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ilock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ilock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1815,7 +1849,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ilock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ilock_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1833,7 +1868,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ilock_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ehpriv_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1851,7 +1887,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ehpriv_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ehpriv_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1869,7 +1906,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ehpriv_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1887,7 +1925,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cache_acc_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1905,7 +1944,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ucode_val_reg( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex3_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1923,7 +1963,8 @@ tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_ucode tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_rcvd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1941,7 +1982,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_wNComp_rcvd_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_wNComp_excp_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1959,7 +2001,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_wNComp_excp_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dac_int_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1977,7 +2020,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dac_int_det_reg( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) perv_fir_rpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1995,7 +2039,8 @@ tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) perv_fir_rpt_reg( tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2013,7 +2058,8 @@ tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_val_reg tri_rlmreg_p #(.WIDTH(UCODEDEPTH), .INIT(0), .NEEDS_SRESET(1)) ucode_cnt_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2034,7 +2080,8 @@ generate begin : ucode_cnt_memAttr tri_rlmreg_p #(.WIDTH(9), .INIT(1), .NEEDS_SRESET(1)) ucode_cnt_memAttr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_ucode_cnt_set[ucodeEntry]), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_imq.v b/dev/verilog/work/lq_imq.v index 2416aea..b6e081a 100755 --- a/dev/verilog/work/lq_imq.v +++ b/dev/verilog/work/lq_imq.v @@ -1,4 +1,4 @@ -// © IBM Corp. 2020 +// © IBM Corp. 2022 // Licensed under the Apache License, Version 2.0 (the "License"), as modified by // the terms below; you may not use the files in this repository except in // compliance with the License as modified. @@ -86,7 +86,8 @@ module lq_imq( imq_arb_mmq_st_data, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -150,13 +151,10 @@ module lq_imq( inout vdd; - - inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -631,7 +629,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_request_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -650,7 +649,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_lq_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -669,7 +669,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH((`REAL_IFAR_WIDTH-4)), .INIT(0), .NEEDS_SRESET(1)) iu_lq_ra_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_lq_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -688,7 +689,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) iu_lq_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_lq_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -707,7 +709,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) iu_lq_userdef_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_lq_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -726,7 +729,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -745,7 +749,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_ttype_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -764,7 +769,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -783,7 +789,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -802,7 +809,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_u_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -821,7 +829,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_lpid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -840,7 +849,8 @@ module lq_imq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -859,7 +869,8 @@ module lq_imq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_ind_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -878,7 +889,8 @@ module lq_imq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_lbit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mm_lq_int_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -897,7 +909,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`IUQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -919,7 +932,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH - 4), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -944,7 +958,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -969,7 +984,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -994,7 +1010,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_usr_def_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1019,7 +1036,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1044,7 +1062,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iuq_entry_seq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_iuq_set_val[iuq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1066,7 +1085,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iuq_seq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1085,7 +1105,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) iuq_seq_rd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1104,7 +1125,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`MMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1126,7 +1148,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1151,7 +1174,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_ttype_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1176,7 +1200,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1201,7 +1226,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_usr_def_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1226,7 +1252,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1251,7 +1278,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_seq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1276,7 +1304,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_lpid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(entry_mmq_set_val[mmq]), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1298,7 +1327,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`MMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_ind_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1317,7 +1347,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`MMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1336,7 +1367,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(`MMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) mmq_entry_lbit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1355,7 +1387,8 @@ module lq_imq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmq_ret_token_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1374,7 +1407,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mmq_seq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -1393,7 +1427,8 @@ module lq_imq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mmq_seq_rd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_ldq.v b/dev/verilog/work/lq_ldq.v index 5af82dd..8ad9640 100755 --- a/dev/verilog/work/lq_ldq.v +++ b/dev/verilog/work/lq_ldq.v @@ -251,7 +251,8 @@ module lq_ldq( vcs, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -571,8 +572,8 @@ output [8:9] lq_pc_bo_diagout; inout vcs; inout vdd; inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -2899,7 +2900,8 @@ lq_ldq_rot rrotl( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -3212,7 +3214,8 @@ lq_ldq_relq relq( .vcs(vcs), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -3959,7 +3962,8 @@ assign lq_pc_pfetch_quiesce = lq_pc_pfetch_quiesce_q; tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3978,7 +3982,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3997,7 +4002,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lge_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lca_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4016,7 +4022,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_lca_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4035,7 +4042,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_ldq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4054,7 +4062,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_ldq_val_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4073,7 +4082,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_cTag_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4092,7 +4102,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_qw_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_crit_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4111,7 +4122,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_crit_qw_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4130,7 +4142,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel0_resp_l1_dump_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algebraic_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4149,7 +4162,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algebraic_sel_reg tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4168,7 +4182,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel1_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4187,7 +4202,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel2_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4206,7 +4222,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rot_sel3_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4227,7 +4244,8 @@ generate begin : iu_lq_cp_next_itag_tid tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) iu_lq_cp_next_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4249,7 +4267,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_n_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4268,7 +4287,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_n_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_resolved_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4287,7 +4307,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) odq_ldq_resolved_reg( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_report_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4306,7 +4327,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_repor tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_report_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4325,7 +4347,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) odq_ldq_report_tid_ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_lq_rvs_empty_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4343,7 +4366,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_lq_rvs_empty_reg tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_blk_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4362,7 +4386,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_blk_req_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_rviss_blk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4381,7 +4406,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_rviss_blk_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_collide_binv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4400,7 +4426,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_collide_binv_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_stq_rel1_blk_store_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4419,7 +4446,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_stq_rel1_blk_store_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldreq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4438,7 +4466,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ldreq_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldreq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4457,7 +4486,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldreq_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4476,7 +4506,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4495,7 +4526,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_pfetch_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_odq_ldreq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4514,7 +4546,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_odq_ldreq_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_streq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4533,7 +4566,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_streq_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_othreq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4552,7 +4586,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_othreq_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_reserved_taken_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4571,7 +4606,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_reserved_taken_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_resv_taken_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4589,7 +4625,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_resv_taken_restart_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_xu_quiesce_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4607,7 +4644,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_xu_quiesce_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ldq_quiesce_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4625,7 +4663,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_ldq_quiesce_r tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_stq_quiesce_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4643,7 +4682,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_stq_quiesce_r tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_pfetch_quiesce_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4661,7 +4701,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq_pc_pfetch_quiesc tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_mm_lmq_stq_empty_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4679,7 +4720,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_mm_lmq_stq_empty_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4697,7 +4739,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4716,7 +4759,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_full_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4735,7 +4779,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ld_gath_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4754,7 +4799,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ld_gath_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_full_qHit_held_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4773,7 +4819,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_full_qHit_held_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_resv_qHit_held_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4792,7 +4839,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_resv_qHit_held_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_oth_qHit_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4811,7 +4859,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_oth_qHit_clr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_set_hold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4830,7 +4879,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_set_hold_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4848,7 +4898,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ldq_restart_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_full_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4866,7 +4917,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_full_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4884,7 +4936,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ldq_hit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_full_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4902,7 +4955,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_full_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_full_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4920,7 +4974,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_full_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_qwhit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4938,7 +4993,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_lgq_qwhit_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_qwhit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4956,7 +5012,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_lgq_qwhit_reg( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4975,7 +5032,8 @@ tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_p_addr_ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4993,7 +5051,8 @@ tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex5_wimge_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_cmmt_perf_events_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5011,7 +5070,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_cmmt_perf_events_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_all_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5029,7 +5089,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_al tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5047,7 +5108,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldqe_set_va tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex6_ldqe_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5065,7 +5127,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex6_ldqe_pfetch tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex7_ldqe_pfetch_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5083,7 +5146,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex7_ldqe_pfetch tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldm_hit_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5102,7 +5166,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_ldm_hit_reg tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_hold_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5121,7 +5186,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_hold_tid_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES + 1), .INIT(2 ** (`LMQ_ENTRIES)), .NEEDS_SRESET(1)) fifo_ldq_req_nxt_ptr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5140,7 +5206,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES + 1), .INIT(2 ** (`LMQ_ENTRIES)), .NEEDS_SRES tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5159,7 +5226,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_va tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_pfetch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5180,7 +5248,8 @@ generate begin : fifo_ldq_req_tid tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fifo_ldq_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5204,7 +5273,8 @@ generate begin : fifo_ldq_req tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) fifo_ldq_req_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fifo_ldq_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5226,7 +5296,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5245,7 +5316,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_val_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_req_cmpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5264,7 +5336,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_req_cmpl_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_cntr_reset_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5283,7 +5356,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_cntr_reset tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resent_ecc_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5302,7 +5376,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resent_ecc tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_reset_cpl_rpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5323,7 +5398,8 @@ generate begin : ldqe_iTag tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_iTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_ldqe_act[ldq1]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5347,7 +5423,8 @@ generate begin : ldqe_thrd_id tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldqe_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_ldqe_act[ldq2]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5371,7 +5448,8 @@ generate begin : ldqe_wimge tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ldqe_wimge_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_ldqe_act[ldq3]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5393,7 +5471,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_byte_swap_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5412,7 +5491,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_byte_swap_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5430,7 +5510,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resv_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_pfetch_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5451,7 +5532,8 @@ generate begin : ldqe_op_size tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldqe_op_size_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq4]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5475,7 +5557,8 @@ generate begin : ldqe_tgpr tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldqe_tgpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq5]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5499,7 +5582,8 @@ generate begin : ldqe_usr_def tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_usr_def_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq6]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5523,7 +5607,8 @@ generate begin : ldqe_class_id tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_class_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq7]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5547,7 +5632,8 @@ generate begin : ldqe_perf_events tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_perf_events_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq7]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5571,7 +5657,8 @@ generate begin : ldqe_dvc tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldqe_dvc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldqe_ctrl_act[ldq8]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5595,7 +5682,8 @@ generate begin : ldqe_ttype tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ldqe_ttype_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq9]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5619,7 +5707,8 @@ generate begin : ldqe_dacrw tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_dacrw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_ldqe_act[ldq10]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5643,7 +5732,8 @@ generate begin : ldqe_p_addr tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldqe_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_ldqe_act[ldq11]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5665,7 +5755,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_mkill_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5684,7 +5775,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_mkill_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resolved_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5703,7 +5795,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_resolved_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5722,7 +5815,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_nFlush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5741,7 +5835,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_n tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_back_inv_np1Flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5762,7 +5857,8 @@ generate begin : ldqe_beat_cntr tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_beat_cntr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldqe_ctrl_act[ldq12]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5784,7 +5880,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dRel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5803,7 +5900,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dRel_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5822,7 +5920,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_l1_dump_re tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dGpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5841,7 +5940,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_dGpr_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_axu_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5860,7 +5960,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_axu_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_lock_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5879,7 +5980,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_lock_set_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_watch_set_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5898,7 +6000,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_watch_set_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5919,7 +6022,8 @@ generate begin : ldqe_state tri_rlmreg_p #(.WIDTH(7), .INIT(64), .NEEDS_SRESET(1)) ldqe_state_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5943,7 +6047,8 @@ generate begin : ldqe_sentRel_cntr tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldqe_sentRel_cntr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldqe_ctrl_act[ldq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5964,7 +6069,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_all_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5983,7 +6089,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_al tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6002,7 +6109,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_lgqe_set_va tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_valid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6023,7 +6131,8 @@ generate begin : lgqe_iTag tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_iTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_lgqe_act[lgq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6047,7 +6156,8 @@ generate begin : lgqe_ldTag tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_ldTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_lgqe_act[lgq0]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6071,7 +6181,8 @@ generate begin : lgqe_thrd_id tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lgqe_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_lgqe_act[lgq1]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6093,7 +6204,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_byte_swap_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6114,7 +6226,8 @@ generate begin : lgqe_op_size tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) lgqe_op_size_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_lgqe_act[lgq2]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6138,7 +6251,8 @@ generate begin : lgqe_tgpr tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) lgqe_tgpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_lgqe_act[lgq3]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6160,7 +6274,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_gpr_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6179,7 +6294,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_gpr_done_r tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_resolved_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6198,7 +6314,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_resolved_r tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_nFlush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6217,7 +6334,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_n tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_back_inv_np1Flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6238,7 +6356,8 @@ generate begin : lgqe_dacrw tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_dacrw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_lgqe_act[lgq4]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6262,7 +6381,8 @@ generate begin : lgqe_dvc tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lgqe_dvc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6286,7 +6406,8 @@ generate begin : lgqe_p_addr tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lgqe_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_lgqe_act[lgq6]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6308,7 +6429,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6327,7 +6449,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_algebraic_ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_axu_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex5_stg_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6348,7 +6471,8 @@ generate begin : lgqe_perf_events tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lgqe_perf_events_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex4_lgqe_act[lgq6]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6370,7 +6494,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_ecc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6388,7 +6513,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_ec tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_eccue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6406,7 +6532,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_upd_gpr_ec tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_need_cpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6425,7 +6552,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgqe_need_cpl_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rst_eccdet_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6444,7 +6572,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rst_eccdet tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beats_home_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6463,7 +6592,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beats_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_beats_home_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6482,7 +6612,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_beats_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_beats_home_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6501,7 +6632,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_beats_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_beats_home_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6520,7 +6652,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_beats_ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_entrySent_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6539,7 +6672,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_entryS tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_entrySent_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6558,7 +6692,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_entryS tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_entrySent_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6577,7 +6712,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_entryS tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_sentL1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6596,7 +6732,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_sentL1 tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_sentL1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6615,7 +6752,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_sentL1 tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel6_req_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6634,7 +6772,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel6_req_do tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel1_resp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6653,7 +6792,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel1_resp_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel2_resp_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6672,7 +6812,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_rel2_resp_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_inval_rel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6691,7 +6832,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_inval_rel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ecc_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6710,7 +6852,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ecc_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ue_det_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6728,7 +6871,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_err_ue_det_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6746,7 +6890,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6764,7 +6909,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6783,7 +6929,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l1_dump_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6802,7 +6949,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l1_dump_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6821,7 +6969,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l1_dump_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_clr_relq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6840,7 +6989,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_clr_relq_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_resp_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6858,7 +7008,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_resp_qw_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6877,7 +7028,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_cTag_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_opsize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6896,7 +7048,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_opsize_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_wimge_i_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6915,7 +7068,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_wimge_i_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_byte_swap_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6934,7 +7088,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_byte_swap_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_byte_swap_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6953,7 +7108,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_byte_swap_reg( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6972,7 +7128,8 @@ tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_p_ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dvcEn_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -6991,7 +7148,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dvcEn_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_lockSet_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7010,7 +7168,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_lockSet_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_watchSet_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7029,7 +7188,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_watchSet_reg( tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tGpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7048,7 +7208,8 @@ tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tGpr tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_axu_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7067,7 +7228,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_axu_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algEn_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7086,7 +7248,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_algEn_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_classID_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7105,7 +7268,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_classID_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7124,7 +7288,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_tid_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel1_val_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7143,7 +7308,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_tid_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dir_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7161,7 +7327,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_dir_tid_re tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_relDir_start_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7179,7 +7346,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_relDir_sta tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_set_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7197,7 +7365,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_set_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_set_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7216,7 +7385,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_set_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel4_set_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7235,7 +7405,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel4_set_val_reg( tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_cclass_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel1_val_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7254,7 +7425,8 @@ tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_cclass_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7273,7 +7445,8 @@ tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_cclass_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7292,7 +7465,8 @@ tri_rlmreg_p #(.WIDTH((57-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ldq tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_data_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7311,7 +7485,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_data_sel_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7330,7 +7505,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7349,7 +7525,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7368,7 +7545,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7387,7 +7565,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7406,7 +7585,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_l2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7425,7 +7605,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_l2_val tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7444,7 +7625,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet_ue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7462,7 +7644,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_eccdet tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_ecc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7480,7 +7663,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_ec tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_eccue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7498,7 +7682,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_upd_gpr_ec tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_need_cpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7517,7 +7702,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_need_cpl_r tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_sent_cpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7536,7 +7722,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_sent_cpl_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_gpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7555,7 +7742,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_gpr_val_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7574,7 +7762,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_upd_gp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7593,7 +7782,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_upd_gp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7612,7 +7802,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_upd_gp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7631,7 +7822,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel3_upd_gp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel3_drop_cpl_rpt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7650,7 +7842,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel3_drop_ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_l2_rel0_qHitBlk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7669,7 +7862,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_l2_rel0_qHitBlk_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lgq_rel1_gpr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7688,7 +7882,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lgq_rel1_gpr_val_reg( tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel0_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7707,7 +7902,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel0_upd_gp tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel1_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7726,7 +7922,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel1_upd_gp tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel2_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7745,7 +7942,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel2_upd_gp tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel3_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7764,7 +7962,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel3_upd_gp tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel4_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7783,7 +7982,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel4_upd_gp tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel5_upd_gpr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7802,7 +8002,8 @@ tri_rlmreg_p #(.WIDTH(`LGQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) lgq_rel5_upd_gp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_odq_cpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7821,7 +8022,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel4_odq_cp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_odq_cpl_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7840,7 +8042,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel5_odq_cp tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel_qHit_clr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7859,7 +8062,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel_qHit_cl tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_qHit_held_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7880,7 +8084,8 @@ generate begin : cpl_grpEntry_last_sel tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_grpEntry_last_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7902,7 +8107,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_group_last_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7921,7 +8127,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) cpl_group_last_sel_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_execute_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7940,7 +8147,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_execute_vld_ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) lq1_iu_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7959,7 +8167,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(1), .NEEDS_SRESET(1)) lq1_iu_itag_r tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_n_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7978,7 +8187,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_n_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_np1_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -7996,7 +8206,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_np1_flush_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_exception_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8014,7 +8225,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq1_iu_exception_val_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_dacrw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8032,7 +8244,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_dacrw_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_perf_events_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8050,7 +8263,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq1_iu_perf_events_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_larx_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8068,7 +8282,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_larx_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_binv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8086,7 +8301,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ldq_cpl_binv_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_cmmt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8104,7 +8320,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_cmmt_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_need_hole_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8122,7 +8339,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_need_hole_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_latency_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8140,7 +8358,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel_latency_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8158,7 +8377,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -8176,7 +8396,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_stg_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stg_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_ldq_relq.v b/dev/verilog/work/lq_ldq_relq.v index 4693d47..3d09841 100755 --- a/dev/verilog/work/lq_ldq_relq.v +++ b/dev/verilog/work/lq_ldq_relq.v @@ -97,7 +97,8 @@ module lq_ldq_relq( vcs, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -196,8 +197,8 @@ output [8:9] lq_pc_bo_diagout; inout vcs; inout vdd; inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -608,7 +609,8 @@ generate begin : relq .gnd(gnd), // CLOCK AND CLOCKCONTROL PORTS - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(ldq_rel0_arr_rd_act), .wr_act(ldq_rel2_arr_wren), .sg_0(sg_0), @@ -779,7 +781,8 @@ generate begin : ldqe_rel_datRet tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_datRet_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldqe_ctrl_act[ldq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -800,7 +803,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_beat_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -818,7 +822,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_beat_upd_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_beat_upd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -839,7 +844,8 @@ generate begin : ldqe_relAttempts tri_rlmreg_p #(.WIDTH(3), .INIT(7), .NEEDS_SRESET(1)) ldqe_relAttempts_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldqe_ctrl_act[ldq]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -860,7 +866,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_sent_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -878,7 +885,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arb_se tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -896,7 +904,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_val_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -914,7 +923,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_qw_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_thresh_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -932,7 +942,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_thresh_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ldq_rel0_arb_cTag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -953,7 +964,8 @@ generate begin : rel_grpEntry_last_sel tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_grpEntry_last_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -974,7 +986,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_group_last_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -992,7 +1005,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(8), .NEEDS_SRESET(1)) rel_group_last_sel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1010,7 +1024,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_sel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_rdat_sel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1028,7 +1043,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_rdat_sel_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_rdat_par_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1046,7 +1062,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel3_rdat_par_err_reg( tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_rdat_perr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1064,7 +1081,8 @@ tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ldqe_rel_rdat_p tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1082,7 +1100,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel1_arr_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_wren_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1100,7 +1119,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_wren_reg( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_waddr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1118,7 +1138,8 @@ tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) ldq_rel2_arr_waddr_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel0_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1136,7 +1157,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ldq_rel1_rdat_qw_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_relq_parity_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_ldq_rot.v b/dev/verilog/work/lq_ldq_rot.v index 850b3b8..928cf04 100755 --- a/dev/verilog/work/lq_ldq_rot.v +++ b/dev/verilog/work/lq_ldq_rot.v @@ -59,7 +59,8 @@ module lq_ldq_rot( ldq_rel2_dvc, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -110,16 +111,11 @@ output [0:127] ldq_rel2_rot_data; output [0:1] ldq_rel2_dvc; // Pervasive - - inout vdd; - - inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -418,7 +414,8 @@ assign ldq_rel2_dvc = {rel2_dvc1r_cmpr, rel2_dvc2r_cmpr}; tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) rel2_byte_mask_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -437,7 +434,8 @@ tri_rlmreg_p #(.WIDTH((2**`GPR_WIDTH_ENC)/8), .INIT(0), .NEEDS_SRESET(1)) rel2_b tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) rel2_rot_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ldq_rel1_stg_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -456,7 +454,8 @@ tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) rel2_rot_data_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc1_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -475,7 +474,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc1_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rel2_dvc2_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_lsq.v b/dev/verilog/work/lq_lsq.v index 7462e33..0a61e18 100755 --- a/dev/verilog/work/lq_lsq.v +++ b/dev/verilog/work/lq_lsq.v @@ -350,7 +350,8 @@ module lq_lsq( vcs, vdd, gnd, - nclk, + clk, + rst, sg_2, fce_2, func_sl_thold_2, @@ -850,19 +851,11 @@ module lq_lsq( output lq_pc_err_l2credit_overrun; // L2 Credits were Overrun // Pervasive - - inout vcs; - - inout vdd; - - inout gnd; - - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_2; input fce_2; input func_sl_thold_2; @@ -1429,7 +1422,8 @@ module lq_lsq( .gnd(gnd), // CLOCK AND CLOCKCONTROL PORTS - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(stq_ctl_stq1_stg_act), .wr_act(tiup), .sg_0(sg_0), @@ -1625,7 +1619,8 @@ module lq_lsq( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -1923,7 +1918,8 @@ module lq_lsq( .vcs(vdd), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2239,7 +2235,8 @@ module lq_lsq( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2307,7 +2304,8 @@ module lq_lsq( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2461,7 +2459,8 @@ module lq_lsq( // Pervasive .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0), .func_sl_thold_0_b(func_sl_thold_0_b), .func_sl_force(func_sl_force), @@ -2541,7 +2540,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_inv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2560,7 +2560,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2579,7 +2580,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ldq_odq_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2598,7 +2600,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ldq_odq_cline_chk_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2617,7 +2620,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2636,7 +2640,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2655,7 +2660,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex4_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2674,7 +2680,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex5_byte_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2693,7 +2700,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_p_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2712,7 +2720,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2731,7 +2740,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2749,7 +2759,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2767,7 +2778,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_thrd_id_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2786,7 +2798,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2805,7 +2818,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_algebraic_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2824,7 +2838,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_opsize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2843,7 +2858,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_opsize_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2862,7 +2878,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_dreq_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2881,7 +2898,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2900,7 +2918,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_ld_pop_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2919,7 +2938,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_st_pop_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2938,7 +2958,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_req_st_gather_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -2957,7 +2978,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2976,7 +2998,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_vld_stg1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2995,7 +3018,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_coming_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3014,7 +3038,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ditc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3033,7 +3058,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_crit_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3052,7 +3078,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_l1_dump_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3071,7 +3098,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ecc_err_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3090,7 +3118,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_reld_ecc_err_ue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3109,7 +3138,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3128,7 +3158,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3147,7 +3178,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit3_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3166,7 +3198,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_target_bit4_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3185,7 +3218,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mm_lq_lsu_lpidr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3204,7 +3238,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_dbell_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3223,7 +3258,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) l2_back_inv_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3242,7 +3278,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH((63-`CL_SIZE-(64-`REAL_IFAR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) rv1_back_inv_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(l2_back_inv_val_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3261,7 +3298,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) an_ac_req_spare_ctrl_a1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3280,7 +3318,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_core_tag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3299,7 +3338,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_qw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3318,7 +3358,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) an_ac_reld_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(an_ac_reld_data_vld_stg1_q), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3337,7 +3378,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(an_ac_back_inv_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3356,7 +3398,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_sync_ack_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3375,7 +3418,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_stcx_complete_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3394,7 +3438,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) an_ac_stcx_pass_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3413,7 +3458,8 @@ module lq_lsq( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_icbi_ack_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3432,7 +3478,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_icbi_ack_thread_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3451,7 +3498,8 @@ module lq_lsq( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), @@ -3473,7 +3521,8 @@ module lq_lsq( tri_rlmreg_p #(.INIT(0), .WIDTH(25), .NEEDS_SRESET(1)) abist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_abist_ena_dc), .thold_b(abst_sl_thold_0_b), .sg(sg_0), @@ -3511,7 +3560,8 @@ module lq_lsq( tri_plat #(.WIDTH(10)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_2, func_sl_thold_2, @@ -3539,7 +3589,8 @@ module lq_lsq( tri_plat #(.WIDTH(10)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({func_nsl_thold_1, func_sl_thold_1, @@ -3615,7 +3666,8 @@ module lq_lsq( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(abst_slat_thold_b), .dclk(abst_slat_d2clk), @@ -3645,7 +3697,8 @@ module lq_lsq( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(time_slat_thold_b), .dclk(time_slat_d2clk), @@ -3673,7 +3726,8 @@ module lq_lsq( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(repr_slat_thold_b), .dclk(repr_slat_d2clk), @@ -3701,7 +3755,8 @@ module lq_lsq( .vd(vdd), .gd(gnd), .delay_lclkr(delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force), .thold_b(func_slat_thold_b), .dclk(func_slat_d2clk), diff --git a/dev/verilog/work/lq_odq.v b/dev/verilog/work/lq_odq.v index 8b5f9ed..40cc17e 100755 --- a/dev/verilog/work/lq_odq.v +++ b/dev/verilog/work/lq_odq.v @@ -112,7 +112,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) lsq_perv_odq_events, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -254,19 +255,11 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) // Performance Events output [0:4+`THREADS-1] lsq_perv_odq_events; - // TODO: What else??? - // Pervasive - - inout vdd; - - inout gnd; - - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -1936,7 +1929,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1956,7 +1950,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1976,7 +1971,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1996,7 +1992,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2016,7 +2013,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2036,7 +2034,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2056,7 +2055,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2076,7 +2076,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2096,7 +2097,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2115,7 +2117,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2134,7 +2137,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2153,7 +2157,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2173,7 +2178,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2193,7 +2199,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2213,7 +2220,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2233,7 +2241,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2253,7 +2262,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2273,7 +2283,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2293,7 +2304,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2313,7 +2325,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2333,7 +2346,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2353,7 +2367,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2373,7 +2388,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2393,7 +2409,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2413,7 +2430,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2433,7 +2451,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2454,7 +2473,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2474,7 +2494,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2494,7 +2515,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2514,7 +2536,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2534,7 +2557,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2554,7 +2578,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2581,7 +2606,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2601,7 +2627,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2621,7 +2648,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2641,7 +2669,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2661,7 +2690,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2681,7 +2711,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2701,7 +2732,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2721,7 +2753,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2741,7 +2774,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2761,7 +2795,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2781,7 +2816,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2801,7 +2837,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2821,7 +2858,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2841,7 +2879,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2861,7 +2900,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2881,7 +2921,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2901,7 +2942,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2921,7 +2963,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2941,7 +2984,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2961,7 +3005,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2981,7 +3026,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3001,7 +3047,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3021,7 +3068,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3041,7 +3089,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3061,7 +3110,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3080,7 +3130,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3099,7 +3150,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3119,7 +3171,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3139,7 +3192,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3159,7 +3213,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3179,7 +3234,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3199,7 +3255,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3219,7 +3276,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3244,7 +3302,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3266,7 +3325,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_itag_latch ( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_lq_i0_completed[tid]), @@ -3289,7 +3349,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_itag_latch ( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_lq_i1_completed[tid]), @@ -3314,7 +3375,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3337,7 +3399,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_latch ( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3356,7 +3419,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_latch ( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3378,7 +3442,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3398,7 +3463,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3418,7 +3484,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3438,7 +3505,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3458,7 +3526,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3478,7 +3547,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3498,7 +3568,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3518,7 +3589,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3538,7 +3610,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3558,7 +3631,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3578,7 +3652,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3598,7 +3673,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3618,7 +3694,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3638,7 +3715,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3658,7 +3736,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3678,7 +3757,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3698,7 +3778,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3718,7 +3799,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3738,7 +3820,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3758,7 +3841,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3778,7 +3862,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3798,7 +3883,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3818,7 +3904,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3838,7 +3925,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3858,7 +3946,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3878,7 +3967,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3898,7 +3988,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3918,7 +4009,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3938,7 +4030,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3958,7 +4051,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3978,7 +4072,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -3998,7 +4093,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4018,7 +4114,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4038,7 +4135,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -4058,7 +4156,8 @@ module lq_odq( // 0 = ibm (Umbra), 1 = non-ibm, 2 = ibm (MPG) ( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_perv.v b/dev/verilog/work/lq_perv.v index 63fcebc..28f2199 100755 --- a/dev/verilog/work/lq_perv.v +++ b/dev/verilog/work/lq_perv.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -37,7 +37,8 @@ module lq_perv( vdd, gnd, - nclk, + clk, + rst, pc_lq_trace_bus_enable, pc_lq_debug_mux1_ctrls, pc_lq_debug_mux2_ctrls, @@ -129,8 +130,8 @@ module lq_perv( inout vdd; inout gnd; -(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) -input [0:`NCLK_WIDTH-1] nclk; +input clk; +input rst; // Pervasive Debug Control input pc_lq_trace_bus_enable; @@ -591,10 +592,11 @@ assign event_bus_out = perf_event_data_q; // Pervasive Clock Control Logic // XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX -tri_plat #(.WIDTH(18)) perv_3to2_reg( +tri_plat#(.WIDTH(18)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({pc_lq_func_sl_thold_3, pc_lq_func_slp_sl_thold_3, @@ -663,10 +665,11 @@ assign mpw1_dc_b = mpw1_dc_b_int; assign mpw2_dc_b = mpw2_dc_b_int[0]; -tri_plat #(.WIDTH(3)) perv_2to1_reg( +tri_plat#(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({gptr_sl_thold_2, func_slp_sl_thold_2_int, @@ -676,10 +679,11 @@ tri_plat #(.WIDTH(3)) perv_2to1_reg( sg_1}) ); -tri_plat #(.WIDTH(3)) perv_1to0_reg( +tri_plat#(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(pc_lq_ccflush_dc), .din({gptr_sl_thold_1, func_slp_sl_thold_1, @@ -702,7 +706,8 @@ tri_lcbcntl_mac perv_lcbctrl_0( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_siv[3]), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -719,7 +724,8 @@ tri_lcbcntl_mac perv_lcbctrl_1( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_siv[4]), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -736,7 +742,8 @@ tri_lcbcntl_array_mac perv_lcbctrl_g6t_0( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_siv[0]), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -753,7 +760,8 @@ tri_lcbcntl_array_mac perv_lcbctrl_g8t_0( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_siv[1]), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -770,7 +778,8 @@ tri_lcbcntl_array_mac perv_lcbctrl_cam_0( .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_siv[2]), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -789,7 +798,8 @@ tri_lcbcntl_array_mac perv_lcbctrl_cam_0( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_trace_bus_enable_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -807,7 +817,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_trace_bus_enable_reg( tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux1_ctrls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -825,7 +836,8 @@ tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux1_ctrls_re tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux2_ctrls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -843,7 +855,8 @@ tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(1)) pc_lq_debug_mux2_ctrls_re tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_mode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -861,7 +874,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_mode_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_tid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -879,7 +893,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pc_lq_instr_trace_t tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_debug_data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -897,7 +912,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_debug_data_out_re tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_coretrace_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -915,7 +931,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux1_coretrace_out_reg( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_debug_data_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -933,7 +950,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_debug_data_out_re tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_coretrace_out_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_trace_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -951,7 +969,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lq_mux2_coretrace_out_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -969,7 +988,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -987,7 +1007,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_event_bus_enable_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -1005,7 +1026,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_lq_event_bus_enable_reg( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) perf_event_en_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_event_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -1023,7 +1045,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) perf_event_en_reg( tri_rlmreg_p #(.WIDTH((4*`THREADS)), .INIT(0), .NEEDS_SRESET(1)) perf_event_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_event_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), @@ -1041,7 +1064,8 @@ tri_rlmreg_p #(.WIDTH((4*`THREADS)), .INIT(0), .NEEDS_SRESET(1)) perf_event_data tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pc_lq_event_count_mode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_lq_event_bus_enable_q), .force_t(func_slp_sl_force), .d_mode(d_mode_dc_int[0]), diff --git a/dev/verilog/work/lq_pfetch.v b/dev/verilog/work/lq_pfetch.v index 9ce37df..f738fa5 100755 --- a/dev/verilog/work/lq_pfetch.v +++ b/dev/verilog/work/lq_pfetch.v @@ -84,7 +84,8 @@ module lq_pfetch( vdd, gnd, vcs, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -188,16 +189,11 @@ module lq_pfetch( inout vcs; - - inout vdd; - - inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -648,7 +644,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_i0_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -667,7 +664,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i0_isLoad_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -686,7 +684,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i0_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -705,7 +704,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rv_i0_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -724,7 +724,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) rv_i0_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -743,7 +744,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv_i1_vld_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -762,7 +764,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i1_isLoad_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -781,7 +784,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) rv_i1_rte_lq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -800,7 +804,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) rv_i1_ifar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -819,7 +824,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) rv_i1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -838,7 +844,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -857,7 +864,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -876,7 +884,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -895,7 +904,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush4_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -914,7 +924,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) inj_pfetch_parity_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -970,7 +981,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) odq_resolved_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -989,7 +1001,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) odq_report_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1008,7 +1021,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) odq_report_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1060,7 +1074,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pf_iar_tbl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf_itag_tbl_act[i]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1079,7 +1094,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pf_itag_tbl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf_itag_tbl_act[i]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1098,7 +1114,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pf_tid_tbl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf_itag_tbl_act[i]), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1118,7 +1135,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`LDSTQ_ENTRIES), .INIT(0)) latch_pf_iar_tbl_val( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1176,7 +1194,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_iar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1195,7 +1214,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex7_iar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1214,7 +1234,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex8_iar_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1233,7 +1254,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_thrd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1252,7 +1274,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_thrd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1271,7 +1294,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex8_thrd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1290,7 +1314,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex6_eff_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1309,7 +1334,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex7_eff_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1328,7 +1354,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) ex8_eff_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1347,7 +1374,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex6_req_val_4pf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1368,7 +1396,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex7_req_val_4pf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1387,7 +1416,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_req_val_4pf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1406,7 +1436,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) pf1_req_val_4pf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1427,7 +1458,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) pf2_req_val_4pf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1448,7 +1480,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex6_loadmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex6_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1467,7 +1500,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex7_loadmiss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex7_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1494,7 +1528,8 @@ module lq_pfetch( .vdd(vdd), .vcs(vcs), // CLOCK and CLOCKCONTROL ports - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(rpt_rd_act[0:1]), .wr_act(rpt_wen[0:1]), .sg_0(sg_0), @@ -1607,7 +1642,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) byp_rpt_ary_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1625,7 +1661,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) byp1_rpt_ary_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1644,7 +1681,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(70), .INIT(0), .NEEDS_SRESET(1)) rpt_byp_dat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(byp_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1662,7 +1700,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(70), .INIT(0), .NEEDS_SRESET(1)) rpt_byp_dat1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(byp1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1716,7 +1755,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) ex8_last_dat_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1735,7 +1775,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) ex8_stride_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1754,7 +1795,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_pf_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1773,7 +1815,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_burst_cnt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1792,7 +1835,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_dup_flag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1811,7 +1855,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex8_pf_hits_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1830,7 +1875,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex8_rpt_pe_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1848,7 +1894,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex8_pfetch_pe_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ex8_pf_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1908,7 +1955,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf1_new_stride( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1927,7 +1975,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf1_rpt_stride( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1946,7 +1995,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf1_data_ea( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1965,7 +2015,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0)) latch_pf1_iar( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1984,7 +2035,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf1_pf_state( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2003,7 +2055,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf1_burst_cnt( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2022,7 +2075,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_dup_flag( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2041,7 +2095,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf1_hits( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2062,7 +2117,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pf1_rpt_pe_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2078,7 +2134,8 @@ module lq_pfetch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf1_thrd( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2097,7 +2154,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_same_cline( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2116,7 +2174,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf1_stride_too_small( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf1_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2175,7 +2234,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf2_gen_pfetch( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2194,7 +2254,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0)) latch_pf2_rpt_stride( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2213,7 +2274,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf2_data_ea( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2232,7 +2294,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PF_IFAR_WIDTH), .INIT(0)) latch_pf2_iar( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2251,7 +2314,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf2_pf_state( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2270,7 +2334,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) latch_pf2_burst_cnt( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2289,7 +2354,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf2_hits( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2310,7 +2376,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pf2_rpt_pe_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2326,7 +2393,8 @@ module lq_pfetch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf2_thrd( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2409,7 +2477,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) latch_rpt_lru( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_valid), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2474,7 +2543,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) pfq_stride_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2493,7 +2563,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0), .NEEDS_SRESET(1)) pfq_data_ea_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2512,7 +2583,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) pfq_thrd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2531,7 +2603,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pfq_dscr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2551,7 +2624,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE), .INIT(1)) latch_pfq_dup_flag( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf2_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2572,7 +2646,8 @@ module lq_pfetch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pfq_full_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2591,7 +2666,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pfq_wrt_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2682,7 +2758,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(5), .INIT(1)) latch_pf_state( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2706,7 +2783,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) latch_pf_count( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2732,7 +2810,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`PFETCH_Q_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) pfq_rd_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2787,7 +2866,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(22), .INIT(0), .NEEDS_SRESET(1)) pf3_stride_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf3_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2821,7 +2901,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH((59-(64-(2**`GPR_WIDTH_ENC))+1)), .INIT(0)) latch_pf3_req_addr( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf3_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2842,7 +2923,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) latch_pf3_req_val( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf3_act), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -2863,7 +2945,8 @@ module lq_pfetch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) latch_pf3_thrd( - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pf3_act), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_spr.v b/dev/verilog/work/lq_spr.v index f521fa6..3639aa1 100755 --- a/dev/verilog/work/lq_spr.v +++ b/dev/verilog/work/lq_spr.v @@ -36,8 +36,8 @@ module lq_spr parameter a2mode = 1 )( - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input d_mode_dc, input delay_lclkr_dc, @@ -273,7 +273,8 @@ assign spr_dbcr2_dvc1m = tspr_cspr_dbcr2_dvc1m; assign spr_dbcr2_dvc2m = tspr_cspr_dbcr2_dvc2m; lq_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_cspr( - .nclk(nclk), + .clk(clk), + .rst(rst), .d_mode_dc(d_mode_dc), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), @@ -377,7 +378,8 @@ generate begin : thread genvar t; for (t=0; t<`THREADS; t=t+1) begin : thread lq_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) lq_spr_tspr( - .nclk(nclk), + .clk(clk), + .rst(rst), .d_mode_dc(d_mode_dc), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), @@ -439,7 +441,8 @@ generate begin : thread endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -457,7 +460,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_in_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_act_in), @@ -475,7 +479,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_in_latch( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_act_in), @@ -493,7 +498,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_in_latch( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_act_in), @@ -511,7 +517,8 @@ tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_in_latch( ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_act_in), @@ -529,7 +536,8 @@ tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_in_l ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -547,7 +555,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_in_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -565,7 +574,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_out_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_val_in_q), @@ -583,7 +593,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_out_latch( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_val_in_q), @@ -601,7 +612,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_out_latch( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_val_in_q), @@ -619,7 +631,8 @@ tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_out_latch( ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(slowspr_val_in_q), @@ -637,7 +650,8 @@ tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_out_ ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -655,7 +669,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_out_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), diff --git a/dev/verilog/work/lq_spr_cspr.v b/dev/verilog/work/lq_spr_cspr.v index fed26d2..1e5bf12 100755 --- a/dev/verilog/work/lq_spr_cspr.v +++ b/dev/verilog/work/lq_spr_cspr.v @@ -37,7 +37,8 @@ module lq_spr_cspr )( (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input d_mode_dc, input delay_lclkr_dc, @@ -864,7 +865,8 @@ assign cspr_tspr_msr_gs = msr_gs_q; generate if (a2mode == 1) begin : dac1_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dac1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -884,7 +886,8 @@ endgenerate generate if (a2mode == 1) begin : dac2_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dac2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -902,7 +905,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac3_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dac3_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -915,7 +919,8 @@ endgenerate .dout(dac3_q) ); tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dac4_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dac4_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -930,7 +935,8 @@ endgenerate generate if (a2mode == 1) begin : dvc1_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dvc1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -950,7 +956,8 @@ endgenerate generate if (a2mode == 1) begin : dvc2_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dvc2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -968,7 +975,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lesr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(lesr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -981,7 +989,8 @@ endgenerate .dout(lesr1_q) ); tri_ser_rlmreg_p #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(1)) lesr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(lesr2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -995,7 +1004,8 @@ endgenerate ); //wtf set dfwd=1 tri_ser_rlmreg_p #(.WIDTH(11), .INIT(1848), .NEEDS_SRESET(1)) lsucr0_latch( tri_ser_rlmreg_p #(.WIDTH(11), .INIT(1852), .NEEDS_SRESET(1)) lsucr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(lsucr0_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -1008,7 +1018,8 @@ endgenerate .dout(lsucr0_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) pesr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(pesr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -1021,7 +1032,8 @@ endgenerate .dout(pesr_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xucr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xucr2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -1034,7 +1046,8 @@ endgenerate .dout(xucr2_q) ); tri_ser_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) xudbg0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xudbg0_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -1051,7 +1064,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xudbg0_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1069,7 +1083,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xudbg0_done_reg( // Latch Instances tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1087,7 +1102,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( ); tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac12m_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1105,7 +1121,8 @@ tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac12m_latch( ); tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac34m_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1123,7 +1140,8 @@ tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_dac34m_latch( ); tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_load_dac_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1141,7 +1159,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_load_dac_latch( ); tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_store_dac_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1159,7 +1178,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_is_any_store_dac_latch( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_dacrw_cmpr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), @@ -1177,7 +1197,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_dacrw_cmpr_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1195,7 +1216,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1213,7 +1235,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1234,7 +1257,8 @@ generate begin : dbcr0_dac1 for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac1 tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1258,7 +1282,8 @@ generate begin : dbcr0_dac2 for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac2 tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1282,7 +1307,8 @@ generate begin : dbcr0_dac3 for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac3 tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1306,7 +1332,8 @@ generate begin : dbcr0_dac4 for (tid = 0; tid <= `THREADS - 1; tid = tid + 1) begin : dbcr0_dac4 tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) dbcr0_dac4_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1327,7 +1354,8 @@ end endgenerate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc1m_on_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1345,7 +1373,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc1m_on_latc ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc2m_on_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1363,7 +1392,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbcr2_dvc2m_on_latc ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_ds_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1381,7 +1411,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_ds_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_pr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1399,7 +1430,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_pr_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_gs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1419,7 +1451,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_gs_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_data_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1437,7 +1470,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_data_val_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc1_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1455,7 +1489,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc1_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc2_act_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -1473,7 +1508,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dvc2_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xudbg0_inprog_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_spr_tspr.v b/dev/verilog/work/lq_spr_tspr.v index c969f3f..c44178e 100755 --- a/dev/verilog/work/lq_spr_tspr.v +++ b/dev/verilog/work/lq_spr_tspr.v @@ -37,7 +37,8 @@ module lq_spr_tspr )( (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input d_mode_dc, input delay_lclkr_dc, @@ -470,7 +471,8 @@ assign spr_eplc_wr = eplc_we_q; generate if (a2mode == 1) begin : acop_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) acop_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(acop_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -490,7 +492,8 @@ endgenerate generate if (a2mode == 1) begin : dbcr2_latch_gen tri_ser_rlmreg_p #(.WIDTH(29), .INIT(0), .NEEDS_SRESET(1)) dbcr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dbcr2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -508,7 +511,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) dbcr3_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dbcr3_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -521,7 +525,8 @@ endgenerate .dout(dbcr3_q) ); tri_ser_rlmreg_p #(.WIDTH(6), .INIT(32), .NEEDS_SRESET(1)) dscr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dscr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -536,7 +541,8 @@ endgenerate generate if (hvmode == 1) begin : eplc_latch_gen tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) eplc_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(eplc_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -556,7 +562,8 @@ endgenerate generate if (hvmode == 1) begin : epsc_latch_gen tri_ser_rlmreg_p #(.WIDTH(25), .INIT(0), .NEEDS_SRESET(1)) epsc_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(epsc_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -576,7 +583,8 @@ endgenerate generate if (hvmode == 1) begin : hacop_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) hacop_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(hacop_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc), @@ -599,7 +607,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eplc_we_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -618,7 +627,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) eplc_we_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) epsc_we_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), diff --git a/dev/verilog/work/lq_stq.v b/dev/verilog/work/lq_stq.v index a6d0352..f85d159 100755 --- a/dev/verilog/work/lq_stq.v +++ b/dev/verilog/work/lq_stq.v @@ -255,7 +255,8 @@ module lq_stq( stq_arb_release_tid, vdd, gnd, - nclk, + clk, + rst, sg_0, func_sl_thold_0_b, func_sl_force, @@ -545,13 +546,10 @@ module lq_stq( inout vdd; - - inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_0; input func_sl_thold_0_b; input func_sl_force; @@ -3527,7 +3525,8 @@ module lq_stq( //------------------------------------------------------------------------------ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3545,7 +3544,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_ld_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3563,7 +3563,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv_lq_ld_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_dir_rd_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3581,7 +3582,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_dir_rd_val_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv0_cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3599,7 +3601,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv0_cp_flush_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3617,7 +3620,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_cp_flush_latch( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3635,7 +3639,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3653,7 +3658,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i0_flushed_latch( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rv1_i0_act), @@ -3671,7 +3677,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i0_itag_l ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3689,7 +3696,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3707,7 +3715,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_i1_flushed_latch( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rv1_i1_act), @@ -3725,7 +3734,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex0_i1_itag_l ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3743,7 +3753,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3761,7 +3772,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i0_flushed_latch( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_i0_act), @@ -3779,7 +3791,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i0_itag_l ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3797,7 +3810,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_vld_latch( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3815,7 +3829,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_i1_flushed_latch( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_i1_act), @@ -3833,7 +3848,8 @@ tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_i1_itag_l ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stqe_alloc_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3851,7 +3867,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRES ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_alloc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3869,7 +3886,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_alloc_latc ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_addr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3887,7 +3905,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_addr_val_l ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_fwd_addr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3905,7 +3924,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_fwd_addr_v ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3923,7 +3943,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_val_l ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_nxt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3941,7 +3962,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_data_nxt_l ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_illeg_lswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3959,7 +3981,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_illeg_lswx ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_strg_noop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3977,7 +4000,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_strg_noop_ ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ready_sent_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -3995,7 +4019,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ready_sent ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_odq_resolved_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4013,7 +4038,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_odq_resolv ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_compl_rcvd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4031,7 +4057,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_compl_rcvd ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_have_cp_next_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4049,7 +4076,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_have_cp_ne ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stqe_need_ready_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stqe_need_ready_act), @@ -4067,7 +4095,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRES ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4085,7 +4114,8 @@ tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_flushed_la ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_ack_rcvd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4108,7 +4138,8 @@ generate begin : stqe_lmqhit_latch_gen tri_rlmreg_p #(.WIDTH(`LMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stqe_lmqhit_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4134,7 +4165,8 @@ generate begin : stqe_need_ext_ack_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_need_ext_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4160,7 +4192,8 @@ generate for (i = 0; i <= `STQ_ENTRIES - 1; i = i + 1) begin : stqe_blk_loads_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_blk_loads_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4187,7 +4220,8 @@ generate begin : stqe_all_thrd_chk_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_all_thrd_chk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4215,7 +4249,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) stqe_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stqe_itag_act[i]), @@ -4241,7 +4276,8 @@ generate begin : stqe_addr_latch_gen tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) stqe_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4267,7 +4303,8 @@ generate begin : stqe_rotcmp_latch_gen tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stqe_rotcmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_addr_act[i]), @@ -4293,7 +4330,8 @@ generate begin : stqe_cline_chk_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_cline_chk_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4319,7 +4357,8 @@ generate begin : stqe_ttype_latch_gen tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) stqe_ttype_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4345,7 +4384,8 @@ generate begin : stqe_byte_en_latch_gen tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stqe_byte_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_addr_act[i]), @@ -4371,7 +4411,8 @@ generate begin : stqe_wimge_latch_gen tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) stqe_wimge_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4397,7 +4438,8 @@ generate begin : stqe_byte_swap_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_byte_swap_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4423,7 +4465,8 @@ generate begin : stqe_opsize_latch_gen tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) stqe_opsize_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4449,7 +4492,8 @@ generate begin : stqe_axu_val_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_axu_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4475,7 +4519,8 @@ generate begin : stqe_epid_val_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_epid_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4501,7 +4546,8 @@ generate begin : stqe_usr_def_latch_gen tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stqe_usr_def_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4527,7 +4573,8 @@ generate begin : stqe_is_store_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_store_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4553,7 +4600,8 @@ generate begin : stqe_is_sync_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_sync_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4579,7 +4627,8 @@ generate begin : stqe_is_resv_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_resv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4605,7 +4654,8 @@ generate begin : stqe_is_icswxr_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_icswxr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4631,7 +4681,8 @@ generate begin : stqe_is_icbi_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_icbi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4657,7 +4708,8 @@ generate begin : stqe_is_inval_op_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_is_inval_op_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4683,7 +4735,8 @@ generate begin : stqe_dreq_val_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_dreq_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4709,7 +4762,8 @@ generate begin : stqe_has_data_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_has_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4735,7 +4789,8 @@ generate begin : stqe_send_l2_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_send_l2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4761,7 +4816,8 @@ generate begin : stqe_lock_clr_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_lock_clr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4787,7 +4843,8 @@ generate begin : stqe_watch_clr_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_watch_clr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_addr_act[i]), @@ -4813,7 +4870,8 @@ generate begin : stqe_l_fld_latch_gen tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_l_fld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4839,7 +4897,8 @@ generate begin : stqe_thrd_id_latch_gen tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stqe_thrd_id_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stqe_itag_act[i]), @@ -4865,7 +4924,8 @@ generate begin : stqe_tgpr_latch_gen tri_rlmreg_p #(.WIDTH(AXU_TARGET_ENC), .INIT(0), .NEEDS_SRESET(1)) stqe_tgpr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4891,7 +4951,8 @@ generate begin : stqe_dvc_en_latch_gen tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_dvc_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4917,7 +4978,8 @@ generate begin : stqe_dacrw_latch_gen tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stqe_dacrw_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex5_addr_act[i]), @@ -4943,7 +5005,8 @@ generate begin : stqe_dvcr_cmpr_latch_gen tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) stqe_dvcr_cmpr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4969,7 +5032,8 @@ generate begin : stqe_qHit_held_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_qHit_held_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -4995,7 +5059,8 @@ generate begin : stqe_held_early_clr_latch_gen tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) stqe_held_early_clr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5021,7 +5086,8 @@ generate begin : stqe_data1_latch_gen tri_rlmreg_p #(.WIDTH(`STQ_DATA_SIZE), .INIT(0), .NEEDS_SRESET(1)) stqe_data1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stqe_data_act[i]), @@ -5042,7 +5108,8 @@ generate endgenerate tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_data_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_fxu1_val), @@ -5060,7 +5127,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_axu_data_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_axu_val), @@ -5078,7 +5146,8 @@ generate ); tri_rlmreg_p #(.WIDTH((`STQ_DATA_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex4_fu_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_axu_val), @@ -5096,7 +5165,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5114,7 +5184,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_next_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5137,7 +5208,8 @@ generate for (i = 0; i <= `THREADS-1; i = i + 1) begin : cp_next_itag_latch_gen tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_next_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_lq_cp_next_val[i]), @@ -5158,7 +5230,8 @@ generate endgenerate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5180,7 +5253,8 @@ generate for (i = 0; i <= `THREADS-1; i = i + 1) begin : cp_i0_completed_itag_latch_gen tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_i0_completed_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_lq_i0_completed[i]), @@ -5201,7 +5275,8 @@ generate endgenerate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_i1_completed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5224,7 +5299,8 @@ generate begin : cp_i1_completed_itag_latch_gen tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) cp_I1_completed_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_lq_i1_completed[i]), @@ -5247,7 +5323,8 @@ generate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq_cpl_need_hold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .force_t(func_sl_force), .d_mode(d_mode_dc), @@ -5263,7 +5340,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_lq_icbi_complete_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5281,7 +5359,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_icbi_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5299,7 +5378,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) l2_icbi_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5317,7 +5397,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rv1_binv_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5335,7 +5416,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_binv_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5353,7 +5435,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_binv_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5371,7 +5454,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_binv_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5389,7 +5473,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_binv_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5407,7 +5492,8 @@ generate ); tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) rv1_binv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(l2_back_inv_val), @@ -5425,7 +5511,8 @@ generate ); tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex0_binv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rv1_binv_val_q), @@ -5443,7 +5530,8 @@ generate ); tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex1_binv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_binv_val_q), @@ -5461,7 +5549,8 @@ generate ); tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex2_binv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_binv_val_q), @@ -5479,7 +5568,8 @@ generate ); tri_rlmreg_p #(.WIDTH(((63-`CL_SIZE)-(64-(`DC_SIZE-3))+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_binv_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_binv_val_q), @@ -5497,7 +5587,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_binv_blk_cclass_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5515,7 +5606,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_ici_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq1_cmmt_act), @@ -5533,7 +5625,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_xucr0_cul_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5551,7 +5644,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_reject_dci_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5569,7 +5663,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_reject_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5587,7 +5682,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_dci_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq1_cmmt_act), @@ -5605,7 +5701,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_dci_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5623,7 +5720,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_dci_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5641,7 +5739,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_dci_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5659,7 +5758,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5677,7 +5777,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5695,7 +5796,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5713,7 +5815,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5731,7 +5834,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5749,7 +5853,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_flushed_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5767,7 +5872,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(2 ** (`STQ_ENTRIES - 1)), .NEEDS_SRESET(1)) stq1_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq1_cmmt_act), @@ -5785,7 +5891,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq1_cmmt_act), @@ -5803,7 +5910,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq2_cmmt_val_q), @@ -5821,7 +5929,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq3_cmmt_val_q), @@ -5839,7 +5948,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq4_cmmt_val_q), @@ -5857,7 +5967,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq5_cmmt_val_q), @@ -5875,7 +5986,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq6_cmmt_val_q), @@ -5893,7 +6005,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5911,7 +6024,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5929,7 +6043,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5947,7 +6062,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq5_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5965,7 +6081,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -5983,7 +6100,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_cmmt_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -6001,7 +6119,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_v_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6019,7 +6138,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_sync_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6036,7 +6156,8 @@ generate .dout(ext_ack_queue_sync_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_stcx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6053,7 +6174,8 @@ generate .dout(ext_ack_queue_stcx_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_icswxr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6078,7 +6200,8 @@ generate begin : ext_ack_queue_itag_latch_gen tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6104,7 +6227,8 @@ generate begin : ext_ack_queue_cr_wa_latch_gen tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6130,7 +6254,8 @@ generate begin : ext_ack_queue_dacrw_det_latch_gen tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_dacrw_det_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6151,7 +6276,8 @@ generate endgenerate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ext_ack_queue_dacrw_rpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6169,7 +6295,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq2_mftgpr_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -6187,7 +6314,8 @@ generate ); tri_rlmreg_p #(.WIDTH(3), .INIT(6), .NEEDS_SRESET(1)) stq2_rtry_cnt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq2_rtry_cnt_act), @@ -6205,7 +6333,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stq_restart_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6223,7 +6352,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_stq_restart_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6241,7 +6371,8 @@ generate ); tri_rlmreg_p #(.WIDTH((`STQ_FWD_ENTRIES-1)), .INIT(0), .NEEDS_SRESET(1)) stq_fwd_pri_mask_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_act), @@ -6259,7 +6390,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_fwd_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6277,7 +6409,8 @@ generate ); tri_rlmreg_p #(.WIDTH((`STQ_DATA_SIZE)), .INIT(0), .NEEDS_SRESET(1)) ex5_fwd_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ldreq_valid), @@ -6295,7 +6428,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_set_stq_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6313,7 +6447,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_set_stq_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6331,7 +6466,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_ldreq_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6349,7 +6485,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_pfetch_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6367,7 +6504,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_streq_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6385,7 +6523,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_streq_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6403,7 +6542,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_wchkall_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6421,7 +6561,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) hwsync_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6439,7 +6580,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) lwsync_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6457,7 +6599,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) icswxr_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6475,7 +6618,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) icswxr_ack_dly1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6493,7 +6637,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) local_instr_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6511,7 +6656,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) resv_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6529,7 +6675,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stcx_pass_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6547,7 +6694,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icbi_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6565,7 +6713,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icbi_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6583,7 +6732,8 @@ generate ); tri_rlmreg_p #(.WIDTH((57-RI+1)), .INIT(0), .NEEDS_SRESET(1)) icbi_addr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq2_cmmt_val_q), @@ -6601,7 +6751,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ici_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6619,7 +6770,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) credit_free_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6637,7 +6789,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex4_fwd_agecmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6655,7 +6808,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_req_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6673,7 +6827,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_req_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6691,7 +6846,8 @@ generate ); tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) ex4_req_byte_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_req_act), @@ -6709,7 +6865,8 @@ generate ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_req_p_addr_l_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_req_act), @@ -6727,7 +6884,8 @@ generate ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_req_opsize_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_req_act), @@ -6745,7 +6903,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_req_algebraic_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_req_act), @@ -6763,7 +6922,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_req_thrd_id_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6781,7 +6941,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_req_thrd_id_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_req_act), @@ -6799,7 +6960,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_req_thrd_id_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6817,7 +6979,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) thrd_held_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6835,7 +6998,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv0_cr_hole_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6853,7 +7017,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rv1_cr_hole_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6871,7 +7036,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_cr_hole_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6889,7 +7055,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cr_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6907,7 +7074,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) sync_ack_save_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6925,7 +7093,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) cr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6943,7 +7112,8 @@ generate ); tri_rlmreg_p #(.WIDTH((`CR_POOL_ENC+`THREADS_POOL_ENC-1+1)), .INIT(0), .NEEDS_SRESET(1)) cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cr_we_d), @@ -6961,7 +7131,8 @@ generate ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) cr_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(cr_we_d), @@ -6979,7 +7150,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) stcx_thrd_fail_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -6997,7 +7169,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icswxr_thrd_busy_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7015,7 +7188,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) icswxr_thrd_nbusy_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7033,7 +7207,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq3_cmmt_attmpt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7051,7 +7226,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq_need_hole_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7069,7 +7245,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) any_ack_hold_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7087,7 +7264,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) any_ack_val_ok_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7105,7 +7283,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) arb_release_itag_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7123,7 +7302,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xucr0_cls_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7141,7 +7321,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_iucr0_icbi_ack_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7158,7 +7339,8 @@ generate .dout(spr_iucr0_icbi_ack_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_lsucr0_dfwd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7176,7 +7358,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_thrd_match_restart_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7194,7 +7377,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_thrd_match_restart_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7212,7 +7396,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_thrd_nomatch_restart_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7230,7 +7415,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_thrd_nomatch_restart_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7248,7 +7434,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_older_ldmiss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7266,7 +7453,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_illeg_lswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_fxu1_val), @@ -7284,7 +7472,8 @@ generate ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_strg_noop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_fxu1_val), @@ -7302,7 +7491,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7320,7 +7510,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_fxu1_val), @@ -7338,7 +7529,8 @@ generate ); tri_rlmreg_p #(.WIDTH((((2**`GPR_WIDTH_ENC)/8)-1-0+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_dvc1_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_fxu1_val), @@ -7356,7 +7548,8 @@ generate ); tri_rlmreg_p #(.WIDTH((((2**`GPR_WIDTH_ENC)/8)-1-0+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_fxu1_dvc2_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_fxu1_val), @@ -7374,7 +7567,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_fxu1_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7392,7 +7586,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7410,7 +7605,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_axu_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_axu_val), @@ -7428,7 +7624,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_axu_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7446,7 +7643,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_qHit_set_oth_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7464,7 +7662,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex5_qHit_set_miss_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7482,7 +7681,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) ex3_nxt_oldest_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7500,7 +7700,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq_tag_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -7523,7 +7724,8 @@ generate begin : stq_tag_ptr_latch_gen tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) stq_tag_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq_tag_act[i]), @@ -7544,7 +7746,8 @@ generate endgenerate tri_rlmreg_p #(.WIDTH(`STQ_ENTRIES_ENC), .INIT(0), .NEEDS_SRESET(1)) stq4_cmmt_tag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(stq3_cmmt_val_q), @@ -7562,7 +7765,8 @@ generate ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) dbg_int_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), diff --git a/dev/verilog/work/mmq.v b/dev/verilog/work/mmq.v index 39cebde..f767cd3 100755 --- a/dev/verilog/work/mmq.v +++ b/dev/verilog/work/mmq.v @@ -39,8 +39,8 @@ (* recursive_synthesis="0" *) module mmq( - (* pin_data = "PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ac_ccflush_dc, input tc_ac_scan_dis_dc_b, @@ -1385,7 +1385,8 @@ endgenerate mmq_inval #(.MMQ_INVAL_CSWITCH_0TO3(MMQ_INVAL_CSWITCH_0TO3)) mmq_inval( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -1589,7 +1590,8 @@ mmq_spr #(.BCFG_MMUCR1_VALUE(BCFG_MMUCR1_VALUE), .BCFG_MMUCR2_VALUE(BCFG_MMUCR2_ .BCFG_MMUCFG_VALUE(BCFG_MMUCFG_VALUE), .BCFG_TLB0CFG_VALUE(BCFG_TLB0CFG_VALUE), .MMQ_SPR_CSWITCH_0TO3(MMQ_SPR_CSWITCH_0TO3)) mmq_spr( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .cp_flush(xu_ex5_flush[0:`THREADS - 1]), .cp_flush_p1(cp_flush_p1), .tc_ccflush_dc(tc_ac_ccflush_dc), @@ -1853,7 +1855,8 @@ mmq_spr #(.BCFG_MMUCR1_VALUE(BCFG_MMUCR1_VALUE), .BCFG_MMUCR2_VALUE(BCFG_MMUCR2_ mmq_dbg mmq_dbg( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_func_slp_sl_thold_2(pc_func_slp_sl_thold_2[0]), .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), .pc_sg_2(pc_sg_2[0]), @@ -2226,7 +2229,8 @@ mmq_dbg mmq_dbg( mmq_perf mmq_perf( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_func_sl_thold_2(pc_func_sl_thold_2[0]), .pc_func_slp_nsl_thold_2(pc_func_slp_nsl_thold_2), .pc_sg_2(pc_sg_2[0]), @@ -2341,7 +2345,8 @@ mmq_perf mmq_perf( mmq_perv mmq_perv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_mm_sg_3(pc_mm_sg_3), .pc_mm_func_sl_thold_3(pc_mm_func_sl_thold_3), .pc_mm_func_slp_sl_thold_3(pc_mm_func_slp_sl_thold_3), @@ -2693,7 +2698,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; mmq_tlb_req mmq_tlb_req( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -2881,7 +2887,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; mmq_tlb_ctl mmq_tlb_ctl( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -3168,7 +3175,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; mmq_tlb_cmp #(.MMQ_TLB_CMP_CSWITCH_0TO7(MMQ_TLB_CMP_CSWITCH_0TO7)) mmq_tlb_cmp( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -3540,7 +3548,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; mmq_tlb_lrat mmq_tlb_lrat( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -3681,7 +3690,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; mmq_htw mmq_htw( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .tc_ccflush_dc(tc_ac_ccflush_dc), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_diag_dc(tc_ac_scan_diag_dc), @@ -3812,7 +3822,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[17]), .ccflush_dc(tc_ac_ccflush_dc), .scan_dis_dc_b(tc_ac_scan_dis_dc_b), @@ -3872,7 +3883,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[17]), .ccflush_dc(tc_ac_ccflush_dc), @@ -3933,7 +3945,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[18]), .ccflush_dc(tc_ac_ccflush_dc), .scan_dis_dc_b(tc_ac_scan_dis_dc_b), @@ -3993,7 +4006,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[18]), .ccflush_dc(tc_ac_ccflush_dc), @@ -4058,7 +4072,8 @@ assign mm_xu_ord_write_done = mm_xu_ord_write_done_sig[0:`THREADS - 1]; .gnd(gnd), .vdd(vdd), .vcs(vdd), - .nclk(nclk), + .clk(clk), + .rst(rst), .rd_act(tlb_delayed_act[19]), .wr_act(tlb_delayed_act[33]), diff --git a/dev/verilog/work/mmq_dbg.v b/dev/verilog/work/mmq_dbg.v index 3ea41b2..ed7fa88 100755 --- a/dev/verilog/work/mmq_dbg.v +++ b/dev/verilog/work/mmq_dbg.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* @@ -44,8 +44,8 @@ module mmq_dbg( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_func_slp_sl_thold_2, input pc_func_slp_nsl_thold_2, @@ -1544,7 +1544,8 @@ module mmq_dbg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) trace_bus_enable_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1563,7 +1564,8 @@ module mmq_dbg( //======================================================================================== tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) debug_mux1_ctrls_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1581,7 +1583,8 @@ module mmq_dbg( ); tri_rlmreg_p #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) debug_mux1_ctrls_loc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1602,7 +1605,8 @@ module mmq_dbg( tri_rlmreg_p #(.WIDTH(`DEBUG_TRIGGER_WIDTH), .INIT(0)) trigger_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_mm_trace_bus_enable_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1621,7 +1625,8 @@ module mmq_dbg( tri_rlmreg_p #(.WIDTH(`DEBUG_TRACE_WIDTH), .INIT(0)) trace_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_mm_trace_bus_enable_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1640,7 +1645,8 @@ module mmq_dbg( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) trace_data_out_int_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_mm_trace_bus_enable_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1658,7 +1664,8 @@ module mmq_dbg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_mm_trace_bus_enable_q), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1675,7 +1682,8 @@ module mmq_dbg( tri_regk #(.WIDTH(DEBUG_LATCH_WIDTH), .INIT(0), .NEEDS_SRESET(0)) debug_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1694,7 +1702,8 @@ module mmq_dbg( tri_regk #(.WIDTH(TRIGGER_LATCH_WIDTH), .INIT(0), .NEEDS_SRESET(0)) trigger_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1713,7 +1722,8 @@ module mmq_dbg( tri_regk #(.WIDTH(`DEBUG_TRACE_WIDTH), .INIT(0), .NEEDS_SRESET(0)) debug_bus_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1732,7 +1742,8 @@ module mmq_dbg( tri_regk #(.WIDTH(`DEBUG_TRIGGER_WIDTH), .INIT(0), .NEEDS_SRESET(0)) trace_triggers_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1750,7 +1761,8 @@ module mmq_dbg( ); tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) coretrace_ctrls_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_mm_trace_bus_enable_q), @@ -1775,7 +1787,8 @@ module mmq_dbg( tri_plat #(.WIDTH(4)) perv_2to1_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -1785,7 +1798,8 @@ module mmq_dbg( tri_plat #(.WIDTH(4)) perv_1to0_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_htw.v b/dev/verilog/work/mmq_htw.v index 098ff3a..ed3711a 100755 --- a/dev/verilog/work/mmq_htw.v +++ b/dev/verilog/work/mmq_htw.v @@ -41,8 +41,8 @@ module mmq_htw( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, @@ -1466,7 +1466,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1485,7 +1486,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1504,7 +1506,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_htw_req0_tag_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1523,7 +1526,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req0_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[24 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1542,7 +1546,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1561,7 +1566,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1580,7 +1586,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_htw_req1_tag_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1599,7 +1606,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req1_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[24 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1618,7 +1626,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1637,7 +1646,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1656,7 +1666,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_htw_req2_tag_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1675,7 +1686,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req2_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[24 + 2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1694,7 +1706,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1713,7 +1726,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1732,7 +1746,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_tag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_htw_req3_tag_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1751,7 +1766,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH((`TLB_WAY_WIDTH-1-`TLB_WORD_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_htw_req3_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[24 + 3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1769,7 +1785,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1787,7 +1804,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1805,7 +1823,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_inptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1823,7 +1842,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_lsuptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1841,7 +1861,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(htw_lsu_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1859,7 +1880,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(htw_lsu_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1877,7 +1899,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(htw_lsu_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1895,7 +1918,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_u_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(htw_lsu_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1913,7 +1937,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_lsu_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(htw_lsu_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1931,7 +1956,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1949,7 +1975,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pte0_score_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1967,7 +1994,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_score_cl_offset_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1985,7 +2013,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte0_score_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2003,7 +2032,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) pte0_score_qwbeat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2021,7 +2051,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_ibit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2039,7 +2070,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2057,7 +2089,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte0_score_dataval_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2075,7 +2108,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2093,7 +2127,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) pte1_score_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2111,7 +2146,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_score_cl_offset_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2129,7 +2165,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) pte1_score_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2147,7 +2184,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) pte1_score_qwbeat_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2165,7 +2203,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_ibit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2183,7 +2222,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2201,7 +2241,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte1_score_dataval_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_score_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2219,7 +2260,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pte_load_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2237,7 +2279,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ptereload_ptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2256,7 +2299,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tm1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2274,7 +2318,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tm1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2292,7 +2337,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tm1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2310,7 +2356,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tm1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2328,7 +2375,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tm1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2347,7 +2395,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2365,7 +2414,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2383,7 +2433,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2401,7 +2452,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2419,7 +2471,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2438,7 +2491,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2456,7 +2510,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2474,7 +2529,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2492,7 +2548,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2510,7 +2567,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2528,7 +2586,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) reld_data_tp1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2547,7 +2606,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) reld_core_tag_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2565,7 +2625,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) reld_qw_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2583,7 +2644,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_crit_qw_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2601,7 +2663,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ditc_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2619,7 +2682,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_data_vld_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2637,7 +2701,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(128), .INIT(0), .NEEDS_SRESET(1)) reld_data_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2655,7 +2720,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ecc_err_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2673,7 +2739,8 @@ module mmq_htw( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) reld_ecc_err_ue_tp2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2692,7 +2759,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) pte0_reld_data_tp3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte0_reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2710,7 +2778,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) pte1_reld_data_tp3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pte1_reld_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2728,7 +2797,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[28]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2746,7 +2816,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag4_clr_resv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[28]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2764,7 +2835,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) htw_tag5_clr_resv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[28]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2782,7 +2854,8 @@ module mmq_htw( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2803,7 +2876,8 @@ module mmq_htw( tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) @@ -2812,7 +2886,8 @@ module mmq_htw( tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) diff --git a/dev/verilog/work/mmq_inval.v b/dev/verilog/work/mmq_inval.v index ae2f6c9..916a50e 100755 --- a/dev/verilog/work/mmq_inval.v +++ b/dev/verilog/work/mmq_inval.v @@ -48,8 +48,8 @@ module mmq_inval( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, @@ -2037,7 +2037,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2055,7 +2056,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH((`MMQ_INVAL_TTYPE_WIDTH-2)), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2073,7 +2075,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2091,7 +2094,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2109,7 +2113,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2128,7 +2133,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2146,7 +2152,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2164,7 +2171,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2182,7 +2190,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2200,7 +2209,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2218,7 +2228,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2237,7 +2248,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2255,7 +2267,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2273,7 +2286,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2291,7 +2305,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2309,7 +2324,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2327,7 +2343,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_flush_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2345,7 +2362,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`RS_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ea_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2363,7 +2381,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2382,7 +2401,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2400,7 +2420,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2418,7 +2439,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2436,7 +2458,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2454,7 +2477,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2472,7 +2496,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2491,7 +2516,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2509,7 +2535,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2527,7 +2554,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`RS_IS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_rs_is_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2545,7 +2573,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2563,7 +2592,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`T_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_t_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2581,7 +2611,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex5_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2600,7 +2631,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2618,7 +2650,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MMQ_INVAL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2636,7 +2669,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex6_isel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2654,7 +2688,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2672,7 +2707,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2690,7 +2726,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ts_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2708,7 +2745,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2726,7 +2764,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2744,7 +2783,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2762,7 +2802,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex6_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2780,7 +2821,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) mm_xu_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2798,7 +2840,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_np1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2816,7 +2859,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_read_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2834,7 +2878,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ord_write_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2853,7 +2898,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) inv_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2871,7 +2917,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2889,7 +2936,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_ack_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2907,7 +2955,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2925,7 +2974,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) iu_flush_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2943,7 +2993,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`BUS_SNOOP_SEQ_WIDTH), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2961,7 +3012,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2979,7 +3031,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_ack_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2997,7 +3050,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) bus_snoop_hold_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3015,7 +3069,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlbi_complete_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3033,7 +3088,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) local_barrier_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3051,7 +3107,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) global_barrier_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3069,7 +3126,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3087,7 +3145,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3105,7 +3164,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3123,7 +3183,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3141,7 +3202,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex7_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3159,7 +3221,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_ivax_lpid_reject_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3177,7 +3240,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_ivax_lpid_reject_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3195,7 +3259,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) local_snoop_reject_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3214,7 +3279,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) snoop_coming_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3232,7 +3298,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3250,7 +3317,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_coming_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3268,7 +3336,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_coming_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3286,7 +3355,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(26), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_coming_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3304,7 +3374,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_tlb_spec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_coming_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3322,7 +3393,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(snoop_coming_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3340,7 +3412,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) snoop_ack_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3358,7 +3431,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) mm_xu_quiesce_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3376,7 +3450,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(4*`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) mm_pc_quiesce_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3396,7 +3471,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3414,7 +3490,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3432,7 +3509,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) an_ac_back_inv_lpar_id_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3451,7 +3529,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(2), .INIT(1), .NEEDS_SRESET(1)) lsu_tokens_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3469,7 +3548,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lsu_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3487,7 +3567,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lsu_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3505,7 +3586,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lsu_ubits_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3523,7 +3605,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) lsu_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3541,7 +3624,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lsu_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3559,7 +3643,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lsu_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3577,7 +3662,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3595,7 +3681,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3613,7 +3700,8 @@ module mmq_inval( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lsu_lbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3632,7 +3720,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) power_managed_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3655,7 +3744,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_INVAL_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3673,7 +3763,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`MM_THREADS+2), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3691,7 +3782,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3709,7 +3801,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) tlbwe_back_inv_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3727,7 +3820,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) inv_seq_inprogress_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3745,7 +3839,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(13), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ccr2_notlb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3763,7 +3858,8 @@ module mmq_inval( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3780,7 +3876,8 @@ module mmq_inval( // non-scannable config latches, includes bogus sg, scin, scout ports tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) epcr_dgtmi_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3798,7 +3895,8 @@ module mmq_inval( ); tri_regk #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(0)) lpidr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3816,7 +3914,8 @@ module mmq_inval( ); tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) mmucr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3834,7 +3933,8 @@ module mmq_inval( ); tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(0)) mmucr1_csinv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3858,7 +3958,8 @@ module mmq_inval( tri_plat #(.WIDTH(5)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -3867,7 +3968,8 @@ module mmq_inval( tri_plat #(.WIDTH(5)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_perf.v b/dev/verilog/work/mmq_perf.v index 1978e24..d597ebc 100755 --- a/dev/verilog/work/mmq_perf.v +++ b/dev/verilog/work/mmq_perf.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* @@ -44,8 +44,8 @@ module mmq_perf( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input pc_func_sl_thold_2, @@ -767,7 +767,8 @@ module mmq_perf( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rp_mm_event_bus_enable_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -786,7 +787,8 @@ module mmq_perf( tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH*`THREADS), .INIT(0)) mmq_spr_event_mux_ctrls_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -805,7 +807,8 @@ module mmq_perf( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_mm_event_count_mode_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -824,7 +827,8 @@ module mmq_perf( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rp_mm_event_bus_enable_int_q), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -843,7 +847,8 @@ module mmq_perf( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0)) xu_mm_msr_pr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rp_mm_event_bus_enable_int_q), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -862,7 +867,8 @@ module mmq_perf( tri_rlmreg_p #(.WIDTH(`PERF_EVENT_WIDTH*`THREADS), .INIT(0)) event_bus_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rp_mm_event_bus_enable_int_q), .thold_b(pc_func_sl_thold_0_b), .sg(pc_sg_0), @@ -879,7 +885,8 @@ module mmq_perf( tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rp_mm_event_bus_enable_int_q), @@ -898,7 +905,8 @@ module mmq_perf( tri_regk #(.WIDTH(24), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_t1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rp_mm_event_bus_enable_int_q), @@ -917,7 +925,8 @@ module mmq_perf( tri_regk #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(0)) mm_perf_event_core_level_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(rp_mm_event_bus_enable_int_q), @@ -944,7 +953,8 @@ module mmq_perf( tri_plat #(.WIDTH(4)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -954,7 +964,8 @@ module mmq_perf( tri_plat #(.WIDTH(4)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_perv.v b/dev/verilog/work/mmq_perv.v index f1e0443..5d88ce1 100755 --- a/dev/verilog/work/mmq_perv.v +++ b/dev/verilog/work/mmq_perv.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // ********************************************************************* // @@ -41,8 +41,8 @@ module mmq_perv( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input [0:1] pc_mm_sg_3, input [0:1] pc_mm_func_sl_thold_3, @@ -330,7 +330,8 @@ module mmq_perv( tri_plat #(.WIDTH(20)) perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_mm_sg_3[0:1], pc_mm_func_slp_sl_thold_3[0:1], @@ -373,7 +374,8 @@ module mmq_perv( tri_plat #(.WIDTH(19)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_sg_2_int[0:1], pc_func_slp_sl_thold_2_int[0:1], @@ -413,7 +415,8 @@ module mmq_perv( tri_plat #(.WIDTH(19)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din( {pc_sg_1_int[0:1], pc_func_slp_sl_thold_1_int[0:1], @@ -483,7 +486,8 @@ module mmq_perv( .vdd(vdd), .gnd(gnd), .sg(pc_sg_0_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_in_q), .scan_diag_dc(tc_scan_diag_dc), .thold(pc_gptr_sl_thold_0_int), @@ -501,7 +505,8 @@ module mmq_perv( .vdd(vdd), .gnd(gnd), .sg(pc_sg_0_int[1]), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_lcbctrl[0]), .scan_diag_dc(tc_scan_diag_dc), .thold(pc_gptr_sl_thold_0_int), @@ -519,7 +524,8 @@ module mmq_perv( .vdd(vdd), .gnd(gnd), .sg(pc_sg_0_int[1]), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_lcbctrl[1]), .scan_diag_dc(tc_scan_diag_dc), .thold(pc_gptr_sl_thold_0_int), @@ -569,7 +575,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[1]), .thold_b(abst_slat_thold_b), .dclk(abst_slat_d2clk), @@ -593,7 +600,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[1]), .thold_b(time_slat_thold_b), .dclk(time_slat_d2clk), @@ -617,7 +625,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[1]), .thold_b(repr_slat_thold_b), .dclk(repr_slat_d2clk), @@ -641,7 +650,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(tiup), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[0]), .thold_b(gptr_slat_thold_b), .dclk(gptr_slat_d2clk), @@ -665,7 +675,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[0]), .thold_b(bcfg_slat_thold_b), .dclk(bcfg_slat_d2clk), @@ -689,7 +700,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[0]), .thold_b(ccfg_slat_thold_b), .dclk(ccfg_slat_d2clk), @@ -713,7 +725,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[0]), .thold_b(dcfg_slat_thold_b), .dclk(dcfg_slat_d2clk), @@ -737,7 +750,8 @@ module mmq_perv( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc_int[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(slat_force[0]), .thold_b(func_slat_thold_b), .dclk(func_slat_d2clk), @@ -814,7 +828,8 @@ module mmq_perv( tri_rlmreg_p #(.INIT(0), .WIDTH(42), .NEEDS_SRESET(0)) abist_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(pc_mm_abist_ena_dc), .thold_b(pc_abst_sl_thold_0_b), .sg(pc_sg_0_int[1]), diff --git a/dev/verilog/work/mmq_spr.v b/dev/verilog/work/mmq_spr.v index 1452d5c..a72c9a4 100755 --- a/dev/verilog/work/mmq_spr.v +++ b/dev/verilog/work/mmq_spr.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* TITLE: Memory Management Unit Special Purpose Registers @@ -39,8 +39,8 @@ module mmq_spr( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input [0:`THREADS-1] cp_flush, output [0:`MM_THREADS-1] cp_flush_p1, @@ -2374,7 +2374,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2392,7 +2393,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_p1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2412,7 +2414,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2430,7 +2433,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2448,7 +2452,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2466,7 +2471,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_in_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2484,7 +2490,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_in_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2503,7 +2510,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_int_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2521,7 +2529,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_int_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2539,7 +2548,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_int_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2557,7 +2567,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_int_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2576,7 +2587,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_CTL_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_ctl_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2594,7 +2606,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ETID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_etid_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2612,7 +2625,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_addr_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2630,7 +2644,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_val_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2649,7 +2664,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mmu_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2667,7 +2683,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2686,7 +2703,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_pid1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2705,7 +2723,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2724,7 +2743,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr0_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2743,7 +2763,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2761,7 +2782,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2779,7 +2801,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2798,7 +2821,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucr3_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2817,7 +2841,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lpidr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2835,7 +2860,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2853,7 +2879,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mesr2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2871,7 +2898,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucsr0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2889,7 +2917,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mmucfg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2907,7 +2936,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0cfg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2925,7 +2955,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_tlb0ps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2943,7 +2974,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratcfg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2961,7 +2993,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lratps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2979,7 +3012,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_eptcfg_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2997,7 +3031,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3015,7 +3050,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3034,7 +3070,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lper_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3052,7 +3089,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_lperu_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3071,7 +3109,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3089,7 +3128,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3107,7 +3147,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3125,7 +3166,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3143,7 +3185,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3161,7 +3204,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3179,7 +3223,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3197,7 +3242,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3215,7 +3261,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3233,7 +3280,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3251,7 +3299,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3269,7 +3318,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3287,7 +3337,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3305,7 +3356,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3324,7 +3376,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas0_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3342,7 +3395,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas1_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3360,7 +3414,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3378,7 +3433,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas3_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3396,7 +3452,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas4_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3414,7 +3471,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas5_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3432,7 +3490,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas6_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3450,7 +3509,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas7_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3468,7 +3528,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas8_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3486,7 +3547,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas2u_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3504,7 +3566,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas01_64b_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3522,7 +3585,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas56_64b_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3540,7 +3604,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas73_64b_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3558,7 +3623,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_mas81_64b_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3577,7 +3643,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_64b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3596,7 +3663,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`SPR_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) spr_mas_data_out_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mas_data_out_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3614,7 +3682,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_match_any_mas_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_match_mas_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3633,7 +3702,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mmu_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3652,7 +3722,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) pid1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mmu_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3671,7 +3742,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3690,7 +3762,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR0_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mmucr0_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3709,7 +3782,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR1_WIDTH), .INIT(BCFG_MMUCR1_VALUE), .NEEDS_SRESET(1)) mmucr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3727,7 +3801,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR2_WIDTH), .INIT(BCFG_MMUCR2_VALUE), .NEEDS_SRESET(1)) mmucr2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3745,7 +3820,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3763,7 +3839,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3782,7 +3859,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MMUCR3_WIDTH), .INIT(BCFG_MMUCR3_VALUE), .NEEDS_SRESET(1)) mmucr3_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3800,7 +3878,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tstmode4k_1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3820,7 +3899,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lpidr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mmu_act_q[`MM_THREADS]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3838,7 +3918,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MESR1_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mmu_act_q[`MM_THREADS]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3856,7 +3937,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MESR2_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mesr2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(spr_mmu_act_q[`MM_THREADS]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3874,7 +3956,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_atsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3892,7 +3975,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_0_esel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3910,7 +3994,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_0_hes_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3928,7 +4013,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_0_wq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3946,7 +4032,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3964,7 +4051,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_iprot_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3982,7 +4070,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4000,7 +4089,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4018,7 +4108,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_0_ts_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4036,7 +4127,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_0_tsize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4054,7 +4146,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_0_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4072,7 +4165,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_0_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4090,7 +4184,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_0_rpnl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4108,7 +4203,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_0_ubits_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4126,7 +4222,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_0_usxwr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4144,7 +4241,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_0_indd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4162,7 +4260,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_0_tsized_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4180,7 +4279,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_0_wimged_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4198,7 +4298,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_0_sgs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4216,7 +4317,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_0_slpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4234,7 +4336,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_0_spid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4252,7 +4355,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_0_isize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4270,7 +4374,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4288,7 +4393,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_0_sas_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4306,7 +4412,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_0_rpnu_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4324,7 +4431,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_tgs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4342,7 +4450,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_0_vf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4360,7 +4469,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_0_tlpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4379,7 +4489,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_atsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4397,7 +4508,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mas0_1_esel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4415,7 +4527,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas0_1_hes_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4433,7 +4546,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) mas0_1_wq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4451,7 +4565,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4469,7 +4584,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_iprot_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4487,7 +4603,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4505,7 +4622,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4523,7 +4641,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas1_1_ts_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4541,7 +4660,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas1_1_tsize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4559,7 +4679,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(52-(64-`SPR_DATA_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) mas2_1_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4578,7 +4699,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas2_1_wimge_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4596,7 +4718,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) mas3_1_rpnl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4614,7 +4737,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas3_1_ubits_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4632,7 +4756,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) mas3_1_usxwr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4650,7 +4775,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas4_1_indd_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4668,7 +4794,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(1), .NEEDS_SRESET(1)) mas4_1_tsized_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4686,7 +4813,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) mas4_1_wimged_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4704,7 +4832,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas5_1_sgs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4722,7 +4851,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas5_1_slpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4740,7 +4870,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mas6_1_spid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4758,7 +4889,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) mas6_1_isize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4776,7 +4908,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4794,7 +4927,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas6_1_sas_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4812,7 +4946,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) mas7_1_rpnu_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4830,7 +4965,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_tgs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4848,7 +4984,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mas8_1_vf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4866,7 +5003,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) mas8_1_tlpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4885,7 +5023,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mmucsr0_tlb0fi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4903,7 +5042,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(52-(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_0_alpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4921,7 +5061,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_0_lps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4940,7 +5081,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(52 -(64-`REAL_ADDR_WIDTH)), .INIT(0), .NEEDS_SRESET(1)) lper_1_alpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4958,7 +5100,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lper_1_lps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(mas_update_pending_act[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4977,7 +5120,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) spr_mmu_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4995,7 +5139,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) spr_val_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5014,7 +5159,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5039,7 +5185,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_dtlb_error_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5057,7 +5204,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mas_itlb_error_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5075,7 +5223,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_we_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5093,7 +5242,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_we_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5111,7 +5261,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_we_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5129,7 +5280,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_we_pending_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5147,7 +5299,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_ts_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5165,7 +5318,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_0_tid_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5183,7 +5337,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_0_epn_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5201,7 +5356,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5219,7 +5375,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_0_lps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5237,7 +5394,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_0_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5255,7 +5413,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_0_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_mm_ierat_mmucr1_we_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5273,7 +5432,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_0_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_derat_mmucr1_we_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5293,7 +5453,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) cp_mm_except_taken_t1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5318,7 +5479,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_ts_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5336,7 +5498,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas1_1_tid_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5354,7 +5517,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_mas2_1_epn_error_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5372,7 +5536,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`REAL_ADDR_WIDTH-12), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5390,7 +5555,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) tlb_lper_1_lps_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5408,7 +5574,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) tlb_mmucr1_1_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cat_emf_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5426,7 +5593,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ierat_mmucr1_1_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu_mm_ierat_mmucr1_we_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5444,7 +5612,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) derat_mmucr1_1_een_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_derat_mmucr1_we_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5465,7 +5634,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(4), .INIT(MMQ_SPR_CSWITCH_0TO3), .NEEDS_SRESET(1)) cswitch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5487,7 +5657,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cat_emf_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5505,7 +5676,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5523,7 +5695,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5540,7 +5713,8 @@ endgenerate // non-scannable timing latches tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5558,7 +5732,8 @@ endgenerate ); tri_regk #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5576,7 +5751,8 @@ endgenerate ); tri_regk #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5594,7 +5770,8 @@ endgenerate ); tri_regk #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5612,7 +5789,8 @@ endgenerate ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5630,7 +5808,8 @@ endgenerate ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr1_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5648,7 +5827,8 @@ endgenerate ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) iu_mm_ierat_mmucr0_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5666,7 +5846,8 @@ endgenerate ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) xu_mm_derat_mmucr0_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -5737,7 +5918,8 @@ endgenerate .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(pc_cfg_sl_force), .thold_b(pc_cfg_sl_thold_0_b), .dclk(lcb_dclk), @@ -5754,7 +5936,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(2), .INIT(BCFG_MMUCFG_VALUE), .NEEDS_SRESET(1)) mmucfg_47to48_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5772,7 +5955,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(3), .INIT(BCFG_TLB0CFG_VALUE), .NEEDS_SRESET(1)) tlb0cfg_45to47_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5790,7 +5974,8 @@ endgenerate tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) bcfg_spare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_cfg_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5869,7 +6054,8 @@ endgenerate tri_plat #(.WIDTH(7)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_cfg_sl_thold_2, pc_cfg_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -5878,7 +6064,8 @@ endgenerate tri_plat #(.WIDTH(7)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_cfg_sl_thold_1, pc_cfg_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_cfg_sl_thold_0, pc_cfg_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_tlb_cmp.v b/dev/verilog/work/mmq_tlb_cmp.v index 27312f8..c2ea0d2 100755 --- a/dev/verilog/work/mmq_tlb_cmp.v +++ b/dev/verilog/work/mmq_tlb_cmp.v @@ -39,8 +39,8 @@ module mmq_tlb_cmp( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, @@ -5409,7 +5409,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5427,7 +5428,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5445,7 +5447,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5463,7 +5466,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5482,7 +5486,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[9]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5500,7 +5505,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_clone1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5518,7 +5524,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_clone2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5537,7 +5544,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr3_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[9]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5557,7 +5565,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_tag3_dataout_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[9]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5576,7 +5585,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5594,7 +5604,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_tag3_cmpmask_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5613,7 +5624,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5631,7 +5643,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5649,7 +5662,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5667,7 +5681,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5685,7 +5700,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way0_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5703,7 +5719,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way1_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[12]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5721,7 +5738,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way2_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5739,7 +5757,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tlb_way3_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[13]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5758,7 +5777,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5776,7 +5796,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH((`TLB_WAYS+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_wayhit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5794,7 +5815,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr4_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5812,7 +5834,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_dataina_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[14]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5830,7 +5853,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_datainb_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[15]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5848,7 +5872,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`LRU_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lru_tag4_dataout_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5866,7 +5891,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_tag4_way_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5884,7 +5910,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_tag4_way_clone_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5902,7 +5929,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_rw_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_tag4_way_rw_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5920,7 +5948,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_WAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag4_way_rw_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_tag4_way_rw_clone_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5938,7 +5967,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS+1), .INIT(0), .NEEDS_SRESET(1)) tlbwe_tag4_back_inv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5956,7 +5986,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlbwe_tag4_back_inv_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5975,7 +6006,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH((2*`THDID_WIDTH+1+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[14]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -5993,7 +6025,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`ERAT_REL_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_rel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[14]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6011,7 +6044,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`ERAT_REL_DATA_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_rel_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[15]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6029,7 +6063,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH((2*`THDID_WIDTH+13+1)), .INIT(0), .NEEDS_SRESET(1)) tlb_erat_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6047,7 +6082,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_write_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6065,7 +6101,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lru_wr_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6083,7 +6120,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) lru_datain_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6101,7 +6139,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) eratmiss_done_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6119,7 +6158,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6137,7 +6177,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_inelig_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6155,7 +6196,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lrat_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6173,7 +6215,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) pt_fault_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6191,7 +6234,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) hv_priv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6209,7 +6253,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_except_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6227,7 +6272,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) mm_xu_ord_par_mhit_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6245,7 +6291,8 @@ module mmq_tlb_cmp( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lru_update_clear_enab_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6263,7 +6310,8 @@ module mmq_tlb_cmp( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_tag5_parerr_zeroize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6281,7 +6329,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6299,7 +6348,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6317,7 +6367,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlb_tag5_perf_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[11]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6335,7 +6386,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_dsi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6353,7 +6405,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_isi_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6371,7 +6424,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_pt_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6389,7 +6443,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_data_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6407,7 +6462,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_st_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6425,7 +6481,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) esr_epid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6443,7 +6500,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cr0_eq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6461,7 +6519,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) cr0_eq_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6479,7 +6538,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_multihit_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6497,7 +6557,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH((`TLB_WAYS+1)), .INIT(0), .NEEDS_SRESET(1)) tag4_parerr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[10]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6515,7 +6576,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6533,7 +6595,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lru_par_err_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6552,7 +6615,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6571,7 +6635,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(9), .INIT(0), .NEEDS_SRESET(1)) mmucr1_clone_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6589,7 +6654,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_a_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[14]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6607,7 +6673,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_b_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[15]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6625,7 +6692,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(8), .INIT(MMQ_TLB_CMP_CSWITCH_0TO7), .NEEDS_SRESET(1)) cswitch_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6651,7 +6719,8 @@ module mmq_tlb_cmp( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) spare_c_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[16]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -6670,7 +6739,8 @@ module mmq_tlb_cmp( // Changed these to spares tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) spare_nsl_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -6688,7 +6758,8 @@ module mmq_tlb_cmp( ); tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) spare_nsl_clone_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -6706,7 +6777,8 @@ module mmq_tlb_cmp( ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) epcr_dmiuh_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -6724,7 +6796,8 @@ module mmq_tlb_cmp( ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) msr_gs_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -6742,7 +6815,8 @@ module mmq_tlb_cmp( ); tri_regk #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(0)) msr_pr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -6768,7 +6842,8 @@ module mmq_tlb_cmp( tri_plat #(.WIDTH(5)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -6777,7 +6852,8 @@ module mmq_tlb_cmp( tri_plat #(.WIDTH(5)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_tlb_ctl.v b/dev/verilog/work/mmq_tlb_ctl.v index 6266522..6536617 100755 --- a/dev/verilog/work/mmq_tlb_ctl.v +++ b/dev/verilog/work/mmq_tlb_ctl.v @@ -42,9 +42,8 @@ module mmq_tlb_ctl( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, input tc_scan_diag_dc, @@ -3427,7 +3426,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) xu_ex1_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3445,7 +3445,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3463,7 +3464,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3481,7 +3483,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3499,7 +3502,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3517,7 +3521,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3536,7 +3541,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3554,7 +3560,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3572,7 +3579,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_flush_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3590,7 +3598,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3608,7 +3617,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3626,7 +3636,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3644,7 +3655,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3663,7 +3675,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3681,7 +3694,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3699,7 +3713,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3717,7 +3732,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3735,7 +3751,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3754,7 +3771,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3772,7 +3790,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3790,7 +3809,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3808,7 +3828,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3826,7 +3847,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3845,7 +3867,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3863,7 +3886,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3881,7 +3905,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3899,7 +3924,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3917,7 +3943,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3936,7 +3963,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3954,7 +3982,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3972,7 +4001,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CTL_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3990,7 +4020,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH((`CTL_STATE_WIDTH+1)), .INIT(0), .NEEDS_SRESET(1)) ex6_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4008,7 +4039,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4026,7 +4058,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag0_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_tag0_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4044,7 +4077,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag1_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4062,7 +4096,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_TAG_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_tag2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4081,7 +4116,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4100,7 +4136,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_ADDR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_addr2_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4118,7 +4155,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`TLB_WAYS), .INIT(0), .NEEDS_SRESET(1)) tlb_write_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4136,7 +4174,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_illeg_instr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4155,7 +4194,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) tlb_seq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4173,7 +4213,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_taken_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4191,7 +4232,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr4_mmu_mchk_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4209,7 +4251,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) snoop_val_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_snoop_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4227,7 +4270,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(35), .INIT(0), .NEEDS_SRESET(1)) snoop_attr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_snoop_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4245,7 +4289,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) snoop_vpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_snoop_act), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4263,7 +4308,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_clr_resv_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4281,7 +4327,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) tlb_resv_match_vec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4299,7 +4346,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4317,7 +4365,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4335,7 +4384,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4353,7 +4403,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4371,7 +4422,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_as_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4389,7 +4441,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4407,7 +4460,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv0_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4425,7 +4479,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CLASS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv0_class_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4444,7 +4499,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4462,7 +4518,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4480,7 +4537,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4498,7 +4556,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4516,7 +4575,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_as_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4534,7 +4594,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_gs_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4552,7 +4613,8 @@ module mmq_tlb_ctl( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_resv1_ind_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4570,7 +4632,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`CLASS_WIDTH), .INIT(0), .NEEDS_SRESET(1)) tlb_resv1_class_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act_q[5 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4589,7 +4652,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(`PTE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ptereload_req_pte_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ptereload_req_valid), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4608,7 +4672,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(34), .INIT(0), .NEEDS_SRESET(1)) tlb_delayed_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4627,7 +4692,8 @@ module mmq_tlb_ctl( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tlb_ctl_spare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4644,7 +4710,8 @@ module mmq_tlb_ctl( // non-scannable timing latches tri_regk #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) tlb_resv0_tag1_match_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -4669,7 +4736,8 @@ module mmq_tlb_ctl( `ifdef MM_THREADS2 tri_regk #(.WIDTH(11), .INIT(0), .NEEDS_SRESET(0)) tlb_resv1_tag1_match_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_mm_ccr2_notlb_b), @@ -4700,7 +4768,8 @@ module mmq_tlb_ctl( tri_plat #(.WIDTH(5)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_sg_2, pc_fce_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ) @@ -4709,7 +4778,8 @@ module mmq_tlb_ctl( tri_plat #(.WIDTH(5)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_func_slp_nsl_thold_1, pc_sg_1, pc_fce_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_func_slp_nsl_thold_0, pc_sg_0, pc_fce_0} ) diff --git a/dev/verilog/work/mmq_tlb_lrat.v b/dev/verilog/work/mmq_tlb_lrat.v index bc7330a..379f8df 100755 --- a/dev/verilog/work/mmq_tlb_lrat.v +++ b/dev/verilog/work/mmq_tlb_lrat.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* TITLE: MMU Logical to Real Translate Logic @@ -46,9 +46,8 @@ module mmq_tlb_lrat( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, input tc_scan_diag_dc, @@ -1878,7 +1877,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1897,7 +1897,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1915,7 +1916,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hv_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1934,7 +1936,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1953,7 +1956,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1971,7 +1975,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hv_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1990,7 +1995,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2009,7 +2015,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_TTYPE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2027,7 +2034,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hv_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2046,7 +2054,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) ex5_esel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2065,7 +2074,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_atsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2084,7 +2094,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_hes_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2103,7 +2114,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex5_wq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2122,7 +2134,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) ex6_esel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2141,7 +2154,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_atsel_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2160,7 +2174,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_hes_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2179,7 +2194,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex6_wq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2198,7 +2214,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2217,7 +2234,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2236,7 +2254,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2255,7 +2274,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2274,7 +2294,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2293,7 +2314,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2312,7 +2334,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_hit_status_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2331,7 +2354,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) lrat_tag3_hit_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2350,7 +2374,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_hit_status_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2369,7 +2394,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY_LOG2), .INIT(0), .NEEDS_SRESET(1)) lrat_tag4_hit_entry_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20 + 3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2387,7 +2413,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2405,7 +2432,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag1_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2423,7 +2451,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[21]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2441,7 +2470,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_entry_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[21]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2459,7 +2489,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LRAT_NUM_ENTRY), .INIT(0), .NEEDS_SRESET(1)) lrat_tag2_matchline_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[21]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2477,7 +2508,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) tlb_addr_cap_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tlb_delayed_act[20]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2495,7 +2527,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) spare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2513,7 +2546,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) lrat_entry_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2531,7 +2565,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) lrat_mas_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2549,7 +2584,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_act_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2568,7 +2604,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2586,7 +2623,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry0_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2604,7 +2642,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2622,7 +2661,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2640,7 +2680,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2658,7 +2699,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2676,7 +2718,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2694,7 +2737,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry0_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2712,7 +2756,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2730,7 +2775,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry1_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2748,7 +2794,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2766,7 +2813,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2784,7 +2832,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2802,7 +2851,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2820,7 +2870,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2838,7 +2889,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry1_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2856,7 +2908,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2874,7 +2927,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry2_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2892,7 +2946,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2910,7 +2965,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2928,7 +2984,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2946,7 +3003,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2964,7 +3022,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2982,7 +3041,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry2_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3000,7 +3060,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3018,7 +3079,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry3_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3036,7 +3098,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3054,7 +3117,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3072,7 +3136,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3090,7 +3155,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3108,7 +3174,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3126,7 +3193,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry3_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[3]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3144,7 +3212,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3162,7 +3231,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry4_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3180,7 +3250,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3198,7 +3269,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3216,7 +3288,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3234,7 +3307,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3252,7 +3326,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3270,7 +3345,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry4_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[4]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3288,7 +3364,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3306,7 +3383,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry5_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3324,7 +3402,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3342,7 +3421,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3360,7 +3440,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3378,7 +3459,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3396,7 +3478,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3414,7 +3497,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry5_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[5]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3432,7 +3516,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3450,7 +3535,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry6_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3468,7 +3554,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3486,7 +3573,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3504,7 +3592,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3522,7 +3611,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3540,7 +3630,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3558,7 +3649,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry6_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[6]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3576,7 +3668,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry7_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3594,7 +3687,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_entry7_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3612,7 +3706,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3630,7 +3725,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3648,7 +3744,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3666,7 +3763,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3684,7 +3782,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_cmpmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3702,7 +3801,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(1)) lrat_entry7_xbitmask_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_entry_act_q[7]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3720,7 +3820,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_lpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3738,7 +3839,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH((64-`LRAT_MINSIZE_LOG2-1-(64-`REAL_ADDR_WIDTH)+1)), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_rpn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3756,7 +3858,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3774,7 +3877,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_datain_size_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3792,7 +3896,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_datain_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3810,7 +3915,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_datain_xbit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_datain_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3828,7 +3934,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas1_v_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3846,7 +3953,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mmucr3_x_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3864,7 +3972,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) lrat_mas1_tsize_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3882,7 +3991,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`RPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_mas2_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[0]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3900,7 +4010,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(20), .INIT(0), .NEEDS_SRESET(1)) lrat_mas3_rpnl_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3918,7 +4029,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) lrat_mas7_rpnu_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3936,7 +4048,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) lrat_mas8_tlpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[1]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3954,7 +4067,8 @@ module mmq_tlb_lrat( tri_rlmreg_p #(.WIDTH(`MM_THREADS), .INIT(0), .NEEDS_SRESET(1)) lrat_mas_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3972,7 +4086,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbre_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3990,7 +4105,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbsx_hit_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4008,7 +4124,8 @@ module mmq_tlb_lrat( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lrat_mas_tlbsx_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lrat_mas_act_q[2]), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -4030,7 +4147,8 @@ module mmq_tlb_lrat( tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) @@ -4039,7 +4157,8 @@ module mmq_tlb_lrat( tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) diff --git a/dev/verilog/work/mmq_tlb_req.v b/dev/verilog/work/mmq_tlb_req.v index 09a777c..5baa151 100755 --- a/dev/verilog/work/mmq_tlb_req.v +++ b/dev/verilog/work/mmq_tlb_req.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. //******************************************************************** //* TITLE: Memory Management Unit TLB Input Request Queue from ERATs @@ -41,9 +41,8 @@ module mmq_tlb_req( inout vdd, inout gnd, - (* pin_data ="PIN_FUNCTION=/G_CLK/" *) - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input tc_ccflush_dc, input tc_scan_dis_dc_b, input tc_scan_diag_dc, @@ -1261,7 +1260,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1279,7 +1279,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req0_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1297,7 +1298,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1315,7 +1317,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1333,7 +1336,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1351,7 +1355,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1369,7 +1374,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req0_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1387,7 +1393,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1405,7 +1412,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req1_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1423,7 +1431,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1441,7 +1450,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1459,7 +1469,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1477,7 +1488,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1495,7 +1507,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req1_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1513,7 +1526,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1531,7 +1545,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req2_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1549,7 +1564,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1567,7 +1583,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1585,7 +1602,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1603,7 +1621,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1621,7 +1640,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req2_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1639,7 +1659,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1657,7 +1678,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_req3_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1675,7 +1697,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1693,7 +1716,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1711,7 +1735,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1729,7 +1754,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1747,7 +1773,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_req3_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1765,7 +1792,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_inptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1783,7 +1811,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ierat_outptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1801,7 +1830,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1819,7 +1849,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_seq_ierat_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1837,7 +1868,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ierat_flush_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1855,7 +1887,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) xu_mm_ierat_miss_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1874,7 +1907,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1892,7 +1926,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1910,7 +1945,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1928,7 +1964,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1946,7 +1983,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1964,7 +2002,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu3_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -1982,7 +2021,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2000,7 +2040,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2018,7 +2059,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2036,7 +2078,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2054,7 +2097,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu4_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2072,7 +2116,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu4_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2090,7 +2135,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2108,7 +2154,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2126,7 +2173,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2144,7 +2192,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2162,7 +2211,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ierat_iu5_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2180,7 +2230,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ierat_iu5_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2199,7 +2250,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req0_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2217,7 +2269,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2235,7 +2288,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2253,7 +2307,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2271,7 +2326,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req0_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2289,7 +2345,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2307,7 +2364,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req0_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2325,7 +2383,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req0_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2343,7 +2402,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req0_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2361,7 +2421,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req0_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2379,7 +2440,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req0_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2397,7 +2459,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req1_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2415,7 +2478,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2433,7 +2497,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2451,7 +2516,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2469,7 +2535,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req1_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2487,7 +2554,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2505,7 +2573,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req1_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2523,7 +2592,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req1_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2541,7 +2611,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req1_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2559,7 +2630,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req1_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2577,7 +2649,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req1_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2595,7 +2668,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req2_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2613,7 +2687,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2631,7 +2706,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2649,7 +2725,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2667,7 +2744,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req2_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2685,7 +2763,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2703,7 +2782,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req2_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2721,7 +2801,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req2_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2739,7 +2820,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req2_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2757,7 +2839,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req2_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2775,7 +2858,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req2_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2793,7 +2877,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req3_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2811,7 +2896,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2829,7 +2915,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2847,7 +2934,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2865,7 +2953,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req3_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2883,7 +2972,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2901,7 +2991,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_req3_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2919,7 +3010,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_req3_dup_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2937,7 +3029,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_req3_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2955,7 +3048,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_req3_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2973,7 +3067,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_req3_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -2991,7 +3086,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_inptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3009,7 +3105,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_outptr_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3027,7 +3124,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tlb_seq_derat_req_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3046,7 +3144,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex4_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3064,7 +3163,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3082,7 +3182,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3100,7 +3201,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3118,7 +3220,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3136,7 +3239,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3154,7 +3258,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3172,7 +3277,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3190,7 +3296,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex4_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3208,7 +3315,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex4_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3226,7 +3334,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex5_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3244,7 +3353,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3262,7 +3372,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3280,7 +3391,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3298,7 +3410,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3316,7 +3429,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3334,7 +3448,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3352,7 +3467,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3370,7 +3486,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex5_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3388,7 +3505,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex5_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3406,7 +3524,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex6_valid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3424,7 +3543,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`THDID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_thdid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3442,7 +3562,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EPN_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_epn_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3460,7 +3581,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`REQ_STATE_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_state_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3478,7 +3600,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_ttype_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3496,7 +3619,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`PID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_pid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3514,7 +3638,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`LPID_WIDTH), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_lpid_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3532,7 +3657,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_itag_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3550,7 +3676,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(`EMQ_ENTRIES), .INIT(0), .NEEDS_SRESET(1)) derat_ex6_emq_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3568,7 +3695,8 @@ module mmq_tlb_req( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) derat_ex6_nonspec_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3586,7 +3714,8 @@ module mmq_tlb_req( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) spare_latch( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_mm_ccr2_notlb_b), .thold_b(pc_func_slp_sl_thold_0_b), .sg(pc_sg_0), @@ -3608,7 +3737,8 @@ module mmq_tlb_req( tri_plat #(.WIDTH(3)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_2, pc_func_slp_sl_thold_2, pc_sg_2} ), .q( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ) @@ -3617,7 +3747,8 @@ module mmq_tlb_req( tri_plat #(.WIDTH(3)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ccflush_dc), .din( {pc_func_sl_thold_1, pc_func_slp_sl_thold_1, pc_sg_1} ), .q( {pc_func_sl_thold_0, pc_func_slp_sl_thold_0, pc_sg_0} ) diff --git a/dev/verilog/work/pcq.v b/dev/verilog/work/pcq.v index b006632..f98dd5c 100755 --- a/dev/verilog/work/pcq.v +++ b/dev/verilog/work/pcq.v @@ -41,8 +41,8 @@ module pcq( // inout vdd, // inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, //SCOM and Register Interfaces // SCOM Satellite input [0:3] an_ac_scom_sat_id, @@ -391,7 +391,8 @@ module pcq( pcq_regs pcq_regs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_dis_dc_b(an_ac_scan_dis_dc_b), .lcb_clkoff_dc_b(clkoff_dc_b), .lcb_d_mode_dc(d_mode_dc), @@ -576,7 +577,8 @@ module pcq( pcq_ctrl pcq_ctrl( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_dis_dc_b(an_ac_scan_dis_dc_b), .lcb_clkoff_dc_b(clkoff_dc_b), .lcb_mpw1_dc_b(mpw1_dc_b[1]), @@ -608,7 +610,8 @@ module pcq( pcq_dbg pcq_dbg( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_dis_dc_b(an_ac_scan_dis_dc_b), .lcb_clkoff_dc_b(clkoff_dc_b), .lcb_mpw1_dc_b(mpw1_dc_b[2]), @@ -641,7 +644,8 @@ module pcq( pcq_spr pcq_spr( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_dis_dc_b(an_ac_scan_dis_dc_b), .lcb_clkoff_dc_b(clkoff_dc_b), .lcb_mpw1_dc_b(mpw1_dc_b[0]), @@ -702,7 +706,8 @@ module pcq( pcq_clks pcq_clks( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .rtim_sl_thold_7(an_ac_rtim_sl_thold_7), .func_sl_thold_7(an_ac_func_sl_thold_7), .func_nsl_thold_7(an_ac_func_nsl_thold_7), @@ -772,7 +777,8 @@ module pcq( .vdd(vdd), .gnd(gnd), .sg(pc_pc_sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_in), .scan_diag_dc(an_ac_scan_diag_dc), .thold(pc_pc_gptr_sl_thold_0), diff --git a/dev/verilog/work/pcq_clks.v b/dev/verilog/work/pcq_clks.v index 68ca9e0..c67f8b1 100755 --- a/dev/verilog/work/pcq_clks.v +++ b/dev/verilog/work/pcq_clks.v @@ -41,7 +41,8 @@ module pcq_clks( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input rtim_sl_thold_7, input func_sl_thold_7, input func_nsl_thold_7, @@ -142,7 +143,8 @@ module pcq_clks( pcq_clks_ctrl clkctrl( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .rtim_sl_thold_6(rtim_sl_thold_6), .func_sl_thold_6(func_sl_thold_6), .func_nsl_thold_6(func_nsl_thold_6), @@ -185,7 +187,8 @@ module pcq_clks( pcq_clks_stg clkstg( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .ccflush_out_dc(ccflush_out_dc), .gptr_sl_thold_5(gptr_sl_thold_5), .time_sl_thold_5(time_sl_thold_5), @@ -252,17 +255,14 @@ module pcq_clks( .pc_pc_sg_0(pc_pc_sg_0) ); - - tri_plat #(.WIDTH(6)) lvl7to6_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), - .din({rtim_sl_thold_7, func_sl_thold_7, func_nsl_thold_7, ary_nsl_thold_7, sg_7, fce_7}), - .q( {rtim_sl_thold_6, func_sl_thold_6, func_nsl_thold_6, ary_nsl_thold_6, sg_6, fce_6}) ); diff --git a/dev/verilog/work/pcq_clks_ctrl.v b/dev/verilog/work/pcq_clks_ctrl.v index 239fd00..20f76d1 100755 --- a/dev/verilog/work/pcq_clks_ctrl.v +++ b/dev/verilog/work/pcq_clks_ctrl.v @@ -41,7 +41,8 @@ module pcq_clks_ctrl( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input rtim_sl_thold_6, input func_sl_thold_6, input func_nsl_thold_6, @@ -209,7 +210,8 @@ module pcq_clks_ctrl( tri_plat #(.WIDTH(1)) fast_stop_staging( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc_int), .din(rg_ck_fast_xstop), .q(fast_xstop_gated_staged) @@ -218,7 +220,8 @@ module pcq_clks_ctrl( tri_plat #(.WIDTH(2)) sg_fce_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc_int), .din({sg_in, fce_in}), .q ({sg_5, fce_5 }) @@ -227,7 +230,8 @@ module pcq_clks_ctrl( tri_plat #(.WIDTH(16)) thold_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc_int), .din({gptr_sl_thold_in, time_sl_thold_in, repr_sl_thold_in, cfg_run_sl_thold_in, diff --git a/dev/verilog/work/pcq_clks_stg.v b/dev/verilog/work/pcq_clks_stg.v index 16b3eb5..d588270 100755 --- a/dev/verilog/work/pcq_clks_stg.v +++ b/dev/verilog/work/pcq_clks_stg.v @@ -41,7 +41,8 @@ module pcq_clks_stg( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input ccflush_out_dc, input gptr_sl_thold_5, input time_sl_thold_5, @@ -166,7 +167,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(18)) lvl5to4_plat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din({gptr_sl_thold_5, time_sl_thold_5, repr_sl_thold_5, @@ -210,7 +212,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(18)) fu_clkstg_4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din({pc_pc_gptr_sl_thold_4_int, pc_pc_time_sl_thold_4_int, pc_pc_repr_sl_thold_4_int, @@ -233,7 +236,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(6)) pc_lvl4to3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din({pc_pc_func_sl_thold_4_int, pc_pc_func_slp_sl_thold_4_int, pc_pc_cfg_sl_thold_4_int, @@ -253,7 +257,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_sl_thold_3), .q(pc_pc_func_sl_thold_2) @@ -262,7 +267,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_sl_thold_2), .q(pc_pc_func_sl_thold_1) @@ -271,7 +277,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_sl_thold_1), .q(pc_pc_func_sl_thold_0) @@ -283,7 +290,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_slp_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_slp_sl_thold_3), .q(pc_pc_func_slp_sl_thold_2) @@ -292,7 +300,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_slp_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_slp_sl_thold_2), .q(pc_pc_func_slp_sl_thold_1) @@ -301,7 +310,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) func_slp_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_func_slp_sl_thold_1), .q(pc_pc_func_slp_sl_thold_0) @@ -313,7 +323,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_sl_thold_3), .q(pc_pc_cfg_sl_thold_2) @@ -322,7 +333,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_sl_thold_2), .q(pc_pc_cfg_sl_thold_1) @@ -331,7 +343,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_sl_thold_1), .q(pc_pc_cfg_sl_thold_0) @@ -343,7 +356,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_slp_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_slp_sl_thold_3), .q(pc_pc_cfg_slp_sl_thold_2) @@ -352,7 +366,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_slp_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_slp_sl_thold_2), .q(pc_pc_cfg_slp_sl_thold_1) @@ -361,7 +376,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) cfg_slp_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_cfg_slp_sl_thold_1), .q(pc_pc_cfg_slp_sl_thold_0) @@ -373,7 +389,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) gptr_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_gptr_sl_thold_3), .q(pc_pc_gptr_sl_thold_2) @@ -382,7 +399,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) gptr_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_gptr_sl_thold_2), .q(pc_pc_gptr_sl_thold_1) @@ -391,7 +409,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) gptr_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_gptr_sl_thold_1), .q(pc_pc_gptr_sl_thold_0) @@ -403,7 +422,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) sg_3_2( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_sg_3), .q(pc_pc_sg_2) @@ -412,7 +432,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) sg_2_1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_sg_2), .q(pc_pc_sg_1) @@ -421,7 +442,8 @@ module pcq_clks_stg( tri_plat #(.WIDTH(1)) sg_1_0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_out_dc), .din(pc_pc_sg_1), .q(pc_pc_sg_0) diff --git a/dev/verilog/work/pcq_ctrl.v b/dev/verilog/work/pcq_ctrl.v index fd8fd78..835d2fd 100755 --- a/dev/verilog/work/pcq_ctrl.v +++ b/dev/verilog/work/pcq_ctrl.v @@ -41,7 +41,8 @@ module pcq_ctrl( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_dis_dc_b, input lcb_clkoff_dc_b, input lcb_mpw1_dc_b, @@ -264,7 +265,8 @@ module pcq_ctrl( tri_rlmlatch_p #(.INIT(1)) initactive( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -281,7 +283,8 @@ module pcq_ctrl( tri_rlmreg_p #(.WIDTH(HOLDCNTR_SIZE), .INIT(0)) holdcntr( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(initcntr_enabled), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -298,7 +301,8 @@ module pcq_ctrl( tri_rlmreg_p #(.WIDTH(INITCNTR_SIZE), .INIT(INITCNT_START)) initcntr( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(initcntr_enabled), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -315,7 +319,8 @@ module pcq_ctrl( tri_rlmlatch_p #(.INIT(0)) initerat( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(initcntr_enabled), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -332,7 +337,8 @@ module pcq_ctrl( tri_rlmreg_p #(.WIDTH(PMCTRLS_T0_SIZE), .INIT(0)) pmctrls_t0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -356,7 +362,8 @@ module pcq_ctrl( tri_rlmreg_p #(.WIDTH(PMCTRLS_T1_SIZE), .INIT(0)) pmctrls_t1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -376,7 +383,8 @@ module pcq_ctrl( tri_rlmreg_p #(.WIDTH(SPARECTRL_SIZE), .INIT(0)) sparectrl( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), diff --git a/dev/verilog/work/pcq_dbg.v b/dev/verilog/work/pcq_dbg.v index ed385e4..08fdf60 100755 --- a/dev/verilog/work/pcq_dbg.v +++ b/dev/verilog/work/pcq_dbg.v @@ -41,7 +41,8 @@ module pcq_dbg( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_dis_dc_b, input lcb_clkoff_dc_b, input lcb_mpw1_dc_b, @@ -336,7 +337,8 @@ module pcq_dbg( tri_rlmreg_p #(.WIDTH(RAMCTRL_SIZE), .INIT(0)) ramctrl( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rg_db_trace_bus_enable), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -353,7 +355,8 @@ module pcq_dbg( tri_rlmreg_p #(.WIDTH(SCMISC_SIZE), .INIT(0)) scmisc( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rg_db_trace_bus_enable), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -370,7 +373,8 @@ module pcq_dbg( tri_rlmreg_p #(.WIDTH(FIRMISC_SIZE), .INIT(0)) firmisc( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rg_db_trace_bus_enable), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -387,7 +391,8 @@ module pcq_dbg( tri_rlmreg_p #(.WIDTH(TRACEOUT_SIZE), .INIT(0)) traceout( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rg_db_trace_bus_enable), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -404,7 +409,8 @@ module pcq_dbg( tri_rlmreg_p #(.WIDTH(CORETRACE_SIZE), .INIT(0)) coretrace( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rg_db_trace_bus_enable), .thold_b(pc_pc_func_slp_sl_thold_0_b), .sg(pc_pc_sg_0), diff --git a/dev/verilog/work/pcq_local_fir2.v b/dev/verilog/work/pcq_local_fir2.v index 691e1bb..ca5fbeb 100755 --- a/dev/verilog/work/pcq_local_fir2.v +++ b/dev/verilog/work/pcq_local_fir2.v @@ -39,7 +39,8 @@ module pcq_local_fir2( // Include model build parameters `include "tri_a2o.vh" - nclk, + clk, + rst, vdd, gnd, lcb_clkoff_dc_b, @@ -89,9 +90,10 @@ module pcq_local_fir2( // Port Definitions //===================================================================== // Global lines for clocking and scan control - input [0:`NCLK_WIDTH-1] nclk; inout vdd; inout gnd; + input clk; + input rst; input lcb_clkoff_dc_b; //from lcb_cntl external to component input lcb_mpw1_dc_b; //from lcb_cntl external to component input lcb_mpw2_dc_b; //from lcb_cntl external to component @@ -221,7 +223,8 @@ module pcq_local_fir2( .delay_lclkr(lcb_delay_lclkr_dc), .mpw1_b(lcb_mpw1_dc_b), .mpw2_b(lcb_mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_force), .sg(lcb_sg_0), .thold_b(func_thold_b), @@ -250,7 +253,8 @@ module pcq_local_fir2( .delay_lclkr(lcb_delay_lclkr_dc), .mpw1_b(lcb_mpw1_dc_b), .mpw2_b(lcb_mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(mode_force), .sg(lcb_sg_0), .thold_b(mode_thold_b), @@ -266,7 +270,8 @@ module pcq_local_fir2( .delay_lclkr(lcb_delay_lclkr_dc), .mpw1_b(lcb_mpw1_dc_b), .mpw2_b(lcb_mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(mode_force), .sg(lcb_sg_0), .thold_b(mode_thold_b), diff --git a/dev/verilog/work/pcq_regs.v b/dev/verilog/work/pcq_regs.v index 50bd9d6..41a0738 100755 --- a/dev/verilog/work/pcq_regs.v +++ b/dev/verilog/work/pcq_regs.v @@ -41,7 +41,8 @@ module pcq_regs( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input scan_dis_dc_b, input lcb_clkoff_dc_b, input lcb_d_mode_dc, @@ -676,7 +677,8 @@ module pcq_regs( //===================================================================== tri_serial_scom2 #(.WIDTH(SCOM_WIDTH), .INTERNAL_ADDR_DECODE(1'b0), .PIPELINE_PARITYCHK(1'b0)) scomsat( // Global lines for clocking and cop control - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .scom_func_thold(lcb_func_slp_sl_thold_0), @@ -1499,7 +1501,8 @@ module pcq_regs( pcq_regs_fir fir_regs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .lcb_clkoff_dc_b(lcb_clkoff_dc_b), .lcb_mpw1_dc_b(lcb_mpw1_dc_b), .lcb_mpw2_dc_b(lcb_mpw2_dc_b), @@ -1683,7 +1686,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(ARDSR_SIZE), .INIT(0)) axrv_dbgsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1700,7 +1704,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(IDSR_SIZE), .INIT(0)) iu_dbgsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1717,7 +1722,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(MPDSR_SIZE), .INIT(0)) mmpc_dbgsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1734,7 +1740,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(XDSR_SIZE), .INIT(0)) xu_dbgsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1751,7 +1758,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(LDSR_SIZE), .INIT(0)) lq_dbgsel_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1768,7 +1776,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(PCCR0_SIZE), .INIT(0)) pccr0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1785,7 +1794,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(RECERRCNTR_SIZE), .INIT(0)) rec_err_cntr( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1802,7 +1812,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) pccr0_par( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1819,7 +1830,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(DCFG_STAGE1_SIZE), .INIT(0)) dcfg_stage1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1838,7 +1850,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(THRCTL1_SIZE), .INIT(0)) thrctl1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1855,7 +1868,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(THRCTL2_SIZE), .INIT(0)) thrctl2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1872,7 +1886,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT(0)) spattn_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1889,7 +1904,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT({SPATTN_USED {1'b1}})) spattn_mask_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1906,7 +1922,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(1), .INIT(SPATTN_PARITY_INIT)) spattn_par( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1923,7 +1940,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T0_SIZE), .INIT(1)) bcfg_stage1_t0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1946,7 +1964,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T0_SIZE), .INIT(0)) bcfg_stage2_t0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(debug_mode_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1967,7 +1986,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(ERRDBG_T0_SIZE), .INIT(0)) errdbg_t0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -1988,7 +2008,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T1_SIZE), .INIT(1)) bcfg_stage1_t1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2011,7 +2032,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T1_SIZE), .INIT(0)) bcfg_stage2_t1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(debug_mode_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2030,7 +2052,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(ERRDBG_T1_SIZE), .INIT(0)) errdbg_t1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_act), .thold_b(lcb_cfg_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2063,7 +2086,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(RAMI_SIZE), .INIT(0)) rami_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_wr_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2081,7 +2105,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(RAMC_SIZE), .INIT(0)) ramc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ram_ctrl_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2099,7 +2124,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(RAMD_SIZE), .INIT(0)) ramd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ram_data_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2117,7 +2143,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(FU_RAM_DIN_SIZE), .INIT(0)) fu_ram_din( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(fu_pc_ram_data_val), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2135,7 +2162,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(XU_RAM_DIN_SIZE), .INIT(0)) xu_ram_din( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(xu_pc_ram_data_val), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2153,7 +2181,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(LQ_RAM_DIN_SIZE), .INIT(0)) lq_ram_din( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(lq_pc_ram_data_val), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2171,7 +2200,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(ERRINJ_SIZE), .INIT(0)) errinj_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(errinj_enab_scom_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2189,7 +2219,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(SCOM_MISC_SIZE), .INIT(0)) sc_misc( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2210,7 +2241,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(64), .INIT(0)) scaddr_dec( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(scom_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2227,7 +2259,8 @@ module pcq_regs( tri_rlmreg_p #(.WIDTH(FUNC_STAGE1_SIZE), .INIT(0)) func_stage1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2244,7 +2277,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T0_SIZE), .INIT(0)) inj_stage1_t0( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(errinj_enab_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2286,7 +2320,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T1_SIZE), .INIT(0)) inj_stage1_t1( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(errinj_enab_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2311,7 +2346,8 @@ module pcq_regs( tri_ser_rlmreg_p #(.WIDTH(FUNC_STAGE3_SIZE), .INIT(0)) func_stage3( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(ram_enab_act), .thold_b(lcb_func_slp_sl_thold_0_b), .sg(lcb_sg_0), @@ -2345,7 +2381,8 @@ module pcq_regs( .vd(vdd), .gd(gnd), .delay_lclkr(lcb_delay_lclkr_dc), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(cfg_slat_force), .thold_b(cfg_slat_thold_b), .dclk(cfg_slat_d2clk), @@ -2369,7 +2406,8 @@ module pcq_regs( .delay_lclkr(lcb_delay_lclkr_dc), .mpw1_b(lcb_mpw1_dc_b), .mpw2_b(lcb_mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(force_cfgslp), .sg(lcb_sg_0), .thold_b(lcb_cfg_slp_sl_thold_0_b), diff --git a/dev/verilog/work/pcq_regs_fir.v b/dev/verilog/work/pcq_regs_fir.v index 69f30e3..6546f8b 100755 --- a/dev/verilog/work/pcq_regs_fir.v +++ b/dev/verilog/work/pcq_regs_fir.v @@ -41,7 +41,8 @@ module pcq_regs_fir( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input lcb_clkoff_dc_b, input lcb_mpw1_dc_b, input lcb_mpw2_dc_b, @@ -384,7 +385,8 @@ module pcq_regs_fir( .FIR_ACTION1_PAR_INIT(FIR0ACT1_PAR_INIT) ) FIR0( // Global lines for clocking and scan control - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .lcb_clkoff_dc_b(lcb_clkoff_dc_b), @@ -461,7 +463,8 @@ module pcq_regs_fir( .FIR_ACTION1_PAR_INIT(FIR1ACT1_PAR_INIT) ) FIR1( // Global lines for clocking and scan control - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .lcb_clkoff_dc_b(lcb_clkoff_dc_b), @@ -532,7 +535,8 @@ module pcq_regs_fir( .FIR_ACTION1_PAR_INIT(FIR2ACT1_PAR_INIT) ) FIR2( // Global lines for clocking and scan control - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .lcb_clkoff_dc_b(lcb_clkoff_dc_b), @@ -968,7 +972,8 @@ module pcq_regs_fir( .delay_lclkr(lcb_delay_lclkr_dc), .mpw1_b(lcb_mpw1_dc_b), .mpw2_b(lcb_mpw2_dc_b), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_force), .sg(lcb_sg_0), .thold_b(func_thold_b), diff --git a/dev/verilog/work/pcq_spr.v b/dev/verilog/work/pcq_spr.v index a4c087f..2c0a7c5 100755 --- a/dev/verilog/work/pcq_spr.v +++ b/dev/verilog/work/pcq_spr.v @@ -41,7 +41,8 @@ module pcq_spr( inout vdd, inout gnd, - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // pervasive signals input scan_dis_dc_b, input lcb_clkoff_dc_b, @@ -221,7 +222,8 @@ module pcq_spr( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -238,7 +240,8 @@ module pcq_spr( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -255,7 +258,8 @@ module pcq_spr( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -272,7 +276,8 @@ module pcq_spr( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -289,7 +294,8 @@ module pcq_spr( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -306,7 +312,8 @@ module pcq_spr( tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(slowspr_val_d), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -323,7 +330,8 @@ module pcq_spr( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -340,7 +348,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(CESR1_SIZE), .INIT(0)) cesr1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cesr1_wren), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -357,7 +366,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(CESR1_IS0_SIZE), .INIT(0)) cesr1_is0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cesr1_is_wren[0]), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -374,7 +384,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(CESR1_IS1_SIZE), .INIT(0)) cesr1_is1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(cesr1_is_wren[1]), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -391,7 +402,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(RESR1_SIZE), .INIT(0)) resr1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(resr1_wren), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -408,7 +420,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(RESR2_SIZE), .INIT(0)) resr2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(resr2_wren), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -425,7 +438,8 @@ module pcq_spr( tri_ser_rlmreg_p #(.WIDTH(SRAMD_SIZE), .INIT(0)) sramd_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(sramd_wren), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), @@ -442,7 +456,8 @@ module pcq_spr( tri_rlmreg_p #(.WIDTH(MISC_SIZE), .INIT(0)) misc_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(pc_pc_func_sl_thold_0_b), .sg(pc_pc_sg_0), diff --git a/dev/verilog/work/rv.v b/dev/verilog/work/rv.v index 292555e..e88f142 100755 --- a/dev/verilog/work/rv.v +++ b/dev/verilog/work/rv.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -542,9 +542,8 @@ module rv( //------------------------------------------------------------------------------------------------------------ // Pervasive //------------------------------------------------------------------------------------------------------------ - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input[0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input rp_rv_ccflush_dc, input rp_rv_func_sl_thold_3, input rp_rv_gptr_sl_thold_3, @@ -1520,7 +1519,8 @@ module rv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .func_sl_thold_1(func_sl_thold_1), .sg_1(sg_1), .clkoff_b(clkoff_dc_b), @@ -1721,7 +1721,8 @@ module rv( .fx0_rvs_dbg_bus(fx0_rvs_dbg_bus), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .func_sl_thold_1(func_sl_thold_1), .sg_1(sg_1), .clkoff_b(clkoff_dc_b), @@ -1886,7 +1887,8 @@ module rv( .fx1_rvs_dbg_bus(fx1_rvs_dbg_bus), .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .func_sl_thold_1(func_sl_thold_1), .sg_1(sg_1), .clkoff_b(clkoff_dc_b), @@ -2047,7 +2049,8 @@ module rv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .func_sl_thold_1(func_sl_thold_1), .sg_1(sg_1), .clkoff_b(clkoff_dc_b), @@ -2190,7 +2193,8 @@ module rv( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .func_sl_thold_1(func_sl_thold_1), .sg_1(sg_1), .clkoff_b(clkoff_dc_b), @@ -2243,7 +2247,8 @@ module rv( tri_144x78_2r4w lqrf( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .delay_lclkr_dc(delay_lclkr_dc[0]), @@ -2409,7 +2414,8 @@ module rv( //------------------------------------------------------------------- // Pervasive //------------------------------------------------------------------- - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), @@ -2432,7 +2438,8 @@ module rv( rv_perv prv( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .rp_rv_ccflush_dc(rp_rv_ccflush_dc), diff --git a/dev/verilog/work/rv_axu0_rvs.v b/dev/verilog/work/rv_axu0_rvs.v index c8cad30..adea907 100755 --- a/dev/verilog/work/rv_axu0_rvs.v +++ b/dev/verilog/work/rv_axu0_rvs.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -182,8 +182,8 @@ module rv_axu0_rvs( inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input func_sl_thold_1, input sg_1, input clkoff_b, @@ -574,7 +574,8 @@ module rv_axu0_rvs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .ccflush_dc(ccflush_dc), @@ -636,7 +637,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -655,7 +657,8 @@ module rv_axu0_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_ord_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -674,7 +677,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex1_ord_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -693,7 +697,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex2_ord_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -712,7 +717,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex3_ord_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -733,7 +739,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -752,7 +759,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -771,7 +779,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) axu0_rv_itag_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -789,7 +798,8 @@ module rv_axu0_rvs( tri_rlmlatch_p #( .INIT(0)) axu0_rv_itag_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -808,7 +818,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) axu0_rv_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -827,7 +838,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -846,7 +858,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -865,7 +878,8 @@ module rv_axu0_rvs( tri_rlmlatch_p #(.INIT(0)) lq_rv_itag0_spec_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -884,7 +898,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -903,7 +918,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_itag2_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -922,7 +938,8 @@ module rv_axu0_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_itag2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -941,7 +958,8 @@ module rv_axu0_rvs( cp_next_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -972,7 +990,8 @@ module rv_axu0_rvs( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/rv_barf.v b/dev/verilog/work/rv_barf.v index 467e7a2..1fd987a 100755 --- a/dev/verilog/work/rv_barf.v +++ b/dev/verilog/work/rv_barf.v @@ -14,23 +14,23 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns //----------------------------------------------------------------------------------------------------- // Title: rv_station12.vhdl -// Desc: Paramaterizable reservation station +// Desc: Parameterizable reservation station //----------------------------------------------------------------------------------------------------- module rv_barf( w0_dat, @@ -44,7 +44,8 @@ module rv_barf( r0_dat, vdd, gnd, - nclk, + clk, + rst, sg_1, func_sl_thold_1, ccflush_dc, @@ -80,7 +81,8 @@ module rv_barf( // pervasive inout vdd; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_1; input func_sl_thold_1; input ccflush_dc; @@ -216,7 +218,8 @@ module rv_barf( perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0[n], sg_0[n]}) @@ -238,7 +241,8 @@ module rv_barf( q_dat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b[n]), .sg(sg_0[n]), diff --git a/dev/verilog/work/rv_dep.v b/dev/verilog/work/rv_dep.v index b3caa82..40ae8bf 100755 --- a/dev/verilog/work/rv_dep.v +++ b/dev/verilog/work/rv_dep.v @@ -115,8 +115,8 @@ module rv_dep( //------------------------------------------------------------------------------------------------------------ inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input func_sl_thold_1, input sg_1, @@ -247,7 +247,8 @@ module rv_dep( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .chip_b_sl_sg_0_t(sg_0), .chip_b_sl_2_thold_0_b(func_sl_thold_0_b), .force_t(force_t), @@ -309,7 +310,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -326,7 +328,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(7), .INIT(0) ) xx_rv_itag_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -344,7 +347,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -361,7 +365,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -378,7 +383,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary2_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -395,7 +401,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary3_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -412,7 +419,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary4_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -429,7 +437,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary5_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -446,7 +455,8 @@ module rv_dep( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC-2), .INIT(0)) xx_rv_itag_ary6_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -477,7 +487,8 @@ module rv_dep( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1,sg_1}), .q({func_sl_thold_0,sg_0}) diff --git a/dev/verilog/work/rv_dep_scard.v b/dev/verilog/work/rv_dep_scard.v index 05812f7..602d22e 100755 --- a/dev/verilog/work/rv_dep_scard.v +++ b/dev/verilog/work/rv_dep_scard.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -68,7 +68,8 @@ module rv_dep_scard( i1_s3_itag_v, vdd, gnd, - nclk, + clk, + rst, chip_b_sl_sg_0_t, chip_b_sl_2_thold_0_b, force_t, @@ -141,8 +142,8 @@ module rv_dep_scard( //------------------------------------------------------------------------------------------------------------ inout vdd; inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input chip_b_sl_sg_0_t; input chip_b_sl_2_thold_0_b; input force_t; @@ -270,7 +271,8 @@ module rv_dep_scard( tri_rlmreg_p #(.WIDTH(num_entries_g), .INIT(0) ) scorecard_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv0_sc_act), .thold_b(chip_b_sl_2_thold_0_b), .sg(chip_b_sl_sg_0_t), diff --git a/dev/verilog/work/rv_deps.v b/dev/verilog/work/rv_deps.v index 0494309..70ed201 100755 --- a/dev/verilog/work/rv_deps.v +++ b/dev/verilog/work/rv_deps.v @@ -563,8 +563,8 @@ module rv_deps( //------------------------------------------------------------------------------------------------------------ inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input func_sl_thold_1, input sg_1, @@ -1574,7 +1574,8 @@ module rv_deps( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .clkoff_b(clkoff_b), @@ -1687,7 +1688,8 @@ module rv_deps( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .clkoff_b(clkoff_b), @@ -2586,7 +2588,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2604,7 +2607,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2623,7 +2627,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_lq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2642,7 +2647,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_sq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2661,7 +2667,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_fx0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2680,7 +2687,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_fx1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2699,7 +2707,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_axu0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2718,7 +2727,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_rte_axu1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2737,7 +2747,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t0_i0_instr_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2756,7 +2767,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t0_i0_ifar_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2775,7 +2787,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2794,7 +2807,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_2ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2813,7 +2827,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t0_i0_ucode_cnt_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2832,7 +2847,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2851,7 +2867,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2870,7 +2887,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_cord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2889,7 +2907,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_spec_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2908,7 +2927,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2927,7 +2947,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2946,7 +2967,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2965,7 +2987,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2984,7 +3007,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3003,7 +3027,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3022,7 +3047,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_t3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3041,7 +3067,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_t3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3060,7 +3087,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_t3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3079,7 +3107,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3098,7 +3127,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3117,7 +3147,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3136,7 +3167,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3155,7 +3187,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3174,7 +3207,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3193,7 +3227,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_s3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3212,7 +3247,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i0_s3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3231,7 +3267,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i0_s3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3250,7 +3287,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3269,7 +3307,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s2_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3288,7 +3327,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i0_s3_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3307,7 +3347,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i0_ilat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3326,7 +3367,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t0_i0_branch_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3344,7 +3386,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_isLoad_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3363,7 +3406,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i0_isStore_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3384,7 +3428,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i0_spare_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3403,7 +3448,8 @@ module rv_deps( tri_rlmlatch_p #( .INIT(0)) rv0_t0_i1_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3422,7 +3468,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_lq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3441,7 +3488,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_sq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3460,7 +3508,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_fx0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3479,7 +3528,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_fx1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3498,7 +3548,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_axu0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3517,7 +3568,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_rte_axu1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3536,7 +3588,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t0_i1_instr_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3555,7 +3608,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t0_i1_ifar_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3574,7 +3628,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3595,7 +3650,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t0_i1_ucode_cnt_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3614,7 +3670,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t0_i1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3633,7 +3690,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3652,7 +3710,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_cord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3671,7 +3730,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_spec_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3690,7 +3750,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3709,7 +3770,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3728,7 +3790,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3747,7 +3810,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3766,7 +3830,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3785,7 +3850,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3804,7 +3870,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_t3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3823,7 +3890,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_t3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3842,7 +3910,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_t3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3861,7 +3930,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3880,7 +3950,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3899,7 +3970,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3918,7 +3990,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3937,7 +4010,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3956,7 +4030,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3975,7 +4050,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_s3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3994,7 +4070,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t0_i1_s3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4013,7 +4090,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t0_i1_s3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4033,7 +4111,8 @@ module rv_deps( rv0_t0_i1_s1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4053,7 +4132,8 @@ module rv_deps( rv0_t0_i1_s2_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4073,7 +4153,8 @@ module rv_deps( rv0_t0_i1_s3_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4091,7 +4172,8 @@ module rv_deps( rv0_t0_i1_s1_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4110,7 +4192,8 @@ module rv_deps( rv0_t0_i1_s2_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4129,7 +4212,8 @@ module rv_deps( rv0_t0_i1_s3_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4149,7 +4233,8 @@ module rv_deps( rv0_t0_i1_ilat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4169,7 +4254,8 @@ module rv_deps( rv0_t0_i1_branch_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4187,7 +4273,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_isLoad_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4206,7 +4293,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t0_i1_isStore_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4227,7 +4315,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t0_i1_spare_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t0_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4254,7 +4343,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4273,7 +4363,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_lq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4292,7 +4383,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_sq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4311,7 +4403,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_fx0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4330,7 +4423,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_fx1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4349,7 +4443,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_axu0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4368,7 +4463,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_rte_axu1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4387,7 +4483,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t1_i0_instr_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4406,7 +4503,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t1_i0_ifar_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4425,7 +4523,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4444,7 +4543,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_2ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4463,7 +4563,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t1_i0_ucode_cnt_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4482,7 +4583,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4501,7 +4603,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4520,7 +4623,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_cord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4539,7 +4643,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_spec_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4558,7 +4663,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4577,7 +4683,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4596,7 +4703,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4615,7 +4723,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4634,7 +4743,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4653,7 +4763,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4672,7 +4783,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_t3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4691,7 +4803,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_t3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4710,7 +4823,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_t3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4729,7 +4843,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4748,7 +4863,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4767,7 +4883,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4786,7 +4903,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4805,7 +4923,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4824,7 +4943,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4843,7 +4963,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_s3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4862,7 +4983,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i0_s3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4881,7 +5003,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i0_s3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4900,7 +5023,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4919,7 +5043,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s2_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4938,7 +5063,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i0_s3_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4957,7 +5083,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i0_ilat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4976,7 +5103,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t1_i0_branch_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -4994,7 +5122,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_isLoad_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5013,7 +5142,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i0_isStore_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5034,7 +5164,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i0_spare_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5053,7 +5184,8 @@ module rv_deps( tri_rlmlatch_p #( .INIT(0)) rv0_t1_i1_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5072,7 +5204,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_lq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5091,7 +5224,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_sq_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5110,7 +5244,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_fx0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5129,7 +5264,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_fx1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5148,7 +5284,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_axu0_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5167,7 +5304,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_rte_axu1_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5186,7 +5324,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) rv0_t1_i1_instr_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5205,7 +5344,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) rv0_t1_i1_ifar_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5224,7 +5364,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_ucode_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5245,7 +5386,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`UCODE_ENTRIES_ENC), .INIT(0)) rv0_t1_i1_ucode_cnt_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5264,7 +5406,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5283,7 +5426,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5302,7 +5446,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_cord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5321,7 +5466,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_spec_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5340,7 +5486,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5359,7 +5506,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5378,7 +5526,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5397,7 +5546,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5416,7 +5566,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5435,7 +5586,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5454,7 +5606,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_t3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5473,7 +5626,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_t3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5492,7 +5646,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_t3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5511,7 +5666,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5530,7 +5686,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s1_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5549,7 +5706,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s1_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5568,7 +5726,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5587,7 +5746,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s2_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5606,7 +5766,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s2_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5625,7 +5786,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_s3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5644,7 +5806,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) rv0_t1_i1_s3_p_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5663,7 +5826,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) rv0_t1_i1_s3_t_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5682,7 +5846,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5701,7 +5866,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s2_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5720,7 +5886,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) rv0_t1_i1_s3_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5739,7 +5906,8 @@ module rv_deps( rv0_t1_i1_s1_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5758,7 +5926,8 @@ module rv_deps( rv0_t1_i1_s2_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5777,7 +5946,8 @@ module rv_deps( rv0_t1_i1_s3_dep_hit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5796,7 +5966,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i1_ilat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5815,7 +5986,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(`G_BRANCH_LEN), .INIT(0)) rv0_t1_i1_branch_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5833,7 +6005,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_isLoad_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5852,7 +6025,8 @@ module rv_deps( tri_rlmlatch_p #(.INIT(0)) rv0_t1_i1_isStore_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5873,7 +6047,8 @@ module rv_deps( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) rv0_t1_i1_spare_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(iu6_t1_i1_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5910,7 +6085,8 @@ module rv_deps( rv0_instr_i0_flushed_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5930,7 +6106,8 @@ module rv_deps( rv0_instr_i1_flushed_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5950,7 +6127,8 @@ module rv_deps( rv1_lq_instr_i0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5971,7 +6149,8 @@ module rv_deps( rv1_lq_instr_i0_rte_lq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -5991,7 +6170,8 @@ rv1_lq_instr_i0_rte_lq_reg( rv1_lq_instr_i0_rte_sq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6010,7 +6190,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_ucode_preissue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6028,7 +6209,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6047,7 +6229,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6066,7 +6249,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_s3_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6085,7 +6269,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_isLoad_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6103,7 +6288,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_isStore_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6122,7 +6308,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6141,7 +6328,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i0_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6161,7 +6349,8 @@ rv1_lq_instr_i0_rte_sq_reg( rv1_lq_instr_i1_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6182,7 +6371,8 @@ rv1_lq_instr_i1_vld_reg( rv1_lq_instr_i1_rte_lq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6202,7 +6392,8 @@ rv1_lq_instr_i1_vld_reg( rv1_lq_instr_i1_rte_sq_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6221,7 +6412,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_ucode_preissue_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6239,7 +6431,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_2ucode_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6258,7 +6451,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_ucode_cnt_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6277,7 +6471,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_s3_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6296,7 +6491,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_isLoad_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6314,7 +6510,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_isStore_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6333,7 +6530,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6352,7 +6550,8 @@ rv1_lq_instr_i1_rte_sq_reg( rv1_lq_instr_i1_ifar_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -6382,7 +6581,8 @@ rv1_lq_instr_i1_rte_sq_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1,sg_1}), .q({func_sl_thold_0,sg_0}) diff --git a/dev/verilog/work/rv_fx0_rvs.v b/dev/verilog/work/rv_fx0_rvs.v index b6abd12..4a0354f 100755 --- a/dev/verilog/work/rv_fx0_rvs.v +++ b/dev/verilog/work/rv_fx0_rvs.v @@ -246,8 +246,8 @@ module rv_fx0_rvs( output [0:31] fx0_rvs_dbg_bus, inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input func_sl_thold_1, input sg_1, input clkoff_b, @@ -637,7 +637,8 @@ module rv_fx0_rvs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .ccflush_dc(ccflush_dc), @@ -744,7 +745,8 @@ module rv_fx0_rvs( ex0_is_brick_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -764,7 +766,8 @@ module rv_fx0_rvs( ex0_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -784,7 +787,8 @@ module rv_fx0_rvs( ex0_ord_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -804,7 +808,8 @@ module rv_fx0_rvs( ex0_t1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -826,7 +831,8 @@ module rv_fx0_rvs( ex0_t1_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -846,7 +852,8 @@ module rv_fx0_rvs( ex0_t2_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -866,7 +873,8 @@ module rv_fx0_rvs( ex0_t2_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -886,7 +894,8 @@ module rv_fx0_rvs( ex0_t3_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -906,7 +915,8 @@ module rv_fx0_rvs( ex0_t3_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -926,7 +936,8 @@ module rv_fx0_rvs( ex0_s1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -946,7 +957,8 @@ module rv_fx0_rvs( ex0_s2_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -966,7 +978,8 @@ module rv_fx0_rvs( ex0_s2_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -986,7 +999,8 @@ module rv_fx0_rvs( ex0_s3_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1006,7 +1020,8 @@ module rv_fx0_rvs( ex0_s3_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1027,7 +1042,8 @@ module rv_fx0_rvs( cp_next_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1058,7 +1074,8 @@ module rv_fx0_rvs( perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/rv_fx1_rvs.v b/dev/verilog/work/rv_fx1_rvs.v index ff26526..09b524f 100755 --- a/dev/verilog/work/rv_fx1_rvs.v +++ b/dev/verilog/work/rv_fx1_rvs.v @@ -219,8 +219,8 @@ module rv_fx1_rvs( inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input func_sl_thold_1, input sg_1, input clkoff_b, @@ -612,7 +612,8 @@ module rv_fx1_rvs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .ccflush_dc(ccflush_dc), @@ -693,7 +694,8 @@ module rv_fx1_rvs( ex0_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -714,7 +716,8 @@ module rv_fx1_rvs( ex0_t1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -734,7 +737,8 @@ module rv_fx1_rvs( ex0_t2_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -754,7 +758,8 @@ module rv_fx1_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_t3_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -774,7 +779,8 @@ module rv_fx1_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_s1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -793,7 +799,8 @@ module rv_fx1_rvs( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex0_s3_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -827,7 +834,8 @@ module rv_fx1_rvs( perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/rv_lq_rvs.v b/dev/verilog/work/rv_lq_rvs.v index d0c4159..a859d46 100755 --- a/dev/verilog/work/rv_lq_rvs.v +++ b/dev/verilog/work/rv_lq_rvs.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -218,9 +218,8 @@ module rv_lq_rvs( inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input func_sl_thold_1, input sg_1, input clkoff_b, @@ -628,7 +627,8 @@ module rv_lq_rvs( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_1(sg_1), .func_sl_thold_1(func_sl_thold_1), .ccflush_dc(ccflush_dc), @@ -710,7 +710,8 @@ module rv_lq_rvs( cp_flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -728,7 +729,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_s1_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -745,7 +747,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_s2_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -764,7 +767,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex0_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -784,7 +788,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_spec_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -803,7 +808,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_t1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -821,7 +827,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_s1_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -840,7 +847,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) ex0_s2_v_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -859,7 +867,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex0_s2_t_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(rv_ex0_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -878,7 +887,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag0_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -895,7 +905,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) lq_rv_ext_itag0_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -913,7 +924,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -931,7 +943,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag1_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -948,7 +961,8 @@ module rv_lq_rvs( tri_rlmlatch_p #(.INIT(0)) lq_rv_ext_itag1_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -966,7 +980,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -984,7 +999,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_rv_ext_itag2_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1002,7 +1018,8 @@ module rv_lq_rvs( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_rv_ext_itag2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1022,7 +1039,8 @@ module rv_lq_rvs( cp_next_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1054,7 +1072,8 @@ module rv_lq_rvs( perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0 ,sg_0}) diff --git a/dev/verilog/work/rv_perv.v b/dev/verilog/work/rv_perv.v index ecb0974..1fffe02 100755 --- a/dev/verilog/work/rv_perv.v +++ b/dev/verilog/work/rv_perv.v @@ -39,9 +39,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg inout vdd, inout gnd, - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, input rp_rv_ccflush_dc, input rp_rv_func_sl_thold_3, input rp_rv_gptr_sl_thold_3, @@ -187,7 +186,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg perv_3to2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(rp_rv_ccflush_dc), .din({rp_rv_func_sl_thold_3, rp_rv_gptr_sl_thold_3, rp_rv_sg_3, rp_rv_fce_3}), .q({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2}) @@ -198,7 +198,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(rp_rv_ccflush_dc), .din({func_sl_thold_2, gptr_sl_thold_2, sg_2, fce_2}), .q({func_sl_thold_1_int, gptr_sl_thold_1, sg_1_int, fce_1}) @@ -212,7 +213,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(rp_rv_ccflush_dc), .din({gptr_sl_thold_1 , func_sl_thold_1_int, sg_1_int}), .q({gptr_sl_thold_0, func_sl_thold_0, sg_0}) @@ -245,7 +247,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_scan_in), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -264,7 +267,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg .vdd(vdd), .gnd(gnd), .sg(sg_0), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_in(gptr_sio), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), @@ -369,7 +373,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg debug_bus_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trc_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -387,7 +392,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg debug_mux_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trc_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -405,7 +411,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg event_bus_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(evt_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -423,7 +430,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg event_count_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(evt_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -441,7 +449,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg spr_msr_gs_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(evt_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -459,7 +468,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg spr_msr_pr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(evt_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -477,7 +487,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg event_mux_ctrls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(evt_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -495,7 +506,8 @@ module rv_perv( // 0 = ibm umbra, 1 = xilinx, 2 = ibm mpg core_trace_ctrls_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(trc_act), .thold_b(func_sl_thold_0_b), .sg(sg_0), diff --git a/dev/verilog/work/rv_rf_byp.v b/dev/verilog/work/rv_rf_byp.v index f1eaae0..b159dfb 100755 --- a/dev/verilog/work/rv_rf_byp.v +++ b/dev/verilog/work/rv_rf_byp.v @@ -14,17 +14,17 @@ // necessary for implementation of the Work that are available from OpenPOWER // via the Power ISA End User License Agreement (EULA) are explicitly excluded // hereunder, and may be obtained from OpenPOWER under the terms and conditions -// of the EULA. +// of the EULA. // // Unless required by applicable law or agreed to in writing, the reference design // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // for the specific language governing permissions and limitations under the License. -// +// // Additional rights, including the ability to physically implement a softcore that // is compliant with the required sections of the Power ISA Specification, are // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be -// obtained (along with the Power ISA) here: https://openpowerfoundation.org. +// obtained (along with the Power ISA) here: https://openpowerfoundation.org. `timescale 1 ns / 1 ns @@ -184,10 +184,10 @@ module rv_rf_byp( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -1580,7 +1580,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_t1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1608,7 +1609,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_t2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1636,7 +1638,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_t3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1658,7 +1661,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_s1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -1677,7 +1681,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_s2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -1696,7 +1701,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu0_s3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -1721,7 +1727,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) lq_t1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1750,7 +1757,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) lq_t3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1772,7 +1780,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) lq_s1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1791,7 +1800,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) lq_s2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1816,7 +1826,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_t1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1844,7 +1855,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_t2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1872,7 +1884,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_t3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1894,7 +1907,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_s1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -1913,7 +1927,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_s2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -1932,7 +1947,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(elmnt_width), .INIT(0), .NEEDS_SRESET(1)) fxu1_s3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -1957,7 +1973,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) rel_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1977,7 +1994,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) rel_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2000,7 +2018,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2025,7 +2044,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_is_brick_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[i]), @@ -2053,7 +2073,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) fx0_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2082,7 +2103,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[i]), @@ -2105,7 +2127,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex0_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -2125,7 +2148,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex1_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[1]), @@ -2145,7 +2169,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex2_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[2]), @@ -2165,7 +2190,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex3_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[3]), @@ -2185,7 +2211,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex4_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[4]), @@ -2205,7 +2232,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex5_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[5]), @@ -2225,7 +2253,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex6_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[6]), @@ -2245,7 +2274,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex7_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[7]), @@ -2265,7 +2295,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) fx0_ex8_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[8]), @@ -2284,7 +2315,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_rel_itag_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2304,7 +2336,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_rel_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2324,7 +2357,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ext_rel_itag_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2344,7 +2378,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_ext_rel_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2364,7 +2399,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_ext_itag0_sel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2384,7 +2420,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) fx0_need_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2404,7 +2441,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex3_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2424,7 +2462,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex4_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2444,7 +2483,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex5_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2464,7 +2504,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex6_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2484,7 +2525,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex7_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2504,7 +2546,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_ex8_ord_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2525,7 +2568,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx0_release_ord_hold_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2545,7 +2589,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_ex0_ord_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -2565,7 +2610,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_ex1_ord_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[1]), @@ -2584,7 +2630,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_ex2_ord_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[2]), @@ -2602,7 +2649,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx0_ex3_ord_flush_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[3]), @@ -2621,7 +2669,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_sched_rel_pri_or_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2639,7 +2688,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx0_rel_itag_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2658,7 +2708,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_ext_rel_itag_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2676,7 +2727,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx0_ex5_recircd_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2694,7 +2746,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx0_ex6_recircd_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2712,7 +2765,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx0_ex7_recircd_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2737,7 +2791,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[i]), @@ -2767,7 +2822,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) fx1_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2796,7 +2852,8 @@ module rv_rf_byp( begin : fxu1_itag_gen tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[i]), @@ -2819,7 +2876,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex0_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -2839,7 +2897,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex1_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[1]), @@ -2859,7 +2918,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex2_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[2]), @@ -2879,7 +2939,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex3_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[3]), @@ -2899,7 +2960,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex4_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[4]), @@ -2918,7 +2980,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex5_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[5]), @@ -2937,7 +3000,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) fx1_ex6_ilat_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[6]), @@ -2957,7 +3021,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx1_rel_itag_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2977,7 +3042,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_rel_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2997,7 +3063,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) fx1_ext_rel_itag_vld_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3017,7 +3084,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_ext_rel_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3037,7 +3105,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ext_itag0_sel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3057,7 +3126,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ex0_need_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3077,7 +3147,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ex1_need_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3097,7 +3168,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ex2_need_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3117,7 +3189,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ex3_need_rel_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3136,7 +3209,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ex1_stq_pipe_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3154,7 +3228,8 @@ module rv_rf_byp( ); tri_rlmlatch_p #(.INIT(0)) fx1_ex2_stq_pipe_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3173,7 +3248,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_sched_rel_pri_or_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3192,7 +3268,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_rel_itag_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3211,7 +3288,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx1_ext_rel_itag_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3236,7 +3314,8 @@ module rv_rf_byp( tri_rlmlatch_p #(.INIT(0)) fx0_abort_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[i]), @@ -3259,7 +3338,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_ex0_s1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -3278,7 +3358,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_ex0_s2_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -3297,7 +3378,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx0_ex0_s3_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx0_act[0]), @@ -3316,7 +3398,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_ex0_s1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -3337,7 +3420,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_ex0_s2_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -3357,7 +3441,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) fx1_ex0_s3_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(fx1_act[0]), @@ -3382,7 +3467,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) lq_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -3410,7 +3496,8 @@ module rv_rf_byp( tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) lq_itag_reg( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq_act[i]), @@ -3443,7 +3530,8 @@ module rv_rf_byp( tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/rv_station.v b/dev/verilog/work/rv_station.v index 097f1bf..204307b 100755 --- a/dev/verilog/work/rv_station.v +++ b/dev/verilog/work/rv_station.v @@ -137,7 +137,8 @@ module rv_station( rvs_dbg_bus, vdd, gnd, - nclk, + clk, + rst, sg_1, func_sl_thold_1, ccflush_dc, @@ -275,8 +276,8 @@ module rv_station( // pervasive inout vdd; inout gnd; - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input sg_1; input func_sl_thold_1; input ccflush_dc; @@ -693,7 +694,8 @@ module rv_station( .w_act(w_act), .r0_addr(ex0_barf_addr_q), .r0_dat(ex0_instr_dat), - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .sg_1(sg_1), @@ -1531,7 +1533,8 @@ module rv_station( q_cord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_cord_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1598,7 +1601,8 @@ module rv_station( q_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1673,7 +1677,8 @@ module rv_station( q_spec_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1715,7 +1720,8 @@ module rv_station( tri_rlmlatch_p #(.INIT(0)) q_e_miss_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_e_miss_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1737,7 +1743,8 @@ module rv_station( lq_rv_itag1_restart_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1757,7 +1764,8 @@ module rv_station( lq_rv_itag1_hold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1777,7 +1785,8 @@ module rv_station( lq_rv_itag1_cord_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1797,7 +1806,8 @@ module rv_station( lq_rv_clr_hold_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1907,7 +1917,8 @@ module rv_station( q_hold_brick_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1927,7 +1938,8 @@ module rv_station( q_hold_brick_cnt_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1949,7 +1961,8 @@ module rv_station( q_is_brick_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -1968,7 +1981,8 @@ module rv_station( q_brick_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2535,7 +2549,8 @@ module rv_station( ex0_barf_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2559,7 +2574,8 @@ module rv_station( issued_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2577,7 +2593,8 @@ module rv_station( issued_addr_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2599,7 +2616,8 @@ module rv_station( xx_rv_ex3_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2617,7 +2635,8 @@ module rv_station( xx_rv_ex4_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2636,7 +2655,8 @@ module rv_station( flush_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2656,7 +2676,8 @@ module rv_station( flush2_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2682,7 +2703,8 @@ module rv_station( barf_ev_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2709,7 +2731,8 @@ module rv_station( xx_rv_rel_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2727,7 +2750,8 @@ module rv_station( xx_rv_rel_itag_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2749,7 +2773,8 @@ module rv_station( xx_rv_abort_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2773,7 +2798,8 @@ module rv_station( q_dat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2793,7 +2819,8 @@ module rv_station( q_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2815,7 +2842,8 @@ module rv_station( q_ilat_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2835,7 +2863,8 @@ module rv_station( q_tid_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2853,7 +2882,8 @@ module rv_station( q_bard_addr_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2873,7 +2903,8 @@ module rv_station( q_s1_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2893,7 +2924,8 @@ module rv_station( q_s2_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2913,7 +2945,8 @@ module rv_station( q_s3_itag_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2933,7 +2966,8 @@ module rv_station( q_s1_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2953,7 +2987,8 @@ module rv_station( q_s2_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2973,7 +3008,8 @@ module rv_station( q_s3_v_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(q_dat_act[n]), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -2993,7 +3029,8 @@ module rv_station( q_issued_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3012,7 +3049,8 @@ module rv_station( q_s1_rdy_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3032,7 +3070,8 @@ module rv_station( q_s2_rdy_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3052,7 +3091,8 @@ module rv_station( q_s3_rdy_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3083,7 +3123,8 @@ module rv_station( q_rdy_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3108,7 +3149,8 @@ module rv_station( lq_rv_itag1_rst_vld_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3128,7 +3170,8 @@ module rv_station( lq_rv_itag1_rst_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3149,7 +3192,8 @@ module rv_station( q_ev_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3169,7 +3213,8 @@ module rv_station( q_flushed_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3189,7 +3234,8 @@ module rv_station( q_credit_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3209,7 +3255,8 @@ module rv_station( ex1_credit_free_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3229,7 +3276,8 @@ module rv_station( rvs_empty_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3249,7 +3297,8 @@ module rv_station( q_hold_all_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3268,7 +3317,8 @@ module rv_station( q_hold_ord_q_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3287,7 +3337,8 @@ module rv_station( perf_bus_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3306,7 +3357,8 @@ module rv_station( dbg_bus_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .act(tiup), .thold_b(func_sl_thold_0_b), .sg(sg_0), @@ -3338,7 +3390,8 @@ module rv_station( perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(ccflush_dc), .din({func_sl_thold_1, sg_1}), .q({func_sl_thold_0, sg_0}) diff --git a/dev/verilog/work/xu.v b/dev/verilog/work/xu.v index 034e15e..2800f4f 100755 --- a/dev/verilog/work/xu.v +++ b/dev/verilog/work/xu.v @@ -38,8 +38,8 @@ module xu( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -947,7 +947,8 @@ module xu( xu0 xu0( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .pc_xu_ccflush_dc(pc_xu_ccflush_dc), @@ -1213,7 +1214,8 @@ module xu( xu1 xu1( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -1337,7 +1339,8 @@ module xu( xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(`CR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`CR_POOL * `THREADS), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -1391,7 +1394,8 @@ module xu( xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(`XER_POOL_ENC + `THREADS_POOL_ENC), .POOL(`XER_POOL * `THREADS), .RD_PORTS(3 + `THREADS), .WR_PORTS(2), .BYPASS(1)) xer( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -1440,7 +1444,8 @@ module xu( xu_rf #(.WIDTH(`GPR_WIDTH), .PAR_WIDTH(`GPR_WIDTH/8), .POOL_ENC(`BR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`BR_POOL * `THREADS), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -1474,7 +1479,8 @@ module xu( xu_rf #(.WIDTH(`GPR_WIDTH), .PAR_WIDTH(`GPR_WIDTH/8), .POOL_ENC(`CTR_POOL_ENC + `THREADS_POOL_ENC), .POOL(`CTR_POOL * `THREADS), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -1504,7 +1510,8 @@ module xu( xu_gpr gpr( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .pc_xu_ccflush_dc(pc_xu_ccflush_dc), @@ -1552,7 +1559,8 @@ module xu( xu_spr #(.hvmode(1), .a2mode(1)) spr( - .nclk(nclk), + .clk(clk), + .rst(rst), // CHIP IO .an_ac_chipid_dc(an_ac_chipid_dc), @@ -1908,7 +1916,8 @@ module xu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_pc_ram_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1921,7 +1930,8 @@ module xu( .dout(xu_pc_ram_done_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) xu_pc_ram_data_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(xu_pc_ram_done_d), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1934,7 +1944,8 @@ module xu( .dout(xu_pc_ram_data_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1947,7 +1958,8 @@ module xu( .dout(lq_xu_gpr_ex6_we_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_wa_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq_xu_ex5_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1960,7 +1972,8 @@ module xu( .dout(lq_xu_gpr_ex6_wa_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) lq_xu_gpr_ex6_wd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq_xu_ex5_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), diff --git a/dev/verilog/work/xu0.v b/dev/verilog/work/xu0.v index 5f5013a..5e71b31 100755 --- a/dev/verilog/work/xu0.v +++ b/dev/verilog/work/xu0.v @@ -38,7 +38,8 @@ module xu0 //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, inout vdd, inout gnd, @@ -508,7 +509,8 @@ module xu0 xu_alu alu( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -543,8 +545,9 @@ module xu0 ); - tri_st_popcnt pop( - .nclk(nclk), + tri_st_popcnt pop ( + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .delay_lclkr_dc(delay_lclkr_dc), @@ -583,7 +586,8 @@ module xu0 xu0_bcd bcd( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -616,7 +620,8 @@ module xu0 xu0_div_r4 div( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -650,7 +655,8 @@ module xu0 tri_st_mult mult( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -689,7 +695,8 @@ module xu0 xu0_br br( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .pc_br_func_sl_thold_2(1'b0), //<> .pc_br_sg_2(1'b1), //<> .clkoff_b(1'b1), //<> @@ -754,7 +761,8 @@ module xu0 xu0_byp byp( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -944,7 +952,8 @@ module xu0 xu0_dec dec( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), diff --git a/dev/verilog/work/xu0_bcd.v b/dev/verilog/work/xu0_bcd.v index f8a8e89..c82764c 100755 --- a/dev/verilog/work/xu0_bcd.v +++ b/dev/verilog/work/xu0_bcd.v @@ -36,7 +36,8 @@ module xu0_bcd( // Clocks - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Power inout vdd, @@ -201,7 +202,8 @@ module xu0_bcd( // Latches tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -219,7 +221,8 @@ module xu0_bcd( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_addg6s_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_bcd_ex1_val), @@ -237,7 +240,8 @@ module xu0_bcd( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_cdtbcd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_bcd_ex1_val), @@ -255,7 +259,8 @@ module xu0_bcd( ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) ex3_bcd_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_val_q), @@ -273,7 +278,8 @@ module xu0_bcd( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), diff --git a/dev/verilog/work/xu0_br.v b/dev/verilog/work/xu0_br.v index 35f529e..97d1bf6 100755 --- a/dev/verilog/work/xu0_br.v +++ b/dev/verilog/work/xu0_br.v @@ -41,7 +41,8 @@ module xu0_br( vdd, gnd, - nclk, + clk, + rst, pc_br_func_sl_thold_2, pc_br_sg_2, clkoff_b, @@ -116,7 +117,8 @@ module xu0_br( // pervasive inout vdd; inout gnd; - input [0:`NCLK_WIDTH-1] nclk; + input clk; + input rst; input pc_br_func_sl_thold_2; input pc_br_sg_2; input clkoff_b; @@ -1007,7 +1009,8 @@ endgenerate //----------------------------------------------- tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1026,7 +1029,8 @@ tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex0_vld_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_br_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1051,7 +1055,8 @@ generate tri_rlmreg_p #(.WIDTH((`EFF_IFAR_ARCH-`EFF_IFAR_WIDTH)), .INIT(0)) iu_br_flush_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_br_flush[i]), @@ -1073,7 +1078,8 @@ generate begin : q_depth_gen if((62-`EFF_IFAR_ARCH+n) > 31) tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) br_upper_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_br_flush_q[i]), @@ -1091,7 +1097,8 @@ generate ); else tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) br_upper_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_br_flush_q[i]), @@ -1112,7 +1119,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex4_itag_saved_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1134,7 +1142,8 @@ generate tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1153,7 +1162,8 @@ generate tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1172,7 +1182,8 @@ generate tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex3_cr3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1191,7 +1202,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_ctr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1209,7 +1221,8 @@ generate ); tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_lr1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1228,7 +1241,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex3_lr2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1247,7 +1261,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex1_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1266,7 +1281,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex1_fusion_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1285,7 +1301,8 @@ generate tri_rlmreg_p #(.WIDTH(32), .INIT(0)) ex1_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1304,7 +1321,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex1_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1323,7 +1341,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1342,7 +1361,8 @@ generate tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex1_lr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1361,7 +1381,8 @@ generate tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex1_ctr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1380,7 +1401,8 @@ generate tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex1_cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1399,7 +1421,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex1_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1418,7 +1441,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex1_bta_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1437,7 +1461,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex1_pred_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1456,7 +1481,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex1_ls_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1475,7 +1501,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex1_bh_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1494,7 +1521,8 @@ generate tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex1_gshare_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_act), @@ -1513,7 +1541,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex2_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1532,7 +1561,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex2_slow_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1551,7 +1581,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex2_fusion_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1570,7 +1601,8 @@ generate tri_rlmreg_p #(.WIDTH(32), .INIT(0)) ex2_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1589,7 +1621,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex2_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1608,7 +1641,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex2_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1627,7 +1661,8 @@ generate tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex2_lr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1646,7 +1681,8 @@ generate tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex2_ctr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1665,7 +1701,8 @@ generate tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex2_cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1684,7 +1721,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex2_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1703,7 +1741,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex2_bta_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1722,7 +1761,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex2_pred_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1741,7 +1781,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex2_ls_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1760,7 +1801,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex2_bh_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1779,7 +1821,8 @@ generate tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex2_gshare_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -1798,7 +1841,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex3_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1817,7 +1861,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_slow_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1836,7 +1881,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_fusion_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1855,7 +1901,8 @@ generate tri_rlmreg_p #(.WIDTH(26), .INIT(0)) ex3_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1874,7 +1921,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex3_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1893,7 +1941,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex3_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1912,7 +1961,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex3_nia_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1931,7 +1981,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex3_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1950,7 +2001,8 @@ generate tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex3_lr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1969,7 +2021,8 @@ generate tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex3_ctr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -1988,7 +2041,8 @@ generate tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex3_cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2007,7 +2061,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_b_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2026,7 +2081,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_bc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2045,7 +2101,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_bclr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2064,7 +2121,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_bcctr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2083,7 +2141,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_bctar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2102,7 +2161,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_pred_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2121,7 +2181,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_bta_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2140,7 +2201,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex3_pred_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2159,7 +2221,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex3_ls_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2178,7 +2241,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_bh_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2197,7 +2261,8 @@ generate tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex3_gshare_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2216,7 +2281,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_mcrf_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2235,7 +2301,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crand_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2254,7 +2321,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crandc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2273,7 +2341,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_creqv_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2292,7 +2361,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crnand_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2311,7 +2381,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crnor_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2330,7 +2401,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_cror_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2349,7 +2421,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crorc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2368,7 +2441,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex3_is_crxor_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_act), @@ -2387,7 +2461,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_vld_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2406,7 +2481,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_slow_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2425,7 +2501,8 @@ generate tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0)) ex4_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2444,7 +2521,8 @@ generate tri_rlmreg_p #(.WIDTH(`LR_POOL_ENC), .INIT(0)) ex4_lr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2463,7 +2541,8 @@ generate tri_rlmreg_p #(.WIDTH(`CTR_POOL_ENC), .INIT(0)) ex4_ctr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2482,7 +2561,8 @@ generate tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0)) ex4_cr_wa_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2501,7 +2581,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_taken_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2520,7 +2601,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_ARCH+1)), .INIT(0)) ex4_bta_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2538,7 +2620,8 @@ generate ); tri_rlmreg_p #(.WIDTH(18), .INIT(0)) ex4_gshare_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2557,7 +2640,8 @@ generate tri_rlmreg_p #(.WIDTH(3), .INIT(0)) ex4_ls_ptr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2576,7 +2660,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`EFF_IFAR_WIDTH+1)), .INIT(0)) ex4_ls_data_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2595,7 +2680,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_ls_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_act), @@ -2614,7 +2700,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_redirect_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2633,7 +2720,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ex4_itag_saved_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2652,7 +2740,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_lr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2671,7 +2760,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex4_lr_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_lr_we_d), @@ -2690,7 +2780,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_ctr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2709,7 +2800,8 @@ generate tri_rlmreg_p #(.WIDTH((-1+`GPR_WIDTH+1)), .INIT(0)) ex4_ctr_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ctr_we_d), @@ -2728,7 +2820,8 @@ generate tri_rlmlatch_p #(.INIT(0)) ex4_cr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2747,7 +2840,8 @@ generate tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex4_cr_wd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_cr_we_d), @@ -2765,7 +2859,8 @@ generate ); tri_rlmreg_p #(.WIDTH(4), .INIT(0)) ex4_perf_event( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2784,7 +2879,8 @@ generate tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -2808,7 +2904,8 @@ generate tri_plat #(.WIDTH(2)) perv_2to1_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({pc_br_func_sl_thold_2,pc_br_sg_2}), .q({func_sl_thold_1,sg_1}) @@ -2818,7 +2915,8 @@ generate tri_plat #(.WIDTH(2)) perv_1to0_reg( .vd(vdd), .gd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .flush(tc_ac_ccflush_dc), .din({func_sl_thold_1,sg_1}), .q({func_sl_thold_0,sg_0}) diff --git a/dev/verilog/work/xu0_byp.v b/dev/verilog/work/xu0_byp.v index 50d8730..ec84cde 100755 --- a/dev/verilog/work/xu0_byp.v +++ b/dev/verilog/work/xu0_byp.v @@ -34,9 +34,10 @@ module xu0_byp( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -1171,7 +1172,8 @@ module xu0_byp( // Latches //------------------------------------------------------------------------------------------ tri_rlmreg_p #(.WIDTH(7), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1184,7 +1186,8 @@ module xu0_byp( .dout(exx_xu0_act_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1197,7 +1200,8 @@ module xu0_byp( .dout(exx_lq_act_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1210,7 +1214,8 @@ module xu0_byp( .dout(ex1_s1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1223,7 +1228,8 @@ module xu0_byp( .dout(ex1_s2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1239,7 +1245,8 @@ generate begin : ex1_gpr_s1_xu0_sel_gen genvar i; for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1258,7 +1265,8 @@ generate begin : ex1_gpr_s2_xu0_sel_gen genvar i; for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1277,7 +1285,8 @@ generate begin : ex1_gpr_s1_xu1_sel_gen genvar i; for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1296,7 +1305,8 @@ generate begin : ex1_gpr_s2_xu1_sel_gen genvar i; for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1315,7 +1325,8 @@ generate begin : ex1_gpr_s1_lq_sel_gen genvar i; for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1334,7 +1345,8 @@ generate begin : ex1_gpr_s2_lq_sel_gen genvar i; for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1350,7 +1362,8 @@ generate begin : ex1_gpr_s2_lq_sel_gen end endgenerate tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_imm_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1366,7 +1379,8 @@ generate begin : ex1_spr_s1_xu0_sel_gen genvar i; for (i=3;i<=6;i=i+1) begin : ex1_spr_s1_xu0_sel_entry tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1385,7 +1399,8 @@ generate begin : ex1_spr_s1_xu1_sel_gen genvar i; for (i=3;i<=3;i=i+1) begin : ex1_spr_s1_xu1_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1404,7 +1419,8 @@ generate begin : ex1_spr_s1_lq_sel_gen genvar i; for (i=5;i<=6;i=i+1) begin : ex1_spr_s1_lq_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1423,7 +1439,8 @@ generate begin : ex1_spr_s2_xu0_sel_gen genvar i; for (i=3;i<=6;i=i+1) begin : ex1_spr_s2_xu0_sel_entry tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1442,7 +1459,8 @@ generate begin : ex1_spr_s2_xu1_sel_gen genvar i; for (i=3;i<=3;i=i+1) begin : ex1_spr_s2_xu1_sel_entry tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1461,7 +1479,8 @@ generate begin : ex1_spr_s2_lq_sel_gen genvar i; for (i=5;i<=6;i=i+1) begin : ex1_spr_s2_lq_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1480,7 +1499,8 @@ generate begin : ex1_spr_s3_xu0_sel_gen genvar i; for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1499,7 +1519,8 @@ generate begin : ex1_spr_s3_xu1_sel_gen genvar i; for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1518,7 +1539,8 @@ generate begin : ex1_spr_s3_lq_sel_gen genvar i; for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1537,7 +1559,8 @@ generate begin : ex1_gpr_s1_rel_sel_gen genvar i; for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1556,7 +1579,8 @@ generate begin : ex1_gpr_s2_rel_sel_gen genvar i; for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1572,7 +1596,8 @@ generate begin : ex1_gpr_s2_rel_sel_gen end endgenerate tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex0_xu0_ivax_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1585,7 +1610,8 @@ endgenerate .dout(ex1_gpr_s1_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1598,7 +1624,8 @@ endgenerate .dout(ex1_gpr_s2_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s1_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1611,7 +1638,8 @@ endgenerate .dout(ex1_spr_s1_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s2_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1624,7 +1652,8 @@ endgenerate .dout(ex1_spr_s2_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1637,7 +1666,8 @@ endgenerate .dout(ex1_spr_s3_reg_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1650,7 +1680,8 @@ endgenerate .dout(ex1_abt_s1_lq_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1663,7 +1694,8 @@ endgenerate .dout(ex1_abt_s2_lq_sel_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(7),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1676,7 +1708,8 @@ endgenerate .dout(ex1_abt_s3_lq_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1689,7 +1722,8 @@ endgenerate .dout(ex1_abt_s1_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1702,7 +1736,8 @@ endgenerate .dout(ex1_abt_s2_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1715,7 +1750,8 @@ endgenerate .dout(ex1_abt_s3_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1728,7 +1764,8 @@ endgenerate .dout(ex1_abt_s1_xu0_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1741,7 +1778,8 @@ endgenerate .dout(ex1_abt_s2_xu0_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1754,7 +1792,8 @@ endgenerate .dout(ex1_abt_s3_xu0_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mflr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1767,7 +1806,8 @@ endgenerate .dout(ex2_is_mflr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfxer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1780,7 +1820,8 @@ endgenerate .dout(ex2_is_mfxer_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtxer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1793,7 +1834,8 @@ endgenerate .dout(ex2_is_mtxer_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfcr_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1806,7 +1848,8 @@ endgenerate .dout(ex2_is_mfcr_sel_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfcr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1819,7 +1862,8 @@ endgenerate .dout(ex2_is_mfcr_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtcr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1832,7 +1876,8 @@ endgenerate .dout(ex2_is_mtcr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfctr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1845,7 +1890,8 @@ endgenerate .dout(ex2_is_mfctr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtxer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -1858,7 +1904,8 @@ endgenerate .dout(ex3_is_mtxer_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -1871,7 +1918,8 @@ endgenerate .dout(ex4_xu0_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -1884,7 +1932,8 @@ endgenerate .dout(ex5_xu0_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -1897,7 +1946,8 @@ endgenerate .dout(ex6_xu0_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex7_xu0_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[6]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX7]), @@ -1910,7 +1960,8 @@ endgenerate .dout(ex7_xu0_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex8_xu0_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[7]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX8]), @@ -1923,7 +1974,8 @@ endgenerate .dout(ex8_xu0_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_lq_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -1936,7 +1988,8 @@ endgenerate .dout(ex6_lq_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex7_lq_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_lq_act[6]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX7]), @@ -1949,7 +2002,8 @@ endgenerate .dout(ex7_lq_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex8_lq_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_lq_act[7]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX8]), @@ -1962,7 +2016,8 @@ endgenerate .dout(ex8_lq_rt_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -1975,7 +2030,8 @@ endgenerate .dout(ex4_xu0_cr_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -1988,7 +2044,8 @@ endgenerate .dout(ex5_xu0_cr_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2001,7 +2058,8 @@ endgenerate .dout(ex6_xu0_cr_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_lq_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2014,7 +2072,8 @@ endgenerate .dout(ex6_lq_cr_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_xer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2027,7 +2086,8 @@ endgenerate .dout(ex4_xu0_xer_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_xer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2040,7 +2100,8 @@ endgenerate .dout(ex5_xu0_xer_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_xu0_xer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2053,7 +2114,8 @@ endgenerate .dout(ex6_xu0_xer_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_ctr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_xu0_ctr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2066,7 +2128,8 @@ endgenerate .dout(ex4_xu0_ctr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu0_lr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_xu0_lr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2079,7 +2142,8 @@ endgenerate .dout(ex4_xu0_lr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_xu0_ivax_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2092,7 +2156,8 @@ endgenerate .dout(ex2_rs1_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2105,7 +2170,8 @@ endgenerate .dout(ex2_rs2_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2118,7 +2184,8 @@ endgenerate .dout(ex2_cr1_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2131,7 +2198,8 @@ endgenerate .dout(ex2_cr2_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_cr3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2144,7 +2212,8 @@ endgenerate .dout(ex2_cr3_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_bit_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2157,7 +2226,8 @@ endgenerate .dout(ex2_cr_bit_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2170,7 +2240,8 @@ endgenerate .dout(ex2_xer2_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2183,7 +2254,8 @@ endgenerate .dout(ex2_xer3_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2196,7 +2268,8 @@ endgenerate .dout(ex3_xer3_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_lr1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2209,7 +2282,8 @@ endgenerate .dout(ex2_lr1_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_lr2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2222,7 +2296,8 @@ endgenerate .dout(ex2_lr2_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ctr2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2235,7 +2310,8 @@ endgenerate .dout(ex2_ctr2_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) ex2_cr_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2248,7 +2324,8 @@ endgenerate .dout(ex2_cr_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) ex2_xer_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2261,7 +2338,8 @@ endgenerate .dout(ex2_xer_sel_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rs1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2274,7 +2352,8 @@ endgenerate .dout(ex3_rs1_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mfspr_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2287,7 +2366,8 @@ endgenerate .dout(ex3_mfspr_sel_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_mfspr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_mfspr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2300,7 +2380,8 @@ endgenerate .dout(ex3_mfspr_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ord_rt_data_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_data_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2313,7 +2394,8 @@ endgenerate .dout(ord_rt_data_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_cr_data_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_data_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2326,7 +2408,8 @@ endgenerate .dout(ord_cr_data_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_xer_data_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_data_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2339,7 +2422,8 @@ endgenerate .dout(ord_xer_data_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs_capt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2352,7 +2436,8 @@ endgenerate .dout(ex2_rs_capt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ra_capt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2365,7 +2450,8 @@ endgenerate .dout(ex2_ra_capt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ra_capt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2378,7 +2464,8 @@ endgenerate .dout(ex3_ra_capt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ra_capt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2391,7 +2478,8 @@ endgenerate .dout(ex4_ra_capt_q) ); tri_rlmreg_p #(.WIDTH(12), .OFFSET(52),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_noimm_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2404,7 +2492,8 @@ endgenerate .dout(ex2_rs2_noimm_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_mtcr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2417,7 +2506,8 @@ endgenerate .dout(ex3_mtcr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mtcr_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2430,7 +2520,8 @@ endgenerate .dout(ex3_mtcr_sel_q) ); tri_rlmreg_p #(.WIDTH(9), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_rs_is_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_rs_capt_q), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2443,7 +2534,8 @@ endgenerate .dout(mm_rs_is_q) ); tri_rlmreg_p #(.WIDTH(12), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_ra_entry_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_ra_capt_q), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2456,7 +2548,8 @@ endgenerate .dout(mm_ra_entry_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) mm_data_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ra_capt_q), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2469,7 +2562,8 @@ endgenerate .dout(mm_data_q) ); tri_rlmreg_p #(.WIDTH(7), .OFFSET(57),.INIT(0), .NEEDS_SRESET(1)) ex3_cnt_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2482,7 +2576,8 @@ endgenerate .dout(ex3_cnt_rt_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(56),.INIT(0), .NEEDS_SRESET(1)) ex3_prm_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2495,7 +2590,8 @@ endgenerate .dout(ex3_prm_rt_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(60),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2508,7 +2604,8 @@ endgenerate .dout(ex3_dlm_rt_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_xer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2521,7 +2618,8 @@ endgenerate .dout(ex3_dlm_xer_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_dlm_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2534,7 +2632,8 @@ endgenerate .dout(ex3_dlm_cr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_ord_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2547,7 +2646,8 @@ endgenerate .dout(ex6_mul_ord_done_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2560,7 +2660,8 @@ endgenerate .dout(ex6_mul_abort_q) ); tri_rlmreg_p #(.WIDTH(9), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_mul_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2573,7 +2674,8 @@ endgenerate .dout(ex6_mul_done_q) ); tri_rlmreg_p #(.WIDTH(11), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2586,7 +2688,8 @@ endgenerate .dout(exx_xu0_abort_q) ); tri_rlmreg_p #(.WIDTH(5), .OFFSET(3),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2599,7 +2702,8 @@ endgenerate .dout(exx_xu1_abort_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2612,7 +2716,8 @@ endgenerate .dout(exx_lq_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2625,7 +2730,8 @@ endgenerate .dout(ex2_rs1_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2638,7 +2744,8 @@ endgenerate .dout(ex2_rs2_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs3_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2651,7 +2758,8 @@ endgenerate .dout(ex2_rs3_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) exx_rel3_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2664,7 +2772,8 @@ endgenerate .dout(exx_rel3_act_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel3_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq_xu_rel_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2677,7 +2786,8 @@ endgenerate .dout(exx_rel3_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel4_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_rel3_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), diff --git a/dev/verilog/work/xu0_dec.v b/dev/verilog/work/xu0_dec.v index a6d9021..8387650 100755 --- a/dev/verilog/work/xu0_dec.v +++ b/dev/verilog/work/xu0_dec.v @@ -38,7 +38,8 @@ module xu0_dec( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, inout vdd, inout gnd, @@ -1883,7 +1884,8 @@ module xu0_dec( // Latches //------------------------------------------------------------------------------------------ tri_rlmreg_p #(.WIDTH(5), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1896,7 +1898,8 @@ module xu0_dec( .dout(exx_act_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1909,7 +1912,8 @@ module xu0_dec( .dout(ex1_s2_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_s2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1922,7 +1926,8 @@ module xu0_dec( .dout(ex1_s2_t_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1935,7 +1940,8 @@ module xu0_dec( .dout(ex1_s3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_s3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1948,7 +1954,8 @@ module xu0_dec( .dout(ex1_s3_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1961,7 +1968,8 @@ module xu0_dec( .dout(ex1_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1974,7 +1982,8 @@ module xu0_dec( .dout(ex1_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1987,7 +1996,8 @@ module xu0_dec( .dout(ex1_t3_t_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2000,7 +2010,8 @@ module xu0_dec( .dout(ex1_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2013,7 +2024,8 @@ module xu0_dec( .dout(ex1_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2026,7 +2038,8 @@ module xu0_dec( .dout(ex1_t3_v_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2039,7 +2052,8 @@ module xu0_dec( .dout(ex1_t1_p_q) ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2052,7 +2066,8 @@ module xu0_dec( .dout(ex1_t2_p_q) ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2065,7 +2080,8 @@ module xu0_dec( .dout(ex1_t3_p_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2078,7 +2094,8 @@ module xu0_dec( .dout(ex1_instr_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2091,7 +2108,8 @@ module xu0_dec( .dout(ex1_ucode_q) ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2104,7 +2122,8 @@ module xu0_dec( .dout(ex1_itag_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_add_ci_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2117,7 +2136,8 @@ module xu0_dec( .dout(ex2_add_ci_sel_q) ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2130,7 +2150,8 @@ module xu0_dec( .dout(ex2_itag_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2143,7 +2164,8 @@ module xu0_dec( .dout(ex2_t1_p_q) ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2156,7 +2178,8 @@ module xu0_dec( .dout(ex2_t2_p_q) ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2169,7 +2192,8 @@ module xu0_dec( .dout(ex2_t3_p_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2182,7 +2206,8 @@ module xu0_dec( .dout(ex3_t1_p_q) ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2195,7 +2220,8 @@ module xu0_dec( .dout(ex3_t2_p_q) ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2208,7 +2234,8 @@ module xu0_dec( .dout(ex3_t3_p_q) ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2221,7 +2248,8 @@ module xu0_dec( .dout(ex3_itag_q) ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_itag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2234,7 +2262,8 @@ module xu0_dec( .dout(ex4_itag_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2247,7 +2276,8 @@ module xu0_dec( .dout(cp_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), @@ -2260,7 +2290,8 @@ module xu0_dec( .dout(ex0_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2273,7 +2304,8 @@ module xu0_dec( .dout(ex1_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2286,7 +2318,8 @@ module xu0_dec( .dout(ex2_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2299,7 +2332,8 @@ module xu0_dec( .dout(ex3_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2312,7 +2346,8 @@ module xu0_dec( .dout(ex4_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2325,7 +2360,8 @@ module xu0_dec( .dout(ex5_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -2338,7 +2374,8 @@ module xu0_dec( .dout(ex6_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_ord_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2351,7 +2388,8 @@ module xu0_dec( .dout(ex1_ord_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2364,7 +2402,8 @@ module xu0_dec( .dout(ex2_ord_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_ord_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2377,7 +2416,8 @@ module xu0_dec( .dout(ex3_ord_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_ord_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2390,7 +2430,8 @@ module xu0_dec( .dout(ex4_ord_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_cm_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2403,7 +2444,8 @@ module xu0_dec( .dout(spr_msr_cm_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2416,7 +2458,8 @@ module xu0_dec( .dout(spr_msr_gs_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_msr_pr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2429,7 +2472,8 @@ module xu0_dec( .dout(spr_msr_pr_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_epcr_dgtmi_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2442,7 +2486,8 @@ module xu0_dec( .dout(spr_epcr_dgtmi_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_notlb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -2455,7 +2500,8 @@ module xu0_dec( .dout(spr_ccr2_notlb_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_br_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2468,7 +2514,8 @@ module xu0_dec( .dout(ex4_br_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_ord_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -2481,7 +2528,8 @@ module xu0_dec( .dout(ex1_ord_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2494,7 +2542,8 @@ module xu0_dec( .dout(ex2_ord_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ord_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2507,7 +2556,8 @@ module xu0_dec( .dout(ex3_ord_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2520,7 +2570,8 @@ module xu0_dec( .dout(ex2_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2533,7 +2584,8 @@ module xu0_dec( .dout(ex2_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2546,7 +2598,8 @@ module xu0_dec( .dout(ex2_t3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2559,7 +2612,8 @@ module xu0_dec( .dout(ex2_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2572,7 +2626,8 @@ module xu0_dec( .dout(ex2_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -2585,7 +2640,8 @@ module xu0_dec( .dout(ex2_t3_t_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2598,7 +2654,8 @@ module xu0_dec( .dout(ex3_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2611,7 +2668,8 @@ module xu0_dec( .dout(ex3_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2624,7 +2682,8 @@ module xu0_dec( .dout(ex3_t3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2637,7 +2696,8 @@ module xu0_dec( .dout(ex3_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2650,7 +2710,8 @@ module xu0_dec( .dout(ex3_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -2663,7 +2724,8 @@ module xu0_dec( .dout(ex3_t3_t_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2676,7 +2738,8 @@ module xu0_dec( .dout(ex4_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2689,7 +2752,8 @@ module xu0_dec( .dout(ex4_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2702,7 +2766,8 @@ module xu0_dec( .dout(ex4_t3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2715,7 +2780,8 @@ module xu0_dec( .dout(ex4_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2728,7 +2794,8 @@ module xu0_dec( .dout(ex4_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2741,7 +2808,8 @@ module xu0_dec( .dout(ex4_t3_t_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2754,7 +2822,8 @@ module xu0_dec( .dout(ex4_t1_p_q) ); tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex4_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2767,7 +2836,8 @@ module xu0_dec( .dout(ex4_t2_p_q) ); tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex4_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -2780,7 +2850,8 @@ module xu0_dec( .dout(ex4_t3_p_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2793,7 +2864,8 @@ module xu0_dec( .dout(ex5_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2806,7 +2878,8 @@ module xu0_dec( .dout(ex5_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2819,7 +2892,8 @@ module xu0_dec( .dout(ex5_t3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2832,7 +2906,8 @@ module xu0_dec( .dout(ex5_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2845,7 +2920,8 @@ module xu0_dec( .dout(ex5_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2858,7 +2934,8 @@ module xu0_dec( .dout(ex5_t3_t_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2871,7 +2948,8 @@ module xu0_dec( .dout(ex5_t1_p_q) ); tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2884,7 +2962,8 @@ module xu0_dec( .dout(ex5_t2_p_q) ); tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2897,7 +2976,8 @@ module xu0_dec( .dout(ex5_t3_p_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2910,7 +2990,8 @@ module xu0_dec( .dout(ex5_ord_t1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2923,7 +3004,8 @@ module xu0_dec( .dout(ex5_ord_t2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2936,7 +3018,8 @@ module xu0_dec( .dout(ex5_ord_t3_v_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2949,7 +3032,8 @@ module xu0_dec( .dout(ex5_ord_t1_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2962,7 +3046,8 @@ module xu0_dec( .dout(ex5_ord_t2_t_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2975,7 +3060,8 @@ module xu0_dec( .dout(ex5_ord_t3_t_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -2988,7 +3074,8 @@ module xu0_dec( .dout(ex5_ord_t1_p_q) ); tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -3001,7 +3088,8 @@ module xu0_dec( .dout(ex5_ord_t2_p_q) ); tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex5_ord_t3_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex4_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -3014,7 +3102,8 @@ module xu0_dec( .dout(ex5_ord_t3_p_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_gpr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3027,7 +3116,8 @@ module xu0_dec( .dout(ex6_gpr_we_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3040,7 +3130,8 @@ module xu0_dec( .dout(ex6_xer_we_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3053,7 +3144,8 @@ module xu0_dec( .dout(ex6_cr_we_q) ); tri_rlmreg_p #(.WIDTH(-CR_LEFT+`GPR_POOL_ENC), .OFFSET(CR_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex6_cr_wa_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3066,7 +3158,8 @@ module xu0_dec( .dout(ex6_cr_wa_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ctr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3079,7 +3172,8 @@ module xu0_dec( .dout(ex4_ctr_we_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_lr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3092,7 +3186,8 @@ module xu0_dec( .dout(ex4_lr_we_q) ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_t1_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3105,7 +3200,8 @@ module xu0_dec( .dout(ex6_t1_p_q) ); tri_rlmreg_p #(.WIDTH(-XER_LEFT+`GPR_POOL_ENC), .OFFSET(XER_LEFT),.INIT(0), .NEEDS_SRESET(1)) ex6_t2_p_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3118,7 +3214,8 @@ module xu0_dec( .dout(ex6_t2_p_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_attn_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3131,7 +3228,8 @@ module xu0_dec( .dout(spr_ccr2_en_attn_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr4_en_dnh_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3144,7 +3242,8 @@ module xu0_dec( .dout(spr_ccr4_en_dnh_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_ccr2_en_pc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3157,7 +3256,8 @@ module xu0_dec( .dout(spr_ccr2_en_pc_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3170,7 +3270,8 @@ module xu0_dec( .dout(ex2_ord_tid_q) ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_itag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3183,7 +3284,8 @@ module xu0_dec( .dout(ex2_ord_itag_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratre_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3196,7 +3298,8 @@ module xu0_dec( .dout(ex2_ord_is_eratre_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratwe_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3209,7 +3312,8 @@ module xu0_dec( .dout(ex2_ord_is_eratwe_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratsx_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3222,7 +3326,8 @@ module xu0_dec( .dout(ex2_ord_is_eratsx_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_eratilx_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3235,7 +3340,8 @@ module xu0_dec( .dout(ex2_ord_is_eratilx_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_erativax_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3248,7 +3354,8 @@ module xu0_dec( .dout(ex2_ord_is_erativax_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbre_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3261,7 +3368,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbre_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbwe_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3274,7 +3382,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbwe_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsx_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3287,7 +3396,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbsx_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsxr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3300,7 +3410,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbsxr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbsrx_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3313,7 +3424,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbsrx_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbivax_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3326,7 +3438,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbivax_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_is_tlbilx_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3339,7 +3452,8 @@ module xu0_dec( .dout(ex2_ord_is_tlbilx_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(19),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tlb_ws_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3352,7 +3466,8 @@ module xu0_dec( .dout(ex2_ord_tlb_ws_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(8),.INIT(0), .NEEDS_SRESET(1)) ex2_ord_tlb_t_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3365,7 +3480,8 @@ module xu0_dec( .dout(ex2_ord_tlb_t_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_priv_excep_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3378,7 +3494,8 @@ module xu0_dec( .dout(ex2_priv_excep_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_hyp_priv_excep_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3391,7 +3508,8 @@ module xu0_dec( .dout(ex2_hyp_priv_excep_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_illegal_op_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3404,7 +3522,8 @@ module xu0_dec( .dout(ex2_illegal_op_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_flush2ucode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3417,7 +3536,8 @@ module xu0_dec( .dout(ex2_flush2ucode_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_tlb_illeg_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3430,7 +3550,8 @@ module xu0_dec( .dout(ex2_tlb_illeg_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_excep_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3443,7 +3564,8 @@ module xu0_dec( .dout(ex3_priv_excep_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hyp_priv_excep_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3456,7 +3578,8 @@ module xu0_dec( .dout(ex3_hyp_priv_excep_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illegal_op_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3469,7 +3592,8 @@ module xu0_dec( .dout(ex3_illegal_op_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_flush2ucode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3482,7 +3606,8 @@ module xu0_dec( .dout(ex3_flush2ucode_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_flush2ucode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3495,7 +3620,8 @@ module xu0_dec( .dout(ex4_flush2ucode_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3508,7 +3634,8 @@ module xu0_dec( .dout(ex1_ord_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3521,7 +3648,8 @@ module xu0_dec( .dout(ex2_ord_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3534,7 +3662,8 @@ module xu0_dec( .dout(ex3_ord_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3547,7 +3676,8 @@ module xu0_dec( .dout(ex4_ord_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -3560,7 +3690,8 @@ module xu0_dec( .dout(ex5_ord_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ord_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -3573,7 +3704,8 @@ module xu0_dec( .dout(ex6_ord_complete_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_pri_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3586,7 +3718,8 @@ module xu0_dec( .dout(xu_iu_pri_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_pri_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3599,7 +3732,8 @@ module xu0_dec( .dout(xu_iu_pri_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_hold_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3612,7 +3746,8 @@ module xu0_dec( .dout(xu_iu_hold_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_hold_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3625,7 +3760,8 @@ module xu0_dec( .dout(xu_lq_hold_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mm_hold_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3638,7 +3774,8 @@ module xu0_dec( .dout(xu_mm_hold_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_iu_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3651,7 +3788,8 @@ module xu0_dec( .dout(xu_iu_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_lq_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3664,7 +3802,8 @@ module xu0_dec( .dout(xu_lq_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_mm_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3677,7 +3816,8 @@ module xu0_dec( .dout(xu_mm_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_iu_val_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3690,7 +3830,8 @@ module xu0_dec( .dout(xu_iu_val_2_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_lq_val_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3703,7 +3844,8 @@ module xu0_dec( .dout(xu_lq_val_2_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu_mm_val_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3716,7 +3858,8 @@ module xu0_dec( .dout(xu_mm_val_2_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_miss_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3729,7 +3872,8 @@ module xu0_dec( .dout(ord_tlb_miss_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_lrat_miss_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3742,7 +3886,8 @@ module xu0_dec( .dout(ord_lrat_miss_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_inelig_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3755,7 +3900,8 @@ module xu0_dec( .dout(ord_tlb_inelig_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_pt_fault_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3768,7 +3914,8 @@ module xu0_dec( .dout(ord_pt_fault_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hv_priv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3781,7 +3928,8 @@ module xu0_dec( .dout(ord_hv_priv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_illeg_mmu_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3794,7 +3942,8 @@ module xu0_dec( .dout(ord_illeg_mmu_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_lq_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3807,7 +3956,8 @@ module xu0_dec( .dout(ord_lq_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_spr_priv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3820,7 +3970,8 @@ module xu0_dec( .dout(ord_spr_priv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_spr_illegal_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3833,7 +3984,8 @@ module xu0_dec( .dout(ord_spr_illegal_spr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hyp_priv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3846,7 +3998,8 @@ module xu0_dec( .dout(ord_hyp_priv_spr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ex3_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3859,7 +4012,8 @@ module xu0_dec( .dout(ord_ex3_np1_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ill_tlb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3872,7 +4026,8 @@ module xu0_dec( .dout(ord_ill_tlb_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_priv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3885,7 +4040,8 @@ module xu0_dec( .dout(ord_priv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hyp_priv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3898,7 +4054,8 @@ module xu0_dec( .dout(ord_hyp_priv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_hold_lq_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3911,7 +4068,8 @@ module xu0_dec( .dout(ord_hold_lq_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_outstanding_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3924,7 +4082,8 @@ module xu0_dec( .dout(ord_outstanding_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flushed_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3937,7 +4096,8 @@ module xu0_dec( .dout(ord_flushed_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3950,7 +4110,8 @@ module xu0_dec( .dout(ord_done_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_mmu_req_sent_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3963,7 +4124,8 @@ module xu0_dec( .dout(ord_mmu_req_sent_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_core_block_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3976,7 +4138,8 @@ module xu0_dec( .dout(ord_core_block_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_ierat_par_err_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3989,7 +4152,8 @@ module xu0_dec( .dout(ord_ierat_par_err_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_derat_par_err_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4002,7 +4166,8 @@ module xu0_dec( .dout(ord_derat_par_err_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_multihit_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4015,7 +4180,8 @@ module xu0_dec( .dout(ord_tlb_multihit_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_par_err_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4028,7 +4194,8 @@ module xu0_dec( .dout(ord_tlb_par_err_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_tlb_lru_par_err_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4041,7 +4208,8 @@ module xu0_dec( .dout(ord_tlb_lru_par_err_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_local_snoop_reject_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4054,7 +4222,8 @@ module xu0_dec( .dout(ord_local_snoop_reject_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mmu_ord_n_flush_req_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4067,7 +4236,8 @@ module xu0_dec( .dout(mmu_ord_n_flush_req_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_ord_n_flush_req_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4080,7 +4250,8 @@ module xu0_dec( .dout(iu_ord_n_flush_req_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_ord_n_flush_req_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4093,7 +4264,8 @@ module xu0_dec( .dout(lq_ord_n_flush_req_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4106,7 +4278,8 @@ module xu0_dec( .dout(ex4_np1_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_n_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4119,7 +4292,8 @@ module xu0_dec( .dout(ex4_n_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_excep_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4132,7 +4306,8 @@ module xu0_dec( .dout(ex4_excep_val_q) ); tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_excep_vector_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4145,7 +4320,8 @@ module xu0_dec( .dout(ex4_excep_vector_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ucode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4158,7 +4334,8 @@ module xu0_dec( .dout(ex2_ucode_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_ehpriv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4171,7 +4348,8 @@ module xu0_dec( .dout(ex2_is_ehpriv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_ehpriv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4184,7 +4362,8 @@ module xu0_dec( .dout(ex3_is_ehpriv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtiar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4197,7 +4376,8 @@ module xu0_dec( .dout(ex2_is_mtiar_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mtiar_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4210,7 +4390,8 @@ module xu0_dec( .dout(ex3_mtiar_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_mtiar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4223,7 +4404,8 @@ module xu0_dec( .dout(ord_mtiar_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_valid), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4236,7 +4418,8 @@ module xu0_dec( .dout(ord_instr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_erativax_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4249,7 +4432,8 @@ module xu0_dec( .dout(ex2_is_erativax_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) xu0_iu_mtiar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4262,7 +4446,8 @@ module xu0_dec( .dout(xu0_iu_mtiar_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_is_cp_next_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4275,7 +4460,8 @@ module xu0_dec( .dout(ord_is_cp_next_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flush_1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4288,7 +4474,8 @@ module xu0_dec( .dout(ord_flush_1_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_flush_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4304,7 +4491,8 @@ generate begin : spr_mmucr0_tlbsel_gen genvar i; for (i=0;i<`THREADS;i=i+1) begin : spr_mmucr0_tlbsel_entry tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) spr_mmucr0_tlbsel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4320,7 +4508,8 @@ generate begin : spr_mmucr0_tlbsel_gen end endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mm_xu_tlbwe_binv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4333,7 +4522,8 @@ endgenerate .dout(mm_xu_tlbwe_binv_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4346,7 +4536,8 @@ endgenerate .dout(ex2_instr_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4359,7 +4550,8 @@ endgenerate .dout(ex3_instr_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4372,7 +4564,8 @@ endgenerate .dout(ex4_instr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_hpriv_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4385,7 +4578,8 @@ endgenerate .dout(ex4_hpriv_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_popcnt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4398,7 +4592,8 @@ endgenerate .dout(ex2_any_popcnt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_popcnt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4411,7 +4606,8 @@ endgenerate .dout(ex3_any_popcnt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_any_popcnt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4424,7 +4620,8 @@ endgenerate .dout(ex4_any_popcnt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_cntlz_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4437,7 +4634,8 @@ endgenerate .dout(ex2_any_cntlz_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_cntlz_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4450,7 +4648,8 @@ endgenerate .dout(ex3_any_cntlz_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_bpermd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4463,7 +4662,8 @@ endgenerate .dout(ex2_is_bpermd_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_bpermd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4476,7 +4676,8 @@ endgenerate .dout(ex3_is_bpermd_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_dlmzb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4489,7 +4690,8 @@ endgenerate .dout(ex2_is_dlmzb_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_dlmzb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4502,7 +4704,8 @@ endgenerate .dout(ex3_is_dlmzb_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_multicyc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4515,7 +4718,8 @@ endgenerate .dout(ex2_mul_multicyc_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_multicyc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4528,7 +4732,8 @@ endgenerate .dout(ex3_mul_multicyc_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_2c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4541,7 +4746,8 @@ endgenerate .dout(ex2_mul_2c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_3c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4554,7 +4760,8 @@ endgenerate .dout(ex2_mul_3c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_4c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4567,7 +4774,8 @@ endgenerate .dout(ex2_mul_4c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_2c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4580,7 +4788,8 @@ endgenerate .dout(ex3_mul_2c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_3c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4593,7 +4802,8 @@ endgenerate .dout(ex3_mul_3c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_4c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4606,7 +4816,8 @@ endgenerate .dout(ex3_mul_4c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_2c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4619,7 +4830,8 @@ endgenerate .dout(ex4_mul_2c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_3c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4632,7 +4844,8 @@ endgenerate .dout(ex4_mul_3c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_4c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4645,7 +4858,8 @@ endgenerate .dout(ex4_mul_4c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_3c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -4658,7 +4872,8 @@ endgenerate .dout(ex5_mul_3c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_4c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -4671,7 +4886,8 @@ endgenerate .dout(ex5_mul_4c_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_mul_4c_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -4684,7 +4900,8 @@ endgenerate .dout(ex6_mul_4c_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) exx_mul_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4697,7 +4914,8 @@ endgenerate .dout(exx_mul_tid_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4710,7 +4928,8 @@ endgenerate .dout(ex2_is_mtspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4723,7 +4942,8 @@ endgenerate .dout(ex3_is_mtspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ram_active_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -4736,7 +4956,8 @@ endgenerate .dout(ex6_ram_active_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -4749,7 +4970,8 @@ endgenerate .dout(ex6_tid_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spec_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -4762,7 +4984,8 @@ endgenerate .dout(ex1_spec_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_spec_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4775,7 +4998,8 @@ endgenerate .dout(ex2_spec_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_spec_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4788,7 +5012,8 @@ endgenerate .dout(ex3_spec_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_async_flush_before_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4801,7 +5026,8 @@ endgenerate .dout(ord_async_flush_before_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_async_flush_after_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4814,7 +5040,8 @@ endgenerate .dout(ord_async_flush_after_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_async_credit_wait_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4827,7 +5054,8 @@ endgenerate .dout(ord_async_credit_wait_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) async_flush_req_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4840,7 +5068,8 @@ endgenerate .dout(async_flush_req_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) async_flush_req_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4853,7 +5082,8 @@ endgenerate .dout(async_flush_req_2_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_async_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4866,7 +5096,8 @@ endgenerate .dout(iu_async_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_credits_returned_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4879,7 +5110,8 @@ endgenerate .dout(iu_xu_credits_returned_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_mfspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4892,7 +5124,8 @@ endgenerate .dout(ex2_any_mfspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_mfspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4905,7 +5138,8 @@ endgenerate .dout(ex3_any_mfspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_any_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4918,7 +5152,8 @@ endgenerate .dout(ex2_any_mtspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_any_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4931,7 +5166,8 @@ endgenerate .dout(ex3_any_mtspr_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_perf_event_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4944,7 +5180,8 @@ endgenerate .dout(ex4_perf_event_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_any_mfspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4957,7 +5194,8 @@ endgenerate .dout(ord_any_mfspr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ord_any_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex1_ord_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4970,7 +5208,8 @@ endgenerate .dout(ord_any_mtspr_q) ); tri_rlmreg_p #(.WIDTH(6), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_timer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ord_outstanding_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4983,7 +5222,8 @@ endgenerate .dout(ord_timer_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ord_timeout_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), diff --git a/dev/verilog/work/xu0_div_r4.v b/dev/verilog/work/xu0_div_r4.v index d2d0283..5e98d7e 100755 --- a/dev/verilog/work/xu0_div_r4.v +++ b/dev/verilog/work/xu0_div_r4.v @@ -36,7 +36,8 @@ module xu0_div_r4( // Clocks - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Power inout vdd, @@ -1098,7 +1099,8 @@ module xu0_div_r4( //------------------------------------------------------------------- //mark_unused(xersrc_q[1])mark_unused(ex4_div_recform_q) tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex2_div_ctr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1116,7 +1118,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1134,7 +1137,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1152,7 +1156,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_size_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1170,7 +1175,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_extd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1188,7 +1194,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_div_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1206,7 +1213,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1224,7 +1232,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1242,7 +1251,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_cycle_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1260,7 +1270,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_cycles_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_cycle_act_d), @@ -1278,7 +1289,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((65-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_denom_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1296,7 +1308,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_numer_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1317,7 +1330,8 @@ module xu0_div_r4( tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_PR_sum_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1336,7 +1350,8 @@ module xu0_div_r4( tri_rlmreg_p #(.WIDTH((66-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_PR_carry_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1354,7 +1369,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_Q_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1372,7 +1388,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_QM_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1390,7 +1407,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_oddshift_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1408,7 +1426,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_divrunning_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1426,7 +1445,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_divrunning_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1444,7 +1464,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_divflush_1d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1462,7 +1483,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_divflush_2d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1481,7 +1503,8 @@ module xu0_div_r4( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_rslt_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1500,7 +1523,8 @@ module xu0_div_r4( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_quotient_correction_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1518,7 +1542,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((65-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex3_dmask_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1538,7 +1563,8 @@ module xu0_div_r4( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_ovf_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1556,7 +1582,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1574,7 +1601,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1592,7 +1620,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_size_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1610,7 +1639,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1628,7 +1658,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_extd_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1646,7 +1677,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_2s_rslt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1664,7 +1696,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_div_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1682,7 +1715,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1700,7 +1734,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_cycle_watch_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1718,7 +1753,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_quot_watch_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1736,7 +1772,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_ovf_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1754,7 +1791,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1772,7 +1810,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1790,7 +1829,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_div_done_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1808,7 +1848,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_quotient_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1826,7 +1867,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_recform_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1844,7 +1886,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_size_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1862,7 +1905,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_2s_rslt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1880,7 +1924,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH((63-msb+1)), .INIT(0), .NEEDS_SRESET(1)) ex4_div_rt_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(divrunning_act), @@ -1898,7 +1943,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_div_ovf_cond3_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_div_val_q), @@ -1916,7 +1962,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -1934,7 +1981,8 @@ module xu0_div_r4( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_numer_eq_zero_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1952,7 +2000,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) xersrc_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -1970,7 +2019,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tiup), @@ -1988,7 +2038,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_div_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_div_ex1_div_act), @@ -2006,7 +2057,8 @@ module xu0_div_r4( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_div_tid_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_div_val_q), @@ -2023,7 +2075,8 @@ module xu0_div_r4( .dout(ex3_div_tid_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_divrunning_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), diff --git a/dev/verilog/work/xu1.v b/dev/verilog/work/xu1.v index c750369..370b900 100755 --- a/dev/verilog/work/xu1.v +++ b/dev/verilog/work/xu1.v @@ -37,9 +37,10 @@ module xu1( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -253,7 +254,8 @@ module xu1( xu_alu alu( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -289,7 +291,8 @@ module xu1( xu1_byp byp( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -390,7 +393,8 @@ module xu1( xu1_dec dec( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), diff --git a/dev/verilog/work/xu1_byp.v b/dev/verilog/work/xu1_byp.v index 2ce0e39..7efa33c 100755 --- a/dev/verilog/work/xu1_byp.v +++ b/dev/verilog/work/xu1_byp.v @@ -34,9 +34,10 @@ module xu1_byp( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -620,7 +621,8 @@ generate begin : dvc_2t // Latches //------------------------------------------------------------------------------------------ tri_rlmreg_p #(.WIDTH(4), .OFFSET(4),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -633,7 +635,8 @@ generate begin : dvc_2t .dout(exx_xu0_act_q) ); tri_rlmreg_p #(.WIDTH(6), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -646,7 +649,8 @@ generate begin : dvc_2t .dout(exx_xu1_act_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -659,7 +663,8 @@ generate begin : dvc_2t .dout(exx_lq_act_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), @@ -672,7 +677,8 @@ generate begin : dvc_2t .dout(ex0_s1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), @@ -685,7 +691,8 @@ generate begin : dvc_2t .dout(ex0_s2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex0_s3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), @@ -698,7 +705,8 @@ generate begin : dvc_2t .dout(ex0_s3_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s1_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -711,7 +719,8 @@ generate begin : dvc_2t .dout(ex1_s1_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s2_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -724,7 +733,8 @@ generate begin : dvc_2t .dout(ex1_s2_v_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_s3_v_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -740,7 +750,8 @@ generate begin : ex1_gpr_s1_xu0_sel_gen genvar i; for (i=2;i<=8;i=i+1) begin : ex1_gpr_s1_xu0_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -759,7 +770,8 @@ generate begin : ex1_gpr_s2_xu0_sel_gen genvar i; for (i=2;i<=8;i=i+1) begin : ex1_gpr_s2_xu0_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -778,7 +790,8 @@ generate begin : ex1_gpr_s1_xu1_sel_gen genvar i; for (i=2;i<=5;i=i+1) begin : ex1_gpr_s1_xu1_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -797,7 +810,8 @@ generate begin : ex1_gpr_s2_xu1_sel_gen genvar i; for (i=2;i<=5;i=i+1) begin : ex1_gpr_s2_xu1_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -816,7 +830,8 @@ generate begin : ex1_gpr_s1_lq_sel_gen genvar i; for (i=5;i<=8;i=i+1) begin : ex1_gpr_s1_lq_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -835,7 +850,8 @@ generate begin : ex1_gpr_s2_lq_sel_gen genvar i; for (i=5;i<=8;i=i+1) begin : ex1_gpr_s2_lq_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -851,7 +867,8 @@ generate begin : ex1_gpr_s2_lq_sel_gen end endgenerate tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_imm_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -867,7 +884,8 @@ generate begin : ex1_spr_s3_xu0_sel_gen genvar i; for (i=3;i<=8;i=i+1) begin : ex1_spr_s3_xu0_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -886,7 +904,8 @@ generate begin : ex1_spr_s3_xu1_sel_gen genvar i; for (i=3;i<=5;i=i+1) begin : ex1_spr_s3_xu1_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -905,7 +924,8 @@ generate begin : ex1_spr_s3_lq_sel_gen genvar i; for (i=5;i<=6;i=i+1) begin : ex1_spr_s3_lq_sel_entry tri_rlmreg_p #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -924,7 +944,8 @@ generate begin : ex1_gpr_s1_rel_sel_gen genvar i; for (i=3;i<=4;i=i+1) begin : ex1_gpr_s1_rel_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_rel_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -943,7 +964,8 @@ generate begin : ex1_gpr_s2_rel_sel_gen genvar i; for (i=3;i<=4;i=i+1) begin : ex1_gpr_s2_rel_sel_entry tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_rel_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -959,7 +981,8 @@ generate begin : ex1_gpr_s2_rel_sel_gen end endgenerate tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s1_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -972,7 +995,8 @@ endgenerate .dout(ex1_gpr_s1_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_gpr_s2_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -985,7 +1009,8 @@ endgenerate .dout(ex1_gpr_s2_reg_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_spr_s3_reg_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -998,7 +1023,8 @@ endgenerate .dout(ex1_spr_s3_reg_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1011,7 +1037,8 @@ endgenerate .dout(ex1_abt_s1_lq_sel_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1024,7 +1051,8 @@ endgenerate .dout(ex1_abt_s2_lq_sel_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(7),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_lq_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1037,7 +1065,8 @@ endgenerate .dout(ex1_abt_s3_lq_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1050,7 +1079,8 @@ endgenerate .dout(ex1_abt_s1_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1063,7 +1093,8 @@ endgenerate .dout(ex1_abt_s2_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu1_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1076,7 +1107,8 @@ endgenerate .dout(ex1_abt_s3_xu1_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s1_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1089,7 +1121,8 @@ endgenerate .dout(ex1_abt_s1_xu0_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s2_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1102,7 +1135,8 @@ endgenerate .dout(ex1_abt_s2_xu0_sel_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex1_abt_s3_xu0_sel_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -1115,7 +1149,8 @@ endgenerate .dout(ex1_abt_s3_xu0_sel_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_xu1_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -1128,7 +1163,8 @@ endgenerate .dout(ex4_xu1_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex5_xu1_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -1141,7 +1177,8 @@ endgenerate .dout(ex5_xu1_rt_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -1154,7 +1191,8 @@ endgenerate .dout(ex5_xu0_cr_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex6_lq_cr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_lq_act[5]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX6]), @@ -1167,7 +1205,8 @@ endgenerate .dout(ex6_lq_cr_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_xu0_xer_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu0_act[4]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -1180,7 +1219,8 @@ endgenerate .dout(ex5_xu0_xer_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1193,7 +1233,8 @@ endgenerate .dout(ex2_rs1_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1206,7 +1247,8 @@ endgenerate .dout(ex2_rs2_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_bit_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1219,7 +1261,8 @@ endgenerate .dout(ex2_cr_bit_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_xer3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_xu1_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1232,7 +1275,8 @@ endgenerate .dout(ex2_xer3_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(3),.INIT(0), .NEEDS_SRESET(1)) exx_xu0_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1245,7 +1289,8 @@ endgenerate .dout(exx_xu0_abort_q) ); tri_rlmreg_p #(.WIDTH(6), .OFFSET(2),.INIT(0), .NEEDS_SRESET(1)) exx_xu1_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1258,7 +1303,8 @@ endgenerate .dout(exx_xu1_abort_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) exx_lq_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1271,7 +1317,8 @@ endgenerate .dout(exx_lq_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs1_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1284,7 +1331,8 @@ endgenerate .dout(ex2_rs1_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs2_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1297,7 +1345,8 @@ endgenerate .dout(ex2_rs2_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_rs3_abort_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -1310,7 +1359,8 @@ endgenerate .dout(ex2_rs3_abort_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) exx_rel3_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1323,7 +1373,8 @@ endgenerate .dout(exx_rel3_act_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel3_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(lq_xu_rel_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -1336,7 +1387,8 @@ endgenerate .dout(exx_rel3_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) exx_rel4_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_rel3_act_q), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), diff --git a/dev/verilog/work/xu1_dec.v b/dev/verilog/work/xu1_dec.v index 29f94b9..79d0af1 100755 --- a/dev/verilog/work/xu1_dec.v +++ b/dev/verilog/work/xu1_dec.v @@ -38,9 +38,10 @@ module xu1_dec( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -691,7 +692,8 @@ module xu1_dec( //------------------------------------------------------------------------------------------ tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -709,7 +711,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex1_s3_type_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -727,7 +730,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t1_v_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -745,7 +749,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t2_v_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -763,7 +768,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_t3_v_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -781,7 +787,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t1_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -799,7 +806,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t2_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -817,7 +825,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_t3_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -835,7 +844,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -853,7 +863,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex1_ucode_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -871,7 +882,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex1_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), @@ -889,7 +901,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_add_ci_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -907,7 +920,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -925,7 +939,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t1_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -943,7 +958,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t2_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -961,7 +977,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex2_t3_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -979,7 +996,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -997,7 +1015,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_gpr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1015,7 +1034,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1033,7 +1053,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1051,7 +1072,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_opsize_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1069,7 +1091,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_lswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1087,7 +1110,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_stswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1105,7 +1129,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t1_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1123,7 +1148,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t2_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1141,7 +1167,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`CR_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_t3_p_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1159,7 +1186,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`ITAG_SIZE_ENC), .INIT(0), .NEEDS_SRESET(1)) ex3_itag_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1177,7 +1205,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_gpr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1195,7 +1224,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1213,7 +1243,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_cr_we_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1231,7 +1262,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_lswx_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1249,7 +1281,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_strg_noop_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), @@ -1267,7 +1300,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1285,7 +1319,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1303,7 +1338,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1321,7 +1357,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1339,7 +1376,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1357,7 +1395,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_stq_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1375,7 +1414,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_val_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), @@ -1393,7 +1433,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) msr_cm_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1411,7 +1452,8 @@ module xu1_dec( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_ram_active_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1429,7 +1471,8 @@ module xu1_dec( ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/8), .INIT(0), .NEEDS_SRESET(1)) ex2_dvc_mask_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), diff --git a/dev/verilog/work/xu_alu.v b/dev/verilog/work/xu_alu.v index 5ac5f7c..d4a03be 100755 --- a/dev/verilog/work/xu_alu.v +++ b/dev/verilog/work/xu_alu.v @@ -36,7 +36,8 @@ module xu_alu( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, inout vdd, inout gnd, @@ -180,7 +181,8 @@ module xu_alu( //--------------------------------------------------------------- xu_alu_add add( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .delay_lclkr_dc(delay_lclkr_dc), @@ -210,7 +212,8 @@ module xu_alu( 1'b0; tri_st_rot rot( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -247,7 +250,8 @@ module xu_alu( //--------------------------------------------------------------- xu_alu_cmp cmp( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .d_mode_dc(d_mode_dc), @@ -280,7 +284,8 @@ module xu_alu( //--------------------------------------------------------------- tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -298,7 +303,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_isel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -316,7 +322,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -334,7 +341,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_trap_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -352,7 +360,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmpl_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -370,7 +379,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -388,7 +398,8 @@ module xu_alu( ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_6to10_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -406,7 +417,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -424,7 +436,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ca_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dec_alu_ex1_act), @@ -442,7 +455,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ca_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -460,7 +474,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_add_ovf_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -478,7 +493,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_rot_log_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -496,7 +512,8 @@ module xu_alu( ); tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -514,7 +531,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), @@ -532,7 +550,8 @@ module xu_alu( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ca_en_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act_q), diff --git a/dev/verilog/work/xu_alu_add.v b/dev/verilog/work/xu_alu_add.v index c569f79..0a8ecd2 100755 --- a/dev/verilog/work/xu_alu_add.v +++ b/dev/verilog/work/xu_alu_add.v @@ -37,9 +37,10 @@ module xu_alu_add //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -175,7 +176,8 @@ module xu_alu_add .vd(vdd), .gd(gnd), .act(ex1_act), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_sl_force), .thold_b(func_sl_thold_0_b), .delay_lclkr(delay_lclkr_dc), diff --git a/dev/verilog/work/xu_alu_cmp.v b/dev/verilog/work/xu_alu_cmp.v index 7ba95ca..720f5f7 100755 --- a/dev/verilog/work/xu_alu_cmp.v +++ b/dev/verilog/work/xu_alu_cmp.v @@ -34,7 +34,8 @@ `include "tri_a2o.vh" module xu_alu_cmp( // Clocks - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // Power inout vdd, @@ -167,7 +168,8 @@ module xu_alu_cmp( // Latch Instances tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_msb_64b_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -185,7 +187,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_msb_64b_sel_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -203,7 +206,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_diff_sign_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -221,7 +225,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs1_trm1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -239,7 +244,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_rs2_trm1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -257,7 +263,8 @@ module xu_alu_cmp( ); tri_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -275,7 +282,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_trap_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -293,7 +301,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmpl_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), @@ -311,7 +320,8 @@ module xu_alu_cmp( ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sel_cmp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_act), diff --git a/dev/verilog/work/xu_fctr.v b/dev/verilog/work/xu_fctr.v index 2ff030a..191411e 100755 --- a/dev/verilog/work/xu_fctr.v +++ b/dev/verilog/work/xu_fctr.v @@ -41,7 +41,8 @@ module xu_fctr parameter WIDTH = 2 ) ( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, input force_t, input thold_b, @@ -108,9 +109,9 @@ module xu_fctr assign dout[t] = zero_b[t]; end - tri_rlmreg_p #(.WIDTH(DELAY_WIDTH), .INIT(0), .NEEDS_SRESET(1)) delay_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(act[t]), diff --git a/dev/verilog/work/xu_gpr.v b/dev/verilog/work/xu_gpr.v index 21e8ba5..1e6908f 100755 --- a/dev/verilog/work/xu_gpr.v +++ b/dev/verilog/work/xu_gpr.v @@ -36,9 +36,10 @@ module xu_gpr( //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -162,7 +163,8 @@ module xu_gpr( tri_144x78_2r4w gpr0( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), .mpw2_dc_b(mpw2_dc_b), @@ -197,7 +199,8 @@ module xu_gpr( tri_144x78_2r4w gpr1( .vdd(vdd), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .delay_lclkr_dc(delay_lclkr_dc), .mpw1_dc_b(mpw1_dc_b), .mpw2_dc_b(mpw2_dc_b), @@ -230,7 +233,8 @@ module xu_gpr( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -248,7 +252,8 @@ module xu_gpr( ); tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), diff --git a/dev/verilog/work/xu_rf.v b/dev/verilog/work/xu_rf.v index c920232..5d7c973 100755 --- a/dev/verilog/work/xu_rf.v +++ b/dev/verilog/work/xu_rf.v @@ -48,10 +48,10 @@ module xu_rf //------------------------------------------------------------------- // Clocks & Power //------------------------------------------------------------------- - (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk - input [0:`NCLK_WIDTH-1] nclk, inout vdd, inout gnd, + input clk, + input rst, //------------------------------------------------------------------- // Pervasive @@ -451,7 +451,8 @@ generate for (r=0;r<=POOL-1;r=r+1) begin : entry tri_regk #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) reg_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(reg_act[r]), @@ -472,7 +473,8 @@ endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r0e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -490,7 +492,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r0a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r0e_e), @@ -508,7 +511,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r0d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r0e_q), @@ -530,7 +534,8 @@ endgenerate begin : r1_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r1e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -548,7 +553,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r1e_e), @@ -566,7 +572,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r1e_q), @@ -589,7 +596,8 @@ endgenerate begin : r2_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r2e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -607,7 +615,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r2e_e), @@ -625,7 +634,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r2e_q), @@ -648,7 +658,8 @@ endgenerate begin : r3_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r3e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -666,7 +677,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r3a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r3e_e), @@ -684,7 +696,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r3d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r3e_q), @@ -707,7 +720,8 @@ endgenerate begin : r4_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) r4e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -725,7 +739,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r4a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r4e_e), @@ -743,7 +758,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) r4d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(r4e_q), @@ -763,7 +779,8 @@ endgenerate endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w0e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -781,7 +798,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w0a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w0e_e), @@ -799,7 +817,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w0d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w0e_e), @@ -820,7 +839,8 @@ endgenerate begin : w1_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -838,7 +858,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w1e_e), @@ -856,7 +877,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w1d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w1e_e), @@ -879,7 +901,8 @@ endgenerate begin : w2_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -897,7 +920,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w2e_e), @@ -915,7 +939,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w2e_e), @@ -938,7 +963,8 @@ endgenerate begin : w3_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -956,7 +982,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w3e_e), @@ -974,7 +1001,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w3e_e), @@ -997,7 +1025,8 @@ endgenerate begin : w4_gen1 tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1015,7 +1044,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w4e_e), @@ -1033,7 +1063,8 @@ endgenerate ); tri_rlmreg_p #(.WIDTH(WIDTH), .INIT(0), .NEEDS_SRESET(1)) w4d_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(w4e_e), diff --git a/dev/verilog/work/xu_spr.v b/dev/verilog/work/xu_spr.v index aa8ceaf..38f6697 100755 --- a/dev/verilog/work/xu_spr.v +++ b/dev/verilog/work/xu_spr.v @@ -37,8 +37,8 @@ module xu_spr parameter hvmode = 1, parameter a2mode = 1 )( - input [0:`NCLK_WIDTH-1] nclk, - + input clk, + input rst, // CHIP IO input [54:61] an_ac_coreid, input [32:35] an_ac_chipid_dc, @@ -669,7 +669,8 @@ module xu_spr xu_spr_cspr #(.hvmode(hvmode), .a2mode(a2mode)) xu_spr_cspr( - .nclk(nclk), + .clk(clk), + .rst(rst), // CHIP IO .an_ac_sleep_en(an_ac_sleep_en), .an_ac_reservation_vld(an_ac_reservation_vld), @@ -910,7 +911,8 @@ module xu_spr begin : thread xu_spr_tspr #(.hvmode(hvmode), .a2mode(a2mode)) xu_spr_tspr( - .nclk(nclk), + .clk(clk), + .rst(rst), // CHIP IO .an_ac_ext_interrupt(an_ac_ext_interrupt[t]), .an_ac_crit_interrupt(an_ac_crit_interrupt[t]), @@ -1107,7 +1109,8 @@ module xu_spr .vdd(vdd), .vcs(vcs), .gnd(gnd), - .nclk(nclk), + .clk(clk), + .rst(rst), .sg_0(sg_0[0]), .abst_sl_thold_0(abst_sl_thold_0), .ary_nsl_thold_0(ary_nsl_thold_0), @@ -1188,7 +1191,8 @@ module xu_spr // FUNC Latch Instances tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_1_request_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1206,7 +1210,8 @@ module xu_spr ); tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_2_request_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1224,7 +1229,8 @@ module xu_spr ); tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_3_request_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1242,7 +1248,8 @@ module xu_spr ); tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) reset_wd_request_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), @@ -1265,7 +1272,8 @@ module xu_spr begin : thread tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) int_rest_ifar_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(int_rest_act[r]), @@ -1286,7 +1294,8 @@ module xu_spr endgenerate tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) trace_bus_enable_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force[0]), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1299,7 +1308,8 @@ module xu_spr .dout(trace_bus_enable_q) ); tri_rlmreg_p #(.WIDTH(11), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) debug_mux_ctrls_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(trace_bus_enable_q), .force_t(func_slp_sl_force[0]), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1312,7 +1322,8 @@ module xu_spr .dout(debug_mux_ctrls_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) debug_data_out_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(trace_bus_enable_q), .force_t(func_slp_sl_force[0]), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), @@ -1328,7 +1339,8 @@ module xu_spr // ABST Latch Instances tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_wenb_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1346,7 +1358,8 @@ module xu_spr ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) abist_waddr_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1364,7 +1377,8 @@ module xu_spr ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) abist_di_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1382,7 +1396,8 @@ module xu_spr ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t1p_renb_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1400,7 +1415,8 @@ module xu_spr ); tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) abist_raddr_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1418,7 +1434,8 @@ module xu_spr ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_wl32_comp_ena_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1436,7 +1453,8 @@ module xu_spr ); tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) abist_g8t_dcomp_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1454,7 +1472,8 @@ module xu_spr ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_bw_1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1472,7 +1491,8 @@ module xu_spr ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) abist_g8t_bw_0_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_abist_ena_dc), @@ -1490,7 +1510,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1501,7 +1522,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1512,7 +1534,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1523,7 +1546,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1534,7 +1558,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1545,7 +1570,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1556,7 +1582,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1567,7 +1594,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1578,7 +1606,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1589,7 +1618,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1600,7 +1630,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1611,7 +1642,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1622,7 +1654,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1633,7 +1666,8 @@ module xu_spr ); tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1644,7 +1678,8 @@ module xu_spr ); tri_regs #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_in_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1655,7 +1690,8 @@ module xu_spr ); tri_regs #(.WIDTH((`THREADS+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_out_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .force_t(so_force), @@ -1673,7 +1709,8 @@ module xu_spr .vdd(vdd), .gnd(gnd), .sg(sg_0[0]), - .nclk(nclk), + .clk(clk), + .rst(rst), .scan_diag_dc(an_ac_scan_diag_dc), .thold(gptr_sl_thold_0), .clkoff_dc_b(g8t_clkoff_dc_b), @@ -1687,20 +1724,34 @@ module xu_spr ); - tri_plat #(.WIDTH(1)) perv_2to1_reg_00 (.din(func_slp_sl_thold_2 ),.q(func_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_01 (.din(func_sl_thold_2 ),.q(func_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_02 (.din(func_slp_nsl_thold_2 ),.q(func_slp_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_03 (.din(func_nsl_thold_2 ),.q(func_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_04 (.din(time_sl_thold_2 ),.q(time_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_05 (.din(repr_sl_thold_2 ),.q(repr_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_06 (.din(gptr_sl_thold_2 ),.q(gptr_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_07 (.din(bolt_sl_thold_2 ),.q(bolt_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_08 (.din(abst_sl_thold_2 ),.q(abst_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_09 (.din(ary_nsl_thold_2 ),.q(ary_nsl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_10 (.din(cfg_sl_thold_2 ),.q(cfg_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_11 (.din(cfg_slp_sl_thold_2 ),.q(cfg_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_12 (.din(sg_2 ),.q(sg_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_2to1_reg_13 (.din(fce_2 ),.q(fce_1 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_00 (.din(func_slp_sl_thold_2 ),.q(func_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_01 (.din(func_sl_thold_2 ),.q(func_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_02 (.din(func_slp_nsl_thold_2 ),.q(func_slp_nsl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_03 (.din(func_nsl_thold_2 ),.q(func_nsl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_04 (.din(time_sl_thold_2 ),.q(time_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_05 (.din(repr_sl_thold_2 ),.q(repr_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_06 (.din(gptr_sl_thold_2 ),.q(gptr_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_07 (.din(bolt_sl_thold_2 ),.q(bolt_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_08 (.din(abst_sl_thold_2 ),.q(abst_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_09 (.din(ary_nsl_thold_2 ),.q(ary_nsl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_10 (.din(cfg_sl_thold_2 ),.q(cfg_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_11 (.din(cfg_slp_sl_thold_2 ),.q(cfg_slp_sl_thold_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_12 (.din(sg_2 ),.q(sg_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_2to1_reg_13 (.din(fce_2 ),.q(fce_1 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); generate begin : perv_1to0_reg_gen @@ -1708,12 +1759,18 @@ module xu_spr for (t = 0; t <= `THREADS; t = t + 1) begin : thread - tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(func_slp_sl_thold_1),.q(func_slp_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(func_sl_thold_1 ),.q(func_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(func_nsl_thold_1 ),.q(func_nsl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(cfg_sl_thold_1 ),.q(cfg_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(sg_1 ),.q(sg_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(fce_1 ),.q(fce_0[t] ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(func_slp_sl_thold_1),.q(func_slp_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(func_sl_thold_1 ),.q(func_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(func_nsl_thold_1 ),.q(func_nsl_thold_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(cfg_sl_thold_1 ),.q(cfg_sl_thold_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(sg_1 ),.q(sg_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(fce_1 ),.q(fce_0[t] ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); tri_lcbor perv_lcbor_cfg_sl( @@ -1792,14 +1849,22 @@ module xu_spr ); - tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(abst_sl_thold_1 ),.q(abst_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(ary_nsl_thold_1 ),.q(ary_nsl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(time_sl_thold_1 ),.q(time_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(repr_sl_thold_1 ),.q(repr_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(gptr_sl_thold_1 ),.q(gptr_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(bolt_sl_thold_1 ),.q(bolt_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_6 (.din(func_slp_nsl_thold_1 ),.q(func_slp_nsl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); - tri_plat #(.WIDTH(1)) perv_1to0_reg_7 (.din(cfg_slp_sl_thold_1 ),.q(cfg_slp_sl_thold_0 ),.vd(vdd),.gd(gnd),.nclk(nclk),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_0 (.din(abst_sl_thold_1 ),.q(abst_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_1 (.din(ary_nsl_thold_1 ),.q(ary_nsl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_2 (.din(time_sl_thold_1 ),.q(time_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_3 (.din(repr_sl_thold_1 ),.q(repr_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_4 (.din(gptr_sl_thold_1 ),.q(gptr_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_5 (.din(bolt_sl_thold_1 ),.q(bolt_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_6 (.din(func_slp_nsl_thold_1 ),.q(func_slp_nsl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); + tri_plat #(.WIDTH(1)) perv_1to0_reg_7 (.din(cfg_slp_sl_thold_1 ),.q(cfg_slp_sl_thold_0 ),.vd(vdd),.gd(gnd),.clk(clk), + .rst(rst),.flush(pc_xu_ccflush_dc)); tri_lcbor perv_lcbor_abst_sl( diff --git a/dev/verilog/work/xu_spr_cspr.v b/dev/verilog/work/xu_spr_cspr.v index d32be15..a90e4b6 100755 --- a/dev/verilog/work/xu_spr_cspr.v +++ b/dev/verilog/work/xu_spr_cspr.v @@ -38,8 +38,9 @@ module xu_spr_cspr parameter a2mode = 1, parameter spr_xucr0_init = `INIT_XUCR0 )( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // CHIP IO input [0:`THREADS-1] an_ac_reservation_vld, input an_ac_tb_update_enable, @@ -2933,7 +2934,8 @@ wire [0:0] core_event; }; tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(ccr0_act), .force_t(bcfg_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2946,7 +2948,8 @@ wire [0:0] core_event; .dout(ccr0_q) ); tri_ser_rlmreg_p #(.WIDTH(24), .INIT(3994575), .NEEDS_SRESET(1)) ccr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(ccr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2959,7 +2962,8 @@ wire [0:0] core_event; .dout(ccr1_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(1), .NEEDS_SRESET(1)) ccr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(ccr2_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2972,7 +2976,8 @@ wire [0:0] core_event; .dout(ccr2_q) ); tri_ser_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccr4_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(ccr4_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2985,7 +2990,8 @@ wire [0:0] core_event; .dout(ccr4_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbl_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(tbl_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2998,7 +3004,8 @@ wire [0:0] core_event; .dout(tbl_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) tbu_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(tbu_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3011,7 +3018,8 @@ wire [0:0] core_event; .dout(tbu_q) ); tri_ser_rlmreg_p #(.WIDTH(`THREADS), .INIT(1), .NEEDS_SRESET(1)) tens_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(tens_act), .force_t(bcfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3024,7 +3032,8 @@ wire [0:0] core_event; .dout(tens_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xesr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3037,7 +3046,8 @@ wire [0:0] core_event; .dout(xesr1_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) xesr2_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xesr2_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3050,7 +3060,8 @@ wire [0:0] core_event; .dout(xesr2_q) ); tri_ser_rlmreg_p #(.WIDTH(26), .INIT((spr_xucr0_init)), .NEEDS_SRESET(1)) xucr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xucr0_act), .force_t(ccfg_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3063,7 +3074,8 @@ wire [0:0] core_event; .dout(xucr0_q) ); tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) xucr4_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xucr4_act), .force_t(dcfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3080,7 +3092,8 @@ wire [0:0] core_event; // Latch Instances tri_rlmreg_p #(.WIDTH(4), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3093,7 +3106,8 @@ wire [0:0] core_event; .dout(exx_act_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex0_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX0]), @@ -3106,7 +3120,8 @@ wire [0:0] core_event; .dout(ex0_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3119,7 +3134,8 @@ wire [0:0] core_event; .dout(ex1_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3132,7 +3148,8 @@ wire [0:0] core_event; .dout(ex1_aspr_act_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_aspr_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3145,7 +3162,8 @@ wire [0:0] core_event; .dout(ex1_aspr_tid_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3158,7 +3176,8 @@ wire [0:0] core_event; .dout(ex1_tid_q) ); tri_rlmreg_p #(.WIDTH(32), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex1_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3171,7 +3190,8 @@ wire [0:0] core_event; .dout(ex1_instr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex1_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -3184,7 +3204,8 @@ wire [0:0] core_event; .dout(ex1_msr_gs_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3197,7 +3218,8 @@ wire [0:0] core_event; .dout(ex2_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_rd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3210,7 +3232,8 @@ wire [0:0] core_event; .dout(ex2_val_rd_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_val_wr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3223,7 +3246,8 @@ wire [0:0] core_event; .dout(ex2_val_wr_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3236,7 +3260,8 @@ wire [0:0] core_event; .dout(ex2_tid_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3249,7 +3274,8 @@ wire [0:0] core_event; .dout(ex2_aspr_addr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3262,7 +3288,8 @@ wire [0:0] core_event; .dout(ex2_is_mfspr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mftb_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3275,7 +3302,8 @@ wire [0:0] core_event; .dout(ex2_is_mftb_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3288,7 +3316,8 @@ wire [0:0] core_event; .dout(ex2_is_mtmsr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3301,7 +3330,8 @@ wire [0:0] core_event; .dout(ex2_is_mtspr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_wait_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3314,7 +3344,8 @@ wire [0:0] core_event; .dout(ex2_is_wait_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_priv_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3327,7 +3358,8 @@ wire [0:0] core_event; .dout(ex2_priv_instr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_hypv_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3340,7 +3372,8 @@ wire [0:0] core_event; .dout(ex2_hypv_instr_q) ); tri_regk #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex2_wait_wc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3353,7 +3386,8 @@ wire [0:0] core_event; .dout(ex2_wait_wc_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_msgclr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3366,7 +3400,8 @@ wire [0:0] core_event; .dout(ex2_is_msgclr_q) ); tri_regk #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3379,7 +3414,8 @@ wire [0:0] core_event; .dout(ex2_instr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3392,7 +3428,8 @@ wire [0:0] core_event; .dout(ex2_msr_gs_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_tenc_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3405,7 +3442,8 @@ wire [0:0] core_event; .dout(ex2_tenc_we_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_ccr0_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3418,7 +3456,8 @@ wire [0:0] core_event; .dout(ex2_ccr0_we_q) ); tri_regk #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex2_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3431,7 +3470,8 @@ wire [0:0] core_event; .dout(ex2_aspr_re_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3444,7 +3484,8 @@ wire [0:0] core_event; .dout(ex2_dnh_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3457,7 +3498,8 @@ wire [0:0] core_event; .dout(ex3_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_val_rd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3470,7 +3512,8 @@ wire [0:0] core_event; .dout(ex3_val_rd_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_wr_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3483,7 +3526,8 @@ wire [0:0] core_event; .dout(ex3_sspr_wr_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sspr_rd_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3496,7 +3540,8 @@ wire [0:0] core_event; .dout(ex3_sspr_rd_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3509,7 +3554,8 @@ wire [0:0] core_event; .dout(ex3_spr_we_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3522,7 +3568,8 @@ wire [0:0] core_event; .dout(ex3_aspr_we_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex2_aspr_addr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3535,7 +3582,8 @@ wire [0:0] core_event; .dout(ex3_aspr_addr_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3548,7 +3596,8 @@ wire [0:0] core_event; .dout(ex3_tid_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_rdata_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3561,7 +3610,8 @@ wire [0:0] core_event; .dout(ex3_aspr_rdata_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3574,7 +3624,8 @@ wire [0:0] core_event; .dout(ex3_is_mtspr_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(9),.INIT(0), .NEEDS_SRESET(1)) ex3_wait_wc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3587,7 +3638,8 @@ wire [0:0] core_event; .dout(ex3_wait_wc_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_msgclr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3600,7 +3652,8 @@ wire [0:0] core_event; .dout(ex3_is_msgclr_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(11),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3613,7 +3666,8 @@ wire [0:0] core_event; .dout(ex3_instr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_cspr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3626,7 +3680,8 @@ wire [0:0] core_event; .dout(ex3_cspr_rt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_hypv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3639,7 +3694,8 @@ wire [0:0] core_event; .dout(ex3_hypv_spr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_illeg_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3652,7 +3708,8 @@ wire [0:0] core_event; .dout(ex3_illeg_spr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_priv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3665,7 +3722,8 @@ wire [0:0] core_event; .dout(ex3_priv_spr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+8), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_rt_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3678,7 +3736,8 @@ wire [0:0] core_event; .dout(ex3_rt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3691,7 +3750,8 @@ wire [0:0] core_event; .dout(ex3_wait_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_ce_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3704,7 +3764,8 @@ wire [0:0] core_event; .dout(ex3_aspr_ce_addr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex3_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3717,7 +3778,8 @@ wire [0:0] core_event; .dout(ex3_aspr_re_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3730,7 +3792,8 @@ wire [0:0] core_event; .dout(ex4_val_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/32), .OFFSET(2-`GPR_WIDTH/32),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_re_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3743,7 +3806,8 @@ wire [0:0] core_event; .dout(ex4_aspr_re_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_spr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3756,7 +3820,8 @@ wire [0:0] core_event; .dout(ex4_spr_rt_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex4_corr_rdata_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[3]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3769,7 +3834,8 @@ wire [0:0] core_event; .dout(ex4_corr_rdata_q) ); tri_regk #(.WIDTH(`GPR_WIDTH/8+1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3782,7 +3848,8 @@ wire [0:0] core_event; .dout(ex4_sprg_ce_q) ); tri_regk #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_aspr_ce_addr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(ex3_sprg_ce), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3795,7 +3862,8 @@ wire [0:0] core_event; .dout(ex4_aspr_ce_addr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_hypv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3808,7 +3876,8 @@ wire [0:0] core_event; .dout(ex4_hypv_spr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_illeg_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3821,7 +3890,8 @@ wire [0:0] core_event; .dout(ex4_illeg_spr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_priv_spr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3834,7 +3904,8 @@ wire [0:0] core_event; .dout(ex4_priv_spr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[3]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3847,7 +3918,8 @@ wire [0:0] core_event; .dout(ex4_np1_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -3860,7 +3932,8 @@ wire [0:0] core_event; .dout(ex5_sprg_ce_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_sprg_ue_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -3873,7 +3946,8 @@ wire [0:0] core_event; .dout(ex4_sprg_ue_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_sprg_ue_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX5]), @@ -3886,7 +3960,8 @@ wire [0:0] core_event; .dout(ex5_sprg_ue_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_dbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3899,7 +3974,8 @@ wire [0:0] core_event; .dout(cpl_dbell_taken_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_cdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3912,7 +3988,8 @@ wire [0:0] core_event; .dout(cpl_cdbell_taken_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3925,7 +4002,8 @@ wire [0:0] core_event; .dout(cpl_gdbell_taken_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gcdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3938,7 +4016,8 @@ wire [0:0] core_event; .dout(cpl_gcdbell_taken_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cpl_gmcdbell_taken_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3951,7 +4030,8 @@ wire [0:0] core_event; .dout(cpl_gmcdbell_taken_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cslc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3964,7 +4044,8 @@ wire [0:0] core_event; .dout(set_xucr0_cslc_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_cul_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3977,7 +4058,8 @@ wire [0:0] core_event; .dout(set_xucr0_cul_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) set_xucr0_clo_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3990,7 +4072,8 @@ wire [0:0] core_event; .dout(set_xucr0_clo_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_np1_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4003,7 +4086,8 @@ wire [0:0] core_event; .dout(ex3_np1_flush_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) running_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4016,7 +4100,8 @@ wire [0:0] core_event; .dout(running_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(2**(`THREADS-1)), .NEEDS_SRESET(1)) llpri_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(llpri_inc), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4029,7 +4114,8 @@ wire [0:0] core_event; .dout(llpri_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dec_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4042,7 +4128,8 @@ wire [0:0] core_event; .dout(dec_dbg_dis_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4055,7 +4142,8 @@ wire [0:0] core_event; .dout(tb_dbg_dis_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4068,7 +4156,8 @@ wire [0:0] core_event; .dout(tb_act_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ext_dbg_dis_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4081,7 +4170,8 @@ wire [0:0] core_event; .dout(ext_dbg_dis_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4094,7 +4184,8 @@ wire [0:0] core_event; .dout(msrovride_enab_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitimpl_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4107,7 +4198,8 @@ wire [0:0] core_event; .dout(waitimpl_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) waitrsv_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4120,7 +4212,8 @@ wire [0:0] core_event; .dout(waitrsv_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_reservation_vld_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4133,7 +4226,8 @@ wire [0:0] core_event; .dout(an_ac_reservation_vld_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) an_ac_sleep_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4146,7 +4240,8 @@ wire [0:0] core_event; .dout(an_ac_sleep_en_q) ); tri_rlmreg_p #(.WIDTH(8), .OFFSET(54),.INIT(0), .NEEDS_SRESET(1)) an_ac_coreid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4159,7 +4254,8 @@ wire [0:0] core_event; .dout(an_ac_coreid_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_enable_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4172,7 +4268,8 @@ wire [0:0] core_event; .dout(tb_update_enable_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4185,7 +4282,8 @@ wire [0:0] core_event; .dout(tb_update_pulse_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) tb_update_pulse_1_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4198,7 +4296,8 @@ wire [0:0] core_event; .dout(tb_update_pulse_1_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_wd_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4211,7 +4310,8 @@ wire [0:0] core_event; .dout(pc_xu_reset_wd_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_3_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4224,7 +4324,8 @@ wire [0:0] core_event; .dout(pc_xu_reset_3_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_2_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4237,7 +4338,8 @@ wire [0:0] core_event; .dout(pc_xu_reset_2_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_reset_1_complete_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4250,7 +4352,8 @@ wire [0:0] core_event; .dout(pc_xu_reset_1_complete_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4263,7 +4366,8 @@ wire [0:0] core_event; .dout(lq_xu_dbell_val_q) ); tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_type_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4276,7 +4380,8 @@ wire [0:0] core_event; .dout(lq_xu_dbell_type_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_brdcast_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4289,7 +4394,8 @@ wire [0:0] core_event; .dout(lq_xu_dbell_brdcast_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_lpid_match_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4302,7 +4408,8 @@ wire [0:0] core_event; .dout(lq_xu_dbell_lpid_match_q) ); tri_rlmreg_p #(.WIDTH(14), .OFFSET(50),.INIT(0), .NEEDS_SRESET(1)) lq_xu_dbell_pirtag_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4315,7 +4422,8 @@ wire [0:0] core_event; .dout(lq_xu_dbell_pirtag_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4328,7 +4436,8 @@ wire [0:0] core_event; .dout(dbell_present_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4341,7 +4450,8 @@ wire [0:0] core_event; .dout(cdbell_present_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4354,7 +4464,8 @@ wire [0:0] core_event; .dout(gdbell_present_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4367,7 +4478,8 @@ wire [0:0] core_event; .dout(gcdbell_present_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_present_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4380,7 +4492,8 @@ wire [0:0] core_event; .dout(gmcdbell_present_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xucr0_clfc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4393,7 +4506,8 @@ wire [0:0] core_event; .dout(xucr0_clfc_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_run_thread_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4406,7 +4520,8 @@ wire [0:0] core_event; .dout(iu_run_thread_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) inj_sprg_ecc_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4419,7 +4534,8 @@ wire [0:0] core_event; .dout(inj_sprg_ecc_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4432,7 +4548,8 @@ wire [0:0] core_event; .dout(dbell_interrupt_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) cdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4445,7 +4562,8 @@ wire [0:0] core_event; .dout(cdbell_interrupt_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4458,7 +4576,8 @@ wire [0:0] core_event; .dout(gdbell_interrupt_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gcdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4471,7 +4590,8 @@ wire [0:0] core_event; .dout(gcdbell_interrupt_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) gmcdbell_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4484,7 +4604,8 @@ wire [0:0] core_event; .dout(gmcdbell_interrupt_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4497,7 +4618,8 @@ wire [0:0] core_event; .dout(iu_quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_icache_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4510,7 +4632,8 @@ wire [0:0] core_event; .dout(iu_icache_quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) lsu_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4523,7 +4646,8 @@ wire [0:0] core_event; .dout(lsu_quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mm_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4536,7 +4660,8 @@ wire [0:0] core_event; .dout(mm_quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) bx_quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4549,7 +4674,8 @@ wire [0:0] core_event; .dout(bx_quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesce_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4562,7 +4688,8 @@ wire [0:0] core_event; .dout(quiesce_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) quiesced_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4575,7 +4702,8 @@ wire [0:0] core_event; .dout(quiesced_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) instr_trace_mode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4588,7 +4716,8 @@ wire [0:0] core_event; .dout(instr_trace_mode_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) instr_trace_tid_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4601,7 +4730,8 @@ wire [0:0] core_event; .dout(instr_trace_tid_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) timer_update_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4614,7 +4744,8 @@ wire [0:0] core_event; .dout(timer_update_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_read_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4627,7 +4758,8 @@ wire [0:0] core_event; .dout(spr_xu_ord_read_done_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_xu_ord_write_done_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4640,7 +4772,8 @@ wire [0:0] core_event; .dout(spr_xu_ord_write_done_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) xu_spr_ord_ready_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4653,7 +4786,8 @@ wire [0:0] core_event; .dout(xu_spr_ord_ready_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_sspr_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4666,7 +4800,8 @@ wire [0:0] core_event; .dout(ex4_sspr_val_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4679,7 +4814,8 @@ wire [0:0] core_event; .dout(flush_q) ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex1_ifar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[0]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX1]), @@ -4692,7 +4828,8 @@ wire [0:0] core_event; .dout(ex1_ifar_q) ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .OFFSET(62-`EFF_IFAR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex2_ifar_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -4705,7 +4842,8 @@ wire [0:0] core_event; .dout(ex2_ifar_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4718,7 +4856,8 @@ wire [0:0] core_event; .dout(ram_active_q) ); tri_rlmreg_p #(.WIDTH(5), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timer_div_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(timer_div_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4731,7 +4870,8 @@ wire [0:0] core_event; .dout(timer_div_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4744,7 +4884,8 @@ wire [0:0] core_event; .dout(msrovride_enab_2_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) msrovride_enab_3_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4757,7 +4898,8 @@ wire [0:0] core_event; .dout(msrovride_enab_3_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wait_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4770,7 +4912,8 @@ wire [0:0] core_event; .dout(ex3_wait_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_wait_flush_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX4]), @@ -4783,7 +4926,8 @@ wire [0:0] core_event; .dout(ex4_wait_flush_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_pm_hold_thread_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4796,7 +4940,8 @@ wire [0:0] core_event; .dout(pc_xu_pm_hold_thread_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) power_savings_on_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4809,7 +4954,8 @@ wire [0:0] core_event; .dout(power_savings_on_q) ); tri_rlmreg_p #(.WIDTH(4*`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_bus_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_event_bus_enable), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4822,7 +4968,8 @@ wire [0:0] core_event; .dout(perf_event_bus_q) ); tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) perf_event_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(pc_xu_event_bus_enable), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4840,7 +4987,8 @@ wire [0:0] core_event; .vd(vdd), .gd(gnd), .act(1'b1), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_sl_force), .thold_b(func_sl_thold_0_b), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4866,7 +5014,8 @@ wire [0:0] core_event; assign spare_0_d = (~spare_0_q); xu_fctr #(.WIDTH(`THREADS), .PASSTHRU(0), .DELAY_WIDTH(4), .CLOCKGATE(1)) quiesced_fctr( - .nclk(nclk), + .clk(clk), + .rst(rst), .vdd(vdd), .gnd(gnd), .force_t(func_sl_force), @@ -4885,7 +5034,8 @@ wire [0:0] core_event; tri_ser_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ccr0_we_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(bcfg_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), diff --git a/dev/verilog/work/xu_spr_tspr.v b/dev/verilog/work/xu_spr_tspr.v index 3d0b3c5..901e5e7 100755 --- a/dev/verilog/work/xu_spr_tspr.v +++ b/dev/verilog/work/xu_spr_tspr.v @@ -37,8 +37,9 @@ module xu_spr_tspr parameter hvmode = 1, parameter a2mode = 1 )( - input [0:`NCLK_WIDTH-1] nclk, + input clk, + input rst, // CHIP IO input an_ac_ext_interrupt, input an_ac_crit_interrupt, @@ -2729,7 +2730,8 @@ module xu_spr_tspr // SPR Latch Instances tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ccr3_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(ccr3_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2744,7 +2746,8 @@ module xu_spr_tspr generate if (a2mode == 1) begin : csrr0_latch_gen tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) csrr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(csrr0_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2764,7 +2767,8 @@ endgenerate generate if (a2mode == 1) begin : csrr1_latch_gen tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) csrr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(csrr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2782,7 +2786,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(21), .INIT(0), .NEEDS_SRESET(1)) dbcr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dbcr0_act), .force_t(dcfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2795,7 +2800,8 @@ endgenerate .dout(dbcr0_q) ); tri_ser_rlmreg_p #(.WIDTH(18), .INIT(0), .NEEDS_SRESET(1)) dbcr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dbcr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2808,7 +2814,8 @@ endgenerate .dout(dbcr1_q) ); tri_ser_rlmreg_p #(.WIDTH(20), .INIT(0), .NEEDS_SRESET(1)) dbsr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dbsr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2821,7 +2828,8 @@ endgenerate .dout(dbsr_q) ); tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dear_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dear_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2834,7 +2842,8 @@ endgenerate .dout(dear_q) ); tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) dec_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dec_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2849,7 +2858,8 @@ endgenerate generate if (a2mode == 1) begin : decar_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) decar_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(decar_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2867,7 +2877,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) dnhdr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(dnhdr_act), .force_t(dcfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2882,7 +2893,8 @@ endgenerate generate if (hvmode == 1) begin : epcr_latch_gen tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) epcr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(epcr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2900,7 +2912,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) esr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(esr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2915,7 +2928,8 @@ endgenerate generate if (hvmode == 1) begin : gdear_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) gdear_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gdear_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2935,7 +2949,8 @@ endgenerate generate if (hvmode == 1) begin : gdec_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) gdec_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gdec_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2955,7 +2970,8 @@ endgenerate generate if (hvmode == 1) begin : gdecar_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) gdecar_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gdecar_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2975,7 +2991,8 @@ endgenerate generate if (hvmode == 1) begin : gesr_latch_gen tri_ser_rlmreg_p #(.WIDTH(17), .INIT(0), .NEEDS_SRESET(1)) gesr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gesr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -2995,7 +3012,8 @@ endgenerate generate if (hvmode == 1) begin : gpir_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) gpir_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gpir_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3015,7 +3033,8 @@ endgenerate generate if (hvmode == 1) begin : gsrr0_latch_gen tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) gsrr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gsrr0_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3035,7 +3054,8 @@ endgenerate generate if (hvmode == 1) begin : gsrr1_latch_gen tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) gsrr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gsrr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3055,7 +3075,8 @@ endgenerate generate if (hvmode == 1) begin : gtcr_latch_gen tri_ser_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) gtcr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gtcr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3075,7 +3096,8 @@ endgenerate generate if (hvmode == 1) begin : gtsr_latch_gen tri_ser_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) gtsr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(gtsr_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3095,7 +3117,8 @@ endgenerate generate if (a2mode == 1) begin : mcsr_latch_gen tri_ser_rlmreg_p #(.WIDTH(15), .INIT(0), .NEEDS_SRESET(1)) mcsr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(mcsr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3115,7 +3138,8 @@ endgenerate generate if (a2mode == 1) begin : mcsrr0_latch_gen tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) mcsrr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(mcsrr0_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3135,7 +3159,8 @@ endgenerate generate if (a2mode == 1) begin : mcsrr1_latch_gen tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) mcsrr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(mcsrr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3153,7 +3178,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) msr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(msr_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3168,7 +3194,8 @@ endgenerate generate if (hvmode == 1) begin : msrp_latch_gen tri_ser_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) msrp_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(msrp_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3186,7 +3213,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH+2), .INIT(0), .NEEDS_SRESET(1)) siar_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(siar_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3199,7 +3227,8 @@ endgenerate .dout(siar_q) ); tri_ser_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(1)) srr0_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(srr0_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3212,7 +3241,8 @@ endgenerate .dout(srr0_q) ); tri_ser_rlmreg_p #(.WIDTH(14), .INIT(0), .NEEDS_SRESET(1)) srr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(srr1_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3227,7 +3257,8 @@ endgenerate generate if (a2mode == 1) begin : tcr_latch_gen tri_ser_rlmreg_p #(.WIDTH(12), .INIT(0), .NEEDS_SRESET(1)) tcr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(tcr_act), .force_t(func_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3247,7 +3278,8 @@ endgenerate generate if (a2mode == 1) begin : tsr_latch_gen tri_ser_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) tsr_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(tsr_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3267,7 +3299,8 @@ endgenerate generate if (a2mode == 1) begin : udec_latch_gen tri_ser_rlmreg_p #(.WIDTH(32), .INIT(2147483647), .NEEDS_SRESET(1)) udec_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(udec_act), .force_t(func_slp_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3285,7 +3318,8 @@ generate end endgenerate tri_ser_rlmreg_p #(.WIDTH(5), .INIT(0), .NEEDS_SRESET(1)) xucr1_latch( - .nclk(nclk),.vd(vdd),.gd(gnd), + .clk(clk), + .rst(rst),.vd(vdd),.gd(gnd), .act(xucr1_act), .force_t(ccfg_sl_force), .d_mode(d_mode_dc),.delay_lclkr(delay_lclkr_dc[DWR]), @@ -3307,7 +3341,8 @@ endgenerate begin : dvc1_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc1_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dvc1_act), @@ -3336,7 +3371,8 @@ endgenerate begin : dvc2_latch_gen tri_ser_rlmreg_p #(.WIDTH(`GPR_WIDTH), .INIT(0), .NEEDS_SRESET(1)) dvc2_latch( - .nclk(nclk), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dvc2_act), @@ -3363,7 +3399,8 @@ endgenerate // Latch Instances tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_xu_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3376,7 +3413,8 @@ endgenerate .dout(iu_xu_act_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(1),.INIT(0), .NEEDS_SRESET(1)) exx_act_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3389,7 +3427,8 @@ endgenerate .dout(exx_act_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mfmsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3402,7 +3441,8 @@ endgenerate .dout(ex2_is_mfmsr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_wrtee_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3415,7 +3455,8 @@ endgenerate .dout(ex2_wrtee_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_wrteei_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3428,7 +3469,8 @@ endgenerate .dout(ex2_wrteei_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_dnh_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3441,7 +3483,8 @@ endgenerate .dout(ex2_dnh_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtmsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3454,7 +3497,8 @@ endgenerate .dout(ex2_is_mtmsr_q) ); tri_regk #(.WIDTH(1), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex2_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3467,7 +3511,8 @@ endgenerate .dout(ex2_is_mtspr_q) ); tri_regk #(.WIDTH(15), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[1]), .force_t(func_nsl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX2]), @@ -3480,7 +3525,8 @@ endgenerate .dout(ex2_instr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtspr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3493,7 +3539,8 @@ endgenerate .dout(ex3_is_mtspr_q) ); tri_rlmreg_p #(.WIDTH(15), .OFFSET(6),.INIT(0), .NEEDS_SRESET(1)) ex3_instr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3506,7 +3553,8 @@ endgenerate .dout(ex3_instr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wrtee_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3519,7 +3567,8 @@ endgenerate .dout(ex3_wrtee_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_wrteei_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3532,7 +3581,8 @@ endgenerate .dout(ex3_wrteei_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dnh_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3545,7 +3595,8 @@ endgenerate .dout(ex3_dnh_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_mtmsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3558,7 +3609,8 @@ endgenerate .dout(ex3_is_mtmsr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfi_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3571,7 +3623,8 @@ endgenerate .dout(iu_rfi_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfgi_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3584,7 +3637,8 @@ endgenerate .dout(iu_rfgi_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfci_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3597,7 +3651,8 @@ endgenerate .dout(iu_rfci_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_rfmci_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3610,7 +3665,8 @@ endgenerate .dout(iu_rfmci_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_int_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3623,7 +3679,8 @@ endgenerate .dout(iu_int_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_gint_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3636,7 +3693,8 @@ endgenerate .dout(iu_gint_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_cint_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3649,7 +3707,8 @@ endgenerate .dout(iu_cint_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_mcint_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3662,7 +3721,8 @@ endgenerate .dout(iu_mcint_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) iu_dear_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_xu_dear_update), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3675,7 +3735,8 @@ endgenerate .dout(iu_dear_q) ); tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .OFFSET(62-`EFF_IFAR_ARCH),.INIT(0), .NEEDS_SRESET(1)) iu_nia_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_nia_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3688,7 +3749,8 @@ endgenerate .dout(iu_nia_q) ); tri_rlmreg_p #(.WIDTH(17), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_esr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_xu_esr_update), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3701,7 +3763,8 @@ endgenerate .dout(iu_esr_q) ); tri_rlmreg_p #(.WIDTH(15), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_mcsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3714,7 +3777,8 @@ endgenerate .dout(iu_mcsr_q) ); tri_rlmreg_p #(.WIDTH(19), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_xu_dbsr_update), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3727,7 +3791,8 @@ endgenerate .dout(iu_dbsr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dear_update_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3740,7 +3805,8 @@ endgenerate .dout(iu_dear_update_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_update_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3753,7 +3819,8 @@ endgenerate .dout(iu_dbsr_update_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_esr_update_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3766,7 +3833,8 @@ endgenerate .dout(iu_esr_update_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_force_gsrr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(iu_int_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3779,7 +3847,8 @@ endgenerate .dout(iu_force_gsrr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_ude_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3792,7 +3861,8 @@ endgenerate .dout(iu_dbsr_ude_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu_dbsr_ide_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3805,7 +3875,8 @@ endgenerate .dout(iu_dbsr_ide_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_spr_wd_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3818,7 +3889,8 @@ endgenerate .dout(ex3_spr_wd_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH/8), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex3_tid_rpwr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3831,7 +3903,8 @@ endgenerate .dout(ex3_tid_rpwr_q) ); tri_rlmreg_p #(.WIDTH(`GPR_WIDTH), .OFFSET(64-`GPR_WIDTH),.INIT(0), .NEEDS_SRESET(1)) ex3_tspr_rt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(exx_act_data[2]), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -3844,7 +3917,8 @@ endgenerate .dout(ex3_tspr_rt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_tb_tap_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3857,7 +3931,8 @@ endgenerate .dout(fit_tb_tap_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_tb_tap_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3870,7 +3945,8 @@ endgenerate .dout(wdog_tb_tap_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_tb_tap_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3883,7 +3959,8 @@ endgenerate .dout(gfit_tb_tap_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_tb_tap_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3896,7 +3973,8 @@ endgenerate .dout(gwdog_tb_tap_q) ); tri_rlmreg_p #(.WIDTH(4), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) hang_pulse_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3909,7 +3987,8 @@ endgenerate .dout(hang_pulse_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) lltap_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3922,7 +4001,8 @@ endgenerate .dout(lltap_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) llcnt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3935,7 +4015,8 @@ endgenerate .dout(llcnt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_pr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3948,7 +4029,8 @@ endgenerate .dout(msrovride_pr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3961,7 +4043,8 @@ endgenerate .dout(msrovride_gs_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) msrovride_de_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3974,7 +4057,8 @@ endgenerate .dout(msrovride_de_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_ext_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -3987,7 +4071,8 @@ endgenerate .dout(an_ac_ext_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_crit_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4000,7 +4085,8 @@ endgenerate .dout(an_ac_crit_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4013,7 +4099,8 @@ endgenerate .dout(an_ac_perf_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4026,7 +4113,8 @@ endgenerate .dout(an_ac_perf_interrupt2_q) ); tri_rlmreg_p #(.WIDTH(3), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) mux_msr_gs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4039,7 +4127,8 @@ endgenerate .dout(mux_msr_gs_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mux_msr_pr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4052,7 +4141,8 @@ endgenerate .dout(mux_msr_pr_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_llbust_attempt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4065,7 +4155,8 @@ endgenerate .dout(err_llbust_attempt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_llbust_failed_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4078,7 +4169,8 @@ endgenerate .dout(err_llbust_failed_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_llbust_attempt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4091,7 +4183,8 @@ endgenerate .dout(inj_llbust_attempt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) inj_llbust_failed_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4104,7 +4197,8 @@ endgenerate .dout(inj_llbust_failed_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_external_mchk_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4117,7 +4211,8 @@ endgenerate .dout(an_ac_external_mchk_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) mchk_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4130,7 +4225,8 @@ endgenerate .dout(mchk_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) crit_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4143,7 +4239,8 @@ endgenerate .dout(crit_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) wdog_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4156,7 +4253,8 @@ endgenerate .dout(wdog_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) dec_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4169,7 +4267,8 @@ endgenerate .dout(dec_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) udec_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4182,7 +4281,8 @@ endgenerate .dout(udec_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) perf_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4195,7 +4295,8 @@ endgenerate .dout(perf_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) fit_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4208,7 +4309,8 @@ endgenerate .dout(fit_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ext_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4221,7 +4323,8 @@ endgenerate .dout(ext_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gwdog_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4234,7 +4337,8 @@ endgenerate .dout(gwdog_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gdec_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4247,7 +4351,8 @@ endgenerate .dout(gdec_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) gfit_interrupt_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4260,7 +4365,8 @@ endgenerate .dout(gfit_interrupt_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) single_instr_mode_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4273,7 +4379,8 @@ endgenerate .dout(single_instr_mode_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) single_instr_mode_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4286,7 +4393,8 @@ endgenerate .dout(single_instr_mode_2_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) machine_check_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4299,7 +4407,8 @@ endgenerate .dout(machine_check_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) raise_iss_pri_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4312,7 +4421,8 @@ endgenerate .dout(raise_iss_pri_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) raise_iss_pri_2_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4325,7 +4435,8 @@ endgenerate .dout(raise_iss_pri_2_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) pc_xu_inj_wdt_reset_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4338,7 +4449,8 @@ endgenerate .dout(pc_xu_inj_wdt_reset_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) err_wdt_reset_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4351,7 +4463,8 @@ endgenerate .dout(err_wdt_reset_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ram_active_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4364,7 +4477,8 @@ endgenerate .dout(ram_active_q) ); tri_rlmreg_p #(.WIDTH(10), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) timebase_taps_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_slp_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4377,7 +4491,8 @@ endgenerate .dout(timebase_taps_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) dbsr_mrr_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(dbsr_mrr_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4390,7 +4505,8 @@ endgenerate .dout(dbsr_mrr_q) ); tri_rlmreg_p #(.WIDTH(2), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) tsr_wrs_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(tsr_wrs_act), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4403,7 +4519,8 @@ endgenerate .dout(tsr_wrs_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac1_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4416,7 +4533,8 @@ endgenerate .dout(iac1_en_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac2_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4429,7 +4547,8 @@ endgenerate .dout(iac2_en_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac3_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4442,7 +4561,8 @@ endgenerate .dout(iac3_en_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iac4_en_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4455,7 +4575,8 @@ endgenerate .dout(iac4_en_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_dnh_val_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DEX3]), @@ -4468,7 +4589,8 @@ endgenerate .dout(ex3_dnh_val_q) ); tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) an_ac_perf_interrupt_edge_latch( - .nclk(nclk), .vd(vdd), .gd(gnd), + .clk(clk), + .rst(rst), .vd(vdd), .gd(gnd), .act(1'b1), .force_t(func_sl_force), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc[DX]), @@ -4485,7 +4607,8 @@ endgenerate .vd(vdd), .gd(gnd), .act(1'b1), - .nclk(nclk), + .clk(clk), + .rst(rst), .force_t(func_sl_force), .thold_b(func_sl_thold_0_b), .delay_lclkr(delay_lclkr_dc[DX]),