issues 13,14: single clk, no more nclk

pull/18/head
openpowerwtf 2 years ago
parent 24d56dc84b
commit af556071b0

@ -32,7 +32,8 @@


module a2owb ( module a2owb (


input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input scan_in, input scan_in,
output scan_out, output scan_out,


@ -183,7 +184,8 @@ wire [0:`THREADS-1] an_ac_sync_ack;
wire [0:`THREADS-1] an_ac_reservation_vld; wire [0:`THREADS-1] an_ac_reservation_vld;


c c0( c c0(
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(scan_in), .scan_in(scan_in),
.scan_out(scan_out), .scan_out(scan_out),


@ -308,7 +310,7 @@ c c0(
); );


a2l2wb n0( a2l2wb n0(
.clk(clk_1x), .clk(clk),
.rst(rst), .rst(rst),


// request // request
@ -437,11 +439,4 @@ a2l2wb n0(


); );


wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule endmodule

@ -34,7 +34,8 @@


module a2owb ( module a2owb (


input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input scan_in, input scan_in,
output scan_out, output scan_out,


@ -251,7 +252,8 @@ assign an_ac_lbist_ary_wrt_thru_dc = 0;




c c0( c c0(
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(scan_in), .scan_in(scan_in),
.scan_out(scan_out), .scan_out(scan_out),


@ -376,7 +378,7 @@ c c0(
); );


a2l2wb n0( a2l2wb n0(
.clk(clk_1x), .clk(clk),
.rst(rst), .rst(rst),


// request // request
@ -505,11 +507,4 @@ a2l2wb n0(


); );


wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule endmodule

@ -1,427 +0,0 @@
#!/usr/bin/python3
#
# Parse table comments and create equations.

from optparse import OptionParser
import re
from shutil import copyfile

#--------------------------------------------------------------------------------------------------
# Initialize

TYPE_INPUT = 0
TYPE_OUTPUT = 1
TYPE_SKIP = 99

lines = []
tableMatches = []
tableNames = []
tableLines = []
tables = {}

failOnError = True
inFile = 'test.vhdl'
outFileExt = 'vtable'
overwrite = True
backupExt = 'orig'
backup = True
noisy = False
quiet = False
verilog = False

#--------------------------------------------------------------------------------------------------
# Handle command line

usage = 'vtable [options] inFile'

parser = OptionParser(usage)
parser.add_option('-f', '--outfile', dest='outFile', help='output file, default=[inFile]' + outFileExt)
parser.add_option('-o', '--overwrite', dest='overwrite', help='overwrite inFile, default=' + str(overwrite))
parser.add_option('-b', '--backup', dest='backup', help='backup original file, default=' + str(backup))
parser.add_option('-q', '--quiet', dest='quiet', action='store_true', help='quiet messages, default=' + str(quiet))
parser.add_option('-n', '--noisy', dest='noisy', action='store_true', help='noisy messages, default=' + str(noisy))
parser.add_option('-V', '--verilog', dest='verilog', action='store_true', help='source is verilog, default=' + str(verilog))

options, args = parser.parse_args()

if len(args) != 1:
parser.error(usage)
quit(-1)
else:
inFile = args[0]

if options.overwrite == '0':
overwrite = False
elif options.overwrite == '1':
overwrite == True
if options.outFile is not None:
parser.error('Can\'t specify outfile and overrite!')
quit(-1)
elif options.overwrite is not None:
parser.error('overwrite: 0|1')
quit(-1)

if options.quiet is not None:
quiet = True

if options.noisy is not None:
noisy = True

if options.verilog is not None:
verilog = True

if options.backup == '0':
backup = False
elif options.backup == '1':
backup == True
elif options.backup is not None:
parser.error('backup: 0|1')
quit(-1)

if options.outFile is not None:
outFile = options.outFile
elif overwrite:
outFile = inFile
else:
outFile = inFile + '.' + outFileExt

backupFile = inFile + '.' + backupExt

#--------------------------------------------------------------------------------------------------
# Objects

class Signal:

def __init__(self, name, type):
self.name = name;
self.type = type;

class Table:

def __init__(self, name):
self.name = name
self.source = []
self.signals = {}
self.signalsByCol = {}
self.typesByCol = {}
self.specs = [] # list of specsByCol
self.equations = []
self.added = False

def validate(self):
# check that all signals have a good type
for col in self.signalsByCol:
if col not in self.typesByCol:
error('Table ' + self.name + ': no signal type for ' + self.signalsByCol[col])
elif self.typesByCol[col] == None:
error('Table ' + self.name + ': bad signal type (' + str(self.typesByCol[col]) + ') for ' + str(self.signalsByCol[col]))

def makeRTL(self, form=None):
outputsByCol = {}


#for col,type in self.typesByCol.items():
for col in sorted(self.typesByCol):
type = self.typesByCol[col]
if type == TYPE_OUTPUT:
if col in self.signalsByCol:
outputsByCol[col] = self.signalsByCol[col]
else:
print(self.signalsByCol)
print(self.typesByCol)
error('Table ' + self.name + ': output is specified in col ' + str(col) + ' but no signal exists')

#for sigCol,sig in outputsByCol.items():
for sigCol in sorted(outputsByCol):
sig = outputsByCol[sigCol]
if not verilog:
line = sig + ' <= '
else:
line = 'assign ' + sig + ' = '
nonzero = False
for specsByCol in self.specs:
terms = []
if sigCol not in specsByCol:
#error('* Output ' + sig + ' has no specified value for column ' + str(col))
1 # no error, can be dontcare
elif specsByCol[sigCol] == '1':
for col,val in specsByCol.items():
if col not in self.typesByCol:
if noisy:
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ') - no associated signal', False) #wtf UNTIL CAN HANDLE COMMENTS AT END!!!!!!!!!!!!!!!!!!!
elif self.typesByCol[col] == TYPE_INPUT:
if val == '0':
terms.append(opNot + self.signalsByCol[col])
if nonzero and len(terms) == 1:
line = line + ') ' + opOr + '\n (';
elif len(terms) == 1:
line = line + '\n ('
nonzero = True
elif val == '1':
terms.append(self.signalsByCol[col])
if nonzero and len(terms) == 1:
line = line + ') ' + opOr + '\n (';
elif len(terms) == 1:
line = line + '\n ('
nonzero = True
else:
error('Table ' + self.name +': unexpected value in spec column ' + str(col) + ' (' + str(val) + ')')
if len(terms) > 0:
line = line + (' ' + opAnd + ' ').join(terms)
if not nonzero:
line = line + zero + ";";
else:
line = line + ');'
self.equations.append(line)

return self.equations

def printv(self):
self.makeRTL()
print('\n'.join(self.equations))

def printinfo(self):
print('Table: ' + self.name)
print
for l in self.source:
print(l)
print
print('Signals by column:')
for col in sorted(self.signalsByCol):
print('{0:>3}. {1:} ({2:}) '.format(col, self.signalsByCol[col], 'in' if self.typesByCol[col] == TYPE_INPUT else 'out'))


#--------------------------------------------------------------------------------------------------
# Functions

def error(msg, quitOverride=None):
print('*** ' + msg)
if quitOverride == False:
1
elif (quitOverride == None) or failOnError:
quit(-10)
elif quitOverride:
quit(-10)

#--------------------------------------------------------------------------------------------------
# Do something

if not verilog:
openBracket = '('
closeBracket = ')'
opAnd = 'and'
opOr = 'or'
opNot = 'not '
zero = "'0'"
tablePattern = re.compile(r'^\s*?--tbl(?:\s+([^\s]+).*$|\s*$)')
tableGenPattern = re.compile(r'^\s*?--vtable(?:\s+([^\s]+).*$)')
commentPattern = re.compile(r'^\s*?(--.*$|\s*$)')
tableLinePattern = re.compile(r'^.*?--(.*)')
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')
else:
openBracket = '['
closeBracket = ']'
opAnd = '&'
opOr = '|'
opNot = '~'
zero = "'b0"
tablePattern = re.compile(r'^\s*?\/\/tbl(?:\s+([^\s]+).*$|\s*$)')
tableGenPattern = re.compile(r'^\s*?\/\/vtable(?:\s+([^\s]+).*$)')
commentPattern = re.compile(r'^\s*?(\/\/.*$|\s*$)')
tableLinePattern = re.compile(r'^.*?\/\/(.*)')
namePattern = re.compile(r'([a-zA-z\d_\(\)\.\[\]]+)')

# find the lines with table spec
try:
inf = open(inFile)
for i, line in enumerate(inf):
lines.append(line.strip('\n'))
for match in re.finditer(tablePattern, line):
tableMatches.append(i)
inf.close()
except Exception as e:
error('Error opening input file ' + inFile + '\n' + str(e), True)

# validate matches; should be paired, nothing but comments and empties; table may be named
# between them

for i in range(0, len(tableMatches), 2):

if i + 1 > len(tableMatches) - 1:
error('Mismatched table tags.\nFound so far: ' + ', '.join(tableNames), True)

tLines = lines[tableMatches[i]:tableMatches[i+1]+1]
tableLines.append(tLines)
tName = re.match(tablePattern, lines[tableMatches[i]]).groups()[0]
if tName is None:
tName = 'noname_' + str(tableMatches[i] + 1)
tableNames.append(tName)

for line in tLines:
if not re.match(commentPattern, line):
error('Found noncomment, nonempty line in table ' + tName + ':\n' + line, True)

print('Found tables: ' + ', '.join(tableNames))

# build table objects

for table, tName in zip(tableLines, tableNames):
print('Parsing ' + tName + '...')
namesByCol = {}
colsByName = {}
bitsByCol = {}
typesByCol = {}
specs = []

# parse the table - do by Table.parse()
tLines = table[1:-1] # exclude --tbl
for line in tLines:
if line.strip() == '':
continue
try:
spec = re.search(tableLinePattern, line).groups()[0]
except Exception as e:
error('Problem parsing table line:\n' + line, True)
if len(spec) > 0:
if spec[0] == 'n':
for match in re.finditer(namePattern, spec[1:]):
# col 0 is first col after n
namesByCol[match.start()] = match.groups()[0]
colsByName[match.groups()[0]] = match.start()
elif spec[0] == 'b':
for i, c in enumerate(spec[1:]):
if c == ' ' or c == '|':
continue
try:
bit = int(c)
except:
error('Unexpected char in bit line at position ' + str(i) + ' (' + c + ')\n' + line)
bit = None
if i in bitsByCol and bitsByCol[i] is not None:
bitsByCol[i] = bitsByCol[i]*10+bit
else:
bitsByCol[i] = bit
elif spec[0] == 't':
for i, c in enumerate(spec[1:]):
if c.lower() == 'i':
typesByCol[i] = TYPE_INPUT
elif c.lower() == 'o':
typesByCol[i] = TYPE_OUTPUT
elif c.lower() == '*':
typesByCol[i] = TYPE_SKIP
elif c != ' ':
error('Unexpected char in type line at position ' + str(i) + ' (' + c + ')\n' + line)
typesByCol[i] = None
else:
typesByCol[i] = None
elif spec[0] == 's':
specsByCol = {}
for i, c in enumerate(spec[1:]):
if c == '0' or c == '1':
specsByCol[i] = c
specs.append(specsByCol)
else:
#print('other:')
#print(line)
1

# create table object

# add strand to name where defined; don't combine for now into vector
# consecutive strands belong to the last defined name
lastName = None
lastCol = 0
signalsByCol = {}

for col,name in namesByCol.items(): # load with unstranded names
signalsByCol[col] = name

# sort by col so consecutive columns can be easily tracked
#for col,val in bitsByCol.items(): # update with stranded names
for col in sorted(bitsByCol):
val = bitsByCol[col]

if col > lastCol + 1:
lastName = None
if val is None:
lastName = None
if col in namesByCol:
if val is None:
signalsByCol[col] = namesByCol[col]
else:
lastName = namesByCol[col]
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
elif lastName is not None:
signalsByCol[col] = lastName + openBracket + str(val) + closeBracket
else:
error('Can\'t associate bit number ' + str(val) + ' in column ' + str(col) + ' with a signal name.')
lastCol = col

t = Table(tName)
t.source = table
t.signalsByCol = signalsByCol
t.typesByCol = typesByCol
t.specs = specs

tables[tName] = t

for name in tables:
t = tables[name]
t.validate()
t.makeRTL()

print()
print('Results:')

# find the lines with generate spec and replace them with new version
outLines = []
inTable = False
for i, line in enumerate(lines):
if not inTable:
match = re.search(tableGenPattern, line)
if match is not None:
tName = match.groups(1)[0]
if tName not in tables:
if tName == 1:
tName = '<blank>'
error('Found vtable start for \'' + tName + '\' but didn\'t generate that table: line ' + str(i+1) + '\n' + line, True)
else:
outLines.append(line)
outLines += tables[tName].equations
tables[tName].added = True
inTable = True
else:
outLines.append(line)
else:
match = re.search(tableGenPattern, line)
if match is not None:
if match.groups(1)[0] != tName:
error('Found vtable end for \'' + match.groups(1)[0] + '\' but started table \'' + tName + '\': line ' + str(i+1) + '\n' + line, True)
outLines.append(line)
inTable = False
else:
1#print('stripped: ' + line)

if backup:
try:
copyfile(inFile, backupFile)
except Exception as e:
error('Error creating backup file!\n' + str(e), True)

try:
of = open(outFile, 'w')
for line in outLines:
of.write("%s\n" % line)
except Exception as e:
error('Error writing output file ' + outFile + '!\n' + str(e), True)

print('Generated ' + str(len(tables)) + ' tables: ' + ', '.join(tableNames))
notAdded = {}
for table in tables:
if not tables[table].added:
notAdded[table] = True
print('Output file: ' + outFile)
if backup:
print('Backup file: ' + backupFile)
if len(notAdded) != 0:
error('Tables generated but not added to file! ' + ', '.join(notAdded))

@ -34,7 +34,8 @@


module a2owb ( module a2owb (


input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input scan_in, input scan_in,
output scan_out, output scan_out,


@ -251,7 +252,8 @@ assign an_ac_lbist_ary_wrt_thru_dc = 0;




c c0( c c0(
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(scan_in), .scan_in(scan_in),
.scan_out(scan_out), .scan_out(scan_out),


@ -505,11 +507,4 @@ a2l2wb n0(


); );


wire clk_1x, clk_2x, clk_4x, rst;

assign clk_1x = nclk[0];
assign clk_2x = nclk[2];
assign clk_4x = nclk[3];
assign rst = nclk[1];

endmodule endmodule

@ -60,8 +60,7 @@


module a2owb ( module a2owb (


input clk_1x, input clk,
input clk_2x,
input rst, input rst,


input [0:31] cfg_dat, input [0:31] cfg_dat,
@ -83,7 +82,6 @@ module a2owb (
input [31:0] wb_datr input [31:0] wb_datr
); );


wire [0:`NCLK_WIDTH-1] nclk;
wire [0:`THREADS-1] an_ac_stcx_complete /*verilator public */; wire [0:`THREADS-1] an_ac_stcx_complete /*verilator public */;
wire [0:`THREADS-1] an_ac_stcx_pass; wire [0:`THREADS-1] an_ac_stcx_pass;
wire an_ac_icbi_ack; wire an_ac_icbi_ack;
@ -206,8 +204,6 @@ wire an_ac_hang_pulse;
//wire ac_an_reset_3_request; //wire ac_an_reset_3_request;
//wire ac_an_reset_wd_request; //wire ac_an_reset_wd_request;


assign nclk = {clk_1x, rst, clk_2x, 3'b00};

assign mem_dat = 0; assign mem_dat = 0;


assign an_ac_chipid_dc = 4'h0; assign an_ac_chipid_dc = 4'h0;
@ -251,7 +247,8 @@ assign an_ac_uncond_dbg_event = 0;




c c0( c c0(
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(scan_in), .scan_in(scan_in),
.scan_out(), .scan_out(),


@ -379,7 +376,7 @@ c c0(
); );


a2l2wb n0( a2l2wb n0(
.clk(clk_1x), .clk(clk),
.rst(rst), .rst(rst),


.cfg_wr(cfg_wr), .cfg_wr(cfg_wr),

@ -49,6 +49,9 @@
`define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array `define EXPAND_TLB_TYPE 2 // 0 = erat-only, 1 = tlb logic, 2 = tlb array
//`define EXPAND_TLB_TYPE 0 // doesn't work in sim //`define EXPAND_TLB_TYPE 0 // doesn't work in sim


// 0: none 1: DP
//`define FLOAT_TYPE 0 // fails with completion x's in sim
`define FLOAT_TYPE 1


/*wtf these are a mess; need to be doc'd and create dependency reqts and legal ranges; /*wtf these are a mess; need to be doc'd and create dependency reqts and legal ranges;
shrinking values causes lots of bit sel vector problems, and sim fails shrinking values causes lots of bit sel vector problems, and sim fails

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -1,10 +1,8 @@
# RTL # RTL



## fpga/sim arrays ## fpga/sim arrays


* created sim-only (not fpga?) clk1x versions in trilib_clk1x to eliminate any possible problems with iverilog * arrays that had 2x/4x clks
and verilator dealing with multiple clocks


``` ```
trilib/tri_144x78_2r4w.v trilib/tri_144x78_2r4w.v
@ -19,6 +17,18 @@ trilib/tri_512x16_1r1w_1.v
trilib/tri_128x16_1r1w_1.v trilib/tri_128x16_1r1w_1.v
``` ```


* also got rid of reset_q usages (clk and reset in same nclk vector)
***i doubt reset is needed in any of the array components***

```
trilib/tri_128x16_1r1w_1.v: reg reset_q;
trilib/tri_512x16_1r1w_1.v: reg reset_q;
trilib/tri_64x72_1r1w.v: reg reset_q;
trilib/tri_cam_16x143_1r1w1c.v: reg sreset_q;
trilib/tri_cam_32x143_1r1w1c.v: reg sreset_q;
trilib/tri_iuq_cpl_arr.v: reg reset_q;
```

### arrays using clk4x ### arrays using clk4x


* 4W was done with clk4x * 4W was done with clk4x
@ -27,7 +37,6 @@ trilib/tri_128x16_1r1w_1.v
``` ```
grep "nclk\[3\]" trilib/* grep "nclk\[3\]" trilib/*
trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x
trilib/tri_144x78_2r4w.v: .WCLK(nclk[3]), // Port A write clock input : clk4x
``` ```


### arrays using clk2x ### arrays using clk2x

@ -1,4 +1,4 @@
// © IBM Corp. 2022 // © IBM Corp. 2020
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -33,6 +33,10 @@


// Use this line for 1 thread. Comment out for 2 thread design. // Use this line for 1 thread. Comment out for 2 thread design.
//`define THREADS1 //`define THREADS1
`define RESET_VECTOR 32'h00000000

// 0: none 1: DP
`define FLOAT_TYPE 1


`define gpr_t 3'b000 `define gpr_t 3'b000
`define cr_t 3'b001 `define cr_t 3'b001
@ -111,7 +115,7 @@
`define IBUFF_INSTR_WIDTH 70 `define IBUFF_INSTR_WIDTH 70
`define IBUFF_IFAR_WIDTH 20 `define IBUFF_IFAR_WIDTH 20
`define IBUFF_DEPTH 16 `define IBUFF_DEPTH 16
`define PF_IAR_BITS 12 // number of IAR bits used by prefetch `define PF_IAR_BITS 12 // number of IAR bits used by prefetch
`define FXU0_PIPE_START 1 `define FXU0_PIPE_START 1
`define FXU0_PIPE_END 8 `define FXU0_PIPE_END 8
`define FXU1_PIPE_START 1 `define FXU1_PIPE_START 1
@ -121,7 +125,7 @@
`define LQ_REL_PIPE_START 2 `define LQ_REL_PIPE_START 2
`define LQ_REL_PIPE_END 4 `define LQ_REL_PIPE_END 4
`define LOAD_CREDITS 8 `define LOAD_CREDITS 8
`define STORE_CREDITS 4 `define STORE_CREDITS 4 //wtf 32 is normal; fpga bug needed 4
`define IUQ_ENTRIES 4 // Instruction Fetch Queue Size `define IUQ_ENTRIES 4 // Instruction Fetch Queue Size
`define MMQ_ENTRIES 2 // MMU Queue Size `define MMQ_ENTRIES 2 // MMU Queue Size
`define CR_WIDTH 4 `define CR_WIDTH 4
@ -133,16 +137,32 @@
`define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings) `define INCLUDE_IERAT_BYPASS 1 // 0 => Removes IERAT Bypass logic, 1=> includes (power savings)
`define XER_WIDTH 10 `define XER_WIDTH 10


`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT //wtf: change for verilatorsim - didnt help
`define INIT_IUCR0 16'h00FA // BP enabled //`define INIT_BHT 1 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT
`define INIT_BHT 0 // 0=> array init time set to 16 clocks, 1=> increased to 512 to init BHT

//`define INIT_IUCR0 16'h0000 // BP disabled
`define INIT_IUCR0 16'h00FA // BP enabled
`define INIT_XUCR0 32'h00000460 // normal

`define INIT_MASK 2'b10 `define INIT_MASK 2'b10
`define RELQ_INCLUDE 0 // Reload Queue Included `define RELQ_INCLUDE 0 // Reload Queue Included


`define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1 `define G_BRANCH_LEN `EFF_IFAR_WIDTH + 1 + 1 + `EFF_IFAR_WIDTH + 3 + 18 + 1


//wtf: add completion stuff
/*
assign spr_cpcr0_fx0_cnt = cpcr0_l2[35:39];
assign spr_cpcr0_fx1_cnt = cpcr0_l2[43:47];
assign spr_cpcr0_lq_cnt = cpcr0_l2[51:55];
assign spr_cpcr0_sq_cnt = cpcr0_l2[59:63];
*/
`define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132 `define INIT_CPCR0 32'h0C0C100C // 000a aaaa 000b bbbb 000c cccc 000d dddd watermarks: a=fx0 b=fx1 c=ls d=sq ---- um p.543 wrong!; was this in vlog: hex 0C0C100C = 202117132
//`define INIT_CPCR0 32'h01010201 // 1/1/2/1 //`define INIT_CPCR0 32'h01010201 // 1/1/2/1

/*
assign spr_cpcr1_fu0_cnt = cpcr1_l2[43:47];
assign spr_cpcr1_fu1_cnt = cpcr1_l2[51:55];
*/
`define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504 `define INIT_CPCR1 32'h000C0C00 // 0000 0000 000a aaaa 000b bbbb 0000 0000 credits: a=fx0 b=fx1 c=ls d=sq ---- um p.544 wrong!; was this in vlog: hex 000C0C00 = 789504
//`define INIT_CPCR1 32'h00010100 // 1/1 //`define INIT_CPCR1 32'h00010100 // 1/1


@ -36,11 +36,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_128x168_1w_0( module tri_128x168_1w_0 (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
act, act,
ccflush_dc, ccflush_dc,
scan_dis_dc_b, scan_dis_dc_b,
@ -102,7 +103,8 @@ module tri_128x168_1w_0(
inout vcs; inout vcs;


// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; input act;
input ccflush_dc; input ccflush_dc;
input scan_dis_dc_b; input scan_dis_dc_b;
@ -227,7 +229,7 @@ module tri_128x168_1w_0(
.DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]), .DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ADDRA(ramb_addr), .ADDRA(ramb_addr),
.ADDRB(ramb_addr), .ADDRB(ramb_addr),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(tidn), .CLKB(tidn),
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
@ -235,7 +237,7 @@ module tri_128x168_1w_0(
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(act), .ENA(act),
.ENB(tidn), .ENB(tidn),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(tidn), .SSRB(tidn),
.WEA(write[w]), .WEA(write[w]),
.WEB(tidn) .WEB(tidn)
@ -252,5 +254,5 @@ module tri_128x168_1w_0(
assign bo_pc_failout = 1'b0; assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0; assign bo_pc_diagloop = 1'b0;


assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob}); assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, unused_dob});
endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -33,13 +33,16 @@
// //
//***************************************************************************** //*****************************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_128x16_1r1w_1( module tri_128x16_1r1w_1 (
vdd, vdd,
vcs, vcs,
gnd, gnd,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
lcb_d_mode_dc, lcb_d_mode_dc,
@ -106,7 +109,8 @@ module tri_128x16_1r1w_1(
inout vcs; inout vcs;
inout gnd; inout gnd;


input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;


input rd_act; input rd_act;
input wr_act; input wr_act;
@ -179,67 +183,38 @@ module tri_128x16_1r1w_1(
//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36; //for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;


wire clk; wire clk;
wire clk2x;
wire [0:8] b0addra; wire [0:8] b0addra;
wire [0:8] b0addrb; wire [0:8] b0addrb;
wire wea; wire wea;
wire web; wire web;
wire wren_a; wire wren_a;
// Latches wire [0:15] w_data_in_0;
reg reset_q; wire [0:15] r_data_out_0_bram;
reg gate_fq;
wire gate_d;
wire [0:35] r_data_out_1_d;
reg [0:35] r_data_out_1_fq;
wire [0:35] w_data_in_0;


wire [0:35] r_data_out_0_bram; // Latches
wire [0:35] r_data_out_1_bram; reg [0:15] r_data_out_1_q;


wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;


(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


assign clk = nclk[0]; // sim array
assign clk2x = nclk[2]; reg [0:15] mem[0:127];



always @(posedge clk) integer i;
begin: rlatch initial begin
reset_q <= nclk[1]; for (i = 0; i < 128; i = i + 1)
end mem[i] = 0;

end
//
// NEW clk2x gate logic start
//

always @(posedge nclk[0])
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end



//wtf:icarus $dumpvars cannot dump a vpiMemory
always @(posedge nclk[2]) generate
begin: flatch genvar j;
toggle2x_q <= toggle2x_d; for (j = 0; j < 128; j=j+1) begin: loc
gate_fq <= gate_d; wire [0:15] dat;
r_data_out_1_fq <= r_data_out_1_d; assign dat = mem[j][0:15];
end end

endgenerate
assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;

// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));


assign b0addra[2:8] = wr_adr; assign b0addra[2:8] = wr_adr;
assign b0addrb[2:8] = rd_adr; assign b0addrb[2:8] = rd_adr;
@ -249,72 +224,37 @@ module tri_128x16_1r1w_1(
assign b0addrb[0:1] = 2'b00; assign b0addrb[0:1] = 2'b00;


// port a is a read-modify-write port // port a is a read-modify-write port
assign wren_a = ((bw != 16'b0000000000000000 & wr_act == 1'b1)) ? 1'b1 : assign wren_a = (bw != 0) & wr_act;
1'b0; assign wea = wren_a;
assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk
assign web = 1'b0; assign web = 1'b0;
assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
r_data_out_0_bram[0]; assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
r_data_out_0_bram[1]; assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
r_data_out_0_bram[2]; assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
r_data_out_0_bram[3]; assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
r_data_out_0_bram[4]; assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
r_data_out_0_bram[5]; assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
r_data_out_0_bram[6]; assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
r_data_out_0_bram[7]; assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
r_data_out_0_bram[8]; always @(posedge clk) begin
assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
r_data_out_0_bram[9]; r_data_out_1_q <= mem[b0addrb];
assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : if (wea) begin
r_data_out_0_bram[10]; mem[b0addra] <= w_data_in_0;
assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : end
r_data_out_0_bram[11];
assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] : end
r_data_out_0_bram[12];
assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] : assign r_data_out_0_bram = mem[b0addra];
r_data_out_0_bram[13]; assign dout = r_data_out_1_q[0:15];
assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
r_data_out_0_bram[14];
assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
r_data_out_0_bram[15];
assign w_data_in_0[16:35] = {20{1'b0}};

assign r_data_out_1_d = r_data_out_1_bram;



RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(reset_q),
.SSRB(reset_q),
.ADDRA(b0addra),
.ADDRB(b0addrb),
.DIA(w_data_in_0[0:31]),
.DIB({32{1'b0}}),
.DOA(r_data_out_0_bram[0:31]),
.DOB(r_data_out_1_bram[0:31]),
.DOPA(r_data_out_0_bram[32:35]),
.DOPB(r_data_out_1_bram[32:35]),
.DIPA(w_data_in_0[32:35]),
.DIPB(4'b0000),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);

assign dout = r_data_out_1_fq[0:15];


assign func_scan_out = func_scan_in; assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in; assign time_scan_out = time_scan_in;
@ -324,12 +264,12 @@ module tri_128x16_1r1w_1(
assign bo_pc_failout = 1'b0; assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0; assign bo_pc_diagloop = 1'b0;


assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, assign unused = |{vdd, vcs, gnd, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_bram[16:35], r_data_out_1_fq[16:35]}; tri_lcb_act_dis_dc, rd_act};
endmodule endmodule

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -37,11 +37,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_128x34_4w_1r1w( module tri_128x34_4w_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
sg_0, sg_0,
@ -110,7 +111,8 @@ module tri_128x34_4w_1r1w(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
inout vcs; inout vcs;
// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input rd_act; input rd_act;
input wr_act; input wr_act;
input sg_0; input sg_0;
@ -254,16 +256,16 @@ module tri_128x34_4w_1r1w(
.DOPB(dopb), .DOPB(dopb),
.ADDRA(ramb_rd_addr), .ADDRA(ramb_rd_addr),
.ADDRB(ramb_wr_addr), .ADDRB(ramb_wr_addr),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), .DIA(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[w][x * ramb_base_width:x * ramb_base_width + 31]),
.DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), .DIPA(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]), .DIPB(ramb_data_in[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(rd_act), .ENA(rd_act),
.ENB(wr_act), .ENB(wr_act),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(tidn), .WEA(tidn),
.WEB(wr_way[w]) .WEB(wr_way[w])
); );
@ -278,7 +280,8 @@ module tri_128x34_4w_1r1w(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(1'b1), .act(1'b1),
.thold_b(func_sl_thold_0_b), .thold_b(func_sl_thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -296,7 +299,8 @@ module tri_128x34_4w_1r1w(
tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_l2), .act(rd_act_l2),
.thold_b(func_sl_thold_0_b), .thold_b(func_sl_thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -319,6 +323,6 @@ module tri_128x34_4w_1r1w(
assign bo_pc_failout = {tidn, tidn}; assign bo_pc_failout = {tidn, tidn};
assign bo_pc_diagloop = {tidn, tidn}; assign bo_pc_diagloop = {tidn, tidn};


assign unused = | ({nclk[2:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]}); assign unused = | ({sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, dob, dopb, func_sov, ramb_data_out[0][34:35], ramb_data_out[1][34:35], ramb_data_out[2][34:35], ramb_data_out[3][34:35]});


endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -26,22 +26,25 @@
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ps / 1 ps `timescale 1 ns / 1 ns


//***************************************************************************** //*****************************************************************************
// Description: Tri-Lam Array Wrapper // Description: Tri-Lam Array Wrapper
// //
//***************************************************************************** //*****************************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_144x78_2r4w( module tri_144x78_2r4w (
// Inputs // Inputs
// Power // Power
inout vdd, inout vdd,
inout gnd, inout gnd,
// Clock & Scan // Clock & Scan
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,


//------------------------------------------------------------------- //-------------------------------------------------------------------
// Pervasive // Pervasive
@ -84,554 +87,72 @@ module tri_144x78_2r4w(
input [64-`GPR_WIDTH:77] w_data_in_4 input [64-`GPR_WIDTH:77] w_data_in_4
); );


// Configuration Statement for NCsim wire unused;
//for all:RAM64X1D use entity unisim.RAM64X1D;

parameter tiup = 1'b1;
parameter tidn = 1'b0;


//------------------------------------------------------------------- // sim array
// Signals reg [64-`GPR_WIDTH:77] mem[0:143];
//-------------------------------------------------------------------
//reg write_en;
//reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
//reg [64-`GPR_WIDTH:77] write_data;
wire write_en;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] write_addr;
wire [64-`GPR_WIDTH:77] write_data;


wire [0:(`GPR_POOL*`THREADS-1)/64] write_en_arr; reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
wire [0:5] write_addr_arr; wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d;
wire [0:1] wr_mux_ctrl; reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;

wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d;
//-------------------------------------------------------------------
// Latch Signals
//-------------------------------------------------------------------
wire w1e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w1a_q;
wire [64-`GPR_WIDTH:77] w1d_q;
wire w2e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w2a_q;
wire [64-`GPR_WIDTH:77] w2d_q;
wire w3e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w3a_q;
wire [64-`GPR_WIDTH:77] w3d_q;
wire w4e_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w4a_q;
wire [64-`GPR_WIDTH:77] w4d_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
wire [0:5] read1_addr_arr;
wire [0:5] read2_addr_arr;
wire [0:(`GPR_POOL*`THREADS-1)/64] read1_en_arr;
wire [0:(`GPR_POOL*`THREADS-1)/64] read2_en_arr;
reg [64-`GPR_WIDTH:77] read1_data;
reg [64-`GPR_WIDTH:77] read2_data;
wire [64-`GPR_WIDTH:77] r1d_array[0:(`GPR_POOL*`THREADS-1)/64];
wire [64-`GPR_WIDTH:77] r2d_array[0:(`GPR_POOL*`THREADS-1)/64];
wire [64-`GPR_WIDTH:77] r1d_d;
wire [64-`GPR_WIDTH:77] r2d_d;
wire [64-`GPR_WIDTH:77] r1d_q;
wire [64-`GPR_WIDTH:77] r2d_q;


(* analysis_not_referenced="true" *) reg [64-`GPR_WIDTH:77] r1d_q;
wire unused; wire [64-`GPR_WIDTH:77] r1d_d;
wire [64-`GPR_WIDTH:77] unused_port; reg [64-`GPR_WIDTH:77] r2d_q;
wire [64-`GPR_WIDTH:77] unused_port2; wire [64-`GPR_WIDTH:77] r2d_d;


//------------------------------------------------------------------- integer i;
// Scanchain initial begin
//------------------------------------------------------------------- for (i = 0; i < 144; i = i + 1)
parameter w1e_offset = 0; mem[i] = 0;
parameter w1a_offset = w1e_offset + 1; end
parameter w1d_offset = w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w2e_offset = w1d_offset + (`GPR_WIDTH+14);
parameter w2a_offset = w2e_offset + 1;
parameter w2d_offset = w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w3e_offset = w2d_offset + (`GPR_WIDTH+14);
parameter w3a_offset = w3e_offset + 1;
parameter w3d_offset = w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter w4e_offset = w3d_offset + (`GPR_WIDTH+14);
parameter w4a_offset = w4e_offset + 1;
parameter w4d_offset = w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r1a_offset = w4d_offset + (`GPR_WIDTH+14);
parameter r2a_offset = r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r1d_offset = r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC;
parameter r2d_offset = r1d_offset + (`GPR_WIDTH+14);
parameter scan_right = r2d_offset + (`GPR_WIDTH+14);
wire [0:scan_right-1] siv;
wire [0:scan_right-1] sov;


//wtf:icarus $dumpvars cannot dump a vpiMemory
generate generate
begin genvar j;

for (j = 0; j < 144; j=j+1) begin: loc
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX wire [64-`GPR_WIDTH:63] dat;
// Read Control wire [0:7] par;
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX // 4b0
// BYPASS assign dat = mem[j][64-`GPR_WIDTH:63];

assign par = mem[j][64:63 + `GPR_WIDTH/8];
assign r1d_d = read1_data;

assign r2d_d = read2_data;

assign r_data_out_1 = r1d_q;
assign r_data_out_2 = r2d_q;

// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Write Control
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
assign wr_mux_ctrl = {nclk[0], nclk[2]};

//wtf moved these here to try to get them to work in icarus - they seem to now
assign write_en = ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
(wr_mux_ctrl == 2'b01) ? w_late_en_2 :
(wr_mux_ctrl == 2'b10) ? w_late_en_3 :
w_late_en_4);

assign write_addr = ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
(wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
(wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
w_addr_in_4);

assign write_data = ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
(wr_mux_ctrl == 2'b01) ? w_data_in_2 :
(wr_mux_ctrl == 2'b10) ? w_data_in_3 :
w_data_in_4);


//always @ ( * )
//begin
//write_addr = #10 ((wr_mux_ctrl == 2'b00) ? w_addr_in_1 :
// (wr_mux_ctrl == 2'b01) ? w_addr_in_2 :
// (wr_mux_ctrl == 2'b10) ? w_addr_in_3 :
// w_addr_in_4);

//write_en = #10 ((wr_mux_ctrl == 2'b00) ? w_late_en_1 :
// (wr_mux_ctrl == 2'b01) ? w_late_en_2 :
// (wr_mux_ctrl == 2'b10) ? w_late_en_3 :
// w_late_en_4);

// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX
// Depth Control
// XXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXXX

//write_data = #10 ((wr_mux_ctrl == 2'b00) ? w_data_in_1 :
// (wr_mux_ctrl == 2'b01) ? w_data_in_2 :
// (wr_mux_ctrl == 2'b10) ? w_data_in_3 :
// w_data_in_4);
//end

if (((`GPR_POOL*`THREADS - 1)/64) == 0)
begin : depth1
if (`GPR_POOL_ENC+`THREADS_POOL_ENC < 6)
begin
assign write_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
assign read1_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
assign read2_addr_arr[0:(6 - `GPR_POOL_ENC+`THREADS_POOL_ENC) - 1] = {6-`GPR_POOL_ENC+`THREADS_POOL_ENC{1'b0}};
end

assign write_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = write_addr;
assign read1_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r1a_q;
assign read2_addr_arr[6 - `GPR_POOL_ENC+`THREADS_POOL_ENC:5] = r2a_q;
assign write_en_arr[0] = write_en;
assign read1_en_arr[0] = 1'b1;
assign read2_en_arr[0] = 1'b1;
end

if (((`GPR_POOL*`THREADS - 1)/64) != 0)
begin : depthMulti
assign write_addr_arr = write_addr[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
assign read1_addr_arr = r1a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];
assign read2_addr_arr = r2a_q[`GPR_POOL_ENC+`THREADS_POOL_ENC - 6:`GPR_POOL_ENC+`THREADS_POOL_ENC - 1];

genvar wen;
for (wen = 0; wen <= ((`GPR_POOL*`THREADS - 1)/64); wen = wen + 1)
begin : wrenGen
wire wen_match = wen;
assign write_en_arr[wen] = write_en & (write_addr[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match);
assign read1_en_arr[wen] = r1a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
assign read2_en_arr[wen] = r2a_q[0:(`GPR_POOL_ENC+`THREADS_POOL_ENC - 6) - 1] == wen_match;
end
end

always @( * )
begin: rdDataMux
reg [64-`GPR_WIDTH:77] rd1_data;
reg [64-`GPR_WIDTH:77] rd2_data;
//(* analysis_not_referenced="true" *)
integer rdArr;
rd1_data = {`GPR_WIDTH+14{1'b0}};
rd2_data = {`GPR_WIDTH+14{1'b0}};

for (rdArr = 0; rdArr <= ((`GPR_POOL*`THREADS - 1)/64); rdArr = rdArr + 1)
begin
rd1_data = (r1d_array[rdArr] & {`GPR_WIDTH+14{read1_en_arr[rdArr]}}) | rd1_data;
rd2_data = (r2d_array[rdArr] & {`GPR_WIDTH+14{read2_en_arr[rdArr]}}) | rd2_data;
end
read1_data = rd1_data;
read2_data = rd2_data;
end

genvar depth;
for (depth = 0; depth <= ((`GPR_POOL*`THREADS - 1)/64); depth = depth + 1)
begin : depth_loop
genvar i;
for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
begin : r1
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_1(
.SPO(unused_port[i]),
.DPO(r1d_array[depth][i]), // Port A 1-bit data output

.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
.A1(write_addr_arr[4]),
.A2(write_addr_arr[3]),
.A3(write_addr_arr[2]),
.A4(write_addr_arr[1]),
.A5(write_addr_arr[0]),

//.A(write_addr_arr),
.D(write_data[i]), // Port A 1-bit data input

.DPRA0(read1_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
.DPRA1(read1_addr_arr[4]),
.DPRA2(read1_addr_arr[3]),
.DPRA3(read1_addr_arr[2]),
.DPRA4(read1_addr_arr[1]),
.DPRA5(read1_addr_arr[0]),

//.DPRA(read1_addr_arr),
.WCLK(nclk[3]), // Port A write clock input : clk4x
.WE(write_en_arr[depth]) // Port A write enable input
);
end end

//genvar i;
for (i = 64 - `GPR_WIDTH; i < 78; i = i + 1)
begin : r2
RAM64X1D #(.INIT(64'h0000000000000000)) RAM64X1D_2(
.SPO(unused_port2[i]),
.DPO(r2d_array[depth][i]), // Port A 1-bit data output

.A0(write_addr_arr[5]), // Port A - Write Address (A0-A5)
.A1(write_addr_arr[4]),
.A2(write_addr_arr[3]),
.A3(write_addr_arr[2]),
.A4(write_addr_arr[1]),
.A5(write_addr_arr[0]),

//.A(write_addr_arr),
.D(write_data[i]), // Port A 1-bit data input

.DPRA0(read2_addr_arr[5]), // Port B - Read Address (DPRA0-DPRA5)
.DPRA1(read2_addr_arr[4]),
.DPRA2(read2_addr_arr[3]),
.DPRA3(read2_addr_arr[2]),
.DPRA4(read2_addr_arr[1]),
.DPRA5(read2_addr_arr[0]),

//.DPRA(read2_addr_arr),
.WCLK(nclk[3]), // Port A write clock input : clk4x
.WE(write_en_arr[depth]) // Port A write enable input
);
end
end
end
endgenerate endgenerate


//---------------------------------------------------------------------------------------------------------------------------------------- assign r1a_d = r_addr_in_1;
// Latches assign r2a_d = r_addr_in_2;
//----------------------------------------------------------------------------------------------------------------------------------------

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w1e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1e_offset]),
.scout(sov[w1e_offset]),
.din(w_late_en_1),
.dout(w1e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w1a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w1a_offset:w1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_1),
.dout(w1a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w1d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w1d_offset:w1d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_1[64 - `GPR_WIDTH:77]),
.dout(w1d_q)
);

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w2e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2e_offset]),
.scout(sov[w2e_offset]),
.din(w_late_en_2),
.dout(w2e_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w2a_latch( always @(posedge clk) begin
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w2a_offset:w2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_2),
.dout(w2a_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w2d_latch( r1a_q <= r1a_d;
.nclk(nclk), r2a_q <= r2a_d;
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w2d_offset:w2d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_2[64 - `GPR_WIDTH:77]),
.dout(w2d_q)
);


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w3e_latch( r1d_q <= r1d_d;
.nclk(nclk), r2d_q <= r2d_d;
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w3e_offset]),
.scout(sov[w3e_offset]),
.din(w_late_en_3),
.dout(w3e_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w3a_latch( if (w_late_en_1) begin
.nclk(nclk), mem[w_addr_in_1] <= w_data_in_1;
.vd(vdd), end
.gd(gnd), if (w_late_en_2) begin
.act(tiup), mem[w_addr_in_2] <= w_data_in_2;
.force_t(func_sl_force), end
.delay_lclkr(delay_lclkr_dc), if (w_late_en_3) begin
.mpw1_b(mpw1_dc_b), mem[w_addr_in_3] <= w_data_in_3;
.mpw2_b(mpw2_dc_b), end
.thold_b(func_sl_thold_0_b), if (w_late_en_4) begin
.d_mode(1'b0), mem[w_addr_in_4] <= w_data_in_4;
.sg(sg_0), end
.scin(siv[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w3a_offset:w3a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_3),
.dout(w3a_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w3d_latch( end
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w3d_offset:w3d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_3[64 - `GPR_WIDTH:77]),
.dout(w3d_q)
);

tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) w4e_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4e_offset]),
.scout(sov[w4e_offset]),
.din(w_late_en_4),
.dout(w4e_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) w4a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[w4a_offset:w4a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(w_addr_in_4),
.dout(w4a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) w4d_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[w4d_offset:w4d_offset + `GPR_WIDTH+14 - 1]),
.din(w_data_in_4[64 - `GPR_WIDTH:77]),
.dout(w4d_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r1a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[r1a_offset:r1a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(r_addr_in_1),
.dout(r1a_q)
);

tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC+`THREADS_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) r2a_latch(
.nclk(nclk),
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.scout(sov[r2a_offset:r2a_offset + `GPR_POOL_ENC+`THREADS_POOL_ENC - 1]),
.din(r_addr_in_2),
.dout(r2a_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r1d_latch( // r_late_en_x are unused in original also
.nclk(nclk), assign r1d_d = mem[r1a_q];
.vd(vdd), assign r2d_d = mem[r2a_q];
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[r1d_offset:r1d_offset + `GPR_WIDTH+14 - 1]),
.din(r1d_d),
.dout(r1d_q)
);


tri_rlmreg_p #(.WIDTH(`GPR_WIDTH+14), .INIT(0), .NEEDS_SRESET(1)) r2d_latch( assign r_data_out_1 = r1d_q;
.nclk(nclk), assign r_data_out_2 = r2d_q;
.vd(vdd),
.gd(gnd),
.act(tiup),
.force_t(func_sl_force),
.delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b),
.thold_b(func_sl_thold_0_b),
.d_mode(1'b0),
.sg(sg_0),
.scin(siv[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
.scout(sov[r2d_offset:r2d_offset + `GPR_WIDTH+14 - 1]),
.din(r2d_d),
.dout(r2d_q)
);


assign siv[0:scan_right-1] = {sov[1:scan_right-1], scan_in}; assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b};
assign scan_out = sov[0];


assign unused = | {unused_port, unused_port2, func_slp_sl_force, func_slp_sl_thold_0_b};
endmodule endmodule

@ -36,11 +36,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_256x144_8w_1r1w( module tri_256x144_8w_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
sg_0, sg_0,
@ -115,7 +116,8 @@ inout vdd;
inout vcs; inout vcs;


// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input [0:7] rd_act; input [0:7] rd_act;
input [0:7] wr_act; input [0:7] wr_act;
input sg_0; input sg_0;
@ -362,8 +364,8 @@ generate
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), .DIA(p0_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
.DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]), .DIB(p1_arr_data_in[way][(arr * 32) + 0:(arr * 32) + 31]),
.DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]), .DIPA(p0_arr_par_in[way][(arr * 4) + 0:(arr * 4) + 3]),
@ -372,8 +374,8 @@ generate
.ENB(wr_act[way]), .ENB(wr_act[way]),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), //sreset .SSRA(rst),
.SSRB(nclk[1]), //sreset .SSRB(rst),
.WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]), .WEA(p0_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]),
.WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3]) .WEB(p1_wayEn[way][(arr * 4) + 0:(arr * 4) + 3])
); );
@ -392,7 +394,6 @@ assign unused = |({
cascadeoutlatb , cascadeoutlatb ,
cascadeoutrega , cascadeoutrega ,
cascadeoutregb , cascadeoutregb ,
nclk[0:`NCLK_WIDTH-1] ,
gnd , gnd ,
vdd , vdd ,
vcs , vcs ,
@ -445,7 +446,8 @@ assign unused = |({
tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmreg_p #(.WIDTH(ways), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -471,7 +473,8 @@ generate
.mpw1_b(mpw1_dc_b), .mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b), .mpw2_b(mpw2_dc_b),
.force_t(func_sl_force), .force_t(func_sl_force),
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(rd_act_q[way]), .act(rd_act_q[way]),

@ -37,11 +37,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_32x70_2w_1r1w( module tri_32x70_2w_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
sg_0, sg_0,
@ -113,7 +114,8 @@ inout gnd;
inout vdd; inout vdd;
inout vcs; inout vcs;
// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input [0:1] rd_act; input [0:1] rd_act;
input [0:1] wr_act; input [0:1] wr_act;
input sg_0; input sg_0;
@ -333,7 +335,8 @@ assign ary_nsl_thold_0_b = ~ ary_nsl_thold_0;
tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch( tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(write_enable_AB), .act(write_enable_AB),
.force_t(tidn[0]), .force_t(tidn[0]),
.d_mode(tidn[0]), .d_mode(tidn[0]),
@ -351,7 +354,8 @@ tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_latc
tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch( tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(write_enable_CD), .act(write_enable_CD),
.force_t(tidn[0]), .force_t(tidn[0]),
.d_mode(tidn[0]), .d_mode(tidn[0]),
@ -369,7 +373,8 @@ tri_regk #(.WIDTH(addressable_ports), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_latc
tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(tidn[0]), .force_t(tidn[0]),
.d_mode(tidn[0]), .d_mode(tidn[0]),
@ -387,7 +392,8 @@ tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrA_bit0_out_latch(
tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch( tri_regk #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) arrC_bit0_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(tidn[0]), .force_t(tidn[0]),
.d_mode(tidn[0]), .d_mode(tidn[0]),
@ -412,16 +418,16 @@ arr0_A(
.DOPB(ramb_data_p1_outA[32:35]), .DOPB(ramb_data_p1_outA[32:35]),
.ADDRA(ramb_addr_wr_rd0), .ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1), .ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in_l[0:31]), .DIA(ramb_data_in_l[0:31]),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(ramb_data_in_l[32:35]), .DIPA(ramb_data_in_l[32:35]),
.DIPB(tidn[32:35]), .DIPB(tidn[32:35]),
.ENA(act[0]), .ENA(act[0]),
.ENB(act[0]), .ENB(act[0]),
.SSRA(nclk[1]), //sreset .SSRA(rst),
.SSRB(nclk[1]), //sreset .SSRB(rst),
.WEA(write_enable_AB), .WEA(write_enable_AB),
.WEB(tidn[0]) .WEB(tidn[0])
); );
@ -435,16 +441,16 @@ arr1_B(
.DOPB(ramb_data_p1_outB[32:35]), .DOPB(ramb_data_p1_outB[32:35]),
.ADDRA(ramb_addr_wr_rd0), .ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1), .ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in_r[0:31]), .DIA(ramb_data_in_r[0:31]),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(ramb_data_in_r[32:35]), .DIPA(ramb_data_in_r[32:35]),
.DIPB(tidn[32:35]), .DIPB(tidn[32:35]),
.ENA(act[0]), .ENA(act[0]),
.ENB(act[0]), .ENB(act[0]),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_AB), .WEA(write_enable_AB),
.WEB(tidn[0]) .WEB(tidn[0])
); );
@ -458,16 +464,16 @@ arr2_C(
.DOPB(ramb_data_p1_outC[32:35]), .DOPB(ramb_data_p1_outC[32:35]),
.ADDRA(ramb_addr_wr_rd0), .ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1), .ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in_l[0:31]), .DIA(ramb_data_in_l[0:31]),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(ramb_data_in_l[32:35]), .DIPA(ramb_data_in_l[32:35]),
.DIPB(tidn[32:35]), .DIPB(tidn[32:35]),
.ENA(act[1]), .ENA(act[1]),
.ENB(act[1]), .ENB(act[1]),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_CD), .WEA(write_enable_CD),
.WEB(tidn[0]) .WEB(tidn[0])
); );
@ -481,16 +487,16 @@ arr3_D(
.DOPB(ramb_data_p1_outD[32:35]), .DOPB(ramb_data_p1_outD[32:35]),
.ADDRA(ramb_addr_wr_rd0), .ADDRA(ramb_addr_wr_rd0),
.ADDRB(ramb_addr_rd1), .ADDRB(ramb_addr_rd1),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in_r[0:31]), .DIA(ramb_data_in_r[0:31]),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(ramb_data_in_r[32:35]), .DIPA(ramb_data_in_r[32:35]),
.DIPB(tidn[32:35]), .DIPB(tidn[32:35]),
.ENA(act[1]), .ENA(act[1]),
.ENB(act[1]), .ENB(act[1]),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_CD), .WEA(write_enable_CD),
.WEB(tidn[0]) .WEB(tidn[0])
); );
@ -502,7 +508,8 @@ arr3_D(
tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -520,7 +527,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_q[0]), .act(rd_act_q[0]),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -538,7 +546,8 @@ tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out0_reg(
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_q[1]), .act(rd_act_q[1]),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -36,11 +36,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_512x162_4w_0( module tri_512x162_4w_0 (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
ccflush_dc, ccflush_dc,
lcb_clkoff_dc_b, lcb_clkoff_dc_b,
lcb_d_mode_dc, lcb_d_mode_dc,
@ -116,7 +117,8 @@ module tri_512x162_4w_0(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
inout vcs; inout vcs;
// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input ccflush_dc; input ccflush_dc;
input lcb_clkoff_dc_b; input lcb_clkoff_dc_b;
input lcb_d_mode_dc; input lcb_d_mode_dc;
@ -257,7 +259,7 @@ module tri_512x162_4w_0(
.DOPB(dopb), .DOPB(dopb),
.ADDRA(ramb_addr), .ADDRA(ramb_addr),
.ADDRB(ramb_addr), .ADDRB(ramb_addr),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(tidn), .CLKB(tidn),
.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]), .DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
@ -265,7 +267,7 @@ module tri_512x162_4w_0(
.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]), .DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
.ENA(act[w]), .ENA(act[w]),
.ENB(tidn), .ENB(tidn),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(tidn), .SSRB(tidn),
.WEA(write[w]), .WEA(write[w]),
.WEB(tidn) .WEB(tidn)
@ -283,7 +285,8 @@ module tri_512x162_4w_0(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(0)) rd_act_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(1'b1), .act(1'b1),
.thold_b(lcb_func_sl_thold_0_b), .thold_b(lcb_func_sl_thold_0_b),
.sg(lcb_sg_0), .sg(lcb_sg_0),
@ -301,7 +304,8 @@ module tri_512x162_4w_0(
tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch( tri_rlmreg_p #(.WIDTH(port_bitwidth*ways), .INIT(0), .NEEDS_SRESET(0)) data_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_l2), .act(rd_act_l2),
.thold_b(lcb_func_sl_thold_0_b), .thold_b(lcb_func_sl_thold_0_b),
.sg(lcb_sg_0), .sg(lcb_sg_0),
@ -319,7 +323,8 @@ module tri_512x162_4w_0(
tri_plat #(.WIDTH(1)) perv_1to0_reg( tri_plat #(.WIDTH(1)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(ccflush_dc), .flush(ccflush_dc),
.din(lcb_sg_1), .din(lcb_sg_1),
.q(lcb_sg_0) .q(lcb_sg_0)
@ -332,7 +337,7 @@ module tri_512x162_4w_0(
assign bo_pc_failout = 2'b00; assign bo_pc_failout = 2'b00;
assign bo_pc_diagloop = 2'b00; assign bo_pc_diagloop = 2'b00;


assign unused = | ({nclk[2:`NCLK_WIDTH-1], ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout}); assign unused = | ({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[1][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[2][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ramb_data_out[3][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, lcb_clkoff_dc_b, lcb_d_mode_dc, lcb_act_dis_dc, scan_dis_dc_b, scan_diag_dc, bitw_abist, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, write_thru_en_dc, abst_scan_in, time_scan_in, repr_scan_in, func_scan_in, lcb_delay_lclkr_np_dc, ctrl_lcb_delay_lclkr_np_dc, dibw_lcb_delay_lclkr_np_dc, ctrl_lcb_mpw1_np_dc_b, dibw_lcb_mpw1_np_dc_b, lcb_mpw1_pp_dc_b, lcb_mpw1_2_pp_dc_b, aodo_lcb_delay_lclkr_dc, aodo_lcb_mpw1_dc_b, aodo_lcb_mpw2_dc_b, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, write_act, dob, dopb, unused_scout});
end end
endgenerate endgenerate
endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -33,13 +33,16 @@
// //
//***************************************************************************** //*****************************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_512x16_1r1w_1( module tri_512x16_1r1w_1 (
vdd, vdd,
vcs, vcs,
gnd, gnd,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
lcb_d_mode_dc, lcb_d_mode_dc,
@ -106,7 +109,8 @@ module tri_512x16_1r1w_1(
inout vcs; inout vcs;
inout gnd; inout gnd;


input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;


input rd_act; input rd_act;
input wr_act; input wr_act;
@ -173,146 +177,76 @@ module tri_512x16_1r1w_1(


output [0:15] dout; output [0:15] dout;


// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk; wire clk;
wire clk2x;
wire [0:8] b0addra; wire [0:8] b0addra;
wire [0:8] b0addrb; wire [0:8] b0addrb;
wire wea; wire wea;
wire web; wire web;
wire wren_a; wire wren_a;
// Latches wire [0:15] w_data_in_0;
reg reset_q; wire [0:15] r_data_out_0_bram;
reg gate_fq;
wire gate_d;
wire [0:35] r_data_out_1_d;
reg [0:35] r_data_out_1_fq;
wire [0:35] w_data_in_0;


wire [0:35] r_data_out_0_bram; // Latches
wire [0:35] r_data_out_1_bram; reg [0:15] r_data_out_1_q;


wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;


(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


assign clk = nclk[0]; // sim array
assign clk2x = nclk[2]; reg [0:15] mem[0:511];


always @(posedge clk) integer i;
begin: rlatch initial begin
reset_q <= nclk[1]; for (i = 0; i < 512; i = i + 1)
end mem[i] = 0;

end
//
// NEW clk2x gate logic start //wtf:icarus $dumpvars cannot dump a vpiMemory
// generate

genvar j;
always @(posedge clk) for (j = 0; j < 512; j=j+1) begin: loc
begin: tlatch wire [0:15] dat;
if (reset_q == 1'b1) assign dat = mem[j][0:15];
toggle_q <= 1'b1; end
else endgenerate
toggle_q <= toggle_d;
end //wtf do they use diff addresses?

always @(posedge clk2x)
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
r_data_out_1_fq <= r_data_out_1_d;
end

assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;

// should force gate_fq to be on during odd 2x clock (second half of 1x clock).
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));

//
// NEW clk2x gate logic end
//

assign b0addra[0:8] = wr_adr; assign b0addra[0:8] = wr_adr;
assign b0addrb[0:8] = rd_adr; assign b0addrb[0:8] = rd_adr;


// Unused Address Bits
//b0addra(0 to 1) <= "00";
//b0addrb(0 to 1) <= "00";

// port a is a read-modify-write port // port a is a read-modify-write port
assign wren_a = ((bw != 16'b0000000000000000) & (wr_act == 1'b1)) ? 1'b1 : assign wren_a = (bw != 0) & wr_act;
1'b0; assign wea = wren_a;
assign wea = wren_a & (~(gate_fq)); // write in 2nd half of nclk
assign web = 1'b0; assign web = 1'b0;
assign w_data_in_0[0] = (bw[0] == 1'b1) ? di[0] : assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
r_data_out_0_bram[0]; assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
assign w_data_in_0[1] = (bw[1] == 1'b1) ? di[1] : assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
r_data_out_0_bram[1]; assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
assign w_data_in_0[2] = (bw[2] == 1'b1) ? di[2] : assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
r_data_out_0_bram[2]; assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
assign w_data_in_0[3] = (bw[3] == 1'b1) ? di[3] : assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
r_data_out_0_bram[3]; assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
assign w_data_in_0[4] = (bw[4] == 1'b1) ? di[4] : assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
r_data_out_0_bram[4]; assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
assign w_data_in_0[5] = (bw[5] == 1'b1) ? di[5] : assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
r_data_out_0_bram[5]; assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
assign w_data_in_0[6] = (bw[6] == 1'b1) ? di[6] : assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
r_data_out_0_bram[6]; assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
assign w_data_in_0[7] = (bw[7] == 1'b1) ? di[7] : assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
r_data_out_0_bram[7]; assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];
assign w_data_in_0[8] = (bw[8] == 1'b1) ? di[8] :
r_data_out_0_bram[8]; always @(posedge clk) begin
assign w_data_in_0[9] = (bw[9] == 1'b1) ? di[9] :
r_data_out_0_bram[9]; r_data_out_1_q <= mem[b0addrb];
assign w_data_in_0[10] = (bw[10] == 1'b1) ? di[10] : if (wea) begin
r_data_out_0_bram[10]; mem[b0addra] <= w_data_in_0;
assign w_data_in_0[11] = (bw[11] == 1'b1) ? di[11] : end
r_data_out_0_bram[11];
assign w_data_in_0[12] = (bw[12] == 1'b1) ? di[12] :
r_data_out_0_bram[12];
assign w_data_in_0[13] = (bw[13] == 1'b1) ? di[13] :
r_data_out_0_bram[13];
assign w_data_in_0[14] = (bw[14] == 1'b1) ? di[14] :
r_data_out_0_bram[14];
assign w_data_in_0[15] = (bw[15] == 1'b1) ? di[15] :
r_data_out_0_bram[15];
assign w_data_in_0[16:35] = 20'b0;


assign r_data_out_1_d = r_data_out_1_bram; end

RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(reset_q),
.SSRB(reset_q),
.ADDRA(b0addra),
.ADDRB(b0addrb),
.DIA(w_data_in_0[0:31]),
.DIB(32'b0),
.DOA(r_data_out_0_bram[0:31]),
.DOB(r_data_out_1_bram[0:31]),
.DOPA(r_data_out_0_bram[32:35]),
.DOPB(r_data_out_1_bram[32:35]),
.DIPA(w_data_in_0[32:35]),
.DIPB(4'h0),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);


assign dout = r_data_out_1_fq[0:15]; assign r_data_out_0_bram = mem[b0addra];
assign dout = r_data_out_1_q[0:15];


assign func_scan_out = func_scan_in; assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in; assign time_scan_out = time_scan_in;
@ -322,12 +256,12 @@ module tri_512x16_1r1w_1(
assign bo_pc_failout = 1'b0; assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0; assign bo_pc_diagloop = 1'b0;


assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b, assign unused = |{vdd, vcs, gnd, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b, lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act, r_data_out_0_bram[16:35], r_data_out_1_fq[16:35]}; tri_lcb_act_dis_dc, rd_act};
endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -36,11 +36,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_64x144_1r1w( module tri_64x144_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
sg_0, sg_0,
@ -114,7 +115,8 @@ inout vdd;
inout vcs; inout vcs;


// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input rd_act; input rd_act;
input wr_act; input wr_act;
input sg_0; input sg_0;
@ -302,8 +304,8 @@ generate begin
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]), .DIA(ramb_data_in[(32 * anum):31 + (32 * anum)]),
.DIB(32'b0), .DIB(32'b0),
.DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]), .DIPA(ramb_par_in[(4 * anum):3 + (4 * anum)]),
@ -312,8 +314,8 @@ generate begin
.ENB(act), .ENB(act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), //sreset .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(wrt_en[anum * 4:anum * 4 + 3]), .WEA(wrt_en[anum * 4:anum * 4 + 3]),
.WEB(4'b0) //' .WEB(4'b0) //'
); );
@ -336,7 +338,6 @@ assign unused = | {
cascadeoutregb , cascadeoutregb ,
ramb_data_dummy , ramb_data_dummy ,
ramb_par_dummy , ramb_par_dummy ,
nclk[2:`NCLK_WIDTH-1] ,
gnd , gnd ,
vdd , vdd ,
vcs , vcs ,
@ -387,7 +388,8 @@ assign unused = | {
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -405,7 +407,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( tri_rlmreg_p #(.WIDTH(port_bitwidth), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_q), .act(rd_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -36,11 +36,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_64x34_8w_1r1w( module tri_64x34_8w_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
rd_act, rd_act,
wr_act, wr_act,
sg_0, sg_0,
@ -116,7 +117,8 @@ inout vdd;
inout vcs; inout vcs;


// CLOCK and CLOCKCONTROL ports // CLOCK and CLOCKCONTROL ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input rd_act; input rd_act;
input wr_act; input wr_act;
input sg_0; input sg_0;
@ -319,8 +321,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -329,8 +331,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), //sreset .SSRA(rst),
.SSRB(nclk[1]), //sreset .SSRB(rst),
.WEA(write_enable_way[0]), .WEA(write_enable_way[0]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -351,8 +353,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -361,8 +363,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[1]), .WEA(write_enable_way[1]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -383,8 +385,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -393,8 +395,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[2]), .WEA(write_enable_way[2]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -415,8 +417,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -425,8 +427,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[3]), .WEA(write_enable_way[3]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -447,8 +449,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -457,8 +459,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[4]), .WEA(write_enable_way[4]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -479,8 +481,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -489,8 +491,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[5]), .WEA(write_enable_way[5]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -511,8 +513,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -521,8 +523,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[6]), .WEA(write_enable_way[6]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -543,8 +545,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.CASCADEINLATB(1'b0), .CASCADEINLATB(1'b0),
.CASCADEINREGA(1'b0), .CASCADEINREGA(1'b0),
.CASCADEINREGB(1'b0), .CASCADEINREGB(1'b0),
.CLKA(nclk[0]), .CLKA(clk),
.CLKB(nclk[0]), .CLKB(clk),
.DIA(arr_data_in), .DIA(arr_data_in),
.DIB(tidn[0:31]), .DIB(tidn[0:31]),
.DIPA(arr_par_in), .DIPA(arr_par_in),
@ -553,8 +555,8 @@ RAMB36 #(.SIM_COLLISION_CHECK("NONE"), .READ_WIDTH_A(36), .READ_WIDTH_B(36), .WR
.ENB(rd_act), .ENB(rd_act),
.REGCEA(1'b0), .REGCEA(1'b0),
.REGCEB(1'b0), .REGCEB(1'b0),
.SSRA(nclk[1]), .SSRA(rst),
.SSRB(nclk[1]), .SSRB(rst),
.WEA(write_enable_way[7]), .WEA(write_enable_way[7]),
.WEB(tidn[0:3]) .WEB(tidn[0:3])
); );
@ -566,7 +568,7 @@ assign bo_pc_failout = tidn[0:3];
assign bo_pc_diagloop = tidn[0:3]; assign bo_pc_diagloop = tidn[0:3];


assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutregb, tiup, wr_act, assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutregb, tiup, wr_act,
ramb_data_p0_concat, nclk[2:`NCLK_WIDTH-1], gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0, ramb_data_p0_concat, gnd, vdd, vcs, sg_0, abst_sl_thold_0, ary_nsl_thold_0,
time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc, time_sl_thold_0, repr_sl_thold_0, g8t_clkoff_dc_b, ccflush_dc, scan_dis_dc_b, scan_diag_dc,
g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di, g8t_d_mode_dc, g8t_mpw1_dc_b, g8t_mpw2_dc_b, g8t_delay_lclkr_dc, wr_abst_act, rd0_abst_act, abist_di,
abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, tc_lbist_ary_wrt_thru_dc, abist_ena_1,
@ -582,7 +584,8 @@ assign unused = |({cascadeoutlata, cascadeoutlatb, cascadeoutrega, cascadeoutreg
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -600,7 +603,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rd_act_reg(
tri_rlmreg_p #(.WIDTH((ways*port_bitwidth)), .INIT(0), .NEEDS_SRESET(1)) data_out_reg( tri_rlmreg_p #(.WIDTH((ways*port_bitwidth)), .INIT(0), .NEEDS_SRESET(1)) data_out_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(rd_act_q), .act(rd_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -26,20 +26,23 @@
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ps / 1 ps `timescale 1 ns / 1 ns


//***************************************************************************** //*****************************************************************************
// Description: Tri-Lam Array Wrapper // Description: Tri-Lam Array Wrapper
// //
//***************************************************************************** //*****************************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_64x72_1r1w( module tri_64x72_1r1w (
vdd, vdd,
vcs, vcs,
gnd, gnd,
nclk, clk,
rst,
sg_0, sg_0,
abst_sl_thold_0, abst_sl_thold_0,
ary_nsl_thold_0, ary_nsl_thold_0,
@ -102,7 +105,8 @@ module tri_64x72_1r1w(
inout gnd; inout gnd;


// Clock Pervasive // Clock Pervasive
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input sg_0; input sg_0;
input abst_sl_thold_0; input abst_sl_thold_0;
input ary_nsl_thold_0; input ary_nsl_thold_0;
@ -167,150 +171,75 @@ module tri_64x72_1r1w(
input abist_raw_dc_b; input abist_raw_dc_b;
input [0:3] obs0_abist_cmp; input [0:3] obs0_abist_cmp;


// Configuration Statement for NCsim
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk; wire clk;
wire clk2x;
reg [0:8] addra;
reg [0:8] addrb;
reg wea;
reg web;
wire [0:71] bdo;
wire [0:71] bdi;
wire sreset; wire sreset;
wire [0:71] tidn; wire [0:71] tidn;
// Latches
reg reset_q;
reg gate_fq;
wire gate_d;
wire [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_d;
reg [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] bdo_fq;

wire toggle_d;
reg toggle_q;
wire toggle2x_d;
reg toggle2x_q;


(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


// sim array
reg [0:63] mem[0:71];

reg r0_e_q;
wire r0_e_d;
reg [0:5] r0_a_q;
wire [0:5] r0_a_d;
reg [0:71] r0_d_q;
wire [0:71] r0_d_d;

reg w0_e_q;
wire w0_e_d;
reg [0:5] w0_a_q;
wire [0:5] w0_a_d;
reg [0:71] w0_d_q;
wire [0:71] w0_d_d;

integer i;
initial begin
for (i = 0; i < 64; i = i + 1)
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate generate
assign tidn = 72'b0; genvar j;
assign clk = nclk[0]; for (j = 0; j < 63; j=j+1) begin: loc
assign clk2x = nclk[2]; wire [0:63] dat;
assign sreset = nclk[1]; wire [0:7] par;

assign dat = mem[j][0:63];
always @(posedge clk) assign par = mem[j][0:7];
begin: rlatch end
// reset_q <= #10 sreset; endgenerate
reset_q <= sreset; //wtf try for icarus
end

//
// NEW clk2x gate logic start
//

always @(posedge clk)
begin: tlatch
if (reset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end

always @(posedge clk2x)
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
bdo_fq <= bdo_d;
end

assign toggle_d = (~toggle_q);
assign toggle2x_d = toggle_q;


// should force gate_fq to be on during odd 2x clock (second half of 1x clock). generate
//gate_d <= toggle_q xor toggle2x_q;
// if you want the first half do the following
assign gate_d = (~(toggle_q ^ toggle2x_q));

//
// NEW clk2x gate logic end
//

if (`GPR_WIDTH == 32)
begin
assign bdi = {tidn[0:31], di[32:63], di[64:70], tidn[71]};
end
if (`GPR_WIDTH == 64)
begin
assign bdi = di[0:71];
end

assign bdo_d = bdo[64 - `GPR_WIDTH:72 - (64/`GPR_WIDTH)];
assign do0 = bdo_fq;


always @ (*)
begin
/*
wea = #10 (wr_act & gate_fq);
web = #10 (wr_act & gate_fq);


addra = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : always @(posedge clk) begin
{2'b00, rd0_adr, 1'b0});


addrb = #10 ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : r0_e_q <= rd0_act;
{2'b00, rd0_adr, 1'b1}); r0_a_q <= rd0_adr;
wea = #10 (wr_act & gate_fq); r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;
*/
wea = wr_act & gate_fq;
web = wr_act & gate_fq;


addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : if (w0_e_q) begin
{2'b00, rd0_adr, 1'b0}); mem[w0_a_q] <= w0_d_q;
end
w0_e_q <= wr_act;
w0_a_q <= wr_adr;
w0_d_q <= di;


addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : end
{2'b00, rd0_adr, 1'b1});
end
/* make wires?
assign wea = wr_act & gate_fq;
assign web = wr_act & gate_fq;
assign addra = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b0} : {2'b00, rd0_adr, 1'b0});
assign addrb = ((gate_fq == 1'b1) ? {2'b00, wr_adr, 1'b1} : {2'b00, rd0_adr, 1'b1});
*/


RAMB16_S36_S36 assign do0 = r0_d_q;
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0a(
.CLKA(clk2x),
.CLKB(clk2x),
.SSRA(sreset),
.SSRB(sreset),
.ADDRA(addra),
.ADDRB(addrb),
.DIA(bdi[00:31]),
.DIB(bdi[32:63]),
.DIPA(bdi[64:67]),
.DIPB(bdi[68:71]),
.DOA(bdo[00:31]),
.DOB(bdo[32:63]),
.DOPA(bdo[64:67]),
.DOPB(bdo[68:71]),
.ENA(1'b1),
.ENB(1'b1),
.WEA(wea),
.WEB(web)
);


assign abst_scan_out = abst_scan_in; assign abst_scan_out = abst_scan_in;
assign time_scan_out = time_scan_in; assign time_scan_out = time_scan_in;
assign repr_scan_out = repr_scan_in; assign repr_scan_out = repr_scan_in;


assign bo_pc_failout = 1'b0; assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0; assign bo_pc_diagloop = 1'b0;


assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc}); assign unused = | ({sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});


endgenerate endgenerate

endmodule endmodule

@ -34,6 +34,9 @@
// Use this line for 1 thread. Comment out for 2 thread design. // Use this line for 1 thread. Comment out for 2 thread design.
`define THREADS1 `define THREADS1


// 0: none 1: DP
`define FLOAT_TYPE 1

`define gpr_t 3'b000 `define gpr_t 3'b000
`define cr_t 3'b001 `define cr_t 3'b001
`define lr_t 3'b010 `define lr_t 3'b010

@ -36,10 +36,11 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_aoi22_nlats_wlcb( module tri_aoi22_nlats_wlcb (
vd, vd,
gd, gd,
nclk, clk,
rst,
act, act,
force_t, force_t,
thold_b, thold_b,
@ -71,7 +72,8 @@ module tri_aoi22_nlats_wlcb(


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; // 1: functional, 0: no clock input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock input thold_b; // 1: functional, 0: no clock
@ -107,12 +109,9 @@ module tri_aoi22_nlats_wlcb(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


if (NEEDS_SRESET == 1) if (NEEDS_SRESET == 1) begin
begin : rst assign sreset = rst;
assign sreset = nclk[1]; end else begin
end
if (NEEDS_SRESET != 1)
begin : no_rst
assign sreset = 1'b0; assign sreset = 1'b0;
end end


@ -128,7 +127,7 @@ module tri_aoi22_nlats_wlcb(
assign vthold_b = {WIDTH{thold_b}}; assign vthold_b = {WIDTH{thold_b}};
assign vthold = {WIDTH{~thold_b}}; assign vthold = {WIDTH{~thold_b}};


always @(posedge nclk[0]) begin: l always @(posedge clk) begin: l
//int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout); //int_dout <= (((vact & vthold_b) | vsreset) & int_din) | (((vact_b | vthold) & vsreset_b) & int_dout);
if (sreset) if (sreset)
int_dout <= int_din; int_dout <= int_din;
@ -140,6 +139,6 @@ module tri_aoi22_nlats_wlcb(


assign scout = ZEROS; assign scout = ZEROS;


assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk) | (|scin); assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|scin);
endgenerate endgenerate
endmodule endmodule

@ -41,11 +41,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_bht_1024x8_1r1w( module tri_bht_1024x8_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
pc_iu_func_sl_thold_2, pc_iu_func_sl_thold_2,
pc_iu_sg_2, pc_iu_sg_2,
pc_iu_time_sl_thold_2, pc_iu_time_sl_thold_2,
@ -112,7 +113,8 @@ module tri_bht_1024x8_1r1w(
inout vcs; inout vcs;


// clock and clockcontrol ports // clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input pc_iu_func_sl_thold_2; input pc_iu_func_sl_thold_2;
input pc_iu_sg_2; input pc_iu_sg_2;
input pc_iu_time_sl_thold_2; input pc_iu_time_sl_thold_2;
@ -331,7 +333,8 @@ module tri_bht_1024x8_1r1w(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vcs), .vcs(vcs),
.nclk(nclk), .clk(clk),
.rst(rst),


.rd_act(ary_r_en), .rd_act(ary_r_en),
.wr_act(ary_w_en), .wr_act(ary_w_en),
@ -404,7 +407,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) data_in_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -423,7 +427,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -442,7 +447,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmlatch_p #(.INIT(0)) r_act_reg( tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -461,7 +467,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -480,7 +487,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) r_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ri_act), .act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -499,7 +507,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) data_out_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ro_act), .act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -517,7 +526,8 @@ module tri_bht_1024x8_1r1w(
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reset_act), .act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -540,7 +550,8 @@ module tri_bht_1024x8_1r1w(
tri_plat #(.WIDTH(7)) perv_2to1_reg( tri_plat #(.WIDTH(7)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
@ -550,7 +561,8 @@ module tri_bht_1024x8_1r1w(
tri_plat #(.WIDTH(7)) perv_1to0_reg( tri_plat #(.WIDTH(7)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})

@ -41,11 +41,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_bht_512x4_1r1w( module tri_bht_512x4_1r1w (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
pc_iu_func_sl_thold_2, pc_iu_func_sl_thold_2,
pc_iu_sg_2, pc_iu_sg_2,
pc_iu_time_sl_thold_2, pc_iu_time_sl_thold_2,
@ -112,7 +113,8 @@ module tri_bht_512x4_1r1w(
inout vcs; inout vcs;


// clock and clockcontrol ports // clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input pc_iu_func_sl_thold_2; input pc_iu_func_sl_thold_2;
input pc_iu_sg_2; input pc_iu_sg_2;
input pc_iu_time_sl_thold_2; input pc_iu_time_sl_thold_2;
@ -331,7 +333,8 @@ module tri_bht_512x4_1r1w(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vcs), .vcs(vcs),
.nclk(nclk), .clk(clk),
.rst(rst),


.rd_act(ary_r_en), .rd_act(ary_r_en),
.wr_act(ary_w_en), .wr_act(ary_w_en),
@ -404,7 +407,8 @@ module tri_bht_512x4_1r1w(
tri_rlmlatch_p #(.INIT(0)) data_in_reg( tri_rlmlatch_p #(.INIT(0)) data_in_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -423,7 +427,8 @@ module tri_bht_512x4_1r1w(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -442,7 +447,8 @@ module tri_bht_512x4_1r1w(
tri_rlmlatch_p #(.INIT(0)) r_act_reg( tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -461,7 +467,8 @@ module tri_bht_512x4_1r1w(
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -480,7 +487,8 @@ module tri_bht_512x4_1r1w(
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ri_act), .act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -499,7 +507,8 @@ module tri_bht_512x4_1r1w(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ro_act), .act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -517,7 +526,8 @@ module tri_bht_512x4_1r1w(
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg( tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reset_act), .act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -540,7 +550,8 @@ module tri_bht_512x4_1r1w(
tri_plat #(.WIDTH(7)) perv_2to1_reg( tri_plat #(.WIDTH(7)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}) .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
@ -550,7 +561,8 @@ module tri_bht_512x4_1r1w(
tri_plat #(.WIDTH(7)) perv_1to0_reg( tri_plat #(.WIDTH(7)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0}) .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -14,35 +14,35 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


// VHDL 1076 Macro Expander C version 07/11/00
// job was run on Fri Mar 19 10:58:26 2010

//******************************************************************** //********************************************************************
//* TITLE: I-ERAT CAM Tri-Library Model //* TITLE: I-ERAT CAM Tri-Library Model
//* NAME: tri_cam_16x143_1r1w1c //* NAME: tri_cam_16x143_1r1w1c
//******************************************************************** //********************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_cam_16x143_1r1w1c( module tri_cam_16x143_1r1w1c (
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
tc_ccflush_dc, tc_ccflush_dc,
tc_scan_dis_dc_b, tc_scan_dis_dc_b,
tc_scan_diag_dc, tc_scan_diag_dc,
@ -116,7 +116,8 @@ module tri_cam_16x143_1r1w1c(
inout vcs; inout vcs;


// Clocks and Scan Cntls // Clocks and Scan Cntls
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input tc_ccflush_dc; input tc_ccflush_dc;
input tc_scan_dis_dc_b; input tc_scan_dis_dc_b;
input tc_scan_diag_dc; input tc_scan_diag_dc;
@ -195,15 +196,8 @@ module tri_cam_16x143_1r1w1c(


output [22:51] rpn_np2; output [22:51] rpn_np2;


// tri_cam_16x143_1r1w1c

// Configuration Statement for NCsim
//for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9;
//for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18;
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk; wire clk;
wire clk2x; wire rst;
wire [0:8] bram0_addra; wire [0:8] bram0_addra;
wire [0:8] bram0_addrb; wire [0:8] bram0_addrb;
wire [0:10] bram1_addra; wire [0:10] bram1_addra;
@ -217,9 +211,6 @@ module tri_cam_16x143_1r1w1c(
wire [66:72] array_cmp_data_bramp; wire [66:72] array_cmp_data_bramp;


// Latches // Latches
reg sreset_q;
reg gate_fq;
wire gate_d;
wire [52-RPN_WIDTH:51] comp_addr_np1_d; wire [52-RPN_WIDTH:51] comp_addr_np1_d;
reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input
wire [52-RPN_WIDTH:51] rpn_np2_d; wire [52-RPN_WIDTH:51] rpn_np2_d;
@ -708,51 +699,26 @@ module tri_cam_16x143_1r1w1c(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


// sim array
reg [0:62] mem[0:15];



integer i;
assign clk = (~nclk[0]); initial begin
assign clk2x = nclk[2]; for (i = 0; i < 16; i = i + 1)

mem[i] = 0;
always @(posedge clk)
begin: rlatch
sreset_q <= nclk[1];
end

//
// NEW clk2x gate logic start
//

always @(posedge nclk[0])
begin: tlatch
if (sreset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end

always @(posedge nclk[2])
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
end end


assign toggle_d = (~toggle_q); //wtf:icarus $dumpvars cannot dump a vpiMemory
assign toggle2x_d = toggle_q; generate

genvar j;
// should force gate_fq to be on during odd 2x clock (second half of 1x clock). for (j = 0; j < 16; j=j+1) begin: loc
assign gate_d = toggle_q ^ toggle2x_q; wire [0:62] dat;
// if you want the first half do the following assign dat = mem[j][0:62]; //wtf split into fields someday
//assign gate_d <= ~(toggle_q ^ toggle2x_q); end

endgenerate
//
// NEW clk2x gate logic end always @(posedge clk) begin: slatch
// if (rst) begin

// Slow Latches (nclk)
always @(posedge nclk[0])
begin: slatch
if (sreset_q == 1'b1)
begin
cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}};
cam_cmp_parity_q <= 10'b0; cam_cmp_parity_q <= 10'b0;
rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}};
@ -2539,9 +2505,9 @@ module tri_cam_16x143_1r1w1c(
//--------------------------------------------------------------------- //---------------------------------------------------------------------
// BRAM signal assignments // BRAM signal assignments
//--------------------------------------------------------------------- //---------------------------------------------------------------------
assign bram0_wea = wr_array_val[0] & gate_fq; assign bram0_wea = wr_array_val[0];
assign bram1_wea = wr_array_val[1] & gate_fq; assign bram1_wea = wr_array_val[1];
assign bram2_wea = wr_array_val[1] & gate_fq; assign bram2_wea = wr_array_val[1];;


assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1];
assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1];
@ -2559,8 +2525,24 @@ module tri_cam_16x143_1r1w1c(
assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}};
assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}};


// This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) // was 3 brams using clk2x w/wea on 2of2; matchline is combinational
// uses wr_array_val(0), parity is wr_array_data_bram(66:69) always @(posedge clk) begin

if (bram0_wea) begin
mem[bram0_addra][0:55] <= wr_array_data_bram[0:55];
end
if (bram1_wea) begin
mem[bram0_addra][56:62] <= wr_array_data_bram[66:72];
end

end

assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55];
assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62];
assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55];
assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62];

/*
RAMB16_S36_S36 RAMB16_S36_S36
#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only #(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
bram0( bram0(
@ -2633,6 +2615,7 @@ module tri_cam_16x143_1r1w1c(
.WEA(bram2_wea), .WEA(bram2_wea),
.WEB(1'b0) .WEB(1'b0)
); );
*/


// array write data swizzle -> convert 68-bit data to 73-bit bram data // array write data swizzle -> convert 68-bit data to 73-bit bram data
// 32x143 version, 42b RA // 32x143 version, 42b RA
@ -2695,7 +2678,7 @@ module tri_cam_16x143_1r1w1c(
assign regfile_scan_out = regfile_scan_in; assign regfile_scan_out = regfile_scan_in;
assign time_scan_out = time_scan_in; assign time_scan_out = time_scan_in;


assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, assign unused = |{gnd, vdd, vcs, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc,
tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b,
lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc,
pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2,

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -28,21 +28,21 @@


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


// VHDL 1076 Macro Expander C version 07/11/00
// job was run on Mon Nov 8 10:36:46 2010

//******************************************************************** //********************************************************************
//* TITLE: I-ERAT CAM Tri-Library Model //* TITLE: I-ERAT CAM Tri-Library Model
//* NAME: tri_cam_32x143_1r1w1c //* NAME: tri_cam_32x143_1r1w1c
//******************************************************************** //********************************************************************


// sim version, clk1x

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_cam_32x143_1r1w1c( module tri_cam_32x143_1r1w1c(
gnd, gnd,
vdd, vdd,
vcs, vcs,
nclk, clk,
rst,
tc_ccflush_dc, tc_ccflush_dc,
tc_scan_dis_dc_b, tc_scan_dis_dc_b,
tc_scan_diag_dc, tc_scan_diag_dc,
@ -116,7 +116,8 @@ module tri_cam_32x143_1r1w1c(
inout vcs; inout vcs;


// Clocks and Scan Cntls // Clocks and Scan Cntls
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input tc_ccflush_dc; input tc_ccflush_dc;
input tc_scan_dis_dc_b; input tc_scan_dis_dc_b;
input tc_scan_diag_dc; input tc_scan_diag_dc;
@ -195,15 +196,8 @@ module tri_cam_32x143_1r1w1c(


output [22:51] rpn_np2; output [22:51] rpn_np2;


// tri_cam_32x143_1r1w1c

// Configuration Statement for NCsim
//for all:RAMB16_S9_S9 use entity unisim.RAMB16_S9_S9;
//for all:RAMB16_S18_S18 use entity unisim.RAMB16_S18_S18;
//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;

wire clk; wire clk;
wire clk2x; wire reset;
wire [0:8] bram0_addra; wire [0:8] bram0_addra;
wire [0:8] bram0_addrb; wire [0:8] bram0_addrb;
wire [0:10] bram1_addra; wire [0:10] bram1_addra;
@ -217,9 +211,6 @@ module tri_cam_32x143_1r1w1c(
wire [66:72] array_cmp_data_bramp; wire [66:72] array_cmp_data_bramp;


// Latches // Latches
reg sreset_q;
reg gate_fq;
wire gate_d;
wire [52-RPN_WIDTH:51] comp_addr_np1_d; wire [52-RPN_WIDTH:51] comp_addr_np1_d;
reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input reg [52-RPN_WIDTH:51] comp_addr_np1_q; // the internal latched np1 phase epn(22:51) from com_addr input
wire [52-RPN_WIDTH:51] rpn_np2_d; wire [52-RPN_WIDTH:51] rpn_np2_d;
@ -1156,51 +1147,26 @@ module tri_cam_32x143_1r1w1c(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


// sim array
reg [0:62] mem[0:31];



integer i;
assign clk = (~nclk[0]); initial begin
assign clk2x = nclk[2]; for (i = 0; i < 32; i = i + 1)

mem[i] = 0;
always @(posedge clk)
begin: rlatch
sreset_q <= nclk[1];
end

//
// NEW clk2x gate logic start
//

always @(posedge nclk[0])
begin: tlatch
if (sreset_q == 1'b1)
toggle_q <= 1'b1;
else
toggle_q <= toggle_d;
end

always @(posedge nclk[2])
begin: flatch
toggle2x_q <= toggle2x_d;
gate_fq <= gate_d;
end end


assign toggle_d = (~toggle_q); //wtf:icarus $dumpvars cannot dump a vpiMemory
assign toggle2x_d = toggle_q; generate

genvar j;
// should force gate_fq to be on during odd 2x clock (second half of 1x clock). for (j = 0; j < 32; j=j+1) begin: loc
assign gate_d = toggle_q ^ toggle2x_q; wire [0:62] dat;
// if you want the first half do the following assign dat = mem[j][0:62]; //wtf split into fields someday
//assign gate_d <= ~(toggle_q ^ toggle2x_q); end

endgenerate
//
// NEW clk2x gate logic end always @(posedge clk) begin: slatch
// if (rst) begin

// Slow Latches (nclk)
always @(posedge nclk[0])
begin: slatch
if (sreset_q == 1'b1)
begin
cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}}; cam_cmp_data_q <= {CAM_DATA_WIDTH{1'b0}};
cam_cmp_parity_q <= 10'b0; cam_cmp_parity_q <= 10'b0;
rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}}; rd_cam_data_q <= {CAM_DATA_WIDTH{1'b0}};
@ -4663,13 +4629,12 @@ module tri_cam_32x143_1r1w1c(
.match(match_vec[31]) .match(match_vec[31])
); );



//--------------------------------------------------------------------- //---------------------------------------------------------------------
// BRAM signal assignments // BRAM signal assignments
//--------------------------------------------------------------------- //---------------------------------------------------------------------
assign bram0_wea = wr_array_val[0] & gate_fq; assign bram0_wea = wr_array_val[0];
assign bram1_wea = wr_array_val[1] & gate_fq; assign bram1_wea = wr_array_val[1];
assign bram2_wea = wr_array_val[1] & gate_fq; assign bram2_wea = wr_array_val[1];


assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram0_addra[9 - NUM_ENTRY_LOG2:8] = rw_entry[0:NUM_ENTRY_LOG2 - 1];
assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1]; assign bram1_addra[11 - NUM_ENTRY_LOG2:10] = rw_entry[0:NUM_ENTRY_LOG2 - 1];
@ -4687,6 +4652,24 @@ module tri_cam_32x143_1r1w1c(
assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addra[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}};
assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}}; assign bram2_addrb[0:9 - NUM_ENTRY_LOG2] = {10-NUM_ENTRY_LOG2{1'b0}};


// was 3 brams using clk2x w/wea on 2of2; matchline is combinational
always @(posedge clk) begin

if (bram0_wea) begin
mem[bram0_addra][0:55] <= wr_array_data_bram[0:55];
end
if (bram1_wea) begin
mem[bram0_addra][56:62] <= wr_array_data_bram[66:72];
end

end

assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55];
assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62];
assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55];
assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62];

/*
// This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31) // This ram houses the RPN(20:51) bits, wr_array_data_bram(0:31)
// uses wr_array_val(0), parity is wr_array_data_bram(66:69) // uses wr_array_val(0), parity is wr_array_data_bram(66:69)
RAMB16_S36_S36 RAMB16_S36_S36
@ -4761,6 +4744,7 @@ module tri_cam_32x143_1r1w1c(
.WEA(bram2_wea), .WEA(bram2_wea),
.WEB(1'b0) .WEB(1'b0)
); );
*/


// array write data swizzle -> convert 68-bit data to 73-bit bram data // array write data swizzle -> convert 68-bit data to 73-bit bram data
// 32x143 version, 42b RA // 32x143 version, 42b RA
@ -4839,7 +4823,7 @@ module tri_cam_32x143_1r1w1c(
assign regfile_scan_out = regfile_scan_in; assign regfile_scan_out = regfile_scan_in;
assign time_scan_out = time_scan_in; assign time_scan_out = time_scan_in;


assign unused = |{gnd, vdd, vcs, nclk, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc, assign unused = |{gnd, vdd, vcs, tc_ccflush_dc, tc_scan_dis_dc_b, tc_scan_diag_dc,
tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, tc_lbist_en_dc, an_ac_atpg_en_dc, lcb_d_mode_dc, lcb_clkoff_dc_b,
lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc,
pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2, pc_sg_2, pc_func_slp_sl_thold_2, pc_func_slp_nsl_thold_2, pc_regf_slp_sl_thold_2,

@ -33,6 +33,8 @@
module tri_fu_mul( module tri_fu_mul(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module tri_fu_mul(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_mul_si, f_mul_si,
f_mul_so, f_mul_so,
ex2_act, ex2_act,
@ -56,6 +57,8 @@ module tri_fu_mul(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -65,7 +68,6 @@ module tri_fu_mul(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_mul_si; //perv input f_mul_si; //perv
output f_mul_so; //perv output f_mul_so; //perv
@ -120,7 +122,8 @@ module tri_fu_mul(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -130,7 +133,8 @@ module tri_fu_mul(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -159,7 +163,8 @@ module tri_fu_mul(
.mpw2_b(mpw2_b), //i-- tidn, .mpw2_b(mpw2_b), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -224,7 +229,8 @@ module tri_fu_mul(
tri_fu_mul_92 #(.inst(2)) m92_2( tri_fu_mul_92 #(.inst(2)) m92_2(
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.force_t(force_t), //i-- .force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
@ -247,7 +253,8 @@ module tri_fu_mul(
tri_fu_mul_92 #(.inst(1)) m92_1( tri_fu_mul_92 #(.inst(1)) m92_1(
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.force_t(force_t), //i-- .force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
@ -270,7 +277,8 @@ module tri_fu_mul(
tri_fu_mul_92 #(.inst(0)) m92_0( tri_fu_mul_92 #(.inst(0)) m92_0(
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.force_t(force_t), //i-- .force_t(force_t), //i--
.lcb_delay_lclkr(delay_lclkr), //i-- tidn .lcb_delay_lclkr(delay_lclkr), //i-- tidn
.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0 .lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0

@ -39,7 +39,8 @@
module tri_fu_mul_92( module tri_fu_mul_92(
vdd, vdd,
gnd, gnd,
nclk, clk,
rst,
si, si,
so, so,
ex2_act, ex2_act,
@ -58,7 +59,8 @@ module tri_fu_mul_92(
parameter inst = 0; parameter inst = 0;
inout vdd; inout vdd;
inout gnd; inout gnd;
input [0:`NCLK_WIDTH-1] nclk; //perv input clk;
input rst;
input si; //perv input si; //perv
output so; //perv output so; //perv
input ex2_act; //act input ex2_act; //act
@ -4385,7 +4387,8 @@ module tri_fu_mul_92(
.mpw1_b(lcb_mpw1_b), //in -- tidn , .mpw1_b(lcb_mpw1_b), //in -- tidn ,
.mpw2_b(lcb_mpw2_b), //in -- tidn , .mpw2_b(lcb_mpw2_b), //in -- tidn ,
.force_t(force_t), //in -- tidn , .force_t(force_t), //in -- tidn ,
.nclk(nclk), //in .clk(clk), //in
.rst(rst),
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex2_act), //in .act(ex2_act), //in

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -26,16 +26,18 @@
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 fs / 1 fs `timescale 1 ns / 1 ns


// *!**************************************************************** // *!****************************************************************
// *! FILENAME : tri_iuq_cpl_arr.v // *! FILENAME : tri_iuq_cpl_arr.v
// *! DESCRIPTION : iuq completion array (fpga model) // *! DESCRIPTION : iuq completion array (fpga model)
// *!**************************************************************** // *!****************************************************************


// sim model - get rid of latched reset and other junk

`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr); module tri_iuq_cpl_arr (gnd, vdd, clk, rst, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, force_t, thold_0_b, sg_0, scan_in, scan_out, re0, ra0, do0, re1, ra1, do1, we0, wa0, di0, we1, wa1, di1, perr);
parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array parameter ADDRESSABLE_PORTS = 64; // number of addressable register in this array
parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports) parameter ADDRESSBUS_WIDTH = 6; // width of the bus to address all ports (2^ADDRESSBUS_WIDTH >= addressable_ports)
parameter PORT_BITWIDTH = 64; // bitwidth of ports parameter PORT_BITWIDTH = 64; // bitwidth of ports
@ -49,7 +51,8 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
(* power_pin=1 *) (* power_pin=1 *)
inout vdd; inout vdd;


input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;


//------------------------------------------------------------------- //-------------------------------------------------------------------
// Pervasive // Pervasive
@ -100,10 +103,8 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
wire [0:PORT_BITWIDTH-1] do1_d; wire [0:PORT_BITWIDTH-1] do1_d;
reg [0:PORT_BITWIDTH-1] di1_q; reg [0:PORT_BITWIDTH-1] di1_q;


wire correct_clk; wire clk;
wire reset; wire reset;
wire reset_hi;
reg reset_q;


wire [0:PORT_BITWIDTH-1] dout0; //std wire [0:PORT_BITWIDTH-1] dout0; //std
wire wen0; //std wire wen0; //std
@ -129,36 +130,18 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for




generate generate
assign reset = nclk[1];
assign correct_clk = nclk[0];

assign reset_hi = reset;


// Slow Latches (nclk)


always @(posedge correct_clk or posedge reset) always @(posedge clk) begin
begin: slatch if (rst)
begin we1_latch_q <= 1'b0;
if (reset == 1'b1) else begin
we1_latch_q <= 1'b0; we1_latch_q <= we1_q;
else wa1_latch_q <= wa1_q;
begin di1_latch_q <= di1_q;
we1_latch_q <= we1_q;
wa1_latch_q <= wa1_q;
di1_latch_q <= di1_q;
end
end end
end end



// need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
// repower latches for resets
always @(posedge correct_clk)
begin: rlatch
reset_q <= reset_hi;
end

// need to select which array to write based on the lowest order bit of the address which will indicate odd or even itag
// when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order // when both we0 and we1 are both asserted it is assumed that the low order bit of wa0 will not be equal to the low order
// bit of wa1 // bit of wa1
assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 }; assign addr_w0 = (wa0_q[ADDRESSBUS_WIDTH-1]) ? {wa1_q[0:ADDRESSBUS_WIDTH-2], 1'b0 } : {wa0_q[0:ADDRESSBUS_WIDTH-2], 1'b0 };
@ -199,7 +182,7 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
.DPRA5(addr_r0[5]), .DPRA5(addr_r0[5]),


//.DPRA(addr_r0), //.DPRA(addr_r0),
.WCLK(correct_clk), .WCLK(clk),
.WE(wen0) .WE(wen0)
); );


@ -225,7 +208,7 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
.DPRA5(addr_r1[5]), .DPRA5(addr_r1[5]),


//.DPRA(addr_r1), //.DPRA(addr_r1),
.WCLK(correct_clk), .WCLK(clk),
.WE(wen1) .WE(wen1)
); );


@ -238,44 +221,31 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
assign do0 = do0_q; assign do0 = do0_q;
assign do1 = do1_q; assign do1 = do1_q;


if (LATCHED_READ == 1'b0) if (LATCHED_READ == 1'b0) begin : read_latched_false
begin : read_latched_false always @(*) begin
always @(*)
begin
re0_q <= re0; re0_q <= re0;
ra0_q <= ra0; ra0_q <= ra0;
re1_q <= re1; re1_q <= re1;
ra1_q <= ra1; ra1_q <= ra1;
end end
end end else begin : read_latched_true
if (LATCHED_READ == 1'b1) always @(posedge clk) begin: read_latches
begin : read_latched_true if (reset) begin
always @(posedge correct_clk) re0_q <= 1'b0;
begin: read_latches ra0_q <= {ADDRESSBUS_WIDTH{1'b0}};
if (correct_clk == 1'b1) re1_q <= 1'b0;
begin ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
if (reset_q == 1'b1) end else begin
begin re0_q <= re0;
re0_q <= 1'b0; ra0_q <= ra0;
ra0_q <= {ADDRESSBUS_WIDTH{1'b0}}; re1_q <= re1;
re1_q <= 1'b0; ra1_q <= ra1;
ra1_q <= {ADDRESSBUS_WIDTH{1'b0}};
end
else
begin
re0_q <= re0;
ra0_q <= ra0;
re1_q <= re1;
ra1_q <= ra1;
end
end end
end end
end end


if (LATCHED_WRITE == 1'b0) if (LATCHED_WRITE == 1'b0) begin : write_latched_false
begin : write_latched_false always @(*) begin
always @(*)
begin
we0_q <= we0; we0_q <= we0;
wa0_q <= wa0; wa0_q <= wa0;
di0_q <= di0; di0_q <= di0;
@ -283,61 +253,43 @@ module tri_iuq_cpl_arr(gnd, vdd, nclk, delay_lclkr_dc, mpw1_dc_b, mpw2_dc_b, for
wa1_q <= wa1; wa1_q <= wa1;
di1_q <= di1; di1_q <= di1;
end end
end end else begin : write_latched_true
if (LATCHED_WRITE == 1'b1) always @(posedge clk) begin: write_latches
begin : write_latched_true if (reset) begin
always @(posedge correct_clk) we0_q <= 1'b0;
begin: write_latches wa0_q <= {ADDRESSBUS_WIDTH{1'b0}};
if (correct_clk == 1'b1) di0_q <= {PORT_BITWIDTH{1'b0}};
begin we1_q <= 1'b0;
if (reset_q == 1'b1) wa1_q <= {ADDRESSBUS_WIDTH{1'b0}};
begin di1_q <= {PORT_BITWIDTH{1'b0}};
we0_q <= 1'b0; end else begin
wa0_q <= {ADDRESSBUS_WIDTH{1'b0}}; we0_q <= we0;
di0_q <= {PORT_BITWIDTH{1'b0}}; wa0_q <= wa0;
we1_q <= 1'b0; di0_q <= di0;
wa1_q <= {ADDRESSBUS_WIDTH{1'b0}}; we1_q <= we1;
di1_q <= {PORT_BITWIDTH{1'b0}}; wa1_q <= wa1;
end di1_q <= di1;
else
begin
we0_q <= we0;
wa0_q <= wa0;
di0_q <= di0;
we1_q <= we1;
wa1_q <= wa1;
di1_q <= di1;
end
end end
end end
end end


if (LATCHED_READ_DATA == 1'b0) if (LATCHED_READ_DATA == 1'b0) begin : read_data_latched_false
begin : read_data_latched_false always @(*) begin
always @(*)
begin
do0_q <= do0_d; do0_q <= do0_d;
do1_q <= do1_d; do1_q <= do1_d;
end end
end end else begin : read_data_latched_true
if (LATCHED_READ_DATA == 1'b1) always @(posedge clk) begin: read_data_latches
begin : read_data_latched_true if (reset) begin
always @(posedge correct_clk) do0_q <= 0;
begin: read_data_latches do1_q <= 0;
if (correct_clk == 1'b1) end else begin
begin do0_q <= do0_d;
if (reset_q == 1'b1) do1_q <= do1_d;
begin
do0_q <= {PORT_BITWIDTH{1'b0}};
do1_q <= {PORT_BITWIDTH{1'b0}};
end
else
begin
do0_q <= do0_d;
do1_q <= do1_d;
end
end end
end end
end end

endgenerate endgenerate

endmodule endmodule

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,11 +35,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_lcbcntl_array_mac( module tri_lcbcntl_array_mac (
vdd, vdd,
gnd, gnd,
sg, sg,
nclk, clk,
rst,
scan_in, scan_in,
scan_diag_dc, scan_diag_dc,
thold, thold,
@ -54,7 +55,8 @@ module tri_lcbcntl_array_mac(
inout vdd; inout vdd;
inout gnd; inout gnd;
input sg; input sg;
input [0:`NCLK_WIDTH-1] nclk; input rst;
input clk;
input scan_in; input scan_in;
input scan_diag_dc; input scan_diag_dc;
input thold; input thold;
@ -79,5 +81,5 @@ module tri_lcbcntl_array_mac(
assign mpw2_dc_b = 1'b1; assign mpw2_dc_b = 1'b1;
assign scan_out = 1'b0; assign scan_out = 1'b0;


assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold;
endmodule endmodule

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,11 +35,12 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_lcbcntl_mac( module tri_lcbcntl_mac (
vdd, vdd,
gnd, gnd,
sg, sg,
nclk, clk,
rst,
scan_in, scan_in,
scan_diag_dc, scan_diag_dc,
thold, thold,
@ -54,7 +55,8 @@ module tri_lcbcntl_mac(
inout vdd; inout vdd;
inout gnd; inout gnd;
input sg; input sg;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input scan_in; input scan_in;
input scan_diag_dc; input scan_diag_dc;
input thold; input thold;
@ -79,5 +81,5 @@ module tri_lcbcntl_mac(
assign mpw2_dc_b = 1'b1; assign mpw2_dc_b = 1'b1;
assign scan_out = 1'b0; assign scan_out = 1'b0;


assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold; assign unused = vdd | gnd | sg | scan_in | scan_diag_dc | thold;
endmodule endmodule

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,14 +35,15 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_lcbnd( module tri_lcbnd (
vd, vd,
gd, gd,
act, act,
delay_lclkr, delay_lclkr,
mpw1_b, mpw1_b,
mpw2_b, mpw2_b,
nclk, clk,
rst,
force_t, force_t,
sg, sg,
thold_b, thold_b,
@ -58,7 +59,8 @@ module tri_lcbnd(
input delay_lclkr; input delay_lclkr;
input mpw1_b; input mpw1_b;
input mpw2_b; input mpw2_b;
input[0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input force_t; input force_t;
input sg; input sg;
input thold_b; input thold_b;
@ -77,5 +79,5 @@ module tri_lcbnd(


assign d1clk = gate_b; assign d1clk = gate_b;
assign d2clk = thold_b; assign d2clk = thold_b;
assign lclk = nclk; assign lclk = {clk,rst,{`NCLK_WIDTH-2{1'b0}}};
endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,11 +35,13 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_lcbs( //wtf this should be changed to output clk,rst instead of lclk; think it's only for alternate ring lats?
module tri_lcbs (
vd, vd,
gd, gd,
delay_lclkr, delay_lclkr,
nclk, clk,
rst,
force_t, force_t,
thold_b, thold_b,
dclk, dclk,
@ -48,7 +50,8 @@ module tri_lcbs(
inout vd; inout vd;
inout gd; inout gd;
input delay_lclkr; input delay_lclkr;
input[0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input force_t; input force_t;
input thold_b; input thold_b;
output dclk; output dclk;
@ -63,5 +66,5 @@ module tri_lcbs(


// No scan chain in this methodology // No scan chain in this methodology
assign dclk = thold_b; assign dclk = thold_b;
assign lclk = nclk; assign lclk = {clk, rst, {`NCLK_WIDTH-2{1'b0}}};
endmodule endmodule

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -72,7 +72,8 @@ module tri_lq_rmw(
dcarr_wr_addr, dcarr_wr_addr,
dcarr_wr_data_wabcd, dcarr_wr_data_wabcd,
dcarr_wr_data_wefgh, dcarr_wr_data_wefgh,
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
d_mode_dc, d_mode_dc,
@ -126,8 +127,8 @@ output [52:59] dcarr_wr_addr;
output [0:143] dcarr_wr_data_wabcd; output [0:143] dcarr_wr_data_wabcd;
output [0:143] dcarr_wr_data_wefgh; output [0:143] dcarr_wr_data_wefgh;


(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) input clk;
input [0:`NCLK_WIDTH-1] nclk; input rst;
inout vdd; inout vdd;
inout gnd; inout gnd;
input d_mode_dc; input d_mode_dc;
@ -352,7 +353,8 @@ assign stq_byp_val_wefgh = stq_byp_val_wefgh_q;
// Registers // Registers
// ############################################################################################# // #############################################################################################
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(tiup), .act(tiup),
@ -370,7 +372,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_stg_act_latch(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(tiup), .act(tiup),
@ -390,7 +393,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_stg_act_latch(
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -408,7 +412,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_stq5_rd_addr_reg(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -426,7 +431,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq6_arr_wren_reg(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -444,7 +450,8 @@ tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) stq7_arr_wren_reg(
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -462,7 +469,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_way_en_reg(
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq6_stg_act_q), .act(stq6_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -480,7 +488,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_way_en_reg(
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -498,7 +507,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq6_addr_reg(
tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq6_stg_act_q), .act(stq6_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -516,7 +526,8 @@ tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) stq7_addr_reg(
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq6_stg_act_q), .act(stq6_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -534,7 +545,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wabcd_reg(
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq6_stg_act_q), .act(stq6_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -552,7 +564,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq7_wr_data_wefgh_reg(
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq7_stg_act_q), .act(stq7_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -570,7 +583,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wabcd_reg(
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq7_stg_act_q), .act(stq7_stg_act_q),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -588,7 +602,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq8_wr_data_wefgh_reg(
tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -606,7 +621,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wabcd_reg(
tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -624,7 +640,8 @@ tri_rlmreg_p #(.WIDTH(16), .INIT(0), .NEEDS_SRESET(1)) stq6_byte_en_wefgh_reg(
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -642,7 +659,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wabcd_r
tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg( tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stq5_stg_act), .act(stq5_stg_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -660,7 +678,8 @@ tri_rlmreg_p #(.WIDTH(144), .INIT(0), .NEEDS_SRESET(1)) stq6_byp_wr_data_wefgh_r
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -678,7 +697,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wabcd_reg(
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -696,7 +716,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq7_byp_val_wefgh_reg(
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),
@ -714,7 +735,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wabcd_reg(
tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) stq_byp_val_wefgh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .d_mode(d_mode_dc),

@ -38,13 +38,14 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_parity_recovery( module tri_parity_recovery (
perr_si, perr_si,
perr_so, perr_so,
delay_lclkr, delay_lclkr,
mpw1_b, mpw1_b,
mpw2_b, mpw2_b,
nclk, clk,
rst,
force_t, force_t,
thold_0_b, thold_0_b,
sg_0, sg_0,
@ -132,7 +133,8 @@ module tri_parity_recovery(


input [0:9] mpw1_b; input [0:9] mpw1_b;
input [0:1] mpw2_b; input [0:1] mpw2_b;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input force_t; input force_t;
input thold_0_b; input thold_0_b;
input sg_0; input sg_0;
@ -380,7 +382,8 @@ module tri_parity_recovery(




tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -412,7 +415,8 @@ module tri_parity_recovery(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr( tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -440,7 +444,8 @@ module tri_parity_recovery(




tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr( tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -468,7 +473,8 @@ module tri_parity_recovery(


//------------------------------------------- //-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr( tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -537,7 +543,8 @@ module tri_parity_recovery(




tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm( tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -557,7 +564,8 @@ module tri_parity_recovery(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -770,7 +778,8 @@ module tri_parity_recovery(




tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,7 +35,7 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_plat(vd, gd, nclk, flush, din, q); module tri_plat (vd, gd, clk, rst, flush, din, q);
parameter WIDTH = 1; parameter WIDTH = 1;
parameter OFFSET = 0; parameter OFFSET = 0;
parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v parameter INIT = 0; // will be converted to the least signficant 31 bits of init_v
@ -43,7 +43,8 @@ module tri_plat(vd, gd, nclk, flush, din, q);


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input flush; input flush;
input [OFFSET:OFFSET+WIDTH-1] din; input [OFFSET:OFFSET+WIDTH-1] din;
output [OFFSET:OFFSET+WIDTH-1] q; output [OFFSET:OFFSET+WIDTH-1] q;
@ -53,10 +54,10 @@ module tri_plat(vd, gd, nclk, flush, din, q);


(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;
assign unused = | {vd, gd, nclk[1:`NCLK_WIDTH-1]}; assign unused = | {vd, gd};




always @ (posedge nclk[0]) always @ (posedge clk)
begin begin
int_dout <= din; int_dout <= din;
end end

@ -35,10 +35,11 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_regk( module tri_regk (
vd, vd,
gd, gd,
nclk, clk,
rst,
act, act,
force_t, force_t,
thold_b, thold_b,
@ -62,7 +63,8 @@ module tri_regk(


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; // 1: functional, 0: no clock input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock input thold_b; // 1: functional, 0: no clock
@ -85,9 +87,9 @@ module tri_regk(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; assign sreset = (NEEDS_SRESET == 1) ? rst : 0;


always @(posedge nclk[0]) begin: l always @(posedge clk) begin: l
if (sreset) if (sreset)
int_dout <= init_v; int_dout <= init_v;
else if (act & thold_b) else if (act & thold_b)
@ -98,7 +100,8 @@ module tri_regk(


assign scout = {WIDTH{1'b0}}; assign scout = {WIDTH{1'b0}};


assign unused = | {vd, gd, nclk, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); assign unused = | {vd, gd, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin};

endgenerate endgenerate


endmodule endmodule

@ -35,10 +35,11 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_regs( module tri_regs (
vd, vd,
gd, gd,
nclk, clk,
rst,
force_t, force_t,
thold_b, thold_b,
delay_lclkr, delay_lclkr,
@ -57,7 +58,8 @@ module tri_regs(


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input force_t; // 1: force LCB active input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock input thold_b; // 1: functional, 0: no clock
input delay_lclkr; // 0: functional input delay_lclkr; // 0: functional
@ -73,9 +75,9 @@ module tri_regs(
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; assign sreset = (NEEDS_SRESET == 1) ? rst : 0;


always @(posedge nclk[0]) begin: l always @(posedge clk) begin: l
if (sreset) if (sreset)
int_dout <= init_v; int_dout <= init_v;
end end
@ -84,7 +86,7 @@ module tri_regs(


assign scout = {WIDTH{1'b0}}; assign scout = {WIDTH{1'b0}};


assign unused = |{vd, gd, delay_lclkr, scin} | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); assign unused = |{vd, gd, delay_lclkr, scin};


endgenerate endgenerate



@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -35,7 +35,7 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); module tri_rlmlatch_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout);
parameter INIT = 0; // will be converted to the least signficant parameter INIT = 0; // will be converted to the least signficant
// 31 bits of init_v // 31 bits of init_v
parameter IBUF = 1'b0; //inverted latch IOs, if set to true. parameter IBUF = 1'b0; //inverted latch IOs, if set to true.
@ -45,7 +45,8 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; // 1: functional, 0: no clock input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock input thold_b; // 1: functional, 0: no clock
@ -62,8 +63,6 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
parameter WIDTH = 1; parameter WIDTH = 1;
parameter [0:WIDTH-1] init_v = INIT; parameter [0:WIDTH-1] init_v = INIT;


// tri_rlmlatch_p

generate generate
wire sreset; wire sreset;
wire int_din; wire int_din;
@ -71,11 +70,11 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire unused; wire unused;


assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; assign sreset = (NEEDS_SRESET == 1) ? rst : 0;


assign int_din = IBUF ? ~din : din; assign int_din = IBUF ? ~din : din;


always @(posedge nclk[0]) begin: l always @(posedge clk) begin: l
if (sreset) // reset value if (sreset) // reset value
int_dout <= init_v[0]; int_dout <= init_v[0];
else if ((act | force_t) & thold_b) // activate or force, and not clk off else if ((act | force_t) & thold_b) // activate or force, and not clk off
@ -84,9 +83,9 @@ module tri_rlmlatch_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lcl


assign dout = IBUF ? ~int_dout : int_dout; assign dout = IBUF ? ~int_dout : int_dout;


assign scout = 1'b0; assign scout = 0;


assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); assign unused = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | scin | vd | gd;


endgenerate endgenerate
endmodule endmodule

@ -1,4 +1,4 @@
// © IBM Corp. 2020 // © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by // Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in // the terms below; you may not use the files in this repository except in
// compliance with the License as modified. // compliance with the License as modified.
@ -35,7 +35,7 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout); module tri_rlmreg_p (vd, gd, clk, rst, act, force_t, thold_b, d_mode, sg, delay_lclkr, mpw1_b, mpw2_b, scin, din, scout, dout);
parameter WIDTH = 4; parameter WIDTH = 4;
parameter OFFSET = 0; //starting bit parameter OFFSET = 0; //starting bit
parameter INIT = 0; // will be converted to the least signficant parameter INIT = 0; // will be converted to the least signficant
@ -50,7 +50,8 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; // 1: functional, 0: no clock input act; // 1: functional, 0: no clock
input force_t; // 1: force LCB active input force_t; // 1: force LCB active
input thold_b; // 1: functional, 0: no clock input thold_b; // 1: functional, 0: no clock
@ -76,11 +77,11 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr
(* analysis_not_referenced="true" *) (* analysis_not_referenced="true" *)
wire [0:WIDTH] unused; wire [0:WIDTH] unused;


assign sreset = (NEEDS_SRESET == 1) ? nclk[1] : 0; assign sreset = (NEEDS_SRESET == 1) ? rst : 0;


assign int_din = sreset ? init_v : (IBUF == 1'b1) ? ~din : din; //wtf why is sreset needed here??? sim fails w/o it. assign int_din = sreset ? init_v : (IBUF == 1'b1) ? ~din : din; //wtf why is sreset needed here??? sim fails w/o it.


always @(posedge nclk[0]) begin: l always @(posedge clk) begin: l
if (sreset) // reset value if (sreset) // reset value
int_dout <= init_v; int_dout <= init_v;
else if ((act | force_t) & thold_b) // activate or force, and not clk off else if ((act | force_t) & thold_b) // activate or force, and not clk off
@ -91,7 +92,7 @@ module tri_rlmreg_p(vd, gd, nclk, act, force_t, thold_b, d_mode, sg, delay_lclkr


assign scout = {WIDTH{1'b0}}; assign scout = {WIDTH{1'b0}};


assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd | (|nclk[2:`NCLK_WIDTH-1]) | ((NEEDS_SRESET == 1) ? 0 : nclk[1]); assign unused[0] = d_mode | sg | delay_lclkr | mpw1_b | mpw2_b | vd | gd;
assign unused[1:WIDTH] = scin; assign unused[1:WIDTH] = scin;


endgenerate endgenerate

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -52,7 +52,8 @@ module tri_rot16_ru(
stq8_rmw_data, stq8_rmw_data,
data_latched, data_latched,
data_rot, data_rot,
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
delay_lclkr_dc, delay_lclkr_dc,
@ -81,7 +82,8 @@ output [0:15] data_latched; // latched data, not rotated
output [0:15] data_rot; // rotated data out output [0:15] data_rot; // rotated data out


(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;


inout vdd; inout vdd;
inout gnd; inout gnd;
@ -453,7 +455,8 @@ tri_lcbnd my_lcb(
.mpw1_b(mpw1_dc_b), .mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b), .mpw2_b(mpw2_dc_b),
.force_t(func_sl_force), .force_t(func_sl_force),
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(act), .act(act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -57,7 +57,8 @@ module tri_rot16s_ru(
data_latched, data_latched,
data_rot, data_rot,
algebraic_bit, algebraic_bit,
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
delay_lclkr_dc, delay_lclkr_dc,
@ -91,10 +92,10 @@ output [0:15] data_rot; // rotated data out
output [0:5] algebraic_bit; output [0:5] algebraic_bit;


(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) (* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *)
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;


inout vdd; inout vdd;

inout gnd; inout gnd;
input delay_lclkr_dc; input delay_lclkr_dc;
input mpw1_dc_b; input mpw1_dc_b;
@ -613,7 +614,8 @@ tri_lcbnd my_lcb(
.mpw1_b(mpw1_dc_b), .mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b), .mpw2_b(mpw2_dc_b),
.force_t(func_sl_force), .force_t(func_sl_force),
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(act), .act(act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,10 +35,11 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_ser_rlmreg_p( module tri_ser_rlmreg_p (
vd, vd,
gd, gd,
nclk, clk,
rst,
act, act,
force_t, force_t,
thold_b, thold_b,
@ -62,7 +63,8 @@ module tri_ser_rlmreg_p(


inout vd; inout vd;
inout gd; inout gd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input act; input act;
input force_t; input force_t;
input thold_b; input thold_b;
@ -89,7 +91,8 @@ module tri_ser_rlmreg_p(
assign dout = dout_buf; assign dout = dout_buf;


tri_aoi22_nlats_wlcb #(.WIDTH(WIDTH), .OFFSET(OFFSET), .INIT(INIT), .IBUF(IBUF), .DUALSCAN(DUALSCAN), .NEEDS_SRESET(NEEDS_SRESET)) tri_ser_rlmreg_p( tri_aoi22_nlats_wlcb #(.WIDTH(WIDTH), .OFFSET(OFFSET), .INIT(INIT), .IBUF(IBUF), .DUALSCAN(DUALSCAN), .NEEDS_SRESET(NEEDS_SRESET)) tri_ser_rlmreg_p(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vd), .vd(vd),
.gd(gd), .gd(gd),
.act(act), .act(act),

@ -37,8 +37,9 @@


`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_serial_scom2( module tri_serial_scom2 (
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
scom_func_thold, scom_func_thold,
@ -94,17 +95,18 @@ module tri_serial_scom2(
parameter RINGID_NOBITS = 3; parameter RINGID_NOBITS = 3;


// clock, scan and misc interfaces // clock, scan and misc interfaces
input [0:`NCLK_WIDTH-1] nclk;
inout vdd; inout vdd;
inout gnd; inout gnd;
input scom_func_thold; input clk;
input rst;
input scom_func_thold;
input sg; input sg;
input act_dis_dc; input act_dis_dc;
input clkoff_dc_b; input clkoff_dc_b;
input mpw1_dc_b; input mpw1_dc_b;
input mpw2_dc_b; input mpw2_dc_b;
input d_mode_dc; input d_mode_dc;
input delay_lclkr_dc; input delay_lclkr_dc;


//lcb_align_0 : in std_ulogic; //lcb_align_0 : in std_ulogic;


@ -336,14 +338,15 @@ module tri_serial_scom2(
.thold_b(func_thold_b) .thold_b(func_thold_b)
); );


tri_lcbnd lcb_func( tri_lcbnd lcb_func(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(local_act_int), .act(local_act_int),
.delay_lclkr(delay_lclkr_dc), .delay_lclkr(delay_lclkr_dc),
.mpw1_b(mpw1_dc_b), .mpw1_b(mpw1_dc_b),
.mpw2_b(mpw2_dc_b), .mpw2_b(mpw2_dc_b),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(func_force), .force_t(func_force),
.sg(sg), .sg(sg),
.thold_b(func_thold_b), .thold_b(func_thold_b),

@ -35,7 +35,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_st_mult( module tri_st_mult(
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
d_mode_dc, d_mode_dc,
@ -72,10 +73,10 @@ module tri_st_mult(
//------------------------------------------------------------------- //-------------------------------------------------------------------
// Clocks & Power // Clocks & Power
//------------------------------------------------------------------- //-------------------------------------------------------------------
(* pin_data="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk;
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;


//------------------------------------------------------------------- //-------------------------------------------------------------------
// Pervasive // Pervasive
@ -499,7 +500,8 @@ module tri_st_mult(
//------------------------------------------------------------------- //-------------------------------------------------------------------


tri_st_mult_core mcore( tri_st_mult_core mcore(
.nclk(nclk), .clk(clk),
.rst(rst),
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.delay_lclkr_dc(delay_lclkr_dc), .delay_lclkr_dc(delay_lclkr_dc),
@ -746,7 +748,8 @@ module tri_st_mult(
//------------------------------------------------------------------- //-------------------------------------------------------------------


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_spr_msr_cm_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -764,7 +767,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_msr_cm_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_spr_msr_cm_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mul_val_q), .act(ex2_mul_val_q),
@ -782,7 +786,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_spr_msr_cm_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_spr_msr_cm_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex3_act), .act(ex3_act),
@ -800,7 +805,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spr_msr_cm_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_spr_msr_cm_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex4_act), .act(ex4_act),
@ -818,7 +824,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_is_ord_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_is_ord_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -836,7 +843,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_is_ord_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_mul_is_ord_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mul_val_q), .act(ex2_mul_val_q),
@ -854,7 +862,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_is_ord_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_is_ord_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex3_act), .act(ex3_act),
@ -872,7 +881,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_is_ord_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_is_ord_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex4_act), .act(ex4_act),
@ -890,7 +900,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_src_latch( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex3_xer_src_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mul_val_q), .act(ex2_mul_val_q),
@ -908,7 +919,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex4_xer_src_latch( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex4_xer_src_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex3_act), .act(ex3_act),
@ -926,7 +938,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex5_xer_src_latch( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex5_xer_src_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex4_act), .act(ex4_act),
@ -944,7 +957,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex6_xer_src_latch( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) ex6_xer_src_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_act), .act(ex5_act),
@ -962,7 +976,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_val_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_val_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -980,7 +995,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex3_mulstage_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex3_mulstage_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -998,7 +1014,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_mulstage_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex4_mulstage_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1016,7 +1033,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_mulstage_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex5_mulstage_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1034,7 +1052,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_mulstage_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex6_mulstage_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1052,7 +1071,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_retsel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_retsel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -1070,7 +1090,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_retsel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_retsel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mul_val_q), .act(ex2_mul_val_q),
@ -1088,7 +1109,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_retsel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_retsel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1106,7 +1128,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_retsel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex5_retsel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1124,7 +1147,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) exx_mul_abort_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) exx_mul_abort_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1142,7 +1166,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_done_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_mul_done_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1160,7 +1185,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_done_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_mul_done_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1178,7 +1204,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_recform_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_is_recform_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -1196,7 +1223,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_recform_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_is_recform_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1214,7 +1242,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_recform_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_is_recform_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1232,7 +1261,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_is_recform_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_is_recform_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1250,7 +1280,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_is_recform_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_is_recform_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1268,7 +1299,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_xer_ov_update_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -1286,7 +1318,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_xer_ov_update_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1304,7 +1337,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex4_xer_ov_update_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1322,7 +1356,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xer_ov_update_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_xer_ov_update_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1340,7 +1375,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_ov_update_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_xer_ov_update_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1358,7 +1394,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_size_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_size_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -1376,7 +1413,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_sign_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mul_sign_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_mul_val), .act(ex1_mul_val),
@ -1394,7 +1432,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bs_lo_sign_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bs_lo_sign_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1412,7 +1451,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bd_lo_sign_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_bd_lo_sign_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1430,7 +1470,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1448,7 +1489,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1466,7 +1508,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1484,7 +1527,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all0_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1502,7 +1546,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_all1_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1520,7 +1565,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ci_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex5_ci_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1538,7 +1584,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex6_res_latch( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex6_res_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_act), .act(ex5_act),
@ -1556,7 +1603,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) carry_32_dly1_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) carry_32_dly1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1574,7 +1622,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly1_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1592,7 +1641,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly2_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly2_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1610,7 +1660,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly3_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) all0_lo_dly3_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -1628,7 +1679,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(rslt_lo_act), .act(rslt_lo_act),
@ -1646,7 +1698,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_dly_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0), .NEEDS_SRESET(1)) rslt_lo_dly_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(rslt_lo_act_q), .act(rslt_lo_act_q),
@ -1664,7 +1717,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_0_latch( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_0_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mulsrc0_act), .act(ex2_mulsrc0_act),
@ -1682,7 +1736,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_1_latch( tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) ex3_mulsrc_1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mulsrc1_act), .act(ex2_mulsrc1_act),
@ -1700,7 +1755,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_hw_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_hw_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1718,7 +1774,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ld_li_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ld_li_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1736,7 +1793,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ldo_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_ldo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1754,7 +1812,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_lw_hd_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex6_rslt_lw_hd_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1772,7 +1831,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reshi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reshi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1790,7 +1850,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1808,7 +1869,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1826,7 +1888,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly2_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_sel_reslodly2_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1844,7 +1907,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1862,7 +1926,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1880,7 +1945,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_hi_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_hi_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1898,7 +1964,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo1_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo1_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1916,7 +1983,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo2_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo2_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1934,7 +2002,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo3_b_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_eq_sel_all0_lo3_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1952,7 +2021,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mullw_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mullw_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1970,7 +2040,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mulldo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_ret_mulldo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -1988,7 +2059,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_undef_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex6_cmp0_undef_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex5_mul_done_q), .act(ex5_mul_done_q),
@ -2006,7 +2078,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) cp_flush_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -2024,7 +2097,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_mul_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex2_mul_tid_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -2042,7 +2116,8 @@ module tri_st_mult(
); );


tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_mul_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0), .NEEDS_SRESET(1)) ex3_mul_tid_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_mul_val_q), .act(ex2_mul_val_q),
@ -2059,7 +2134,8 @@ module tri_st_mult(
.dout(ex3_mul_tid_q) .dout(ex3_mul_tid_q)
); );
tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_mul_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex4_mul_tid_latch(
.nclk(nclk), .vd(vdd), .gd(gnd), .clk(clk),
.rst(rst), .vd(vdd), .gd(gnd),
.act(ex3_act), .act(ex3_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc),
@ -2072,7 +2148,8 @@ module tri_st_mult(
.dout(ex4_mul_tid_q) .dout(ex4_mul_tid_q)
); );
tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_mul_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .OFFSET(0),.INIT(0), .NEEDS_SRESET(1)) ex5_mul_tid_latch(
.nclk(nclk), .vd(vdd), .gd(gnd), .clk(clk),
.rst(rst), .vd(vdd), .gd(gnd),
.act(ex4_act), .act(ex4_act),
.force_t(func_sl_force), .force_t(func_sl_force),
.d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc), .d_mode(d_mode_dc), .delay_lclkr(delay_lclkr_dc),
@ -2086,7 +2163,8 @@ module tri_st_mult(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rslt_lo_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) rslt_lo_act_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),

@ -40,7 +40,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_st_mult_core( module tri_st_mult_core(
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
delay_lclkr_dc, delay_lclkr_dc,
@ -63,9 +64,10 @@ module tri_st_mult_core(
ex5_pp5_0c_out ex5_pp5_0c_out
); );
// Pervasive --------------------------------------- // Pervasive ---------------------------------------
input [0:`NCLK_WIDTH-1] nclk;
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input delay_lclkr_dc; input delay_lclkr_dc;
input mpw1_dc_b; input mpw1_dc_b;
input mpw2_dc_b; input mpw2_dc_b;
@ -7231,7 +7233,8 @@ module tri_st_mult_core(
.mpw1_b(mpw1_dc_b), //in -- 0 , .mpw1_b(mpw1_dc_b), //in -- 0 ,
.mpw2_b(mpw2_dc_b), //in -- 0 , .mpw2_b(mpw2_dc_b), //in -- 0 ,
.force_t(func_sl_force), //in -- 0 , .force_t(func_sl_force), //in -- 0 ,
.nclk(nclk), //in .clk(clk),
.rst(rst),
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex3_act), //in .act(ex3_act), //in
@ -7248,7 +7251,8 @@ module tri_st_mult_core(
.mpw1_b(mpw1_dc_b), //in -- 0 , .mpw1_b(mpw1_dc_b), //in -- 0 ,
.mpw2_b(mpw2_dc_b), //in -- 0 , .mpw2_b(mpw2_dc_b), //in -- 0 ,
.force_t(func_sl_force), //in -- 0 , .force_t(func_sl_force), //in -- 0 ,
.nclk(nclk), //in .clk(clk),
.rst(rst),
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex4_act), //in .act(ex4_act), //in

@ -36,7 +36,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_st_popcnt( module tri_st_popcnt(
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
delay_lclkr_dc, delay_lclkr_dc,
@ -56,7 +57,8 @@ module tri_st_popcnt(
//------------------------------------------------------------------- //-------------------------------------------------------------------
// Clocks & Power // Clocks & Power
//------------------------------------------------------------------- //-------------------------------------------------------------------
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
inout vdd; inout vdd;
inout gnd; inout gnd;


@ -193,7 +195,8 @@ module tri_st_popcnt(
//------------------------------------------------------------------- //-------------------------------------------------------------------


tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) exx_act_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -211,7 +214,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_instr_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[1]), .act(exx_act[1]),
@ -229,7 +233,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_popcnt_sel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex3_popcnt_sel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[2]), .act(exx_act[2]),
@ -247,7 +252,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b3_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b3_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[2]), .act(exx_act[2]),
@ -265,7 +271,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b2_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b2_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[2]), .act(exx_act[2]),
@ -283,7 +290,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b1_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[2]), .act(exx_act[2]),
@ -301,7 +309,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b0_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex3_b0_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[2]), .act(exx_act[2]),
@ -319,7 +328,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b3_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b3_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -337,7 +347,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b2_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b2_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -355,7 +366,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b1_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -373,7 +385,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b0_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(1)) ex4_b0_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -391,7 +404,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word0_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word0_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -409,7 +423,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word1_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex4_word1_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),
@ -427,7 +442,8 @@ module tri_st_popcnt(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_popcnt_sel_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex4_popcnt_sel_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(exx_act[3]), .act(exx_act[3]),

@ -35,7 +35,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module tri_st_rot( module tri_st_rot(
nclk, clk,
rst,
vdd, vdd,
gnd, gnd,
d_mode_dc, d_mode_dc,
@ -59,7 +60,8 @@ module tri_st_rot(
ex3_xer_ca, ex3_xer_ca,
ex3_cr_eq ex3_cr_eq
); );
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
inout vdd; inout vdd;
inout gnd; inout gnd;
input d_mode_dc; input d_mode_dc;
@ -430,7 +432,8 @@ module tri_st_rot(
//------------------------------------------------------------------- //-------------------------------------------------------------------


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_act_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b1), .act(1'b1),
@ -448,7 +451,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_mb_ins_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_mb_ins_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -466,7 +470,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_me_ins_b_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_me_ins_b_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -484,7 +489,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_amt_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_amt_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -502,7 +508,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_right_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_right_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -520,7 +527,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_word_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) ex2_sh_word_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -538,7 +546,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_zm_ins_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_zm_ins_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -556,7 +565,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_wd_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_wd_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -574,7 +584,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_dw_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_chk_shov_dw_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -592,7 +603,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -610,7 +622,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_sh_amt_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -628,7 +641,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -646,7 +660,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_rb_amt_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -664,7 +679,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -682,7 +698,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_rb_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -700,7 +717,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -718,7 +736,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_rb_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -736,7 +755,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -754,7 +774,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_me_ins_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -772,7 +793,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_hi_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_hi_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -790,7 +812,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_lo_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_use_mb_ins_lo_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -808,7 +831,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyw_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyw_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -826,7 +850,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyd_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_ins_prtyd_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -844,7 +869,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mb_gt_me_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_mb_gt_me_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -862,7 +888,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cmp_byte_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_cmp_byte_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -880,7 +907,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_byte_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_byte_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -898,7 +926,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_half_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_half_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -916,7 +945,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_wd_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sgnxtd_wd_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -934,7 +964,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_wd_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_wd_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -952,7 +983,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_dw_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sra_dw_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -970,7 +1002,8 @@ module tri_st_rot(
); );


tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_log_fcn_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0), .NEEDS_SRESET(1)) ex2_log_fcn_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -988,7 +1021,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_rot_log_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex2_sel_rot_log_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex1_act), .act(ex1_act),
@ -1006,7 +1040,8 @@ module tri_st_rot(
); );


tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sh_word_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) ex3_sh_word_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_act_q), .act(ex2_act_q),
@ -1030,7 +1065,8 @@ module tri_st_rot(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_act_unqiue), .act(ex2_act_unqiue),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(func_sl_force), .force_t(func_sl_force),
.thold_b(func_sl_thold_0_b), .thold_b(func_sl_thold_0_b),
.delay_lclkr(delay_lclkr_dc), .delay_lclkr(delay_lclkr_dc),
@ -1083,7 +1119,8 @@ module tri_st_rot(
//------------------------------------------------------------------- //-------------------------------------------------------------------


tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sra_se_latch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ex3_sra_se_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(ex2_act_q), .act(ex2_act_q),
@ -1102,7 +1139,8 @@ module tri_st_rot(




tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dummy_latch( tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dummy_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(1'b0), .act(1'b0),

@ -1,281 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri Array Wrapper
//
//*****************************************************************************

// sim version, clk1x

`include "tri_a2o.vh"

module tri_128x16_1r1w_1(
vdd,
vcs,
gnd,
nclk,
rd_act,
wr_act,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
func_scan_in,
func_scan_out,
lcb_sg_0,
lcb_sl_thold_0_b,
lcb_time_sl_thold_0,
lcb_abst_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_repr_sl_thold_0,
time_scan_in,
time_scan_out,
abst_scan_in,
abst_scan_out,
repr_scan_in,
repr_scan_out,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
bw,
wr_adr,
rd_adr,
di,
dout
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 16; // bitwidth of ports
parameter ways = 1; // number of ways

// POWER PINS
inout vdd;
inout vcs;
inout gnd;

input [0:`NCLK_WIDTH-1] nclk;

input rd_act;
input wr_act;

// DC TEST PINS
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;

input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input func_scan_in;
output func_scan_out;

input lcb_sg_0;
input lcb_sl_thold_0_b;
input lcb_time_sl_thold_0;
input lcb_abst_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_repr_sl_thold_0;
input time_scan_in;
output time_scan_out;
input abst_scan_in;
output abst_scan_out;
input repr_scan_in;
output repr_scan_out;

input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:6] abist_wr_adr;
input wr_abst_act;
input [0:6] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

input [0:15] bw;
input [0:6] wr_adr;
input [0:6] rd_adr;
input [0:15] di;

output [0:15] dout;

// tri_128x16_1r1w_1

// Configuration Statement for NCsim
//for all:ramb16_s36_s36 use entity unisim.RAMB16_S36_S36;

wire clk;
wire [0:8] b0addra;
wire [0:8] b0addrb;
wire wea;
wire web;
wire wren_a;
wire [0:15] w_data_in_0;
wire [0:15] r_data_out_0_bram;

// Latches
reg reset_q;
reg [0:15] r_data_out_1_q;


(* analysis_not_referenced="true" *)
wire unused;

// sim array
reg [0:15] mem[0:127];

integer i;
initial begin
for (i = 0; i < 128; i = i + 1)
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar j;
for (j = 0; j < 128; j=j+1) begin: loc
wire [0:15] dat;
assign dat = mem[j][0:15];
end
endgenerate

assign clk = nclk[0];

always @(posedge clk)
begin: rlatch
reset_q <= nclk[1];
end

assign b0addra[2:8] = wr_adr;
assign b0addrb[2:8] = rd_adr;

// Unused Address Bits
assign b0addra[0:1] = 2'b00;
assign b0addrb[0:1] = 2'b00;

// port a is a read-modify-write port
assign wren_a = (bw != 0) & wr_act;
assign wea = wren_a;
assign web = 1'b0;
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];

always @(posedge clk) begin

r_data_out_1_q <= mem[b0addrb];
if (wea) begin
mem[b0addra] <= w_data_in_0;
end

end

assign r_data_out_0_bram = mem[b0addra];
assign dout = r_data_out_1_q[0:15];

assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in;
assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act};
endmodule

@ -1,157 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri-Lam Array Wrapper
//
//*****************************************************************************

// sim version, clk1x

`include "tri_a2o.vh"

module tri_144x78_2r4w(
// Inputs
// Power
inout vdd,
inout gnd,
// Clock & Scan
input [0:`NCLK_WIDTH-1] nclk,

//-------------------------------------------------------------------
// Pervasive
//-------------------------------------------------------------------
input delay_lclkr_dc,
input mpw1_dc_b,
input mpw2_dc_b,
input func_sl_force,
input func_sl_thold_0_b,
input func_slp_sl_force,
input func_slp_sl_thold_0_b,
input sg_0,
input scan_in,
output scan_out,

//-------------------------------------------------------------------
// Read Port
//-------------------------------------------------------------------
input r_late_en_1,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_1,
output [64-`GPR_WIDTH:77] r_data_out_1,
input r_late_en_2,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r_addr_in_2,
output [64-`GPR_WIDTH:77] r_data_out_2,

//-------------------------------------------------------------------
// Write Port
//-------------------------------------------------------------------
input w_late_en_1,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_1,
input [64-`GPR_WIDTH:77] w_data_in_1,
input w_late_en_2,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_2,
input [64-`GPR_WIDTH:77] w_data_in_2,
input w_late_en_3,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_3,
input [64-`GPR_WIDTH:77] w_data_in_3,
input w_late_en_4,
input [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] w_addr_in_4,
input [64-`GPR_WIDTH:77] w_data_in_4
);

wire unused;

// sim array
reg [64-`GPR_WIDTH:77] mem[0:143];

reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r1a_d;
reg [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_q;
wire [0:`GPR_POOL_ENC+`THREADS_POOL_ENC-1] r2a_d;

reg [64-`GPR_WIDTH:77] r1d_q;
wire [64-`GPR_WIDTH:77] r1d_d;
reg [64-`GPR_WIDTH:77] r2d_q;
wire [64-`GPR_WIDTH:77] r2d_d;

integer i;
initial begin
for (i = 0; i < 144; i = i + 1)
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar j;
for (j = 0; j < 144; j=j+1) begin: loc
wire [64-`GPR_WIDTH:63] dat;
wire [0:7] par;
// 4b0
assign dat = mem[j][64-`GPR_WIDTH:63];
assign par = mem[j][64:63 + `GPR_WIDTH/8];
end
endgenerate

assign r1a_d = r_addr_in_1;
assign r2a_d = r_addr_in_2;

always @(posedge nclk[0]) begin

r1a_q <= r1a_d;
r2a_q <= r2a_d;

r1d_q <= r1d_d;
r2d_q <= r2d_d;

if (w_late_en_1) begin
mem[w_addr_in_1] <= w_data_in_1;
end
if (w_late_en_2) begin
mem[w_addr_in_2] <= w_data_in_2;
end
if (w_late_en_3) begin
mem[w_addr_in_3] <= w_data_in_3;
end
if (w_late_en_4) begin
mem[w_addr_in_4] <= w_data_in_4;
end

end

// r_late_en_x are unused in original also
assign r1d_d = mem[r1a_q];
assign r2d_d = mem[r2a_q];

assign r_data_out_1 = r1d_q;
assign r_data_out_2 = r2d_q;

assign unused = | {func_slp_sl_force, func_slp_sl_thold_0_b};

endmodule

@ -1,273 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri Array Wrapper
//
//*****************************************************************************

// sim version, clk1x

`include "tri_a2o.vh"

module tri_512x16_1r1w_1(
vdd,
vcs,
gnd,
nclk,
rd_act,
wr_act,
lcb_d_mode_dc,
lcb_clkoff_dc_b,
lcb_mpw1_dc_b,
lcb_mpw2_dc_b,
lcb_delay_lclkr_dc,
ccflush_dc,
scan_dis_dc_b,
scan_diag_dc,
func_scan_in,
func_scan_out,
lcb_sg_0,
lcb_sl_thold_0_b,
lcb_time_sl_thold_0,
lcb_abst_sl_thold_0,
lcb_ary_nsl_thold_0,
lcb_repr_sl_thold_0,
time_scan_in,
time_scan_out,
abst_scan_in,
abst_scan_out,
repr_scan_in,
repr_scan_out,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
bw,
wr_adr,
rd_adr,
di,
dout
);
parameter addressable_ports = 128; // number of addressable register in this array
parameter addressbus_width = 9; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
parameter port_bitwidth = 16; // bitwidth of ports
parameter ways = 1; // number of ways

// POWER PINS
inout vdd;
inout vcs;
inout gnd;

input [0:`NCLK_WIDTH-1] nclk;

input rd_act;
input wr_act;

// DC TEST PINS
input lcb_d_mode_dc;
input lcb_clkoff_dc_b;
input [0:4] lcb_mpw1_dc_b;
input lcb_mpw2_dc_b;
input [0:4] lcb_delay_lclkr_dc;

input ccflush_dc;
input scan_dis_dc_b;
input scan_diag_dc;
input func_scan_in;
output func_scan_out;

input lcb_sg_0;
input lcb_sl_thold_0_b;
input lcb_time_sl_thold_0;
input lcb_abst_sl_thold_0;
input lcb_ary_nsl_thold_0;
input lcb_repr_sl_thold_0;
input time_scan_in;
output time_scan_out;
input abst_scan_in;
output abst_scan_out;
input repr_scan_in;
output repr_scan_out;

input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:6] abist_wr_adr;
input wr_abst_act;
input [0:6] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

input [0:15] bw;
input [0:8] wr_adr;
input [0:8] rd_adr;
input [0:15] di;

output [0:15] dout;

wire clk;
wire [0:8] b0addra;
wire [0:8] b0addrb;
wire wea;
wire web;
wire wren_a;
wire [0:15] w_data_in_0;
wire [0:15] r_data_out_0_bram;

// Latches
reg reset_q;
reg [0:15] r_data_out_1_q;


(* analysis_not_referenced="true" *)
wire unused;

// sim array
reg [0:15] mem[0:511];

integer i;
initial begin
for (i = 0; i < 512; i = i + 1)
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar j;
for (j = 0; j < 512; j=j+1) begin: loc
wire [0:15] dat;
assign dat = mem[j][0:15];
end
endgenerate

assign clk = nclk[0];

always @(posedge clk)
begin: rlatch
reset_q <= nclk[1];
end

//wtf do they use diff addresses?
assign b0addra[0:8] = wr_adr;
assign b0addrb[0:8] = rd_adr;

// port a is a read-modify-write port
assign wren_a = (bw != 0) & wr_act;
assign wea = wren_a;
assign web = 1'b0;
assign w_data_in_0[0] = bw[0] ? di[0] : r_data_out_0_bram[0];
assign w_data_in_0[1] = bw[1] ? di[1] : r_data_out_0_bram[1];
assign w_data_in_0[2] = bw[2] ? di[2] : r_data_out_0_bram[2];
assign w_data_in_0[3] = bw[3] ? di[3] : r_data_out_0_bram[3];
assign w_data_in_0[4] = bw[4] ? di[4] : r_data_out_0_bram[4];
assign w_data_in_0[5] = bw[5] ? di[5] : r_data_out_0_bram[5];
assign w_data_in_0[6] = bw[6] ? di[6] : r_data_out_0_bram[6];
assign w_data_in_0[7] = bw[7] ? di[7] : r_data_out_0_bram[7];
assign w_data_in_0[8] = bw[8] ? di[8] : r_data_out_0_bram[8];
assign w_data_in_0[9] = bw[9] ? di[9] : r_data_out_0_bram[9];
assign w_data_in_0[10] = bw[10] ? di[10] : r_data_out_0_bram[10];
assign w_data_in_0[11] = bw[11] ? di[11] : r_data_out_0_bram[11];
assign w_data_in_0[12] = bw[12] ? di[12] : r_data_out_0_bram[12];
assign w_data_in_0[13] = bw[13] ? di[13] : r_data_out_0_bram[13];
assign w_data_in_0[14] = bw[14] ? di[14] : r_data_out_0_bram[14];
assign w_data_in_0[15] = bw[15] ? di[15] : r_data_out_0_bram[15];

always @(posedge clk) begin

r_data_out_1_q <= mem[b0addrb];
if (wea) begin
mem[b0addra] <= w_data_in_0;
end

end

assign r_data_out_0_bram = mem[b0addra];
assign dout = r_data_out_1_q[0:15];

assign func_scan_out = func_scan_in;
assign time_scan_out = time_scan_in;
assign abst_scan_out = abst_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = |{vdd, vcs, gnd, nclk, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_mpw1_dc_b, lcb_mpw2_dc_b,
lcb_delay_lclkr_dc, ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_sg_0, lcb_sl_thold_0_b,
lcb_time_sl_thold_0, lcb_abst_sl_thold_0, lcb_ary_nsl_thold_0, lcb_repr_sl_thold_0,
abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, wr_abst_act, abist_rd0_adr, rd0_abst_act,
tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp,
lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata,
pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc, rd_act};
endmodule

@ -1,245 +0,0 @@
// © IBM Corp. 2022
// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
// the terms below; you may not use the files in this repository except in
// compliance with the License as modified.
// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
//
// Modified Terms:
//
// 1) For the purpose of the patent license granted to you in Section 3 of the
// License, the "Work" hereby includes implementations of the work of authorship
// in physical form.
//
// 2) Notwithstanding any terms to the contrary in the License, any licenses
// necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA.
//
// Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License.
//
// Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org.

`timescale 1 ns / 1 ns

//*****************************************************************************
// Description: Tri-Lam Array Wrapper
//
//*****************************************************************************

// sim version, clk1x

`include "tri_a2o.vh"

module tri_64x72_1r1w(
vdd,
vcs,
gnd,
nclk,
sg_0,
abst_sl_thold_0,
ary_nsl_thold_0,
time_sl_thold_0,
repr_sl_thold_0,
rd0_act,
rd0_adr,
do0,
wr_act,
wr_adr,
di,
abst_scan_in,
abst_scan_out,
time_scan_in,
time_scan_out,
repr_scan_in,
repr_scan_out,
scan_dis_dc_b,
scan_diag_dc,
ccflush_dc,
clkoff_dc_b,
d_mode_dc,
mpw1_dc_b,
mpw2_dc_b,
delay_lclkr_dc,
lcb_bolt_sl_thold_0,
pc_bo_enable_2,
pc_bo_reset,
pc_bo_unload,
pc_bo_repair,
pc_bo_shdata,
pc_bo_select,
bo_pc_failout,
bo_pc_diagloop,
tri_lcb_mpw1_dc_b,
tri_lcb_mpw2_dc_b,
tri_lcb_delay_lclkr_dc,
tri_lcb_clkoff_dc_b,
tri_lcb_act_dis_dc,
abist_di,
abist_bw_odd,
abist_bw_even,
abist_wr_adr,
wr_abst_act,
abist_rd0_adr,
rd0_abst_act,
tc_lbist_ary_wrt_thru_dc,
abist_ena_1,
abist_g8t_rd0_comp_ena,
abist_raw_dc_b,
obs0_abist_cmp
);

// Power
(* analysis_not_referenced="true" *)
inout vdd;
(* analysis_not_referenced="true" *)
inout vcs;
(* analysis_not_referenced="true" *)
inout gnd;

// Clock Pervasive
input [0:`NCLK_WIDTH-1] nclk;
input sg_0;
input abst_sl_thold_0;
input ary_nsl_thold_0;
input time_sl_thold_0;
input repr_sl_thold_0;

// Reads
input rd0_act;
input [0:5] rd0_adr;
output [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] do0;

// Writes
input wr_act;
input [0:5] wr_adr;
input [64-`GPR_WIDTH:72-(64/`GPR_WIDTH)] di;

// Scan
input abst_scan_in;
output abst_scan_out;
input time_scan_in;
output time_scan_out;
input repr_scan_in;
output repr_scan_out;

// Misc Pervasive
input scan_dis_dc_b;
input scan_diag_dc;
input ccflush_dc;
input clkoff_dc_b;
input d_mode_dc;
input [0:4] mpw1_dc_b;
input mpw2_dc_b;
input [0:4] delay_lclkr_dc;

// BOLT-ON
input lcb_bolt_sl_thold_0;
input pc_bo_enable_2; // general bolt-on enable
input pc_bo_reset; // reset
input pc_bo_unload; // unload sticky bits
input pc_bo_repair; // execute sticky bit decode
input pc_bo_shdata; // shift data for timing write and diag loop
input pc_bo_select; // select for mask and hier writes
output bo_pc_failout; // fail/no-fix reg
output bo_pc_diagloop;
input tri_lcb_mpw1_dc_b;
input tri_lcb_mpw2_dc_b;
input tri_lcb_delay_lclkr_dc;
input tri_lcb_clkoff_dc_b;
input tri_lcb_act_dis_dc;

// ABIST
input [0:3] abist_di;
input abist_bw_odd;
input abist_bw_even;
input [0:5] abist_wr_adr;
input wr_abst_act;
input [0:5] abist_rd0_adr;
input rd0_abst_act;
input tc_lbist_ary_wrt_thru_dc;
input abist_ena_1;
input abist_g8t_rd0_comp_ena;
input abist_raw_dc_b;
input [0:3] obs0_abist_cmp;

wire sreset;
wire [0:71] tidn;

(* analysis_not_referenced="true" *)
wire unused;

// sim array
reg [0:63] mem[0:71];

reg r0_e_q;
wire r0_e_d;
reg [0:5] r0_a_q;
wire [0:5] r0_a_d;
reg [0:71] r0_d_q;
wire [0:71] r0_d_d;

reg w0_e_q;
wire w0_e_d;
reg [0:5] w0_a_q;
wire [0:5] w0_a_d;
reg [0:71] w0_d_q;
wire [0:71] w0_d_d;

integer i;
initial begin
for (i = 0; i < 64; i = i + 1)
mem[i] = 0;
end

//wtf:icarus $dumpvars cannot dump a vpiMemory
generate
genvar j;
for (j = 0; j < 63; j=j+1) begin: loc
wire [0:63] dat;
wire [0:7] par;
assign dat = mem[j][0:63];
assign par = mem[j][0:7];
end
endgenerate

generate

assign clk = nclk[0];
assign sreset = nclk[1];

always @(posedge clk) begin

r0_e_q <= rd0_act;
r0_a_q <= rd0_adr;
r0_d_q <= r0_e_q ? mem[r0_a_q] : 0;

if (w0_e_q) begin
mem[w0_a_q] <= w0_d_q;
end
w0_e_q <= wr_act;
w0_a_q <= wr_adr;
w0_d_q <= di;

end

assign do0 = r0_d_q;

assign abst_scan_out = abst_scan_in;
assign time_scan_out = time_scan_in;
assign repr_scan_out = repr_scan_in;

assign bo_pc_failout = 1'b0;
assign bo_pc_diagloop = 1'b0;

assign unused = | ({nclk[3:`NCLK_WIDTH-1], sg_0, abst_sl_thold_0, ary_nsl_thold_0, time_sl_thold_0, repr_sl_thold_0, scan_dis_dc_b, scan_diag_dc, ccflush_dc, clkoff_dc_b, d_mode_dc, mpw1_dc_b, mpw2_dc_b, delay_lclkr_dc, abist_di, abist_bw_odd, abist_bw_even, abist_wr_adr, abist_rd0_adr, wr_abst_act, rd0_abst_act, tc_lbist_ary_wrt_thru_dc, abist_ena_1, abist_g8t_rd0_comp_ena, abist_raw_dc_b, obs0_abist_cmp, rd0_act, tidn, lcb_bolt_sl_thold_0, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc});

endgenerate

endmodule

File diff suppressed because it is too large Load Diff

File diff suppressed because it is too large Load Diff

@ -44,7 +44,8 @@ module c(
// inout vcs, // inout vcs,
// inout vdd, // inout vdd,
// inout gnd, // inout gnd,
input[0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input scan_in, input scan_in,
output scan_out, output scan_out,


@ -191,8 +192,11 @@ module c(


); );



`ifndef FLOAT_TYPE
parameter float_type = 1; parameter float_type = 1;
`else
parameter float_type = `FLOAT_TYPE;
`endif


// I$ // I$
// Cache inject // Cache inject
@ -1816,7 +1820,8 @@ module c(
//.vcs(vcs), //.vcs(vcs),
//.vdd(vdd), //.vdd(vdd),
//.gnd(gnd), //.gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_sg_3(rp_iu_sg_3), .pc_iu_sg_3(rp_iu_sg_3),
.pc_iu_fce_3(rp_iu_fce_3), .pc_iu_fce_3(rp_iu_fce_3),
.pc_iu_func_slp_sl_thold_3(rp_iu_func_slp_sl_thold_3), .pc_iu_func_slp_sl_thold_3(rp_iu_func_slp_sl_thold_3),
@ -2514,7 +2519,8 @@ module c(
//------------------------------------------------------------------- //-------------------------------------------------------------------
// Clocks & Power // Clocks & Power
//------------------------------------------------------------------- //-------------------------------------------------------------------
.nclk(nclk), .clk(clk),
.rst(rst),
// .vcs(vcs), // .vcs(vcs),
// .vdd(vdd), // .vdd(vdd),
// .gnd(gnd), // .gnd(gnd),
@ -3159,6 +3165,8 @@ module c(


rv rv
rv0( rv0(
.clk(clk),
.rst(rst),


//------------------------------------------------------------------- //-------------------------------------------------------------------
// Instructions from IU // Instructions from IU
@ -3637,7 +3645,6 @@ module c(
//------------------------------------------------------------------- //-------------------------------------------------------------------
//.vdd(vdd), //.vdd(vdd),
//.gnd(gnd), //.gnd(gnd),
.nclk(nclk),


.rp_rv_ccflush_dc(rp_rv_ccflush_dc), .rp_rv_ccflush_dc(rp_rv_ccflush_dc),
.rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3), .rp_rv_func_sl_thold_3(rp_rv_func_sl_thold_3),
@ -3654,6 +3661,9 @@ module c(


lq lq
lq0( lq0(
.clk(clk),
.rst(rst),

//-------------------------------------------------------------- //--------------------------------------------------------------
// SPR Interface // SPR Interface
//-------------------------------------------------------------- //--------------------------------------------------------------
@ -4088,7 +4098,6 @@ module c(
//.vcs(vcs), //.vcs(vcs),
//.vdd(vdd), //.vdd(vdd),
//.gnd(gnd), //.gnd(gnd),
.nclk(nclk),


//--Thold inputs //--Thold inputs
.pc_lq_init_reset(pc_lq_init_reset), .pc_lq_init_reset(pc_lq_init_reset),
@ -4166,13 +4175,13 @@ module c(
.func_scan_out(scan_out_lq) .func_scan_out(scan_out_lq)
); );


// 6=64-bit model, 5=32-bit model
mmq mmq
mmu0( mmu0(
// .vcs(vcs), // .vcs(vcs),
// .vdd(vdd), // .vdd(vdd),
// .gnd(gnd), // .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),


.tc_ac_ccflush_dc(rp_mm_ccflush_dc), .tc_ac_ccflush_dc(rp_mm_ccflush_dc),
.tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b), .tc_ac_scan_dis_dc_b(an_ac_scan_dis_dc_b),
@ -4456,12 +4465,12 @@ module c(


); );



c_fu_pc #(.float_type(float_type)) c_fu_pc #(.float_type(float_type))
fupc( fupc(
// .vdd(vdd), // .vdd(vdd),
// .gnd(gnd), // .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),


.fu_debug_bus_in(fu_debug_bus_in), .fu_debug_bus_in(fu_debug_bus_in),
.fu_debug_bus_out(fu_debug_bus_out), .fu_debug_bus_out(fu_debug_bus_out),
@ -4853,7 +4862,8 @@ module c(
perv_rp( perv_rp(
// .vdd(vdd), // .vdd(vdd),
// .gnd(gnd), // .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),


//CLOCK CONTROLS //CLOCK CONTROLS
//Top level clock controls //Top level clock controls

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -36,30 +36,35 @@
//* //*
//***************************************************************************** //*****************************************************************************


(* recursive_synthesis=0 *) //wtf: move pcq to top-level? keep this as c_fu to do the float_type generate

`include "tri_a2o.vh"


`ifndef FLOAT_TYPE
`define FLOAT_TYPE 1
`endif


module c_fu_pc( module c_fu_pc(
`include "tri_a2o.vh"
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// Common I/O Ports // Common I/O Ports
// ---------------------------------------------------------------------- // ----------------------------------------------------------------------
// inout vdd, // inout vdd,
// inout gnd, // inout gnd,
(* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,


input [0:31] fu_debug_bus_in, input [0:31] fu_debug_bus_in,
output [0:31] fu_debug_bus_out, output [0:31] fu_debug_bus_out,
input [0:3] fu_coretrace_ctrls_in, input [0:3] fu_coretrace_ctrls_in,
output [0:3] fu_coretrace_ctrls_out, output [0:3] fu_coretrace_ctrls_out,
input [0:4*`THREADS-1] fu_event_bus_in, input [0:4*`THREADS-1] fu_event_bus_in,
output [0:4*`THREADS-1] fu_event_bus_out, output [0:4*`THREADS-1] fu_event_bus_out,


input [0:31] pc_debug_bus_in, input [0:31] pc_debug_bus_in,
output [0:31] pc_debug_bus_out, output [0:31] pc_debug_bus_out,
input [0:3] pc_coretrace_ctrls_in, input [0:3] pc_coretrace_ctrls_in,
output [0:3] pc_coretrace_ctrls_out, output [0:3] pc_coretrace_ctrls_out,


(* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in (* pin_data="PIN_FUNCTION=/SCAN_IN/" *) // scan_in
input fu_gptr_scan_in, input fu_gptr_scan_in,
@ -466,8 +471,7 @@ module c_fu_pc(




// ###################### CONSTANTS ###################### -- // ###################### CONSTANTS ###################### --
parameter float_type = 1; parameter float_type = `FLOAT_TYPE;





// ####################### SIGNALS ####################### -- // ####################### SIGNALS ####################### --
@ -516,7 +520,8 @@ module c_fu_pc(
pc0( pc0(
// .vdd(vdd), // .vdd(vdd),
// .gnd(gnd), // .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
//SCOM Satellite //SCOM Satellite
.an_ac_scom_sat_id(an_ac_scom_sat_id), .an_ac_scom_sat_id(an_ac_scom_sat_id),
.an_ac_scom_dch(an_ac_scom_dch), .an_ac_scom_dch(an_ac_scom_dch),
@ -795,7 +800,8 @@ module c_fu_pc(
//.gnd(gnd), //.gnd(gnd),
//.vcs(vcs), //.vcs(vcs),
//.vdd(vdd), //.vdd(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),


.debug_bus_in(fu_debug_bus_in), .debug_bus_in(fu_debug_bus_in),
.debug_bus_out(fu_debug_bus_out), .debug_bus_out(fu_debug_bus_out),
@ -1009,17 +1015,17 @@ module c_fu_pc(
assign axu0_rv_itag_vld = {`THREADS{1'b0}}; assign axu0_rv_itag_vld = {`THREADS{1'b0}};
assign axu1_rv_itag_vld = {`THREADS{1'b0}}; assign axu1_rv_itag_vld = {`THREADS{1'b0}};


assign fu_slowspr_val_out = fu_slowspr_val_in; assign fu_slowspr_val_out = fu_slowspr_val_in;
assign fu_slowspr_rw_out = fu_slowspr_rw_in; assign fu_slowspr_rw_out = fu_slowspr_rw_in;
assign fu_slowspr_etid_out = fu_slowspr_etid_in; assign fu_slowspr_etid_out = fu_slowspr_etid_in;
assign fu_slowspr_addr_out = fu_slowspr_addr_in; assign fu_slowspr_addr_out = fu_slowspr_addr_in;
assign fu_slowspr_data_out = fu_slowspr_data_in; assign fu_slowspr_data_out = fu_slowspr_data_in;
assign fu_slowspr_done_out = fu_slowspr_done_in; assign fu_slowspr_done_out = fu_slowspr_done_in;


assign fu_debug_bus_out = fu_debug_bus_in; assign fu_debug_bus_out = fu_debug_bus_in;
assign fu_coretrace_ctrls_out = fu_coretrace_ctrls_in; assign fu_coretrace_ctrls_out = fu_coretrace_ctrls_in;


assign fu_event_bus_out = fu_event_bus_in; assign fu_event_bus_out = fu_event_bus_in;


assign fu_pc_err_regfile_parity = {`THREADS{1'b0}}; assign fu_pc_err_regfile_parity = {`THREADS{1'b0}};
assign fu_pc_err_regfile_ue = {`THREADS{1'b0}}; assign fu_pc_err_regfile_ue = {`THREADS{1'b0}};

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -37,7 +37,8 @@ module c_perv_rp(


// inout vdd, // inout vdd,
// inout gnd, // inout gnd,
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
//CLOCK CONTROLS //CLOCK CONTROLS
//Top level clock controls //Top level clock controls
input an_ac_ccflush_dc, input an_ac_ccflush_dc,
@ -327,7 +328,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(6)) perv_4to3_reg( tri_plat #(.WIDTH(6)) perv_4to3_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4, .din({pc_rp_func_sl_thold_4, pc_rp_func_slp_sl_thold_4, pc_rp_gptr_sl_thold_4,
@ -340,7 +342,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(6)) perv_3to2_reg( tri_plat #(.WIDTH(6)) perv_3to2_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int, .din({func_sl_thold_3_int, func_slp_sl_thold_3_int, gptr_sl_thold_3_int,
@ -353,7 +356,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(6)) perv_2to1_reg( tri_plat #(.WIDTH(6)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2, .din({func_sl_thold_2, func_slp_sl_thold_2, gptr_sl_thold_2,
@ -366,7 +370,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(6)) perv_1to0_reg( tri_plat #(.WIDTH(6)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1, .din({func_sl_thold_1, func_slp_sl_thold_1, gptr_sl_thold_1,
@ -381,7 +386,8 @@ module c_perv_rp(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.sg(sg_0), .sg(sg_0),
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(gptr_scan_in), .scan_in(gptr_scan_in),
.scan_diag_dc(scan_diag_dc), .scan_diag_dc(scan_diag_dc),
.thold(gptr_sl_thold_0), .thold(gptr_sl_thold_0),
@ -432,7 +438,8 @@ module c_perv_rp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.delay_lclkr(delay_lclkr[0]), .delay_lclkr(delay_lclkr[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(slat_force), .force_t(slat_force),
.thold_b(func_slat_thold_b), .thold_b(func_slat_thold_b),
.dclk(func_slat_d2clk), .dclk(func_slat_d2clk),
@ -443,7 +450,8 @@ module c_perv_rp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.delay_lclkr(delay_lclkr[0]), .delay_lclkr(delay_lclkr[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(slat_force), .force_t(slat_force),
.thold_b(abst_slat_thold_b), .thold_b(abst_slat_thold_b),
.dclk(abst_slat_d2clk), .dclk(abst_slat_d2clk),
@ -454,7 +462,8 @@ module c_perv_rp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.delay_lclkr(delay_lclkr[0]), .delay_lclkr(delay_lclkr[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(slat_force), .force_t(slat_force),
.thold_b(cfg_slat_thold_b), .thold_b(cfg_slat_thold_b),
.dclk(cfg_slat_d2clk), .dclk(cfg_slat_d2clk),
@ -468,7 +477,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(6)) pcq_lvl8to7( tri_plat #(.WIDTH(6)) pcq_lvl8to7(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(an_ac_ccflush_dc), .flush(an_ac_ccflush_dc),


.din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8, .din({rtim_sl_thold_8, func_sl_thold_8, func_nsl_thold_8,
@ -489,7 +499,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(16)) iu_clkstg_4to3( tri_plat #(.WIDTH(16)) iu_clkstg_4to3(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
@ -508,7 +519,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(15)) rv_clkstg_4to3( tri_plat #(.WIDTH(15)) rv_clkstg_4to3(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
@ -527,7 +539,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(16)) xu_clkstg_4to3( tri_plat #(.WIDTH(16)) xu_clkstg_4to3(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
@ -546,7 +559,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(16)) lq_clkstg_4to3( tri_plat #(.WIDTH(16)) lq_clkstg_4to3(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
@ -565,7 +579,8 @@ module c_perv_rp(
tri_plat #(.WIDTH(15)) mm_clkstg_4to3( tri_plat #(.WIDTH(15)) mm_clkstg_4to3(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(pc_rp_ccflush_out_dc), .flush(pc_rp_ccflush_out_dc),


.din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4, .din({pc_rp_gptr_sl_thold_4, pc_rp_time_sl_thold_4, pc_rp_repr_sl_thold_4,
@ -642,7 +657,8 @@ module c_perv_rp(
tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp( tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(1'b1), .act(1'b1),
.thold_b(func_slp_sl_thold_0_b), .thold_b(func_slp_sl_thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -674,7 +690,8 @@ module c_perv_rp(
tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp( tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(1'b1), .act(1'b1),
.thold_b(func_slp_sl_thold_0_b), .thold_b(func_slp_sl_thold_0_b),
.sg(sg_0), .sg(sg_0),

@ -90,7 +90,8 @@ module fu(
lq_rv_itag0_spec, lq_rv_itag0_spec,
lq_rv_itag0_vld, lq_rv_itag0_vld,
lq_rv_itag1_restart, lq_rv_itag1_restart,
nclk, clk,
rst,
pc_fu_abist_di_0, pc_fu_abist_di_0,
pc_fu_abist_di_1, pc_fu_abist_di_1,
pc_fu_abist_ena_dc, pc_fu_abist_ena_dc,
@ -238,6 +239,8 @@ module fu(
// parameter UCODE_ENTRIES_ENC = 3; // parameter UCODE_ENTRIES_ENC = 3;
// parameter REGMODE = 6; //32 or 64 bit mode // parameter REGMODE = 6; //32 or 64 bit mode
//INPUTS //INPUTS
input clk;
input rst;
input abst_scan_in; input abst_scan_in;
input an_ac_lbist_en_dc; input an_ac_lbist_en_dc;
input bcfg_scan_in; input bcfg_scan_in;
@ -300,8 +303,6 @@ module fu(
input lq_rv_itag0_spec; input lq_rv_itag0_spec;
input lq_rv_itag0_vld; input lq_rv_itag0_vld;
input lq_rv_itag1_restart; input lq_rv_itag1_restart;
(* PIN_DATA="PIN_FUNCTION=/G_CLK/CAP_LIMIT=/99999/" *) // nclk
input [0:`NCLK_WIDTH-1] nclk;
input [0:3] pc_fu_abist_di_0; input [0:3] pc_fu_abist_di_0;
input [0:3] pc_fu_abist_di_1; input [0:3] pc_fu_abist_di_1;
input pc_fu_abist_ena_dc; input pc_fu_abist_ena_dc;
@ -766,7 +767,8 @@ module fu(
fu_perv prv( fu_perv prv(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_fu_sg_3(pc_fu_sg_3), .pc_fu_sg_3(pc_fu_sg_3),
.pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3), .pc_fu_abst_sl_thold_3(pc_fu_abst_sl_thold_3),
.pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3), .pc_fu_func_sl_thold_3(pc_fu_func_sl_thold_3),
@ -803,7 +805,8 @@ module fu(
// Floating Point Register, ex0 // Floating Point Register, ex0


fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC)) fpr( fu_fpr #( .fpr_pool(`FPR_POOL * `THREADS), .fpr_pool_enc(`FPR_POOL_ENC + `THREAD_POOL_ENC), .axu_spare_enc(`AXU_SPARE_ENC)) fpr(
.nclk(nclk), .clk(clk),
.rst(rst),
.clkoff_b(clkoff_dc_b), .clkoff_b(clkoff_dc_b),
.act_dis(act_dis), .act_dis(act_dis),
.flush(pc_fu_ccflush_dc), .flush(pc_fu_ccflush_dc),
@ -924,6 +927,8 @@ module fu(
fu_sto sto( fu_sto sto(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.clk(clk),
.rst(rst),
.clkoff_b(clkoff_dc_b), .clkoff_b(clkoff_dc_b),
.act_dis(act_dis), .act_dis(act_dis),
.flush(pc_fu_ccflush_dc), .flush(pc_fu_ccflush_dc),
@ -933,7 +938,6 @@ module fu(
.sg_1(sg_1[1]), .sg_1(sg_1[1]),
.thold_1(func_sl_thold_1[1]), .thold_1(func_sl_thold_1[1]),
.fpu_enable(fpu_enable), .fpu_enable(fpu_enable),
.nclk(nclk),
.f_sto_si(f_sto_si), .f_sto_si(f_sto_si),
.f_sto_so(f_sto_so), .f_sto_so(f_sto_so),
.f_dcd_ex1_sto_act(f_dcd_ex1_sto_act), .f_dcd_ex1_sto_act(f_dcd_ex1_sto_act),
@ -955,10 +959,9 @@ module fu(


assign fpu_enable = f_dcd_msr_fp_act; assign fpu_enable = f_dcd_msr_fp_act;





fu_mad #( .THREADS(`THREADS)) mad( fu_mad #( .THREADS(`THREADS)) mad(
.clk(clk),
.rst(rst),
.f_dcd_ex7_cancel(f_dcd_ex7_cancel), .f_dcd_ex7_cancel(f_dcd_ex7_cancel),
.f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0), .f_dcd_ex1_bypsel_a_res0(f_dcd_ex1_bypsel_a_res0),
.f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1), .f_dcd_ex1_bypsel_a_res1(f_dcd_ex1_bypsel_a_res1),
@ -1203,8 +1206,7 @@ module fu(
.sg_1(sg_1[0]), .sg_1(sg_1[0]),
.thold_1(func_sl_thold_1[0]), .thold_1(func_sl_thold_1[0]),
.fpu_enable(fpu_enable), .fpu_enable(fpu_enable),
.f_dcd_ex1_act(f_dcd_ex1_mad_act), .f_dcd_ex1_act(f_dcd_ex1_mad_act)
.nclk(nclk)
); );


//Needed for RTX //Needed for RTX
@ -1221,6 +1223,8 @@ module fu(


fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC)) dcd( fu_dcd #(.ITAG_SIZE_ENC(`ITAG_SIZE_ENC), .EFF_IFAR(`EFF_IFAR), .REGMODE(`REGMODE), .THREAD_POOL_ENC(`THREAD_POOL_ENC), .CR_POOL_ENC(`CR_POOL_ENC)) dcd(
// INPUTS // INPUTS
.clk(clk),
.rst(rst),
.act_dis(act_dis), .act_dis(act_dis),
.bcfg_scan_in(bcfg_scan_in), .bcfg_scan_in(bcfg_scan_in),
.ccfg_scan_in(ccfg_scan_in), .ccfg_scan_in(ccfg_scan_in),
@ -1301,7 +1305,6 @@ module fu(
.iu_fu_rf0_instr_match(iu_fu_rf0_instr_match), .iu_fu_rf0_instr_match(iu_fu_rf0_instr_match),
.mpw1_b(mpw1_dc_b[0:9]), .mpw1_b(mpw1_dc_b[0:9]),
.mpw2_b(mpw2_dc_b[0:1]), .mpw2_b(mpw2_dc_b[0:1]),
.nclk(nclk),
.pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls), .pc_fu_debug_mux_ctrls(pc_fu_debug_mux_ctrls),
.pc_fu_event_count_mode(pc_fu_event_count_mode), .pc_fu_event_count_mode(pc_fu_event_count_mode),
.pc_fu_ram_active(pc_fu_ram_active), .pc_fu_ram_active(pc_fu_ram_active),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_add( module fu_add(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_add(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_add_si, f_add_si,
f_add_so, f_add_so,
ex2_act_b, ex2_act_b,
@ -74,6 +75,9 @@ module fu_add(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -83,7 +87,6 @@ module fu_add(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_add_si; //perv input f_add_si; //perv
output f_add_so; //perv output f_add_so; //perv
@ -226,7 +229,8 @@ module fu_add(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -236,7 +240,8 @@ module fu_add(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -268,7 +273,8 @@ module fu_add(
.delay_lclkr(delay_lclkr[3]), //i-- tidn, .delay_lclkr(delay_lclkr[3]), //i-- tidn,
.mpw1_b(mpw1_b[3]), //i-- tidn, .mpw1_b(mpw1_b[3]), //i-- tidn,
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -304,7 +310,8 @@ module fu_add(
.mpw1_b(mpw1_b[4]), // tidn ,--in .mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex4_act), //in .act(ex4_act), //in

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -33,6 +33,8 @@
module fu_alg( module fu_alg(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module fu_alg(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_alg_si, f_alg_si,
f_alg_so, f_alg_so,
ex1_act, ex1_act,
@ -86,6 +87,8 @@ module fu_alg(
// parameter expand_type = 2; // 0 - ibm tech, 1 - other ); // parameter expand_type = 2; // 0 - ibm tech, 1 - other );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -95,7 +98,6 @@ module fu_alg(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_alg_si; //perv input f_alg_si; //perv
output f_alg_so; //perv output f_alg_so; //perv
@ -410,7 +412,8 @@ module fu_alg(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -420,7 +423,8 @@ module fu_alg(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -450,7 +454,8 @@ module fu_alg(
.delay_lclkr(delay_lclkr[2]), //i-- tidn, .delay_lclkr(delay_lclkr[2]), //i-- tidn,
.mpw1_b(mpw1_b[2]), //i-- tidn, .mpw1_b(mpw1_b[2]), //i-- tidn,
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -476,7 +481,8 @@ module fu_alg(
.mpw1_b(mpw1_b[2]), // tidn ,--in .mpw1_b(mpw1_b[2]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex2_act), //in .act(ex2_act), //in
@ -514,7 +520,8 @@ module fu_alg(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex1_act), .act(ex1_act),
@ -1014,7 +1021,8 @@ module fu_alg(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex3_act), .act(ex3_act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_byp( module fu_byp(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_byp(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_byp_si, f_byp_si,
f_byp_so, f_byp_so,
ex1_act, ex1_act,
@ -177,6 +178,9 @@ module fu_byp(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -186,7 +190,6 @@ module fu_byp(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_byp_si; //perv input f_byp_si; //perv
output f_byp_so; //perv output f_byp_so; //perv
@ -639,7 +642,6 @@ module fu_byp(
wire temp_ex1_a_frac_mul_17; wire temp_ex1_a_frac_mul_17;
wire temp_ex1_a_frac_mul_35; wire temp_ex1_a_frac_mul_35;



// REPOWER_MODE=/SERIAL/ // REPOWER_MODE=/SERIAL/


//AOI22_e5n_sn08b SP/UNDEF //AOI22_e5n_sn08b SP/UNDEF
@ -683,7 +685,8 @@ module fu_byp(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -693,7 +696,8 @@ module fu_byp(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -722,7 +726,8 @@ module fu_byp(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -746,7 +751,8 @@ module fu_byp(
.mpw1_b(mpw1_b), // tidn ,--in .mpw1_b(mpw1_b), // tidn ,--in
.mpw2_b(mpw2_b), // tidn ,--in .mpw2_b(mpw2_b), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex1_act), //in .act(ex1_act), //in

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -50,6 +50,8 @@
module fu_cr2( module fu_cr2(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -59,7 +61,6 @@ module fu_cr2(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_cr2_si, f_cr2_si,
f_cr2_so, f_cr2_so,
ex1_act, ex1_act,
@ -89,6 +90,8 @@ module fu_cr2(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -98,7 +101,6 @@ module fu_cr2(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_cr2_si; // perv input f_cr2_si; // perv
output f_cr2_so; // perv output f_cr2_so; // perv
@ -287,7 +289,8 @@ module fu_cr2(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -297,7 +300,8 @@ module fu_cr2(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -327,7 +331,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -376,7 +381,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), //ex1_act .act(fpu_enable), //ex1_act
@ -433,7 +439,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable),//ex2_act .act(fpu_enable),//ex2_act
@ -472,7 +479,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable),//ex3_act .act(fpu_enable),//ex3_act
@ -516,7 +524,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable),//ex4_act .act(fpu_enable),//ex4_act
@ -538,7 +547,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable),//ex5_act .act(fpu_enable),//ex5_act
@ -561,7 +571,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable),//ex6_act .act(fpu_enable),//ex6_act
@ -670,7 +681,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex2_act), .act(ex2_act),
@ -690,7 +702,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex3_act), .act(ex3_act),
@ -710,7 +723,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex4_act), .act(ex4_act),
@ -730,7 +744,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex5_act), .act(ex5_act),
@ -749,7 +764,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex6_act), .act(ex6_act),
@ -773,7 +789,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_th0_act), .act(ex7_th0_act),
@ -793,7 +810,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_th1_act), .act(ex7_th1_act),
@ -813,7 +831,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_th2_act), .act(ex7_th2_act),
@ -833,7 +852,8 @@ module fu_cr2(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_th3_act), .act(ex7_th3_act),

@ -41,6 +41,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module fu_dcd( module fu_dcd(
clk,
rst,
act_dis, act_dis,
bcfg_scan_in, bcfg_scan_in,
ccfg_scan_in, ccfg_scan_in,
@ -117,7 +119,6 @@ module fu_dcd(
iu_fu_rf0_instr_match, iu_fu_rf0_instr_match,
mpw1_b, mpw1_b,
mpw2_b, mpw2_b,
nclk,
pc_fu_debug_mux_ctrls, pc_fu_debug_mux_ctrls,
pc_fu_event_count_mode, pc_fu_event_count_mode,
pc_fu_instr_trace_mode, pc_fu_instr_trace_mode,
@ -447,7 +448,8 @@ module fu_dcd(
input iu_fu_rf0_instr_match; input iu_fu_rf0_instr_match;
input [0:9] mpw1_b; input [0:9] mpw1_b;
input [0:1] mpw2_b; input [0:1] mpw2_b;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input [0:10] pc_fu_debug_mux_ctrls; input [0:10] pc_fu_debug_mux_ctrls;
input [0:2] pc_fu_event_count_mode; input [0:2] pc_fu_event_count_mode;
input pc_fu_instr_trace_mode; input pc_fu_instr_trace_mode;
@ -1558,7 +1560,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg0( tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg0(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.delay_lclkr(delay_lclkr[9]), .delay_lclkr(delay_lclkr[9]),
@ -1581,7 +1584,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg1( tri_rlmlatch_p #(.INIT(0) ) cp_flush_reg1(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.delay_lclkr(delay_lclkr[9]), .delay_lclkr(delay_lclkr[9]),
@ -1664,7 +1668,8 @@ module fu_dcd(
tri_plat #( .WIDTH(3)) thold_reg_0( tri_plat #( .WIDTH(3)) thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din({thold_1, .din({thold_1,
cfg_sl_thold_1, cfg_sl_thold_1,
@ -1678,7 +1683,8 @@ module fu_dcd(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -1717,7 +1723,8 @@ module fu_dcd(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.delay_lclkr(delay_lclkr[9]), .delay_lclkr(delay_lclkr[9]),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(cfg_sl_force), .force_t(cfg_sl_force),
.thold_b(cfg_sl_thold_0_b), .thold_b(cfg_sl_thold_0_b),
.dclk(cfg_slat_d2clk), .dclk(cfg_slat_d2clk),
@ -1759,7 +1766,8 @@ module fu_dcd(
endgenerate endgenerate


tri_rlmreg_p #(.INIT(0), .WIDTH(8)) act_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(8)) act_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1849,7 +1857,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(1)) ex0_iu( tri_rlmreg_p #(.INIT(0), .WIDTH(8), .NEEDS_SRESET(1)) ex0_iu(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.delay_lclkr(delay_lclkr[0]), .delay_lclkr(delay_lclkr[0]),
@ -1880,7 +1889,8 @@ module fu_dcd(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex0_frt( tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex0_frt(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(msr_fp_act), .act(msr_fp_act),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1920,7 +1930,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(15), .NEEDS_SRESET(1)) ex1_iu( tri_rlmreg_p #(.INIT(0), .WIDTH(15), .NEEDS_SRESET(1)) ex1_iu(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1970,7 +1981,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex1_frt( tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex1_frt(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex1_instr_act), .act(ex1_instr_act),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2001,7 +2013,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex1_instl( tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex1_instl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex1_instr_act), .act(ex1_instr_act),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2020,7 +2033,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex1_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex1_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2051,7 +2065,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex1_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex1_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2528,7 +2543,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex2_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex2_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2582,7 +2598,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(6)) ex2_frt( tri_rlmreg_p #(.INIT(0), .WIDTH(6)) ex2_frt(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex1_v), .act(ex1_v),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2609,7 +2626,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex2_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex2_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2638,7 +2656,8 @@ module fu_dcd(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex2_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex2_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2712,7 +2731,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(7)) ex3_ctlng_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(7)) ex3_ctlng_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2737,7 +2757,8 @@ module fu_dcd(


//------------------------------------------- //-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_ctl_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_ctl_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex2_axu_v), .act(ex2_axu_v),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2792,7 +2813,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex3_stdv_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex3_stdv_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2814,7 +2836,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex3_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex3_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2844,7 +2867,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex3_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex3_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2890,7 +2914,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex4_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(30)) ex4_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2942,7 +2967,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex4_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(16)) ex4_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -2972,7 +2998,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex4_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex4_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3006,7 +3033,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(22)) ex5_ctl_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(22)) ex5_ctl_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3052,7 +3080,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex5_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex5_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3084,7 +3113,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex5_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex5_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3139,7 +3169,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex6_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(21)) ex6_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3183,7 +3214,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex6_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(17)) ex6_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3215,7 +3247,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex6_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex6_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3297,7 +3330,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(23)) ex7_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(23)) ex7_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3347,7 +3381,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3381,7 +3416,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_la( tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex7_la(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3409,7 +3445,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex7_crbf( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex7_crbf(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3471,7 +3508,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex8_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(32)) ex8_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3526,7 +3564,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(8)) ex8_itagl( tri_rlmreg_p #(.INIT(0), .WIDTH(8)) ex8_itagl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3549,7 +3588,8 @@ module fu_dcd(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex8_la( tri_rlmreg_p #(.INIT(0), .WIDTH(18)) ex8_la(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3586,7 +3626,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex9_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(14)) ex9_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3620,7 +3661,8 @@ module fu_dcd(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex9_la( tri_rlmreg_p #(.INIT(0), .WIDTH(9)) ex9_la(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3839,7 +3881,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axu_ex( tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axu_ex(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -3892,10 +3935,12 @@ module fu_dcd(
.perr_so(perr_so), .perr_so(perr_so),
.mpw1_b(mpw1_b), .mpw1_b(mpw1_b),
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(force_t), .force_t(force_t),
.thold_0_b(thold_0_b), .thold_0_b(thold_0_b),
.sg_0(sg_0), .sg_0(sg_0),
.delay_lclkr(10'b0),
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),


@ -4010,7 +4055,8 @@ module fu_dcd(
// Latches // Latches


tri_rlmreg_p #(.INIT(0), .WIDTH(15)) spr_ctl( tri_rlmreg_p #(.INIT(0), .WIDTH(15)) spr_ctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4039,7 +4085,8 @@ module fu_dcd(
//------------------------------------------- //-------------------------------------------


tri_rlmreg_p #(.INIT(0), .WIDTH(2 ** REGMODE)) spr_data( tri_rlmreg_p #(.INIT(0), .WIDTH(2 ** REGMODE)) spr_data(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4061,7 +4108,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axucr0_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(4)) axucr0_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(cfg_sl_force), .force_t(cfg_sl_force),
.d_mode(tiup), .d_mode(tiup),
@ -4083,7 +4131,8 @@ module fu_dcd(




tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) a0esr_lat( tri_ser_rlmreg_p #(.WIDTH(32), .INIT(0)) a0esr_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(a0esr_wr), .act(a0esr_wr),
.force_t(cfg_sl_force), .force_t(cfg_sl_force),
.delay_lclkr(delay_lclkr[9]), .delay_lclkr(delay_lclkr[9]),
@ -4190,7 +4239,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(65)) ex8_ram_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(65)) ex8_ram_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex7_instr_valid), .act(ex7_instr_valid),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4216,7 +4266,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex8_ramv_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) ex8_ramv_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4323,7 +4374,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(8)) event_bus_out_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(8)) event_bus_out_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_act), .act(event_act),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4346,7 +4398,8 @@ module fu_dcd(




tri_rlmreg_p #(.INIT(0), .WIDTH(35)) perf_data( tri_rlmreg_p #(.INIT(0), .WIDTH(35)) perf_data(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_act), .act(event_act),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4390,7 +4443,8 @@ module fu_dcd(
// Debug Bus // Debug Bus


tri_rlmreg_p #(.INIT(0), .WIDTH(32)) dbg_group3_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(32)) dbg_group3_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -4531,7 +4585,8 @@ module fu_dcd(
// Trace Bus latches, using pc_fu_trace_bus_enable for act // Trace Bus latches, using pc_fu_trace_bus_enable for act


tri_rlmreg_p #(.INIT(0), .WIDTH(68)) dbg0_data( tri_rlmreg_p #(.INIT(0), .WIDTH(68)) dbg0_data(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dbg0_act), .act(dbg0_act),
.force_t(func_slp_sl_force), .force_t(func_slp_sl_force),
.d_mode(tiup), .d_mode(tiup),
@ -4563,7 +4618,8 @@ module fu_dcd(
//Another set, closer to the I/O on the bottom //Another set, closer to the I/O on the bottom


tri_rlmreg_p #(.INIT(0), .WIDTH(5)) dbg1_data( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) dbg1_data(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),

@ -38,6 +38,8 @@
module fu_divsqrt( module fu_divsqrt(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -47,7 +49,6 @@ module fu_divsqrt(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_dsq_si, f_dsq_si,
f_dsq_so, f_dsq_so,
ex0_act_b, ex0_act_b,
@ -103,6 +104,8 @@ module fu_divsqrt(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;


input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
@ -114,8 +117,6 @@ module fu_divsqrt(
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act


input [0:`NCLK_WIDTH-1] nclk;

//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
input f_dsq_si; //perv scan input f_dsq_si; //perv scan
output f_dsq_so; //perv scan output f_dsq_so; //perv scan
@ -968,7 +969,8 @@ module fu_divsqrt(
tri_plat #(.WIDTH(1)) thold_reg_0( tri_plat #(.WIDTH(1)) thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -978,7 +980,8 @@ module fu_divsqrt(
tri_plat #(.WIDTH(1)) sg_reg_0( tri_plat #(.WIDTH(1)) sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -1012,7 +1015,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1089,7 +1093,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1136,7 +1141,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1178,7 +1184,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1228,7 +1235,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1295,7 +1303,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1361,7 +1370,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1407,7 +1417,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1487,7 +1498,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1508,7 +1520,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1590,7 +1603,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1611,7 +1625,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1632,7 +1647,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1653,7 +1669,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1674,7 +1691,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1699,7 +1717,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -2351,7 +2370,8 @@ module fu_divsqrt(
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -2725,7 +2745,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] &
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -2956,7 +2977,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] &
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -3001,7 +3023,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] &
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -3062,7 +3085,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] &
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -3136,7 +3160,8 @@ exz_exp_addres_x0[4] & exz_exp_addres_x0[5] &
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_eie( module fu_eie(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_eie(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_eie_si, f_eie_si,
f_eie_so, f_eie_so,
ex2_act, ex2_act,
@ -73,6 +74,9 @@ module fu_eie(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -82,7 +86,6 @@ module fu_eie(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_eie_si; // perv input f_eie_si; // perv
output f_eie_so; // perv output f_eie_so; // perv
@ -202,7 +205,8 @@ module fu_eie(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -212,7 +216,8 @@ module fu_eie(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -240,7 +245,8 @@ module fu_eie(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -533,7 +539,8 @@ module fu_eie(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex2_act), .act(ex2_act),
@ -553,7 +560,8 @@ module fu_eie(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex2_act), .act(ex2_act),
@ -573,7 +581,8 @@ module fu_eie(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex2_act), .act(ex2_act),
@ -705,7 +714,8 @@ module fu_eie(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex3_act), .act(ex3_act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -33,6 +33,8 @@
module fu_eov( module fu_eov(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module fu_eov(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_eov_si, f_eov_si,
f_eov_so, f_eov_so,
ex3_act_b, ex3_act_b,
@ -81,6 +82,9 @@ module fu_eov(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -90,7 +94,6 @@ module fu_eov(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_eov_si; // perv input f_eov_si; // perv
output f_eov_so; // perv output f_eov_so; // perv
@ -348,7 +351,8 @@ module fu_eov(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -358,7 +362,8 @@ module fu_eov(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -379,7 +384,8 @@ module fu_eov(
.mpw1_b(mpw1_b[5]), // tidn .mpw1_b(mpw1_b[5]), // tidn
.mpw2_b(mpw2_b[1]), // tidn .mpw2_b(mpw2_b[1]), // tidn
.force_t(force_t), // tidn .force_t(force_t), // tidn
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex5_act), //in .act(ex5_act), //in
@ -405,7 +411,8 @@ module fu_eov(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -468,7 +475,8 @@ module fu_eov(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex4_act), .act(ex4_act),
@ -1011,7 +1019,8 @@ module fu_eov(
.mpw2_b(mpw2_b[1]), // tidn, .mpw2_b(mpw2_b[1]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex5_act), .act(ex5_act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -39,6 +39,8 @@
module fu_fmt( module fu_fmt(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -48,7 +50,6 @@ module fu_fmt(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_fmt_si, f_fmt_si,
f_fmt_so, f_fmt_so,
ex1_act, ex1_act,
@ -139,6 +140,9 @@ module fu_fmt(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -148,7 +152,6 @@ module fu_fmt(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_fmt_si; //perv input f_fmt_si; //perv
output f_fmt_so; //perv output f_fmt_so; //perv
@ -510,7 +513,8 @@ module fu_fmt(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -520,7 +524,8 @@ module fu_fmt(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -550,7 +555,8 @@ module fu_fmt(
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -618,7 +624,8 @@ module fu_fmt(
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex1_act), .act(ex1_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1343,7 +1350,8 @@ module fu_fmt(
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex2_act), .act(ex2_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),

@ -41,7 +41,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module fu_fpr( module fu_fpr(
nclk, clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -165,7 +166,8 @@ module fu_fpr(
//parameter threads = 2; //parameter threads = 2;
parameter axu_spare_enc = 3; parameter axu_spare_enc = 3;


input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -541,7 +543,8 @@ module fu_fpr(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -551,7 +554,8 @@ module fu_fpr(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -571,7 +575,8 @@ module fu_fpr(
tri_plat #(.WIDTH(4)) ab_thold_reg_0( tri_plat #(.WIDTH(4)) ab_thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din({abst_sl_thold_1, .din({abst_sl_thold_1,
time_sl_thold_1, time_sl_thold_1,
@ -620,7 +625,8 @@ module fu_fpr(
endgenerate endgenerate


tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex6_lctl( tri_rlmreg_p #(.INIT(0), .WIDTH(5)) ex6_lctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -689,7 +695,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(2)) ex6_ldv( tri_rlmreg_p #(.INIT(0), .WIDTH(2)) ex6_ldv(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -710,7 +717,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(12)) ex7_lctl( tri_rlmreg_p #(.INIT(0), .WIDTH(12)) ex7_lctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -732,7 +740,8 @@ module fu_fpr(
); );


tri_rlmreg_p #(.INIT(0), .WIDTH(10)) ex7_rlctl( tri_rlmreg_p #(.INIT(0), .WIDTH(10)) ex7_rlctl(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_reload_v), .act(ex5_reload_v),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -751,7 +760,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_ldat( tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_ldat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_load_v), .act(ex5_load_v),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -770,7 +780,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_rldat( tri_rlmreg_p #(.INIT(0), .WIDTH(64), .NEEDS_SRESET(0)) ex7_rldat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_reload_v), .act(ex5_reload_v),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1313,7 +1324,8 @@ module fu_fpr(
tri_144x78_2r4w fpr0( // .regsize(64), #( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) tri_144x78_2r4w fpr0( // .regsize(64), #( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc))
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.delay_lclkr_dc(delay_lclkra[0]), .delay_lclkr_dc(delay_lclkra[0]),
.mpw1_dc_b(mpw1_ba[0]), .mpw1_dc_b(mpw1_ba[0]),
.mpw2_dc_b(mpw2_b[0]), .mpw2_dc_b(mpw2_b[0]),
@ -1347,11 +1359,11 @@ module fu_fpr(
.w_data_in_4(zeros[0:77]) .w_data_in_4(zeros[0:77])
); );



tri_144x78_2r4w fpr1(// .regsize(64),#( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc)) tri_144x78_2r4w fpr1(// .regsize(64),#( .gpr_pool(fpr_pool), .gpr_pool_enc(fpr_pool_enc))
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.delay_lclkr_dc(delay_lclkra[0]), .delay_lclkr_dc(delay_lclkra[0]),
.mpw1_dc_b(mpw1_ba[0]), .mpw1_dc_b(mpw1_ba[0]),
.mpw2_dc_b(mpw2_b[0]), .mpw2_dc_b(mpw2_b[0]),
@ -1388,7 +1400,8 @@ module fu_fpr(
// ABIST timing latches // ABIST timing latches


tri_rlmreg_p #(.INIT(0), .WIDTH(53), .NEEDS_SRESET(0)) ab_reg( tri_rlmreg_p #(.INIT(0), .WIDTH(53), .NEEDS_SRESET(0)) ab_reg(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(ab_force), .force_t(ab_force),
.d_mode(tiup), .d_mode(tiup),
@ -1430,7 +1443,8 @@ module fu_fpr(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.sg(sg_0), .sg(sg_0),
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(time_scan_in), // Connects to time scan ring .scan_in(time_scan_in), // Connects to time scan ring
.scan_diag_dc(scan_diag_dc), .scan_diag_dc(scan_diag_dc),
.thold(time_sl_thold_0), //Connects to time thold .thold(time_sl_thold_0), //Connects to time thold
@ -1469,7 +1483,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(34), .NEEDS_SRESET(0)) ex1_par( tri_rlmreg_p #(.INIT(0), .WIDTH(34), .NEEDS_SRESET(0)) ex1_par(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1533,7 +1548,8 @@ module fu_fpr(




tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) ldwt_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) ldwt_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1555,7 +1571,8 @@ module fu_fpr(
); );
//------------------------------------------- //-------------------------------------------
tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) reldwt_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(132), .NEEDS_SRESET(0)) reldwt_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
@ -1614,7 +1631,8 @@ module fu_fpr(
// Target Bypass // Target Bypass


tri_rlmreg_p #(.INIT(0), .WIDTH(134), .NEEDS_SRESET(0)) tgwt_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(134), .NEEDS_SRESET(0)) tgwt_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -38,6 +38,8 @@
module fu_gst( module fu_gst(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -47,7 +49,6 @@ module fu_gst(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_gst_si, f_gst_si,
f_gst_so, f_gst_so,
ex1_act, ex1_act,
@ -65,6 +66,8 @@ module fu_gst(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;


input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
@ -75,7 +78,6 @@ module fu_gst(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
// //
input f_gst_si; //perv scan input f_gst_si; //perv scan
@ -464,7 +466,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -474,7 +477,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -502,7 +506,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -545,7 +550,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -577,7 +583,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -895,7 +902,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -921,7 +929,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -979,7 +988,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1008,7 +1018,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1312,7 +1323,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------
@ -1337,7 +1349,8 @@ ex3_mantissa_shlev3[47] | ex3_mantissa_shlev3[48] | ex3_mantissa_shlev3[49] | ex
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
//----------------- //-----------------

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -33,6 +33,8 @@
module fu_lza( module fu_lza(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module fu_lza(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_lza_si, f_lza_si,
f_lza_so, f_lza_so,
ex2_act_b, ex2_act_b,
@ -64,6 +65,8 @@ module fu_lza(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -73,7 +76,6 @@ module fu_lza(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_lza_si; //perv input f_lza_si; //perv
output f_lza_so; //perv output f_lza_so; //perv
@ -173,7 +175,8 @@ module fu_lza(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -183,7 +186,8 @@ module fu_lza(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -214,7 +218,8 @@ module fu_lza(
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -242,7 +247,8 @@ module fu_lza(
.mpw1_b(mpw1_b[3]), // tidn ,--in .mpw1_b(mpw1_b[3]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex3_act), //in .act(ex3_act), //in
@ -259,7 +265,8 @@ module fu_lza(
.mpw1_b(mpw1_b[4]), // tidn ,--in .mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex4_act), //in .act(ex4_act), //in

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_lze( module fu_lze(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_lze(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_lze_si, f_lze_si,
f_lze_so, f_lze_so,
ex2_act_b, ex2_act_b,
@ -67,6 +68,8 @@ module fu_lze(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -76,7 +79,6 @@ module fu_lze(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_lze_si; //perv input f_lze_si; //perv
output f_lze_so; //perv output f_lze_so; //perv
@ -184,7 +186,8 @@ module fu_lze(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -194,7 +197,8 @@ module fu_lze(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -225,7 +229,8 @@ module fu_lze(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -889,7 +894,8 @@ module fu_lze(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex3_act), .act(ex3_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),

@ -14,23 +14,25 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


`include "tri_a2o.vh" `include "tri_a2o.vh"


module fu_mad( module fu_mad(
clk,
rst,
f_dcd_ex7_cancel, f_dcd_ex7_cancel,
f_dcd_ex1_bypsel_a_res0, f_dcd_ex1_bypsel_a_res0,
f_dcd_ex1_bypsel_a_res1, f_dcd_ex1_bypsel_a_res1,
@ -267,8 +269,7 @@ module fu_mad(
mpw2_b, mpw2_b,
thold_1, thold_1,
sg_1, sg_1,
fpu_enable, fpu_enable
nclk
); );
parameter THREADS = 2; parameter THREADS = 2;
input f_dcd_ex7_cancel; input f_dcd_ex7_cancel;
@ -537,6 +538,9 @@ module fu_mad(
//-------------------------------------------------------------------------- //--------------------------------------------------------------------------
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input [0:18] scan_in; input [0:18] scan_in;
output [0:18] scan_out; output [0:18] scan_out;
input clkoff_b; // tiup input clkoff_b; // tiup
@ -548,9 +552,6 @@ module fu_mad(
input thold_1; input thold_1;
input sg_1; input sg_1;
input fpu_enable; input fpu_enable;
input [0:`NCLK_WIDTH-1] nclk;
// This entity contains macros

parameter tiup = 1'b1; parameter tiup = 1'b1;
parameter tidn = 1'b0; parameter tidn = 1'b0;


@ -944,7 +945,8 @@ module fu_mad(
//--------------------------------------------------------- -- fuq_byp.vhdl //--------------------------------------------------------- -- fuq_byp.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1102,7 +1104,8 @@ module fu_mad(
//----------------------------------------------------------- fu_fmt.vhdl //----------------------------------------------------------- fu_fmt.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1217,7 +1220,8 @@ module fu_mad(
//----------------------------------------------------------- fu_eie.vhdl //----------------------------------------------------------- fu_eie.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1261,7 +1265,8 @@ module fu_mad(
//----------------------------------------------------------- fu_eov.vhdl //----------------------------------------------------------- fu_eov.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1317,7 +1322,8 @@ module fu_mad(
//----------------------------------------------------------- fu_mul.vhdl //----------------------------------------------------------- fu_mul.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1345,7 +1351,8 @@ module fu_mad(
//----------------------------------------------------------- fu_alg.vhdl //----------------------------------------------------------- fu_alg.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1406,7 +1413,8 @@ module fu_mad(
//----------------------------------------------------------- fuq_sa3.vhdl //----------------------------------------------------------- fuq_sa3.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1435,7 +1443,8 @@ module fu_mad(
//----------------------------------------------------------- fu_add.vhdl //----------------------------------------------------------- fu_add.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1479,7 +1488,8 @@ module fu_mad(
//----------------------------------------------------------- fu_lze.vhdl //----------------------------------------------------------- fu_lze.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1520,7 +1530,8 @@ module fu_mad(
//----------------------------------------------------------- fu_lza.vhdl //----------------------------------------------------------- fu_lza.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1559,7 +1570,8 @@ module fu_mad(
//----------------------------------------------------------- fu_nrm.vhdl //----------------------------------------------------------- fu_nrm.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1604,7 +1616,8 @@ module fu_mad(
//----------------------------------------------------------- fu_rnd.vhdl //----------------------------------------------------------- fu_rnd.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1712,7 +1725,8 @@ module fu_mad(
//----------------------------------------------------------- fu_gst.vhdl //----------------------------------------------------------- fu_gst.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1743,7 +1757,8 @@ module fu_mad(
//----------------------------------------------------------- fu_divsqrt.vhdl //----------------------------------------------------------- fu_divsqrt.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -1836,7 +1851,8 @@ module fu_mad(
//----------------------------------------------------------- fu_pic.vhdl //----------------------------------------------------------- fu_pic.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -2090,7 +2106,8 @@ module fu_mad(
//----------------------------------------------------------- fu_cr2.vhdl //----------------------------------------------------------- fu_cr2.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -2136,7 +2153,8 @@ module fu_mad(
//----------------------------------------------------------- fuq_scr.vhdl //----------------------------------------------------------- fuq_scr.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -2249,7 +2267,8 @@ module fu_mad(
//----------------------------------------------------------- fuq_tblexp.vhdl //----------------------------------------------------------- fuq_tblexp.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--
@ -2286,7 +2305,8 @@ module fu_mad(
//----------------------------------------------------------- fuq_tbllut.vhdl //----------------------------------------------------------- fuq_tbllut.vhdl
.vdd(vdd), //i-- .vdd(vdd), //i--
.gnd(gnd), //i-- .gnd(gnd), //i--
.nclk(nclk), //i-- .clk(clk),
.rst(rst), //i--
.clkoff_b(clkoff_b), //i-- .clkoff_b(clkoff_b), //i--
.act_dis(act_dis), //i-- .act_dis(act_dis), //i--
.flush(flush), //i-- .flush(flush), //i--

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_nrm( module fu_nrm(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_nrm(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_nrm_si, f_nrm_si,
f_nrm_so, f_nrm_so,
ex4_act_b, ex4_act_b,
@ -72,6 +73,9 @@ module fu_nrm(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -81,7 +85,6 @@ module fu_nrm(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_nrm_si; // perv input f_nrm_si; // perv
output f_nrm_so; // perv output f_nrm_so; // perv
@ -214,7 +217,8 @@ module fu_nrm(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -224,7 +228,8 @@ module fu_nrm(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -245,7 +250,8 @@ module fu_nrm(
.mpw1_b(mpw1_b[5]), // tidn .mpw1_b(mpw1_b[5]), // tidn
.mpw2_b(mpw2_b[1]), // tidn .mpw2_b(mpw2_b[1]), // tidn
.force_t(force_t), // tidn .force_t(force_t), // tidn
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex5_act), //in .act(ex5_act), //in
@ -271,7 +277,8 @@ module fu_nrm(
.mpw2_b(mpw2_b[0]), //i-- tidn, .mpw2_b(mpw2_b[0]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -545,7 +552,8 @@ module fu_nrm(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex5_act), .act(ex5_act),
@ -568,7 +576,8 @@ module fu_nrm(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex5_act), .act(ex5_act),

@ -92,6 +92,8 @@
module fu_oscr( module fu_oscr(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -101,7 +103,6 @@ module fu_oscr(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_scr_si, f_scr_si,
f_scr_so, f_scr_so,
ex3_act_b, ex3_act_b,
@ -189,6 +190,8 @@ module fu_oscr(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -198,7 +201,6 @@ module fu_oscr(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_scr_si; // perv input f_scr_si; // perv
output f_scr_so; // perv output f_scr_so; // perv
@ -640,7 +642,8 @@ module fu_oscr(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -650,7 +653,8 @@ module fu_oscr(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -690,7 +694,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -766,7 +771,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -805,7 +811,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -849,7 +856,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -884,7 +892,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -943,7 +952,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), // ex6_act, -- todo: act pin .act(tiup), // ex6_act, -- todo: act pin
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1008,7 +1018,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_act), .act(ex6_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1269,7 +1280,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_act), .act(ex7_act),
@ -1291,7 +1303,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex7_act), //ex7_th1_act, todo: act pin .act(ex7_act), //ex7_th1_act, todo: act pin
@ -1312,7 +1325,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex7_act), .act(ex7_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1587,7 +1601,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1838,7 +1853,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2014,7 +2030,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2572,7 +2589,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2592,7 +2610,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2626,7 +2645,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2646,7 +2666,8 @@ module fu_oscr(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -39,7 +39,8 @@
module fu_perv( module fu_perv(
vdd, vdd,
gnd, gnd,
nclk, clk,
rst,
pc_fu_sg_3, pc_fu_sg_3,
pc_fu_abst_sl_thold_3, pc_fu_abst_sl_thold_3,
pc_fu_func_sl_thold_3, pc_fu_func_sl_thold_3,
@ -74,7 +75,8 @@ module fu_perv(
inout vdd; inout vdd;
inout gnd; inout gnd;


input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input [0:1] pc_fu_sg_3; input [0:1] pc_fu_sg_3;
input pc_fu_abst_sl_thold_3; input pc_fu_abst_sl_thold_3;
input [0:1] pc_fu_func_sl_thold_3; input [0:1] pc_fu_func_sl_thold_3;
@ -158,7 +160,8 @@ module fu_perv(
tri_plat #(.WIDTH(12)) perv_3to2_reg( tri_plat #(.WIDTH(12)) perv_3to2_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),


.din({ .din({
@ -190,7 +193,8 @@ module fu_perv(
tri_plat #(.WIDTH(12)) perv_2to1_reg( tri_plat #(.WIDTH(12)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),


.din({ .din({
@ -224,7 +228,8 @@ module fu_perv(
tri_plat #(.WIDTH(3)) perv_1to0_reg( tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({ gptr_sl_thold_1, .din({ gptr_sl_thold_1,
sg_1_int[0], sg_1_int[0],
@ -253,7 +258,8 @@ module fu_perv(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.sg(sg_0), .sg(sg_0),
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(gptr_scan_in), .scan_in(gptr_scan_in),
.scan_diag_dc(tc_ac_scan_diag_dc), .scan_diag_dc(tc_ac_scan_diag_dc),
.thold(gptr_sl_thold_0_int), .thold(gptr_sl_thold_0_int),
@ -270,7 +276,8 @@ module fu_perv(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.sg(sg_0), .sg(sg_0),
.nclk(nclk), .clk(clk),
.rst(rst),
.scan_in(gptr_sio), .scan_in(gptr_sio),
.scan_diag_dc(tc_ac_scan_diag_dc), .scan_diag_dc(tc_ac_scan_diag_dc),
.thold(gptr_sl_thold_0_int), .thold(gptr_sl_thold_0_int),
@ -306,7 +313,8 @@ module fu_perv(
assign repr_in = 1'b0; assign repr_in = 1'b0;


tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat( tri_rlmreg_p #(.INIT(0), .WIDTH(1)) repr_rpwr_lat(
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tihi), .act(tihi),
.force_t(repr_sl_force), .force_t(repr_sl_force),
.d_mode(tiup), .d_mode(tiup),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -33,6 +33,8 @@
module fu_pic( module fu_pic(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module fu_pic(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_pic_si, f_pic_si,
f_pic_so, f_pic_so,
f_dcd_ex1_act, f_dcd_ex1_act,
@ -276,6 +277,8 @@ module fu_pic(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -285,7 +288,6 @@ module fu_pic(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_pic_si; //perv input f_pic_si; //perv
output f_pic_so; //perv output f_pic_so; //perv
@ -1166,7 +1168,8 @@ module fu_pic(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -1176,7 +1179,8 @@ module fu_pic(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -1201,7 +1205,8 @@ module fu_pic(
tri_rlmreg_p #(.WIDTH(21)) act_lat( tri_rlmreg_p #(.WIDTH(21)) act_lat(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(force_t), .force_t(force_t),
.d_mode(tiup), .d_mode(tiup),
.delay_lclkr(delay_lclkr[4]), .delay_lclkr(delay_lclkr[4]),
@ -1324,7 +1329,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[1]), .delay_lclkr(delay_lclkr[1]),
.mpw1_b(mpw1_b[1]), .mpw1_b(mpw1_b[1]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(f_dcd_ex1_act), .act(f_dcd_ex1_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1534,7 +1540,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[2]), .delay_lclkr(delay_lclkr[2]),
.mpw1_b(mpw1_b[2]), .mpw1_b(mpw1_b[2]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex2_act), .act(ex2_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1677,7 +1684,8 @@ module fu_pic(
.delay_lclkr(tidn), .delay_lclkr(tidn),
.mpw1_b(tidn), .mpw1_b(tidn),
.mpw2_b(tidn), .mpw2_b(tidn),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex2_act), .act(ex2_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1987,7 +1995,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[3]), .delay_lclkr(delay_lclkr[3]),
.mpw1_b(mpw1_b[3]), .mpw1_b(mpw1_b[3]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex3_act), .act(ex3_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2029,7 +2038,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[3]), .delay_lclkr(delay_lclkr[3]),
.mpw1_b(mpw1_b[3]), .mpw1_b(mpw1_b[3]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex3_act), .act(ex3_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2126,7 +2136,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[3]), .delay_lclkr(delay_lclkr[3]),
.mpw1_b(mpw1_b[3]), .mpw1_b(mpw1_b[3]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex3_act), .act(ex3_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2337,7 +2348,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[4]), .delay_lclkr(delay_lclkr[4]),
.mpw1_b(mpw1_b[4]), .mpw1_b(mpw1_b[4]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex4_act), .act(ex4_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2374,7 +2386,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[4]), .delay_lclkr(delay_lclkr[4]),
.mpw1_b(mpw1_b[4]), .mpw1_b(mpw1_b[4]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex4_act), .act(ex4_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2452,7 +2465,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[4]), .delay_lclkr(delay_lclkr[4]),
.mpw1_b(mpw1_b[4]), .mpw1_b(mpw1_b[4]),
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex4_act), .act(ex4_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -2774,7 +2788,8 @@ module fu_pic(
.delay_lclkr(delay_lclkr[5]), .delay_lclkr(delay_lclkr[5]),
.mpw1_b(mpw1_b[5]), .mpw1_b(mpw1_b[5]),
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_act), .act(ex5_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_rnd( module fu_rnd(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_rnd(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_rnd_si, f_rnd_si,
f_rnd_so, f_rnd_so,
ex4_act_b, ex4_act_b,
@ -131,6 +132,9 @@ module fu_rnd(
parameter expand_type = 2; // 0 - ibm tech, 1 - other ); parameter expand_type = 2; // 0 - ibm tech, 1 - other );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -140,7 +144,6 @@ module fu_rnd(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_rnd_si; // perv input f_rnd_si; // perv
output f_rnd_so; // perv output f_rnd_so; // perv
@ -428,7 +431,8 @@ module fu_rnd(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -438,7 +442,8 @@ module fu_rnd(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -469,7 +474,8 @@ module fu_rnd(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -521,7 +527,8 @@ module fu_rnd(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex5_act), .act(ex5_act),
@ -1145,7 +1152,8 @@ module fu_rnd(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex6_act), .act(ex6_act),
@ -1166,7 +1174,8 @@ module fu_rnd(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex6_act), .act(ex6_act),
@ -1189,7 +1198,8 @@ module fu_rnd(
.mpw2_b(mpw2_b[1]), //i-- tidn, .mpw2_b(mpw2_b[1]), //i-- tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex6_act), .act(ex6_act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -34,6 +34,8 @@
module fu_sa3( module fu_sa3(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -43,7 +45,6 @@ module fu_sa3(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_sa3_si, f_sa3_si,
f_sa3_so, f_sa3_so,
ex2_act_b, ex2_act_b,
@ -57,6 +58,9 @@ module fu_sa3(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -66,7 +70,6 @@ module fu_sa3(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_sa3_si; //perv input f_sa3_si; //perv
output f_sa3_so; //perv output f_sa3_so; //perv
@ -1306,7 +1309,8 @@ module fu_sa3(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -1316,7 +1320,8 @@ module fu_sa3(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -1347,7 +1352,8 @@ module fu_sa3(
.mpw2_b(mpw2_b[0]), // tidn, .mpw2_b(mpw2_b[0]), // tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -1373,7 +1379,8 @@ module fu_sa3(
.mpw1_b(mpw1_b[3]), // tidn ,--in .mpw1_b(mpw1_b[3]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex3_act), //in .act(ex3_act), //in

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -59,6 +59,8 @@
module fu_sto( module fu_sto(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -68,7 +70,6 @@ module fu_sto(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
f_sto_si, f_sto_si,
f_sto_so, f_sto_so,
f_dcd_ex1_sto_act, f_dcd_ex1_sto_act,
@ -86,6 +87,8 @@ module fu_sto(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;
input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -95,7 +98,6 @@ module fu_sto(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input f_sto_si; input f_sto_si;
output f_sto_so; output f_sto_so;
@ -243,7 +245,8 @@ module fu_sto(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -253,7 +256,8 @@ module fu_sto(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -278,7 +282,8 @@ module fu_sto(
tri_rlmreg_p #(.WIDTH(4)) act_lat( tri_rlmreg_p #(.WIDTH(4)) act_lat(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.force_t(force_t), // tidn .force_t(force_t), // tidn
.d_mode(tiup), .d_mode(tiup),
.delay_lclkr(delay_lclkr[1]), // tidn, .delay_lclkr(delay_lclkr[1]), // tidn,
@ -314,7 +319,8 @@ module fu_sto(
.delay_lclkr(delay_lclkr[1]), //tidn, .delay_lclkr(delay_lclkr[1]), //tidn,
.mpw1_b(mpw1_b[1]), //tidn, .mpw1_b(mpw1_b[1]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex1_act), .act(ex1_act),
@ -339,7 +345,8 @@ module fu_sto(
.delay_lclkr(delay_lclkr[1]), //tidn, .delay_lclkr(delay_lclkr[1]), //tidn,
.mpw1_b(mpw1_b[1]), //tidn, .mpw1_b(mpw1_b[1]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex1_act), .act(ex1_act),
@ -663,7 +670,8 @@ module fu_sto(
.delay_lclkr(delay_lclkr[2]), //tidn, .delay_lclkr(delay_lclkr[2]), //tidn,
.mpw1_b(mpw1_b[2]), //tidn, .mpw1_b(mpw1_b[2]), //tidn,
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex2_act), .act(ex2_act),

@ -14,23 +14,25 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


module fu_tblexp( module fu_tblexp(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -40,7 +42,6 @@ module fu_tblexp(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
si, si,
so, so,
ex2_act_b, ex2_act_b,
@ -65,6 +66,9 @@ module fu_tblexp(


inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -74,7 +78,6 @@ module fu_tblexp(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input si; // perv input si; // perv
output so; // perv output so; // perv
@ -188,7 +191,8 @@ module fu_tblexp(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -198,7 +202,8 @@ module fu_tblexp(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -229,7 +234,8 @@ module fu_tblexp(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(fpu_enable), .act(fpu_enable),
@ -559,7 +565,8 @@ module fu_tblexp(
.mpw2_b(mpw2_b[0]), //tidn, .mpw2_b(mpw2_b[0]), //tidn,
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
.act(ex3_act), .act(ex3_act),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -33,6 +33,8 @@
module fu_tbllut( module fu_tbllut(
vdd, vdd,
gnd, gnd,
clk,
rst,
clkoff_b, clkoff_b,
act_dis, act_dis,
flush, flush,
@ -42,7 +44,6 @@ module fu_tbllut(
sg_1, sg_1,
thold_1, thold_1,
fpu_enable, fpu_enable,
nclk,
si, si,
so, so,
ex2_act, ex2_act,
@ -64,6 +65,9 @@ module fu_tbllut(
); );
inout vdd; inout vdd;
inout gnd; inout gnd;
input clk;
input rst;

input clkoff_b; // tiup input clkoff_b; // tiup
input act_dis; // ??tidn?? input act_dis; // ??tidn??
input flush; // ??tidn?? input flush; // ??tidn??
@ -73,7 +77,6 @@ module fu_tbllut(
input sg_1; input sg_1;
input thold_1; input thold_1;
input fpu_enable; //dc_act input fpu_enable; //dc_act
input [0:`NCLK_WIDTH-1] nclk;


input si; //perv input si; //perv
output so; //perv output so; //perv
@ -236,7 +239,8 @@ module fu_tbllut(
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex2_act), .act(ex2_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -792,7 +796,8 @@ module fu_tbllut(
.mpw2_b(mpw2_b[1]), .mpw2_b(mpw2_b[1]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_act), .act(ex5_act),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -816,7 +821,8 @@ module fu_tbllut(
tri_plat thold_reg_0( tri_plat thold_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(thold_1), .din(thold_1),
.q(thold_0) .q(thold_0)
@ -826,7 +832,8 @@ module fu_tbllut(
tri_plat sg_reg_0( tri_plat sg_reg_0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(flush), .flush(flush),
.din(sg_1), .din(sg_1),
.q(sg_0) .q(sg_0)
@ -855,7 +862,8 @@ module fu_tbllut(
.mpw2_b(mpw2_b[0]), .mpw2_b(mpw2_b[0]),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(fpu_enable), .act(fpu_enable),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(sg_0), .sg(sg_0),
@ -885,7 +893,8 @@ module fu_tbllut(
.mpw1_b(mpw1_b[3]), // tidn ,--in .mpw1_b(mpw1_b[3]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex3_act), //in .act(ex3_act), //in
@ -902,7 +911,8 @@ module fu_tbllut(
.mpw1_b(mpw1_b[4]), // tidn ,--in .mpw1_b(mpw1_b[4]), // tidn ,--in
.mpw2_b(mpw2_b[0]), // tidn ,--in .mpw2_b(mpw2_b[0]), // tidn ,--in
.force_t(force_t), // tidn ,--in .force_t(force_t), // tidn ,--in
.nclk(nclk), //in .clk(clk),
.rst(rst), //in
.vd(vdd), //inout .vd(vdd), //inout
.gd(gnd), //inout .gd(gnd), //inout
.act(ex4_act), //in .act(ex4_act), //in

@ -40,8 +40,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module iuq( module iuq(
(* pin_data="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,
input pc_iu_sg_3, input pc_iu_sg_3,
input pc_iu_fce_3, input pc_iu_fce_3,
input pc_iu_func_slp_sl_thold_3, // was: chip_b_sl_2_thold_3_b input pc_iu_func_slp_sl_thold_3, // was: chip_b_sl_2_thold_3_b
@ -1375,7 +1375,8 @@ module iuq(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_fce_2(pc_iu_fce_2), .pc_iu_fce_2(pc_iu_fce_2),
@ -1402,7 +1403,8 @@ module iuq(
//.vcs(vdd), //.vcs(vdd),
//.vdd(vdd), //.vdd(vdd),
//.gnd(gnd), //.gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_ac_scan_dis_dc_b(tc_ac_scan_dis_dc_b),
.tc_ac_scan_diag_dc(tc_ac_scan_diag_dc), .tc_ac_scan_diag_dc(tc_ac_scan_diag_dc),
@ -1830,7 +1832,8 @@ module iuq(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2),
@ -1898,7 +1901,8 @@ module iuq(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2),
@ -1965,7 +1969,8 @@ module iuq(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2), .pc_iu_time_sl_thold_2(pc_iu_time_sl_thold_2),
@ -2031,7 +2036,8 @@ module iuq(
iuq_slice_top iuq_slice_top0( iuq_slice_top iuq_slice_top0(
//.vdd(vdd), //.vdd(vdd),
//.gnd(gnd), //.gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2), .pc_iu_func_slp_sl_thold_2(pc_iu_func_slp_sl_thold_2),
@ -2717,7 +2723,8 @@ module iuq(
iuq_cpl_top iuq_cpl_top0( iuq_cpl_top iuq_cpl_top0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.clkoff_dc_b(clkoff_b), .clkoff_dc_b(clkoff_b),
.d_mode_dc(d_mode), .d_mode_dc(d_mode),
@ -3319,7 +3326,8 @@ module iuq(
tri_plat #(.WIDTH(15)) perv_3to2_reg( tri_plat #(.WIDTH(15)) perv_3to2_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_slp_sl_thold_3, .din({pc_iu_func_slp_sl_thold_3,
pc_iu_func_nsl_thold_3, pc_iu_func_nsl_thold_3,

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -35,7 +35,8 @@
`include "tri_a2o.vh" `include "tri_a2o.vh"


module iuq_axu_fu_dec( module iuq_axu_fu_dec(
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
//------------------------------------------------------------------- //-------------------------------------------------------------------
inout vdd, inout vdd,
inout gnd, inout gnd,
@ -216,7 +217,8 @@ module iuq_axu_fu_dec(
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
@ -226,7 +228,8 @@ module iuq_axu_fu_dec(
tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0,pc_iu_sg_0})
@ -1230,7 +1233,8 @@ assign only_graphics_mode = ( pri_is0[0] & pri_is0[1] & pri_is0[2]
.gd(gnd), .gd(gnd),
.force_t(force_t), .force_t(force_t),
.delay_lclkr(delay_lclkr), .delay_lclkr(delay_lclkr),
.nclk(nclk), .clk(clk),
.rst(rst),
.mpw1_b(mpw1_b), .mpw1_b(mpw1_b),
.act(tiup), .act(tiup),
.mpw2_b(mpw2_b), .mpw2_b(mpw2_b),

@ -48,7 +48,8 @@ module iuq_axu_fu_rn #(
( (
inout vdd, inout vdd,
inout gnd, inout gnd,
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types input pc_iu_func_sl_thold_2, // acts as reset for non-ibm types
input pc_iu_sg_2, input pc_iu_sg_2,
input clkoff_b, input clkoff_b,
@ -416,7 +417,8 @@ module iuq_axu_fu_rn #(
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + FPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(FPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) fpr_rn_map( iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH((32 + FPR_UCODE_POOL)), .REGISTER_RENAME_DEPTH(FPR_POOL), .STORAGE_WIDTH(`GPR_POOL_ENC)) fpr_rn_map(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0), .pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t), .force_t(force_t),
@ -511,7 +513,8 @@ module iuq_axu_fu_rn #(
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(24), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(24), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC)
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0), .pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t), .force_t(force_t),
@ -582,7 +585,8 @@ module iuq_axu_fu_rn #(
iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(32), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC) iuq_rn_map #(.ARCHITECTED_REGISTER_DEPTH(1), .REGISTER_RENAME_DEPTH(32), .STORAGE_WIDTH(5)) fpscr_rn_map( //`GPR_POOL_ENC)
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0), .pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t), .force_t(force_t),
@ -654,7 +658,8 @@ module iuq_axu_fu_rn #(
tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -673,7 +678,8 @@ module iuq_axu_fu_rn #(
tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch( tri_rlmlatch_p #(.INIT(0)) br_iu_hold_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -696,7 +702,8 @@ module iuq_axu_fu_rn #(
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
@ -706,7 +713,8 @@ module iuq_axu_fu_rn #(
tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0,pc_iu_sg_0})

@ -129,7 +129,8 @@ module iuq_bp(
spr_single_issue, spr_single_issue,
vdd, vdd,
gnd, gnd,
nclk, clk,
rst,
pc_iu_sg_2, pc_iu_sg_2,
pc_iu_func_sl_thold_2, pc_iu_func_sl_thold_2,
clkoff_b, clkoff_b,
@ -277,8 +278,8 @@ module iuq_bp(
//pervasive //pervasive
inout vdd; inout vdd;
inout gnd; inout gnd;
(* pin_data="PIN_FUNCTION=/G_CLK/" *) input clk;
input [0:`NCLK_WIDTH-1] nclk; input rst;
input pc_iu_sg_2; input pc_iu_sg_2;
input pc_iu_func_sl_thold_2; input pc_iu_func_sl_thold_2;
input clkoff_b; input clkoff_b;
@ -1807,7 +1808,8 @@ generate
tri_rlmreg_p #(.WIDTH(128), .INIT(0)) iu0_btb_hist_reg( tri_rlmreg_p #(.WIDTH(128), .INIT(0)) iu0_btb_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu0_btb_hist_act), .act(iu0_btb_hist_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1826,7 +1828,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu1_btb_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu1_btb_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1845,7 +1848,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu2_btb_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu2_btb_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1864,7 +1868,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) gshare_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(gshare_act[0]), .act(gshare_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1882,7 +1887,8 @@ generate
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) gshare_shift0_reg( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) gshare_shift0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1900,7 +1906,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) cp_gshare_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) cp_gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1918,7 +1925,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_gs_count_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_gs_count_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1936,7 +1944,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) cp_gs_taken_reg( tri_rlmlatch_p #(.INIT(0)) cp_gs_taken_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1954,7 +1963,8 @@ generate
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu1_gs_pos_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu1_gs_pos_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1972,7 +1982,8 @@ generate
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_gs_pos_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_gs_pos_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1990,7 +2001,8 @@ generate
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu3_gs_pos_reg( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu3_gs_pos_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2008,7 +2020,8 @@ generate
tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu1_gshare_reg( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu1_gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2027,7 +2040,8 @@ generate
tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu2_gshare_reg( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) iu2_gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2046,7 +2060,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_bh_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_bh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2065,7 +2080,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_lk_reg( tri_rlmlatch_p #(.INIT(0)) iu3_lk_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2084,7 +2100,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_aa_reg( tri_rlmlatch_p #(.INIT(0)) iu3_aa_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2103,7 +2120,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_b_reg( tri_rlmlatch_p #(.INIT(0)) iu3_b_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2122,7 +2140,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_bclr_reg( tri_rlmlatch_p #(.INIT(0)) iu3_bclr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2141,7 +2160,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_bcctr_reg( tri_rlmlatch_p #(.INIT(0)) iu3_bcctr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2160,7 +2180,8 @@ generate
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) iu3_opcode_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) iu3_opcode_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2179,7 +2200,8 @@ generate
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bo_reg( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bo_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2198,7 +2220,8 @@ generate
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bi_reg( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) iu3_bi_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2217,7 +2240,8 @@ generate
tri_rlmreg_p #(.WIDTH(24), .INIT(0)) iu3_tar_reg( tri_rlmreg_p #(.WIDTH(24), .INIT(0)) iu3_tar_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2236,7 +2260,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_ifar_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_ifar_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2255,7 +2280,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_ifar_pri_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu3_ifar_pri_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2274,7 +2300,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_pr_val_reg( tri_rlmlatch_p #(.INIT(0)) iu3_pr_val_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2292,7 +2319,8 @@ generate
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_lnk_reg( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_lnk_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2311,7 +2339,8 @@ generate
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_btb_reg( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu3_btb_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2330,7 +2359,8 @@ generate
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_val_reg( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_val_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2349,7 +2379,8 @@ generate
tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_0_instr_reg( tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_0_instr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_instr_act[0]), .act(iu3_instr_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2368,7 +2399,8 @@ generate
tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_1_instr_reg( tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_1_instr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_instr_act[1]), .act(iu3_instr_act[1]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2387,7 +2419,8 @@ generate
tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_2_instr_reg( tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_2_instr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_instr_act[2]), .act(iu3_instr_act[2]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2406,7 +2439,8 @@ generate
tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_3_instr_reg( tri_rlmreg_p #(.WIDTH(61), .INIT(0)) iu3_3_instr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_instr_act[3]), .act(iu3_instr_act[3]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2425,7 +2459,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_btb_redirect_reg( tri_rlmlatch_p #(.INIT(0)) iu3_btb_redirect_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2444,7 +2479,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_btb_misdirect_reg( tri_rlmlatch_p #(.INIT(0)) iu3_btb_misdirect_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2463,7 +2499,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu3_btb_link_reg( tri_rlmlatch_p #(.INIT(0)) iu3_btb_link_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2482,7 +2519,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_nfg_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu3_nfg_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_act), .act(iu3_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2501,7 +2539,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_redirect_ifar_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_redirect_ifar_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_redirect_act), .act(iu4_redirect_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2520,7 +2559,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu4_redirect_reg( tri_rlmlatch_p #(.INIT(0)) iu4_redirect_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2539,7 +2579,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu4_ls_push_reg( tri_rlmlatch_p #(.INIT(0)) iu4_ls_push_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2558,7 +2599,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu4_ls_pop_reg( tri_rlmlatch_p #(.INIT(0)) iu4_ls_pop_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2577,7 +2619,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_ifar_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu4_ifar_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_act), .act(iu4_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2597,7 +2640,8 @@ generate
tri_rlmreg_p #(.WIDTH(8), .INIT(128)) iu5_ls_t0_ptr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(128)) iu5_ls_t0_ptr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_ptr_act[0]), .act(iu5_ls_ptr_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2615,7 +2659,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t00_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t00_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[0]), .act(iu5_ls_t0_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2634,7 +2679,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t01_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t01_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[1]), .act(iu5_ls_t0_act[1]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2653,7 +2699,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t02_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t02_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[2]), .act(iu5_ls_t0_act[2]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2672,7 +2719,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t03_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t03_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[3]), .act(iu5_ls_t0_act[3]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2691,7 +2739,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t04_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t04_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[4]), .act(iu5_ls_t0_act[4]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2710,7 +2759,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t05_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t05_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[5]), .act(iu5_ls_t0_act[5]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2729,7 +2779,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t06_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t06_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[6]), .act(iu5_ls_t0_act[6]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2748,7 +2799,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t07_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) iu5_ls_t07_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_ls_t0_act[7]), .act(iu5_ls_t0_act[7]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2767,7 +2819,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t00_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t00_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[0]), .act(ex6_ls_t0_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2786,7 +2839,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t01_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t01_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[1]), .act(ex6_ls_t0_act[1]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2805,7 +2859,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t02_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t02_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[2]), .act(ex6_ls_t0_act[2]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2824,7 +2879,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t03_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t03_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[3]), .act(ex6_ls_t0_act[3]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2843,7 +2899,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t04_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t04_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[4]), .act(ex6_ls_t0_act[4]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2862,7 +2919,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t05_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t05_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[5]), .act(ex6_ls_t0_act[5]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2881,7 +2939,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t06_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t06_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[6]), .act(ex6_ls_t0_act[6]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2900,7 +2959,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t07_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex6_ls_t07_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_t0_act[7]), .act(ex6_ls_t0_act[7]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2918,7 +2978,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_val_reg( tri_rlmlatch_p #(.INIT(0)) ex5_val_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2937,7 +2998,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_ifar_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_ifar_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2956,7 +3018,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_bh_update_reg( tri_rlmlatch_p #(.INIT(0)) ex5_bh_update_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2975,7 +3038,8 @@ generate
tri_rlmreg_p #(.WIDTH(10), .INIT(0)) ex5_gshare_reg( tri_rlmreg_p #(.WIDTH(10), .INIT(0)) ex5_gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2994,7 +3058,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh0_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh0_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3013,7 +3078,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh1_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh1_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3032,7 +3098,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh2_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh2_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3051,7 +3118,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_br_pred_reg( tri_rlmlatch_p #(.INIT(0)) ex5_br_pred_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3070,7 +3138,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_br_taken_reg( tri_rlmlatch_p #(.INIT(0)) ex5_br_taken_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3089,7 +3158,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_bcctr_reg( tri_rlmlatch_p #(.INIT(0)) ex5_bcctr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3108,7 +3178,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_bclr_reg( tri_rlmlatch_p #(.INIT(0)) ex5_bclr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3127,7 +3198,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_getNIA_reg( tri_rlmlatch_p #(.INIT(0)) ex5_getNIA_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3146,7 +3218,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_lk_reg( tri_rlmlatch_p #(.INIT(0)) ex5_lk_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3165,7 +3238,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_bh_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3184,7 +3258,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_bta_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) ex5_bta_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3203,7 +3278,8 @@ generate
tri_rlmreg_p #(.WIDTH(8), .INIT(0)) ex5_ls_ptr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) ex5_ls_ptr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3222,7 +3298,8 @@ generate
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_btb_hist_reg( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) ex5_btb_hist_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_d), .act(ex5_val_d),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3241,7 +3318,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_btb_entry_reg( tri_rlmlatch_p #(.INIT(0)) ex5_btb_entry_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3260,7 +3338,8 @@ generate
tri_rlmreg_p #(.WIDTH(128), .INIT(0)) ex5_btb_repl_reg( tri_rlmreg_p #(.WIDTH(128), .INIT(0)) ex5_btb_repl_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex5_val_q), .act(ex5_val_q),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3279,7 +3358,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_ls_push_reg( tri_rlmlatch_p #(.INIT(0)) ex5_ls_push_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3298,7 +3378,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_ls_pop_reg( tri_rlmlatch_p #(.INIT(0)) ex5_ls_pop_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3317,7 +3398,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_group_reg( tri_rlmlatch_p #(.INIT(0)) ex5_group_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3335,7 +3417,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) ex5_flush_reg( tri_rlmlatch_p #(.INIT(0)) ex5_flush_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3354,7 +3437,8 @@ generate
tri_rlmreg_p #(.WIDTH(8), .INIT(128)) ex6_ls_t0_ptr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(128)) ex6_ls_t0_ptr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(ex6_ls_ptr_act), .act(ex6_ls_ptr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3373,7 +3457,8 @@ generate
tri_rlmreg_p #(.WIDTH(7), .INIT(0)) bp_config_reg( tri_rlmreg_p #(.WIDTH(7), .INIT(0)) bp_config_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3392,7 +3477,8 @@ generate
tri_rlmreg_p #(.WIDTH(18), .INIT(0)) br_iu_gshare_reg( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) br_iu_gshare_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3411,7 +3497,8 @@ generate
tri_rlmreg_p #(.WIDTH(8), .INIT(0)) br_iu_ls_ptr_reg( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) br_iu_ls_ptr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3430,7 +3517,8 @@ generate
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) br_iu_ls_data_reg( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0)) br_iu_ls_data_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3449,7 +3537,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) br_iu_ls_update_reg( tri_rlmlatch_p #(.INIT(0)) br_iu_ls_update_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3468,7 +3557,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_reg( tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3487,7 +3577,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) cp_flush_reg( tri_rlmlatch_p #(.INIT(0)) cp_flush_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3506,7 +3597,8 @@ generate
tri_rlmlatch_p #(.INIT(0)) iu_flush_reg( tri_rlmlatch_p #(.INIT(0)) iu_flush_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3524,7 +3616,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data0_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[0]), .act(bcache_shift[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3542,7 +3635,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data1_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[1]), .act(bcache_shift[1]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3560,7 +3654,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data2_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data2_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[2]), .act(bcache_shift[2]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3578,7 +3673,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data3_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data3_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[3]), .act(bcache_shift[3]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3596,7 +3692,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data4_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data4_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[4]), .act(bcache_shift[4]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3614,7 +3711,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data5_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data5_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[5]), .act(bcache_shift[5]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3633,7 +3731,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data6_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data6_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[6]), .act(bcache_shift[6]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3651,7 +3750,8 @@ generate
tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data7_reg( tri_rlmreg_p #(.WIDTH(16), .INIT(0)) bcache_data7_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(bcache_shift[7]), .act(bcache_shift[7]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3675,23 +3775,23 @@ generate
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
); );



tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0,pc_iu_sg_0})
); );



tri_lcbor perv_lcbor( tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b), .clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0), .thold(pc_iu_func_sl_thold_0),

@ -14,17 +14,17 @@
// necessary for implementation of the Work that are available from OpenPOWER // necessary for implementation of the Work that are available from OpenPOWER
// via the Power ISA End User License Agreement (EULA) are explicitly excluded // via the Power ISA End User License Agreement (EULA) are explicitly excluded
// hereunder, and may be obtained from OpenPOWER under the terms and conditions // hereunder, and may be obtained from OpenPOWER under the terms and conditions
// of the EULA. // of the EULA.
// //
// Unless required by applicable law or agreed to in writing, the reference design // Unless required by applicable law or agreed to in writing, the reference design
// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT // distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License // WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
// for the specific language governing permissions and limitations under the License. // for the specific language governing permissions and limitations under the License.
// //
// Additional rights, including the ability to physically implement a softcore that // Additional rights, including the ability to physically implement a softcore that
// is compliant with the required sections of the Power ISA Specification, are // is compliant with the required sections of the Power ISA Specification, are
// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be // available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
// obtained (along with the Power ISA) here: https://openpowerfoundation.org. // obtained (along with the Power ISA) here: https://openpowerfoundation.org.


`timescale 1 ns / 1 ns `timescale 1 ns / 1 ns


@ -43,7 +43,8 @@ module iuq_btb(
inout vcs, inout vcs,


// clock and clockcontrol ports // clock and clockcontrol ports
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input pc_iu_func_sl_thold_2, input pc_iu_func_sl_thold_2,
input pc_iu_sg_2, input pc_iu_sg_2,
input pc_iu_fce_2, input pc_iu_fce_2,
@ -169,7 +170,8 @@ module iuq_btb(
.vdd(vdd), .vdd(vdd),
.vcs(vcs), .vcs(vcs),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.sg_0(pc_iu_sg_0), .sg_0(pc_iu_sg_0),
.abst_sl_thold_0(tidn), .abst_sl_thold_0(tidn),
.ary_nsl_thold_0(tidn), .ary_nsl_thold_0(tidn),
@ -257,7 +259,8 @@ module iuq_btb(
tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg( tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_in_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -276,7 +279,8 @@ module iuq_btb(
tri_rlmlatch_p #(.INIT(0)) w_act_reg( tri_rlmlatch_p #(.INIT(0)) w_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -295,7 +299,8 @@ module iuq_btb(
tri_rlmlatch_p #(.INIT(0)) r_act_reg( tri_rlmlatch_p #(.INIT(0)) r_act_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -314,7 +319,8 @@ module iuq_btb(
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_wi_act), .act(lat_wi_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -333,7 +339,8 @@ module iuq_btb(
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) r_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ri_act), .act(lat_ri_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -352,7 +359,8 @@ module iuq_btb(
tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg( tri_rlmreg_p #(.WIDTH((2*`EFF_IFAR_WIDTH+2+1)), .INIT(0)) data_out_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lat_ro_act), .act(lat_ro_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -370,7 +378,8 @@ module iuq_btb(
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) reset_w_addr_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reset_act), .act(reset_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -389,27 +398,26 @@ module iuq_btb(
// pervasive // pervasive
//----------------------------------------------- //-----------------------------------------------



tri_plat #(.WIDTH(3)) perv_2to1_reg( tri_plat #(.WIDTH(3)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}), .din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_fce_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}) .q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1})
); );



tri_plat #(.WIDTH(3)) perv_1to0_reg( tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}), .din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_fce_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0}) .q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_fce_0})
); );



tri_lcbor perv_lcbor( tri_lcbor perv_lcbor(
.clkoff_b(clkoff_b), .clkoff_b(clkoff_b),
.thold(pc_iu_func_sl_thold_0), .thold(pc_iu_func_sl_thold_0),

@ -36,7 +36,8 @@


module iuq_cpl( module iuq_cpl(
// Clocks // Clocks
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,


// Pervasive // Pervasive
input tc_ac_ccflush_dc, input tc_ac_ccflush_dc,
@ -977,7 +978,8 @@ module iuq_cpl(




iuq_cpl_ctrl iuq_cpl_ctrl( iuq_cpl_ctrl iuq_cpl_ctrl(
.nclk(nclk), .clk(clk),
.rst(rst),
.d_mode_dc(d_mode_dc), .d_mode_dc(d_mode_dc),
.delay_lclkr_dc(delay_lclkr_dc), .delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b), .mpw1_dc_b(mpw1_dc_b),
@ -1527,7 +1529,8 @@ module iuq_cpl(
iuq_cpl_arr( // bitwidth of ports iuq_cpl_arr( // bitwidth of ports
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.nclk(nclk), .clk(clk),
.rst(rst),
.delay_lclkr_dc(delay_lclkr_dc), .delay_lclkr_dc(delay_lclkr_dc),
.mpw1_dc_b(mpw1_dc_b), .mpw1_dc_b(mpw1_dc_b),
.mpw2_dc_b(mpw2_dc_b), .mpw2_dc_b(mpw2_dc_b),
@ -1554,7 +1557,8 @@ module iuq_cpl(
// Latch Instances // Latch Instances


tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) xer_cp_p_latch( tri_rlmreg_p #(.WIDTH(`XER_POOL_ENC), .INIT(0), .NEEDS_SRESET(1)) xer_cp_p_latch(
.nclk(nclk), .clk(clk),
.rst(rst),
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.act(tiup), .act(tiup),
@ -1578,7 +1582,8 @@ module iuq_cpl(
tri_plat #(.WIDTH(3)) perv_2to1_reg( tri_plat #(.WIDTH(3)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({func_sl_thold_2, func_slp_sl_thold_2, sg_2}), .din({func_sl_thold_2, func_slp_sl_thold_2, sg_2}),
.q({func_sl_thold_1, func_slp_sl_thold_1, sg_1}) .q({func_sl_thold_1, func_slp_sl_thold_1, sg_1})
@ -1587,7 +1592,8 @@ module iuq_cpl(
tri_plat #(.WIDTH(3)) perv_1to0_reg( tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({func_sl_thold_1, func_slp_sl_thold_1, sg_1}), .din({func_sl_thold_1, func_slp_sl_thold_1, sg_1}),
.q({func_sl_thold_0, func_slp_sl_thold_0, sg_0}) .q({func_sl_thold_0, func_slp_sl_thold_0, sg_0})

File diff suppressed because it is too large Load Diff

@ -36,8 +36,8 @@


module iuq_cpl_top( module iuq_cpl_top(
// Clocks // Clocks
(* pin_data="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,


// Pervasive // Pervasive
input tc_ac_ccflush_dc, input tc_ac_ccflush_dc,
@ -757,7 +757,8 @@ module iuq_cpl_top(
iuq_cpl iuq_cpl0( iuq_cpl iuq_cpl0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.clkoff_dc_b(clkoff_dc_b), .clkoff_dc_b(clkoff_dc_b),
.d_mode_dc(d_mode_dc), .d_mode_dc(d_mode_dc),
@ -1129,7 +1130,8 @@ module iuq_cpl_top(
iuq_cpl iuq_cpl1( iuq_cpl iuq_cpl1(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.tc_ac_ccflush_dc(tc_ac_ccflush_dc), .tc_ac_ccflush_dc(tc_ac_ccflush_dc),
.clkoff_dc_b(clkoff_dc_b), .clkoff_dc_b(clkoff_dc_b),
.d_mode_dc(d_mode_dc), .d_mode_dc(d_mode_dc),
@ -1499,7 +1501,8 @@ module iuq_cpl_top(
iuq_dbg iuq_cpl_dbg( iuq_dbg iuq_cpl_dbg(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.thold_2(pc_iu_func_sl_thold_2), .thold_2(pc_iu_func_sl_thold_2),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.clkoff_b(clkoff_b), .clkoff_b(clkoff_b),

@ -42,8 +42,8 @@ module iuq_dbg(
inout vdd, inout vdd,
inout gnd, inout gnd,


(* pin_data ="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,
input thold_2, // Connect to slp if unit uses slp input thold_2, // Connect to slp if unit uses slp
input pc_iu_sg_2, input pc_iu_sg_2,
input clkoff_b, input clkoff_b,
@ -156,7 +156,8 @@ module iuq_dbg(
tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch( tri_rlmlatch_p #(.INIT(0)) trace_bus_enable_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -174,7 +175,8 @@ module iuq_dbg(
tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch( tri_rlmreg_p #(.WIDTH(11), .INIT(0)) debug_mux_ctrls_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(trace_bus_enable_q), .act(trace_bus_enable_q),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -192,7 +194,8 @@ module iuq_dbg(
tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) trace_data_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(trace_bus_enable_q), .act(trace_bus_enable_q),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -210,7 +213,8 @@ module iuq_dbg(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) coretrace_ctrls_out_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(trace_bus_enable_q), .act(trace_bus_enable_q),
.thold_b(thold_0_b), .thold_b(thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -231,7 +235,8 @@ module iuq_dbg(
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({thold_2, pc_iu_sg_2}), .din({thold_2, pc_iu_sg_2}),
.q( {thold_1, pc_iu_sg_1}) .q( {thold_1, pc_iu_sg_1})
@ -240,7 +245,8 @@ module iuq_dbg(
tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({thold_1, pc_iu_sg_1}), .din({thold_1, pc_iu_sg_1}),
.q( {thold_0, pc_iu_sg_0}) .q( {thold_0, pc_iu_sg_0})

@ -42,7 +42,8 @@
module iuq_dec_top( module iuq_dec_top(
inout vdd, inout vdd,
inout gnd, inout gnd,
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input pc_iu_sg_2, input pc_iu_sg_2,
input pc_iu_func_sl_thold_2, input pc_iu_func_sl_thold_2,
input clkoff_b, input clkoff_b,
@ -301,7 +302,8 @@ module iuq_dec_top(
iuq_idec fx_dec0( iuq_idec fx_dec0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.clkoff_b(clkoff_b), .clkoff_b(clkoff_b),
@ -444,7 +446,8 @@ module iuq_dec_top(
iuq_idec fx_dec1( iuq_idec fx_dec1(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),
.clkoff_b(clkoff_b), .clkoff_b(clkoff_b),
@ -587,7 +590,8 @@ module iuq_dec_top(
iuq_axu_fu_dec axu_dec0( iuq_axu_fu_dec axu_dec0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.i_dec_si(scan_in[2]), .i_dec_si(scan_in[2]),
.i_dec_so(scan_out[2]), .i_dec_so(scan_out[2]),
.pc_iu_sg_2(pc_iu_sg_2), .pc_iu_sg_2(pc_iu_sg_2),
@ -649,7 +653,8 @@ module iuq_dec_top(
iuq_axu_fu_dec axu_dec1( iuq_axu_fu_dec axu_dec1(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.i_dec_si(scan_in[3]), .i_dec_si(scan_in[3]),
.i_dec_so(scan_out[3]), .i_dec_so(scan_out[3]),
.pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2), .pc_iu_func_sl_thold_2(pc_iu_func_sl_thold_2),

@ -40,7 +40,8 @@
module iuq_dispatch( module iuq_dispatch(
inout vdd, inout vdd,
inout gnd, inout gnd,
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input pc_iu_sg_2, input pc_iu_sg_2,
input pc_iu_func_sl_thold_2, input pc_iu_func_sl_thold_2,
input pc_iu_func_slp_sl_thold_2, input pc_iu_func_slp_sl_thold_2,
@ -2965,7 +2966,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES - 2)) fx0_high_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES - 2)) fx0_high_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -2983,7 +2985,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES - 2)) fx1_high_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES - 2)) fx1_high_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3001,7 +3004,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES - 2)) lq_cmdq_high_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES - 2)) lq_cmdq_high_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3019,7 +3023,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES - 2)) sq_cmdq_high_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES - 2)) sq_cmdq_high_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3037,7 +3042,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES - 2)) fu0_high_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES - 2)) fu0_high_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3055,7 +3061,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES - 2)) fu1_high_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES - 2)) fu1_high_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3073,7 +3080,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES / 2)) fx0_med_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES / 2)) fx0_med_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3091,7 +3099,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES / 2)) fx1_med_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES / 2)) fx1_med_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3109,7 +3118,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES / 2)) lq_cmdq_med_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES / 2)) lq_cmdq_med_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3127,7 +3137,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES / 2)) sq_cmdq_med_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES / 2)) sq_cmdq_med_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3145,7 +3156,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES / 2)) fu0_med_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES / 2)) fu0_med_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3163,7 +3175,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES / 2)) fu1_med_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES / 2)) fu1_med_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3184,7 +3197,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES)) fx0_total_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX0_ENTRIES)) fx0_total_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3202,7 +3216,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES)) fx1_total_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_FX1_ENTRIES)) fx1_total_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3220,7 +3235,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES)) lq_cmdq_total_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`LDSTQ_ENTRIES)) lq_cmdq_total_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3238,7 +3254,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES)) sq_cmdq_total_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`STQ_ENTRIES)) sq_cmdq_total_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3256,7 +3273,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES)) fu0_total_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU0_ENTRIES)) fu0_total_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3274,7 +3292,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES)) fu1_total_credit_cnt_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(`RV_AXU1_ENTRIES)) fu1_total_credit_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3292,7 +3311,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3310,7 +3330,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3328,7 +3349,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmlatch_p #(.INIT(0)) iu_xu_credits_returned_latch( tri_rlmlatch_p #(.INIT(0)) iu_xu_credits_returned_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3347,7 +3369,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) dual_issue_use_fx0_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) dual_issue_use_fx0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3365,7 +3388,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1)) last_thread_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(1)) last_thread_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(last_thread_act), .act(last_thread_act),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3383,7 +3407,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3401,7 +3426,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_done_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_done_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3419,7 +3445,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3437,7 +3464,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_done_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_done_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3455,7 +3483,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch( tri_rlmlatch_p #(.INIT(0)) hold_instructions_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -3473,7 +3502,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3491,7 +3521,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ivax_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ivax_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3509,7 +3540,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_done_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) hold_done_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3527,7 +3559,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_flush_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_flush_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3545,7 +3578,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_hold_done_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_hold_done_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3563,7 +3597,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3581,7 +3616,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_done_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_iu_bus_snoop_hold_done_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(funcslp_force), .force_t(funcslp_force),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
@ -3599,7 +3635,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_ucode_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3617,7 +3654,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_fusion_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) in_fusion_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3635,7 +3673,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) total_pri_mask_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) total_pri_mask_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3653,7 +3692,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) high_pri_mask_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) high_pri_mask_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3671,7 +3711,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) med_pri_mask_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) med_pri_mask_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3689,7 +3730,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) low_pri_mask_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) low_pri_mask_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3712,7 +3754,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(8), .INIT(0)) low_pri_cnt_latch( tri_rlmreg_p #(.WIDTH(8), .INIT(0)) low_pri_cnt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(low_pri_cnt_act[i]), .act(low_pri_cnt_act[i]),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3730,7 +3773,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) low_pri_max_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) low_pri_max_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3751,7 +3795,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3774,7 +3819,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx0_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3792,7 +3838,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx1_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_fx1_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3810,7 +3857,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_lq_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_lq_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3828,7 +3876,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu0_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3846,7 +3895,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu1_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_iu6_dispatch_axu1_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3867,7 +3917,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx0_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx0_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3885,7 +3936,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx1_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_fx1_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3903,7 +3955,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_lq_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_lq_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3921,7 +3974,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_sq_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_sq_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3939,7 +3993,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu0_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu0_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3957,7 +4012,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu1_credit_stall_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) perf_iu6_axu1_credit_stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3975,7 +4031,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx0_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx0_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -3993,7 +4050,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx1_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_fx1_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -4011,7 +4069,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_lq_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_lq_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -4029,7 +4088,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_sq_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_sq_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -4047,7 +4107,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu0_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu0_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -4065,7 +4126,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu1_credit_ok_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu_pc_axu1_credit_ok_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.force_t(force_t), .force_t(force_t),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
@ -4089,7 +4151,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_plat #(.WIDTH(3)) perv_2to1_reg( tri_plat #(.WIDTH(3)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2, pc_iu_func_slp_sl_thold_2, pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1})
@ -4098,7 +4161,8 @@ assign iu_xu_credits_returned = iu_xu_credits_returned_l2;
tri_plat #(.WIDTH(3)) perv_1to0_reg( tri_plat #(.WIDTH(3)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1, pc_iu_func_slp_sl_thold_1, pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0, pc_iu_func_slp_sl_thold_0, pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0, pc_iu_func_slp_sl_thold_0, pc_iu_sg_0})

@ -41,7 +41,8 @@
module iuq_ibuf( module iuq_ibuf(
inout vdd, inout vdd,
inout gnd, inout gnd,
input [0:`NCLK_WIDTH-1] nclk, input clk,
input rst,
input pc_iu_sg_2, input pc_iu_sg_2,
input pc_iu_func_sl_thold_2, input pc_iu_func_sl_thold_2,
input clkoff_b, input clkoff_b,
@ -805,7 +806,8 @@ assign ib_id_iu4_1_fuse_data = iu4_1_fuse_data_q;
tri_rlmlatch_p #(.INIT(0)) uc_select_latch( tri_rlmlatch_p #(.INIT(0)) uc_select_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -824,7 +826,8 @@ tri_rlmlatch_p #(.INIT(0)) uc_select_latch(
tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(buffer_valid_act), .act(buffer_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -843,7 +846,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(0)) buffer_valid_latch(
tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(buffer_head_act), .act(buffer_head_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -862,7 +866,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_head_latch(
tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(buffer_tail_act), .act(buffer_tail_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -881,7 +886,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_DEPTH), .INIT(1)) buffer_tail_latch(
tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_latch( tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu3_val[0]), //tiup, .act(iu3_val[0]), //tiup,
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -900,7 +906,8 @@ tri_rlmreg_p #(.WIDTH((`IBUFF_DEPTH*IBUFF_WIDTH-1+1)), .INIT(0)) buffer_array_la
tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch( tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stall_buffer_act[0]), .act(stall_buffer_act[0]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -919,7 +926,8 @@ tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data0_latch(
tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch( tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stall_buffer_act[1]), .act(stall_buffer_act[1]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -938,7 +946,8 @@ tri_rlmreg_p #(.WIDTH(IDATA_WIDTH), .INIT(0)) stall_buffer_data1_latch(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -957,7 +966,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) stall_latch(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -976,7 +986,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu4_uc_mode_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -995,7 +1006,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_valid_latch(
tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1014,7 +1026,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_0_instr_latch(
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1033,7 +1046,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_ifar_latch(
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1052,7 +1066,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_0_bta_latch(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1071,7 +1086,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_0_ucode_latch(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1090,7 +1106,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_0_ucode_ext_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_valid_din), .act(iu4_0_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1109,7 +1126,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_isram_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch( tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1128,7 +1146,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_0_fuse_val_latch(
tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_0_fuse_val_din), .act(iu4_0_fuse_val_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1147,7 +1166,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_0_fuse_data_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1166,7 +1186,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_valid_latch(
tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch( tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1185,7 +1206,8 @@ tri_rlmreg_p #(.WIDTH(`IBUFF_INSTR_WIDTH), .INIT(0)) iu4_1_instr_latch(
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1204,7 +1226,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_ifar_latch(
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1223,7 +1246,8 @@ tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu4_1_bta_latch(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1242,7 +1266,8 @@ tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu4_1_ucode_latch(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1261,7 +1286,8 @@ tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu4_1_ucode_ext_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_valid_din), .act(iu4_1_valid_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1280,7 +1306,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_isram_latch(
tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch( tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1299,7 +1326,8 @@ tri_rlmlatch_p #(.INIT(0)) iu4_1_fuse_val_latch(
tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu4_1_fuse_val_din), .act(iu4_1_fuse_val_din),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1318,7 +1346,8 @@ tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu4_1_fuse_data_latch(
tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1337,7 +1366,8 @@ tri_rlmlatch_p #(.INIT(0)) cp_flush_latch(
tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch( tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1356,7 +1386,8 @@ tri_rlmlatch_p #(.INIT(0)) br_iu_redirect_latch(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1380,7 +1411,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch(
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
@ -1390,7 +1422,8 @@ tri_rlmreg_p #(.WIDTH(2), .INIT(0)) cp_flush_into_uc_latch(
tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0,pc_iu_sg_0})

@ -42,8 +42,8 @@ module iuq_ic(
inout vcs, inout vcs,
inout vdd, inout vdd,
inout gnd, inout gnd,
(* pin_data="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,


input tc_ac_ccflush_dc, input tc_ac_ccflush_dc,
input tc_ac_scan_dis_dc_b, input tc_ac_scan_dis_dc_b,
@ -527,9 +527,8 @@ module iuq_ic(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(vdd),

.clk(clk),
// CLOCK and CLOCKCONTROL ports .rst(rst),
.nclk(nclk),
.pc_iu_init_reset(pc_iu_init_reset), .pc_iu_init_reset(pc_iu_init_reset),
.tc_ccflush_dc(tc_ac_ccflush_dc), .tc_ccflush_dc(tc_ac_ccflush_dc),
.tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b), .tc_scan_dis_dc_b(tc_ac_scan_dis_dc_b),
@ -697,7 +696,8 @@ module iuq_ic(
iuq_ic_select iuq_ic_select0( iuq_ic_select iuq_ic_select0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0), .pc_iu_sg_0(pc_iu_sg_0),
@ -828,7 +828,8 @@ module iuq_ic(
.vcs(vdd), .vcs(vdd),
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b), .pc_iu_func_slp_sl_thold_0_b(pc_iu_func_slp_sl_thold_0_b),
.pc_iu_time_sl_thold_0(pc_iu_time_sl_thold_0), .pc_iu_time_sl_thold_0(pc_iu_time_sl_thold_0),
@ -1013,11 +1014,11 @@ module iuq_ic(
.event_bus_enable(pc_iu_event_bus_enable) .event_bus_enable(pc_iu_event_bus_enable)
); );



iuq_ic_miss iuq_ic_miss0( iuq_ic_miss iuq_ic_miss0(
.vdd(vdd), .vdd(vdd),
.gnd(gnd), .gnd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b), .pc_iu_func_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
.pc_iu_sg_0(pc_iu_sg_0), .pc_iu_sg_0(pc_iu_sg_0),
.force_t(force_t), .force_t(force_t),
@ -1153,7 +1154,8 @@ module iuq_ic(
tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0)) perf_bus_latch( tri_rlmreg_p #(.WIDTH(4*`THREADS), .INIT(0)) perf_bus_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_event_bus_enable), .act(pc_iu_event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1177,7 +1179,8 @@ module iuq_ic(
tri_plat #(.WIDTH(1)) perv_3to2_reg( tri_plat #(.WIDTH(1)) perv_3to2_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din(pc_iu_bo_enable_3), .din(pc_iu_bo_enable_3),
.q(pc_iu_bo_enable_2) .q(pc_iu_bo_enable_2)
@ -1186,7 +1189,8 @@ module iuq_ic(
tri_plat #(.WIDTH(11)) perv_2to1_reg( tri_plat #(.WIDTH(11)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2, .din({pc_iu_func_sl_thold_2,
pc_iu_func_slp_sl_thold_2, pc_iu_func_slp_sl_thold_2,
@ -1215,7 +1219,8 @@ module iuq_ic(
tri_plat #(.WIDTH(11)) perv_1to0_reg( tri_plat #(.WIDTH(11)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1, .din({pc_iu_func_sl_thold_1,
pc_iu_func_slp_sl_thold_1, pc_iu_func_slp_sl_thold_1,

@ -42,8 +42,8 @@ module iuq_ic_dir(
inout vcs, inout vcs,
inout vdd, inout vdd,
inout gnd, inout gnd,
(* pin_data ="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,
input pc_iu_func_sl_thold_0_b, input pc_iu_func_sl_thold_0_b,
input pc_iu_func_slp_sl_thold_0_b, input pc_iu_func_slp_sl_thold_0_b,
input pc_iu_time_sl_thold_0, input pc_iu_time_sl_thold_0,
@ -718,8 +718,9 @@ module iuq_ic_dir(
tri_128x34_4w_1r1w idir( tri_128x34_4w_1r1w idir(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(),
.nclk(nclk), .clk(clk),
.rst(rst),
.rd_act(dir_rd_act), .rd_act(dir_rd_act),
.wr_act(dir_write), .wr_act(dir_write),
.sg_0(pc_iu_sg_0), .sg_0(pc_iu_sg_0),
@ -866,8 +867,9 @@ module iuq_ic_dir(
tri_512x162_4w_0 idata( tri_512x162_4w_0 idata(
.gnd(gnd), .gnd(gnd),
.vdd(vdd), .vdd(vdd),
.vcs(vdd), .vcs(),
.nclk(nclk), .clk(clk),
.rst(rst),
.ccflush_dc(tc_ac_ccflush_dc), .ccflush_dc(tc_ac_ccflush_dc),
.lcb_clkoff_dc_b(g6t_clkoff_b), .lcb_clkoff_dc_b(g6t_clkoff_b),
.lcb_d_mode_dc(g6t_d_mode), .lcb_d_mode_dc(g6t_d_mode),
@ -1436,7 +1438,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_valid_latch( tri_rlmlatch_p #(.INIT(0)) iu1_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1466,7 +1469,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_tid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), // ??? Is this act worth it? Only tid, 2ucode, & 2ucode_type use for non-slp .act(dir_rd_act), // ??? Is this act worth it? Only tid, 2ucode, & 2ucode_type use for non-slp
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1487,7 +1491,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(0)) iu1_ifar_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0), .NEEDS_SRESET(0)) iu1_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), .act(dir_rd_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1505,7 +1510,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_index51_latch( tri_rlmlatch_p #(.INIT(0)) iu1_index51_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), .act(dir_rd_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1523,7 +1529,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_inval_latch( tri_rlmlatch_p #(.INIT(0)) iu1_inval_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1541,7 +1548,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_prefetch_latch( tri_rlmlatch_p #(.INIT(0)) iu1_prefetch_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1570,7 +1578,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_read_erat_latch( tri_rlmlatch_p #(.INIT(0)) iu1_read_erat_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), .act(dir_rd_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1590,7 +1599,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_latch( tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), .act(dir_rd_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1608,7 +1618,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_type_latch( tri_rlmlatch_p #(.INIT(0)) iu1_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_rd_act), .act(dir_rd_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1627,7 +1638,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_valid_latch( tri_rlmlatch_p #(.INIT(0)) iu2_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1656,7 +1668,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_tid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1676,7 +1689,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH-10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH-10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1695,7 +1709,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_slp_latch( tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(0)) iu2_ifar_eff_slp_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1713,7 +1728,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_latch( tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu1_valid_l2), .act(iu1_valid_l2),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1731,7 +1747,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_type_latch( tri_rlmlatch_p #(.INIT(0)) iu2_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu1_valid_l2), .act(iu1_valid_l2),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1749,7 +1766,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_index51_latch( tri_rlmlatch_p #(.INIT(0)) iu2_index51_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1767,7 +1785,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_inval_latch( tri_rlmlatch_p #(.INIT(0)) iu2_inval_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1785,7 +1804,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_prefetch_latch( tri_rlmlatch_p #(.INIT(0)) iu2_prefetch_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1816,7 +1836,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_read_erat_latch( tri_rlmlatch_p #(.INIT(0)) iu2_read_erat_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1834,7 +1855,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_cam_change_etc_latch( tri_rlmlatch_p #(.INIT(0)) iu2_cam_change_etc_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1854,7 +1876,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0), .NEEDS_SRESET(0)) iu2_stored_rpn_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0), .NEEDS_SRESET(0)) iu2_stored_rpn_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1872,7 +1895,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu2_dir_rd_val_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu2_dir_rd_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1890,7 +1914,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_dir_parity_err_way_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_dir_parity_err_way_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1915,7 +1940,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) dir_val_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) dir_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_val_act), .act(dir_val_act),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1933,7 +1959,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) dir_lru_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) dir_lru_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_lru_act[a/8]), .act(dir_lru_act[a/8]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1954,7 +1981,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu3_miss_flush( tri_rlmlatch_p #(.INIT(0)) iu3_miss_flush(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1984,7 +2012,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu3_tid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu3_tid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2004,7 +2033,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH), .INIT(0), .NEEDS_SRESET(0)) iu3_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu2_valid_l2), .act(iu2_valid_l2),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2022,7 +2052,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_latch( tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu2_valid_l2), .act(iu2_valid_l2),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2040,7 +2071,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_type_latch( tri_rlmlatch_p #(.INIT(0)) iu3_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu2_valid_l2), .act(iu2_valid_l2),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2058,7 +2090,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(1), .INIT(0)) iu3_erat_err_latch( tri_rlmreg_p #(.WIDTH(1), .INIT(0)) iu3_erat_err_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2076,7 +2109,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_multihit_err_way_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_multihit_err_way_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2094,7 +2128,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu3_multihit_flush_latch( tri_rlmlatch_p #(.INIT(0)) iu3_multihit_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2112,7 +2147,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_data_parity_err_way_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu3_data_parity_err_way_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2130,7 +2166,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu3_parity_needs_flush_latch( tri_rlmlatch_p #(.INIT(0)) iu3_parity_needs_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2148,7 +2185,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) iu3_parity_tag_latch( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) iu3_parity_tag_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2166,7 +2204,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) ici_val_latch( tri_rlmlatch_p #(.INIT(0)) ici_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2184,7 +2223,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2202,7 +2242,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) spr_ic_idir_way_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) spr_ic_idir_way_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2220,7 +2261,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu1_spr_idir_read_latch( tri_rlmlatch_p #(.INIT(0)) iu1_spr_idir_read_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2238,7 +2280,8 @@ module iuq_ic_dir(
tri_rlmlatch_p #(.INIT(0)) iu2_spr_idir_read_latch( tri_rlmlatch_p #(.INIT(0)) iu2_spr_idir_read_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2256,7 +2299,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_spr_idir_lru_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu2_spr_idir_lru_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(dir_dataout_act), .act(dir_dataout_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2294,7 +2338,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0)) stored_erat_rpn_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-12), .INIT(0)) stored_erat_rpn_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stored_erat_act[i]), .act(stored_erat_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2312,7 +2357,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) stored_erat_wimge_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) stored_erat_wimge_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stored_erat_act[i]), .act(stored_erat_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2330,7 +2376,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stored_erat_u_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) stored_erat_u_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stored_erat_act[i]), .act(stored_erat_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2357,7 +2404,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_instr_count_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_instr_count_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2375,7 +2423,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_t_event_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_t_event_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2396,7 +2445,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_event_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) perf_event_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2414,7 +2464,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_iu_inj_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) pc_iu_inj_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2439,7 +2490,8 @@ module iuq_ic_dir(
tri_rlmreg_p #(.INIT(0), .WIDTH(41), .NEEDS_SRESET(0)) ab_reg( tri_rlmreg_p #(.INIT(0), .WIDTH(41), .NEEDS_SRESET(0)) ab_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(pc_iu_abist_ena_dc), .act(pc_iu_abist_ena_dc),
.thold_b(pc_iu_abst_sl_thold_0_b), .thold_b(pc_iu_abst_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),

File diff suppressed because it is too large Load Diff

@ -42,7 +42,8 @@
module iuq_ic_miss( module iuq_ic_miss(
vdd, vdd,
gnd, gnd,
nclk, clk,
rst,
pc_iu_func_sl_thold_0_b, pc_iu_func_sl_thold_0_b,
pc_iu_sg_0, pc_iu_sg_0,
force_t, force_t,
@ -133,11 +134,10 @@ module iuq_ic_miss(




inout vdd; inout vdd;

inout gnd; inout gnd;


(* pin_data ="PIN_FUNCTION=/G_CLK/" *) input clk;
input [0:`NCLK_WIDTH-1] nclk; input rst;
input pc_iu_func_sl_thold_0_b; input pc_iu_func_sl_thold_0_b;
input pc_iu_sg_0; input pc_iu_sg_0;
input force_t; input force_t;
@ -1438,7 +1438,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch( tri_rlmlatch_p #(.INIT(0)) spr_ic_cls_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1456,7 +1457,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) bp_config_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) bp_config_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1474,7 +1476,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) an_ac_reld_data_vld_latch( tri_rlmlatch_p #(.INIT(0)) an_ac_reld_data_vld_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1492,7 +1495,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) an_ac_reld_core_tag_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) an_ac_reld_core_tag_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1510,7 +1514,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) an_ac_reld_qw_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) an_ac_reld_qw_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1528,7 +1533,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r1_val_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r1_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1546,7 +1552,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r1_qw_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r1_qw_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1564,7 +1571,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(128), .INIT(0)) reld_data_latch( tri_rlmreg_p #(.WIDTH(128), .INIT(0)) reld_data_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reld_r2_act), .act(reld_r2_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1582,7 +1590,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r2_val_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r2_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1600,7 +1609,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r2_qw_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) reld_r2_qw_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reld_r2_act), .act(reld_r2_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1618,7 +1628,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) r2_crit_qw_latch( tri_rlmlatch_p #(.INIT(0)) r2_crit_qw_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1636,7 +1647,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r3_val_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) reld_r3_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1654,7 +1666,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) r3_loaded_latch( tri_rlmlatch_p #(.INIT(0)) r3_loaded_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1672,7 +1685,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_latch( tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1690,7 +1704,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_ue_latch( tri_rlmlatch_p #(.INIT(0)) an_ac_reld_ecc_err_ue_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1708,7 +1723,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) request_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) request_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_or_default_act), .act(miss_or_default_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1726,7 +1742,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) req_ctag_latch( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) req_ctag_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(icd_icm_any_iu2_valid), .act(icd_icm_any_iu2_valid),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1744,7 +1761,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0)) req_ra_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-4), .INIT(0)) req_ra_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(icd_icm_any_iu2_valid), .act(icd_icm_any_iu2_valid),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1762,7 +1780,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(5), .INIT(0)) req_wimge_latch( tri_rlmreg_p #(.WIDTH(5), .INIT(0)) req_wimge_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(icd_icm_any_iu2_valid), .act(icd_icm_any_iu2_valid),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1780,7 +1799,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) req_userdef_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) req_userdef_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(icd_icm_any_iu2_valid), .act(icd_icm_any_iu2_valid),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1798,7 +1818,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) iu3_miss_match_latch( tri_rlmlatch_p #(.INIT(0)) iu3_miss_match_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(icd_icm_any_iu2_valid), .act(icd_icm_any_iu2_valid),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1822,7 +1843,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(CHECK_ECC+1), .INIT({1'b1, {CHECK_ECC{1'b0}} })) miss_tid_sm_latch( tri_rlmreg_p #(.WIDTH(CHECK_ECC+1), .INIT({1'b1, {CHECK_ECC{1'b0}} })) miss_tid_sm_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_or_default_act), .act(miss_or_default_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1840,7 +1862,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) miss_count_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) miss_count_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_or_default_act), .act(miss_or_default_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1861,7 +1884,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flush_occurred_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flush_occurred_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1879,7 +1903,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flushed_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_flushed_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1897,7 +1922,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_inval_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_inval_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1915,7 +1941,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_block_fp_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_block_fp_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_or_default_act), .act(miss_or_default_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1933,7 +1960,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1951,7 +1979,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_ue_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) miss_ecc_err_ue_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1969,7 +1998,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_wrote_dir_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_wrote_dir_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1987,7 +2017,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_need_hold_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0), .NEEDS_SRESET(1)) miss_need_hold_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_or_default_act), .act(miss_or_default_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2010,7 +2041,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH - 2), .INIT(0)) miss_addr_real_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH - 2), .INIT(0)) miss_addr_real_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2028,7 +2060,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH - 10), .INIT(0)) miss_addr_eff_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH - 10), .INIT(0)) miss_addr_eff_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2046,7 +2079,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) miss_ci_latch( tri_rlmlatch_p #(.INIT(0)) miss_ci_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2064,7 +2098,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) miss_endian_latch( tri_rlmlatch_p #(.INIT(0)) miss_endian_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2082,7 +2117,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) miss_2ucode_latch( tri_rlmlatch_p #(.INIT(0)) miss_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2100,7 +2136,8 @@ assign next_lru_way[3] =
tri_rlmlatch_p #(.INIT(0)) miss_2ucode_type_latch( tri_rlmlatch_p #(.INIT(0)) miss_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(miss_act[i]), .act(miss_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2118,7 +2155,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) miss_way_latch( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) miss_way_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(reld_r2_act), .act(reld_r2_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2139,7 +2177,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_next_cycle_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_next_cycle_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2157,7 +2196,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_latch( tri_rlmreg_p #(.WIDTH(TAGS_USED), .INIT(0)) lru_write_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(default_reld_act), .act(default_reld_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2180,7 +2220,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_event_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) perf_event_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -2201,7 +2242,8 @@ assign next_lru_way[3] =
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) miss_prefetch_perf_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) miss_prefetch_perf_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),

@ -42,8 +42,8 @@ module iuq_ic_select(
inout vdd, inout vdd,
inout gnd, inout gnd,


(* pin_data ="PIN_FUNCTION=/G_CLK/" *) input clk,
input [0:`NCLK_WIDTH-1] nclk, input rst,
input pc_iu_func_sl_thold_0_b, input pc_iu_func_sl_thold_0_b,
input pc_iu_func_slp_sl_thold_0_b, input pc_iu_func_slp_sl_thold_0_b,
input pc_iu_sg_0, input pc_iu_sg_0,
@ -1055,7 +1055,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_latch( tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1073,7 +1074,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_target_latch( tri_rlmlatch_p #(.INIT(0)) an_ac_back_inv_target_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1091,7 +1093,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) an_ac_back_inv_addr_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) an_ac_back_inv_addr_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(back_inv_addr_act), //back_inv_d, .act(back_inv_addr_act), //back_inv_d,
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1109,7 +1112,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_idir_read_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) spr_idir_read_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1127,7 +1131,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) spr_idir_row_latch( tri_rlmreg_p #(.WIDTH(7), .INIT(0), .NEEDS_SRESET(0)) spr_idir_row_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1154,7 +1159,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) oldest_prefetch_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) oldest_prefetch_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1175,7 +1181,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_need_prefetch_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_need_prefetch_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1198,7 +1205,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-4), .INIT(0)) iu0_prefetch_ifar_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-4), .INIT(0)) iu0_prefetch_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu0_prefetch_ifar_act[i]), .act(iu0_prefetch_ifar_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1219,7 +1227,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH((`THREADS*`THREADS-1+1)), .INIT(0)) lq_iu_icbi_val_latch( tri_rlmreg_p #(.WIDTH((`THREADS*`THREADS-1+1)), .INIT(0)) lq_iu_icbi_val_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1242,7 +1251,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) lq_iu_icbi_addr_latch( tri_rlmreg_p #(.WIDTH(`REAL_IFAR_WIDTH-6), .INIT(0)) lq_iu_icbi_addr_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(lq_iu_icbi_val[i]), .act(lq_iu_icbi_val[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1263,7 +1273,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0)) back_inv_latch( tri_rlmlatch_p #(.INIT(0)) back_inv_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1281,7 +1292,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) back_inv_icbi_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) back_inv_icbi_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1299,7 +1311,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_run_thread_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1317,7 +1330,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1335,7 +1349,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm2_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm2_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1353,7 +1368,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm3_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) xu_iu_msr_cm3_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1371,7 +1387,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_ic_stop_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_ic_stop_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1389,7 +1406,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) pc_iu_pm_fetch_halt_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) pc_iu_pm_fetch_halt_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1407,7 +1425,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ierat_hold_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) ierat_hold_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1425,7 +1444,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1443,7 +1463,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_type_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1461,7 +1482,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_flip_index51_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu0_flip_index51_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1488,7 +1510,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0)) iu0_last_tid_sent_latch( tri_rlmlatch_p #(.INIT(0)) iu0_last_tid_sent_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1517,7 +1540,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu0_sent_latch( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu0_sent_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1549,7 +1573,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) iu0_ifar_latch( tri_rlmlatch_p #(.INIT(1), .NEEDS_SRESET(1)) iu0_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1567,7 +1592,8 @@ module iuq_ic_select(
tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu0_ifar_latch( tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) iu0_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1608,7 +1634,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-10), .INIT(0)) stored_erat_ifar_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_WIDTH-10), .INIT(0)) stored_erat_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(stored_erat_act[i]), .act(stored_erat_act[i]),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1628,7 +1655,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) stored_erat_valid_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) stored_erat_valid_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1648,7 +1676,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1666,7 +1695,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) mm_bus_snoop_hold_req_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1684,7 +1714,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1702,7 +1733,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_into_uc_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_into_uc_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1725,7 +1757,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) cp_flush_ifar_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) cp_flush_ifar_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1746,7 +1779,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1764,7 +1798,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_type_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_2ucode_type_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1782,7 +1817,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_nonspec_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) cp_flush_nonspec_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_slp_sl_thold_0_b), .thold_b(pc_iu_func_slp_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1800,7 +1836,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) br_iu_redirect_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) br_iu_redirect_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1818,7 +1855,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) br_iu_bta_latch( tri_rlmreg_p #(.WIDTH(`EFF_IFAR_ARCH), .INIT(0)) br_iu_bta_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1836,7 +1874,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) next_fetch_nonspec_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) next_fetch_nonspec_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1854,7 +1893,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_nonspec_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu1_nonspec_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1872,7 +1912,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_nonspec_latch( tri_rlmreg_p #(.WIDTH(`THREADS), .INIT(0)) iu2_nonspec_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -1895,7 +1936,8 @@ module iuq_ic_select(
tri_rlmreg_p #(.WIDTH(6), .INIT(0)) perf_event_latch( tri_rlmreg_p #(.WIDTH(6), .INIT(0)) perf_event_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(event_bus_enable), .act(event_bus_enable),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),

@ -42,7 +42,8 @@
module iuq_idec( module iuq_idec(
vdd, vdd,
gnd, gnd,
nclk, clk,
rst,
pc_iu_sg_2, pc_iu_sg_2,
pc_iu_func_sl_thold_2, pc_iu_func_sl_thold_2,
clkoff_b, clkoff_b,
@ -179,7 +180,8 @@ module iuq_idec(
`include "tri_a2o.vh" `include "tri_a2o.vh"
inout vdd; inout vdd;
inout gnd; inout gnd;
input [0:`NCLK_WIDTH-1] nclk; input clk;
input rst;
input pc_iu_sg_2; input pc_iu_sg_2;
input pc_iu_func_sl_thold_2; input pc_iu_func_sl_thold_2;
input clkoff_b; input clkoff_b;
@ -5570,7 +5572,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_vld( tri_rlmlatch_p #(.INIT(0)) iu5_vld(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5588,7 +5591,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ucode( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ucode(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5606,7 +5610,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_2ucode( tri_rlmlatch_p #(.INIT(0)) iu5_2ucode(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5624,7 +5629,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_fuse_nop( tri_rlmlatch_p #(.INIT(0)) iu5_fuse_nop(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5642,7 +5648,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_error( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_error(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5660,7 +5667,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_btb_entry( tri_rlmlatch_p #(.INIT(0)) iu5_btb_entry(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5678,7 +5686,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_btb_hist( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_btb_hist(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5696,7 +5705,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_bta_val( tri_rlmlatch_p #(.INIT(0)) iu5_bta_val(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5714,7 +5724,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(20), .INIT(0)) iu5_fusion( tri_rlmreg_p #(.WIDTH(20), .INIT(0)) iu5_fusion(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5732,7 +5743,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_lq( tri_rlmlatch_p #(.INIT(0)) iu5_rte_lq(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5750,7 +5762,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_sq( tri_rlmlatch_p #(.INIT(0)) iu5_rte_sq(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5768,7 +5781,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx0( tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5786,7 +5800,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx1( tri_rlmlatch_p #(.INIT(0)) iu5_rte_fx1(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5804,7 +5819,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu0( tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu0(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5822,7 +5838,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu1( tri_rlmlatch_p #(.INIT(0)) iu5_rte_axu1(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5840,7 +5857,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_valop( tri_rlmlatch_p #(.INIT(0)) iu5_valop(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5858,7 +5876,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_ord( tri_rlmlatch_p #(.INIT(0)) iu5_ord(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5876,7 +5895,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_cord( tri_rlmlatch_p #(.INIT(0)) iu5_cord(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5894,7 +5914,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_spec( tri_rlmlatch_p #(.INIT(0)) iu5_spec(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5912,7 +5933,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_type_fp( tri_rlmlatch_p #(.INIT(0)) iu5_type_fp(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5930,7 +5952,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_type_ap( tri_rlmlatch_p #(.INIT(0)) iu5_type_ap(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5948,7 +5971,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_type_spv( tri_rlmlatch_p #(.INIT(0)) iu5_type_spv(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5966,7 +5990,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_type_st( tri_rlmlatch_p #(.INIT(0)) iu5_type_st(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -5984,7 +6009,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_async_block( tri_rlmlatch_p #(.INIT(0)) iu5_async_block(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6002,7 +6028,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_np1_flush( tri_rlmlatch_p #(.INIT(0)) iu5_np1_flush(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6020,7 +6047,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_core_block( tri_rlmlatch_p #(.INIT(0)) iu5_core_block(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6038,7 +6066,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_isram( tri_rlmlatch_p #(.INIT(0)) iu5_isram(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6056,7 +6085,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_isload( tri_rlmlatch_p #(.INIT(0)) iu5_isload(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6074,7 +6104,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_isstore( tri_rlmlatch_p #(.INIT(0)) iu5_isstore(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6092,7 +6123,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu5_instr( tri_rlmreg_p #(.WIDTH(32), .INIT(0)) iu5_instr(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6110,7 +6142,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_ifar( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_ifar(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6128,7 +6161,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_bta( tri_rlmreg_p #(.WIDTH((`EFF_IFAR_WIDTH)), .INIT(0)) iu5_bta(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6146,7 +6180,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu5_ilat( tri_rlmreg_p #(.WIDTH(4), .INIT(0)) iu5_ilat(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6164,7 +6199,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_t1_v( tri_rlmlatch_p #(.INIT(0)) iu5_t1_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6182,7 +6218,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t1_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t1_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6200,7 +6237,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t1_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t1_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6218,7 +6256,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_t2_v( tri_rlmlatch_p #(.INIT(0)) iu5_t2_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6236,7 +6275,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t2_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t2_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6254,7 +6294,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t2_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t2_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6272,7 +6313,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_t3_v( tri_rlmlatch_p #(.INIT(0)) iu5_t3_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_valid_act), .act(iu5_valid_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6290,7 +6332,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t3_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_t3_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6308,7 +6351,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t3_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_t3_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6326,7 +6370,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_s1_v( tri_rlmlatch_p #(.INIT(0)) iu5_s1_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6344,7 +6389,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s1_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s1_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6362,7 +6408,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s1_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s1_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6380,7 +6427,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_s2_v( tri_rlmlatch_p #(.INIT(0)) iu5_s2_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6398,7 +6446,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s2_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s2_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6416,7 +6465,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s2_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s2_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6434,7 +6484,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_s3_v( tri_rlmlatch_p #(.INIT(0)) iu5_s3_v(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6452,7 +6503,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s3_a( tri_rlmreg_p #(.WIDTH(`GPR_POOL_ENC), .INIT(0)) iu5_s3_a(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6470,7 +6522,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s3_t( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_s3_t(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6488,7 +6541,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_br_pred( tri_rlmlatch_p #(.INIT(0)) iu5_br_pred(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6506,7 +6560,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_bh_update( tri_rlmlatch_p #(.INIT(0)) iu5_bh_update(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6524,7 +6579,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh0_hist( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh0_hist(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6542,7 +6598,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh1_hist( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh1_hist(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6560,7 +6617,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh2_hist( tri_rlmreg_p #(.WIDTH(2), .INIT(0)) iu5_bh2_hist(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6578,7 +6636,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(18), .INIT(0)) iu5_gshare( tri_rlmreg_p #(.WIDTH(18), .INIT(0)) iu5_gshare(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6596,7 +6655,8 @@ assign no_pre =
tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ls_ptr( tri_rlmreg_p #(.WIDTH(3), .INIT(0)) iu5_ls_ptr(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6614,7 +6674,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) iu5_match( tri_rlmlatch_p #(.INIT(0)) iu5_match(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(iu5_instr_act), .act(iu5_instr_act),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6632,7 +6693,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_epcr_dgtmi_latch( tri_rlmlatch_p #(.INIT(0)) spr_epcr_dgtmi_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6650,7 +6712,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_msrp_uclep_latch( tri_rlmlatch_p #(.INIT(0)) spr_msrp_uclep_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6668,7 +6731,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_msr_pr_latch( tri_rlmlatch_p #(.INIT(0)) spr_msr_pr_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6686,7 +6750,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_msr_gs_latch( tri_rlmlatch_p #(.INIT(0)) spr_msr_gs_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6704,7 +6769,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_msr_ucle_latch( tri_rlmlatch_p #(.INIT(0)) spr_msr_ucle_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6722,7 +6788,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) spr_ccr2_ucode_dis_latch( tri_rlmlatch_p #(.INIT(0)) spr_ccr2_ucode_dis_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6740,7 +6807,8 @@ assign no_pre =
tri_rlmlatch_p #(.INIT(0)) cp_flush_latch( tri_rlmlatch_p #(.INIT(0)) cp_flush_latch(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.act(tiup), .act(tiup),
.thold_b(pc_iu_func_sl_thold_0_b), .thold_b(pc_iu_func_sl_thold_0_b),
.sg(pc_iu_sg_0), .sg(pc_iu_sg_0),
@ -6821,7 +6889,8 @@ assign no_pre =
tri_plat #(.WIDTH(2)) perv_2to1_reg( tri_plat #(.WIDTH(2)) perv_2to1_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_2,pc_iu_sg_2}), .din({pc_iu_func_sl_thold_2,pc_iu_sg_2}),
.q({pc_iu_func_sl_thold_1,pc_iu_sg_1}) .q({pc_iu_func_sl_thold_1,pc_iu_sg_1})
@ -6831,7 +6900,8 @@ assign no_pre =
tri_plat #(.WIDTH(2)) perv_1to0_reg( tri_plat #(.WIDTH(2)) perv_1to0_reg(
.vd(vdd), .vd(vdd),
.gd(gnd), .gd(gnd),
.nclk(nclk), .clk(clk),
.rst(rst),
.flush(tc_ac_ccflush_dc), .flush(tc_ac_ccflush_dc),
.din({pc_iu_func_sl_thold_1,pc_iu_sg_1}), .din({pc_iu_func_sl_thold_1,pc_iu_sg_1}),
.q({pc_iu_func_sl_thold_0,pc_iu_sg_0}) .q({pc_iu_func_sl_thold_0,pc_iu_sg_0})

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