From d2901c317783fe98a67f6a7eafe72326a101c314 Mon Sep 17 00:00:00 2001
From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com>
Date: Fri, 29 Jul 2022 08:12:21 -0500
Subject: [PATCH] update

---
 dev/pd/readme.md      | 31 +++++++++++++++++++++++++++++--
 dev/pd/synth/synth.yo | 37 ++++++++++++++++++++++++++++++-------
 dev/pd/synth/verilog  |  2 +-
 3 files changed, 60 insertions(+), 10 deletions(-)

diff --git a/dev/pd/readme.md b/dev/pd/readme.md
index 56ba256..243d885 100644
--- a/dev/pd/readme.md
+++ b/dev/pd/readme.md
@@ -9,9 +9,11 @@
 
 ### test OpenROAD tools
 
-1. attempt unit (or sub-unit) synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (equivalent to a CI timing script to catch functional changes that break timing)
+1. try unit/sub-unit synthesis and static timing, using blackbox arrays amd estimated wiring for some pdk (nangate45?)
 
-* what are the OR steps to do this?
+   * equivalent to a CI timing script to catch functional changes that break timing
+
+* what are the OR steps to do this?  can this be done with only yosys script?s
 
    * floorplan - unbounded?
    * pins - no placement if no bounds, and relaxed i/o assertions?
@@ -24,3 +26,28 @@
 
 * are results consistent with expected cycle time?
 
+### Yosys
+
+* blackbox arrays
+
+```
+cd synth
+yosys -s synth.yo
+```
+
+### OpenROAD
+
+* https://openroad.readthedocs.io/en/latest/user/BuildWithDocker.html
+
+* yosys, OpenROAD, LSOracle
+
+```
+git clone --recursive https://github.com/The-OpenROAD-Project/OpenROAD-flow-scripts
+cd OpenROAD-flow-scripts
+./build_openroad.sh [--threads n]
+```
+
+```
+docker run -it -u $(id -u ${USER}):$(id -g ${USER}) -v $(pwd)/flow/platforms:/OpenROAD-flow-scripts/flow/platforms:ro openroad/flow-scripts
+```
+
diff --git a/dev/pd/synth/synth.yo b/dev/pd/synth/synth.yo
index 5118f13..28c0396 100755
--- a/dev/pd/synth/synth.yo
+++ b/dev/pd/synth/synth.yo
@@ -1,13 +1,36 @@
-#read_verilog ../verilog/unisims
-# blockbox versions
-read_verilog ../verilog/unisims_synth
 
-read_verilog -I../verilog/trilib ../verilog/trilib/*
-read_verilog -I../verilog/trilib ../verilog/work/*
+##### arrays
 
+# The blackbox attribute on modules is used to mark empty stub modules
+# that have the same ports as the real thing but do not contain information
+# on the internal configuration. This modules are only used by the synthesis
+# passes to identify input and output ports of cells. The Verilog backend also
+# does not output blackbox modules on default. read_verilog, unless called with
+# -noblackbox will automatically set the blackbox attribute on any empty module
+# it reads.
+# The whitebox attribute on modules triggers the same behavior as blackbox, but
+# is for whitebox modules, i.e. library modules that contain a behavioral model
+# of the cell type.
+#read_verilog ./verilog/unisims_synth     # blockbox versions
+
+# this ignores module bodies ands adds blackbox automatically
+read_verilog -lib ./verilog/unisims
+
+##### lib and macros
+read_verilog -I./verilog/trilib ./verilog/trilib/*
+read_verilog -I./verilog/trilib ./verilog/work/*
+
+##### synth
+
+#hierarchy -check -top c         # fails with blackbox
 hierarchy -top c
 
 proc; opt; memory -nomap; opt -fast
-#check -assert
 
-#synth -top c
\ No newline at end of file
+#check -assert                   # some driver errors, lots of array errors cuz blackbox?
+#synth -top c                    # fails with blackbox
+
+##### map
+
+##### finish
+
diff --git a/dev/pd/synth/verilog b/dev/pd/synth/verilog
index 2630032..b628320 120000
--- a/dev/pd/synth/verilog
+++ b/dev/pd/synth/verilog
@@ -1 +1 @@
-../verilog
\ No newline at end of file
+../../verilog
\ No newline at end of file