%Warning-PINMISSING: verilog/a2o_litex/a2owb.v:253:3: Cell has missing pin: 'ac_an_event_bus1' 253 | c c0( | ^~ ... For warning description see https://verilator.org/warn/PINMISSING?v=4.224 ... Use "/* verilator lint_off PINMISSING */" and lint_on around source to disable this message. %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i0_s1_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i0_s2_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i0_s3_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i1_s1_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i1_s2_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:1815:4: Cell has missing pin: 'iu_rv_iu6_t0_i1_s3_a' 1815 | iuq0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:4171:4: Cell has missing pin: 'mm_iu_t1_ierat_pid' 4171 | mmu0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:4171:4: Cell has missing pin: 'mm_iu_t1_ierat_mmucr0' 4171 | mmu0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:4171:4: Cell has missing pin: 'mm_xu_t1_derat_pid' 4171 | mmu0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c.v:4171:4: Cell has missing pin: 'mm_xu_t1_derat_mmucr0' 4171 | mmu0( | ^~~~ verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1339:111: Cell has missing pin: 'r4e_e' 1339 | xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(5 + 0), .POOL(24 * 1), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1339:111: Cell has missing pin: 'r4e' 1339 | xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(5 + 0), .POOL(24 * 1), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1339:111: Cell has missing pin: 'r4a' 1339 | xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(5 + 0), .POOL(24 * 1), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1339:111: Cell has missing pin: 'r4d' 1339 | xu_rf #(.WIDTH(4), .PAR_WIDTH(1), .POOL_ENC(5 + 0), .POOL(24 * 1), .RD_PORTS(4), .WR_PORTS(5), .BYPASS(1)) cr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w2e_e' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w2a' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w2d' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w3e_e' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w3a' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w3d' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w4e_e' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w4a' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1393:117: Cell has missing pin: 'w4d' 1393 | xu_rf #(.WIDTH(10), .PAR_WIDTH(2), .POOL_ENC(4 + 0), .POOL(12 * 1), .RD_PORTS(3 + 1), .WR_PORTS(2), .BYPASS(1)) xer( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r2e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r2e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r2a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r2d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r3e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r3e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r3a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r3d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r4e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r4e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r4a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'r4d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w1e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w1a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w1d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w2e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w2a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w2d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w3e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w3a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w3d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w4e_e' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w4a' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1442:115: Cell has missing pin: 'w4d' 1442 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(2), .WR_PORTS(1), .BYPASS(1)) lr( | ^~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r1e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r1e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r1a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r1d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r2e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r2e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r2a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r2d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r3e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r3e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r3a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r3d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r4e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r4e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r4a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'r4d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w1e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w1a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w1d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w2e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w2a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w2d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w3e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w3a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w3d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w4e_e' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w4a' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu.v:1476:116: Cell has missing pin: 'w4d' 1476 | xu_rf #(.WIDTH(64), .PAR_WIDTH(64/8), .POOL_ENC(3 + 0), .POOL(8 * 1), .RD_PORTS(1), .WR_PORTS(1), .BYPASS(1)) ctr( | ^~~ verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:588:45: Cell has missing pin: 'q' 588 | tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) fu_abst_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:588:45: Cell has missing pin: 'q_b' 588 | tri_slat_scan #(.WIDTH(2), .INIT(2'b00)) fu_abst_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:598:47: Cell has missing pin: 'q' 598 | tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) pc_func_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:598:47: Cell has missing pin: 'q_b' 598 | tri_slat_scan #(.WIDTH(4), .INIT(4'b0000)) pc_func_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:607:51: Cell has missing pin: 'q' 607 | tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) fu_func_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:607:51: Cell has missing pin: 'q_b' 607 | tri_slat_scan #(.WIDTH(8), .INIT(8'b00000000)) fu_func_stg( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:617:48: Cell has missing pin: 'q' 617 | tri_slat_scan #(.WIDTH(5), .INIT(5'b00000)) pc_cfg_stg( | ^~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:617:48: Cell has missing pin: 'q_b' 617 | tri_slat_scan #(.WIDTH(5), .INIT(5'b00000)) pc_cfg_stg( | ^~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:630:46: Cell has missing pin: 'q' 630 | tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) fu_cfg_stg( | ^~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:630:46: Cell has missing pin: 'q_b' 630 | tri_slat_scan #(.WIDTH(3), .INIT(3'b000)) fu_cfg_stg( | ^~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:642:52: Cell has missing pin: 'd_mode' 642 | tri_rlmreg_p #(.WIDTH(FUNC2_T0_SIZE), .INIT(0)) func2_t0_rp( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/c_perv_rp.v:674:58: Cell has missing pin: 'd_mode' 674 | tri_rlmreg_p #(.WIDTH(FUNC2_T1_SIZE), .INIT(0)) func2_t1_rp( | ^~~~~~~~~~~ verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu1.v:392:12: Cell has missing pin: 'dec_byp_ex2_val' 392 | xu1_dec dec( | ^~~ verilog/work/xu.v:1217:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1171:19: Cell has missing pin: 'coretrace_ctrls_in' 1171 | tri_debug_mux4 xu_debug_mux( | ^~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1171:19: Cell has missing pin: 'coretrace_ctrls_out' 1171 | tri_debug_mux4 xu_debug_mux( | ^~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1492:57: Cell has missing pin: 'dout' 1492 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1503:57: Cell has missing pin: 'dout' 1503 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) abst_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1514:57: Cell has missing pin: 'dout' 1514 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1525:57: Cell has missing pin: 'dout' 1525 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) bcfg_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1536:57: Cell has missing pin: 'dout' 1536 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1547:57: Cell has missing pin: 'dout' 1547 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) ccfg_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1558:57: Cell has missing pin: 'dout' 1558 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1569:57: Cell has missing pin: 'dout' 1569 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) dcfg_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1580:57: Cell has missing pin: 'dout' 1580 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1591:57: Cell has missing pin: 'dout' 1591 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) time_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1602:57: Cell has missing pin: 'dout' 1602 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1613:57: Cell has missing pin: 'dout' 1613 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) repr_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1624:57: Cell has missing pin: 'dout' 1624 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1635:57: Cell has missing pin: 'dout' 1635 | tri_regs #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) gptr_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1646:61: Cell has missing pin: 'dout' 1646 | tri_regs #(.WIDTH((1+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_in_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/xu_spr.v:1657:61: Cell has missing pin: 'dout' 1657 | tri_regs #(.WIDTH((1+2)), .INIT(0), .NEEDS_SRESET(1)) func_scan_out_latch( | ^~~~~~~~~~~~~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/mmq_inval.v:3782:57: Cell has missing pin: 'scout' 3782 | tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(0)) epcr_dgtmi_latch( | ^~~~~~~~~~~~~~~~ verilog/work/mmq.v:1387:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/mmq_inval.v:3800:57: Cell has missing pin: 'scout' 3800 | tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) lpidr_latch( | ^~~~~~~~~~~ verilog/work/mmq.v:1387:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/mmq_inval.v:3818:57: Cell has missing pin: 'scout' 3818 | tri_regk #(.WIDTH(8), .INIT(0), .NEEDS_SRESET(0)) mmucr1_latch( | ^~~~~~~~~~~~ verilog/work/mmq.v:1387:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/mmq_inval.v:3836:57: Cell has missing pin: 'scout' 3836 | tri_regk #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(0)) mmucr1_csinv_latch( | ^~~~~~~~~~~~~~~~~~ verilog/work/mmq.v:1387:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu.v:805:74: Cell has missing pin: 'gptr_scan_in' 805 | fu_fpr #( .fpr_pool(64 * 1), .fpr_pool_enc(6 + 0), .axu_spare_enc(3)) fpr( | ^~~ verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu.v:805:74: Cell has missing pin: 'gptr_scan_out' 805 | fu_fpr #( .fpr_pool(64 * 1), .fpr_pool_enc(6 + 0), .axu_spare_enc(3)) fpr( | ^~~ verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:677:99: Cell has missing pin: 'addr_v' 677 | tri_serial_scom2 #(.WIDTH(SCOM_WIDTH), .INTERNAL_ADDR_DECODE(1'b0), .PIPELINE_PARITYCHK(1'b0)) scomsat( | ^~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1683:49: Cell has missing pin: 'd_mode' 1683 | tri_rlmreg_p #(.WIDTH(ARDSR_SIZE), .INIT(0)) axrv_dbgsel_reg( | ^~~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1700:48: Cell has missing pin: 'd_mode' 1700 | tri_rlmreg_p #(.WIDTH(IDSR_SIZE), .INIT(0)) iu_dbgsel_reg( | ^~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1717:49: Cell has missing pin: 'd_mode' 1717 | tri_rlmreg_p #(.WIDTH(MPDSR_SIZE), .INIT(0)) mmpc_dbgsel_reg( | ^~~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1734:48: Cell has missing pin: 'd_mode' 1734 | tri_rlmreg_p #(.WIDTH(XDSR_SIZE), .INIT(0)) xu_dbgsel_reg( | ^~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1751:48: Cell has missing pin: 'd_mode' 1751 | tri_rlmreg_p #(.WIDTH(LDSR_SIZE), .INIT(0)) lq_dbgsel_reg( | ^~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1768:49: Cell has missing pin: 'd_mode' 1768 | tri_rlmreg_p #(.WIDTH(PCCR0_SIZE), .INIT(0)) pccr0_reg( | ^~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1785:54: Cell has missing pin: 'd_mode' 1785 | tri_rlmreg_p #(.WIDTH(RECERRCNTR_SIZE), .INIT(0)) rec_err_cntr( | ^~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1802:40: Cell has missing pin: 'd_mode' 1802 | tri_rlmreg_p #(.WIDTH(1), .INIT(0)) pccr0_par( | ^~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1819:55: Cell has missing pin: 'd_mode' 1819 | tri_rlmreg_p #(.WIDTH(DCFG_STAGE1_SIZE), .INIT(0)) dcfg_stage1( | ^~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1838:51: Cell has missing pin: 'd_mode' 1838 | tri_rlmreg_p #(.WIDTH(THRCTL1_SIZE), .INIT(0)) thrctl1_reg( | ^~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1855:51: Cell has missing pin: 'd_mode' 1855 | tri_rlmreg_p #(.WIDTH(THRCTL2_SIZE), .INIT(0)) thrctl2_reg( | ^~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1872:50: Cell has missing pin: 'd_mode' 1872 | tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT(0)) spattn_data_reg( | ^~~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1889:69: Cell has missing pin: 'd_mode' 1889 | tri_rlmreg_p #(.WIDTH(SPATTN_USED), .INIT({SPATTN_USED {1'b1}})) spattn_mask_reg( | ^~~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1906:57: Cell has missing pin: 'd_mode' 1906 | tri_rlmreg_p #(.WIDTH(1), .INIT(SPATTN_PARITY_INIT)) spattn_par( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1923:58: Cell has missing pin: 'd_mode' 1923 | tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T0_SIZE), .INIT(1)) bcfg_stage1_t0( | ^~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1946:62: Cell has missing pin: 'd_mode' 1946 | tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T0_SIZE), .INIT(0)) bcfg_stage2_t0( | ^~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1967:53: Cell has missing pin: 'd_mode' 1967 | tri_rlmreg_p #(.WIDTH(ERRDBG_T0_SIZE), .INIT(0)) errdbg_t0( | ^~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:1988:57: Cell has missing pin: 'd_mode' 1988 | tri_rlmreg_p #(.WIDTH(BCFG_STAGE1_T1_SIZE), .INIT(1)) bcfg_stage1_t1( | ^~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2011:61: Cell has missing pin: 'd_mode' 2011 | tri_ser_rlmreg_p #(.WIDTH(BCFG_STAGE2_T1_SIZE), .INIT(0)) bcfg_stage2_t1( | ^~~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2030:54: Cell has missing pin: 'd_mode' 2030 | tri_rlmreg_p #(.WIDTH(ERRDBG_T1_SIZE), .INIT(0)) errdbg_t1( | ^~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2052:44: Cell has missing pin: 'q' 2052 | tri_slat_scan #(.WIDTH(1), .INIT(1'b0)) ccfg_repwr( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2052:44: Cell has missing pin: 'q_b' 2052 | tri_slat_scan #(.WIDTH(1), .INIT(1'b0)) ccfg_repwr( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2063:48: Cell has missing pin: 'd_mode' 2063 | tri_rlmreg_p #(.WIDTH(RAMI_SIZE), .INIT(0)) rami_reg( | ^~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2081:48: Cell has missing pin: 'd_mode' 2081 | tri_rlmreg_p #(.WIDTH(RAMC_SIZE), .INIT(0)) ramc_reg( | ^~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2099:48: Cell has missing pin: 'd_mode' 2099 | tri_rlmreg_p #(.WIDTH(RAMD_SIZE), .INIT(0)) ramd_reg( | ^~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2117:54: Cell has missing pin: 'd_mode' 2117 | tri_rlmreg_p #(.WIDTH(FU_RAM_DIN_SIZE), .INIT(0)) fu_ram_din( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2135:54: Cell has missing pin: 'd_mode' 2135 | tri_rlmreg_p #(.WIDTH(XU_RAM_DIN_SIZE), .INIT(0)) xu_ram_din( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2153:54: Cell has missing pin: 'd_mode' 2153 | tri_rlmreg_p #(.WIDTH(LQ_RAM_DIN_SIZE), .INIT(0)) lq_ram_din( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2171:50: Cell has missing pin: 'd_mode' 2171 | tri_rlmreg_p #(.WIDTH(ERRINJ_SIZE), .INIT(0)) errinj_reg( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2189:57: Cell has missing pin: 'd_mode' 2189 | tri_ser_rlmreg_p #(.WIDTH(SCOM_MISC_SIZE), .INIT(0)) sc_misc( | ^~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2210:41: Cell has missing pin: 'd_mode' 2210 | tri_rlmreg_p #(.WIDTH(64), .INIT(0)) scaddr_dec( | ^~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2227:55: Cell has missing pin: 'd_mode' 2227 | tri_rlmreg_p #(.WIDTH(FUNC_STAGE1_SIZE), .INIT(0)) func_stage1( | ^~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2244:61: Cell has missing pin: 'd_mode' 2244 | tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T0_SIZE), .INIT(0)) inj_stage1_t0( | ^~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2286:60: Cell has missing pin: 'd_mode' 2286 | tri_ser_rlmreg_p #(.WIDTH(INJ_STAGE1_T1_SIZE), .INIT(0)) inj_stage1_t1( | ^~~~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs.v:2311:59: Cell has missing pin: 'd_mode' 2311 | tri_ser_rlmreg_p #(.WIDTH(FUNC_STAGE3_SIZE), .INIT(0)) func_stage3( | ^~~~~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:264:31: Cell has missing pin: 'd_mode' 264 | tri_rlmlatch_p #(.INIT(1)) initactive( | ^~~~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:281:52: Cell has missing pin: 'd_mode' 281 | tri_rlmreg_p #(.WIDTH(HOLDCNTR_SIZE), .INIT(0)) holdcntr( | ^~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:298:64: Cell has missing pin: 'd_mode' 298 | tri_rlmreg_p #(.WIDTH(INITCNTR_SIZE), .INIT(INITCNT_START)) initcntr( | ^~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:315:31: Cell has missing pin: 'd_mode' 315 | tri_rlmlatch_p #(.INIT(0)) initerat( | ^~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:332:54: Cell has missing pin: 'd_mode' 332 | tri_rlmreg_p #(.WIDTH(PMCTRLS_T0_SIZE), .INIT(0)) pmctrls_t0( | ^~~~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:356:60: Cell has missing pin: 'd_mode' 356 | tri_rlmreg_p #(.WIDTH(PMCTRLS_T1_SIZE), .INIT(0)) pmctrls_t1( | ^~~~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_ctrl.v:376:53: Cell has missing pin: 'd_mode' 376 | tri_rlmreg_p #(.WIDTH(SPARECTRL_SIZE), .INIT(0)) sparectrl( | ^~~~~~~~~ verilog/work/pcq.v:578:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_dbg.v:336:51: Cell has missing pin: 'd_mode' 336 | tri_rlmreg_p #(.WIDTH(RAMCTRL_SIZE), .INIT(0)) ramctrl( | ^~~~~~~ verilog/work/pcq.v:610:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_dbg.v:353:50: Cell has missing pin: 'd_mode' 353 | tri_rlmreg_p #(.WIDTH(SCMISC_SIZE), .INIT(0)) scmisc( | ^~~~~~ verilog/work/pcq.v:610:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_dbg.v:370:51: Cell has missing pin: 'd_mode' 370 | tri_rlmreg_p #(.WIDTH(FIRMISC_SIZE), .INIT(0)) firmisc( | ^~~~~~~ verilog/work/pcq.v:610:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_dbg.v:387:52: Cell has missing pin: 'd_mode' 387 | tri_rlmreg_p #(.WIDTH(TRACEOUT_SIZE), .INIT(0)) traceout( | ^~~~~~~~ verilog/work/pcq.v:610:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_dbg.v:404:53: Cell has missing pin: 'd_mode' 404 | tri_rlmreg_p #(.WIDTH(CORETRACE_SIZE), .INIT(0)) coretrace( | ^~~~~~~~~ verilog/work/pcq.v:610:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:221:58: Cell has missing pin: 'd_mode' 221 | tri_rlmreg_p #(.WIDTH(1), .INIT(0), .NEEDS_SRESET(1)) cp_flush_reg( | ^~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:238:49: Cell has missing pin: 'd_mode' 238 | tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_val_reg( | ^~~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:255:49: Cell has missing pin: 'd_mode' 255 | tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_rw_reg( | ^~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:272:58: Cell has missing pin: 'd_mode' 272 | tri_rlmreg_p #(.WIDTH(2), .INIT(0), .NEEDS_SRESET(1)) slowspr_etid_reg( | ^~~~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:289:59: Cell has missing pin: 'd_mode' 289 | tri_rlmreg_p #(.WIDTH(10), .INIT(0), .NEEDS_SRESET(1)) slowspr_addr_reg( | ^~~~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:306:59: Cell has missing pin: 'd_mode' 306 | tri_rlmreg_p #(.WIDTH(64), .INIT(0), .NEEDS_SRESET(1)) slowspr_data_reg( | ^~~~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:323:49: Cell has missing pin: 'd_mode' 323 | tri_rlmlatch_p #(.INIT(0), .NEEDS_SRESET(1)) slowspr_done_reg( | ^~~~~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:340:53: Cell has missing pin: 'd_mode' 340 | tri_ser_rlmreg_p #(.WIDTH(CESR1_SIZE), .INIT(0)) cesr1_reg( | ^~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:357:57: Cell has missing pin: 'd_mode' 357 | tri_ser_rlmreg_p #(.WIDTH(CESR1_IS0_SIZE), .INIT(0)) cesr1_is0_reg( | ^~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:374:57: Cell has missing pin: 'd_mode' 374 | tri_ser_rlmreg_p #(.WIDTH(CESR1_IS1_SIZE), .INIT(0)) cesr1_is1_reg( | ^~~~~~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:391:53: Cell has missing pin: 'd_mode' 391 | tri_ser_rlmreg_p #(.WIDTH(RESR1_SIZE), .INIT(0)) resr1_reg( | ^~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:408:53: Cell has missing pin: 'd_mode' 408 | tri_ser_rlmreg_p #(.WIDTH(RESR2_SIZE), .INIT(0)) resr2_reg( | ^~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:425:53: Cell has missing pin: 'd_mode' 425 | tri_ser_rlmreg_p #(.WIDTH(SRAMD_SIZE), .INIT(0)) sramd_reg( | ^~~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_spr.v:442:48: Cell has missing pin: 'd_mode' 442 | tri_rlmreg_p #(.WIDTH(MISC_SIZE), .INIT(0)) misc_reg( | ^~~~~~~~ verilog/work/pcq.v:643:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_perv.v:252:21: Cell has missing pin: 'd_mode_dc' 252 | tri_lcbcntl_mac perv_lcbctrl0( | ^~~~~~~~~~~~~ verilog/work/fu.v:768:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_perv.v:269:21: Cell has missing pin: 'd_mode_dc' 269 | tri_lcbcntl_mac perv_lcbctrl1( | ^~~~~~~~~~~~~ verilog/work/fu.v:768:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_mad.v:2089:12: Cell has missing pin: 'f_cr2_ex2_fpscr_shadow' 2089 | fu_cr2 fcr2( | ^~~~ verilog/work/fu.v:963:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_dcd.v:1727:68: Cell has missing pin: 'q' 1727 | tri_slat_scan #(.WIDTH(2), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) cfg_stg( | ^~~~~~~ verilog/work/fu.v:1224:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_dcd.v:1727:68: Cell has missing pin: 'q_b' 1727 | tri_slat_scan #(.WIDTH(2), .INIT(0), .RESET_INVERTS_SCAN(1'b1)) cfg_stg( | ^~~~~~~ verilog/work/fu.v:1224:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/fu_dcd.v:3890:24: Cell has missing pin: 'delay_lclkr' 3890 | tri_parity_recovery fu_parity_recovery( | ^~~~~~~~~~~~~~~~~~ verilog/work/fu.v:1224:1: ... note: In file included from fu.v verilog/work/c_fu_pc.v:796:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/iuq_dec_top.v:649:20: Cell has missing pin: 'fu_dec_debug' 649 | iuq_axu_fu_dec axu_dec1( | ^~~~~~~~ verilog/work/iuq_slice.v:533:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:361:5: Cell has missing pin: 'hold_out' 361 | ) parity_err( | ^~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:361:5: Cell has missing pin: 'mask_out' 361 | ) parity_err( | ^~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:636:60: Cell has missing pin: 'q_b' 636 | tri_nlat_scan #(.WIDTH(PAR_NOBITS), .NEEDS_SRESET(1)) state( | ^~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:692:52: Cell has missing pin: 'q_b' 692 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dec_addr( | ^~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:775:72: Cell has missing pin: 'q_b' 775 | tri_nlat_scan #(.WIDTH(STATE_WIDTH), .INIT(IDLE), .NEEDS_SRESET(1)) state( | ^~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:788:68: Cell has missing pin: 'q_b' 788 | tri_nlat_scan #(.WIDTH(7), .INIT(7'b0000000), .NEEDS_SRESET(1)) counter( | ^~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:801:53: Cell has missing pin: 'q_b' 801 | tri_nlat_scan #(.WIDTH(WIDTH), .NEEDS_SRESET(1)) data_shifter( | ^~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:814:58: Cell has missing pin: 'q_b' 814 | tri_nlat_scan #(.WIDTH(PAR_NOBITS), .NEEDS_SRESET(1)) datapar_shifter( | ^~~~~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:827:76: Cell has missing pin: 'q_b' 827 | tri_nlat_scan #(.WIDTH(HEAD_WIDTH), .INIT(HEAD_INIT), .NEEDS_SRESET(1)) head_lat( | ^~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:840:66: Cell has missing pin: 'q_b' 840 | tri_nlat_scan #(.WIDTH(5), .INIT(5'b00000), .NEEDS_SRESET(1)) tail_lat( | ^~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:853:44: Cell has missing pin: 'q_b' 853 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dch_inlatch( | ^~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:866:49: Cell has missing pin: 'q_b' 866 | tri_nlat_scan #(.WIDTH(2), .NEEDS_SRESET(1)) ack_info( | ^~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:879:44: Cell has missing pin: 'q_b' 879 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) dch_outlatch( | ^~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:892:49: Cell has missing pin: 'q_b' 892 | tri_nlat_scan #(.WIDTH(2), .NEEDS_SRESET(1)) cch_latches( | ^~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:905:44: Cell has missing pin: 'q_b' 905 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) scom_err_latch( | ^~~~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:918:44: Cell has missing pin: 'q_b' 918 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) scom_local_act_latch( | ^~~~~~~~~~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:931:44: Cell has missing pin: 'q_b' 931 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) spare_latch1( | ^~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_serial_scom2.v:944:44: Cell has missing pin: 'q_b' 944 | tri_nlat #(.WIDTH(1), .NEEDS_SRESET(1)) spare_latch2( | ^~~~~~~~~~~~ verilog/work/pcq_regs.v:679:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:651:104: Cell has missing pin: 'mask_out' 651 | tri_err_rpt #(.WIDTH(SCPAR_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCPAR_RPT_RESET_VALUE), .INLINE(1'b0)) scom_err( | ^~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:674:104: Cell has missing pin: 'mask_out' 674 | tri_err_rpt #(.WIDTH(SCACK_ERR_RPT_WIDTH), .MASK_RESET_VALUE(SCACK_RPT_RESET_VALUE), .INLINE(1'b0)) sc_ack_err( | ^~~~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:894:80: Cell has missing pin: 'q_b' 894 | tri_nlat_scan #(.WIDTH(ERROUT_FUNC_SIZE), .INIT({ERROUT_FUNC_SIZE {1'b0}})) error_out( | ^~~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:915:58: Cell has missing pin: 'q_b' 915 | tri_nlat_scan #(.WIDTH(FIR0_WIDTH), .INIT(FIR0_INIT)) f0err_out( | ^~~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:927:58: Cell has missing pin: 'q_b' 927 | tri_nlat_scan #(.WIDTH(FIR1_WIDTH), .INIT(FIR1_INIT)) f1err_out( | ^~~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_regs_fir.v:939:58: Cell has missing pin: 'q_b' 939 | tri_nlat_scan #(.WIDTH(FIR2_WIDTH), .INIT(FIR2_INIT)) f2err_out( | ^~~~~~~~~ verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:59:14: Cell has missing pin: 'vd' 59 | tri_bthmx u00( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:59:14: Cell has missing pin: 'gd' 59 | tri_bthmx u00( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:70:14: Cell has missing pin: 'vd' 70 | tri_bthmx u01( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:70:14: Cell has missing pin: 'gd' 70 | tri_bthmx u01( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:81:14: Cell has missing pin: 'vd' 81 | tri_bthmx u02( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:81:14: Cell has missing pin: 'gd' 81 | tri_bthmx u02( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:92:14: Cell has missing pin: 'vd' 92 | tri_bthmx u03( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:92:14: Cell has missing pin: 'gd' 92 | tri_bthmx u03( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:103:14: Cell has missing pin: 'vd' 103 | tri_bthmx u04( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:103:14: Cell has missing pin: 'gd' 103 | tri_bthmx u04( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:114:14: Cell has missing pin: 'vd' 114 | tri_bthmx u05( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:114:14: Cell has missing pin: 'gd' 114 | tri_bthmx u05( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:125:14: Cell has missing pin: 'vd' 125 | tri_bthmx u06( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:125:14: Cell has missing pin: 'gd' 125 | tri_bthmx u06( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:136:14: Cell has missing pin: 'vd' 136 | tri_bthmx u07( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:136:14: Cell has missing pin: 'gd' 136 | tri_bthmx u07( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:147:14: Cell has missing pin: 'vd' 147 | tri_bthmx u08( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:147:14: Cell has missing pin: 'gd' 147 | tri_bthmx u08( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:158:14: Cell has missing pin: 'vd' 158 | tri_bthmx u09( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:158:14: Cell has missing pin: 'gd' 158 | tri_bthmx u09( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:169:14: Cell has missing pin: 'vd' 169 | tri_bthmx u10( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:169:14: Cell has missing pin: 'gd' 169 | tri_bthmx u10( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:180:14: Cell has missing pin: 'vd' 180 | tri_bthmx u11( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:180:14: Cell has missing pin: 'gd' 180 | tri_bthmx u11( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:191:14: Cell has missing pin: 'vd' 191 | tri_bthmx u12( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:191:14: Cell has missing pin: 'gd' 191 | tri_bthmx u12( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:202:14: Cell has missing pin: 'vd' 202 | tri_bthmx u13( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:202:14: Cell has missing pin: 'gd' 202 | tri_bthmx u13( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:213:14: Cell has missing pin: 'vd' 213 | tri_bthmx u14( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:213:14: Cell has missing pin: 'gd' 213 | tri_bthmx u14( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:224:14: Cell has missing pin: 'vd' 224 | tri_bthmx u15( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:224:14: Cell has missing pin: 'gd' 224 | tri_bthmx u15( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:235:14: Cell has missing pin: 'vd' 235 | tri_bthmx u16( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:235:14: Cell has missing pin: 'gd' 235 | tri_bthmx u16( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:246:14: Cell has missing pin: 'vd' 246 | tri_bthmx u17( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:246:14: Cell has missing pin: 'gd' 246 | tri_bthmx u17( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:257:14: Cell has missing pin: 'vd' 257 | tri_bthmx u18( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:257:14: Cell has missing pin: 'gd' 257 | tri_bthmx u18( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:268:14: Cell has missing pin: 'vd' 268 | tri_bthmx u19( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:268:14: Cell has missing pin: 'gd' 268 | tri_bthmx u19( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:279:14: Cell has missing pin: 'vd' 279 | tri_bthmx u20( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:279:14: Cell has missing pin: 'gd' 279 | tri_bthmx u20( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:290:14: Cell has missing pin: 'vd' 290 | tri_bthmx u21( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:290:14: Cell has missing pin: 'gd' 290 | tri_bthmx u21( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:301:14: Cell has missing pin: 'vd' 301 | tri_bthmx u22( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:301:14: Cell has missing pin: 'gd' 301 | tri_bthmx u22( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:312:14: Cell has missing pin: 'vd' 312 | tri_bthmx u23( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:312:14: Cell has missing pin: 'gd' 312 | tri_bthmx u23( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:323:14: Cell has missing pin: 'vd' 323 | tri_bthmx u24( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:323:14: Cell has missing pin: 'gd' 323 | tri_bthmx u24( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:334:14: Cell has missing pin: 'vd' 334 | tri_bthmx u25( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:334:14: Cell has missing pin: 'gd' 334 | tri_bthmx u25( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:345:14: Cell has missing pin: 'vd' 345 | tri_bthmx u26( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:345:14: Cell has missing pin: 'gd' 345 | tri_bthmx u26( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:356:14: Cell has missing pin: 'vd' 356 | tri_bthmx u27( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:356:14: Cell has missing pin: 'gd' 356 | tri_bthmx u27( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:367:14: Cell has missing pin: 'vd' 367 | tri_bthmx u28( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:367:14: Cell has missing pin: 'gd' 367 | tri_bthmx u28( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:378:14: Cell has missing pin: 'vd' 378 | tri_bthmx u29( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:378:14: Cell has missing pin: 'gd' 378 | tri_bthmx u29( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:389:14: Cell has missing pin: 'vd' 389 | tri_bthmx u30( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:389:14: Cell has missing pin: 'gd' 389 | tri_bthmx u30( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:400:14: Cell has missing pin: 'vd' 400 | tri_bthmx u31( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:400:14: Cell has missing pin: 'gd' 400 | tri_bthmx u31( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:411:14: Cell has missing pin: 'vd' 411 | tri_bthmx u32( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/trilib/tri_st_mult_boothrow.v:411:14: Cell has missing pin: 'gd' 411 | tri_bthmx u32( | ^~~ verilog/trilib/tri_st_mult_core.v:442:1: ... note: In file included from tri_st_mult_core.v verilog/trilib/tri_st_mult.v:503:1: ... note: In file included from tri_st_mult.v verilog/work/xu0.v:654:1: ... note: In file included from xu0.v verilog/work/xu.v:951:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:281:60: Cell has missing pin: 'q_b' 281 | tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION0_INIT)) fir_action0( | ^~~~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:293:60: Cell has missing pin: 'q_b' 293 | tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION0_PAR_INIT)) fir_action0_par( | ^~~~~~~~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:305:60: Cell has missing pin: 'q_b' 305 | tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION1_INIT)) fir_action1( | ^~~~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:317:60: Cell has missing pin: 'q_b' 317 | tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION1_PAR_INIT)) fir_action1_par( | ^~~~~~~~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:329:57: Cell has missing pin: 'q_b' 329 | tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_MASK_INIT)) fir_mask( | ^~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:341:57: Cell has missing pin: 'q_b' 341 | tri_nlat_scan #(.WIDTH(1), .INIT(FIR_MASK_PAR_INIT)) fir_mask_par( | ^~~~~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:353:52: Cell has missing pin: 'q_b' 353 | tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_INIT)) fir( | ^~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:369:39: Cell has missing pin: 'q_b' 369 | tri_nlat #(.WIDTH(1), .INIT(1'b0)) sys_xstop( | ^~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:381:39: Cell has missing pin: 'q_b' 381 | tri_nlat #(.WIDTH(1), .INIT(1'b0)) recov( | ^~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:393:39: Cell has missing pin: 'q_b' 393 | tri_nlat #(.WIDTH(1), .INIT(1'b0)) xstop( | ^~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:405:39: Cell has missing pin: 'q_b' 405 | tri_nlat #(.WIDTH(1), .INIT(1'b0)) trace_err( | ^~~~~~~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-PINMISSING: verilog/work/pcq_local_fir2.v:536:45: Cell has missing pin: 'q_b' 536 | tri_nlat #(.WIDTH(1), .INIT(1'b0)) mchk( | ^~~~ verilog/work/pcq_regs_fir.v:387:1: ... note: In file included from pcq_regs_fir.v verilog/work/pcq_regs.v:1501:1: ... note: In file included from pcq_regs.v verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-IMPLICIT: verilog/trilib_clk1x/tri_64x72_1r1w.v:214:11: Signal definition not found, creating implicitly: 'clk' : ... Suggested alternative: 'nclk' 214 | assign clk = nclk[0]; | ^~~ verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib/tri_slat_scan.v:68:35: Operator VAR 'initv' expects 16 bits on the Initial value, but Initial value's VARREF 'INIT' generates 32 bits. : ... In instance a2owb.c0.lq0.ctl.derat.bcfg_epn_32to47_latch 68 | parameter [0:WIDTH-1] initv = INIT; | ^~~~~ verilog/work/c_perv_rp.v:590:1: ... note: In file included from c_perv_rp.v verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib/tri_slat_scan.v:68:35: Operator VAR 'initv' expects 4 bits on the Initial value, but Initial value's VARREF 'INIT' generates 32 bits. : ... In instance a2owb.c0.lq0.ctl.derat.bcfg_epn_48to51_latch 68 | parameter [0:WIDTH-1] initv = INIT; | ^~~~~ verilog/work/c_perv_rp.v:590:1: ... note: In file included from c_perv_rp.v verilog/work/c.v:4855:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib/tri_aoi22_nlats_wlcb.v:93:35: Operator VAR 'init_v' expects 26 bits on the Initial value, but Initial value's VARREF 'INIT' generates 32 bits. : ... In instance a2owb.c0.xu0.spr.xu_spr_cspr.xucr0_latch.tri_ser_rlmreg_p 93 | parameter [0:WIDTH-1] init_v = INIT; | ^~~~~~ verilog/trilib/tri_ser_rlmreg_p.v:93:1: ... note: In file included from tri_ser_rlmreg_p.v verilog/work/iuq_spr.v:1003:1: ... note: In file included from iuq_spr.v verilog/work/iuq_ifetch.v:695:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib/tri_rlmlatch_p.v:63:26: Operator VAR 'init_v' expects 1 bits on the Initial value, but Initial value's VARREF 'INIT' generates 32 bits. : ... In instance a2owb.c0.iuq0.iuq_cpl_top0.iuq_cpl0.iuq_cpl_ctrl.xhdl6.q_depth_gen[32].genblk1.cp3_nia_a_latch 63 | parameter [0:WIDTH-1] init_v = INIT; | ^~~~~~ verilog/work/xu.v:1912:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:72:36: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map.read_ptr_inc0 72 | assign rollover = i[0:SIZE - 1] == WRAP; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:73:39: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map.read_ptr_inc0 73 | assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:72:36: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map.read_ptr_inc0 72 | assign rollover = i[0:SIZE - 1] == WRAP; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:73:39: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map.read_ptr_inc0 73 | assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:72:36: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map.read_ptr_inc0 72 | assign rollover = i[0:SIZE - 1] == WRAP; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:73:39: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map.read_ptr_inc0 73 | assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:72:36: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map.read_ptr_inc0 72 | assign rollover = i[0:SIZE - 1] == WRAP; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map_inc.v:73:39: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map.read_ptr_inc0 73 | assign rollover_m1 = i[0:SIZE - 1] == WRAP - 1; | ^~ verilog/work/iuq_rn_map.v:369:1: ... note: In file included from iuq_rn_map.v verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:199:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 199 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:201:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 201 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:203:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 203 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:205:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 205 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:207:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 207 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:209:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 209 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:232:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 232 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:234:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 234 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:236:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 236 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:238:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 238 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:240:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 240 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:242:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 242 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:277:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 277 | if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:283:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_1_wr_arc' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 283 | if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:267:115: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 5 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 267 | if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:393:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 or 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.axu_rn0.fpscr_rn_map 393 | free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; | ^ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:199:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 199 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:201:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 201 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:203:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 203 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:205:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 205 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:207:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 207 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:209:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 209 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:232:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 232 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:234:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 234 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:236:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 236 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:238:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 238 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:240:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 240 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:242:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 242 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:277:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 277 | if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:283:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_1_wr_arc' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 283 | if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:267:115: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 4 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 267 | if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:393:17: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.xer_rn_map 393 | free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; | ^ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:199:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 199 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:201:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 201 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:203:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 203 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:205:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 205 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:207:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 207 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:209:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 209 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:232:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 232 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:234:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 234 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:236:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 236 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:238:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 238 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:240:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 240 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:242:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 242 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:277:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 277 | if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:283:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_1_wr_arc' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 283 | if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:267:115: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 267 | if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:393:17: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.ctr_rn_map 393 | free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; | ^ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:393:17: Operator ASSIGN expects 5 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.cr_rn_map 393 | free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; | ^ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:199:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 199 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:201:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 201 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:203:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 203 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:205:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 205 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:207:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 207 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:209:19: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 209 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:232:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src1_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 232 | if (src1_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:234:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src2_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 234 | if (src2_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:236:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src3_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 236 | if (src3_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:238:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src4_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 238 | if (src4_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:240:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src5_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 240 | if (src5_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:242:21: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'src6_a' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 242 | if (src6_a == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:277:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 277 | if ((comp_0_wr_val == 1'b1) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:283:57: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_1_wr_arc' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 283 | if ((comp_1_wr_val == 1'b1) & comp_1_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:267:115: Operator EQ expects 32 bits on the LHS, but LHS's VARREF 'comp_0_wr_arc' generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 267 | if ((comp_0_wr_val == 1'b1) & (comp_1_wr_val == 1'b1) & (comp_0_wr_arc == comp_1_wr_arc) & comp_0_wr_arc == i) | ^~ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn_map.v:393:17: Operator ASSIGN expects 6 bits on the Assign RHS, but Assign RHS's SUB generates 32 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.gpr_rn_map 393 | free_cnt_d = REGISTER_RENAME_DEPTH - ARCHITECTED_REGISTER_DEPTH; | ^ verilog/work/iuq_rn.v:2661:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_cpl_ctrl_inc.v:63:16: Operator ASSIGNW expects 7 bits on the Assign RHS, but Assign RHS's REPLICATE generates 3 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.iu6_i0_itag_inc 63 | assign b = {1'b0, inc[0], inc[1]}; | ^ verilog/work/iuq_rn.v:2113:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_cpl_ctrl_inc.v:66:39: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.iu6_i0_itag_inc 66 | assign rollover = i[1:SIZE - 1] == WRAP; | ^~ verilog/work/iuq_rn.v:2113:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_cpl_ctrl_inc.v:67:42: Operator EQ expects 32 bits on the LHS, but LHS's SEL generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0.iu6_i0_itag_inc 67 | assign rollover_m1 = i[1:SIZE - 1] == WRAP - 1; | ^~ verilog/work/iuq_rn.v:2113:1: ... note: In file included from iuq_rn.v verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn.v:2161:54: Operator AND expects 7 bits on the LHS, but LHS's REPLICATE generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0 2161 | assign cp_credit_cnt_mux = ({6{high_pri_mask_l2}} & cp_high_credit_cnt_l2) | | ^ verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/iuq_rn.v:2162:55: Operator AND expects 7 bits on the LHS, but LHS's REPLICATE generates 6 bits. : ... In instance a2owb.c0.iuq0.iuq_slice_top0.slice0.rn_top0.fx_rn0 2162 | ({6{~high_pri_mask_l2}} & cp_med_credit_cnt_l2); | ^ verilog/work/iuq_rn_top.v:437:1: ... note: In file included from iuq_rn_top.v verilog/work/iuq_slice.v:711:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2537:13: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2537 | mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2540:13: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2540 | mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2545:42: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2545 | assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2546:43: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2546 | assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2547:46: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2547 | assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2548:48: Bit extraction of array[15:0] requires 4 bit index, not 9 bits. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_ierat0.ierat_cam 2548 | assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; | ^ verilog/work/iuq_ic_ierat.v:4471:1: ... note: In file included from iuq_ic_ierat.v verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_ldq_relq.v:593:24: Operator AND expects 4 bits on the LHS, but LHS's SEL generates 3 bits. : ... In instance a2owb.c0.lq0.lsq.ldq.relq 593 | cTag = (ldq[2:0] & {4{ldqe_rel_sel[ldq]}}) | cTag; | ^ verilog/work/lq_ldq.v:3140:1: ... note: In file included from lq_ldq.v verilog/work/lq_lsq.v:1649:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4671:13: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4671 | mem[bram0_addra][0:55] <= wr_array_data_bram[0:55]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4674:13: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4674 | mem[bram0_addra][56:62] <= wr_array_data_bram[66:72]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4679:42: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4679 | assign rd_array_data_d_std[0:55] = mem[bram0_addra][0:55]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4680:43: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4680 | assign rd_array_data_d_std[66:72] = mem[bram0_addra][56:62]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4681:46: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4681 | assign array_cmp_data_bram_std[0:55] = mem[bram0_addrb][0:55]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_cam_32x143_1r1w1c.v:4682:48: Bit extraction of array[31:0] requires 5 bit index, not 9 bits. : ... In instance a2owb.c0.lq0.ctl.derat.derat_cam 4682 | assign array_cmp_data_bramp_std[66:72] = mem[bram0_addrb][56:62]; | ^ verilog/work/lq_derat.v:4346:1: ... note: In file included from lq_derat.v verilog/work/lq_ctl.v:2985:1: ... note: In file included from lq_ctl.v verilog/work/lq.v:1390:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:134:13: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 134 | mem[w_addr_in_1] <= w_data_in_1; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:137:13: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 137 | mem[w_addr_in_2] <= w_data_in_2; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:140:13: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 140 | mem[w_addr_in_3] <= w_data_in_3; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:143:13: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 143 | mem[w_addr_in_4] <= w_data_in_4; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:149:22: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 149 | assign r1d_d = mem[r1a_q]; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_144x78_2r4w.v:150:22: Bit extraction of array[143:0] requires 8 bit index, not 6 bits. : ... In instance a2owb.c0.fupc.dp.a_fuq.fpr.fpr1 150 | assign r2d_d = mem[r2a_q]; | ^ verilog/work/rv.v:2247:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:365:23: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.imq 365 | iuTid = (tid & {2{iu_lq_request_q[tid]}}) | iuTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:365:52: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'iuTid' generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.imq 365 | iuTid = (tid & {2{iu_lq_request_q[tid]}}) | iuTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:365:16: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.imq 365 | iuTid = (tid & {2{iu_lq_request_q[tid]}}) | iuTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:366:23: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.imq 366 | mmTid = (tid & {2{mm_lq_lsu_req_q[tid]}}) | mmTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:366:52: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'mmTid' generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.imq 366 | mmTid = (tid & {2{mm_lq_lsu_req_q[tid]}}) | mmTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_imq.v:366:16: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.imq 366 | mmTid = (tid & {2{mm_lq_lsu_req_q[tid]}}) | mmTid; | ^ verilog/work/lq_lsq.v:2260:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1625:26: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1625 | entryI0 = (stq & {4{stq_wrt_i0_ptr[stq]}}) | entryI0; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1625:54: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'entryI0' generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1625 | entryI0 = (stq & {4{stq_wrt_i0_ptr[stq]}}) | entryI0; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1625:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1625 | entryI0 = (stq & {4{stq_wrt_i0_ptr[stq]}}) | entryI0; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1626:26: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1626 | entryI1 = (stq & {4{stq_wrt_i1_ptr[stq]}}) | entryI1; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1626:54: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'entryI1' generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1626 | entryI1 = (stq & {4{stq_wrt_i1_ptr[stq]}}) | entryI1; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1626:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1626 | entryI1 = (stq & {4{stq_wrt_i1_ptr[stq]}}) | entryI1; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1627:26: Operator AND expects 32 bits on the RHS, but RHS's REPLICATE generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1627 | cmmtTag = (stq & {4{stq3_cmmt_tag_entry[stq]}}) | cmmtTag; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1627:59: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'cmmtTag' generates 4 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1627 | cmmtTag = (stq & {4{stq3_cmmt_tag_entry[stq]}}) | cmmtTag; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:1627:19: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.stq 1627 | cmmtTag = (stq & {4{stq3_cmmt_tag_entry[stq]}}) | cmmtTag; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2199:25: Operator AND expects 32 bits on the RHS, but RHS's SEL generates 1 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2199 | stqTid = (tid & stq3_tid[tid]) | stqTid; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2199:42: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'stqTid' generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2199 | stqTid = (tid & stq3_tid[tid]) | stqTid; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2199:18: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2199 | stqTid = (tid & stq3_tid[tid]) | stqTid; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2218:23: Operator AND expects 32 bits on the RHS, but RHS's SEL generates 1 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2218 | tenc = (tid & ex4_req_thrd_id_q[tid]) | tenc; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2218:49: Operator OR expects 32 bits on the RHS, but RHS's VARREF 'tenc' generates 2 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2218 | tenc = (tid & ex4_req_thrd_id_q[tid]) | tenc; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_stq.v:2218:16: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS's OR generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.stq 2218 | tenc = (tid & ex4_req_thrd_id_q[tid]) | tenc; | ^ verilog/work/lq_lsq.v:1957:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/work/lq_odq.v:1890:29: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS's VARREF 'i' generates 32 bits. : ... In instance a2owb.c0.lq0.lsq.odq 1890 | remove_entry = i; | ^ verilog/work/lq_lsq.v:1517:1: ... note: In file included from lq_lsq.v verilog/work/lq.v:2072:1: ... note: In file included from lq.v verilog/work/c.v:3658:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_64x72_1r1w.v:221:29: Bit extraction of array[71:0] requires 7 bit index, not 6 bits. : ... In instance a2owb.c0.xu0.spr.xu_spr_aspr 221 | r0_d_q <= r0_e_q ? mem[r0_a_q] : 0; | ^ verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_64x72_1r1w.v:221:24: Operator COND expects 72 bits on the Conditional True, but Conditional True's ARRAYSEL generates 64 bits. : ... In instance a2owb.c0.xu0.spr.xu_spr_aspr 221 | r0_d_q <= r0_e_q ? mem[r0_a_q] : 0; | ^ verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_64x72_1r1w.v:224:13: Bit extraction of array[71:0] requires 7 bit index, not 6 bits. : ... In instance a2owb.c0.xu0.spr.xu_spr_aspr 224 | mem[w0_a_q] <= w0_d_q; | ^ verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_64x72_1r1w.v:224:22: Operator ASSIGNDLY expects 64 bits on the Assign RHS, but Assign RHS's VARREF 'w0_d_q' generates 72 bits. : ... In instance a2owb.c0.xu0.spr.xu_spr_aspr 224 | mem[w0_a_q] <= w0_d_q; | ^~ verilog/work/iuq_btb.v:170:1: ... note: In file included from iuq_btb.v verilog/work/iuq.v:1375:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_128x16_1r1w_1.v:255:29: Bit extraction of array[127:0] requires 7 bit index, not 9 bits. : ... In instance a2owb.c0.mmu0.tlb_gen_instance.lru_array0 255 | r_data_out_1_q <= mem[b0addrb]; | ^ verilog/work/mmq.v:4059:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_128x16_1r1w_1.v:257:13: Bit extraction of array[127:0] requires 7 bit index, not 9 bits. : ... In instance a2owb.c0.mmu0.tlb_gen_instance.lru_array0 257 | mem[b0addra] <= w_data_in_0; | ^ verilog/work/mmq.v:4059:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/trilib_clk1x/tri_128x16_1r1w_1.v:262:36: Bit extraction of array[127:0] requires 7 bit index, not 9 bits. : ... In instance a2owb.c0.mmu0.tlb_gen_instance.lru_array0 262 | assign r_data_out_0_bram = mem[b0addra]; | ^ verilog/work/mmq.v:4059:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-WIDTH: verilog/a2o_litex/a2l2wb.v:643:18: Operator ASSIGNW expects 32 bits on the Assign RHS, but Assign RHS's REPLICATE generates 39 bits. : ... In instance a2owb.n0 643 | assign status = {ac_an_pm_thread_running[0], ac_an_special_attn[0], ac_an_machine_check[0], | ^ verilog/a2o_litex/a2owb.v:383:1: ... note: In file included from a2owb.v %Warning-SPLITVAR: verilog/work/iuq_ic_select.v:586:21: 'need_fetch' has split_var metacomment but will not be split because index cannot be determined statically. : ... In instance a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0 586 | need_fetch[t][i] = ib_ic_need_fetch[t][i] & (~|(iu0_sent_l2[t][i])); | ^ verilog/work/iuq_ic.v:699:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v %Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[3].bram_model.MEM' : ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A verilog/unisims/bram_model.v:44:13: ... Location of first driving block 44 | MEM[ADDRB] <= DIB; | ^~~ verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/unisims/bram_model.v:36:13: ... Location of other driving block 36 | MEM[ADDRA] <= DIA; | ^~~ %Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[2].bram_model.MEM' : ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A verilog/unisims/bram_model.v:44:13: ... Location of first driving block 44 | MEM[ADDRB] <= DIB; | ^~~ verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/unisims/bram_model.v:36:13: ... Location of other driving block 36 | MEM[ADDRA] <= DIA; | ^~~ %Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[1].bram_model.MEM' : ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A verilog/unisims/bram_model.v:44:13: ... Location of first driving block 44 | MEM[ADDRB] <= DIB; | ^~~ verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/unisims/bram_model.v:36:13: ... Location of other driving block 36 | MEM[ADDRA] <= DIA; | ^~~ %Warning-MULTIDRIVEN: verilog/unisims/bram_model.v:22:24: Signal has multiple driving blocks with different clocking: 'unnamedblk1.ra[0].bram_model.MEM' : ... In instance a2owb.c0.lq0.ctl.dc32Kdir64B.arr.arr0_A verilog/unisims/bram_model.v:44:13: ... Location of first driving block 44 | MEM[ADDRB] <= DIB; | ^~~ verilog/unisims/RAMB16_S36_S36.v:72:1: ... note: In file included from RAMB16_S36_S36.v verilog/trilib/tri_128x168_1w_0.v:225:1: ... note: In file included from tri_128x168_1w_0.v verilog/work/mmq.v:3813:1: ... note: In file included from mmq.v verilog/work/c.v:4173:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/unisims/bram_model.v:36:13: ... Location of other driving block 36 | MEM[ADDRA] <= DIA; | ^~~ %Warning-UNOPTFLAT: verilog/work/iuq_ic_ierat.v:93:38: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out' : ... In instance a2owb.c0.iuq0 93 | output time_scan_out, | ^~~~~~~~~~~~~ verilog/work/iuq_ic.v:527:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ic_ierat.v:93:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out verilog/work/iuq_ic.v:566:8: Example path: ASSIGNW verilog/work/iuq_ic_ierat.v:91:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellinp__iuq_ic_ierat0__time_scan_in verilog/trilib_clk1x/tri_cam_16x143_1r1w1c.v:2684:25: Example path: ASSIGNW verilog/work/iuq_ic_ierat.v:93:38: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.__Vcellout__iuq_ic_ierat0__time_scan_out %Warning-UNOPTFLAT: verilog/work/xu_spr.v:458:34: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.xu0.spr.siv_repr' : ... In instance a2owb.c0 458 | wire [0:2] siv_repr /*verilator split_var*/ ; | ^~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/xu_spr.v:458:34: Example path: a2owb.c0.xu0.spr.siv_repr verilog/work/xu_spr.v:1129:8: Example path: ASSIGNW verilog/trilib_clk1x/tri_64x72_1r1w.v:129:40: Example path: a2owb.c0.xu0.spr.__Vcellinp__xu_spr_aspr__repr_scan_in verilog/work/xu_spr.v:1844:25: Example path: ASSIGNW verilog/work/xu_spr.v:458:34: Example path: a2owb.c0.xu0.spr.siv_repr %Warning-UNOPTFLAT: verilog/work/xu_spr.v:454:34: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.xu0.spr.siv_time' : ... In instance a2owb.c0 454 | wire [0:2] siv_time /*verilator split_var*/ ; | ^~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/xu_spr.v:454:34: Example path: a2owb.c0.xu0.spr.siv_time verilog/work/xu_spr.v:1127:8: Example path: ASSIGNW verilog/trilib_clk1x/tri_64x72_1r1w.v:127:40: Example path: a2owb.c0.xu0.spr.__Vcellinp__xu_spr_aspr__time_scan_in verilog/work/xu_spr.v:1841:25: Example path: ASSIGNW verilog/work/xu_spr.v:454:34: Example path: a2owb.c0.xu0.spr.siv_time %Warning-UNOPTFLAT: verilog/work/xu_spr.v:446:34: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.xu0.spr.siv_abst' : ... In instance a2owb.c0 446 | wire [0:scan_right_abst-1] siv_abst /*verilator split_var*/ ; | ^~~~~~~~ verilog/work/xu.v:1556:1: ... note: In file included from xu.v verilog/work/c.v:2515:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/xu_spr.v:446:34: Example path: a2owb.c0.xu0.spr.siv_abst verilog/work/xu_spr.v:1125:8: Example path: ASSIGNW verilog/trilib_clk1x/tri_64x72_1r1w.v:125:40: Example path: a2owb.c0.xu0.spr.__Vcellinp__xu_spr_aspr__abst_scan_in verilog/work/xu_spr.v:1829:41: Example path: ASSIGNW verilog/work/xu_spr.v:446:34: Example path: a2owb.c0.xu0.spr.siv_abst %Warning-UNOPTFLAT: verilog/work/pcq_regs.v:338:26: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.fupc.pc0.pcq_regs.func_siv' 338 | wire [0:FUNC_RIGHT] func_siv /*verilator split_var*/ ; | ^~~~~~~~ verilog/work/pcq.v:393:1: ... note: In file included from pcq.v verilog/work/c_fu_pc.v:518:1: ... note: In file included from c_fu_pc.v verilog/work/c.v:4463:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/pcq_regs.v:338:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_siv verilog/work/pcq_regs.v:2277:87: Example path: ASSIGNW verilog/work/pcq_regs.v:339:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_sov[194:201] verilog/work/pcq_regs.v:2402:34: Example path: ASSIGNW verilog/work/pcq_regs.v:338:26: Example path: a2owb.c0.fupc.pc0.pcq_regs.func_siv %Warning-UNOPTFLAT: verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in' : ... In instance a2owb.c0.iuq0.bht0 126 | input func_scan_in; | ^~~~~~~~~~~~ verilog/trilib/tri_bht_1024x8_1r1w.v:332:1: ... note: In file included from tri_bht_1024x8_1r1w.v verilog/work/iuq.v:1831:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Example path: a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in verilog/trilib/tri_bht_1024x8_1r1w.v:348:17: Example path: ASSIGNW verilog/trilib/tri_bht_1024x8_1r1w.v:220:27: Example path: a2owb.c0.iuq0.bht0.sov verilog/trilib/tri_bht_1024x8_1r1w.v:347:17: Example path: ASSIGNW verilog/trilib_clk1x/tri_512x16_1r1w_1.v:126:51: Example path: a2owb.c0.iuq0.bht0.__Vcellinp__bht0__func_scan_in %Warning-UNOPTFLAT: verilog/work/iuq_ibuf.v:176:42: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out' : ... In instance a2owb.c0.iuq0 176 | wire [0:1] valid_out; | ^~~~~~~~~ verilog/work/iuq_slice.v:471:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ibuf.v:176:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out verilog/work/iuq_ibuf.v:682:22: Example path: ASSIGNW verilog/work/iuq_ibuf.v:261:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.error_hole verilog/work/iuq_ibuf.v:596:21: Example path: ASSIGNW verilog/work/iuq_ibuf.v:176:42: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.valid_out %Warning-UNOPTFLAT: verilog/work/iuq_ic_dir.v:566:35: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_dir0.siv' : ... In instance a2owb.c0.iuq0 566 | wire [0:scan_right] siv /*verilator split_var*/ ; | ^~~ verilog/work/iuq_ic.v:829:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ic_dir.v:566:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_dir0.siv verilog/work/iuq_ic_dir.v:1449:8: Example path: ASSIGNW verilog/work/iuq_ic_dir.v:567:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_dir0.sov verilog/work/iuq_ic_dir.v:2468:29: Example path: ASSIGNW verilog/work/iuq_ic_dir.v:566:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_dir0.siv %Warning-UNOPTFLAT: verilog/work/rv_station.v:661:35: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.rv0.fx0_rvs.rvs.siv' : ... In instance a2owb.c0 661 | wire [0:scan_right-1] siv /*verilator split_var*/ ; | ^~~ verilog/work/rv_fx0_rvs.v:533:1: ... note: In file included from rv_fx0_rvs.v verilog/work/rv.v:1551:1: ... note: In file included from rv.v verilog/work/c.v:3163:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/rv_station.v:661:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.siv verilog/work/rv_station.v:1827:63: Example path: ASSIGNW verilog/work/rv_station.v:662:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.sov verilog/work/rv_fx0_rvs.v:651:9: Example path: ASSIGNW verilog/work/rv_fx0_rvs.v:443:30: Example path: a2owb.c0.rv0.fx0_rvs.sov verilog/work/rv_station.v:3329:31: Example path: ASSIGNW verilog/work/rv_station.v:661:35: Example path: a2owb.c0.rv0.fx0_rvs.rvs.siv %Warning-UNOPTFLAT: verilog/work/iuq_bp.v:798:13: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new' : ... In instance a2owb.c0.iuq0 798 | wire [0:15] bcache_data_new /*verilator split_var*/ ; | ^~~~~~~~~~~~~~~ verilog/work/iuq_ifetch.v:1062:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_bp.v:798:13: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new verilog/work/iuq_bp.v:1049:28: Example path: ASSIGNW verilog/work/iuq_bp.v:815:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_hit verilog/work/iuq_bp.v:1013:27: Example path: ASSIGNW verilog/work/iuq_bp.v:791:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.ex5_bh0_hist verilog/work/iuq_bp.v:996:38: Example path: ASSIGNW verilog/work/iuq_bp.v:795:12: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_bh0_wr_data verilog/work/iuq_bp.v:1022:36: Example path: ASSIGNW verilog/work/iuq_bp.v:798:13: Example path: a2owb.c0.iuq0.iuq_ifetch0.xhdl0.bp_gen[0].iuq_bp0.bcache_data_new %Warning-UNOPTFLAT: verilog/work/iuq_ibuf.v:130:41: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0)' : ... In instance a2owb.c0.iuq0 130 | reg [0:IBUFF_WIDTH-1] buffer_data_q[0:16-1] /*verilator split_var*/ ; | ^~~~~~~~~~~~~ verilog/work/iuq_slice.v:471:1: ... note: In file included from iuq_slice.v verilog/work/iuq_slice_top.v:961:1: ... note: In file included from iuq_slice_top.v verilog/work/iuq.v:2033:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ibuf.v:130:41: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0) verilog/work/iuq_ibuf.v:433:8: Example path: ALWAYS verilog/work/iuq_ibuf.v:130:41: Example path: a2owb.c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q(0) %Warning-UNOPTFLAT: verilog/work/iuq_ic_select.v:408:30: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready' : ... In instance a2owb.c0.iuq0 408 | wire [0:1-1] thread_ready; | ^~~~~~~~~~~~ verilog/work/iuq_ic.v:699:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ic_select.v:408:30: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready verilog/work/iuq_ic_select.v:572:4: Example path: ALWAYS verilog/work/iuq_ic_select.v:400:27: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.need_fetch verilog/work/iuq_ic_select.v:686:24: Example path: ASSIGNW verilog/work/iuq_ic_select.v:408:30: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_select0.thread_ready %Warning-UNOPTFLAT: verilog/work/iuq_ic_miss.v:428:35: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm' : ... In instance a2owb.c0.iuq0 428 | wire release_sm; | ^~~~~~~~~~ verilog/work/iuq_ic.v:1019:1: ... note: In file included from iuq_ic.v verilog/work/iuq_ifetch.v:810:1: ... note: In file included from iuq_ifetch.v verilog/work/iuq.v:1403:1: ... note: In file included from iuq.v verilog/work/c.v:1817:1: ... note: In file included from c.v verilog/a2o_litex/a2owb.v:255:1: ... note: In file included from a2owb.v verilog/work/iuq_ic_miss.v:428:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm verilog/work/iuq_ic_miss_table.v:159:22: Example path: ASSIGNW verilog/work/iuq_ic_miss_table.v:68:25: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.unnamedblk1.miss_sm_loop[0].miss_sm.miss_sm_pt verilog/work/iuq_ic_miss.v:802:24: Example path: ASSIGNW verilog/work/iuq_ic_miss.v:428:35: Example path: a2owb.c0.iuq0.iuq_ifetch0.iuq_ic0.iuq_ic_miss0.release_sm %Warning-UNOPTFLAT: verilog/a2o_litex/a2owb.v:86:24: Signal unoptimizable: Feedback to clock or circular logic: 'a2owb.nclk' : ... In instance a2owb 86 | wire [0:6-1] nclk; | ^~~~ verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk verilog/trilib_clk1x/tri_512x16_1r1w_1.v:213:17: Example path: ASSIGNW verilog/trilib_clk1x/tri_512x16_1r1w_1.v:178:51: Example path: a2owb.c0.iuq0.bht2.bht0.clk verilog/trilib_clk1x/tri_512x16_1r1w_1.v:217:8: Example path: ACTIVE verilog/trilib_clk1x/tri_512x16_1r1w_1.v:217:8: Example path: ASSIGNPRE verilog/trilib_clk1x/tri_512x16_1r1w_1.v:188:51: Example path: a2owb.c0.iuq0.bht2.bht0.__Vdly__reset_q verilog/trilib_clk1x/tri_512x16_1r1w_1.v:215:6: Example path: ALWAYS verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk verilog/a2o_litex/a2owb.v:209:13: Example path: ASSIGNW verilog/a2o_litex/a2owb.v:86:24: Example path: a2owb.nclk