Copyright 1986-2020 Xilinx, Inc. All Rights Reserved. -------------------------------------------------------------------------------------------------------------- | Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020 | Date : Wed Aug 3 19:38:40 2022 | Host : gridl294.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.9 (Maipo) | Command : report_utilization -hierarchical -file cmod7_utilization_hierarchical_synth.rpt | Design : cmod7 | Device : 7k410tffv676-1 | Design State : Synthesized -------------------------------------------------------------------------------------------------------------- Utilization Design Information Table of Contents ----------------- 1. Utilization by Hierarchy 1. Utilization by Hierarchy --------------------------- +-----------------------------------------------------------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ | Instance | Module | Total LUTs | Logic LUTs | LUTRAMs | SRLs | FFs | RAMB36 | RAMB18 | DSP Blocks | +-----------------------------------------------------------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+ | cmod7 | (top) | 242181 | 241623 | 556 | 2 | 96706 | 116 | 13 | 0 | | (cmod7) | (top) | 163 | 147 | 16 | 0 | 309 | 20 | 1 | 0 | | a2owb | a2owb | 242018 | 241476 | 540 | 2 | 96397 | 96 | 12 | 0 | | c0 | c | 241529 | 240987 | 540 | 2 | 95676 | 96 | 12 | 0 | | fupc | c_fu_pc | 30285 | 30284 | 0 | 1 | 12787 | 0 | 0 | 0 | | dp.a_fuq | fu | 28069 | 28069 | 0 | 0 | 11589 | 0 | 0 | 0 | | dcd | fu_dcd | 3263 | 3263 | 0 | 0 | 734 | 0 | 0 | 0 | | a0esr_lat | tri_ser_rlmreg_p__parameterized6_9647 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_9697 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized12_9648 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | axu_ex | tri_rlmreg_p__parameterized9_9649 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | axucr0_lat | tri_rlmreg_p__parameterized9_9650 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | cp_flush_reg0 | tri_rlmlatch_p_9651 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_frt | tri_rlmreg_p__parameterized7_9652 | 24 | 24 | 0 | 0 | 24 | 0 | 0 | 0 | | ex0_iu | tri_rlmreg_p__parameterized12_9653 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_crbf | tri_rlmreg_p__parameterized4_9654 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_frt | tri_rlmreg_p__parameterized53_9655 | 1043 | 1043 | 0 | 0 | 30 | 0 | 0 | 0 | | ex1_instl | tri_rlmreg_p__parameterized17_9656 | 222 | 222 | 0 | 0 | 32 | 0 | 0 | 0 | | ex1_itagl | tri_rlmreg_p__parameterized41_9657 | 13 | 13 | 0 | 0 | 13 | 0 | 0 | 0 | | ex1_iu | tri_rlmreg_p__parameterized43_9658 | 103 | 103 | 0 | 0 | 11 | 0 | 0 | 0 | | ex2_crbf | tri_rlmreg_p__parameterized4_9659 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_ctl | tri_rlmreg_p__parameterized255_9660 | 46 | 46 | 0 | 0 | 18 | 0 | 0 | 0 | | ex2_frt | tri_rlmreg_p__parameterized0_9661 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_itagl | tri_rlmreg_p__parameterized3_9662 | 13 | 13 | 0 | 0 | 14 | 0 | 0 | 0 | | ex3_crbf | tri_rlmreg_p__parameterized4_9663 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_ctl_lat | tri_rlmreg_p__parameterized7_9664 | 24 | 24 | 0 | 0 | 20 | 0 | 0 | 0 | | ex3_ctlng_lat | tri_rlmreg_p__parameterized13_9665 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_itagl | tri_rlmreg_p__parameterized3_9666 | 13 | 13 | 0 | 0 | 14 | 0 | 0 | 0 | | ex3_stdv_lat | tri_rlmreg_p__parameterized37_9667 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_crbf | tri_rlmreg_p__parameterized4_9668 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_ctl | tri_rlmreg_p__parameterized53_9669 | 34 | 34 | 0 | 0 | 19 | 0 | 0 | 0 | | ex4_itagl | tri_rlmreg_p__parameterized3_9670 | 19 | 19 | 0 | 0 | 14 | 0 | 0 | 0 | | ex5_crbf | tri_rlmreg_p__parameterized4_9671 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_ctl_lat | tri_rlmreg_p__parameterized257_9672 | 18 | 18 | 0 | 0 | 17 | 0 | 0 | 0 | | ex5_itagl | tri_rlmreg_p__parameterized51_9673 | 13 | 13 | 0 | 0 | 15 | 0 | 0 | 0 | | ex6_crbf | tri_rlmreg_p__parameterized46_9674 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | ex6_ctl | tri_rlmreg_p__parameterized255_9675 | 7 | 7 | 0 | 0 | 17 | 0 | 0 | 0 | | ex6_itagl | tri_rlmreg_p__parameterized51_9676 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | | ex7_crbf | tri_rlmreg_p__parameterized46_9677 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ex7_ctl | tri_rlmreg_p__parameterized311_9678 | 477 | 477 | 0 | 0 | 20 | 0 | 0 | 0 | | ex7_itagl | tri_rlmreg_p__parameterized14_9679 | 38 | 38 | 0 | 0 | 15 | 0 | 0 | 0 | | ex7_la | tri_rlmreg_p__parameterized14_9680 | 42 | 42 | 0 | 0 | 16 | 0 | 0 | 0 | | ex8_ctl | tri_rlmreg_p__parameterized17_9681 | 110 | 110 | 0 | 0 | 30 | 0 | 0 | 0 | | ex8_itagl | tri_rlmreg_p__parameterized12_9682 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | ex8_la | tri_rlmreg_p__parameterized14_9683 | 451 | 451 | 0 | 0 | 16 | 0 | 0 | 0 | | ex8_ram_lat | tri_rlmreg_p__parameterized312_9684 | 64 | 64 | 0 | 0 | 65 | 0 | 0 | 0 | | ex8_ramv_lat | tri_rlmreg_p__parameterized37_9685 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex9_ctl | tri_rlmreg_p__parameterized41_9686 | 20 | 20 | 0 | 0 | 14 | 0 | 0 | 0 | | ex9_la | tri_rlmreg_p__parameterized46_9687 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | fu_parity_recovery | tri_parity_recovery | 247 | 247 | 0 | 0 | 93 | 0 | 0 | 0 | | ex2_perr | tri_rlmreg_p__parameterized7_9690 | 25 | 25 | 0 | 0 | 24 | 0 | 0 | 0 | | ex3_perr | tri_rlmreg_p__parameterized7_9691 | 30 | 30 | 0 | 0 | 24 | 0 | 0 | 0 | | ex4_ctl_perr | tri_rlmreg_p__parameterized9_9692 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | exx_regfile_err_det_lat | tri_rlmreg_p__parameterized46_9693 | 7 | 7 | 0 | 0 | 9 | 0 | 0 | 0 | | holdall_lat | tri_rlmreg_p__parameterized37_9694 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | perr_ctl | tri_rlmreg_p__parameterized214_9695 | 101 | 101 | 0 | 0 | 28 | 0 | 0 | 0 | | perr_sm | tri_rlmreg_p__parameterized189_9696 | 80 | 80 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_ctl | tri_rlmreg_p__parameterized43_9688 | 80 | 80 | 0 | 0 | 13 | 0 | 0 | 0 | | spr_data | tri_rlmreg_p__parameterized33_9689 | 46 | 46 | 0 | 0 | 64 | 0 | 0 | 0 | | fpr | fu_fpr | 10676 | 10676 | 0 | 0 | 5962 | 0 | 0 | 0 | | ex1_par | tri_rlmreg_p__parameterized281 | 0 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | | ex6_lctl | tri_rlmreg_p__parameterized4_9639 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_ldv | tri_rlmreg_p__parameterized2_9640 | 194 | 194 | 0 | 0 | 35 | 0 | 0 | 0 | | ex7_lctl | tri_rlmreg_p__parameterized227_9641 | 129 | 129 | 0 | 0 | 11 | 0 | 0 | 0 | | ex7_ldat | tri_rlmreg_p__parameterized279 | 1432 | 1432 | 0 | 0 | 64 | 0 | 0 | 0 | | ex7_rlctl | tri_rlmreg_p__parameterized6_9642 | 2224 | 2224 | 0 | 0 | 9 | 0 | 0 | 0 | | ex7_rldat | tri_rlmreg_p__parameterized279_9643 | 1578 | 1578 | 0 | 0 | 64 | 0 | 0 | 0 | | fpr0 | tri_144x78_2r4w_9644 | 69 | 69 | 0 | 0 | 338 | 0 | 0 | 0 | | fpr1 | tri_144x78_2r4w_9645 | 5032 | 5032 | 0 | 0 | 5010 | 0 | 0 | 0 | | ldwt_lat | tri_rlmreg_p__parameterized282 | 4 | 4 | 0 | 0 | 130 | 0 | 0 | 0 | | reldwt_lat | tri_rlmreg_p__parameterized282_9646 | 0 | 0 | 0 | 0 | 130 | 0 | 0 | 0 | | tgwt_lat | tri_rlmreg_p__parameterized283 | 12 | 12 | 0 | 0 | 134 | 0 | 0 | 0 | | mad | fu_mad | 13823 | 13823 | 0 | 0 | 4757 | 0 | 0 | 0 | | (mad) | fu_mad | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | | fadd | fu_add | 150 | 150 | 0 | 0 | 174 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized21_9636 | 51 | 51 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_cmp_lat | tri_inv_nlats__parameterized25 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_res_hi_lat | tri_inv_nlats__parameterized13_9637 | 40 | 40 | 0 | 0 | 53 | 0 | 0 | 0 | | ex5_res_lo_lat | tri_inv_nlats__parameterized23_9638 | 54 | 54 | 0 | 0 | 110 | 0 | 0 | 0 | | falg | fu_alg | 525 | 525 | 0 | 0 | 123 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9632 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ctl_lat | tri_rlmreg_p__parameterized22_9633 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_ctl_lat | tri_inv_nlats__parameterized22_9634 | 177 | 177 | 0 | 0 | 15 | 0 | 0 | 0 | | ex3_shc_lat | tri_inv_nlats__parameterized21 | 192 | 192 | 0 | 0 | 24 | 0 | 0 | 0 | | ex3_shd_lat | tri_inv_nlats__parameterized20 | 143 | 143 | 0 | 0 | 68 | 0 | 0 | 0 | | ex4_ctl_lat | tri_rlmreg_p__parameterized20_9635 | 8 | 8 | 0 | 0 | 11 | 0 | 0 | 0 | | fbyp | fu_byp | 3544 | 3544 | 0 | 0 | 444 | 0 | 0 | 0 | | ex2_expo_a_alg_lat | tri_inv_nlats__parameterized17 | 92 | 92 | 0 | 0 | 13 | 0 | 0 | 0 | | ex2_expo_a_eie_lat | tri_inv_nlats__parameterized16 | 1 | 1 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_a_fmt_lat | tri_inv_nlats__parameterized16_9621 | 30 | 30 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_b_alg_lat | tri_inv_nlats__parameterized16_9622 | 10 | 10 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_b_eie_lat | tri_inv_nlats__parameterized16_9623 | 24 | 24 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_b_fmt_lat | tri_inv_nlats__parameterized16_9624 | 48 | 48 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_c_alg_lat | tri_inv_nlats__parameterized17_9625 | 0 | 0 | 0 | 0 | 13 | 0 | 0 | 0 | | ex2_expo_c_eie_lat | tri_inv_nlats__parameterized16_9626 | 54 | 54 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_expo_c_fmt_lat | tri_inv_nlats__parameterized16_9627 | 12 | 12 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_frac_a_fmt_lat | tri_inv_nlats__parameterized13_9628 | 145 | 145 | 0 | 0 | 53 | 0 | 0 | 0 | | ex2_frac_a_mul_lat | tri_inv_nlats__parameterized15 | 2860 | 2860 | 0 | 0 | 55 | 0 | 0 | 0 | | ex2_frac_b_alg_lat | tri_inv_nlats__parameterized13_9629 | 187 | 187 | 0 | 0 | 53 | 0 | 0 | 0 | | ex2_frac_b_fmt_lat | tri_inv_nlats__parameterized13_9630 | 50 | 50 | 0 | 0 | 53 | 0 | 0 | 0 | | ex2_frac_c_fmt_lat | tri_inv_nlats__parameterized13_9631 | 30 | 30 | 0 | 0 | 53 | 0 | 0 | 0 | | ex2_frac_c_mul_lat | tri_inv_nlats__parameterized14 | 1 | 1 | 0 | 0 | 53 | 0 | 0 | 0 | | fcr2 | fu_cr2 | 66 | 66 | 0 | 0 | 66 | 0 | 0 | 0 | | ex2_ctl_lat | tri_rlmreg_p__parameterized271_9618 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | ex3_ctl_lat | tri_rlmreg_p__parameterized262_9619 | 22 | 22 | 0 | 0 | 22 | 0 | 0 | 0 | | ex4_ctl_lat | tri_rlmreg_p__parameterized262_9620 | 44 | 44 | 0 | 0 | 22 | 0 | 0 | 0 | | fdsq | fu_divsqrt | 3671 | 3671 | 0 | 0 | 1145 | 0 | 0 | 0 | | (fdsq) | fu_divsqrt | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | | DIVSQRT_XOR2_exx_lev22_csaout_sum_div | tri_xor2__parameterized3 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized294_9605 | 7 | 7 | 0 | 0 | 10 | 0 | 0 | 0 | | ex1_div_ctr_lat | tri_rlmreg_p__parameterized204_9606 | 599 | 599 | 0 | 0 | 21 | 0 | 0 | 0 | | ex1_div_instr_lat | tri_rlmreg_p__parameterized298 | 43 | 43 | 0 | 0 | 12 | 0 | 0 | 0 | | ex2_div_a_stage_lat | tri_rlmreg_p__parameterized300 | 54 | 54 | 0 | 0 | 71 | 0 | 0 | 0 | | ex2_div_b_stage_lat | tri_rlmreg_p__parameterized300_9607 | 111 | 111 | 0 | 0 | 71 | 0 | 0 | 0 | | ex2_div_exp_lat | tri_rlmreg_p__parameterized56_9608 | 267 | 267 | 0 | 0 | 52 | 0 | 0 | 0 | | ex2_div_fpscr_addr_cr_bf_lat | tri_rlmreg_p__parameterized299_9609 | 44 | 44 | 0 | 0 | 24 | 0 | 0 | 0 | | ex2_div_instr_lat | tri_rlmreg_p__parameterized291_9610 | 231 | 231 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_div_itag_lat | tri_rlmreg_p__parameterized21_9611 | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | | ex3_div_PR_sum4carry4_lat | tri_rlmreg_p__parameterized294_9612 | 118 | 118 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_div_PR_sumcarry_lat | tri_rlmreg_p__parameterized301 | 452 | 452 | 0 | 0 | 113 | 0 | 0 | 0 | | ex3_div_Q_QM_lat | tri_rlmreg_p__parameterized301_9613 | 61 | 61 | 0 | 0 | 114 | 0 | 0 | 0 | | ex3_div_bQ_QM_lat | tri_rlmreg_p__parameterized301_9614 | 229 | 229 | 0 | 0 | 112 | 0 | 0 | 0 | | ex3_div_denom_lat | tri_rlmreg_p__parameterized303 | 0 | 0 | 0 | 0 | 53 | 0 | 0 | 0 | | ex3_div_hangcounter_lat | tri_rlmreg_p__parameterized12_9615 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_sqrt_bitmask_lat | tri_rlmreg_p__parameterized302 | 305 | 305 | 0 | 0 | 110 | 0 | 0 | 0 | | ex4_div_done_lat | tri_rlmreg_p__parameterized26_9616 | 180 | 180 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_div_result_lat | tri_rlmreg_p__parameterized304 | 539 | 539 | 0 | 0 | 93 | 0 | 0 | 0 | | ex5_special_case_lat | tri_rlmreg_p__parameterized305 | 40 | 40 | 0 | 0 | 160 | 0 | 0 | 0 | | ex6_div_result_lat | tri_rlmreg_p__parameterized306 | 7 | 7 | 0 | 0 | 66 | 0 | 0 | 0 | | exx_div_denorm_lat | tri_rlmreg_p__parameterized268_9617 | 367 | 367 | 0 | 0 | 26 | 0 | 0 | 0 | | feie | fu_eie | 255 | 255 | 0 | 0 | 47 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9600 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_bop_lat | tri_rlmreg_p__parameterized288_9601 | 38 | 38 | 0 | 0 | 13 | 0 | 0 | 0 | | ex3_ctl_lat | tri_rlmreg_p__parameterized18_9602 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_pop_lat | tri_rlmreg_p__parameterized288_9603 | 200 | 200 | 0 | 0 | 13 | 0 | 0 | 0 | | ex4_iexp_lat | tri_rlmreg_p__parameterized289_9604 | 16 | 16 | 0 | 0 | 13 | 0 | 0 | 0 | | feov | fu_eov | 71 | 71 | 0 | 0 | 59 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9596 | 17 | 17 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_iexp_lat | tri_rlmreg_p__parameterized290_9597 | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | | ex6_misc_lat | tri_rlmreg_p__parameterized288 | 23 | 23 | 0 | 0 | 12 | 0 | 0 | 0 | | ex6_ovctl_lat | tri_nand2_nlats__parameterized0_9598 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_urnd0_lat | tri_nand2_nlats | 9 | 9 | 0 | 0 | 13 | 0 | 0 | 0 | | ex6_urnd1_lat | tri_nand2_nlats_9599 | 2 | 2 | 0 | 0 | 13 | 0 | 0 | 0 | | ffmt | fu_fmt | 15 | 15 | 0 | 0 | 88 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized18_9594 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_ctl_lat | tri_rlmreg_p__parameterized21_9595 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_pass_lat | tri_rlmreg_p__parameterized287 | 10 | 10 | 0 | 0 | 78 | 0 | 0 | 0 | | fgst | fu_gst | 345 | 345 | 0 | 0 | 120 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized294 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_gst_ctrl_lat | tri_rlmreg_p__parameterized295 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_gst_stage_lat | tri_rlmreg_p__parameterized296 | 153 | 153 | 0 | 0 | 31 | 0 | 0 | 0 | | ex4_gst_ctrl_lat | tri_rlmreg_p__parameterized295_9589 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_gst_stage_lat | tri_rlmreg_p__parameterized15_9590 | 54 | 54 | 0 | 0 | 20 | 0 | 0 | 0 | | ex5_gst_ctrl_lat | tri_rlmreg_p__parameterized26_9591 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_gst_stage_lat | tri_rlmreg_p__parameterized297 | 109 | 109 | 0 | 0 | 24 | 0 | 0 | 0 | | ex6_gst_ctrl_lat | tri_rlmreg_p__parameterized295_9592 | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_gst_stage_lat | tri_rlmreg_p__parameterized16_9593 | 1 | 1 | 0 | 0 | 31 | 0 | 0 | 0 | | flza | fu_lza | 507 | 507 | 0 | 0 | 191 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized291 | 9 | 9 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_lzo_lat | tri_inv_nlats__parameterized26 | 1 | 1 | 0 | 0 | 163 | 0 | 0 | 0 | | ex4_sub_lat | tri_inv_nlats__parameterized27 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_amt_lat | tri_nand2_nlats__parameterized1 | 204 | 204 | 0 | 0 | 16 | 0 | 0 | 0 | | ex5_dcd_lat | tri_inv_nlats__parameterized28 | 292 | 292 | 0 | 0 | 9 | 0 | 0 | 0 | | flze | fu_lze | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9587 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_shr_lat | tri_rlmreg_p__parameterized21_9588 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | fmul | tri_fu_mul | 499 | 499 | 0 | 0 | 428 | 0 | 0 | 0 | | m92_0 | tri_fu_mul_92__parameterized1 | 312 | 312 | 0 | 0 | 140 | 0 | 0 | 0 | | pp3_lat_car | tri_inv_nlats__parameterized19_9585 | 173 | 173 | 0 | 0 | 68 | 0 | 0 | 0 | | pp3_lat_sum | tri_inv_nlats__parameterized18_9586 | 139 | 139 | 0 | 0 | 72 | 0 | 0 | 0 | | m92_1 | tri_fu_mul_92__parameterized0 | 14 | 14 | 0 | 0 | 144 | 0 | 0 | 0 | | pp3_lat_car | tri_inv_nlats__parameterized19_9583 | 12 | 12 | 0 | 0 | 71 | 0 | 0 | 0 | | pp3_lat_sum | tri_inv_nlats__parameterized18_9584 | 2 | 2 | 0 | 0 | 73 | 0 | 0 | 0 | | m92_2 | tri_fu_mul_92 | 173 | 173 | 0 | 0 | 144 | 0 | 0 | 0 | | pp3_lat_car | tri_inv_nlats__parameterized19 | 77 | 77 | 0 | 0 | 71 | 0 | 0 | 0 | | pp3_lat_sum | tri_inv_nlats__parameterized18 | 96 | 96 | 0 | 0 | 73 | 0 | 0 | 0 | | fnrm | fu_nrm | 117 | 117 | 0 | 0 | 106 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized26_9582 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_fmv_lat | tri_rlmreg_p__parameterized293 | 0 | 0 | 0 | 0 | 33 | 0 | 0 | 0 | | ex6_nrm_lg_lat | tri_nand2_nlats__parameterized3 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_nrm_pass_lat | tri_rlmreg_p__parameterized292 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | | ex6_nrm_x_lat | tri_nand2_nlats__parameterized0 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_res_lat | tri_nand2_nlats__parameterized2 | 99 | 99 | 0 | 0 | 53 | 0 | 0 | 0 | | fpic | fu_pic | 300 | 300 | 0 | 0 | 263 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized255_9575 | 28 | 28 | 0 | 0 | 16 | 0 | 0 | 0 | | ex2_ctl_lat | tri_rlmreg_p__parameterized307 | 47 | 47 | 0 | 0 | 37 | 0 | 0 | 0 | | ex3_ctl_lat | tri_rlmreg_p__parameterized308 | 54 | 54 | 0 | 0 | 41 | 0 | 0 | 0 | | ex3_flg_lat | tri_rlmreg_p__parameterized14_9576 | 35 | 35 | 0 | 0 | 18 | 0 | 0 | 0 | | ex4_ctl_lat | tri_rlmreg_p__parameterized271_9577 | 23 | 23 | 0 | 0 | 27 | 0 | 0 | 0 | | ex4_flg_lat | tri_rlmreg_p__parameterized309 | 23 | 23 | 0 | 0 | 30 | 0 | 0 | 0 | | ex4_scr_lat | tri_rlmreg_p__parameterized12_9578 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_ctl_lat | tri_rlmreg_p__parameterized263 | 33 | 33 | 0 | 0 | 20 | 0 | 0 | 0 | | ex5_flg_lat | tri_rlmreg_p__parameterized61_9579 | 28 | 28 | 0 | 0 | 28 | 0 | 0 | 0 | | ex5_scr_lat | tri_rlmreg_p__parameterized12_9580 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_flg_lat | tri_rlmreg_p__parameterized219_9581 | 26 | 26 | 0 | 0 | 34 | 0 | 0 | 0 | | frnd | fu_rnd | 288 | 288 | 0 | 0 | 94 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9573 | 9 | 9 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ctl_lat | tri_rlmreg_p__parameterized290 | 77 | 77 | 0 | 0 | 16 | 0 | 0 | 0 | | ex7_expo_lat | tri_rlmreg_p__parameterized289 | 19 | 19 | 0 | 0 | 14 | 0 | 0 | 0 | | ex7_flag_lat | tri_rlmreg_p__parameterized6_9574 | 169 | 169 | 0 | 0 | 9 | 0 | 0 | 0 | | ex7_frac_lat | tri_rlmreg_p__parameterized280 | 14 | 14 | 0 | 0 | 53 | 0 | 0 | 0 | | fsa3 | fu_sa3 | 1156 | 1156 | 0 | 0 | 273 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized22_9572 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_000_lat | tri_inv_nlats__parameterized13 | 188 | 188 | 0 | 0 | 53 | 0 | 0 | 0 | | ex4_053_car_lat | tri_inv_nlats__parameterized24 | 423 | 423 | 0 | 0 | 109 | 0 | 0 | 0 | | ex4_053_sum_lat | tri_inv_nlats__parameterized23 | 544 | 544 | 0 | 0 | 110 | 0 | 0 | 0 | | fscr | fu_oscr | 1600 | 1600 | 0 | 0 | 940 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized41_9563 | 48 | 48 | 0 | 0 | 6 | 0 | 0 | 0 | | cadd_lat_thr0 | tri_rlmreg_p__parameterized9_9564 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | cfpscr_thr0_lat | tri_rlmreg_p__parameterized52_9565 | 34 | 34 | 0 | 0 | 35 | 0 | 0 | 0 | | ex5_ctl_lat | tri_rlmreg_p__parameterized262 | 22 | 22 | 0 | 0 | 22 | 0 | 0 | 0 | | ex6_ctl_lat | tri_rlmreg_p__parameterized262_9566 | 20 | 20 | 0 | 0 | 22 | 0 | 0 | 0 | | ex7_ctl_lat | tri_rlmreg_p__parameterized262_9567 | 111 | 111 | 0 | 0 | 22 | 0 | 0 | 0 | | ex7_flag_lat | tri_rlmreg_p__parameterized268_9568 | 518 | 518 | 0 | 0 | 25 | 0 | 0 | 0 | | ex7_mvdat_lat | tri_rlmreg_p__parameterized52_9569 | 33 | 33 | 0 | 0 | 33 | 0 | 0 | 0 | | ex8_crf_lat | tri_rlmreg_p__parameterized9_9570 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | fpscr_th0_lat | tri_rlmreg_p__parameterized299_9571 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oscr_hscr_arr_thr1.hfpscr_thr0_lat | tri_rlmreg_p__parameterized310 | 814 | 814 | 0 | 0 | 768 | 0 | 0 | 0 | | ftbe | fu_tblexp | 43 | 43 | 0 | 0 | 21 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized4_9561 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_expo_lat | tri_rlmreg_p__parameterized8_9562 | 32 | 32 | 0 | 0 | 20 | 0 | 0 | 0 | | ftbl | fu_tbllut | 666 | 666 | 0 | 0 | 165 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized13_9559 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_lut_lat | tri_rlmreg_p__parameterized0_9560 | 162 | 162 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_lut_b_lat | tri_inv_nlats__parameterized30 | 23 | 23 | 0 | 0 | 16 | 0 | 0 | 0 | | ex4_lut_e_lat | tri_inv_nlats__parameterized29 | 14 | 14 | 0 | 0 | 20 | 0 | 0 | 0 | | ex4_lut_r_lat | tri_inv_nlats__parameterized22 | 285 | 285 | 0 | 0 | 15 | 0 | 0 | 0 | | ex5_lut_lat | tri_inv_nlats__parameterized31 | 175 | 175 | 0 | 0 | 77 | 0 | 0 | 0 | | ex6_lut_lat | tri_rlmreg_p__parameterized299 | 0 | 0 | 0 | 0 | 28 | 0 | 0 | 0 | | sto | fu_sto | 307 | 307 | 0 | 0 | 136 | 0 | 0 | 0 | | act_lat | tri_rlmreg_p__parameterized9_9558 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sins_lat | tri_rlmreg_p__parameterized284 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_sop_lat | tri_rlmreg_p__parameterized285 | 263 | 263 | 0 | 0 | 65 | 0 | 0 | 0 | | ex3_sto_lat | tri_rlmreg_p__parameterized286 | 40 | 40 | 0 | 0 | 67 | 0 | 0 | 0 | | pc0 | pcq | 2216 | 2215 | 0 | 1 | 1198 | 0 | 0 | 0 | | (pc0) | pcq | 266 | 266 | 0 | 0 | 0 | 0 | 0 | 0 | | pcq_clks | pcq_clks | 1 | 0 | 0 | 1 | 1 | 0 | 0 | 0 | | clkctrl | pcq_clks_ctrl | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fast_stop_staging | tri_plat__parameterized2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | clkstg | pcq_clks_stg | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | lvl5to4_plat | tri_plat__parameterized8_9557 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | 0 | | pcq_ctrl | pcq_ctrl | 1 | 1 | 0 | 0 | 28 | 0 | 0 | 0 | | holdcntr | tri_rlmreg_p__parameterized5_9553 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | initactive | tri_rlmlatch_p__parameterized1_9554 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | initcntr | tri_rlmreg_p__parameterized314 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | initerat | tri_rlmlatch_p_9555 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pmctrls_t0 | tri_rlmreg_p__parameterized43_9556 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | pcq_regs | pcq_regs | 1872 | 1872 | 0 | 0 | 972 | 0 | 0 | 0 | | axrv_dbgsel_reg | tri_rlmreg_p__parameterized257_9501 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | bcfg_stage1_t0 | tri_rlmreg_p__parameterized259_9502 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | bcfg_stage2_t0 | tri_ser_rlmreg_p__parameterized30 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized30 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | dcfg_stage1 | tri_rlmreg_p__parameterized9_9503 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | errdbg_t0 | tri_rlmreg_p__parameterized43_9504 | 14 | 14 | 0 | 0 | 15 | 0 | 0 | 0 | | errinj_reg | tri_rlmreg_p__parameterized311_9505 | 15 | 15 | 0 | 0 | 23 | 0 | 0 | 0 | | fir_regs | pcq_regs_fir | 381 | 381 | 0 | 0 | 270 | 0 | 0 | 0 | | (fir_regs) | pcq_regs_fir | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | | FIR0 | pcq_local_fir2 | 202 | 202 | 0 | 0 | 118 | 0 | 0 | 0 | | fir | tri_nlat_scan__parameterized11_9546 | 18 | 18 | 0 | 0 | 28 | 0 | 0 | 0 | | fir_action0 | tri_nlat_scan__parameterized6 | 11 | 11 | 0 | 0 | 28 | 0 | 0 | 0 | | fir_action0_par | tri_nlat_scan__parameterized7_9547 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action1 | tri_nlat_scan__parameterized8 | 15 | 15 | 0 | 0 | 28 | 0 | 0 | 0 | | fir_action1_par | tri_nlat_scan__parameterized9_9548 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_mask | tri_nlat_scan__parameterized10 | 104 | 104 | 0 | 0 | 28 | 0 | 0 | 0 | | fir_mask_par | tri_nlat_scan__parameterized7_9549 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mchkgen.mchk | tri_nlat__parameterized0_9550 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | sys_xstop | tri_nlat__parameterized0_9551 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xstop | tri_nlat__parameterized0_9552 | 53 | 53 | 0 | 0 | 1 | 0 | 0 | 0 | | FIR1 | pcq_local_fir2__parameterized0 | 115 | 115 | 0 | 0 | 86 | 0 | 0 | 0 | | fir | tri_nlat_scan__parameterized15_9539 | 2 | 2 | 0 | 0 | 20 | 0 | 0 | 0 | | fir_action0 | tri_nlat_scan__parameterized12 | 13 | 13 | 0 | 0 | 20 | 0 | 0 | 0 | | fir_action0_par | tri_nlat_scan__parameterized7_9540 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action1 | tri_nlat_scan__parameterized13 | 8 | 8 | 0 | 0 | 20 | 0 | 0 | 0 | | fir_action1_par | tri_nlat_scan__parameterized9_9541 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_mask | tri_nlat_scan__parameterized14 | 70 | 70 | 0 | 0 | 20 | 0 | 0 | 0 | | fir_mask_par | tri_nlat_scan__parameterized7_9542 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mchkgen.mchk | tri_nlat__parameterized0_9543 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | sys_xstop | tri_nlat__parameterized0_9544 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xstop | tri_nlat__parameterized0_9545 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | FIR2 | pcq_local_fir2__parameterized1 | 14 | 14 | 0 | 0 | 9 | 0 | 0 | 0 | | fir | tri_nlat_scan__parameterized7 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action0 | tri_nlat_scan__parameterized7_9533 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action0_par | tri_nlat_scan__parameterized7_9534 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action1 | tri_nlat_scan__parameterized7_9535 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_action1_par | tri_nlat_scan__parameterized7_9536 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_mask | tri_nlat_scan__parameterized9 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | fir_mask_par | tri_nlat_scan__parameterized9_9537 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mchkgen.mchk | tri_nlat__parameterized0 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xstop | tri_nlat__parameterized0_9538 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | error_out | tri_nlat_scan__parameterized17 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | f0err_out | tri_nlat_scan__parameterized11 | 23 | 23 | 0 | 0 | 26 | 0 | 0 | 0 | | f1err_out | tri_nlat_scan__parameterized15 | 7 | 7 | 0 | 0 | 10 | 0 | 0 | 0 | | sc_ack_err | tri_err_rpt__parameterized1 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | hold | tri_nlat_scan__parameterized5_9532 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | scom_err | tri_err_rpt__parameterized0 | 11 | 11 | 0 | 0 | 11 | 0 | 0 | 0 | | hold | tri_nlat_scan__parameterized16 | 11 | 11 | 0 | 0 | 11 | 0 | 0 | 0 | | fu_ram_din | tri_rlmreg_p__parameterized33_9506 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | func_stage1 | tri_rlmreg_p__parameterized2_9507 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | func_stage3 | tri_ser_rlmreg_p__parameterized13_9508 | 188 | 188 | 0 | 0 | 15 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized13_9531 | 188 | 188 | 0 | 0 | 15 | 0 | 0 | 0 | | inj_stage1_t0 | tri_ser_rlmreg_p__parameterized20_9509 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized20_9530 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | iu_dbgsel_reg | tri_rlmreg_p__parameterized257_9510 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lq_dbgsel_reg | tri_rlmreg_p__parameterized257_9511 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lq_ram_din | tri_rlmreg_p__parameterized312 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | mmpc_dbgsel_reg | tri_rlmreg_p__parameterized257_9512 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | pccr0_par | tri_rlmreg_p__parameterized37_9513 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pccr0_reg | tri_rlmreg_p__parameterized43_9514 | 26 | 26 | 0 | 0 | 15 | 0 | 0 | 0 | | ramc_reg | tri_rlmreg_p__parameterized311_9515 | 11 | 11 | 0 | 0 | 23 | 0 | 0 | 0 | | ramd_reg | tri_rlmreg_p__parameterized33_9516 | 8 | 8 | 0 | 0 | 64 | 0 | 0 | 0 | | rami_reg | tri_rlmreg_p__parameterized17_9517 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | rec_err_cntr | tri_rlmreg_p__parameterized9_9518 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | sc_misc | tri_ser_rlmreg_p__parameterized31 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized31 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | scaddr_dec | tri_rlmreg_p__parameterized33_9519 | 540 | 540 | 0 | 0 | 49 | 0 | 0 | 0 | | scomsat | tri_serial_scom2 | 624 | 624 | 0 | 0 | 104 | 0 | 0 | 0 | | ack_info | tri_nlat_scan__parameterized5 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | cch_latches | tri_nlat_scan__parameterized5_9526 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | | counter | tri_nlat_scan__parameterized1 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | data_shifter | tri_nlat_scan__parameterized2 | 300 | 300 | 0 | 0 | 64 | 0 | 0 | 0 | | datapar_shifter | tri_nlat_scan__parameterized3 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | dch_inlatch | tri_nlat | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | head_lat | tri_nlat_scan__parameterized4 | 69 | 69 | 0 | 0 | 12 | 0 | 0 | 0 | | scom_err_latch | tri_nlat_9527 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | scom_local_act_latch | tri_nlat_9528 | 30 | 30 | 0 | 0 | 1 | 0 | 0 | 0 | | state | tri_nlat_scan__parameterized0 | 193 | 193 | 0 | 0 | 5 | 0 | 0 | 0 | | tail_lat | tri_nlat_scan__parameterized0_9529 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | spattn_data_reg | tri_rlmreg_p__parameterized37_9520 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spattn_mask_reg | tri_rlmreg_p__parameterized313 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spattn_par | tri_rlmreg_p__parameterized42_9521 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | thrctl1_reg | tri_rlmreg_p__parameterized227_9522 | 2 | 2 | 0 | 0 | 12 | 0 | 0 | 0 | | thrctl2_reg | tri_rlmreg_p__parameterized12_9523 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | xu_dbgsel_reg | tri_rlmreg_p__parameterized50_9524 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | | xu_ram_din | tri_rlmreg_p__parameterized312_9525 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | pcq_spr | pcq_spr | 76 | 76 | 0 | 0 | 197 | 0 | 0 | 0 | | cesr1_is0_reg | tri_ser_rlmreg_p__parameterized16_9481 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized16_9500 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | cesr1_is1_reg | tri_ser_rlmreg_p__parameterized16_9482 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized16_9499 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | cesr1_reg | tri_ser_rlmreg_p__parameterized17_9483 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized17_9498 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_9484 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | misc_reg | tri_rlmreg_p__parameterized2_9485 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | resr1_reg | tri_ser_rlmreg_p__parameterized21_9486 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized21_9497 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | resr2_reg | tri_ser_rlmreg_p__parameterized21_9487 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized21_9496 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | slowspr_addr_reg | tri_rlmreg_p__parameterized6_9488 | 68 | 68 | 0 | 0 | 10 | 0 | 0 | 0 | | slowspr_data_reg | tri_rlmreg_p__parameterized33_9489 | 7 | 7 | 0 | 0 | 64 | 0 | 0 | 0 | | slowspr_done_reg | tri_rlmlatch_p_9490 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_etid_reg | tri_rlmreg_p__parameterized2_9491 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_rw_reg | tri_rlmlatch_p_9492 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_val_reg | tri_rlmlatch_p_9493 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | sramd_reg | tri_ser_rlmreg_p__parameterized12_9494 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_9495 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | iuq0 | iuq | 53985 | 53445 | 540 | 0 | 19347 | 25 | 6 | 0 | | bht0 | tri_bht_1024x8_1r1w | 41 | 41 | 0 | 0 | 64 | 1 | 0 | 0 | | (bht0) | tri_bht_1024x8_1r1w | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | bht0 | tri_512x16_1r1w_1_9473 | 6 | 6 | 0 | 0 | 20 | 1 | 0 | 0 | | data_in_reg | tri_rlmreg_p__parameterized2_9474 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | data_out_reg | tri_rlmreg_p__parameterized12_9475 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | r_act_reg | tri_rlmlatch_p_9476 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | r_addr_reg | tri_rlmreg_p__parameterized6_9477 | 4 | 4 | 0 | 0 | 10 | 0 | 0 | 0 | | reset_w_addr_reg | tri_rlmreg_p__parameterized46_9478 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | | w_act_reg | tri_rlmreg_p__parameterized9_9479 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | w_addr_reg | tri_rlmreg_p__parameterized6_9480 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | bht1 | tri_bht_1024x8_1r1w_7075 | 41 | 41 | 0 | 0 | 63 | 1 | 0 | 0 | | (bht1) | tri_bht_1024x8_1r1w_7075 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | bht0 | tri_512x16_1r1w_1_9465 | 6 | 6 | 0 | 0 | 19 | 1 | 0 | 0 | | data_in_reg | tri_rlmreg_p__parameterized2_9466 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | data_out_reg | tri_rlmreg_p__parameterized12_9467 | 14 | 14 | 0 | 0 | 8 | 0 | 0 | 0 | | r_act_reg | tri_rlmlatch_p_9468 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r_addr_reg | tri_rlmreg_p__parameterized6_9469 | 4 | 4 | 0 | 0 | 10 | 0 | 0 | 0 | | reset_w_addr_reg | tri_rlmreg_p__parameterized46_9470 | 15 | 15 | 0 | 0 | 9 | 0 | 0 | 0 | | w_act_reg | tri_rlmreg_p__parameterized9_9471 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | w_addr_reg | tri_rlmreg_p__parameterized6_9472 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | bht2 | tri_bht_512x4_1r1w | 34 | 34 | 0 | 0 | 44 | 1 | 0 | 0 | | (bht2) | tri_bht_512x4_1r1w | 0 | 0 | 0 | 0 | 0 | 0 | 0 | 0 | | bht0 | tri_512x16_1r1w_1 | 8 | 8 | 0 | 0 | 7 | 1 | 0 | 0 | | data_in_reg | tri_rlmlatch_p_9458 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | data_out_reg | tri_rlmreg_p__parameterized9_9459 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | r_act_reg | tri_rlmlatch_p_9460 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | r_addr_reg | tri_rlmreg_p__parameterized46_9461 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | reset_w_addr_reg | tri_rlmreg_p__parameterized46_9462 | 14 | 14 | 0 | 0 | 9 | 0 | 0 | 0 | | w_act_reg | tri_rlmreg_p__parameterized9_9463 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | w_addr_reg | tri_rlmreg_p__parameterized46_9464 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | iuq_btb0 | iuq_btb | 69 | 69 | 0 | 0 | 146 | 1 | 0 | 0 | | btb0 | tri_64x72_1r1w_9451 | 3 | 3 | 0 | 0 | 44 | 1 | 0 | 0 | | data_in_reg | tri_rlmreg_p | 0 | 0 | 0 | 0 | 41 | 0 | 0 | 0 | | data_out_reg | tri_rlmreg_p_9452 | 12 | 12 | 0 | 0 | 41 | 0 | 0 | 0 | | r_act_reg | tri_rlmlatch_p_9453 | 44 | 44 | 0 | 0 | 1 | 0 | 0 | 0 | | r_addr_reg | tri_rlmreg_p__parameterized0_9454 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | reset_w_addr_reg | tri_rlmreg_p__parameterized0_9455 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | w_act_reg | tri_rlmlatch_p_9456 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | w_addr_reg | tri_rlmreg_p__parameterized0_9457 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | iuq_cpl_top0 | iuq_cpl_top | 12680 | 12140 | 540 | 0 | 3801 | 0 | 0 | 0 | | iuq_cpl0 | iuq_cpl | 12680 | 12140 | 540 | 0 | 3801 | 0 | 0 | 0 | | iuq_cpl_arr | tri_iuq_cpl_arr | 3200 | 2660 | 540 | 0 | 564 | 0 | 0 | 0 | | iuq_cpl_ctrl | iuq_cpl_ctrl | 8970 | 8970 | 0 | 0 | 3232 | 0 | 0 | 0 | | async_delay_cnt_latch | tri_rlmreg_p__parameterized5_8593 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | attn_hold_latch | tri_rlmlatch_p_8594 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_exception_latch | tri_rlmreg_p__parameterized9_8595 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | axu0_exception_val_latch | tri_rlmlatch_p_8596 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_execute_vld_latch | tri_rlmlatch_p_8597 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_flush2ucode_latch | tri_rlmlatch_p_8598 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_itag_latch | tri_rlmreg_p__parameterized13_8599 | 89 | 89 | 0 | 0 | 6 | 0 | 0 | 0 | | axu0_n_flush_latch | tri_rlmlatch_p_8600 | 21 | 21 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_n_np1_flush_latch | tri_rlmlatch_p_8601 | 18 | 18 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_np1_flush_latch | tri_rlmlatch_p_8602 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | br_bta_latch | tri_rlmreg_p__parameterized40_8603 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | br_execute_vld_latch | tri_rlmlatch_p_8604 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | br_itag_latch | tri_rlmreg_p__parameterized13_8605 | 220 | 220 | 0 | 0 | 7 | 0 | 0 | 0 | | br_redirect_latch | tri_rlmlatch_p_8606 | 41 | 41 | 0 | 0 | 1 | 0 | 0 | 0 | | br_taken_latch | tri_rlmlatch_p_8607 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ccr2_ucode_dis_latch | tri_rlmlatch_p_8608 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cdbell_int_latch | tri_rlmlatch_p_8609 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp1_br_bta_itag_latch | tri_rlmreg_p__parameterized13_8610 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | cp1_br_bta_latch | tri_rlmreg_p__parameterized40_8611 | 126 | 126 | 0 | 0 | 62 | 0 | 0 | 0 | | cp1_br_bta_v_latch | tri_rlmlatch_p_8612 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp1_dispatched_latch | tri_rlmreg_p__parameterized17_8613 | 15 | 15 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_executed_latch | tri_rlmreg_p__parameterized17_8614 | 37 | 37 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_flush2ucode_latch | tri_rlmreg_p__parameterized17_8615 | 17 | 17 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_flush2ucode_type_latch | tri_rlmreg_p__parameterized17_8616 | 34 | 34 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_i0_dispatched_delay_latch | tri_rlmreg_p__parameterized17_8617 | 34 | 34 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_i0_itag_latch | tri_rlmreg_p__parameterized13_8618 | 15 | 15 | 0 | 0 | 6 | 0 | 0 | 0 | | cp1_i0_ptr0_latch | tri_rlmreg_p__parameterized42_8619 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp1_i0_ptr1_latch | tri_rlmreg_p__parameterized214_8620 | 899 | 899 | 0 | 0 | 31 | 0 | 0 | 0 | | cp1_i1_dispatched_delay_latch | tri_rlmreg_p__parameterized17_8621 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_i1_itag_latch | tri_rlmreg_p__parameterized101_8622 | 15 | 15 | 0 | 0 | 6 | 0 | 0 | 0 | | cp1_i1_ptr0_latch | tri_rlmreg_p__parameterized215_8623 | 28 | 28 | 0 | 0 | 2 | 0 | 0 | 0 | | cp1_i1_ptr1_latch | tri_rlmreg_p__parameterized53_8624 | 909 | 909 | 0 | 0 | 30 | 0 | 0 | 0 | | cp1_n_flush_latch | tri_rlmreg_p__parameterized17_8625 | 94 | 94 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_n_np1_flush_latch | tri_rlmreg_p__parameterized17_8626 | 12 | 12 | 0 | 0 | 32 | 0 | 0 | 0 | | cp1_np1_flush_latch | tri_rlmreg_p__parameterized17_8627 | 18 | 18 | 0 | 0 | 32 | 0 | 0 | 0 | | cp2_async_int_latch | tri_rlmreg_p__parameterized216 | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | | cp2_async_int_val_latch | tri_rlmlatch_p_8628 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_flush_latch | tri_rlmlatch_p_8629 | 221 | 221 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_axu_excvec_latch | tri_rlmreg_p__parameterized9_8630 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | cp2_i0_axu_excvec_val_latch | tri_rlmlatch_p_8631 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_bp_pred_latch | tri_rlmlatch_p_8632 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_br_miss_latch | tri_rlmlatch_p_8633 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_br_pred_latch | tri_rlmlatch_p_8634 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_completed_latch | tri_rlmlatch_p_8635 | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_db_events_latch | tri_rlmreg_p__parameterized204_8636 | 43 | 43 | 0 | 0 | 19 | 0 | 0 | 0 | | cp2_i0_db_val_latch | tri_rlmlatch_p_8637 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_flush2ucode_latch | tri_rlmlatch_p_8638 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_flush2ucode_type_latch | tri_rlmlatch_p_8639 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_itag_latch | tri_rlmreg_p__parameterized13_8640 | 186 | 186 | 0 | 0 | 6 | 0 | 0 | 0 | | cp2_i0_iu_excvec_latch | tri_rlmreg_p__parameterized9_8641 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | cp2_i0_iu_excvec_val_latch | tri_rlmlatch_p_8642 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_lq_excvec_latch | tri_rlmreg_p__parameterized0_8643 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | cp2_i0_lq_excvec_val_latch | tri_rlmlatch_p_8644 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_n_np1_flush_latch | tri_rlmlatch_p_8645 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_np1_flush_latch | tri_rlmlatch_p_8646 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i0_xu_excvec_latch | tri_rlmreg_p__parameterized4_8647 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | cp2_i0_xu_excvec_val_latch | tri_rlmlatch_p_8648 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8649 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | cp2_i1_axu_excvec_val_latch | tri_rlmlatch_p_8650 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_bp_pred_latch | tri_rlmlatch_p_8651 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_br_miss_latch | tri_rlmlatch_p_8652 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_br_pred_latch | tri_rlmlatch_p_8653 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_completed_latch | tri_rlmlatch_p_8654 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_db_events_latch | tri_rlmreg_p__parameterized204_8655 | 5 | 5 | 0 | 0 | 19 | 0 | 0 | 0 | | cp2_i1_db_val_latch | tri_rlmlatch_p_8656 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_flush2ucode_latch | tri_rlmlatch_p_8657 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_flush2ucode_type_latch | tri_rlmlatch_p_8658 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_itag_latch | tri_rlmreg_p__parameterized101_8659 | 190 | 190 | 0 | 0 | 6 | 0 | 0 | 0 | | cp2_i1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8660 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | cp2_i1_iu_excvec_val_latch | tri_rlmlatch_p_8661 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8662 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | cp2_i1_lq_excvec_val_latch | tri_rlmlatch_p_8663 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_n_np1_flush_latch | tri_rlmlatch_p_8664 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_np1_flush_latch | tri_rlmlatch_p_8665 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8666 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | cp2_i1_xu_excvec_val_latch | tri_rlmlatch_p_8667 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | cp2_i_bta_latch | tri_rlmreg_p__parameterized40_8668 | 5 | 5 | 0 | 0 | 62 | 0 | 0 | 0 | | cp3_ap_latch | tri_rlmlatch_p_8669 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_ap_save_latch | tri_rlmlatch_p_8670 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_async_hold_latch | tri_rlmlatch_p_8671 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_async_int_latch | tri_rlmreg_p__parameterized17_8672 | 124 | 124 | 0 | 0 | 31 | 0 | 0 | 0 | | cp3_async_int_val_latch | tri_rlmlatch_p_8673 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_attn_latch | tri_rlmlatch_p_8674 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_axu_excvec_latch | tri_rlmreg_p__parameterized9_8675 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | cp3_axu_excvec_val_latch | tri_rlmlatch_p_8676 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_db_events_latch | tri_rlmreg_p__parameterized204_8677 | 90 | 90 | 0 | 0 | 19 | 0 | 0 | 0 | | cp3_db_val_latch | tri_rlmlatch_p_8678 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_epid_latch | tri_rlmlatch_p_8679 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_epid_save_latch | tri_rlmlatch_p_8680 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_flush2ucode_latch | tri_rlmlatch_p_8681 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_flush2ucode_type_latch | tri_rlmlatch_p_8682 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_flush_latch | tri_rlmlatch_p_8683 | 72 | 72 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_flush_nonspec_latch | tri_rlmlatch_p_8684 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_fp_latch | tri_rlmlatch_p_8685 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_fp_save_latch | tri_rlmlatch_p_8686 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_icmp_block_latch | tri_rlmlatch_p_8687 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_ifar_latch | tri_rlmreg_p__parameterized204_8688 | 19 | 19 | 0 | 0 | 19 | 0 | 0 | 0 | | cp3_iu_excvec_latch | tri_rlmreg_p__parameterized9_8689 | 17 | 17 | 0 | 0 | 4 | 0 | 0 | 0 | | cp3_iu_excvec_val_latch | tri_rlmlatch_p_8690 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_lq_excvec_latch | tri_rlmreg_p__parameterized0_8691 | 59 | 59 | 0 | 0 | 6 | 0 | 0 | 0 | | cp3_lq_excvec_val_latch | tri_rlmlatch_p_8692 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_mispredict_latch | tri_rlmlatch_p_8693 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_np1_flush_latch | tri_rlmlatch_p_8694 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_preissue_latch | tri_rlmlatch_p_8695 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_rfi_latch | tri_rlmlatch_p_8696 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_spv_latch | tri_rlmlatch_p_8697 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_spv_save_latch | tri_rlmlatch_p_8698 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_st_latch | tri_rlmlatch_p_8699 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_st_save_latch | tri_rlmlatch_p_8700 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_ucode_latch | tri_rlmlatch_p_8701 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp3_xu_excvec_latch | tri_rlmreg_p__parameterized4_8702 | 32 | 32 | 0 | 0 | 5 | 0 | 0 | 0 | | cp3_xu_excvec_val_latch | tri_rlmlatch_p_8703 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_asyn_icmp_needed_latch | tri_rlmlatch_p_8704 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_asyn_irpt_needed_latch | tri_rlmlatch_p_8705 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_async_n_latch | tri_rlmlatch_p_8706 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_async_np1_latch | tri_rlmlatch_p_8707 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_c_int_latch | tri_rlmlatch_p_8708 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_cdbell_int_latch | tri_rlmlatch_p_8709 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_dbell_int_latch | tri_rlmlatch_p_8710 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_dbsr_latch | tri_rlmreg_p__parameterized204_8711 | 19 | 19 | 0 | 0 | 19 | 0 | 0 | 0 | | cp4_dbsr_update_latch | tri_rlmlatch_p_8712 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_dear_update_latch | tri_rlmlatch_p_8713 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_dp_cp_async_bus_snoop_flush_latch | tri_rlmlatch_p_8714 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_dp_cp_async_flush_latch | tri_rlmlatch_p_8715 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_eheir_update_latch | tri_rlmlatch_p_8716 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_esr_update_latch | tri_rlmlatch_p_8717 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_exc_esr_latch | tri_rlmreg_p__parameterized51_8718 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | cp4_exc_mcsr_latch | tri_rlmreg_p__parameterized43_8719 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | cp4_exc_nia_latch | tri_rlmreg_p__parameterized40_8720 | 113 | 113 | 0 | 0 | 58 | 0 | 0 | 0 | | cp4_exc_val_latch | tri_rlmlatch_p_8721 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_flush_latch | tri_rlmlatch_p_8722 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_g_int_latch | tri_rlmlatch_p_8723 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_gcdbell_int_latch | tri_rlmlatch_p_8724 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_gdbell_int_latch | tri_rlmlatch_p_8725 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_gmcdbell_int_latch | tri_rlmlatch_p_8726 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_mc_int_latch | tri_rlmlatch_p_8727 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_mchk_disabled_latch | tri_rlmlatch_p_8728 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_pc_stop_latch | tri_rlmlatch_p_8729 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | cp4_rfi_latch | tri_rlmlatch_p_8730 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp5_rfi_latch | tri_rlmlatch_p_8731 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp6_rfi_latch | tri_rlmlatch_p_8732 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp7_rfi_latch | tri_rlmlatch_p_8733 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp8_rfi_latch | tri_rlmlatch_p_8734 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_mm_except_taken_latch | tri_rlmreg_p__parameterized0_8735 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | cp_next_itag_latch | tri_rlmreg_p__parameterized13_8736 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | | dbcr0_brt_latch | tri_rlmlatch_p_8737 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_edm_latch | tri_rlmlatch_p_8738 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_icmp_latch | tri_rlmlatch_p_8739 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_idm_latch | tri_rlmlatch_p_8740 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_irpt_latch | tri_rlmlatch_p_8741 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_ret_latch | tri_rlmlatch_p_8742 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr0_trap_latch | tri_rlmlatch_p_8743 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr1_iac12m_latch | tri_rlmlatch_p_8744 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr1_iac34m_latch | tri_rlmlatch_p_8745 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr3_ivc_latch | tri_rlmlatch_p_8746 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dbell_int_latch | tri_rlmlatch_p_8747 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbg_event_en_latch | tri_rlmlatch_p_8748 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | dbg_int_en_latch | tri_rlmlatch_p_8749 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | dbsr_int_latch | tri_rlmlatch_p_8750 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dec_int_latch | tri_rlmlatch_p_8751 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dp_cp_bus_snoop_hold_req_latch | tri_rlmlatch_p_8752 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dp_cp_hold_req_latch | tri_rlmlatch_p_8753 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | eheir_val_latch | tri_rlmlatch_p_8754 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_dsigs_latch | tri_rlmlatch_p_8755 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_dtlbgs_latch | tri_rlmlatch_p_8756 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_duvd_latch | tri_rlmlatch_p_8757 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_extgs_latch | tri_rlmlatch_p_8758 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_gicm_latch | tri_rlmlatch_p_8759 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_icm_latch | tri_rlmlatch_p_8760 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_isigs_latch | tri_rlmlatch_p_8761 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_itlbgs_latch | tri_rlmlatch_p_8762 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_dbg_act_err_latch | tri_rlmlatch_p_8763 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_dbg_stop_latch | tri_rlmlatch_p_8764 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | fex_int_latch | tri_rlmlatch_p_8765 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fit_int_latch | tri_rlmlatch_p_8766 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | flush_delay_latch | tri_rlmreg_p__parameterized2_8767 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | flush_hold_latch | tri_rlmreg_p__parameterized2_8768 | 266 | 266 | 0 | 0 | 2 | 0 | 0 | 0 | | gcdbell_int_latch | tri_rlmlatch_p_8769 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gdbell_int_latch | tri_rlmlatch_p_8770 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gdec_int_latch | tri_rlmlatch_p_8771 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gfit_int_latch | tri_rlmlatch_p_8772 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gmcdbell_int_latch | tri_rlmlatch_p_8773 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gwdog_int_latch | tri_rlmlatch_p_8774 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac1_en_latch | tri_rlmlatch_p_8775 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac2_en_latch | tri_rlmlatch_p_8776 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac3_en_latch | tri_rlmlatch_p_8777 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac4_en_latch | tri_rlmlatch_p_8778 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_lrat_miss_latch | tri_rlmlatch_p_8779 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_pt_fault_latch | tri_rlmlatch_p_8780 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_tlb_inelig_latch | tri_rlmlatch_p_8781 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_async_block_latch | tri_rlmlatch_p_8782 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_bp_pred_latch | tri_rlmlatch_p_8783 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_dispatched_latch | tri_rlmlatch_p_8784 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_error_latch | tri_rlmreg_p__parameterized5_8785 | 113 | 113 | 0 | 0 | 3 | 0 | 0 | 0 | | iu6_i0_fuse_nop_latch | tri_rlmlatch_p_8786 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_ifar_latch | tri_rlmreg_p__parameterized8_8787 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu6_i0_is_attn_latch | tri_rlmlatch_p_8788 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_br_latch | tri_rlmlatch_p_8789 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_dcr_ill_latch | tri_rlmlatch_p_8790 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_ehpriv_latch | tri_rlmlatch_p_8791 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_folded_latch | tri_rlmlatch_p_8792 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_isync_latch | tri_rlmlatch_p_8793 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_np1_flush_latch | tri_rlmlatch_p_8794 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_rfci_latch | tri_rlmlatch_p_8795 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_rfgi_latch | tri_rlmlatch_p_8796 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_rfi_latch | tri_rlmlatch_p_8797 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_rfmci_latch | tri_rlmlatch_p_8798 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_sc_hyp_latch | tri_rlmlatch_p_8799 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_sc_ill_latch | tri_rlmlatch_p_8800 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_is_sc_latch | tri_rlmlatch_p_8801 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_isram_latch | tri_rlmlatch_p_8802 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_itag_latch | tri_rlmreg_p__parameterized0_8803 | 447 | 447 | 0 | 0 | 6 | 0 | 0 | 0 | | iu6_i0_match_latch | tri_rlmlatch_p_8804 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_rollover_latch | tri_rlmlatch_p_8805 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i0_ucode_latch | tri_rlmreg_p__parameterized5_8806 | 34 | 34 | 0 | 0 | 3 | 0 | 0 | 0 | | iu6_i0_valop_latch | tri_rlmlatch_p_8807 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_async_block_latch | tri_rlmlatch_p_8808 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_bp_pred_latch | tri_rlmlatch_p_8809 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_dispatched_latch | tri_rlmlatch_p_8810 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_error_latch | tri_rlmreg_p__parameterized5_8811 | 72 | 72 | 0 | 0 | 3 | 0 | 0 | 0 | | iu6_i1_fuse_nop_latch | tri_rlmlatch_p_8812 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_ifar_latch | tri_rlmreg_p__parameterized8_8813 | 82 | 82 | 0 | 0 | 20 | 0 | 0 | 0 | | iu6_i1_is_attn_latch | tri_rlmlatch_p_8814 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_br_latch | tri_rlmlatch_p_8815 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_dcr_ill_latch | tri_rlmlatch_p_8816 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_ehpriv_latch | tri_rlmlatch_p_8817 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_folded_latch | tri_rlmlatch_p_8818 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_isync_latch | tri_rlmlatch_p_8819 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_np1_flush_latch | tri_rlmlatch_p_8820 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_rfci_latch | tri_rlmlatch_p_8821 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_rfgi_latch | tri_rlmlatch_p_8822 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_rfi_latch | tri_rlmlatch_p_8823 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_rfmci_latch | tri_rlmlatch_p_8824 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_sc_hyp_latch | tri_rlmlatch_p_8825 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_sc_ill_latch | tri_rlmlatch_p_8826 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_is_sc_latch | tri_rlmlatch_p_8827 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_isram_latch | tri_rlmlatch_p_8828 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_itag_latch | tri_rlmreg_p__parameterized66_8829 | 514 | 514 | 0 | 0 | 6 | 0 | 0 | 0 | | iu6_i1_match_latch | tri_rlmlatch_p_8830 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_rollover_latch | tri_rlmlatch_p_8831 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_i1_ucode_latch | tri_rlmreg_p__parameterized5_8832 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | iu6_i1_valop_latch | tri_rlmlatch_p_8833 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu6_uc_hold_rollover_latch | tri_rlmlatch_p_8834 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu7_i0_is_folded_latch | tri_rlmlatch_p_8835 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu7_i1_is_folded_latch | tri_rlmlatch_p_8836 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_lq_recirc_val_latch | tri_rlmlatch_p_8837 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_nonspec_latch | tri_rlmlatch_p_8838 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_step_done_latch | tri_rlmlatch_p_8839 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp3_rfci_latch | tri_rlmlatch_p_8840 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp3_rfgi_latch | tri_rlmlatch_p_8841 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp3_rfi_latch | tri_rlmlatch_p_8842 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp3_rfmci_latch | tri_rlmlatch_p_8843 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp4_rfci_latch | tri_rlmlatch_p_8844 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp4_rfgi_latch | tri_rlmlatch_p_8845 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp4_rfi_latch | tri_rlmlatch_p_8846 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_cp4_rfmci_latch | tri_rlmlatch_p_8847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_dacr_type_latch | tri_rlmlatch_p_8848 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_dacrw_latch | tri_rlmreg_p__parameterized9_8849 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | lq0_eff_addr_latch | tri_rlmreg_p__parameterized33_8850 | 65 | 65 | 0 | 0 | 64 | 0 | 0 | 0 | | lq0_exception_latch | tri_rlmreg_p__parameterized0_8851 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 | | lq0_exception_val_latch | tri_rlmlatch_p_8852 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_execute_vld_latch | tri_rlmlatch_p_8853 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_flush2ucode_latch | tri_rlmlatch_p_8854 | 29 | 29 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_flush2ucode_type_latch | tri_rlmlatch_p_8855 | 26 | 26 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_instr_latch | tri_rlmreg_p__parameterized17_8856 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | lq0_itag_latch | tri_rlmreg_p__parameterized13_8857 | 328 | 328 | 0 | 0 | 7 | 0 | 0 | 0 | | lq0_n_flush_latch | tri_rlmlatch_p_8858 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_np1_flush_latch | tri_rlmlatch_p_8859 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_recirc_val_latch | tri_rlmlatch_p_8860 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_dacr_type_latch | tri_rlmlatch_p_8861 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_dacrw_latch | tri_rlmreg_p__parameterized9_8862 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | lq1_exception_latch | tri_rlmreg_p__parameterized0_8863 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | lq1_exception_val_latch | tri_rlmlatch_p_8864 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_execute_vld_latch | tri_rlmlatch_p_8865 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_itag_latch | tri_rlmreg_p__parameterized13_8866 | 128 | 128 | 0 | 0 | 6 | 0 | 0 | 0 | | lq1_n_flush_latch | tri_rlmlatch_p_8867 | 48 | 48 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_np1_flush_latch | tri_rlmlatch_p_8868 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | lru_par_err_latch | tri_rlmlatch_p_8869 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mmu_mode_latch | tri_rlmlatch_p_8870 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_cm_latch | tri_rlmlatch_p_8871 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_cm_noact_latch | tri_rlmlatch_p_8872 | 19 | 19 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_de_latch | tri_rlmlatch_p_8873 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_gs_latch | tri_rlmlatch_p_8874 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_me_latch | tri_rlmlatch_p_8875 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_pr_latch | tri_rlmlatch_p_8876 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_iu_dbg_action_latch | tri_rlmreg_p__parameterized5_8877 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | pc_iu_init_reset_latch | tri_rlmlatch_p_8878 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_iu_ram_flush_thread_latch | tri_rlmlatch_p_8879 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_iu_step_latch | tri_rlmlatch_p_8880 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_iu_stop_latch | tri_rlmlatch_p__parameterized1_8881 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_stop_hold_latch | tri_rlmlatch_p_8882 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reload_hit_latch | tri_rlmlatch_p_8883 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | select_reset_latch | tri_rlmlatch_p_8884 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_iac1_latch | tri_rlmreg_p__parameterized40_8885 | 134 | 134 | 0 | 0 | 62 | 0 | 0 | 0 | | spr_iac2_latch | tri_rlmreg_p__parameterized40_8886 | 25 | 25 | 0 | 0 | 62 | 0 | 0 | 0 | | spr_iac3_latch | tri_rlmreg_p__parameterized40_8887 | 134 | 134 | 0 | 0 | 62 | 0 | 0 | 0 | | spr_iac4_latch | tri_rlmreg_p__parameterized40_8888 | 24 | 24 | 0 | 0 | 62 | 0 | 0 | 0 | | tlb_miss_latch | tri_rlmlatch_p_8889 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_multihit_err_latch | tri_rlmlatch_p_8890 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_par_err_latch | tri_rlmlatch_p_8891 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | udec_int_latch | tri_rlmlatch_p_8892 | 25 | 25 | 0 | 0 | 1 | 0 | 0 | 0 | | wdog_int_latch | tri_rlmlatch_p_8893 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_async_block_latch | tri_rlmlatch_p_8894 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8895 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8896 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_bp_pred_latch | tri_rlmlatch_p_8897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_br_miss_latch | tri_rlmlatch_p_8898 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_br_pred_latch | tri_rlmlatch_p_8899 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8900 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_is_br_latch | tri_rlmlatch_p_8901 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8902 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8903 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8904 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8905 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_recirc_vld_latch | tri_rlmlatch_p_8906 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8907 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[0].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8908 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_async_block_latch | tri_rlmlatch_p_8909 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8910 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8911 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_bp_pred_latch | tri_rlmlatch_p_8912 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_br_miss_latch | tri_rlmlatch_p_8913 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_br_pred_latch | tri_rlmlatch_p_8914 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8915 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_is_br_latch | tri_rlmlatch_p_8916 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8917 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8918 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8919 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8920 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_recirc_vld_latch | tri_rlmlatch_p_8921 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8922 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[10].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8923 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_async_block_latch | tri_rlmlatch_p_8924 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8925 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8926 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_bp_pred_latch | tri_rlmlatch_p_8927 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_br_miss_latch | tri_rlmlatch_p_8928 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_br_pred_latch | tri_rlmlatch_p_8929 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8930 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_is_br_latch | tri_rlmlatch_p_8931 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8932 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8933 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8934 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8935 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_recirc_vld_latch | tri_rlmlatch_p_8936 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8937 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[11].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8938 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_async_block_latch | tri_rlmlatch_p_8939 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8940 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8941 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_bp_pred_latch | tri_rlmlatch_p_8942 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_br_miss_latch | tri_rlmlatch_p_8943 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_br_pred_latch | tri_rlmlatch_p_8944 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8945 | 37 | 37 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_is_br_latch | tri_rlmlatch_p_8946 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8947 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8948 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8949 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8950 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_recirc_vld_latch | tri_rlmlatch_p_8951 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8952 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[12].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8953 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_async_block_latch | tri_rlmlatch_p_8954 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8955 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8956 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_bp_pred_latch | tri_rlmlatch_p_8957 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_br_miss_latch | tri_rlmlatch_p_8958 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_br_pred_latch | tri_rlmlatch_p_8959 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8960 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_is_br_latch | tri_rlmlatch_p_8961 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8962 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8963 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8964 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8965 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_recirc_vld_latch | tri_rlmlatch_p_8966 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8967 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[13].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8968 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_async_block_latch | tri_rlmlatch_p_8969 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8970 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8971 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_bp_pred_latch | tri_rlmlatch_p_8972 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_br_miss_latch | tri_rlmlatch_p_8973 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_br_pred_latch | tri_rlmlatch_p_8974 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8975 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_is_br_latch | tri_rlmlatch_p_8976 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8977 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8978 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8979 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8980 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_recirc_vld_latch | tri_rlmlatch_p_8981 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8982 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[14].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8983 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_async_block_latch | tri_rlmlatch_p_8984 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_8985 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_axu_excvec_val_latch | tri_rlmlatch_p_8986 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_bp_pred_latch | tri_rlmlatch_p_8987 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_br_miss_latch | tri_rlmlatch_p_8988 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_br_pred_latch | tri_rlmlatch_p_8989 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_db_events_latch | tri_rlmreg_p__parameterized204_8990 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_is_br_latch | tri_rlmlatch_p_8991 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_8992 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_iu_excvec_val_latch | tri_rlmlatch_p_8993 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_8994 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_lq_excvec_val_latch | tri_rlmlatch_p_8995 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_recirc_vld_latch | tri_rlmlatch_p_8996 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_8997 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[15].cp1_xu_excvec_val_latch | tri_rlmlatch_p_8998 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_async_block_latch | tri_rlmlatch_p_8999 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9000 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9001 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_bp_pred_latch | tri_rlmlatch_p_9002 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_br_miss_latch | tri_rlmlatch_p_9003 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_br_pred_latch | tri_rlmlatch_p_9004 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9005 | 35 | 35 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_is_br_latch | tri_rlmlatch_p_9006 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9007 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9008 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9009 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9010 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_recirc_vld_latch | tri_rlmlatch_p_9011 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9012 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[16].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9013 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_async_block_latch | tri_rlmlatch_p_9014 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9015 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9016 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_bp_pred_latch | tri_rlmlatch_p_9017 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_br_miss_latch | tri_rlmlatch_p_9018 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_br_pred_latch | tri_rlmlatch_p_9019 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9020 | 35 | 35 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_is_br_latch | tri_rlmlatch_p_9021 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9022 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9024 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9025 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_recirc_vld_latch | tri_rlmlatch_p_9026 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9027 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[17].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9028 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_async_block_latch | tri_rlmlatch_p_9029 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9030 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9031 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_bp_pred_latch | tri_rlmlatch_p_9032 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_br_miss_latch | tri_rlmlatch_p_9033 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_br_pred_latch | tri_rlmlatch_p_9034 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9035 | 35 | 35 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_is_br_latch | tri_rlmlatch_p_9036 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9037 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9038 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9039 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9040 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_recirc_vld_latch | tri_rlmlatch_p_9041 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9042 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[18].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9043 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_async_block_latch | tri_rlmlatch_p_9044 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9045 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9046 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_bp_pred_latch | tri_rlmlatch_p_9047 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_br_miss_latch | tri_rlmlatch_p_9048 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_br_pred_latch | tri_rlmlatch_p_9049 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9050 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_is_br_latch | tri_rlmlatch_p_9051 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9052 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9053 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9054 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9055 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_recirc_vld_latch | tri_rlmlatch_p_9056 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9057 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[19].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9058 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_async_block_latch | tri_rlmlatch_p_9059 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9060 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9061 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_bp_pred_latch | tri_rlmlatch_p_9062 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_br_miss_latch | tri_rlmlatch_p_9063 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_br_pred_latch | tri_rlmlatch_p_9064 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9065 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_is_br_latch | tri_rlmlatch_p_9066 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9067 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9068 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9069 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9070 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_recirc_vld_latch | tri_rlmlatch_p_9071 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9072 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[1].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9073 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_async_block_latch | tri_rlmlatch_p_9074 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9075 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9076 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_bp_pred_latch | tri_rlmlatch_p_9077 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_br_miss_latch | tri_rlmlatch_p_9078 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_br_pred_latch | tri_rlmlatch_p_9079 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9080 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_is_br_latch | tri_rlmlatch_p_9081 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9082 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9083 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9084 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9085 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_recirc_vld_latch | tri_rlmlatch_p_9086 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9087 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[20].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9088 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_async_block_latch | tri_rlmlatch_p_9089 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9090 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9091 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_bp_pred_latch | tri_rlmlatch_p_9092 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_br_miss_latch | tri_rlmlatch_p_9093 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_br_pred_latch | tri_rlmlatch_p_9094 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9095 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_is_br_latch | tri_rlmlatch_p_9096 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9097 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9098 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9099 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9100 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_recirc_vld_latch | tri_rlmlatch_p_9101 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9102 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[21].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9103 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_async_block_latch | tri_rlmlatch_p_9104 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9105 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9106 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_bp_pred_latch | tri_rlmlatch_p_9107 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_br_miss_latch | tri_rlmlatch_p_9108 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_br_pred_latch | tri_rlmlatch_p_9109 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9110 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_is_br_latch | tri_rlmlatch_p_9111 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9112 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9114 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9115 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_recirc_vld_latch | tri_rlmlatch_p_9116 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9117 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[22].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9118 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_async_block_latch | tri_rlmlatch_p_9119 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9120 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9121 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_bp_pred_latch | tri_rlmlatch_p_9122 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_br_miss_latch | tri_rlmlatch_p_9123 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_br_pred_latch | tri_rlmlatch_p_9124 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9125 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_is_br_latch | tri_rlmlatch_p_9126 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9127 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9128 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9129 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9130 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_recirc_vld_latch | tri_rlmlatch_p_9131 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9132 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[23].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9133 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_async_block_latch | tri_rlmlatch_p_9134 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9135 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9136 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_bp_pred_latch | tri_rlmlatch_p_9137 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_br_miss_latch | tri_rlmlatch_p_9138 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_br_pred_latch | tri_rlmlatch_p_9139 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9140 | 30 | 30 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_is_br_latch | tri_rlmlatch_p_9141 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9142 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9143 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9144 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9145 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_recirc_vld_latch | tri_rlmlatch_p_9146 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9147 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[24].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9148 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_async_block_latch | tri_rlmlatch_p_9149 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9150 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9151 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_bp_pred_latch | tri_rlmlatch_p_9152 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_br_miss_latch | tri_rlmlatch_p_9153 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_br_pred_latch | tri_rlmlatch_p_9154 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9155 | 37 | 37 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_is_br_latch | tri_rlmlatch_p_9156 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9157 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9158 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9159 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9160 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_recirc_vld_latch | tri_rlmlatch_p_9161 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9162 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[25].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9163 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_async_block_latch | tri_rlmlatch_p_9164 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9165 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9166 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_bp_pred_latch | tri_rlmlatch_p_9167 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_br_miss_latch | tri_rlmlatch_p_9168 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_br_pred_latch | tri_rlmlatch_p_9169 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9170 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_is_br_latch | tri_rlmlatch_p_9171 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9172 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9173 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9174 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9175 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_recirc_vld_latch | tri_rlmlatch_p_9176 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9177 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[26].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_async_block_latch | tri_rlmlatch_p_9179 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9180 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9181 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_bp_pred_latch | tri_rlmlatch_p_9182 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_br_miss_latch | tri_rlmlatch_p_9183 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_br_pred_latch | tri_rlmlatch_p_9184 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9185 | 32 | 32 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_is_br_latch | tri_rlmlatch_p_9186 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9187 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9188 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9189 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9190 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_recirc_vld_latch | tri_rlmlatch_p_9191 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9192 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[27].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9193 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_async_block_latch | tri_rlmlatch_p_9194 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9195 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9196 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_bp_pred_latch | tri_rlmlatch_p_9197 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_br_miss_latch | tri_rlmlatch_p_9198 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_br_pred_latch | tri_rlmlatch_p_9199 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9200 | 35 | 35 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_is_br_latch | tri_rlmlatch_p_9201 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9202 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9203 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9204 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9205 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_recirc_vld_latch | tri_rlmlatch_p_9206 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9207 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[28].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9208 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_async_block_latch | tri_rlmlatch_p_9209 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9210 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9211 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_bp_pred_latch | tri_rlmlatch_p_9212 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_br_miss_latch | tri_rlmlatch_p_9213 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_br_pred_latch | tri_rlmlatch_p_9214 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9215 | 39 | 39 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_is_br_latch | tri_rlmlatch_p_9216 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9217 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9218 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9219 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9220 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_recirc_vld_latch | tri_rlmlatch_p_9221 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9222 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[29].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9223 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_async_block_latch | tri_rlmlatch_p_9224 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9225 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9226 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_bp_pred_latch | tri_rlmlatch_p_9227 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_br_miss_latch | tri_rlmlatch_p_9228 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_br_pred_latch | tri_rlmlatch_p_9229 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9230 | 31 | 31 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_is_br_latch | tri_rlmlatch_p_9231 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9232 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9233 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9234 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9235 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_recirc_vld_latch | tri_rlmlatch_p_9236 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9237 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[2].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9238 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_async_block_latch | tri_rlmlatch_p_9239 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9240 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9241 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_bp_pred_latch | tri_rlmlatch_p_9242 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_br_miss_latch | tri_rlmlatch_p_9243 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_br_pred_latch | tri_rlmlatch_p_9244 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9245 | 33 | 33 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_is_br_latch | tri_rlmlatch_p_9246 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9247 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9248 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9249 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9250 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_recirc_vld_latch | tri_rlmlatch_p_9251 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9252 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[30].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9253 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_async_block_latch | tri_rlmlatch_p_9254 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9255 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9256 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_bp_pred_latch | tri_rlmlatch_p_9257 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_br_miss_latch | tri_rlmlatch_p_9258 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_br_pred_latch | tri_rlmlatch_p_9259 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9260 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_is_br_latch | tri_rlmlatch_p_9261 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9262 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9263 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9264 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9265 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_recirc_vld_latch | tri_rlmlatch_p_9266 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9267 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[31].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9268 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_async_block_latch | tri_rlmlatch_p_9269 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9270 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_bp_pred_latch | tri_rlmlatch_p_9272 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_br_miss_latch | tri_rlmlatch_p_9273 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_br_pred_latch | tri_rlmlatch_p_9274 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9275 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_is_br_latch | tri_rlmlatch_p_9276 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9277 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9278 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9279 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9280 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_recirc_vld_latch | tri_rlmlatch_p_9281 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9282 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[3].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9283 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_async_block_latch | tri_rlmlatch_p_9284 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9285 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9286 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_bp_pred_latch | tri_rlmlatch_p_9287 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_br_miss_latch | tri_rlmlatch_p_9288 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_br_pred_latch | tri_rlmlatch_p_9289 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9290 | 37 | 37 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_is_br_latch | tri_rlmlatch_p_9291 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9292 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9294 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9295 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_recirc_vld_latch | tri_rlmlatch_p_9296 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9297 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[4].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9298 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_async_block_latch | tri_rlmlatch_p_9299 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9300 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9301 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_bp_pred_latch | tri_rlmlatch_p_9302 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_br_miss_latch | tri_rlmlatch_p_9303 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_br_pred_latch | tri_rlmlatch_p_9304 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9305 | 37 | 37 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_is_br_latch | tri_rlmlatch_p_9306 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9307 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9308 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9309 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9310 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_recirc_vld_latch | tri_rlmlatch_p_9311 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9312 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[5].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9313 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_async_block_latch | tri_rlmlatch_p_9314 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9315 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9316 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_bp_pred_latch | tri_rlmlatch_p_9317 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_br_miss_latch | tri_rlmlatch_p_9318 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_br_pred_latch | tri_rlmlatch_p_9319 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9320 | 38 | 38 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_is_br_latch | tri_rlmlatch_p_9321 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9322 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9323 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9324 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9325 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_recirc_vld_latch | tri_rlmlatch_p_9326 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9327 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[6].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9328 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_async_block_latch | tri_rlmlatch_p_9329 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9330 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9331 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_bp_pred_latch | tri_rlmlatch_p_9332 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_br_miss_latch | tri_rlmlatch_p_9333 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_br_pred_latch | tri_rlmlatch_p_9334 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9335 | 34 | 34 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_is_br_latch | tri_rlmlatch_p_9336 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9337 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9338 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9339 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9340 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_recirc_vld_latch | tri_rlmlatch_p_9341 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9342 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[7].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9343 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_async_block_latch | tri_rlmlatch_p_9344 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9345 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9346 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_bp_pred_latch | tri_rlmlatch_p_9347 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_br_miss_latch | tri_rlmlatch_p_9348 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_br_pred_latch | tri_rlmlatch_p_9349 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9350 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_is_br_latch | tri_rlmlatch_p_9351 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9352 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9353 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9354 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9355 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_recirc_vld_latch | tri_rlmlatch_p_9356 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9357 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[8].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9358 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_async_block_latch | tri_rlmlatch_p_9359 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_axu_excvec_latch | tri_rlmreg_p__parameterized9_9360 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_axu_excvec_val_latch | tri_rlmlatch_p_9361 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_bp_pred_latch | tri_rlmlatch_p_9362 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_br_miss_latch | tri_rlmlatch_p_9363 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_br_pred_latch | tri_rlmlatch_p_9364 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_db_events_latch | tri_rlmreg_p__parameterized204_9365 | 38 | 38 | 0 | 0 | 18 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_is_br_latch | tri_rlmlatch_p_9366 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_iu_excvec_latch | tri_rlmreg_p__parameterized9_9367 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_iu_excvec_val_latch | tri_rlmlatch_p_9368 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_lq_excvec_latch | tri_rlmreg_p__parameterized0_9369 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_lq_excvec_val_latch | tri_rlmlatch_p_9370 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_recirc_vld_latch | tri_rlmlatch_p_9371 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_xu_excvec_latch | tri_rlmreg_p__parameterized4_9372 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.q_depth_gen[9].cp1_xu_excvec_val_latch | tri_rlmlatch_p_9373 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[0].cp3_nia_a_latch | tri_rlmlatch_p_9374 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[10].cp3_nia_a_latch | tri_rlmlatch_p_9375 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[11].cp3_nia_a_latch | tri_rlmlatch_p_9376 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[12].cp3_nia_a_latch | tri_rlmlatch_p_9377 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[13].cp3_nia_a_latch | tri_rlmlatch_p_9378 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[14].cp3_nia_a_latch | tri_rlmlatch_p_9379 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[15].cp3_nia_a_latch | tri_rlmlatch_p_9380 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[16].cp3_nia_a_latch | tri_rlmlatch_p_9381 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[17].cp3_nia_a_latch | tri_rlmlatch_p_9382 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[18].cp3_nia_a_latch | tri_rlmlatch_p_9383 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[19].cp3_nia_a_latch | tri_rlmlatch_p_9384 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[1].cp3_nia_a_latch | tri_rlmlatch_p_9385 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[20].cp3_nia_a_latch | tri_rlmlatch_p_9386 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[21].cp3_nia_a_latch | tri_rlmlatch_p_9387 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[22].cp3_nia_a_latch | tri_rlmlatch_p_9388 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[23].cp3_nia_a_latch | tri_rlmlatch_p_9389 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[24].cp3_nia_a_latch | tri_rlmlatch_p_9390 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[25].cp3_nia_a_latch | tri_rlmlatch_p_9391 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[26].cp3_nia_a_latch | tri_rlmlatch_p_9392 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[27].cp3_nia_a_latch | tri_rlmlatch_p_9393 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[28].cp3_nia_a_latch | tri_rlmlatch_p_9394 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[29].cp3_nia_a_latch | tri_rlmlatch_p_9395 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[2].cp3_nia_a_latch | tri_rlmlatch_p_9396 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[30].cp3_nia_a_latch | tri_rlmlatch_p_9397 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[31].cp3_nia_a_latch | tri_rlmlatch_p_9398 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[32].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[33].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9399 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[34].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9400 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[35].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9401 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[36].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9402 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[37].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9403 | 62 | 62 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[38].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9404 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[39].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9405 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[3].cp3_nia_a_latch | tri_rlmlatch_p_9406 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[40].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9407 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[41].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9408 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[42].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9409 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[43].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9410 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[44].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9411 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[45].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9412 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[46].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9413 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[47].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9414 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[48].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9415 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[49].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9416 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[4].cp3_nia_a_latch | tri_rlmlatch_p_9417 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[50].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9418 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[51].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9419 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[52].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9420 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[53].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9421 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[54].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9422 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[55].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9423 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[56].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9424 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[57].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9425 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[58].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9426 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[59].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9427 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[5].cp3_nia_a_latch | tri_rlmlatch_p_9428 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[60].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9429 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[61].cp3_nia_a_latch | tri_rlmlatch_p__parameterized2_9430 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[6].cp3_nia_a_latch | tri_rlmlatch_p_9431 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[7].cp3_nia_a_latch | tri_rlmlatch_p_9432 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[8].cp3_nia_a_latch | tri_rlmlatch_p_9433 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl6.q_depth_gen[9].cp3_nia_a_latch | tri_rlmlatch_p_9434 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu1_execute_vld_latch | tri_rlmlatch_p_9435 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu1_itag_latch | tri_rlmreg_p__parameterized13_9436 | 84 | 84 | 0 | 0 | 6 | 0 | 0 | 0 | | xu_bta_latch | tri_rlmreg_p__parameterized40_9437 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | xu_exception_latch | tri_rlmreg_p__parameterized4_9438 | 123 | 123 | 0 | 0 | 5 | 0 | 0 | 0 | | xu_exception_val_latch | tri_rlmlatch_p_9439 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_execute_vld_latch | tri_rlmlatch_p_9440 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_flush2ucode_latch | tri_rlmlatch_p_9441 | 24 | 24 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_itag_latch | tri_rlmreg_p__parameterized13_9442 | 131 | 131 | 0 | 0 | 7 | 0 | 0 | 0 | | xu_iu_msrovride_enab_latch | tri_rlmlatch_p_9443 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_np1_async_flush_latch | tri_rlmlatch_p_9444 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_rest_ifar_latch | tri_rlmreg_p__parameterized40_9445 | 7 | 7 | 0 | 0 | 62 | 0 | 0 | 0 | | xu_iu_single_instr_latch | tri_rlmlatch_p_9446 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_xucr4_mmu_mchk_latch | tri_rlmlatch_p_9447 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_mtiar_latch | tri_rlmlatch_p_9448 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_n_flush_latch | tri_rlmlatch_p_9449 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_np1_flush_latch | tri_rlmlatch_p_9450 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_1to0_reg | tri_plat | 510 | 510 | 0 | 0 | 1 | 0 | 0 | 0 | | xer_cp_p_latch | tri_rlmreg_p__parameterized9_8592 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iuq_ifetch0 | iuq_ifetch | 19706 | 19706 | 0 | 0 | 8798 | 21 | 6 | 0 | | iuq_ic0 | iuq_ic | 13173 | 13173 | 0 | 0 | 5573 | 21 | 6 | 0 | | iuq_ic_dir0 | iuq_ic_dir | 5329 | 5329 | 0 | 0 | 1973 | 20 | 4 | 0 | | (iuq_ic_dir0) | iuq_ic_dir | 7 | 7 | 0 | 0 | 0 | 0 | 0 | 0 | | gen_iu1_read_erat1.iu1_read_erat_latch | tri_rlmlatch_p_8296 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | gen_iu2_read_erat1.iu2_cam_change_etc_latch | tri_rlmlatch_p_8297 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | gen_iu2_read_erat1.iu2_read_erat_latch | tri_rlmlatch_p_8298 | 131 | 131 | 0 | 0 | 1 | 0 | 0 | 0 | | ici_val_latch | tri_rlmlatch_p_8299 | 508 | 508 | 0 | 0 | 8 | 0 | 0 | 0 | | idata | tri_512x162_4w_0 | 1430 | 1430 | 0 | 0 | 654 | 20 | 0 | 0 | | (idata) | tri_512x162_4w_0 | 0 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | | genblk1.data_out_latch | tri_rlmreg_p__parameterized54 | 782 | 782 | 0 | 0 | 648 | 0 | 0 | 0 | | genblk1.rd_act_latch | tri_rlmlatch_p__parameterized0_8591 | 648 | 648 | 0 | 0 | 6 | 0 | 0 | 0 | | idir | tri_128x34_4w_1r1w | 246 | 246 | 0 | 0 | 137 | 0 | 4 | 0 | | (idir) | tri_128x34_4w_1r1w | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | | data_out_latch | tri_rlmreg_p__parameterized24_8589 | 110 | 110 | 0 | 0 | 136 | 0 | 0 | 0 | | rd_act_latch | tri_rlmlatch_p__parameterized0_8590 | 136 | 136 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_2ucode_latch | tri_rlmlatch_p_8300 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_2ucode_type_latch | tri_rlmlatch_p_8301 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_ifar_latch | tri_rlmreg_p__parameterized55 | 320 | 320 | 0 | 0 | 63 | 0 | 0 | 0 | | iu1_index51_latch | tri_rlmlatch_p_8302 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_inval_latch | tri_rlmlatch_p_8303 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_prefetch_latch | tri_rlmlatch_p_8304 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_spr_idir_read_latch | tri_rlmlatch_p_8305 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_valid_latch | tri_rlmlatch_p_8306 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_2ucode_latch | tri_rlmlatch_p_8307 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_2ucode_type_latch | tri_rlmlatch_p_8308 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_dir_rd_val_latch | tri_rlmreg_p__parameterized9_8309 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | iu2_ifar_eff_latch | tri_rlmreg_p__parameterized56 | 46 | 46 | 0 | 0 | 52 | 0 | 0 | 0 | | iu2_ifar_eff_slp_latch | tri_rlmreg_p__parameterized23_8310 | 1154 | 1154 | 0 | 0 | 22 | 0 | 0 | 0 | | iu2_index51_latch | tri_rlmlatch_p_8311 | 169 | 169 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_inval_latch | tri_rlmlatch_p_8312 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_prefetch_latch | tri_rlmlatch_p_8313 | 37 | 37 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_spr_idir_lru_latch | tri_rlmreg_p__parameterized5_8314 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | iu2_spr_idir_read_latch | tri_rlmlatch_p_8315 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_stored_rpn_latch | tri_rlmreg_p__parameterized57 | 170 | 170 | 0 | 0 | 30 | 0 | 0 | 0 | | iu2_valid_latch | tri_rlmlatch_p_8316 | 60 | 60 | 0 | 0 | 4 | 0 | 0 | 0 | | iu3_2ucode_latch | tri_rlmlatch_p_8317 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_2ucode_type_latch | tri_rlmlatch_p_8318 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_data_parity_err_way_latch | tri_rlmreg_p__parameterized9_8319 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | iu3_dir_parity_err_way_latch | tri_rlmreg_p__parameterized9_8320 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | iu3_erat_err_latch | tri_rlmreg_p__parameterized37_8321 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_ifar_latch | tri_rlmreg_p__parameterized15_8322 | 14 | 14 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_miss_flush | tri_rlmlatch_p_8323 | 39 | 39 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_multihit_err_way_latch | tri_rlmreg_p__parameterized9_8324 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | iu3_multihit_flush_latch | tri_rlmlatch_p_8325 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_parity_needs_flush_latch | tri_rlmlatch_p_8326 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_parity_tag_latch | tri_rlmreg_p__parameterized18_8327 | 133 | 133 | 0 | 0 | 7 | 0 | 0 | 0 | | pc_iu_inj_latch | tri_rlmreg_p__parameterized5_8328 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_ic_cls_latch | tri_rlmlatch_p_8329 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ic_idir_way_latch | tri_rlmreg_p__parameterized2_8330 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[0].dir_lru_latch | tri_rlmreg_p__parameterized5_8331 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[0].dir_val_latch | tri_rlmreg_p__parameterized9_8332 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[100].dir_lru_latch | tri_rlmreg_p__parameterized5_8333 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[100].dir_val_latch | tri_rlmreg_p__parameterized9_8334 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[101].dir_lru_latch | tri_rlmreg_p__parameterized5_8335 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[101].dir_val_latch | tri_rlmreg_p__parameterized9_8336 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[102].dir_lru_latch | tri_rlmreg_p__parameterized5_8337 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[102].dir_val_latch | tri_rlmreg_p__parameterized9_8338 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[103].dir_lru_latch | tri_rlmreg_p__parameterized5_8339 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[103].dir_val_latch | tri_rlmreg_p__parameterized9_8340 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[104].dir_lru_latch | tri_rlmreg_p__parameterized5_8341 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[104].dir_val_latch | tri_rlmreg_p__parameterized9_8342 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[105].dir_lru_latch | tri_rlmreg_p__parameterized5_8343 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[105].dir_val_latch | tri_rlmreg_p__parameterized9_8344 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[106].dir_lru_latch | tri_rlmreg_p__parameterized5_8345 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[106].dir_val_latch | tri_rlmreg_p__parameterized9_8346 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[107].dir_lru_latch | tri_rlmreg_p__parameterized5_8347 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[107].dir_val_latch | tri_rlmreg_p__parameterized9_8348 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[108].dir_lru_latch | tri_rlmreg_p__parameterized5_8349 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[108].dir_val_latch | tri_rlmreg_p__parameterized9_8350 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[109].dir_lru_latch | tri_rlmreg_p__parameterized5_8351 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[109].dir_val_latch | tri_rlmreg_p__parameterized9_8352 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[10].dir_lru_latch | tri_rlmreg_p__parameterized5_8353 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[10].dir_val_latch | tri_rlmreg_p__parameterized9_8354 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[110].dir_lru_latch | tri_rlmreg_p__parameterized5_8355 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[110].dir_val_latch | tri_rlmreg_p__parameterized9_8356 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[111].dir_lru_latch | tri_rlmreg_p__parameterized5_8357 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[111].dir_val_latch | tri_rlmreg_p__parameterized9_8358 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[112].dir_lru_latch | tri_rlmreg_p__parameterized5_8359 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[112].dir_val_latch | tri_rlmreg_p__parameterized9_8360 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[113].dir_lru_latch | tri_rlmreg_p__parameterized5_8361 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[113].dir_val_latch | tri_rlmreg_p__parameterized9_8362 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[114].dir_lru_latch | tri_rlmreg_p__parameterized5_8363 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[114].dir_val_latch | tri_rlmreg_p__parameterized9_8364 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[115].dir_lru_latch | tri_rlmreg_p__parameterized5_8365 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[115].dir_val_latch | tri_rlmreg_p__parameterized9_8366 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[116].dir_lru_latch | tri_rlmreg_p__parameterized5_8367 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[116].dir_val_latch | tri_rlmreg_p__parameterized9_8368 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[117].dir_lru_latch | tri_rlmreg_p__parameterized5_8369 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[117].dir_val_latch | tri_rlmreg_p__parameterized9_8370 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[118].dir_lru_latch | tri_rlmreg_p__parameterized5_8371 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[118].dir_val_latch | tri_rlmreg_p__parameterized9_8372 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[119].dir_lru_latch | tri_rlmreg_p__parameterized5_8373 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[119].dir_val_latch | tri_rlmreg_p__parameterized9_8374 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[11].dir_lru_latch | tri_rlmreg_p__parameterized5_8375 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[11].dir_val_latch | tri_rlmreg_p__parameterized9_8376 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[120].dir_lru_latch | tri_rlmreg_p__parameterized5_8377 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[120].dir_val_latch | tri_rlmreg_p__parameterized9_8378 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[121].dir_lru_latch | tri_rlmreg_p__parameterized5_8379 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[121].dir_val_latch | tri_rlmreg_p__parameterized9_8380 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[122].dir_lru_latch | tri_rlmreg_p__parameterized5_8381 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[122].dir_val_latch | tri_rlmreg_p__parameterized9_8382 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[123].dir_lru_latch | tri_rlmreg_p__parameterized5_8383 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[123].dir_val_latch | tri_rlmreg_p__parameterized9_8384 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[124].dir_lru_latch | tri_rlmreg_p__parameterized5_8385 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[124].dir_val_latch | tri_rlmreg_p__parameterized9_8386 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[125].dir_lru_latch | tri_rlmreg_p__parameterized5_8387 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[125].dir_val_latch | tri_rlmreg_p__parameterized9_8388 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[126].dir_lru_latch | tri_rlmreg_p__parameterized5_8389 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[126].dir_val_latch | tri_rlmreg_p__parameterized9_8390 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[127].dir_lru_latch | tri_rlmreg_p__parameterized5_8391 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[127].dir_val_latch | tri_rlmreg_p__parameterized9_8392 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[12].dir_lru_latch | tri_rlmreg_p__parameterized5_8393 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[12].dir_val_latch | tri_rlmreg_p__parameterized9_8394 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[13].dir_lru_latch | tri_rlmreg_p__parameterized5_8395 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[13].dir_val_latch | tri_rlmreg_p__parameterized9_8396 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[14].dir_lru_latch | tri_rlmreg_p__parameterized5_8397 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[14].dir_val_latch | tri_rlmreg_p__parameterized9_8398 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[15].dir_lru_latch | tri_rlmreg_p__parameterized5_8399 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[15].dir_val_latch | tri_rlmreg_p__parameterized9_8400 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[16].dir_lru_latch | tri_rlmreg_p__parameterized5_8401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[16].dir_val_latch | tri_rlmreg_p__parameterized9_8402 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[17].dir_lru_latch | tri_rlmreg_p__parameterized5_8403 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[17].dir_val_latch | tri_rlmreg_p__parameterized9_8404 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[18].dir_lru_latch | tri_rlmreg_p__parameterized5_8405 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[18].dir_val_latch | tri_rlmreg_p__parameterized9_8406 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[19].dir_lru_latch | tri_rlmreg_p__parameterized5_8407 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[19].dir_val_latch | tri_rlmreg_p__parameterized9_8408 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[1].dir_lru_latch | tri_rlmreg_p__parameterized5_8409 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[1].dir_val_latch | tri_rlmreg_p__parameterized9_8410 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[20].dir_lru_latch | tri_rlmreg_p__parameterized5_8411 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[20].dir_val_latch | tri_rlmreg_p__parameterized9_8412 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[21].dir_lru_latch | tri_rlmreg_p__parameterized5_8413 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[21].dir_val_latch | tri_rlmreg_p__parameterized9_8414 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[22].dir_lru_latch | tri_rlmreg_p__parameterized5_8415 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[22].dir_val_latch | tri_rlmreg_p__parameterized9_8416 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[23].dir_lru_latch | tri_rlmreg_p__parameterized5_8417 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[23].dir_val_latch | tri_rlmreg_p__parameterized9_8418 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[24].dir_lru_latch | tri_rlmreg_p__parameterized5_8419 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[24].dir_val_latch | tri_rlmreg_p__parameterized9_8420 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[25].dir_lru_latch | tri_rlmreg_p__parameterized5_8421 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[25].dir_val_latch | tri_rlmreg_p__parameterized9_8422 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[26].dir_lru_latch | tri_rlmreg_p__parameterized5_8423 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[26].dir_val_latch | tri_rlmreg_p__parameterized9_8424 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[27].dir_lru_latch | tri_rlmreg_p__parameterized5_8425 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[27].dir_val_latch | tri_rlmreg_p__parameterized9_8426 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[28].dir_lru_latch | tri_rlmreg_p__parameterized5_8427 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[28].dir_val_latch | tri_rlmreg_p__parameterized9_8428 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[29].dir_lru_latch | tri_rlmreg_p__parameterized5_8429 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[29].dir_val_latch | tri_rlmreg_p__parameterized9_8430 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[2].dir_lru_latch | tri_rlmreg_p__parameterized5_8431 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[2].dir_val_latch | tri_rlmreg_p__parameterized9_8432 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[30].dir_lru_latch | tri_rlmreg_p__parameterized5_8433 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[30].dir_val_latch | tri_rlmreg_p__parameterized9_8434 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[31].dir_lru_latch | tri_rlmreg_p__parameterized5_8435 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[31].dir_val_latch | tri_rlmreg_p__parameterized9_8436 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[32].dir_lru_latch | tri_rlmreg_p__parameterized5_8437 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[32].dir_val_latch | tri_rlmreg_p__parameterized9_8438 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[33].dir_lru_latch | tri_rlmreg_p__parameterized5_8439 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[33].dir_val_latch | tri_rlmreg_p__parameterized9_8440 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[34].dir_lru_latch | tri_rlmreg_p__parameterized5_8441 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[34].dir_val_latch | tri_rlmreg_p__parameterized9_8442 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[35].dir_lru_latch | tri_rlmreg_p__parameterized5_8443 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[35].dir_val_latch | tri_rlmreg_p__parameterized9_8444 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[36].dir_lru_latch | tri_rlmreg_p__parameterized5_8445 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[36].dir_val_latch | tri_rlmreg_p__parameterized9_8446 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[37].dir_lru_latch | tri_rlmreg_p__parameterized5_8447 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[37].dir_val_latch | tri_rlmreg_p__parameterized9_8448 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[38].dir_lru_latch | tri_rlmreg_p__parameterized5_8449 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[38].dir_val_latch | tri_rlmreg_p__parameterized9_8450 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[39].dir_lru_latch | tri_rlmreg_p__parameterized5_8451 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[39].dir_val_latch | tri_rlmreg_p__parameterized9_8452 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[3].dir_lru_latch | tri_rlmreg_p__parameterized5_8453 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[3].dir_val_latch | tri_rlmreg_p__parameterized9_8454 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[40].dir_lru_latch | tri_rlmreg_p__parameterized5_8455 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[40].dir_val_latch | tri_rlmreg_p__parameterized9_8456 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[41].dir_lru_latch | tri_rlmreg_p__parameterized5_8457 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[41].dir_val_latch | tri_rlmreg_p__parameterized9_8458 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[42].dir_lru_latch | tri_rlmreg_p__parameterized5_8459 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[42].dir_val_latch | tri_rlmreg_p__parameterized9_8460 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[43].dir_lru_latch | tri_rlmreg_p__parameterized5_8461 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[43].dir_val_latch | tri_rlmreg_p__parameterized9_8462 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[44].dir_lru_latch | tri_rlmreg_p__parameterized5_8463 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[44].dir_val_latch | tri_rlmreg_p__parameterized9_8464 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[45].dir_lru_latch | tri_rlmreg_p__parameterized5_8465 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[45].dir_val_latch | tri_rlmreg_p__parameterized9_8466 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[46].dir_lru_latch | tri_rlmreg_p__parameterized5_8467 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[46].dir_val_latch | tri_rlmreg_p__parameterized9_8468 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[47].dir_lru_latch | tri_rlmreg_p__parameterized5_8469 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[47].dir_val_latch | tri_rlmreg_p__parameterized9_8470 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[48].dir_lru_latch | tri_rlmreg_p__parameterized5_8471 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[48].dir_val_latch | tri_rlmreg_p__parameterized9_8472 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[49].dir_lru_latch | tri_rlmreg_p__parameterized5_8473 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[49].dir_val_latch | tri_rlmreg_p__parameterized9_8474 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[4].dir_lru_latch | tri_rlmreg_p__parameterized5_8475 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[4].dir_val_latch | tri_rlmreg_p__parameterized9_8476 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[50].dir_lru_latch | tri_rlmreg_p__parameterized5_8477 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[50].dir_val_latch | tri_rlmreg_p__parameterized9_8478 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[51].dir_lru_latch | tri_rlmreg_p__parameterized5_8479 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[51].dir_val_latch | tri_rlmreg_p__parameterized9_8480 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[52].dir_lru_latch | tri_rlmreg_p__parameterized5_8481 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[52].dir_val_latch | tri_rlmreg_p__parameterized9_8482 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[53].dir_lru_latch | tri_rlmreg_p__parameterized5_8483 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[53].dir_val_latch | tri_rlmreg_p__parameterized9_8484 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[54].dir_lru_latch | tri_rlmreg_p__parameterized5_8485 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[54].dir_val_latch | tri_rlmreg_p__parameterized9_8486 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[55].dir_lru_latch | tri_rlmreg_p__parameterized5_8487 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[55].dir_val_latch | tri_rlmreg_p__parameterized9_8488 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[56].dir_lru_latch | tri_rlmreg_p__parameterized5_8489 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[56].dir_val_latch | tri_rlmreg_p__parameterized9_8490 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[57].dir_lru_latch | tri_rlmreg_p__parameterized5_8491 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[57].dir_val_latch | tri_rlmreg_p__parameterized9_8492 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[58].dir_lru_latch | tri_rlmreg_p__parameterized5_8493 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[58].dir_val_latch | tri_rlmreg_p__parameterized9_8494 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[59].dir_lru_latch | tri_rlmreg_p__parameterized5_8495 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[59].dir_val_latch | tri_rlmreg_p__parameterized9_8496 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[5].dir_lru_latch | tri_rlmreg_p__parameterized5_8497 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[5].dir_val_latch | tri_rlmreg_p__parameterized9_8498 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[60].dir_lru_latch | tri_rlmreg_p__parameterized5_8499 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[60].dir_val_latch | tri_rlmreg_p__parameterized9_8500 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[61].dir_lru_latch | tri_rlmreg_p__parameterized5_8501 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[61].dir_val_latch | tri_rlmreg_p__parameterized9_8502 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[62].dir_lru_latch | tri_rlmreg_p__parameterized5_8503 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[62].dir_val_latch | tri_rlmreg_p__parameterized9_8504 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[63].dir_lru_latch | tri_rlmreg_p__parameterized5_8505 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[63].dir_val_latch | tri_rlmreg_p__parameterized9_8506 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[64].dir_lru_latch | tri_rlmreg_p__parameterized5_8507 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[64].dir_val_latch | tri_rlmreg_p__parameterized9_8508 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[65].dir_lru_latch | tri_rlmreg_p__parameterized5_8509 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[65].dir_val_latch | tri_rlmreg_p__parameterized9_8510 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[66].dir_lru_latch | tri_rlmreg_p__parameterized5_8511 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[66].dir_val_latch | tri_rlmreg_p__parameterized9_8512 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[67].dir_lru_latch | tri_rlmreg_p__parameterized5_8513 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[67].dir_val_latch | tri_rlmreg_p__parameterized9_8514 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[68].dir_lru_latch | tri_rlmreg_p__parameterized5_8515 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[68].dir_val_latch | tri_rlmreg_p__parameterized9_8516 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[69].dir_lru_latch | tri_rlmreg_p__parameterized5_8517 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[69].dir_val_latch | tri_rlmreg_p__parameterized9_8518 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[6].dir_lru_latch | tri_rlmreg_p__parameterized5_8519 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[6].dir_val_latch | tri_rlmreg_p__parameterized9_8520 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[70].dir_lru_latch | tri_rlmreg_p__parameterized5_8521 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[70].dir_val_latch | tri_rlmreg_p__parameterized9_8522 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[71].dir_lru_latch | tri_rlmreg_p__parameterized5_8523 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[71].dir_val_latch | tri_rlmreg_p__parameterized9_8524 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[72].dir_lru_latch | tri_rlmreg_p__parameterized5_8525 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[72].dir_val_latch | tri_rlmreg_p__parameterized9_8526 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[73].dir_lru_latch | tri_rlmreg_p__parameterized5_8527 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[73].dir_val_latch | tri_rlmreg_p__parameterized9_8528 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[74].dir_lru_latch | tri_rlmreg_p__parameterized5_8529 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[74].dir_val_latch | tri_rlmreg_p__parameterized9_8530 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[75].dir_lru_latch | tri_rlmreg_p__parameterized5_8531 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[75].dir_val_latch | tri_rlmreg_p__parameterized9_8532 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[76].dir_lru_latch | tri_rlmreg_p__parameterized5_8533 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[76].dir_val_latch | tri_rlmreg_p__parameterized9_8534 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[77].dir_lru_latch | tri_rlmreg_p__parameterized5_8535 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[77].dir_val_latch | tri_rlmreg_p__parameterized9_8536 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[78].dir_lru_latch | tri_rlmreg_p__parameterized5_8537 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[78].dir_val_latch | tri_rlmreg_p__parameterized9_8538 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[79].dir_lru_latch | tri_rlmreg_p__parameterized5_8539 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[79].dir_val_latch | tri_rlmreg_p__parameterized9_8540 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[7].dir_lru_latch | tri_rlmreg_p__parameterized5_8541 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[7].dir_val_latch | tri_rlmreg_p__parameterized9_8542 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[80].dir_lru_latch | tri_rlmreg_p__parameterized5_8543 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[80].dir_val_latch | tri_rlmreg_p__parameterized9_8544 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[81].dir_lru_latch | tri_rlmreg_p__parameterized5_8545 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[81].dir_val_latch | tri_rlmreg_p__parameterized9_8546 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[82].dir_lru_latch | tri_rlmreg_p__parameterized5_8547 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[82].dir_val_latch | tri_rlmreg_p__parameterized9_8548 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[83].dir_lru_latch | tri_rlmreg_p__parameterized5_8549 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[83].dir_val_latch | tri_rlmreg_p__parameterized9_8550 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[84].dir_lru_latch | tri_rlmreg_p__parameterized5_8551 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[84].dir_val_latch | tri_rlmreg_p__parameterized9_8552 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[85].dir_lru_latch | tri_rlmreg_p__parameterized5_8553 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[85].dir_val_latch | tri_rlmreg_p__parameterized9_8554 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[86].dir_lru_latch | tri_rlmreg_p__parameterized5_8555 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[86].dir_val_latch | tri_rlmreg_p__parameterized9_8556 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[87].dir_lru_latch | tri_rlmreg_p__parameterized5_8557 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[87].dir_val_latch | tri_rlmreg_p__parameterized9_8558 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[88].dir_lru_latch | tri_rlmreg_p__parameterized5_8559 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[88].dir_val_latch | tri_rlmreg_p__parameterized9_8560 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[89].dir_lru_latch | tri_rlmreg_p__parameterized5_8561 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[89].dir_val_latch | tri_rlmreg_p__parameterized9_8562 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[8].dir_lru_latch | tri_rlmreg_p__parameterized5_8563 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[8].dir_val_latch | tri_rlmreg_p__parameterized9_8564 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[90].dir_lru_latch | tri_rlmreg_p__parameterized5_8565 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[90].dir_val_latch | tri_rlmreg_p__parameterized9_8566 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[91].dir_lru_latch | tri_rlmreg_p__parameterized5_8567 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[91].dir_val_latch | tri_rlmreg_p__parameterized9_8568 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[92].dir_lru_latch | tri_rlmreg_p__parameterized5_8569 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[92].dir_val_latch | tri_rlmreg_p__parameterized9_8570 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[93].dir_lru_latch | tri_rlmreg_p__parameterized5_8571 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[93].dir_val_latch | tri_rlmreg_p__parameterized9_8572 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[94].dir_lru_latch | tri_rlmreg_p__parameterized5_8573 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[94].dir_val_latch | tri_rlmreg_p__parameterized9_8574 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[95].dir_lru_latch | tri_rlmreg_p__parameterized5_8575 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[95].dir_val_latch | tri_rlmreg_p__parameterized9_8576 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[96].dir_lru_latch | tri_rlmreg_p__parameterized5_8577 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[96].dir_val_latch | tri_rlmreg_p__parameterized9_8578 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[97].dir_lru_latch | tri_rlmreg_p__parameterized5_8579 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[97].dir_val_latch | tri_rlmreg_p__parameterized9_8580 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[98].dir_lru_latch | tri_rlmreg_p__parameterized5_8581 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[98].dir_val_latch | tri_rlmreg_p__parameterized9_8582 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[99].dir_lru_latch | tri_rlmreg_p__parameterized5_8583 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[99].dir_val_latch | tri_rlmreg_p__parameterized9_8584 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[9].dir_lru_latch | tri_rlmreg_p__parameterized5_8585 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl17.dir_val_latch_gen[9].dir_val_latch | tri_rlmreg_p__parameterized9_8586 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl19.gen1.thr[0].stored_erat_rpn_latch | tri_rlmreg_p__parameterized53_8587 | 30 | 30 | 0 | 0 | 30 | 0 | 0 | 0 | | xhdl19.gen1.thr[0].stored_erat_wimge_latch | tri_rlmreg_p__parameterized4_8588 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_ic_ierat0 | iuq_ic_ierat | 3522 | 3522 | 0 | 0 | 2973 | 1 | 2 | 0 | | ccr2_frat_paranoia_latch | tri_rlmreg_p__parameterized6_8177 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | ccr2_notlb_latch | tri_rlmlatch_p__parameterized1_8178 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_ic_csinv_comp_latch | tri_rlmreg_p__parameterized9_8179 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | entry_match_latch | tri_rlmreg_p__parameterized3_8180 | 28 | 28 | 0 | 0 | 16 | 0 | 0 | 0 | | entry_valid_latch | tri_rlmreg_p__parameterized3_8181 | 4 | 4 | 0 | 0 | 16 | 0 | 0 | 0 | | eptr_latch | tri_rlmreg_p__parameterized9_8182 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_extclass_latch | tri_rlmreg_p__parameterized2_8183 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_pid_latch | tri_rlmreg_p__parameterized41_8184 | 102 | 102 | 0 | 0 | 14 | 0 | 0 | 0 | | ex1_state_latch | tri_rlmreg_p__parameterized9_8185 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_stg_act_latch | tri_rlmlatch_p_8186 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_tlbsel_latch | tri_rlmreg_p__parameterized2_8187 | 28 | 28 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_ttype_latch | tri_rlmreg_p__parameterized5_8188 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_valid_latch | tri_rlmreg_p__parameterized37_8189 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ws_latch | tri_rlmreg_p__parameterized2_8190 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_extclass_latch | tri_rlmreg_p__parameterized2_8191 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_pid_latch | tri_rlmreg_p__parameterized41_8192 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_ra_entry_latch | tri_rlmreg_p__parameterized9_8193 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_state_latch | tri_rlmreg_p__parameterized9_8194 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_stg_act_latch | tri_rlmlatch_p_8195 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tlbsel_latch | tri_rlmreg_p__parameterized2_8196 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ttype_latch | tri_rlmreg_p__parameterized5_8197 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_valid_latch | tri_rlmreg_p__parameterized37_8198 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ws_latch | tri_rlmreg_p__parameterized2_8199 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_eratsx_data_latch | tri_rlmreg_p__parameterized0_8200 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_extclass_latch | tri_rlmreg_p__parameterized2_8201 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_parerr_latch | tri_rlmreg_p__parameterized2_8202 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_pid_latch | tri_rlmreg_p__parameterized41_8203 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ex3_ra_entry_latch | tri_rlmreg_p__parameterized9_8204 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_state_latch | tri_rlmreg_p__parameterized9_8205 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_stg_act_latch | tri_rlmlatch_p_8206 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_tlbsel_latch | tri_rlmreg_p__parameterized2_8207 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_ttype_latch | tri_rlmreg_p__parameterized5_8208 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_valid_latch | tri_rlmreg_p__parameterized37_8209 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ws_latch | tri_rlmreg_p__parameterized2_8210 | 100 | 100 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_data_out_latch | tri_rlmreg_p__parameterized33_8211 | 31 | 31 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_extclass_latch | tri_rlmreg_p__parameterized2_8212 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ieen_latch | tri_rlmreg_p__parameterized4_8213 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_parerr_latch | tri_rlmreg_p__parameterized9_8214 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_pid_latch | tri_rlmreg_p__parameterized41_8215 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ex4_ra_entry_latch | tri_rlmreg_p__parameterized9_8216 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_rd_array_data_latch | tri_rlmreg_p__parameterized45_8217 | 15 | 15 | 0 | 0 | 68 | 0 | 0 | 0 | | ex4_rd_cam_data_latch | tri_rlmreg_p__parameterized44_8218 | 23 | 23 | 0 | 0 | 83 | 0 | 0 | 0 | | ex4_state_latch | tri_rlmreg_p__parameterized9_8219 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_stg_act_latch | tri_rlmlatch_p_8220 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlbsel_latch | tri_rlmreg_p__parameterized2_8221 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ttype_latch | tri_rlmreg_p__parameterized5_8222 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_valid_latch | tri_rlmreg_p__parameterized37_8223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ws_latch | tri_rlmreg_p__parameterized2_8224 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_data_in_latch | tri_rlmreg_p__parameterized33_8225 | 128 | 128 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_extclass_latch | tri_rlmreg_p__parameterized2_8226 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_ieen_latch | tri_rlmreg_p__parameterized4_8227 | 4 | 4 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_pid_latch | tri_rlmreg_p__parameterized41_8228 | 28 | 28 | 0 | 0 | 14 | 0 | 0 | 0 | | ex5_ra_entry_latch | tri_rlmreg_p__parameterized9_8229 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_state_latch | tri_rlmreg_p__parameterized9_8230 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_stg_act_latch | tri_rlmlatch_p_8231 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlbsel_latch | tri_rlmreg_p__parameterized2_8232 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_ttype_latch | tri_rlmreg_p__parameterized5_8233 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_valid_latch | tri_rlmreg_p__parameterized37_8234 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ws_latch | tri_rlmreg_p__parameterized2_8235 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_data_in_latch | tri_rlmreg_p__parameterized33_8236 | 88 | 88 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_extclass_latch | tri_rlmreg_p__parameterized2_8237 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ieen_latch | tri_rlmreg_p__parameterized4_8238 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex6_pid_latch | tri_rlmreg_p__parameterized41_8239 | 18 | 18 | 0 | 0 | 14 | 0 | 0 | 0 | | ex6_ra_entry_latch | tri_rlmreg_p__parameterized9_8240 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_state_latch | tri_rlmreg_p__parameterized9_8241 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_stg_act_latch | tri_rlmlatch_p_8242 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_tlbsel_latch | tri_rlmreg_p__parameterized2_8243 | 9 | 9 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ttype_latch | tri_rlmreg_p__parameterized5_8244 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_valid_latch | tri_rlmreg_p__parameterized37_8245 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ws_latch | tri_rlmreg_p__parameterized2_8246 | 89 | 89 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_stg_act_latch | tri_rlmlatch_p_8247 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_tlbsel_latch | tri_rlmreg_p__parameterized2_8248 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_ttype_latch | tri_rlmreg_p__parameterized5_8249 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_valid_latch | tri_rlmreg_p__parameterized37_8250 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hold_req_latch | tri_rlmreg_p__parameterized42_8251 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_cam | tri_cam_16x143_1r1w1c | 1778 | 1778 | 0 | 0 | 1836 | 1 | 2 | 0 | | iu1_flush_enab_latch | tri_rlmlatch_p_8252 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_nonspec_latch | tri_rlmlatch_p_8253 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_pid_latch | tri_rlmreg_p__parameterized41_8254 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | iu1_prefetch_latch | tri_rlmlatch_p_8255 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_state_latch | tri_rlmreg_p__parameterized9_8256 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | iu1_stg_act_latch | tri_rlmlatch_p_8257 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_valid_latch | tri_rlmreg_p__parameterized37_8258 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_array_cmp_data_latch | tri_rlmreg_p__parameterized45_8259 | 17 | 17 | 0 | 0 | 68 | 0 | 0 | 0 | | iu2_cam_cmp_data_latch | tri_rlmreg_p__parameterized44_8260 | 23 | 23 | 0 | 0 | 83 | 0 | 0 | 0 | | iu2_isi_latch | tri_rlmreg_p__parameterized0_8261 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | iu2_miss_latch | tri_rlmreg_p__parameterized2_8262 | 19 | 19 | 0 | 0 | 2 | 0 | 0 | 0 | | iu2_multihit_latch | tri_rlmreg_p__parameterized2_8263 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu2_n_flush_req_latch | tri_rlmreg_p__parameterized37_8264 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_nonspec_latch | tri_rlmlatch_p_8265 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_parerr_latch | tri_rlmreg_p__parameterized2_8266 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | iu2_pid_latch | tri_rlmreg_p__parameterized41_8267 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | iu2_state_latch | tri_rlmreg_p__parameterized9_8268 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu2_stg_act_latch | tri_rlmlatch_p_8269 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_tlbreq_latch | tri_rlmlatch_p_8270 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_valid_latch | tri_rlmreg_p__parameterized37_8271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_stg_act_latch | tri_rlmlatch_p_8272 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_err_ierat_multihit_latch | tri_rlmlatch_p_8273 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_err_ierat_parity_latch | tri_rlmlatch_p_8274 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_ierat_ex2_flush_latch | tri_rlmreg_p__parameterized37_8275 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_ord_par_err_latch | tri_rlmlatch_p_8276 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_ord_read_done_latch | tri_rlmlatch_p_8277 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_ord_write_done_latch | tri_rlmlatch_p_8278 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lru_latch | tri_rlmreg_p__parameterized43_8279 | 27 | 27 | 0 | 0 | 15 | 0 | 0 | 0 | | lru_update_event_latch | tri_rlmreg_p__parameterized6_8280 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | | mchk_flash_inv_latch | tri_rlmreg_p__parameterized9_8281 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | mmucr1_latch | tri_rlmreg_p__parameterized46_8282 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | por_seq_latch | tri_rlmreg_p__parameterized5_8283 | 99 | 99 | 0 | 0 | 3 | 0 | 0 | 0 | | snoop_act_latch | tri_rlmlatch_p_8284 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | snoop_addr_latch | tri_rlmreg_p__parameterized34_8285 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | snoop_attr_latch | tri_rlmreg_p__parameterized48_8286 | 8 | 8 | 0 | 0 | 26 | 0 | 0 | 0 | | snoop_val_latch | tri_rlmreg_p__parameterized5_8287 | 147 | 147 | 0 | 0 | 3 | 0 | 0 | 0 | | tlb_flushed_latch | tri_rlmreg_p__parameterized37_8288 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_miss_latch | tri_rlmreg_p__parameterized37_8289 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_rel_act_latch | tri_rlmlatch_p_8290 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_rel_data_latch | tri_rlmreg_p__parameterized49_8291 | 162 | 162 | 0 | 0 | 127 | 0 | 0 | 0 | | tlb_rel_val_latch | tri_rlmreg_p__parameterized4_8292 | 100 | 100 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_req_inprogress_latch | tri_rlmreg_p__parameterized37_8293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | watermark_latch | tri_rlmreg_p__parameterized47 | 191 | 191 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl4.rpn_holdreg[0].rpn_holdreg_latch | tri_rlmreg_p__parameterized33_8294 | 0 | 0 | 0 | 0 | 50 | 0 | 0 | 0 | | xucr4_mmu_mchk_latch | tri_rlmlatch_p__parameterized1_8295 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_ic_miss0 | iuq_ic_miss | 3423 | 3423 | 0 | 0 | 333 | 0 | 0 | 0 | | an_ac_reld_core_tag_latch | tri_rlmreg_p__parameterized4_8135 | 114 | 114 | 0 | 0 | 5 | 0 | 0 | 0 | | an_ac_reld_data_vld_latch | tri_rlmlatch_p_8136 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | an_ac_reld_qw_latch | tri_rlmreg_p__parameterized2_8137 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | bp_config_latch | tri_rlmreg_p__parameterized9_8138 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | iu3_miss_match_latch | tri_rlmlatch_p_8139 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lru_write_latch | tri_rlmreg_p__parameterized2_8140 | 954 | 954 | 0 | 0 | 2 | 0 | 0 | 0 | | lru_write_next_cycle_latch | tri_rlmreg_p__parameterized2_8141 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_block_fp_latch | tri_rlmreg_p__parameterized2_8142 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_flush_occurred_latch | tri_rlmreg_p__parameterized2_8143 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_flushed_latch | tri_rlmreg_p__parameterized2_8144 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_inval_latch | tri_rlmreg_p__parameterized2_8145 | 71 | 71 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_need_hold_latch | tri_rlmreg_p__parameterized2_8146 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | miss_wrote_dir_latch | tri_rlmreg_p__parameterized2_8147 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | r2_crit_qw_latch | tri_rlmlatch_p_8148 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | r3_loaded_latch | tri_rlmlatch_p_8149 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_data_latch | tri_rlmreg_p__parameterized1_8150 | 215 | 215 | 0 | 0 | 128 | 0 | 0 | 0 | | reld_r1_qw_latch | tri_rlmreg_p__parameterized2_8151 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_r1_val_latch | tri_rlmreg_p__parameterized2_8152 | 281 | 281 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_r2_qw_latch | tri_rlmreg_p__parameterized2_8153 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_r2_val_latch | tri_rlmreg_p__parameterized2_8154 | 1427 | 1427 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_r3_val_latch | tri_rlmreg_p__parameterized2_8155 | 148 | 148 | 0 | 0 | 2 | 0 | 0 | 0 | | req_ctag_latch | tri_rlmreg_p__parameterized2_8156 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | req_ra_latch | tri_rlmreg_p__parameterized61_8157 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | req_wimge_latch | tri_rlmreg_p__parameterized4_8158 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | request_latch | tri_rlmreg_p__parameterized37_8159 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ic_cls_latch | tri_rlmlatch_p_8160 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl21.gen_sm[0].miss_count_latch | tri_rlmreg_p__parameterized5_8161 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl21.gen_sm[0].miss_tid_sm_latch | tri_rlmreg_p__parameterized59 | 24 | 24 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.gen_sm[1].miss_count_latch | tri_rlmreg_p__parameterized5_8162 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl21.gen_sm[1].miss_tid_sm_latch | tri_rlmreg_p__parameterized59_8163 | 31 | 31 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl22.gen[0].miss_2ucode_latch | tri_rlmlatch_p_8164 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[0].miss_2ucode_type_latch | tri_rlmlatch_p_8165 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[0].miss_addr_eff_latch | tri_rlmreg_p__parameterized6_8166 | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 | | xhdl22.gen[0].miss_addr_real_latch | tri_rlmreg_p__parameterized60 | 84 | 84 | 0 | 0 | 40 | 0 | 0 | 0 | | xhdl22.gen[0].miss_ci_latch | tri_rlmlatch_p_8167 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[0].miss_endian_latch | tri_rlmlatch_p_8168 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[0].miss_way_latch | tri_rlmreg_p__parameterized9_8169 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.gen[1].miss_2ucode_latch | tri_rlmlatch_p_8170 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[1].miss_2ucode_type_latch | tri_rlmlatch_p_8171 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[1].miss_addr_eff_latch | tri_rlmreg_p__parameterized6_8172 | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 | | xhdl22.gen[1].miss_addr_real_latch | tri_rlmreg_p__parameterized60_8173 | 8 | 8 | 0 | 0 | 40 | 0 | 0 | 0 | | xhdl22.gen[1].miss_ci_latch | tri_rlmlatch_p_8174 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[1].miss_endian_latch | tri_rlmlatch_p_8175 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl22.gen[1].miss_way_latch | tri_rlmreg_p__parameterized9_8176 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | iuq_ic_select0 | iuq_ic_select | 899 | 899 | 0 | 0 | 294 | 0 | 0 | 0 | | back_inv_icbi_latch | tri_rlmreg_p__parameterized37_8036 | 213 | 213 | 0 | 0 | 1 | 0 | 0 | 0 | | back_inv_latch | tri_rlmlatch_p_8037 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | br_iu_bta_latch | tri_rlmreg_p__parameterized40_8038 | 63 | 63 | 0 | 0 | 62 | 0 | 0 | 0 | | br_iu_redirect_latch | tri_rlmreg_p__parameterized37_8039 | 91 | 91 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_2ucode_latch | tri_rlmreg_p__parameterized37_8040 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_2ucode_type_latch | tri_rlmreg_p__parameterized37_8041 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_into_uc_latch | tri_rlmreg_p__parameterized37_8042 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_8043 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_nonspec_latch | tri_rlmreg_p__parameterized37_8044 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_ic_stop_latch | tri_rlmreg_p__parameterized37_8045 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_hold_latch | tri_rlmreg_p__parameterized37_8046 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu0_2ucode_latch | tri_rlmreg_p__parameterized37_8047 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu0_2ucode_type_latch | tri_rlmreg_p__parameterized37_8048 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu0_flip_index51_latch | tri_rlmreg_p__parameterized37_8049 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu0_need_prefetch_latch | tri_rlmreg_p__parameterized37_8050 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_nonspec_latch | tri_rlmreg_p__parameterized37_8051 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_nonspec_latch | tri_rlmreg_p__parameterized37_8052 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_iu_icbi_val_latch | tri_rlmreg_p__parameterized37_8053 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_bus_snoop_hold_req_latch | tri_rlmreg_p__parameterized37_8054 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_hold_req_latch | tri_rlmreg_p__parameterized37_8055 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | next_fetch_nonspec_latch | tri_rlmreg_p__parameterized37_8056 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_iu_pm_fetch_halt_latch | tri_rlmreg_p__parameterized37_8057 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_idir_read_latch | tri_rlmlatch_p_8058 | 352 | 352 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_idir_row_latch | tri_rlmreg_p__parameterized18_8059 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl10.t[0].iu0_prefetch_ifar_latch | tri_rlmreg_p__parameterized3_8060 | 6 | 6 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl11.t[0].lq_iu_icbi_addr_latch | tri_rlmreg_p__parameterized52_8061 | 30 | 30 | 0 | 0 | 36 | 0 | 0 | 0 | | xhdl13.th[0].ibuff[0].iu0_sent_latch | tri_rlmreg_p__parameterized5_8062 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl13.th[0].ibuff[1].iu0_sent_latch | tri_rlmreg_p__parameterized5_8063 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl13.th[0].ibuff[2].iu0_sent_latch | tri_rlmreg_p__parameterized5_8064 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl13.th[0].ibuff[3].iu0_sent_latch | tri_rlmreg_p__parameterized5_8065 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[0].iu0_ifar_latch | tri_rlmlatch_p_8066 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[10].iu0_ifar_latch | tri_rlmlatch_p_8067 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[11].iu0_ifar_latch | tri_rlmlatch_p_8068 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[12].iu0_ifar_latch | tri_rlmlatch_p_8069 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[13].iu0_ifar_latch | tri_rlmlatch_p_8070 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[14].iu0_ifar_latch | tri_rlmlatch_p_8071 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[15].iu0_ifar_latch | tri_rlmlatch_p_8072 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[16].iu0_ifar_latch | tri_rlmlatch_p_8073 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[17].iu0_ifar_latch | tri_rlmlatch_p_8074 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[18].iu0_ifar_latch | tri_rlmlatch_p_8075 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[19].iu0_ifar_latch | tri_rlmlatch_p_8076 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[1].iu0_ifar_latch | tri_rlmlatch_p_8077 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[20].iu0_ifar_latch | tri_rlmlatch_p_8078 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[21].iu0_ifar_latch | tri_rlmlatch_p_8079 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[22].iu0_ifar_latch | tri_rlmlatch_p_8080 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[23].iu0_ifar_latch | tri_rlmlatch_p_8081 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[24].iu0_ifar_latch | tri_rlmlatch_p_8082 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[25].iu0_ifar_latch | tri_rlmlatch_p_8083 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[26].iu0_ifar_latch | tri_rlmlatch_p_8084 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[27].iu0_ifar_latch | tri_rlmlatch_p_8085 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[28].iu0_ifar_latch | tri_rlmlatch_p_8086 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[29].iu0_ifar_latch | tri_rlmlatch_p_8087 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[2].iu0_ifar_latch | tri_rlmlatch_p_8088 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[30].iu0_ifar_latch | tri_rlmlatch_p_8089 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[31].iu0_ifar_latch | tri_rlmlatch_p_8090 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[32].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8091 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[33].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8092 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[34].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8093 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[35].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8094 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[36].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8095 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[37].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8096 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[38].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8097 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[39].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8098 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[3].iu0_ifar_latch | tri_rlmlatch_p_8099 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[40].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8100 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[41].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8101 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[42].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8102 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[43].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8103 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[44].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8104 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[45].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8105 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[46].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8106 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[47].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8107 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[48].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8108 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[49].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8109 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[4].iu0_ifar_latch | tri_rlmlatch_p_8110 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[50].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8111 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[51].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8112 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[52].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[53].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8114 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[54].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8115 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[55].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8116 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[56].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8117 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[57].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8118 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[58].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8119 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[59].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8120 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[5].iu0_ifar_latch | tri_rlmlatch_p_8121 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[60].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8122 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[61].iu0_ifar_latch | tri_rlmlatch_p__parameterized1_8123 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[6].iu0_ifar_latch | tri_rlmlatch_p_8124 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[7].iu0_ifar_latch | tri_rlmlatch_p_8125 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[8].iu0_ifar_latch | tri_rlmlatch_p_8126 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl14.th[0].q_gen[9].iu0_ifar_latch | tri_rlmlatch_p_8127 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl15.gen1.t[0].stored_erat_ifar_latch | tri_rlmreg_p__parameterized6_8128 | 6 | 6 | 0 | 0 | 10 | 0 | 0 | 0 | | xhdl15.stored_erat_valid_latch | tri_rlmreg_p__parameterized37_8129 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl17.t[0].cp_flush_ifar_latch | tri_rlmreg_p__parameterized40_8130 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | xu_iu_msr_cm2_latch | tri_rlmreg_p__parameterized37_8131 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_msr_cm3_latch | tri_rlmreg_p__parameterized37_8132 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_msr_cm_latch | tri_rlmreg_p__parameterized37_8133 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_run_thread_latch | tri_rlmreg_p__parameterized37_8134 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_ram0 | iuq_ram | 69 | 69 | 0 | 0 | 40 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_8031 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ram_act_reg | tri_rlmreg_p__parameterized37_8032 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ram_done_reg | tri_rlmlatch_p_8033 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ram_instr_reg | tri_rlmreg_p__parameterized52_8034 | 64 | 64 | 0 | 0 | 36 | 0 | 0 | 0 | | ram_val_reg | tri_rlmreg_p__parameterized37_8035 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_spr0 | iuq_spr | 1308 | 1308 | 0 | 0 | 844 | 0 | 0 | 0 | | cp_flush_latch | tri_ser_rlmreg_p__parameterized4_7991 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_8030 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cpcr0_reg | tri_rlmreg_p__parameterized38 | 1 | 1 | 0 | 0 | 20 | 0 | 0 | 0 | | cpcr1_reg | tri_rlmreg_p__parameterized39 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | cpcr_we_reg | tri_rlmreg_p__parameterized37_7992 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | givpr_reg | tri_rlmreg_p__parameterized34_7993 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | iac1_reg | tri_rlmreg_p__parameterized40_7994 | 3 | 3 | 0 | 0 | 62 | 0 | 0 | 0 | | iac2_reg | tri_rlmreg_p__parameterized40_7995 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | iac3_reg | tri_rlmreg_p__parameterized40_7996 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | iac4_reg | tri_rlmreg_p__parameterized40_7997 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | iesr1_reg | tri_ser_rlmreg_p__parameterized7_7998 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized7_8029 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | | iesr2_reg | tri_ser_rlmreg_p__parameterized7_7999 | 4 | 4 | 0 | 0 | 24 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized7_8028 | 4 | 4 | 0 | 0 | 24 | 0 | 0 | 0 | | iesr3_reg | tri_ser_rlmreg_p__parameterized6_8000 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_8027 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | immr0a_reg | tri_rlmreg_p__parameterized35 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | immr0b_reg | tri_rlmreg_p__parameterized35_8001 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | imr0_reg | tri_rlmreg_p__parameterized17_8002 | 42 | 42 | 0 | 0 | 32 | 0 | 0 | 0 | | iucr0_reg | tri_rlmreg_p__parameterized36 | 6 | 6 | 0 | 0 | 13 | 0 | 0 | 0 | | iudbg0_done_reg | tri_rlmlatch_p_8003 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iudbg0_exec_reg | tri_rlmlatch_p_8004 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iudbg0_reg | tri_ser_rlmreg_p__parameterized0_8005 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized0_8026 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | iudbg1_reg | tri_ser_rlmreg_p__parameterized1 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized1 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | iudbg2_reg | tri_ser_rlmreg_p__parameterized2_8006 | 0 | 0 | 0 | 0 | 29 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized2_8025 | 0 | 0 | 0 | 0 | 29 | 0 | 0 | 0 | | iulfsr_reg | tri_ser_rlmreg_p | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | iullcr_reg | tri_ser_rlmreg_p__parameterized3 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized3 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | | ivpr_reg | tri_rlmreg_p__parameterized34_8007 | 20 | 20 | 0 | 0 | 52 | 0 | 0 | 0 | | raise_iss_pri_reg | tri_ser_rlmreg_p__parameterized4_8008 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_8024 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_addr_reg | tri_rlmreg_p__parameterized6_8009 | 795 | 795 | 0 | 0 | 10 | 0 | 0 | 0 | | slowspr_data_reg | tri_rlmreg_p__parameterized33_8010 | 372 | 372 | 0 | 0 | 64 | 0 | 0 | 0 | | slowspr_done_reg | tri_rlmlatch_p_8011 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_etid_reg | tri_rlmreg_p__parameterized2_8012 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | slowspr_rw_reg | tri_rlmlatch_p_8013 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_val_reg | tri_rlmlatch_p_8014 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_gs_latch | tri_ser_rlmreg_p__parameterized4_8015 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_8023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_pr_latch | tri_ser_rlmreg_p__parameterized4_8016 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_8022 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl1.thread_regs[0].cpcr2_reg | tri_rlmreg_p__parameterized29 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | xhdl1.thread_regs[0].cpcr3_reg | tri_rlmreg_p__parameterized30 | 12 | 12 | 0 | 0 | 17 | 0 | 0 | 0 | | xhdl1.thread_regs[0].cpcr4_reg | tri_rlmreg_p__parameterized31 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | xhdl1.thread_regs[0].cpcr5_reg | tri_rlmreg_p__parameterized32 | 9 | 9 | 0 | 0 | 17 | 0 | 0 | 0 | | xhdl1.thread_regs[0].eheir_reg | tri_rlmreg_p__parameterized17_8017 | 1 | 1 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl1.thread_regs[0].iucr1_reg | tri_rlmreg_p__parameterized27 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl1.thread_regs[0].iucr2_reg | tri_rlmreg_p__parameterized12_8018 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl1.thread_regs[0].ppr32_reg | tri_rlmreg_p__parameterized28_8019 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | xu_iu_pri_reg | tri_ser_rlmreg_p__parameterized5 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized5 | 9 | 9 | 0 | 0 | 3 | 0 | 0 | 0 | | xu_iu_pri_val_reg | tri_ser_rlmreg_p__parameterized4_8020 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_8021 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl0.bp_gen[0].iuq_bp0 | iuq_bp | 2829 | 2829 | 0 | 0 | 1329 | 0 | 0 | 0 | | bcache_data0_reg | tri_rlmreg_p__parameterized3_7900 | 8 | 8 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data1_reg | tri_rlmreg_p__parameterized3_7901 | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data2_reg | tri_rlmreg_p__parameterized3_7902 | 21 | 21 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data3_reg | tri_rlmreg_p__parameterized3_7903 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data4_reg | tri_rlmreg_p__parameterized3_7904 | 22 | 22 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data5_reg | tri_rlmreg_p__parameterized3_7905 | 22 | 22 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data6_reg | tri_rlmreg_p__parameterized3_7906 | 21 | 21 | 0 | 0 | 16 | 0 | 0 | 0 | | bcache_data7_reg | tri_rlmreg_p__parameterized3_7907 | 27 | 27 | 0 | 0 | 16 | 0 | 0 | 0 | | bp_config_reg | tri_rlmreg_p__parameterized13_7908 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | | br_iu_gshare_reg | tri_rlmreg_p__parameterized14_7909 | 27 | 27 | 0 | 0 | 18 | 0 | 0 | 0 | | br_iu_ls_data_reg | tri_rlmreg_p__parameterized8_7910 | 160 | 160 | 0 | 0 | 20 | 0 | 0 | 0 | | br_iu_ls_ptr_reg | tri_rlmreg_p__parameterized12_7911 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | br_iu_ls_update_reg | tri_rlmlatch_p_7912 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmlatch_p_7913 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_gs_count_reg | tri_rlmreg_p__parameterized2_7914 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | | cp_gshare_reg | tri_rlmreg_p__parameterized3_7915 | 17 | 17 | 0 | 0 | 10 | 0 | 0 | 0 | | ex5_bcctr_reg | tri_rlmlatch_p_7916 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_bclr_reg | tri_rlmlatch_p_7917 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_bh0_hist_reg | tri_rlmreg_p__parameterized2_7918 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_bh1_hist_reg | tri_rlmreg_p__parameterized2_7919 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_bh2_hist_reg | tri_rlmreg_p__parameterized2_7920 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_bh_reg | tri_rlmreg_p__parameterized2_7921 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_bh_update_reg | tri_rlmlatch_p_7922 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_br_taken_reg | tri_rlmlatch_p_7923 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_bta_reg | tri_rlmreg_p__parameterized8_7924 | 30 | 30 | 0 | 0 | 20 | 0 | 0 | 0 | | ex5_btb_entry_reg | tri_rlmlatch_p_7925 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_btb_repl_reg | tri_rlmreg_p__parameterized1_7926 | 1 | 1 | 0 | 0 | 128 | 0 | 0 | 0 | | ex5_flush_reg | tri_rlmlatch_p_7927 | 270 | 270 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_group_reg | tri_rlmlatch_p_7928 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_gshare_reg | tri_rlmreg_p__parameterized6_7929 | 36 | 36 | 0 | 0 | 10 | 0 | 0 | 0 | | ex5_ifar_reg | tri_rlmreg_p__parameterized8_7930 | 601 | 601 | 0 | 0 | 20 | 0 | 0 | 0 | | ex5_ls_pop_reg | tri_rlmlatch_p_7931 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ls_ptr_reg | tri_rlmreg_p__parameterized12_7932 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_ls_push_reg | tri_rlmlatch_p_7933 | 165 | 165 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_val_reg | tri_rlmlatch_p_7934 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_ls_t00_reg | tri_rlmreg_p__parameterized8_7935 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t01_reg | tri_rlmreg_p__parameterized8_7936 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t02_reg | tri_rlmreg_p__parameterized8_7937 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t03_reg | tri_rlmreg_p__parameterized8_7938 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t04_reg | tri_rlmreg_p__parameterized8_7939 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t05_reg | tri_rlmreg_p__parameterized8_7940 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t06_reg | tri_rlmreg_p__parameterized8_7941 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t07_reg | tri_rlmreg_p__parameterized8_7942 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex6_ls_t0_ptr_reg | tri_rlmreg_p__parameterized11 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | gshare_reg | tri_rlmreg_p__parameterized3_7943 | 51 | 51 | 0 | 0 | 16 | 0 | 0 | 0 | | gshare_shift0_reg | tri_rlmreg_p__parameterized4_7944 | 46 | 46 | 0 | 0 | 4 | 0 | 0 | 0 | | iu0_btb_hist_reg | tri_rlmreg_p__parameterized1_7945 | 6 | 6 | 0 | 0 | 128 | 0 | 0 | 0 | | iu1_btb_hist_reg | tri_rlmreg_p__parameterized2_7946 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_gs_pos_reg | tri_rlmreg_p__parameterized5_7947 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu1_gshare_reg | tri_rlmreg_p__parameterized6_7948 | 12 | 12 | 0 | 0 | 10 | 0 | 0 | 0 | | iu2_btb_hist_reg | tri_rlmreg_p__parameterized2_7949 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu2_gs_pos_reg | tri_rlmreg_p__parameterized5_7950 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | iu2_gshare_reg | tri_rlmreg_p__parameterized6_7951 | 44 | 44 | 0 | 0 | 10 | 0 | 0 | 0 | | iu3_0_instr_reg | tri_rlmreg_p__parameterized10 | 152 | 152 | 0 | 0 | 59 | 0 | 0 | 0 | | iu3_1_instr_reg | tri_rlmreg_p__parameterized10_7952 | 101 | 101 | 0 | 0 | 59 | 0 | 0 | 0 | | iu3_2_instr_reg | tri_rlmreg_p__parameterized10_7953 | 128 | 128 | 0 | 0 | 59 | 0 | 0 | 0 | | iu3_3_instr_reg | tri_rlmreg_p__parameterized10_7954 | 319 | 319 | 0 | 0 | 59 | 0 | 0 | 0 | | iu3_aa_reg | tri_rlmlatch_p_7955 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_b_reg | tri_rlmlatch_p_7956 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_bcctr_reg | tri_rlmlatch_p_7957 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_bclr_reg | tri_rlmlatch_p_7958 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_bh_reg | tri_rlmreg_p__parameterized2_7959 | 89 | 89 | 0 | 0 | 2 | 0 | 0 | 0 | | iu3_bi_reg | tri_rlmreg_p__parameterized4_7960 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | iu3_bo_reg | tri_rlmreg_p__parameterized4_7961 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | iu3_btb_link_reg | tri_rlmlatch_p_7962 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_btb_misdirect_reg | tri_rlmlatch_p_7963 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_btb_redirect_reg | tri_rlmlatch_p_7964 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_btb_reg | tri_rlmreg_p__parameterized8_7965 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_gs_pos_reg | tri_rlmreg_p__parameterized5_7966 | 40 | 40 | 0 | 0 | 3 | 0 | 0 | 0 | | iu3_ifar_pri_reg | tri_rlmreg_p__parameterized2_7967 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu3_ifar_reg | tri_rlmreg_p__parameterized8_7968 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_lk_reg | tri_rlmlatch_p_7969 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_lnk_reg | tri_rlmreg_p__parameterized8_7970 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_nfg_reg | tri_rlmreg_p__parameterized8_7971 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | iu3_opcode_reg | tri_rlmreg_p__parameterized0_7972 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | iu3_pr_val_reg | tri_rlmlatch_p_7973 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_tar_reg | tri_rlmreg_p__parameterized7_7974 | 48 | 48 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_val_reg | tri_rlmreg_p__parameterized9_7975 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_ifar_reg | tri_rlmreg_p__parameterized8_7976 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_ls_pop_reg | tri_rlmlatch_p_7977 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_ls_push_reg | tri_rlmlatch_p_7978 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_redirect_ifar_reg | tri_rlmreg_p__parameterized8_7979 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_redirect_reg | tri_rlmlatch_p_7980 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ls_t00_reg | tri_rlmreg_p__parameterized8_7981 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t01_reg | tri_rlmreg_p__parameterized8_7982 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t02_reg | tri_rlmreg_p__parameterized8_7983 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t03_reg | tri_rlmreg_p__parameterized8_7984 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t04_reg | tri_rlmreg_p__parameterized8_7985 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t05_reg | tri_rlmreg_p__parameterized8_7986 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t06_reg | tri_rlmreg_p__parameterized8_7987 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t07_reg | tri_rlmreg_p__parameterized8_7988 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ls_t0_ptr_reg | tri_rlmreg_p__parameterized11_7989 | 137 | 137 | 0 | 0 | 8 | 0 | 0 | 0 | | iu_flush_reg | tri_rlmlatch_p_7990 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl1.uc_gen[0].iuq_uc0 | iuq_uc | 2327 | 2327 | 0 | 0 | 1012 | 0 | 0 | 0 | | advance_buffers_latch | tri_rlmlatch_p_7831 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | br_hold_latch | tri_rlmlatch_p_7832 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | br_iu_redirect_latch | tri_rlmlatch_p_7833 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7834 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | flush_ifar_latch | tri_rlmreg_p__parameterized25 | 1 | 1 | 0 | 0 | 19 | 0 | 0 | 0 | | flush_into_uc_latch | tri_rlmlatch_p_7835 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_2ucode_latch | tri_rlmlatch_p__parameterized0 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_2ucode_type_latch | tri_rlmlatch_p__parameterized0_7836 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu3_ifar_latch | tri_rlmreg_p__parameterized15 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu3_instr_latch | tri_rlmreg_p__parameterized24 | 239 | 239 | 0 | 0 | 136 | 0 | 0 | 0 | | iu3_val_latch | tri_rlmreg_p__parameterized9_7837 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_done_latch | tri_rlmlatch_p__parameterized0_7838 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_ext0_latch | tri_rlmreg_p__parameterized26 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_ext1_latch | tri_rlmreg_p__parameterized26_7839 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_ifar_latch | tri_rlmreg_p__parameterized15_7840 | 19 | 19 | 0 | 0 | 19 | 0 | 0 | 0 | | iu4_ov_done_latch | tri_rlmlatch_p__parameterized0_7841 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_ov_ext1_latch | tri_rlmreg_p__parameterized26_7842 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_ov_ifar_latch | tri_rlmreg_p__parameterized15_7843 | 10 | 10 | 0 | 0 | 19 | 0 | 0 | 0 | | iu4_ov_instr0_latch | tri_rlmreg_p__parameterized16 | 3 | 3 | 0 | 0 | 32 | 0 | 0 | 0 | | iu4_ov_instr1_latch | tri_rlmreg_p__parameterized16_7844 | 8 | 8 | 0 | 0 | 32 | 0 | 0 | 0 | | iu4_ov_valid_latch | tri_rlmreg_p__parameterized2_7845 | 25 | 25 | 0 | 0 | 3 | 0 | 0 | 0 | | iu4_valid_latch | tri_rlmreg_p__parameterized2_7846 | 9 | 9 | 0 | 0 | 2 | 0 | 0 | 0 | | iu_flush_latch | tri_rlmlatch_p__parameterized0_7847 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_err_ucode_illegal_latch | tri_rlmlatch_p__parameterized0_7848 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_uc_buffer0 | iuq_uc_buffer | 331 | 331 | 0 | 0 | 154 | 0 | 0 | 0 | | buffer1_latch | tri_rlmreg_p__parameterized16_7892 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | buffer2_latch | tri_rlmreg_p__parameterized16_7893 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | buffer3_latch | tri_rlmreg_p__parameterized16_7894 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | buffer4_latch | tri_rlmreg_p__parameterized16_7895 | 19 | 19 | 0 | 0 | 32 | 0 | 0 | 0 | | buffer_valid_latch | tri_rlmreg_p__parameterized9_7896 | 274 | 274 | 0 | 0 | 4 | 0 | 0 | 0 | | uc_ic_hold_latch | tri_rlmlatch_p_7897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | uc_iu4_flush_ifar_latch | tri_rlmreg_p__parameterized15_7898 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | uc_iu4_flush_latch | tri_rlmlatch_p_7899 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | np1_flush_latch | tri_rlmlatch_p_7849 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rom_data_even_late_latch | tri_rlmreg_p__parameterized16_7850 | 0 | 0 | 0 | 0 | 28 | 0 | 0 | 0 | | rom_data_odd_late_latch | tri_rlmreg_p__parameterized16_7851 | 0 | 0 | 0 | 0 | 28 | 0 | 0 | 0 | | romvalid_latch | tri_rlmlatch_p_7852 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | u4_ov_ext0_latch | tri_rlmreg_p__parameterized26_7853 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | uc_control | iuq_uc_control | 909 | 909 | 0 | 0 | 450 | 0 | 0 | 0 | | cond_latch | tri_rlmlatch_p_7855 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | count_latch | tri_rlmreg_p__parameterized22 | 17 | 17 | 0 | 0 | 5 | 0 | 0 | 0 | | early_end_latch | tri_rlmlatch_p_7856 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ep_force_even_late_latch | tri_rlmlatch_p_7857 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ep_force_odd_late_latch | tri_rlmlatch_p_7858 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | flush_to_odd_latch | tri_rlmlatch_p_7859 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | force_ep_latch | tri_rlmlatch_p_7860 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fxm_type_latch | tri_rlmlatch_p_7861 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | inloop_latch | tri_rlmlatch_p_7862 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | instr_even_late_latch | tri_rlmreg_p__parameterized16_7863 | 38 | 38 | 0 | 0 | 31 | 0 | 0 | 0 | | instr_latch | tri_rlmreg_p__parameterized16_7864 | 36 | 36 | 0 | 0 | 32 | 0 | 0 | 0 | | instr_odd_late_latch | tri_rlmreg_p__parameterized16_7865 | 33 | 33 | 0 | 0 | 11 | 0 | 0 | 0 | | iuq_uc_cplbuffer0 | iuq_uc_cplbuffer | 624 | 624 | 0 | 0 | 322 | 0 | 0 | 0 | | buffer_count_latch | tri_rlmreg_p__parameterized9_7872 | 184 | 184 | 0 | 0 | 3 | 0 | 0 | 0 | | genblk2.gen_b[0].buffer_latch | tri_rlmreg_p__parameterized17_7873 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[0].xer_latch | tri_rlmreg_p__parameterized13_7874 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[1].buffer_latch | tri_rlmreg_p__parameterized17_7875 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[1].xer_latch | tri_rlmreg_p__parameterized13_7876 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[2].buffer_latch | tri_rlmreg_p__parameterized17_7877 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[2].xer_latch | tri_rlmreg_p__parameterized13_7878 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[3].buffer_latch | tri_rlmreg_p__parameterized17_7879 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[3].xer_latch | tri_rlmreg_p__parameterized13_7880 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[4].buffer_latch | tri_rlmreg_p__parameterized17_7881 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[4].xer_latch | tri_rlmreg_p__parameterized13_7882 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[5].buffer_latch | tri_rlmreg_p__parameterized17_7883 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[5].xer_latch | tri_rlmreg_p__parameterized13_7884 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[6].buffer_latch | tri_rlmreg_p__parameterized17_7885 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[6].xer_latch | tri_rlmreg_p__parameterized13_7886 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | genblk2.gen_b[7].buffer_latch | tri_rlmreg_p__parameterized17_7887 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | genblk2.gen_b[7].xer_latch | tri_rlmreg_p__parameterized13_7888 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | new_command_latch | tri_rlmlatch_p_7889 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized5_7890 | 112 | 112 | 0 | 0 | 3 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized5_7891 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | rom_addr_latch | tri_rlmreg_p__parameterized21 | 27 | 27 | 0 | 0 | 9 | 0 | 0 | 0 | | sel_even_late_latch | tri_rlmreg_p__parameterized19 | 69 | 69 | 0 | 0 | 10 | 0 | 0 | 0 | | sel_odd_late_latch | tri_rlmreg_p__parameterized20 | 16 | 16 | 0 | 0 | 9 | 0 | 0 | 0 | | skip_to_np1_latch | tri_rlmlatch_p_7866 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | skip_zero_latch | tri_rlmlatch_p_7867 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | valid_latch | tri_rlmlatch_p_7868 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | wait_for_xer_latch | tri_rlmlatch_p__parameterized0_7869 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xer_val_occurred_latch | tri_rlmlatch_p__parameterized0_7870 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_ucode_xer_latch | tri_rlmreg_p__parameterized18 | 28 | 28 | 0 | 0 | 7 | 0 | 0 | 0 | | xu_iu_ucode_xer_val_latch | tri_rlmlatch_p__parameterized0_7871 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | uc_rom_even | iuq_uc_rom_even | 365 | 365 | 0 | 0 | 16 | 0 | 0 | 0 | | rom_addr_latch | tri_rlmreg_p__parameterized23_7854 | 365 | 365 | 0 | 0 | 16 | 0 | 0 | 0 | | uc_rom_odd | iuq_uc_rom_odd | 380 | 380 | 0 | 0 | 21 | 0 | 0 | 0 | | rom_addr_latch | tri_rlmreg_p__parameterized23 | 380 | 380 | 0 | 0 | 21 | 0 | 0 | 0 | | iuq_slice_top0 | iuq_slice_top | 21417 | 21417 | 0 | 0 | 6431 | 0 | 0 | 0 | | dispatch | iuq_dispatch | 348 | 348 | 0 | 0 | 98 | 0 | 0 | 0 | | (dispatch) | iuq_dispatch | 335 | 335 | 0 | 0 | 0 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_7794 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dual_issue_use_fx0_latch | tri_rlmreg_p__parameterized2_7795 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | fu0_total_credit_cnt_latch | tri_rlmreg_p__parameterized175_7796 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | fu1_total_credit_cnt_latch | tri_rlmreg_p__parameterized4_7797 | 13 | 13 | 0 | 0 | 5 | 0 | 0 | 0 | | fx0_total_credit_cnt_latch | tri_rlmreg_p__parameterized175_7798 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | fx1_total_credit_cnt_latch | tri_rlmreg_p__parameterized175_7799 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | hold_done_latch | tri_rlmreg_p__parameterized37_7800 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hold_instructions_latch | tri_rlmlatch_p_7801 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hold_req_latch | tri_rlmreg_p__parameterized37_7802 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | in_fusion_latch | tri_rlmreg_p__parameterized37_7803 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | in_ucode_latch | tri_rlmreg_p__parameterized37_7804 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_axu0_credit_ok_latch | tri_rlmreg_p__parameterized37_7805 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_axu1_credit_ok_latch | tri_rlmreg_p__parameterized37_7806 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_fx0_credit_ok_latch | tri_rlmreg_p__parameterized37_7807 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_fx1_credit_ok_latch | tri_rlmreg_p__parameterized37_7808 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_lq_credit_ok_latch | tri_rlmreg_p__parameterized37_7809 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_pc_sq_credit_ok_latch | tri_rlmreg_p__parameterized37_7810 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_credits_returned_latch | tri_rlmlatch_p_7811 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ivax_hold_req_latch | tri_rlmreg_p__parameterized37_7812 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | low_pri_counts.thread_latches[0].low_pri_cnt_latch | tri_rlmreg_p__parameterized12_7813 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | low_pri_counts.thread_latches[0].low_pri_max_latch | tri_rlmreg_p__parameterized0_7814 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | low_pri_mask_latch | tri_rlmreg_p__parameterized37_7815 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_cmdq_total_cnt_latch | tri_rlmreg_p__parameterized179_7816 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | med_pri_mask_latch | tri_rlmreg_p__parameterized37_7817 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_hold_done_latch | tri_rlmreg_p__parameterized37_7818 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_hold_req_latch | tri_rlmreg_p__parameterized37_7819 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_iu_bus_snoop_hold_req_latch | tri_rlmreg_p__parameterized37_7820 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_iu_flush_req_latch | tri_rlmreg_p__parameterized37_7821 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_iu_hold_done_latch | tri_rlmreg_p__parameterized37_7822 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | sq_cmdq_total_cnt_latch | tri_rlmreg_p__parameterized175_7823 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | total_pri_mask_latch | tri_rlmreg_p__parameterized37_7824 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.thread_latches[0].fu0_med_credit_cnt_latch | tri_rlmreg_p__parameterized169_7825 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl7.thread_latches[0].fu1_med_credit_cnt_latch | tri_rlmreg_p__parameterized4_7826 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl7.thread_latches[0].fx0_med_credit_cnt_latch | tri_rlmreg_p__parameterized169_7827 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl7.thread_latches[0].fx1_med_credit_cnt_latch | tri_rlmreg_p__parameterized169_7828 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl7.thread_latches[0].lq_cmdq_med_cnt_latch | tri_rlmreg_p__parameterized171_7829 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl7.thread_latches[0].sq_cmdq_med_cnt_latch | tri_rlmreg_p__parameterized169_7830 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | slice0 | iuq_slice | 21069 | 21069 | 0 | 0 | 6333 | 0 | 0 | 0 | | dec_top0 | iuq_dec_top | 3197 | 3197 | 0 | 0 | 451 | 0 | 0 | 0 | | (dec_top0) | iuq_dec_top | 430 | 430 | 0 | 0 | 0 | 0 | 0 | 0 | | axu_dec0 | iuq_axu_fu_dec | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | config_reg | tri_rlmreg_p__parameterized12_7793 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | axu_dec1 | iuq_axu_fu_dec_7677 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | config_reg | tri_rlmreg_p__parameterized12_7792 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx_dec0 | iuq_idec | 677 | 677 | 0 | 0 | 222 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7735 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_2ucode | tri_rlmlatch_p_7736 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_async_block | tri_rlmlatch_p_7737 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bh0_hist | tri_rlmreg_p__parameterized2_7738 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_bh1_hist | tri_rlmreg_p__parameterized2_7739 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_bh2_hist | tri_rlmreg_p__parameterized2_7740 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bh_update | tri_rlmlatch_p_7741 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_br_pred | tri_rlmlatch_p_7742 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bta | tri_rlmreg_p__parameterized8_7743 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_bta_val | tri_rlmlatch_p_7744 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_btb_entry | tri_rlmlatch_p_7745 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_cord | tri_rlmlatch_p_7746 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_core_block | tri_rlmlatch_p_7747 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_error | tri_rlmreg_p__parameterized5_7748 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_fuse_nop | tri_rlmlatch_p_7749 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_fusion | tri_rlmreg_p__parameterized8_7750 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_gshare | tri_rlmreg_p__parameterized14_7751 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | iu5_ifar | tri_rlmreg_p__parameterized8_7752 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ilat | tri_rlmreg_p__parameterized9_7753 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_instr | tri_rlmreg_p__parameterized17_7754 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | iu5_isload | tri_rlmlatch_p_7755 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_isram | tri_rlmlatch_p_7756 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_isstore | tri_rlmlatch_p_7757 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ls_ptr | tri_rlmreg_p__parameterized5_7758 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_match | tri_rlmlatch_p_7759 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_np1_flush | tri_rlmlatch_p_7760 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ord | tri_rlmlatch_p_7761 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_axu0 | tri_rlmlatch_p_7762 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_fx0 | tri_rlmlatch_p_7763 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_fx1 | tri_rlmlatch_p_7764 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_lq | tri_rlmlatch_p_7765 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_sq | tri_rlmlatch_p_7766 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s1_a | tri_rlmreg_p__parameterized0_7767 | 86 | 86 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_s1_t | tri_rlmreg_p__parameterized5_7768 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s1_v | tri_rlmlatch_p_7769 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s2_a | tri_rlmreg_p__parameterized0_7770 | 86 | 86 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_s2_t | tri_rlmreg_p__parameterized5_7771 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s2_v | tri_rlmlatch_p_7772 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s3_a | tri_rlmreg_p__parameterized0_7773 | 86 | 86 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_s3_t | tri_rlmreg_p__parameterized5_7774 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s3_v | tri_rlmlatch_p_7775 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_spec | tri_rlmlatch_p_7776 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t1_a | tri_rlmreg_p__parameterized0_7777 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | iu5_t1_t | tri_rlmreg_p__parameterized5_7778 | 270 | 270 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t1_v | tri_rlmlatch_p_7779 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t2_a | tri_rlmreg_p__parameterized0_7780 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | iu5_t2_t | tri_rlmreg_p__parameterized5_7781 | 77 | 77 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t2_v | tri_rlmlatch_p_7782 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t3_a | tri_rlmreg_p__parameterized0_7783 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t3_t | tri_rlmreg_p__parameterized5_7784 | 14 | 14 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_t3_v | tri_rlmlatch_p_7785 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_type_fp | tri_rlmlatch_p_7786 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_type_st | tri_rlmlatch_p_7787 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ucode | tri_rlmreg_p__parameterized5_7788 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_valop | tri_rlmlatch_p_7789 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_vld | tri_rlmlatch_p_7790 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_ucode_dis_latch | tri_rlmlatch_p_7791 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx_dec1 | iuq_idec_7678 | 2090 | 2090 | 0 | 0 | 227 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7679 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_async_block | tri_rlmlatch_p_7680 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bh0_hist | tri_rlmreg_p__parameterized2_7681 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_bh1_hist | tri_rlmreg_p__parameterized2_7682 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_bh2_hist | tri_rlmreg_p__parameterized2_7683 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bh_update | tri_rlmlatch_p_7684 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_br_pred | tri_rlmlatch_p_7685 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_bta | tri_rlmreg_p__parameterized8_7686 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_bta_val | tri_rlmlatch_p_7687 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_btb_entry | tri_rlmlatch_p_7688 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_cord | tri_rlmlatch_p_7689 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_core_block | tri_rlmlatch_p_7690 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_error | tri_rlmreg_p__parameterized5_7691 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_fuse_nop | tri_rlmlatch_p_7692 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_fusion | tri_rlmreg_p__parameterized8_7693 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_gshare | tri_rlmreg_p__parameterized14_7694 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | iu5_ifar | tri_rlmreg_p__parameterized8_7695 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | iu5_ilat | tri_rlmreg_p__parameterized9_7696 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_instr | tri_rlmreg_p__parameterized17_7697 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | iu5_isload | tri_rlmlatch_p_7698 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_isram | tri_rlmlatch_p_7699 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_isstore | tri_rlmlatch_p_7700 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ls_ptr | tri_rlmreg_p__parameterized5_7701 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_match | tri_rlmlatch_p_7702 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_np1_flush | tri_rlmlatch_p_7703 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ord | tri_rlmlatch_p_7704 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_axu0 | tri_rlmlatch_p_7705 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_fx0 | tri_rlmlatch_p_7706 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_fx1 | tri_rlmlatch_p_7707 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_lq | tri_rlmlatch_p_7708 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_rte_sq | tri_rlmlatch_p_7709 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s1_a | tri_rlmreg_p__parameterized0_7710 | 103 | 103 | 0 | 0 | 8 | 0 | 0 | 0 | | iu5_s1_t | tri_rlmreg_p__parameterized5_7711 | 44 | 44 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s1_v | tri_rlmlatch_p_7712 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s2_a | tri_rlmreg_p__parameterized0_7713 | 104 | 104 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_s2_t | tri_rlmreg_p__parameterized5_7714 | 44 | 44 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s2_v | tri_rlmlatch_p_7715 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_s3_a | tri_rlmreg_p__parameterized0_7716 | 106 | 106 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_s3_t | tri_rlmreg_p__parameterized5_7717 | 42 | 42 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_s3_v | tri_rlmlatch_p_7718 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_spec | tri_rlmlatch_p_7719 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t1_a | tri_rlmreg_p__parameterized0_7720 | 262 | 262 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_t1_t | tri_rlmreg_p__parameterized5_7721 | 462 | 462 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t1_v | tri_rlmlatch_p_7722 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t2_a | tri_rlmreg_p__parameterized0_7723 | 300 | 300 | 0 | 0 | 10 | 0 | 0 | 0 | | iu5_t2_t | tri_rlmreg_p__parameterized5_7724 | 473 | 473 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t2_v | tri_rlmlatch_p_7725 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_t3_a | tri_rlmreg_p__parameterized0_7726 | 62 | 62 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_t3_t | tri_rlmreg_p__parameterized5_7727 | 23 | 23 | 0 | 0 | 2 | 0 | 0 | 0 | | iu5_t3_v | tri_rlmlatch_p_7728 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_type_fp | tri_rlmlatch_p_7729 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_type_st | tri_rlmlatch_p_7730 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_ucode | tri_rlmreg_p__parameterized5_7731 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu5_valop | tri_rlmlatch_p_7732 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu5_vld | tri_rlmlatch_p_7733 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_ucode_dis_latch | tri_rlmlatch_p_7734 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_ibuf0 | iuq_ibuf | 9973 | 9973 | 0 | 0 | 2338 | 0 | 0 | 0 | | br_iu_redirect_latch | tri_rlmlatch_p_7651 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | buffer_array_latch | tri_rlmreg_p__parameterized63 | 21 | 21 | 0 | 0 | 1728 | 0 | 0 | 0 | | buffer_head_latch | tri_rlmreg_p__parameterized62 | 1145 | 1145 | 0 | 0 | 31 | 0 | 0 | 0 | | buffer_tail_latch | tri_rlmreg_p__parameterized62_7652 | 2219 | 2219 | 0 | 0 | 34 | 0 | 0 | 0 | | buffer_valid_latch | tri_rlmreg_p__parameterized3_7653 | 62 | 62 | 0 | 0 | 17 | 0 | 0 | 0 | | cp_flush_into_uc_latch | tri_rlmreg_p__parameterized2_7654 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7655 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_0_bta_latch | tri_rlmreg_p__parameterized8_7656 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_0_fuse_data_latch | tri_rlmreg_p__parameterized17_7657 | 34 | 34 | 0 | 0 | 31 | 0 | 0 | 0 | | iu4_0_fuse_val_latch | tri_rlmlatch_p_7658 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_0_ifar_latch | tri_rlmreg_p__parameterized8_7659 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_0_instr_latch | tri_rlmreg_p__parameterized65_7660 | 904 | 904 | 0 | 0 | 67 | 0 | 0 | 0 | | iu4_0_isram_latch | tri_rlmlatch_p_7661 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_0_ucode_ext_latch | tri_rlmreg_p__parameterized9_7662 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_0_ucode_latch | tri_rlmreg_p__parameterized5_7663 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | iu4_0_valid_latch | tri_rlmlatch_p_7664 | 14 | 14 | 0 | 0 | 2 | 0 | 0 | 0 | | iu4_1_bta_latch | tri_rlmreg_p__parameterized8_7665 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_1_fuse_data_latch | tri_rlmreg_p__parameterized17_7666 | 33 | 33 | 0 | 0 | 31 | 0 | 0 | 0 | | iu4_1_fuse_val_latch | tri_rlmlatch_p_7667 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu4_1_ifar_latch | tri_rlmreg_p__parameterized8_7668 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | iu4_1_instr_latch | tri_rlmreg_p__parameterized65_7669 | 849 | 849 | 0 | 0 | 66 | 0 | 0 | 0 | | iu4_1_ucode_ext_latch | tri_rlmreg_p__parameterized9_7670 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu4_1_ucode_latch | tri_rlmreg_p__parameterized5_7671 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iu4_1_valid_latch | tri_rlmlatch_p_7672 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | iu4_uc_mode_latch | tri_rlmreg_p__parameterized2_7673 | 287 | 287 | 0 | 0 | 2 | 0 | 0 | 0 | | stall_buffer_data0_latch | tri_rlmreg_p__parameterized64 | 41 | 41 | 0 | 0 | 108 | 0 | 0 | 0 | | stall_buffer_data1_latch | tri_rlmreg_p__parameterized64_7674 | 155 | 155 | 0 | 0 | 108 | 0 | 0 | 0 | | stall_latch | tri_rlmreg_p__parameterized2_7675 | 4089 | 4089 | 0 | 0 | 8 | 0 | 0 | 0 | | uc_select_latch | tri_rlmlatch_p_7676 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rn_top0 | iuq_rn_top | 7900 | 7900 | 0 | 0 | 3544 | 0 | 0 | 0 | | axu_rn0 | iuq_axu_fu_rn | 2574 | 2574 | 0 | 0 | 1079 | 0 | 0 | 0 | | br_iu_hold_latch | tri_rlmlatch_p_7473 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7474 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | fpr_rn_map | iuq_rn_map_7475 | 2184 | 2184 | 0 | 0 | 884 | 0 | 0 | 0 | | (fpr_rn_map) | iuq_rn_map_7475 | 729 | 729 | 0 | 0 | 0 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized93_7508 | 17 | 17 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized0_7509 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7510 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized0_7511 | 258 | 258 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7512 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized0_7513 | 154 | 154 | 0 | 0 | 6 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized0_7514 | 120 | 120 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized0_7515 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[10].comp_map_latch | tri_rlmreg_p__parameterized75_7516 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[11].comp_map_latch | tri_rlmreg_p__parameterized76_7517 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[12].comp_map_latch | tri_rlmreg_p__parameterized77_7518 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[13].comp_map_latch | tri_rlmreg_p__parameterized78_7519 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[14].comp_map_latch | tri_rlmreg_p__parameterized79_7520 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[15].comp_map_latch | tri_rlmreg_p__parameterized80_7521 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[16].comp_map_latch | tri_rlmreg_p__parameterized81_7522 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[17].comp_map_latch | tri_rlmreg_p__parameterized82_7523 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[18].comp_map_latch | tri_rlmreg_p__parameterized83_7524 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[19].comp_map_latch | tri_rlmreg_p__parameterized84_7525 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[1].comp_map_latch | tri_rlmreg_p__parameterized66_7526 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[20].comp_map_latch | tri_rlmreg_p__parameterized85_7527 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[21].comp_map_latch | tri_rlmreg_p__parameterized86_7528 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[22].comp_map_latch | tri_rlmreg_p__parameterized87_7529 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[23].comp_map_latch | tri_rlmreg_p__parameterized88_7530 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[24].comp_map_latch | tri_rlmreg_p__parameterized89_7531 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[25].comp_map_latch | tri_rlmreg_p__parameterized90_7532 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[26].comp_map_latch | tri_rlmreg_p__parameterized91_7533 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[27].comp_map_latch | tri_rlmreg_p__parameterized92_7534 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[28].comp_map_latch | tri_rlmreg_p__parameterized93_7535 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[29].comp_map_latch | tri_rlmreg_p__parameterized94_7536 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[2].comp_map_latch | tri_rlmreg_p__parameterized67_7537 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[30].comp_map_latch | tri_rlmreg_p__parameterized95_7538 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[31].comp_map_latch | tri_rlmreg_p__parameterized96_7539 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[32].comp_map_latch | tri_rlmreg_p__parameterized97_7540 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[33].comp_map_latch | tri_rlmreg_p__parameterized98_7541 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[34].comp_map_latch | tri_rlmreg_p__parameterized99_7542 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[35].comp_map_latch | tri_rlmreg_p__parameterized100_7543 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[3].comp_map_latch | tri_rlmreg_p__parameterized68_7544 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[4].comp_map_latch | tri_rlmreg_p__parameterized69_7545 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[5].comp_map_latch | tri_rlmreg_p__parameterized70_7546 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[6].comp_map_latch | tri_rlmreg_p__parameterized71_7547 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[7].comp_map_latch | tri_rlmreg_p__parameterized72_7548 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[8].comp_map_latch | tri_rlmreg_p__parameterized73_7549 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[9].comp_map_latch | tri_rlmreg_p__parameterized74_7550 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized0_7551 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7552 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[10].spec_map_arc_latch | tri_rlmreg_p__parameterized75_7553 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[10].spec_map_itag_latch | tri_rlmreg_p__parameterized110_7554 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[11].spec_map_arc_latch | tri_rlmreg_p__parameterized76_7555 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[11].spec_map_itag_latch | tri_rlmreg_p__parameterized111_7556 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[12].spec_map_arc_latch | tri_rlmreg_p__parameterized77_7557 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[12].spec_map_itag_latch | tri_rlmreg_p__parameterized112_7558 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[13].spec_map_arc_latch | tri_rlmreg_p__parameterized78_7559 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[13].spec_map_itag_latch | tri_rlmreg_p__parameterized113_7560 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[14].spec_map_arc_latch | tri_rlmreg_p__parameterized79_7561 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[14].spec_map_itag_latch | tri_rlmreg_p__parameterized114_7562 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[15].spec_map_arc_latch | tri_rlmreg_p__parameterized80_7563 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[15].spec_map_itag_latch | tri_rlmreg_p__parameterized115_7564 | 45 | 45 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[16].spec_map_arc_latch | tri_rlmreg_p__parameterized81_7565 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[16].spec_map_itag_latch | tri_rlmreg_p__parameterized116_7566 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[17].spec_map_arc_latch | tri_rlmreg_p__parameterized82_7567 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[17].spec_map_itag_latch | tri_rlmreg_p__parameterized117_7568 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[18].spec_map_arc_latch | tri_rlmreg_p__parameterized83_7569 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[18].spec_map_itag_latch | tri_rlmreg_p__parameterized118_7570 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[19].spec_map_arc_latch | tri_rlmreg_p__parameterized84_7571 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[19].spec_map_itag_latch | tri_rlmreg_p__parameterized119_7572 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_arc_latch | tri_rlmreg_p__parameterized66_7573 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_itag_latch | tri_rlmreg_p__parameterized101_7574 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[20].spec_map_arc_latch | tri_rlmreg_p__parameterized85_7575 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[20].spec_map_itag_latch | tri_rlmreg_p__parameterized120_7576 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[21].spec_map_arc_latch | tri_rlmreg_p__parameterized86_7577 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[21].spec_map_itag_latch | tri_rlmreg_p__parameterized121_7578 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[22].spec_map_arc_latch | tri_rlmreg_p__parameterized87_7579 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[22].spec_map_itag_latch | tri_rlmreg_p__parameterized122_7580 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[23].spec_map_arc_latch | tri_rlmreg_p__parameterized88_7581 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[23].spec_map_itag_latch | tri_rlmreg_p__parameterized123_7582 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[24].spec_map_arc_latch | tri_rlmreg_p__parameterized89_7583 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[24].spec_map_itag_latch | tri_rlmreg_p__parameterized124_7584 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[25].spec_map_arc_latch | tri_rlmreg_p__parameterized90_7585 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[25].spec_map_itag_latch | tri_rlmreg_p__parameterized125_7586 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[26].spec_map_arc_latch | tri_rlmreg_p__parameterized91_7587 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[26].spec_map_itag_latch | tri_rlmreg_p__parameterized126_7588 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[27].spec_map_arc_latch | tri_rlmreg_p__parameterized92_7589 | 72 | 72 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[27].spec_map_itag_latch | tri_rlmreg_p__parameterized127_7590 | 85 | 85 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[28].spec_map_arc_latch | tri_rlmreg_p__parameterized93_7591 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[28].spec_map_itag_latch | tri_rlmreg_p__parameterized128_7592 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[29].spec_map_arc_latch | tri_rlmreg_p__parameterized94_7593 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[29].spec_map_itag_latch | tri_rlmreg_p__parameterized129_7594 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_arc_latch | tri_rlmreg_p__parameterized67_7595 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_itag_latch | tri_rlmreg_p__parameterized102_7596 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[30].spec_map_arc_latch | tri_rlmreg_p__parameterized95_7597 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[30].spec_map_itag_latch | tri_rlmreg_p__parameterized130_7598 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[31].spec_map_arc_latch | tri_rlmreg_p__parameterized96_7599 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[31].spec_map_itag_latch | tri_rlmreg_p__parameterized131_7600 | 45 | 45 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[32].spec_map_arc_latch | tri_rlmreg_p__parameterized97_7601 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[32].spec_map_itag_latch | tri_rlmreg_p__parameterized132_7602 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[33].spec_map_arc_latch | tri_rlmreg_p__parameterized98_7603 | 18 | 18 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[33].spec_map_itag_latch | tri_rlmreg_p__parameterized133_7604 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[34].spec_map_arc_latch | tri_rlmreg_p__parameterized99_7605 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[34].spec_map_itag_latch | tri_rlmreg_p__parameterized134_7606 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[35].spec_map_arc_latch | tri_rlmreg_p__parameterized100_7607 | 18 | 18 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[35].spec_map_itag_latch | tri_rlmreg_p__parameterized135_7608 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_arc_latch | tri_rlmreg_p__parameterized68_7609 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_itag_latch | tri_rlmreg_p__parameterized103_7610 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_arc_latch | tri_rlmreg_p__parameterized69_7611 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_itag_latch | tri_rlmreg_p__parameterized104_7612 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_arc_latch | tri_rlmreg_p__parameterized70_7613 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_itag_latch | tri_rlmreg_p__parameterized105_7614 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_arc_latch | tri_rlmreg_p__parameterized71_7615 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_itag_latch | tri_rlmreg_p__parameterized106_7616 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_arc_latch | tri_rlmreg_p__parameterized72_7617 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_itag_latch | tri_rlmreg_p__parameterized107_7618 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_arc_latch | tri_rlmreg_p__parameterized73_7619 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_itag_latch | tri_rlmreg_p__parameterized108_7620 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[9].spec_map_arc_latch | tri_rlmreg_p__parameterized74_7621 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[9].spec_map_itag_latch | tri_rlmreg_p__parameterized109_7622 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized136_7623 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[10].buffer_pool_latch0 | tri_rlmreg_p__parameterized146_7624 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[11].buffer_pool_latch0 | tri_rlmreg_p__parameterized147_7625 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[12].buffer_pool_latch0 | tri_rlmreg_p__parameterized148_7626 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[13].buffer_pool_latch0 | tri_rlmreg_p__parameterized149_7627 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[14].buffer_pool_latch0 | tri_rlmreg_p__parameterized150_7628 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[15].buffer_pool_latch0 | tri_rlmreg_p__parameterized151_7629 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[16].buffer_pool_latch0 | tri_rlmreg_p__parameterized152_7630 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[17].buffer_pool_latch0 | tri_rlmreg_p__parameterized153_7631 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[18].buffer_pool_latch0 | tri_rlmreg_p__parameterized154_7632 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[19].buffer_pool_latch0 | tri_rlmreg_p__parameterized155_7633 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized137_7634 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[20].buffer_pool_latch0 | tri_rlmreg_p__parameterized156_7635 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[21].buffer_pool_latch0 | tri_rlmreg_p__parameterized157_7636 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[22].buffer_pool_latch0 | tri_rlmreg_p__parameterized158_7637 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[23].buffer_pool_latch0 | tri_rlmreg_p__parameterized159_7638 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[24].buffer_pool_latch0 | tri_rlmreg_p__parameterized160_7639 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[25].buffer_pool_latch0 | tri_rlmreg_p__parameterized161_7640 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[26].buffer_pool_latch0 | tri_rlmreg_p__parameterized162_7641 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[27].buffer_pool_latch0 | tri_rlmreg_p__parameterized163_7642 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized138_7643 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized139_7644 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized140_7645 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized141_7646 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized142_7647 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[7].buffer_pool_latch0 | tri_rlmreg_p__parameterized143_7648 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[8].buffer_pool_latch0 | tri_rlmreg_p__parameterized144_7649 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[9].buffer_pool_latch0 | tri_rlmreg_p__parameterized145_7650 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | fpscr_rn_map | iuq_rn_map__parameterized4 | 387 | 387 | 0 | 0 | 187 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized212 | 39 | 39 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized4_7476 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7477 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized4_7478 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7479 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized4_7480 | 91 | 91 | 0 | 0 | 5 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized4_7481 | 255 | 255 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized4_7482 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized164_7483 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[10].buffer_pool_latch0 | tri_rlmreg_p__parameterized174_7484 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[11].buffer_pool_latch0 | tri_rlmreg_p__parameterized175_7485 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[12].buffer_pool_latch0 | tri_rlmreg_p__parameterized176_7486 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[13].buffer_pool_latch0 | tri_rlmreg_p__parameterized177_7487 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[14].buffer_pool_latch0 | tri_rlmreg_p__parameterized178_7488 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[15].buffer_pool_latch0 | tri_rlmreg_p__parameterized179_7489 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[16].buffer_pool_latch0 | tri_rlmreg_p__parameterized180_7490 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[17].buffer_pool_latch0 | tri_rlmreg_p__parameterized181_7491 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[18].buffer_pool_latch0 | tri_rlmreg_p__parameterized182_7492 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[19].buffer_pool_latch0 | tri_rlmreg_p__parameterized183_7493 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized165_7494 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[20].buffer_pool_latch0 | tri_rlmreg_p__parameterized184_7495 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[21].buffer_pool_latch0 | tri_rlmreg_p__parameterized185_7496 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[22].buffer_pool_latch0 | tri_rlmreg_p__parameterized186_7497 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[23].buffer_pool_latch0 | tri_rlmreg_p__parameterized205 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[24].buffer_pool_latch0 | tri_rlmreg_p__parameterized206 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[25].buffer_pool_latch0 | tri_rlmreg_p__parameterized207 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[26].buffer_pool_latch0 | tri_rlmreg_p__parameterized208 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[27].buffer_pool_latch0 | tri_rlmreg_p__parameterized209 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[28].buffer_pool_latch0 | tri_rlmreg_p__parameterized210_7498 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[29].buffer_pool_latch0 | tri_rlmreg_p__parameterized211 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized166_7499 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[30].buffer_pool_latch0 | tri_rlmreg_p__parameterized212_7500 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized167_7501 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized168_7502 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized169_7503 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized170_7504 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[7].buffer_pool_latch0 | tri_rlmreg_p__parameterized171_7505 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[8].buffer_pool_latch0 | tri_rlmreg_p__parameterized172_7506 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[9].buffer_pool_latch0 | tri_rlmreg_p__parameterized173_7507 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | fx_rn0 | iuq_rn | 5326 | 5326 | 0 | 0 | 2465 | 0 | 0 | 0 | | br_iu_hold_latch | tri_rlmlatch_p_7076 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_into_uc_latch | tri_rlmlatch_p_7077 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmlatch_p_7078 | 20 | 20 | 0 | 0 | 11 | 0 | 0 | 0 | | cp_high_credit_cnt_latch | tri_rlmreg_p__parameterized132 | 59 | 59 | 0 | 0 | 7 | 0 | 0 | 0 | | cp_med_credit_cnt_latch | tri_rlmreg_p__parameterized116 | 57 | 57 | 0 | 0 | 7 | 0 | 0 | 0 | | cp_rn_empty_latch | tri_rlmlatch_p_7079 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cr_rn_map | iuq_rn_map__parameterized0 | 556 | 556 | 0 | 0 | 255 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized178 | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized4_7446 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7447 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized4_7448 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7449 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized4_7450 | 163 | 163 | 0 | 0 | 5 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized4_7451 | 179 | 179 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized4_7452 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[1].comp_map_latch | tri_rlmreg_p__parameterized164_7453 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[2].comp_map_latch | tri_rlmreg_p__parameterized165 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[3].comp_map_latch | tri_rlmreg_p__parameterized166 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[4].comp_map_latch | tri_rlmreg_p__parameterized167 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[5].comp_map_latch | tri_rlmreg_p__parameterized168 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[6].comp_map_latch | tri_rlmreg_p__parameterized169 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[7].comp_map_latch | tri_rlmreg_p__parameterized170 | 4 | 4 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl3.comp_map0[8].comp_map_latch | tri_rlmreg_p__parameterized171 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized4_7454 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7455 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_arc_latch | tri_rlmreg_p__parameterized164_7456 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_itag_latch | tri_rlmreg_p__parameterized101_7457 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_arc_latch | tri_rlmreg_p__parameterized165_7458 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_itag_latch | tri_rlmreg_p__parameterized102_7459 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_arc_latch | tri_rlmreg_p__parameterized166_7460 | 30 | 30 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_itag_latch | tri_rlmreg_p__parameterized103_7461 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_arc_latch | tri_rlmreg_p__parameterized167_7462 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_itag_latch | tri_rlmreg_p__parameterized104_7463 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_arc_latch | tri_rlmreg_p__parameterized168_7464 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_itag_latch | tri_rlmreg_p__parameterized105_7465 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_arc_latch | tri_rlmreg_p__parameterized169_7466 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_itag_latch | tri_rlmreg_p__parameterized106_7467 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_arc_latch | tri_rlmreg_p__parameterized170_7468 | 30 | 30 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_itag_latch | tri_rlmreg_p__parameterized107_7469 | 45 | 45 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_arc_latch | tri_rlmreg_p__parameterized171_7470 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_itag_latch | tri_rlmreg_p__parameterized108_7471 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized172 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[10].buffer_pool_latch0 | tri_rlmreg_p__parameterized182 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[11].buffer_pool_latch0 | tri_rlmreg_p__parameterized183 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[12].buffer_pool_latch0 | tri_rlmreg_p__parameterized184 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[13].buffer_pool_latch0 | tri_rlmreg_p__parameterized185 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[14].buffer_pool_latch0 | tri_rlmreg_p__parameterized186 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized173 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized174 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized175 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized176 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized177 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized178_7472 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[7].buffer_pool_latch0 | tri_rlmreg_p__parameterized179 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[8].buffer_pool_latch0 | tri_rlmreg_p__parameterized180 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[9].buffer_pool_latch0 | tri_rlmreg_p__parameterized181 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ctr_rn_map | iuq_rn_map__parameterized2 | 114 | 114 | 0 | 0 | 51 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized192_7429 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized5_7430 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7431 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized5_7432 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7433 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized5_7434 | 32 | 32 | 0 | 0 | 3 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized5_7435 | 61 | 61 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized5_7436 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized5_7437 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7438 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized187_7439 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized188_7440 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized28_7441 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized189_7442 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized190_7443 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized191_7444 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized192_7445 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | fdis_frn_iu6_stall_latch | tri_rlmreg_p__parameterized204_7080 | 5 | 5 | 0 | 0 | 26 | 0 | 0 | 0 | | frn_fdis_iu6_i0_2ucode_latch | tri_rlmlatch_p_7081 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_async_block_latch | tri_rlmlatch_p_7082 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bh0_hist_latch | tri_rlmreg_p__parameterized2_7083 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bh1_hist_latch | tri_rlmreg_p__parameterized2_7084 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bh2_hist_latch | tri_rlmreg_p__parameterized2_7085 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bh_update_latch | tri_rlmlatch_p_7086 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_br_pred_latch | tri_rlmlatch_p_7087 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bta_latch | tri_rlmreg_p__parameterized8_7088 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i0_bta_val_latch | tri_rlmlatch_p_7089 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_btb_entry_latch | tri_rlmlatch_p_7090 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_cord_latch | tri_rlmlatch_p_7091 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_core_block_latch | tri_rlmlatch_p_7092 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_error_latch | tri_rlmreg_p__parameterized5_7093 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_fuse_nop_latch | tri_rlmlatch_p_7094 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_fusion_latch | tri_rlmreg_p__parameterized8_7095 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i0_gshare_latch | tri_rlmreg_p__parameterized14_7096 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ifar_latch | tri_rlmreg_p__parameterized8_7097 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ilat_latch | tri_rlmreg_p__parameterized9_7098 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | frn_fdis_iu6_i0_instr_latch | tri_rlmreg_p__parameterized17_7099 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | frn_fdis_iu6_i0_isload_latch | tri_rlmlatch_p_7100 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_isram_latch | tri_rlmlatch_p_7101 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_isstore_latch | tri_rlmlatch_p_7102 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_itag_latch | tri_rlmreg_p__parameterized13_7103 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ls_ptr_latch | tri_rlmreg_p__parameterized5_7104 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_match_latch | tri_rlmlatch_p_7105 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_np1_flush_latch | tri_rlmlatch_p_7106 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ord_latch | tri_rlmlatch_p_7107 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_axu0_latch | tri_rlmlatch_p_7108 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_axu1_latch | tri_rlmlatch_p_7109 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_fx0_latch | tri_rlmlatch_p_7110 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_fx1_latch | tri_rlmlatch_p_7111 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_lq_latch | tri_rlmlatch_p_7112 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_rte_sq_latch | tri_rlmlatch_p_7113 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s1_itag_latch | tri_rlmreg_p__parameterized13_7114 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s1_p_latch | tri_rlmreg_p__parameterized0_7115 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s1_t_latch | tri_rlmreg_p__parameterized5_7116 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s1_v_latch | tri_rlmlatch_p_7117 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s2_itag_latch | tri_rlmreg_p__parameterized13_7118 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s2_p_latch | tri_rlmreg_p__parameterized0_7119 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s2_t_latch | tri_rlmreg_p__parameterized5_7120 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s2_v_latch | tri_rlmlatch_p_7121 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s3_itag_latch | tri_rlmreg_p__parameterized13_7122 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s3_p_latch | tri_rlmreg_p__parameterized0_7123 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s3_t_latch | tri_rlmreg_p__parameterized5_7124 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_s3_v_latch | tri_rlmlatch_p_7125 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_spec_latch | tri_rlmlatch_p_7126 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t1_a_latch | tri_rlmreg_p__parameterized0_7127 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t1_p_latch | tri_rlmreg_p__parameterized0_7128 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t1_t_latch | tri_rlmreg_p__parameterized5_7129 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t1_v_latch | tri_rlmlatch_p_7130 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t2_a_latch | tri_rlmreg_p__parameterized0_7131 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t2_p_latch | tri_rlmreg_p__parameterized0_7132 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t2_t_latch | tri_rlmreg_p__parameterized5_7133 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t2_v_latch | tri_rlmlatch_p_7134 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t3_a_latch | tri_rlmreg_p__parameterized0_7135 | 9 | 9 | 0 | 0 | 5 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t3_p_latch | tri_rlmreg_p__parameterized0_7136 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t3_t_latch | tri_rlmreg_p__parameterized5_7137 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_t3_v_latch | tri_rlmlatch_p_7138 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_type_ap_latch | tri_rlmlatch_p_7139 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_type_fp_latch | tri_rlmlatch_p_7140 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_type_spv_latch | tri_rlmlatch_p_7141 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_type_st_latch | tri_rlmlatch_p_7142 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ucode_cnt_latch | tri_rlmreg_p__parameterized5_7143 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_ucode_latch | tri_rlmreg_p__parameterized5_7144 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i0_valop_latch | tri_rlmlatch_p_7145 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i0_vld_latch | tri_rlmlatch_p_7146 | 33 | 33 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_async_block_latch | tri_rlmlatch_p_7147 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bh0_hist_latch | tri_rlmreg_p__parameterized2_7148 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bh1_hist_latch | tri_rlmreg_p__parameterized2_7149 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bh2_hist_latch | tri_rlmreg_p__parameterized2_7150 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bh_update_latch | tri_rlmlatch_p_7151 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_br_pred_latch | tri_rlmlatch_p_7152 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bta_latch | tri_rlmreg_p__parameterized8_7153 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i1_bta_val_latch | tri_rlmlatch_p_7154 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_btb_entry_latch | tri_rlmlatch_p_7155 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_cord_latch | tri_rlmlatch_p_7156 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_core_block_latch | tri_rlmlatch_p_7157 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_error_latch | tri_rlmreg_p__parameterized5_7158 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_fuse_nop_latch | tri_rlmlatch_p_7159 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_fusion_latch | tri_rlmreg_p__parameterized8_7160 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i1_gshare_latch | tri_rlmreg_p__parameterized14_7161 | 36 | 36 | 0 | 0 | 18 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ifar_latch | tri_rlmreg_p__parameterized8_7162 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ilat_latch | tri_rlmreg_p__parameterized9_7163 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | frn_fdis_iu6_i1_instr_latch | tri_rlmreg_p__parameterized17_7164 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | frn_fdis_iu6_i1_isload_latch | tri_rlmlatch_p_7165 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_isram_latch | tri_rlmlatch_p_7166 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_isstore_latch | tri_rlmlatch_p_7167 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_itag_latch | tri_rlmreg_p__parameterized13_7168 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ls_ptr_latch | tri_rlmreg_p__parameterized5_7169 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_match_latch | tri_rlmlatch_p_7170 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_np1_flush_latch | tri_rlmlatch_p_7171 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ord_latch | tri_rlmlatch_p_7172 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_rte_axu0_latch | tri_rlmlatch_p_7173 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_rte_fx0_latch | tri_rlmlatch_p_7174 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_rte_fx1_latch | tri_rlmlatch_p_7175 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_rte_lq_latch | tri_rlmlatch_p_7176 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_rte_sq_latch | tri_rlmlatch_p_7177 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s1_dep_hit_latch | tri_rlmlatch_p_7178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s1_itag_latch | tri_rlmreg_p__parameterized13_7179 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s1_p_latch | tri_rlmreg_p__parameterized0_7180 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s1_t_latch | tri_rlmreg_p__parameterized5_7181 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s1_v_latch | tri_rlmlatch_p_7182 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s2_dep_hit_latch | tri_rlmlatch_p_7183 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s2_itag_latch | tri_rlmreg_p__parameterized13_7184 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s2_p_latch | tri_rlmreg_p__parameterized0_7185 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s2_t_latch | tri_rlmreg_p__parameterized5_7186 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s2_v_latch | tri_rlmlatch_p_7187 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s3_dep_hit_latch | tri_rlmlatch_p_7188 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s3_itag_latch | tri_rlmreg_p__parameterized13_7189 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s3_p_latch | tri_rlmreg_p__parameterized0_7190 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s3_t_latch | tri_rlmreg_p__parameterized5_7191 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_s3_v_latch | tri_rlmlatch_p_7192 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_spec_latch | tri_rlmlatch_p_7193 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t1_a_latch | tri_rlmreg_p__parameterized0_7194 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t1_p_latch | tri_rlmreg_p__parameterized0_7195 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t1_t_latch | tri_rlmreg_p__parameterized5_7196 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t1_v_latch | tri_rlmlatch_p_7197 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t2_a_latch | tri_rlmreg_p__parameterized0_7198 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t2_p_latch | tri_rlmreg_p__parameterized0_7199 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t2_t_latch | tri_rlmreg_p__parameterized5_7200 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t2_v_latch | tri_rlmlatch_p_7201 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t3_a_latch | tri_rlmreg_p__parameterized0_7202 | 9 | 9 | 0 | 0 | 5 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t3_p_latch | tri_rlmreg_p__parameterized0_7203 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t3_t_latch | tri_rlmreg_p__parameterized5_7204 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_t3_v_latch | tri_rlmlatch_p_7205 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_type_ap_latch | tri_rlmlatch_p_7206 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_type_fp_latch | tri_rlmlatch_p_7207 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_type_spv_latch | tri_rlmlatch_p_7208 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_type_st_latch | tri_rlmlatch_p_7209 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ucode_cnt_latch | tri_rlmreg_p__parameterized5_7210 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_ucode_latch | tri_rlmreg_p__parameterized5_7211 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | frn_fdis_iu6_i1_valop_latch | tri_rlmlatch_p_7212 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | frn_fdis_iu6_i1_vld_latch | tri_rlmlatch_p_7213 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gpr_rn_map | iuq_rn_map | 2190 | 2190 | 0 | 0 | 884 | 0 | 0 | 0 | | (gpr_rn_map) | iuq_rn_map | 733 | 733 | 0 | 0 | 0 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized93 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized0_7380 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7381 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized0_7382 | 258 | 258 | 0 | 0 | 6 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7383 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized0_7384 | 162 | 162 | 0 | 0 | 6 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized0_7385 | 120 | 120 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized0_7386 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[10].comp_map_latch | tri_rlmreg_p__parameterized75 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[11].comp_map_latch | tri_rlmreg_p__parameterized76 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[12].comp_map_latch | tri_rlmreg_p__parameterized77 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[13].comp_map_latch | tri_rlmreg_p__parameterized78 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[14].comp_map_latch | tri_rlmreg_p__parameterized79 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[15].comp_map_latch | tri_rlmreg_p__parameterized80 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[16].comp_map_latch | tri_rlmreg_p__parameterized81 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[17].comp_map_latch | tri_rlmreg_p__parameterized82 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[18].comp_map_latch | tri_rlmreg_p__parameterized83 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[19].comp_map_latch | tri_rlmreg_p__parameterized84 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[1].comp_map_latch | tri_rlmreg_p__parameterized66_7387 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[20].comp_map_latch | tri_rlmreg_p__parameterized85 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[21].comp_map_latch | tri_rlmreg_p__parameterized86 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[22].comp_map_latch | tri_rlmreg_p__parameterized87 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[23].comp_map_latch | tri_rlmreg_p__parameterized88 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[24].comp_map_latch | tri_rlmreg_p__parameterized89 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[25].comp_map_latch | tri_rlmreg_p__parameterized90 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[26].comp_map_latch | tri_rlmreg_p__parameterized91 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[27].comp_map_latch | tri_rlmreg_p__parameterized92 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[28].comp_map_latch | tri_rlmreg_p__parameterized93_7388 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[29].comp_map_latch | tri_rlmreg_p__parameterized94 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[2].comp_map_latch | tri_rlmreg_p__parameterized67 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[30].comp_map_latch | tri_rlmreg_p__parameterized95 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[31].comp_map_latch | tri_rlmreg_p__parameterized96 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[32].comp_map_latch | tri_rlmreg_p__parameterized97 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[33].comp_map_latch | tri_rlmreg_p__parameterized98 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[34].comp_map_latch | tri_rlmreg_p__parameterized99 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[35].comp_map_latch | tri_rlmreg_p__parameterized100 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[3].comp_map_latch | tri_rlmreg_p__parameterized68 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[4].comp_map_latch | tri_rlmreg_p__parameterized69 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[5].comp_map_latch | tri_rlmreg_p__parameterized70 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[6].comp_map_latch | tri_rlmreg_p__parameterized71 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[7].comp_map_latch | tri_rlmreg_p__parameterized72 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[8].comp_map_latch | tri_rlmreg_p__parameterized73 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl3.comp_map0[9].comp_map_latch | tri_rlmreg_p__parameterized74 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized0_7389 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7390 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[10].spec_map_arc_latch | tri_rlmreg_p__parameterized75_7391 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[10].spec_map_itag_latch | tri_rlmreg_p__parameterized110 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[11].spec_map_arc_latch | tri_rlmreg_p__parameterized76_7392 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[11].spec_map_itag_latch | tri_rlmreg_p__parameterized111 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[12].spec_map_arc_latch | tri_rlmreg_p__parameterized77_7393 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[12].spec_map_itag_latch | tri_rlmreg_p__parameterized112 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[13].spec_map_arc_latch | tri_rlmreg_p__parameterized78_7394 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[13].spec_map_itag_latch | tri_rlmreg_p__parameterized113 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[14].spec_map_arc_latch | tri_rlmreg_p__parameterized79_7395 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[14].spec_map_itag_latch | tri_rlmreg_p__parameterized114 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[15].spec_map_arc_latch | tri_rlmreg_p__parameterized80_7396 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[15].spec_map_itag_latch | tri_rlmreg_p__parameterized115 | 45 | 45 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[16].spec_map_arc_latch | tri_rlmreg_p__parameterized81_7397 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[16].spec_map_itag_latch | tri_rlmreg_p__parameterized116_7398 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[17].spec_map_arc_latch | tri_rlmreg_p__parameterized82_7399 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[17].spec_map_itag_latch | tri_rlmreg_p__parameterized117 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[18].spec_map_arc_latch | tri_rlmreg_p__parameterized83_7400 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[18].spec_map_itag_latch | tri_rlmreg_p__parameterized118 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[19].spec_map_arc_latch | tri_rlmreg_p__parameterized84_7401 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[19].spec_map_itag_latch | tri_rlmreg_p__parameterized119 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_arc_latch | tri_rlmreg_p__parameterized66_7402 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_itag_latch | tri_rlmreg_p__parameterized101_7403 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[20].spec_map_arc_latch | tri_rlmreg_p__parameterized85_7404 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[20].spec_map_itag_latch | tri_rlmreg_p__parameterized120 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[21].spec_map_arc_latch | tri_rlmreg_p__parameterized86_7405 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[21].spec_map_itag_latch | tri_rlmreg_p__parameterized121 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[22].spec_map_arc_latch | tri_rlmreg_p__parameterized87_7406 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[22].spec_map_itag_latch | tri_rlmreg_p__parameterized122 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[23].spec_map_arc_latch | tri_rlmreg_p__parameterized88_7407 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[23].spec_map_itag_latch | tri_rlmreg_p__parameterized123 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[24].spec_map_arc_latch | tri_rlmreg_p__parameterized89_7408 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[24].spec_map_itag_latch | tri_rlmreg_p__parameterized124 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[25].spec_map_arc_latch | tri_rlmreg_p__parameterized90_7409 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[25].spec_map_itag_latch | tri_rlmreg_p__parameterized125 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[26].spec_map_arc_latch | tri_rlmreg_p__parameterized91_7410 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[26].spec_map_itag_latch | tri_rlmreg_p__parameterized126 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[27].spec_map_arc_latch | tri_rlmreg_p__parameterized92_7411 | 72 | 72 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[27].spec_map_itag_latch | tri_rlmreg_p__parameterized127 | 85 | 85 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[28].spec_map_arc_latch | tri_rlmreg_p__parameterized93_7412 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[28].spec_map_itag_latch | tri_rlmreg_p__parameterized128 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[29].spec_map_arc_latch | tri_rlmreg_p__parameterized94_7413 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[29].spec_map_itag_latch | tri_rlmreg_p__parameterized129 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_arc_latch | tri_rlmreg_p__parameterized67_7414 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[2].spec_map_itag_latch | tri_rlmreg_p__parameterized102 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[30].spec_map_arc_latch | tri_rlmreg_p__parameterized95_7415 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[30].spec_map_itag_latch | tri_rlmreg_p__parameterized130 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[31].spec_map_arc_latch | tri_rlmreg_p__parameterized96_7416 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[31].spec_map_itag_latch | tri_rlmreg_p__parameterized131 | 45 | 45 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[32].spec_map_arc_latch | tri_rlmreg_p__parameterized97_7417 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[32].spec_map_itag_latch | tri_rlmreg_p__parameterized132_7418 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[33].spec_map_arc_latch | tri_rlmreg_p__parameterized98_7419 | 18 | 18 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[33].spec_map_itag_latch | tri_rlmreg_p__parameterized133 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[34].spec_map_arc_latch | tri_rlmreg_p__parameterized99_7420 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[34].spec_map_itag_latch | tri_rlmreg_p__parameterized134 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[35].spec_map_arc_latch | tri_rlmreg_p__parameterized100_7421 | 18 | 18 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[35].spec_map_itag_latch | tri_rlmreg_p__parameterized135 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_arc_latch | tri_rlmreg_p__parameterized68_7422 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[3].spec_map_itag_latch | tri_rlmreg_p__parameterized103 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_arc_latch | tri_rlmreg_p__parameterized69_7423 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[4].spec_map_itag_latch | tri_rlmreg_p__parameterized104 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_arc_latch | tri_rlmreg_p__parameterized70_7424 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[5].spec_map_itag_latch | tri_rlmreg_p__parameterized105 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_arc_latch | tri_rlmreg_p__parameterized71_7425 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[6].spec_map_itag_latch | tri_rlmreg_p__parameterized106 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_arc_latch | tri_rlmreg_p__parameterized72_7426 | 36 | 36 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[7].spec_map_itag_latch | tri_rlmreg_p__parameterized107 | 44 | 44 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_arc_latch | tri_rlmreg_p__parameterized73_7427 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[8].spec_map_itag_latch | tri_rlmreg_p__parameterized108 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[9].spec_map_arc_latch | tri_rlmreg_p__parameterized74_7428 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl4.spec_map0[9].spec_map_itag_latch | tri_rlmreg_p__parameterized109 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized136 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[10].buffer_pool_latch0 | tri_rlmreg_p__parameterized146 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[11].buffer_pool_latch0 | tri_rlmreg_p__parameterized147 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[12].buffer_pool_latch0 | tri_rlmreg_p__parameterized148 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[13].buffer_pool_latch0 | tri_rlmreg_p__parameterized149 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[14].buffer_pool_latch0 | tri_rlmreg_p__parameterized150 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[15].buffer_pool_latch0 | tri_rlmreg_p__parameterized151 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[16].buffer_pool_latch0 | tri_rlmreg_p__parameterized152 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[17].buffer_pool_latch0 | tri_rlmreg_p__parameterized153 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[18].buffer_pool_latch0 | tri_rlmreg_p__parameterized154 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[19].buffer_pool_latch0 | tri_rlmreg_p__parameterized155 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized137 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[20].buffer_pool_latch0 | tri_rlmreg_p__parameterized156 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[21].buffer_pool_latch0 | tri_rlmreg_p__parameterized157 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[22].buffer_pool_latch0 | tri_rlmreg_p__parameterized158 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[23].buffer_pool_latch0 | tri_rlmreg_p__parameterized159 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[24].buffer_pool_latch0 | tri_rlmreg_p__parameterized160 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[25].buffer_pool_latch0 | tri_rlmreg_p__parameterized161 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[26].buffer_pool_latch0 | tri_rlmreg_p__parameterized162 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[27].buffer_pool_latch0 | tri_rlmreg_p__parameterized163 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized138 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized139 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized140 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized141 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized142 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[7].buffer_pool_latch0 | tri_rlmreg_p__parameterized143 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[8].buffer_pool_latch0 | tri_rlmreg_p__parameterized144 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[9].buffer_pool_latch0 | tri_rlmreg_p__parameterized145 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | high_pri_mask_latch | tri_rlmlatch_p_7214 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | hold_instructions_latch | tri_rlmlatch_p_7215 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lr_rn_map | iuq_rn_map__parameterized1 | 114 | 114 | 0 | 0 | 61 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized191_7366 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized5_7367 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7368 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized5_7369 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7370 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized5_7371 | 38 | 38 | 0 | 0 | 3 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized5_7372 | 49 | 49 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized5_7373 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl3.comp_map0[1].comp_map_latch | tri_rlmreg_p__parameterized187 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized5_7374 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7375 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_arc_latch | tri_rlmreg_p__parameterized187_7376 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl4.spec_map0[1].spec_map_itag_latch | tri_rlmreg_p__parameterized101_7377 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized188 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized28 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized189 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized190 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized191_7378 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized192_7379 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | next_itag_0_latch | tri_rlmreg_p__parameterized132_7216 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | next_itag_1_latch | tri_rlmreg_p__parameterized132_7217 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_2ucode_latch | tri_rlmlatch_p_7218 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_async_block_latch | tri_rlmlatch_p_7219 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bh0_hist_latch | tri_rlmreg_p__parameterized2_7220 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bh1_hist_latch | tri_rlmreg_p__parameterized2_7221 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bh2_hist_latch | tri_rlmreg_p__parameterized2_7222 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bh_update_latch | tri_rlmlatch_p_7223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_br_pred_latch | tri_rlmlatch_p_7224 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bta_latch | tri_rlmreg_p__parameterized8_7225 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_bta_val_latch | tri_rlmlatch_p_7226 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_btb_entry_latch | tri_rlmlatch_p_7227 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_cord_latch | tri_rlmlatch_p_7228 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_core_block_latch | tri_rlmlatch_p_7229 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_error_latch | tri_rlmreg_p__parameterized5_7230 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_fuse_nop_latch | tri_rlmlatch_p_7231 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_fusion_latch | tri_rlmreg_p__parameterized8_7232 | 30 | 30 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_gshare_latch | tri_rlmreg_p__parameterized14_7233 | 27 | 27 | 0 | 0 | 18 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ifar_latch | tri_rlmreg_p__parameterized8_7234 | 34 | 34 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ilat_latch | tri_rlmreg_p__parameterized9_7235 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_instr_latch | tri_rlmreg_p__parameterized17_7236 | 187 | 187 | 0 | 0 | 32 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_isload_latch | tri_rlmlatch_p_7237 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_isram_latch | tri_rlmlatch_p_7238 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_isstore_latch | tri_rlmlatch_p_7239 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_itag_latch | tri_rlmreg_p__parameterized13_7240 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ls_ptr_latch | tri_rlmreg_p__parameterized5_7241 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_match_latch | tri_rlmlatch_p_7242 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_np1_flush_latch | tri_rlmlatch_p_7243 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ord_latch | tri_rlmlatch_p_7244 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_axu0_latch | tri_rlmlatch_p_7245 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_axu1_latch | tri_rlmlatch_p_7246 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_fx0_latch | tri_rlmlatch_p_7247 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_fx1_latch | tri_rlmlatch_p_7248 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_lq_latch | tri_rlmlatch_p_7249 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_rte_sq_latch | tri_rlmlatch_p_7250 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s1_itag_latch | tri_rlmreg_p__parameterized13_7251 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s1_p_latch | tri_rlmreg_p__parameterized0_7252 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s1_t_latch | tri_rlmreg_p__parameterized5_7253 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s1_v_latch | tri_rlmlatch_p_7254 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s2_itag_latch | tri_rlmreg_p__parameterized13_7255 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s2_p_latch | tri_rlmreg_p__parameterized0_7256 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s2_t_latch | tri_rlmreg_p__parameterized5_7257 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s2_v_latch | tri_rlmlatch_p_7258 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s3_itag_latch | tri_rlmreg_p__parameterized13_7259 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s3_p_latch | tri_rlmreg_p__parameterized0_7260 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s3_t_latch | tri_rlmreg_p__parameterized5_7261 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_s3_v_latch | tri_rlmlatch_p_7262 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_spec_latch | tri_rlmlatch_p_7263 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t1_a_latch | tri_rlmreg_p__parameterized0_7264 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t1_p_latch | tri_rlmreg_p__parameterized0_7265 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t1_t_latch | tri_rlmreg_p__parameterized5_7266 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t1_v_latch | tri_rlmlatch_p_7267 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t2_a_latch | tri_rlmreg_p__parameterized0_7268 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t2_p_latch | tri_rlmreg_p__parameterized0_7269 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t2_t_latch | tri_rlmreg_p__parameterized5_7270 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t2_v_latch | tri_rlmlatch_p_7271 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t3_a_latch | tri_rlmreg_p__parameterized0_7272 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t3_p_latch | tri_rlmreg_p__parameterized0_7273 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t3_t_latch | tri_rlmreg_p__parameterized5_7274 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_t3_v_latch | tri_rlmlatch_p_7275 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_type_ap_latch | tri_rlmlatch_p_7276 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_type_fp_latch | tri_rlmlatch_p_7277 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_type_spv_latch | tri_rlmlatch_p_7278 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_type_st_latch | tri_rlmlatch_p_7279 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ucode_cnt_latch | tri_rlmreg_p__parameterized5_7280 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_ucode_latch | tri_rlmreg_p__parameterized5_7281 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_valop_latch | tri_rlmlatch_p_7282 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i0_vld_latch | tri_rlmlatch_p_7283 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_async_block_latch | tri_rlmlatch_p_7284 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bh0_hist_latch | tri_rlmreg_p__parameterized2_7285 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bh1_hist_latch | tri_rlmreg_p__parameterized2_7286 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bh2_hist_latch | tri_rlmreg_p__parameterized2_7287 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bh_update_latch | tri_rlmlatch_p_7288 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_br_pred_latch | tri_rlmlatch_p_7289 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bta_latch | tri_rlmreg_p__parameterized8_7290 | 40 | 40 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_bta_val_latch | tri_rlmlatch_p_7291 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_btb_entry_latch | tri_rlmlatch_p_7292 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_cord_latch | tri_rlmlatch_p_7293 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_core_block_latch | tri_rlmlatch_p_7294 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_error_latch | tri_rlmreg_p__parameterized5_7295 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_fuse_nop_latch | tri_rlmlatch_p_7296 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_fusion_latch | tri_rlmreg_p__parameterized8_7297 | 30 | 30 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_gshare_latch | tri_rlmreg_p__parameterized14_7298 | 27 | 27 | 0 | 0 | 18 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ifar_latch | tri_rlmreg_p__parameterized8_7299 | 34 | 34 | 0 | 0 | 20 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ilat_latch | tri_rlmreg_p__parameterized9_7300 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_instr_latch | tri_rlmreg_p__parameterized17_7301 | 148 | 148 | 0 | 0 | 32 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_isload_latch | tri_rlmlatch_p_7302 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_isram_latch | tri_rlmlatch_p_7303 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_isstore_latch | tri_rlmlatch_p_7304 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_itag_latch | tri_rlmreg_p__parameterized13_7305 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ls_ptr_latch | tri_rlmreg_p__parameterized5_7306 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_match_latch | tri_rlmlatch_p_7307 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_np1_flush_latch | tri_rlmlatch_p_7308 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ord_latch | tri_rlmlatch_p_7309 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_axu0_latch | tri_rlmlatch_p_7310 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_axu1_latch | tri_rlmlatch_p_7311 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_fx0_latch | tri_rlmlatch_p_7312 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_fx1_latch | tri_rlmlatch_p_7313 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_lq_latch | tri_rlmlatch_p_7314 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_rte_sq_latch | tri_rlmlatch_p_7315 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s1_dep_hit_latch | tri_rlmlatch_p_7316 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s1_itag_latch | tri_rlmreg_p__parameterized13_7317 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s1_p_latch | tri_rlmreg_p__parameterized0_7318 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s1_t_latch | tri_rlmreg_p__parameterized5_7319 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s1_v_latch | tri_rlmlatch_p_7320 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s2_dep_hit_latch | tri_rlmlatch_p_7321 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s2_itag_latch | tri_rlmreg_p__parameterized13_7322 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s2_p_latch | tri_rlmreg_p__parameterized0_7323 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s2_t_latch | tri_rlmreg_p__parameterized5_7324 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s2_v_latch | tri_rlmlatch_p_7325 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s3_dep_hit_latch | tri_rlmlatch_p_7326 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s3_itag_latch | tri_rlmreg_p__parameterized13_7327 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s3_p_latch | tri_rlmreg_p__parameterized0_7328 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s3_t_latch | tri_rlmreg_p__parameterized5_7329 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_s3_v_latch | tri_rlmlatch_p_7330 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_spec_latch | tri_rlmlatch_p_7331 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t1_a_latch | tri_rlmreg_p__parameterized0_7332 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t1_p_latch | tri_rlmreg_p__parameterized0_7333 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t1_t_latch | tri_rlmreg_p__parameterized5_7334 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t1_v_latch | tri_rlmlatch_p_7335 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t2_a_latch | tri_rlmreg_p__parameterized0_7336 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t2_p_latch | tri_rlmreg_p__parameterized0_7337 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t2_t_latch | tri_rlmreg_p__parameterized5_7338 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t2_v_latch | tri_rlmlatch_p_7339 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t3_a_latch | tri_rlmreg_p__parameterized0_7340 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t3_p_latch | tri_rlmreg_p__parameterized0_7341 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t3_t_latch | tri_rlmreg_p__parameterized5_7342 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_t3_v_latch | tri_rlmlatch_p_7343 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_type_ap_latch | tri_rlmlatch_p_7344 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_type_fp_latch | tri_rlmlatch_p_7345 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_type_spv_latch | tri_rlmlatch_p_7346 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_type_st_latch | tri_rlmlatch_p_7347 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ucode_cnt_latch | tri_rlmreg_p__parameterized5_7348 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_ucode_latch | tri_rlmreg_p__parameterized5_7349 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_valop_latch | tri_rlmlatch_p_7350 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stall_frn_fdis_iu6_i1_vld_latch | tri_rlmlatch_p_7351 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ucode_cnt_latch | tri_rlmreg_p__parameterized5_7352 | 11 | 11 | 0 | 0 | 3 | 0 | 0 | 0 | | ucode_cnt_save_latch | tri_rlmreg_p__parameterized5_7353 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | xer_rn_map | iuq_rn_map__parameterized3 | 191 | 191 | 0 | 0 | 81 | 0 | 0 | 0 | | free_cnt_latch | tri_rlmreg_p__parameterized203 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | pool_free_0_latch | tri_rlmreg_p__parameterized9_7354 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | pool_free_0_v_latch | tri_rlmlatch_p_7355 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pool_free_1_latch | tri_rlmreg_p__parameterized9_7356 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | pool_free_1_v_latch | tri_rlmlatch_p_7357 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | read_ptr_latch | tri_rlmreg_p__parameterized9_7358 | 60 | 60 | 0 | 0 | 4 | 0 | 0 | 0 | | write_ptr_latch | tri_rlmreg_p__parameterized9_7359 | 97 | 97 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl3.comp_map0[0].comp_map_latch | tri_rlmreg_p__parameterized9_7360 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_arc_latch | tri_rlmreg_p__parameterized9_7361 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl4.spec_map0[0].spec_map_itag_latch | tri_rlmreg_p__parameterized13_7362 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[0].buffer_pool_latch0 | tri_rlmreg_p__parameterized193_7363 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[10].buffer_pool_latch0 | tri_rlmreg_p__parameterized203_7364 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[1].buffer_pool_latch0 | tri_rlmreg_p__parameterized194 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[2].buffer_pool_latch0 | tri_rlmreg_p__parameterized195 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[3].buffer_pool_latch0 | tri_rlmreg_p__parameterized196 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[4].buffer_pool_latch0 | tri_rlmreg_p__parameterized197 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[5].buffer_pool_latch0 | tri_rlmreg_p__parameterized198 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[6].buffer_pool_latch0 | tri_rlmreg_p__parameterized199 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[7].buffer_pool_latch0 | tri_rlmreg_p__parameterized200_7365 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[8].buffer_pool_latch0 | tri_rlmreg_p__parameterized201 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl5.buffer_pool_lat[9].buffer_pool_latch0 | tri_rlmreg_p__parameterized202 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lq0 | lq | 67759 | 67758 | 0 | 1 | 26090 | 49 | 6 | 0 | | ctl | lq_ctl | 35811 | 35811 | 0 | 0 | 14577 | 9 | 6 | 0 | | byp | lq_byp | 2679 | 2679 | 0 | 0 | 1118 | 0 | 0 | 0 | | ex10_xu0_req_abort_latch | tri_rlmlatch_p_7020 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex11_xu0_req_abort_latch | tri_rlmlatch_p_7021 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex12_xu0_req_abort_latch | tri_rlmlatch_p_7022 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex13_xu0_req_abort_latch | tri_rlmlatch_p_7023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s1_lq_sel_latch | tri_rlmreg_p__parameterized4_7024 | 132 | 132 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_s1_rel_sel_latch | tri_rlmreg_p__parameterized2_7025 | 193 | 193 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_s1_xu0_sel_latch | tri_rlmreg_p__parameterized50 | 199 | 199 | 0 | 0 | 11 | 0 | 0 | 0 | | ex1_s1_xu1_sel_latch | tri_rlmreg_p__parameterized0_7026 | 68 | 68 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_s2_lq_sel_latch | tri_rlmreg_p__parameterized4_7027 | 137 | 137 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_s2_rel_sel_latch | tri_rlmreg_p__parameterized2_7028 | 21 | 21 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_s2_xu0_sel_latch | tri_rlmreg_p__parameterized50_7029 | 157 | 157 | 0 | 0 | 11 | 0 | 0 | 0 | | ex1_s2_xu1_sel_latch | tri_rlmreg_p__parameterized0_7030 | 126 | 126 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_rs1_latch | tri_rlmreg_p__parameterized33_7031 | 524 | 524 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_rs2_latch | tri_rlmreg_p__parameterized33_7032 | 487 | 487 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_s1_abort_latch | tri_rlmlatch_p_7033 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_s2_abort_latch | tri_rlmlatch_p_7034 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_req_aborted_latch | tri_rlmlatch_p_7035 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_req_aborted_latch | tri_rlmlatch_p_7036 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xu0_req_abort_latch | tri_rlmlatch_p_7037 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xu0_stg_act_latch | tri_rlmlatch_p_7038 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xu1_req_abort_latch | tri_rlmlatch_p_7039 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xu1_rt_latch | tri_rlmreg_p__parameterized33_7040 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_xu1_stg_act_latch | tri_rlmlatch_p_7041 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_move_data_sel_latch | tri_rlmlatch_p_7042 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mv_rel_data_latch | tri_rlmreg_p__parameterized33_7043 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_req_aborted_latch | tri_rlmlatch_p_7044 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xu0_req_abort_latch | tri_rlmlatch_p_7045 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xu0_rt_latch | tri_rlmreg_p__parameterized33_7046 | 128 | 128 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_xu0_stg_act_latch | tri_rlmlatch_p_7047 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xu1_req_abort_latch | tri_rlmlatch_p_7048 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xu1_rt_latch | tri_rlmreg_p__parameterized33_7049 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_dvc1_cmp_latch | tri_rlmreg_p__parameterized12_7050 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_dvc2_cmp_latch | tri_rlmreg_p__parameterized12_7051 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_fx_ld_data_latch | tri_rlmreg_p__parameterized33_7052 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_gpr_wd0_latch | tri_rlmreg_p__parameterized245_7053 | 34 | 34 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_lq_req_abort_latch | tri_rlmlatch_p_7054 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xu0_req_abort_latch | tri_rlmlatch_p_7055 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xu0_rt_latch | tri_rlmreg_p__parameterized33_7056 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_xu0_stg_act_latch | tri_rlmlatch_p_7057 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xu1_req_abort_latch | tri_rlmlatch_p_7058 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_fx_ld_data_latch | tri_rlmreg_p__parameterized33_7059 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex7_lq_req_abort_latch | tri_rlmlatch_p_7060 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_xu0_req_abort_latch | tri_rlmlatch_p_7061 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_xu0_rt_latch | tri_rlmreg_p__parameterized33_7062 | 128 | 128 | 0 | 0 | 64 | 0 | 0 | 0 | | ex7_xu0_stg_act_latch | tri_rlmlatch_p_7063 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_xu1_req_abort_latch | tri_rlmlatch_p_7064 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_fx_ld_data_latch | tri_rlmreg_p__parameterized33_7065 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex8_lq_req_abort_latch | tri_rlmlatch_p_7066 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_xu0_req_abort_latch | tri_rlmlatch_p_7067 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_xu0_rt_latch | tri_rlmreg_p__parameterized33_7068 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex8_xu1_req_abort_latch | tri_rlmlatch_p_7069 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex9_lq_req_abort_latch | tri_rlmlatch_p_7070 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex9_xu0_req_abort_latch | tri_rlmlatch_p_7071 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_pc_ram_data_latch | tri_rlmreg_p__parameterized33_7072 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | rel3_rel_rt_latch | tri_rlmreg_p__parameterized33_7073 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | rel4_rel_rt_latch | tri_rlmreg_p__parameterized33_7074 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | dc32Kdir64B.arr | tri_64x34_8w_1r1w_5132 | 477 | 477 | 0 | 0 | 275 | 8 | 0 | 0 | | (dc32Kdir64B.arr) | tri_64x34_8w_1r1w_5132 | 1 | 1 | 0 | 0 | 0 | 8 | 0 | 0 | | data_out_reg | tri_rlmreg_p__parameterized256_7018 | 204 | 204 | 0 | 0 | 272 | 0 | 0 | 0 | | rd_act_reg | tri_rlmlatch_p_7019 | 272 | 272 | 0 | 0 | 3 | 0 | 0 | 0 | | dcc | lq_dcc | 9966 | 9966 | 0 | 0 | 1209 | 0 | 0 | 0 | | binv2_stg_act_reg | tri_rlmlatch_p_6574 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | binv3_stg_act_reg | tri_rlmlatch_p_6575 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | binv4_stg_act_reg | tri_rlmlatch_p_6576 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | binv5_stg_act_reg | tri_rlmlatch_p_6577 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | binv6_stg_act_reg | tri_rlmlatch_p_6578 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dbg_int_en_reg | tri_rlmreg_p__parameterized37_6579 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex0_done_reg | tri_rlmlatch_p_6580 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex1_done_reg | tri_regk__parameterized2_6581 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex2_done_reg | tri_rlmlatch_p_6582 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex3_done_reg | tri_regk__parameterized2_6583 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex4_done_reg | tri_rlmlatch_p_6584 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex5_done_reg | tri_regk__parameterized2_6585 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_ex6_done_reg | tri_rlmlatch_p_6586 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_rv1_val_reg | tri_rlmlatch_p_6587 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_tid_reg | tri_rlmreg_p__parameterized37_6588 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dir_arr_rd_val_reg | tri_rlmlatch_p_6589 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_binv_val_reg | tri_rlmlatch_p_6590 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_derat_snoop_val_reg | tri_rlmlatch_p_6591 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_2ucode_reg | tri_rlmlatch_p_6592 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_ucode_cnt_reg | tri_rlmreg_p__parameterized5_6593 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_i0_ucode_preissue_reg | tri_rlmlatch_p_6594 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_vld_reg | tri_rlmreg_p__parameterized37_6595 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_2ucode_reg | tri_rlmlatch_p_6596 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_ucode_cnt_reg | tri_rlmreg_p__parameterized5_6597 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_i1_ucode_preissue_reg | tri_rlmlatch_p_6598 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_vld_reg | tri_rlmreg_p__parameterized37_6599 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_binv_val_reg | tri_regk__parameterized2_6600 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_derat_snoop_val_reg | tri_regk__parameterized2_6601 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_lsu_64bit_mode_reg | tri_regk__parameterized2_6602 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_stg_act_reg | tri_rlmlatch_p_6603 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_algebraic_reg | tri_rlmlatch_p_6604 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_axu_instr_type_reg | tri_rlmreg_p__parameterized5_6605 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_axu_op_val_reg | tri_rlmlatch_p_6606 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_binv_val_reg | tri_rlmlatch_p_6607 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cache_acc_reg | tri_rlmlatch_p_6608 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cr_fld_reg | tri_rlmreg_p__parameterized4_6609 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_dcbf_instr_reg | tri_rlmlatch_p_6610 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbi_instr_reg | tri_rlmlatch_p_6611 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcblc_instr_reg | tri_rlmlatch_p_6612 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbst_instr_reg | tri_rlmlatch_p_6613 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbt_instr_reg | tri_rlmlatch_p_6614 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbtls_instr_reg | tri_rlmlatch_p_6615 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbtst_instr_reg | tri_rlmlatch_p_6616 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbtstls_instr_reg | tri_rlmlatch_p_6617 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dcbz_instr_reg | tri_rlmlatch_p_6618 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dci_instr_reg | tri_rlmlatch_p_6619 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icbi_instr_reg | tri_rlmlatch_p_6620 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icblc_l2_instr_reg | tri_rlmlatch_p_6621 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icbt_l2_instr_reg | tri_rlmlatch_p_6622 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icbtls_l2_instr_reg | tri_rlmlatch_p_6623 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ici_instr_reg | tri_rlmlatch_p_6624 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icswx_epid_reg | tri_rlmlatch_p_6625 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icswx_instr_reg | tri_rlmlatch_p_6626 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_icswxdot_instr_reg | tri_rlmlatch_p_6627 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_instr_reg | tri_rlmreg_p__parameterized17_6628 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | ex2_itag_reg | tri_rlmreg_p__parameterized13_6629 | 87 | 87 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_l_fld_reg | tri_rlmreg_p__parameterized2_6630 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ldawx_instr_reg | tri_rlmlatch_p_6631 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_load_instr_reg | tri_rlmlatch_p_6632 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_lsu_64bit_agen_reg | tri_rlmlatch_p_6633 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_makeitso_instr_reg | tri_rlmlatch_p_6634 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mbar_instr_reg | tri_rlmlatch_p_6635 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_msgsnd_instr_reg | tri_rlmlatch_p_6636 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mtspr_trace_reg | tri_rlmlatch_p_6637 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mutex_hint_reg | tri_rlmlatch_p_6638 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mword_instr_reg | tri_rlmlatch_p_6639 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_optype1_reg | tri_rlmlatch_p_6640 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_optype2_reg | tri_rlmlatch_p_6641 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_optype4_reg | tri_rlmlatch_p_6642 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_optype8_reg | tri_rlmlatch_p_6643 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_pfetch_val_reg | tri_rlmlatch_p_6644 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_resv_instr_reg | tri_rlmlatch_p_6645 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_saxu_instr_reg | tri_rlmlatch_p_6646 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sdp_instr_reg | tri_rlmlatch_p_6647 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sfx_val_reg | tri_rlmlatch_p_6648 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgpr_instr_reg | tri_rlmlatch_p_6649 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_stg_act_reg | tri_rlmlatch_p_6650 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_store_instr_reg | tri_rlmlatch_p_6651 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_strg_index_reg | tri_rlmlatch_p_6652 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sync_instr_reg | tri_rlmlatch_p_6653 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_target_gpr_reg | tri_rlmreg_p__parameterized46_6654 | 11 | 11 | 0 | 0 | 9 | 0 | 0 | 0 | | ex2_taxu_instr_reg | tri_rlmlatch_p_6655 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tdp_instr_reg | tri_rlmlatch_p_6656 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tgpr_instr_reg | tri_rlmlatch_p_6657 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_th_fld_c_reg | tri_rlmlatch_p_6658 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_th_fld_l2_reg | tri_rlmlatch_p_6659 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_thrd_id_reg | tri_rlmreg_p__parameterized37_6660 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tlbsync_instr_reg | tri_rlmlatch_p_6661 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ucode_cnt_reg | tri_rlmreg_p__parameterized5_6662 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_ucode_op_reg | tri_rlmlatch_p_6663 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ucode_val_reg | tri_rlmlatch_p_6664 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_upd_form_reg | tri_rlmlatch_p_6665 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_wchk_instr_reg | tri_rlmlatch_p_6666 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_wclr_instr_reg | tri_rlmlatch_p_6667 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_algebraic_reg | tri_regk__parameterized2_6668 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_axu_instr_type_reg | tri_regk__parameterized9_6669 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_axu_op_val_reg | tri_regk__parameterized2_6670 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_binv_val_reg | tri_regk__parameterized2_6671 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cache_acc_reg | tri_regk__parameterized2_6672 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cr_fld_reg | tri_regk__parameterized13 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_dacr_type_reg | tri_regk__parameterized2_6673 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbf_instr_reg | tri_regk__parameterized2_6674 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbi_instr_reg | tri_regk__parameterized2_6675 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcblc_instr_reg | tri_regk__parameterized2_6676 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbst_instr_reg | tri_regk__parameterized2_6677 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbt_instr_reg | tri_regk__parameterized2_6678 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbtls_instr_reg | tri_regk__parameterized2_6679 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbtst_instr_reg | tri_regk__parameterized2_6680 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbtstls_instr_reg | tri_regk__parameterized2_6681 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dcbz_instr_reg | tri_regk__parameterized2_6682 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dci_instr_reg | tri_regk__parameterized2_6683 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_eff_addr_reg | tri_regk__parameterized1_6684 | 323 | 323 | 0 | 0 | 66 | 0 | 0 | 0 | | ex3_icbi_instr_reg | tri_regk__parameterized2_6685 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icblc_l2_instr_reg | tri_regk__parameterized2_6686 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icbt_l2_instr_reg | tri_regk__parameterized2_6687 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icbtls_l2_instr_reg | tri_regk__parameterized2_6688 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ici_instr_reg | tri_regk__parameterized2_6689 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icswx_epid_reg | tri_regk__parameterized2_6690 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icswx_gs_reg | tri_rlmlatch_p_6691 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icswx_instr_reg | tri_regk__parameterized2_6692 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icswx_pr_reg | tri_rlmlatch_p_6693 | 56 | 56 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_icswxdot_instr_reg | tri_regk__parameterized2_6694 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_instr_reg | tri_regk__parameterized8_6695 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ex3_itag_reg | tri_regk__parameterized10 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_l_fld_reg | tri_regk__parameterized6_6696 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_ldawx_instr_reg | tri_regk__parameterized2_6697 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_load_instr_reg | tri_regk__parameterized2_6698 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_lsu_64bit_agen_reg | tri_regk__parameterized2_6699 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_makeitso_instr_reg | tri_regk__parameterized2_6700 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mbar_instr_reg | tri_regk__parameterized2_6701 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_msgsnd_instr_reg | tri_regk__parameterized2_6702 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mtspr_trace_reg | tri_regk__parameterized2_6703 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mutex_hint_reg | tri_regk__parameterized2_6704 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mword_instr_reg | tri_regk__parameterized2_6705 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_optype1_reg | tri_regk__parameterized2_6706 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_optype2_reg | tri_regk__parameterized2_6707 | 81 | 81 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_optype4_reg | tri_regk__parameterized2_6708 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_optype8_reg | tri_regk__parameterized2_6709 | 30 | 30 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_pfetch_val_reg | tri_rlmlatch_p_6710 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_resv_instr_reg | tri_regk__parameterized2_6711 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_saxu_instr_reg | tri_regk__parameterized2_6712 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sdp_instr_reg | tri_regk__parameterized2_6713 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sfx_val_reg | tri_regk__parameterized2_6714 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sgpr_instr_reg | tri_regk__parameterized2_6715 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_stg_act_reg | tri_rlmlatch_p_6716 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_store_instr_reg | tri_regk__parameterized2_6717 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_stq_val_req_reg | tri_regk__parameterized2_6718 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_strg_index_reg | tri_regk__parameterized2_6719 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sync_instr_reg | tri_regk__parameterized2_6720 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_target_gpr_reg | tri_regk__parameterized7_6721 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ex3_taxu_instr_reg | tri_regk__parameterized2_6722 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_tdp_instr_reg | tri_regk__parameterized2_6723 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_tgpr_instr_reg | tri_regk__parameterized2_6724 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_th_fld_c_reg | tri_regk__parameterized2_6725 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_th_fld_l2_reg | tri_regk__parameterized2_6726 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_thrd_id_reg | tri_regk__parameterized2_6727 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_tlbsync_instr_reg | tri_regk__parameterized2_6728 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ucode_cnt_reg | tri_regk__parameterized9_6729 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_ucode_op_reg | tri_regk__parameterized2_6730 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ucode_val_reg | tri_regk__parameterized2_6731 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_undef_lockset_reg | tri_regk__parameterized2_6732 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_undef_touch_reg | tri_regk__parameterized2_6733 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_upd_form_reg | tri_regk__parameterized2_6734 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wchk_instr_reg | tri_regk__parameterized2_6735 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wclr_instr_reg | tri_regk__parameterized2_6736 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_axu_op_val_reg | tri_rlmlatch_p_6737 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_binv_val_reg | tri_rlmlatch_p_6738 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_blkable_touch_reg | tri_rlmlatch_p_6739 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_c_inh_drop_op_reg | tri_rlmlatch_p_6740 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_cache_acc_reg | tri_rlmlatch_p_6741 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_cr_fld_reg | tri_rlmreg_p__parameterized4_6742 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_dacr_type_reg | tri_rlmlatch_p_6743 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbf_instr_reg | tri_rlmlatch_p_6744 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbi_instr_reg | tri_rlmlatch_p_6745 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcblc_instr_reg | tri_rlmlatch_p_6746 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbst_instr_reg | tri_rlmlatch_p_6747 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbt_instr_reg | tri_rlmlatch_p_6748 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbtls_instr_reg | tri_rlmlatch_p_6749 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbtst_instr_reg | tri_rlmlatch_p_6750 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbtstls_instr_reg | tri_rlmlatch_p_6751 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dcbz_instr_reg | tri_rlmlatch_p_6752 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dci_instr_reg | tri_rlmlatch_p_6753 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_derat_itagHit_reg | tri_rlmlatch_p_6754 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_eff_addr_reg | tri_rlmreg_p__parameterized33_6755 | 176 | 176 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_gath_load_reg | tri_rlmlatch_p_6756 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icbi_instr_reg | tri_rlmlatch_p_6757 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icblc_l2_instr_reg | tri_rlmlatch_p_6758 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icbt_l2_instr_reg | tri_rlmlatch_p_6759 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icbtls_l2_instr_reg | tri_rlmlatch_p_6760 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ici_instr_reg | tri_rlmlatch_p_6761 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icswx_ct_reg | tri_rlmreg_p__parameterized2_6762 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_icswx_ct_val_reg | tri_rlmlatch_p_6763 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icswx_epid_reg | tri_rlmlatch_p_6764 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icswx_instr_reg | tri_rlmlatch_p_6765 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icswx_restart_reg | tri_rlmlatch_p_6766 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_icswxdot_instr_reg | tri_rlmlatch_p_6767 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_instr_reg | tri_rlmreg_p__parameterized17_6768 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ex4_is_inval_op_reg | tri_rlmlatch_p_6769 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_is_sync_reg | tri_rlmlatch_p_6770 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_itag_reg | tri_rlmreg_p__parameterized13_6771 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_l1_lock_set_reg | tri_rlmlatch_p_6772 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_l2load_type_reg | tri_rlmlatch_p_6773 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_l_fld_reg | tri_rlmreg_p__parameterized2_6774 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ldawx_instr_reg | tri_rlmlatch_p_6775 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_le_mode_reg | tri_rlmlatch_p_6776 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_load_instr_reg | tri_rlmlatch_p_6777 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_load_type_reg | tri_rlmlatch_p_6778 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_local_dcbf_reg | tri_rlmlatch_p_6779 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lock_clr_reg | tri_rlmlatch_p_6780 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lsu_64bit_agen_reg | tri_rlmlatch_p_6781 | 33 | 33 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lswx_restart_reg | tri_rlmlatch_p_6782 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_makeitso_instr_reg | tri_rlmlatch_p_6783 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mbar_instr_reg | tri_rlmlatch_p_6784 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_moveOp_val_reg | tri_rlmlatch_p_6785 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_msgsnd_instr_reg | tri_rlmlatch_p_6786 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mtspr_trace_reg | tri_rlmlatch_p_6787 | 71 | 71 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_mutex_hint_reg | tri_rlmlatch_p_6788 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_opsize_enc_reg | tri_rlmreg_p__parameterized5_6789 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_pfetch_val_reg | tri_rlmlatch_p_6790 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_resv_instr_reg | tri_rlmlatch_p_6791 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_saxu_instr_reg | tri_rlmlatch_p_6792 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sdp_instr_reg | tri_rlmlatch_p_6793 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sfx_val_reg | tri_rlmlatch_p_6794 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sgpr_instr_reg | tri_rlmlatch_p_6795 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stg_act_reg | tri_rlmlatch_p_6796 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_store_instr_reg | tri_rlmlatch_p_6797 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stq_val_req_reg | tri_rlmlatch_p_6798 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_strg_gate_reg | tri_rlmlatch_p_6799 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_strg_index_reg | tri_rlmlatch_p_6800 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sync_instr_reg | tri_rlmlatch_p_6801 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_target_gpr_reg | tri_rlmreg_p__parameterized46_6802 | 19 | 19 | 0 | 0 | 9 | 0 | 0 | 0 | | ex4_taxu_instr_reg | tri_rlmlatch_p_6803 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tdp_instr_reg | tri_rlmlatch_p_6804 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tgpr_instr_reg | tri_rlmlatch_p_6805 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_th_fld_c_reg | tri_rlmlatch_p_6806 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_th_fld_l2_reg | tri_rlmlatch_p_6807 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_thrd_id_reg | tri_rlmreg_p__parameterized37_6808 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlbsync_instr_reg | tri_rlmlatch_p_6809 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ucode_op_reg | tri_rlmlatch_p_6810 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ucode_val_reg | tri_rlmlatch_p_6811 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_undef_lockset_reg | tri_rlmlatch_p_6812 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_undef_touch_reg | tri_rlmlatch_p_6813 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wNComp_rcvd_reg | tri_rlmlatch_p_6814 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wNComp_reg | tri_rlmlatch_p_6815 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wchk_instr_reg | tri_rlmlatch_p_6816 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wclr_instr_reg | tri_rlmlatch_p_6817 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_axu_op_val_reg | tri_regk__parameterized2_6818 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_axu_wren_reg | tri_regk__parameterized2_6819 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_blk_pf_load_reg | tri_regk__parameterized2_6820 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_cache_acc_reg | tri_regk__parameterized2_6821 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_classid_reg | tri_regk__parameterized6_6822 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_cr_fld_reg | tri_regk__parameterized13_6823 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_dacr_type_reg | tri_regk__parameterized2_6824 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dacrw_cmpr_reg | tri_regk_6825 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_derat_setHold_reg | tri_regk__parameterized2_6826 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_drop_rel_reg | tri_regk__parameterized2_6827 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dvc_en_reg | tri_regk__parameterized6_6828 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_eff_addr_reg | tri_regk__parameterized1_6829 | 124 | 124 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_execute_vld_reg | tri_regk__parameterized2_6830 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_flush2ucode_type_reg | tri_regk__parameterized2_6831 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_icswx_epid_reg | tri_regk__parameterized2_6832 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_instr_reg | tri_regk__parameterized8_6833 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ex5_itag_reg | tri_regk__parameterized10_6834 | 28 | 28 | 0 | 0 | 7 | 0 | 0 | 0 | | ex5_l1_lock_set_reg | tri_regk__parameterized2_6835 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_l_fld_reg | tri_regk__parameterized6_6836 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_ldawx_instr_reg | tri_regk__parameterized2_6837 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_load_hit_reg | tri_regk__parameterized2_6838 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_load_instr_reg | tri_regk__parameterized2_6839 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_load_miss_reg | tri_regk__parameterized2_6840 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_lock_clr_reg | tri_regk__parameterized2_6841 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_lq_ta_gpr_reg | tri_regk__parameterized7_6842 | 12 | 12 | 0 | 0 | 9 | 0 | 0 | 0 | | ex5_lq_wNComp_val_reg | tri_regk__parameterized2_6843 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_lq_wren_reg | tri_regk__parameterized2_6844 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mftgpr_val_reg | tri_regk__parameterized2_6845 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_opsize_enc_reg | tri_regk__parameterized9_6846 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_pfetch_val_reg | tri_rlmlatch_p_6847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_recirc_val_reg | tri_regk__parameterized2_6848 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_restart_val_reg | tri_regk__parameterized2_6849 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_spec_itag_reg | tri_regk__parameterized10_6850 | 12 | 12 | 0 | 0 | 7 | 0 | 0 | 0 | | ex5_spec_itag_vld_reg | tri_rlmlatch_p_6851 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_spec_load_miss_reg | tri_regk__parameterized2_6852 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_spec_tid_reg | tri_regk__parameterized2_6853 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_stg_act_reg | tri_rlmlatch_p_6854 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_target_gpr_reg | tri_regk__parameterized7_6855 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | ex5_thrd_id_reg | tri_regk__parameterized2_6856 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ttype_reg | tri_regk__parameterized11_6857 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_unable_2lock_reg | tri_regk__parameterized2_6858 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wNComp_cr_upd_reg | tri_regk__parameterized2_6859 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wNComp_ord_reg | tri_regk__parameterized2_6860 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wNComp_reg | tri_regk__parameterized2_6861 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wchkall_cplt_reg | tri_regk__parameterized2_6862 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_axu_wren_reg | tri_rlmlatch_p_6863 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_dacrw_cmpr_reg | tri_rlmreg_p__parameterized9_6864 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_dvc_en_reg | tri_rlmreg_p__parameterized2_6865 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_itag_reg | tri_rlmreg_p__parameterized13_6866 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | ex6_lq_comp_rpt_reg | tri_rlmlatch_p_6867 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_lq_ta_gpr_reg | tri_rlmreg_p__parameterized0_6868 | 3285 | 3285 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_lq_wren_reg | tri_rlmlatch_p_6869 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_stg_act_reg | tri_rlmlatch_p_6870 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_stq5_unable_2lock_reg | tri_rlmlatch_p_6871 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_thrd_id_reg | tri_rlmreg_p__parameterized37_6872 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fgen | lq_fgen | 187 | 187 | 0 | 0 | 145 | 0 | 0 | 0 | | ex2_dlock_excp_reg | tri_rlmlatch_p_6964 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ehpriv_excp_reg | tri_rlmlatch_p_6965 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_hypv_prog_reg | tri_rlmlatch_p_6966 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_illeg_prog_reg | tri_rlmlatch_p_6967 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ilock_excp_reg | tri_rlmlatch_p_6968 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_priv_prog_reg | tri_rlmlatch_p_6969 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sfx_excpt_det_reg | tri_rlmlatch_p_6970 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dlock_excp_reg | tri_rlmlatch_p_6971 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ehpriv_excp_reg | tri_rlmlatch_p_6972 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_hypv_prog_reg | tri_rlmlatch_p_6973 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_illeg_prog_reg | tri_rlmlatch_p_6974 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ilock_excp_reg | tri_rlmlatch_p_6975 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_priv_prog_reg | tri_rlmlatch_p_6976 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sfx_excpt_det_reg | tri_rlmlatch_p_6977 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_axu_fp_unavail_reg | tri_rlmlatch_p_6978 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_cache_acc_reg | tri_rlmlatch_p_6979 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dlock_excp_reg | tri_rlmlatch_p_6980 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_flush_2ucode_reg | tri_rlmlatch_p_6981 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_hypv_prog_reg | tri_rlmlatch_p_6982 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_illeg_prog_reg | tri_rlmlatch_p_6983 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ilock_excp_reg | tri_rlmlatch_p_6984 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_is_dcbz_reg | tri_rlmlatch_p_6985 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_prealign_int_reg | tri_rlmlatch_p_6986 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_priv_prog_reg | tri_rlmlatch_p_6987 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sfx_excpt_det_reg | tri_rlmlatch_p_6988 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ucode_cnt_reg | tri_rlmreg_p__parameterized5_6989 | 57 | 57 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_ucode_dis_prog_reg | tri_rlmlatch_p_6990 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ucode_val_reg | tri_rlmlatch_p_6991 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_valid_resv_reg | tri_rlmlatch_p_6992 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dac_int_det_reg | tri_rlmlatch_p_6993 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dear_val_reg | tri_rlmreg_p__parameterized37_6994 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_derat_multihit_det_reg | tri_rlmlatch_p_6995 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_derat_multihit_flush_reg | tri_rlmlatch_p_6996 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_derat_perr_det_reg | tri_rlmlatch_p_6997 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_derat_perr_flush_reg | tri_rlmlatch_p_6998 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_exception_reg | tri_rlmreg_p__parameterized0_6999 | 11 | 11 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_flush_2ucode_reg | tri_rlmlatch_p_7000 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_high_pri_excp_reg | tri_rlmlatch_p_7001 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_local_flush_reg | tri_rlmlatch_p_7002 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_low_pri_excp_reg | tri_rlmlatch_p_7003 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlb_flush_req_reg | tri_rlmlatch_p_7004 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlb_mchk_req_reg | tri_rlmlatch_p_7005 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wNComp_rcvd_reg | tri_rlmlatch_p_7006 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_wNComp_excp_reg | tri_rlmlatch_p_7007 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_fir_rpt_reg | tri_rlmreg_p__parameterized13_7008 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ucode_cnt_2ucode_reg | tri_rlmreg_p__parameterized12_7009 | 18 | 18 | 0 | 0 | 8 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[0].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[1].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7010 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[2].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7011 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[3].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7012 | 4 | 4 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[4].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7013 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[5].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7014 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[6].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7015 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_memAttr.ucode_cnt_memAttr[7].ucode_cnt_memAttr_reg | tri_rlmreg_p__parameterized260_7016 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | ucode_cnt_val_reg | tri_rlmreg_p__parameterized12_7017 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | iu_lq_cp_flush_reg | tri_rlmreg_p__parameterized37_6873 | 26 | 26 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_lq_cp_next_itag_tid.iu_lq_cp_next_itag_tid[0].iu_lq_cp_next_itag_reg | tri_rlmreg_p__parameterized13_6874 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | iu_lq_recirc_val_reg | tri_rlmreg_p__parameterized37_6875 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_idle_reg | tri_rlmreg_p__parameterized37_6876 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_dacr_type_reg | tri_rlmlatch_p_6877 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_dacrw_reg | tri_rlmreg_p__parameterized9_6878 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lq0_iu_dear_val_reg | tri_rlmreg_p__parameterized37_6879 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_eff_addr_reg | tri_rlmreg_p__parameterized33_6880 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | lq0_iu_exception_reg | tri_rlmreg_p__parameterized0_6881 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | lq0_iu_exception_val_reg | tri_rlmlatch_p_6882 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_execute_vld_reg | tri_rlmreg_p__parameterized37_6883 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_flush2ucode_reg | tri_rlmlatch_p_6884 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_flush2ucode_type_reg | tri_rlmlatch_p_6885 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_instr_reg | tri_rlmreg_p__parameterized17_6886 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | lq0_iu_itag_reg | tri_rlmreg_p__parameterized13_6887 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lq0_iu_n_flush_reg | tri_rlmlatch_p_6888 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_np1_flush_reg | tri_rlmlatch_p_6889 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_iu_recirc_val_reg | tri_rlmreg_p__parameterized37_6890 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_pc_ram_data_val_reg | tri_rlmlatch_p_6891 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_lq_ram_active_reg | tri_rlmreg_p__parameterized37_6892 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_axu_wren_reg | tri_rlmlatch_p_6893 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_ta_gpr_reg | tri_rlmreg_p__parameterized46_6894 | 3624 | 3624 | 0 | 0 | 15 | 0 | 0 | 0 | | rel2_xu_wren_reg | tri_rlmlatch_p_6895 | 788 | 788 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_binv_val_reg | tri_regk__parameterized2_6896 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_en_trace_reg | tri_rlmlatch_p_6897 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_notlb_reg | tri_rlmlatch_p_6898 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_ucode_dis_reg | tri_rlmlatch_p_6899 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_dbcr0_idm_reg | tri_rlmreg_p__parameterized37_6900 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_epcr_duvd_reg | tri_rlmreg_p__parameterized37_6901 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_lpidr_reg | tri_rlmreg_p__parameterized12_6902 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | spr_msr_de_reg | tri_rlmreg_p__parameterized37_6903 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_ds_reg | tri_rlmreg_p__parameterized37_6904 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_fp_reg | tri_rlmreg_p__parameterized37_6905 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_gs_reg | tri_rlmreg_p__parameterized37_6906 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_pr_reg | tri_rlmreg_p__parameterized37_6907 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_pid_reg.spr_pid_reg[0].spr_pid_reg | tri_ser_rlmreg_p__parameterized9_6908 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9_6963 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | spr_xucr0_aflsta_reg | tri_rlmlatch_p_6909 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_dcdis_reg | tri_rlmlatch_p_6910 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_en_trace_um_reg | tri_rlmreg_p__parameterized37_6911 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_flsta_reg | tri_rlmlatch_p_6912 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_mbar_ack_reg | tri_rlmlatch_p_6913 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_mdcp_reg | tri_rlmlatch_p_6914 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_mddp_reg | tri_rlmlatch_p_6915 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_tlbsync_reg | tri_rlmlatch_p_6916 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_wlk_reg | tri_rlmlatch_p_6917 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr4_mddmh_reg | tri_rlmlatch_p_6918 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr4_mmu_mchk_reg | tri_rlmlatch_p_6919 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_ci_reg | tri_rlmlatch_p_6920 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_epid_val_reg | tri_rlmlatch_p_6921 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_mfdpa_val_reg | tri_rlmlatch_p_6922 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_mfdpf_val_reg | tri_rlmlatch_p_6923 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_mftgpr_val_reg | tri_rlmlatch_p_6924 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_resv_reg | tri_rlmlatch_p_6925 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_stg_act_reg | tri_rlmlatch_p_6926 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | stq2_store_val_reg | tri_rlmlatch_p_6927 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_thrd_id_reg | tri_rlmreg_p__parameterized37_6928 | 130 | 130 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_ci_reg | tri_regk__parameterized2_6929 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_icswx_data_reg | tri_regk__parameterized12 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | | stq3_mfdpa_val_reg | tri_regk__parameterized2_6930 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_mfdpf_val_reg | tri_regk__parameterized2_6931 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_mftgpr_val_reg | tri_regk__parameterized2_6932 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_resv_reg | tri_regk__parameterized2_6933 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_stg_act_reg | tri_rlmlatch_p_6934 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_store_val_reg | tri_regk__parameterized2_6935 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_thrd_id_reg | tri_rlmreg_p__parameterized37_6936 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_dcarr_wren_reg | tri_rlmlatch_p_6937 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_mfdpa_val_reg | tri_rlmlatch_p_6938 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_mfdpf_val_reg | tri_rlmlatch_p_6939 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_mftgpr_val_reg | tri_rlmlatch_p_6940 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_stg_act_reg | tri_rlmlatch_p_6941 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_thrd_id_reg | tri_rlmreg_p__parameterized37_6942 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_mfdpa_val_reg | tri_regk__parameterized2_6943 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_mfdpf_val_reg | tri_regk__parameterized2_6944 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_mftgpr_val_reg | tri_regk__parameterized2_6945 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_stg_act_reg | tri_rlmlatch_p_6946 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_thrd_id_reg | tri_rlmreg_p__parameterized37_6947 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_itag_reg | tri_rlmreg_p__parameterized13_6948 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | stq6_mfdpa_val_reg | tri_rlmlatch_p_6949 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_mftgpr_val_reg | tri_rlmlatch_p_6950 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_moveOp_val_reg | tri_rlmlatch_p_6951 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_tgpr_reg | tri_rlmreg_p__parameterized46_6952 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | stq6_thrd_id_reg | tri_rlmreg_p__parameterized37_6953 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_mftgpr_val_reg | tri_regk__parameterized2_6954 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_thrd_id_reg | tri_rlmreg_p__parameterized37_6955 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq8_mftgpr_val_reg | tri_rlmlatch_p_6956 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq8_thrd_id_reg | tri_rlmreg_p__parameterized37_6957 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xer_lq_cp_rd_so_reg | tri_rlmreg_p__parameterized37_6958 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xudbg1_dir_reg_reg | tri_ser_rlmreg_p__parameterized11_6959 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized11_6962 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | xudbg1_parity_reg_reg | tri_ser_rlmreg_p__parameterized14_6960 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized14_6961 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xudbg2_tag_reg | tri_ser_rlmreg_p__parameterized26 | 30 | 30 | 0 | 0 | 30 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized26 | 30 | 30 | 0 | 0 | 30 | 0 | 0 | 0 | | dec | lq_dec | 1023 | 1023 | 0 | 0 | 298 | 0 | 0 | 0 | | ex0_arr_rd_congr_cl_latch | tri_rlmreg_p__parameterized0_6492 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex0_arr_rd_val_latch | tri_rlmlatch_p_6493 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_back_inv_addr_latch | tri_rlmreg_p__parameterized52_6494 | 19 | 19 | 0 | 0 | 36 | 0 | 0 | 0 | | ex0_back_inv_latch | tri_rlmlatch_p_6495 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_derat_snoop_addr_latch | tri_rlmreg_p__parameterized34_6496 | 22 | 22 | 0 | 0 | 52 | 0 | 0 | 0 | | ex0_derat_snoop_val_latch | tri_rlmlatch_p_6497 | 73 | 73 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_hold_taken_latch | tri_rlmlatch_p_6498 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_needs_release_latch | tri_rlmlatch_p_6499 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_stg_act_latch | tri_rlmlatch_p_6500 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_tid_latch | tri_rlmreg_p__parameterized37_6501 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_vld_latch | tri_rlmlatch_p_6502 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_hold_taken_latch | tri_rlmlatch_p_6503 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_instr_latch | tri_rlmreg_p__parameterized17_6504 | 575 | 575 | 0 | 0 | 32 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13_6505 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_needs_release_latch | tri_rlmlatch_p_6506 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_release_attmp_latch | tri_rlmlatch_p_6507 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s1_vld_latch | tri_rlmlatch_p_6508 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s2_vld_latch | tri_rlmlatch_p_6509 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_selimm_addr_latch | tri_rlmreg_p__parameterized253_6510 | 1 | 1 | 0 | 0 | 58 | 0 | 0 | 0 | | ex1_selimm_addr_val_latch | tri_rlmlatch_p_6511 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_stg_act_latch | tri_rlmlatch_p_6512 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t1_wa_latch | tri_rlmreg_p__parameterized0_6513 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_t1_we_latch | tri_rlmlatch_p_6514 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t3_wa_latch | tri_rlmreg_p__parameterized0_6515 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_tid_latch | tri_rlmreg_p__parameterized37_6516 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ucode_cnt_latch | tri_rlmreg_p__parameterized5_6517 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_ucode_latch | tri_rlmreg_p__parameterized2_6518 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_vld_latch | tri_rlmlatch_p_6519 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_axu_physical_upd_latch | tri_rlmlatch_p_6520 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dir_rd_act_latch | tri_rlmlatch_p_6521 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_any_load_dac_latch | tri_rlmlatch_p_6522 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_any_store_dac_latch | tri_rlmlatch_p_6523 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_6524 | 19 | 19 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_needs_release_latch | tri_rlmlatch_p_6525 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_physical_upd_latch | tri_rlmlatch_p_6526 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_stg_act_latch | tri_rlmlatch_p_6527 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_t1_we_latch | tri_rlmlatch_p_6528 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tid_latch | tri_rlmreg_p__parameterized37_6529 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_vld_latch | tri_rlmlatch_p_6530 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_axu_abort_rpt_latch | tri_rlmlatch_p_6531 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_req_abort_rpt_latch | tri_rlmlatch_p_6532 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_stg_act_latch | tri_rlmlatch_p_6533 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_t1_we_latch | tri_rlmlatch_p_6534 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_tid_latch | tri_rlmreg_p__parameterized37_6535 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_vld_latch | tri_rlmlatch_p_6536 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_axu_abort_rpt_latch | tri_rlmlatch_p_6537 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_req_abort_rpt_latch | tri_rlmlatch_p_6538 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stg_act_latch | tri_rlmlatch_p_6539 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_t1_we_latch | tri_rlmlatch_p_6540 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tid_latch | tri_rlmreg_p__parameterized37_6541 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_vld_latch | tri_rlmlatch_p_6542 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_axu_abort_rpt_latch | tri_rlmlatch_p_6543 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_req_abort_rpt_latch | tri_rlmlatch_p_6544 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_stg_act_latch | tri_rlmlatch_p_6545 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_t1_we_latch | tri_rlmlatch_p_6546 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_vld_latch | tri_rlmlatch_p_6547 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_stg_act_latch | tri_rlmlatch_p_6548 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_t1_we_latch | tri_rlmlatch_p_6549 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_stg_act_latch | tri_rlmlatch_p_6550 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_lq_cp_flush_latch | tri_rlmreg_p__parameterized37_6551 | 40 | 40 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_ex5_act_latch | tri_rlmlatch_p_6552 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | release_itag_latch | tri_rlmreg_p__parameterized13_6553 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | release_itag_vld_latch | tri_rlmlatch_p_6554 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | release_tid_latch | tri_rlmreg_p__parameterized37_6555 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_back_inv_latch | tri_rlmlatch_p_6556 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_hold_taken_latch | tri_rlmlatch_p_6557 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_en_ditc_latch | tri_rlmlatch_p_6558 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_en_icswx_latch | tri_rlmlatch_p_6559 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_en_pc_latch | tri_rlmlatch_p_6560 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_gs_latch | tri_rlmreg_p__parameterized37_6561 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_pr_latch | tri_rlmreg_p__parameterized37_6562 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_ucle_latch | tri_rlmreg_p__parameterized37_6563 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msrp_uclep_latch | tri_rlmreg_p__parameterized37_6564 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_release_itag_latch | tri_rlmreg_p__parameterized13_6565 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | stq2_release_tid_latch | tri_rlmreg_p__parameterized37_6566 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_release_vld_latch | tri_rlmlatch_p_6567 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_needs_release_latch | tri_rlmlatch_p_6568 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_release_attmp_latch | tri_rlmlatch_p_6569 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_release_vld_latch | tri_rlmlatch_p_6570 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_mftgpr_val_latch | tri_rlmlatch_p_6571 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_mftgpr_val_latch | tri_rlmlatch_p_6572 | 141 | 141 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_hold_req_latch | tri_rlmlatch_p_6573 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat | lq_derat | 7006 | 7006 | 0 | 0 | 5632 | 1 | 2 | 0 | | (derat) | lq_derat | 4 | 4 | 0 | 0 | 0 | 0 | 0 | 0 | | cam_entry_le_latch | tri_rlmreg_p__parameterized17_6240 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | ccr2_frat_paranoia_latch | tri_rlmreg_p__parameterized227_6241 | 79 | 79 | 0 | 0 | 12 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_6242 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_next_itag[0].cp_next_itag_latch | tri_rlmreg_p__parameterized13_6243 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | cp_next_val_latch | tri_rlmreg_p__parameterized37_6244 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | csync_val_latch | tri_rlmreg_p__parameterized2_6245 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_cam | tri_cam_32x143_1r1w1c | 2914 | 2914 | 0 | 0 | 3302 | 1 | 2 | 0 | | derat_dcc_clr_hold_latch | tri_rlmreg_p__parameterized37_6246 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_match_latch | tri_rlmreg_p__parameterized17_6247 | 125 | 125 | 0 | 0 | 32 | 0 | 0 | 0 | | entry_valid_latch | tri_rlmreg_p__parameterized17_6248 | 388 | 388 | 0 | 0 | 32 | 0 | 0 | 0 | | eplc_wr_latch | tri_rlmreg_p__parameterized5_6249 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | eplc_wr_val_latch | tri_rlmreg_p__parameterized37_6250 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | epsc_wr_latch | tri_rlmreg_p__parameterized5_6251 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | epsc_wr_val_latch | tri_rlmreg_p__parameterized37_6252 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | eptr_latch | tri_rlmreg_p__parameterized4_6253 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | eratm_entry_epn[0].eratm_entry_epn_latch | tri_rlmreg_p__parameterized34_6254 | 17 | 17 | 0 | 0 | 52 | 0 | 0 | 0 | | eratm_entry_epn[1].eratm_entry_epn_latch | tri_rlmreg_p__parameterized34_6255 | 17 | 17 | 0 | 0 | 52 | 0 | 0 | 0 | | eratm_entry_epn[2].eratm_entry_epn_latch | tri_rlmreg_p__parameterized34_6256 | 17 | 17 | 0 | 0 | 52 | 0 | 0 | 0 | | eratm_entry_epn[3].eratm_entry_epn_latch | tri_rlmreg_p__parameterized34_6257 | 17 | 17 | 0 | 0 | 52 | 0 | 0 | 0 | | eratm_entry_itag[0].eratm_entry_itag_latch | tri_rlmreg_p__parameterized13_6258 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | eratm_entry_itag[1].eratm_entry_itag_latch | tri_rlmreg_p__parameterized13_6259 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | eratm_entry_itag[2].eratm_entry_itag_latch | tri_rlmreg_p__parameterized13_6260 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | eratm_entry_itag[3].eratm_entry_itag_latch | tri_rlmreg_p__parameterized13_6261 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | eratm_entry_lratmiss_latch | tri_rlmreg_p__parameterized9_6262 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_lru_par_err_latch | tri_rlmreg_p__parameterized9_6263 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_mkill_latch | tri_rlmreg_p__parameterized9_6264 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_nonspec_val_latch | tri_rlmreg_p__parameterized9_6265 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_ptfault_latch | tri_rlmreg_p__parameterized9_6266 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_state[0].eratm_entry_state_latch | tri_rlmreg_p__parameterized5_6267 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | eratm_entry_state[1].eratm_entry_state_latch | tri_rlmreg_p__parameterized5_6268 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | | eratm_entry_state[2].eratm_entry_state_latch | tri_rlmreg_p__parameterized5_6269 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | | eratm_entry_state[3].eratm_entry_state_latch | tri_rlmreg_p__parameterized5_6270 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | | eratm_entry_tid[0].eratm_entry_tid_latch | tri_rlmreg_p__parameterized37_6271 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | eratm_entry_tid[1].eratm_entry_tid_latch | tri_rlmreg_p__parameterized37_6272 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | eratm_entry_tid[2].eratm_entry_tid_latch | tri_rlmreg_p__parameterized37_6273 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | eratm_entry_tid[3].eratm_entry_tid_latch | tri_rlmreg_p__parameterized37_6274 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | eratm_entry_tlb_multihit_latch | tri_rlmreg_p__parameterized9_6275 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_tlb_par_err_latch | tri_rlmreg_p__parameterized9_6276 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_tlbinelig_latch | tri_rlmreg_p__parameterized9_6277 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | eratm_entry_tlbmiss_latch | tri_rlmreg_p__parameterized9_6278 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | eratre_hole_latch | tri_rlmreg_p__parameterized9_6279 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | eratwe_hole_latch | tri_rlmreg_p__parameterized9_6280 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | ex0_binv_val_latch | tri_rlmlatch_p_6281 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_csync_val_latch | tri_rlmlatch_p_6282 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_eplc_wr_val_latch | tri_rlmreg_p__parameterized37_6283 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_epsc_wr_val_latch | tri_rlmreg_p__parameterized37_6284 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_isync_val_latch | tri_rlmlatch_p_6285 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_rel_val_latch | tri_rlmreg_p__parameterized9_6286 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex0_snoop_val_latch | tri_rlmlatch_p_6287 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_ttype_latch | tri_rlmreg_p__parameterized9_6288 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_ttype_val_latch | tri_rlmreg_p__parameterized37_6289 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_binv_val_latch | tri_rlmlatch_p_6290 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_rel_val_latch | tri_rlmreg_p__parameterized9_6291 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_snoop_val_latch | tri_rlmlatch_p_6292 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_stg_act_latch | tri_rlmlatch_p_6293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ttype03_latch | tri_rlmreg_p__parameterized9_6294 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_ttype67_latch | tri_rlmreg_p__parameterized2_6295 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_ttype_latch | tri_rlmreg_p__parameterized2_6296 | 50 | 50 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_valid_latch | tri_rlmreg_p__parameterized37_6297 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_valid_op_latch | tri_rlmreg_p__parameterized37_6298 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_byte_rev_latch | tri_rlmlatch_p_6299 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_data_in_latch | tri_rlmreg_p__parameterized33_6300 | 141 | 141 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_extclass_latch | tri_rlmreg_p__parameterized2_6301 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_6302 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_pfetch_val_latch | tri_rlmreg_p__parameterized37_6303 | 30 | 30 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_pid_latch | tri_rlmreg_p__parameterized41_6304 | 22 | 22 | 0 | 0 | 14 | 0 | 0 | 0 | | ex2_ra_entry_latch | tri_rlmreg_p__parameterized4_6305 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_state_latch | tri_rlmreg_p__parameterized9_6306 | 38 | 38 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_stg_act_latch | tri_rlmlatch_p_6307 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tlbsel_latch | tri_rlmreg_p__parameterized2_6308 | 10 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ttype_latch | tri_rlmreg_p__parameterized227_6309 | 55 | 55 | 0 | 0 | 11 | 0 | 0 | 0 | | ex2_valid_latch | tri_rlmreg_p__parameterized37_6310 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_valid_op_latch | tri_rlmreg_p__parameterized37_6311 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ws_latch | tri_rlmreg_p__parameterized2_6312 | 38 | 38 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_byte_rev_latch | tri_rlmlatch_p_6313 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_comp_addr_latch | tri_rlmreg_p__parameterized53_6314 | 30 | 30 | 0 | 0 | 30 | 0 | 0 | 0 | | ex3_dsi_latch | tri_rlmreg_p__parameterized6_6315 | 8 | 8 | 0 | 0 | 9 | 0 | 0 | 0 | | ex3_epn_latch | tri_rlmreg_p__parameterized34_6316 | 77 | 77 | 0 | 0 | 52 | 0 | 0 | 0 | | ex3_eratm_itag_hit_latch | tri_rlmreg_p__parameterized9_6317 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_extclass_latch | tri_rlmreg_p__parameterized2_6318 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_itag_latch | tri_rlmreg_p__parameterized13_6319 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_noop_touch_latch | tri_rlmreg_p__parameterized6_6320 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_pfetch_val_latch | tri_rlmreg_p__parameterized37_6321 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_pid_latch | tri_rlmreg_p__parameterized41_6322 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ex3_ra_entry_latch | tri_rlmreg_p__parameterized4_6323 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_state_latch | tri_rlmreg_p__parameterized9_6324 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_stg_act_latch | tri_rlmlatch_p_6325 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_tlbsel_latch | tri_rlmreg_p__parameterized2_6326 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_ttype_latch | tri_rlmreg_p__parameterized227_6327 | 10 | 10 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_valid_latch | tri_rlmreg_p__parameterized37_6328 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_valid_op_latch | tri_rlmreg_p__parameterized37_6329 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ws_latch | tri_rlmreg_p__parameterized2_6330 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_array_cmp_data_latch | tri_rlmreg_p__parameterized45 | 23 | 23 | 0 | 0 | 68 | 0 | 0 | 0 | | ex4_cam_cmp_data_latch | tri_rlmreg_p__parameterized44_6331 | 25 | 25 | 0 | 0 | 83 | 0 | 0 | 0 | | ex4_dsi_latch | tri_rlmreg_p__parameterized6_6332 | 2 | 2 | 0 | 0 | 9 | 0 | 0 | 0 | | ex4_emq_excp_rpt_latch | tri_rlmreg_p__parameterized9_6333 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_epn_hit_restart_latch | tri_rlmlatch_p_6334 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_epn_latch | tri_rlmreg_p__parameterized34_6335 | 277 | 277 | 0 | 0 | 52 | 0 | 0 | 0 | | ex4_extclass_latch | tri_rlmreg_p__parameterized2_6336 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_first_hit_entry_pt_latch | tri_rlmreg_p__parameterized214 | 15 | 15 | 0 | 0 | 31 | 0 | 0 | 0 | | ex4_full_restart_latch | tri_rlmlatch_p_6337 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_gate_miss_latch | tri_rlmlatch_p_6338 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_hit_latch | tri_rlmlatch_p_6339 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_itag_hit_restart_latch | tri_rlmlatch_p_6340 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_itag_latch | tri_rlmreg_p__parameterized13_6341 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_lpid_latch | tri_rlmreg_p__parameterized12_6342 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_lratmiss_latch | tri_rlmlatch_p_6343 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lru_par_err_latch | tri_rlmlatch_p_6344 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_miss_latch | tri_rlmreg_p__parameterized37_6345 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_multihit_b_pt_latch | tri_rlmreg_p__parameterized17_6346 | 13 | 13 | 0 | 0 | 32 | 0 | 0 | 0 | | ex4_multihit_latch | tri_rlmreg_p__parameterized37_6347 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_nonspec_val_latch | tri_rlmlatch_p_6348 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_noop_touch_latch | tri_rlmreg_p__parameterized6_6349 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_oldest_itag_latch | tri_rlmlatch_p_6350 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_parerr_latch | tri_rlmreg_p__parameterized5_6351 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_pfetch_val_latch | tri_rlmreg_p__parameterized37_6352 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_pid_latch | tri_rlmreg_p__parameterized41_6353 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ex4_ptfault_latch | tri_rlmlatch_p_6354 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ra_entry_latch | tri_rlmreg_p__parameterized4_6355 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_rd_array_data_latch | tri_rlmreg_p__parameterized45_6356 | 18 | 18 | 0 | 0 | 68 | 0 | 0 | 0 | | ex4_rd_cam_data_latch | tri_rlmreg_p__parameterized44_6357 | 31 | 31 | 0 | 0 | 84 | 0 | 0 | 0 | | ex4_rpn_latch | tri_rlmreg_p__parameterized53_6358 | 82 | 82 | 0 | 0 | 30 | 0 | 0 | 0 | | ex4_setHold_latch | tri_rlmlatch_p_6359 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_state_latch | tri_rlmreg_p__parameterized9_6360 | 17 | 17 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_stg_act_latch | tri_rlmlatch_p_6361 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlb_excp_det_latch | tri_rlmlatch_p_6362 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlb_multihit_latch | tri_rlmlatch_p_6363 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlb_par_err_latch | tri_rlmlatch_p_6364 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlbinelig_latch | tri_rlmlatch_p_6365 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlbmiss_latch | tri_rlmlatch_p_6366 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_tlbsel_latch | tri_rlmreg_p__parameterized2_6367 | 7 | 7 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ttype_latch | tri_rlmreg_p__parameterized227_6368 | 20 | 20 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_valid_latch | tri_rlmreg_p__parameterized37_6369 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_valid_op_latch | tri_rlmreg_p__parameterized37_6370 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wimge_latch | tri_rlmreg_p__parameterized4_6371 | 11 | 11 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_ws_latch | tri_rlmreg_p__parameterized2_6372 | 112 | 112 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_data_out_latch | tri_rlmreg_p__parameterized33_6373 | 63 | 63 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_deen_latch | tri_rlmreg_p__parameterized0_6374 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_emq_excp_rpt_latch | tri_rlmreg_p__parameterized9_6375 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_emq_latch | tri_rlmreg_p__parameterized9_6376 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_epn_latch | tri_rlmreg_p__parameterized34_6377 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | ex5_extclass_latch | tri_rlmreg_p__parameterized2_6378 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_fir_multihit_latch | tri_rlmreg_p__parameterized37_6379 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_fir_parerr_latch | tri_rlmreg_p__parameterized9_6380 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_itag_latch | tri_rlmreg_p__parameterized13_6381 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex5_lpid_latch | tri_rlmreg_p__parameterized12_6382 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_parerr_latch | tri_rlmreg_p__parameterized0_6383 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_pfetch_val_latch | tri_rlmreg_p__parameterized37_6384 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_pid_latch | tri_rlmreg_p__parameterized41_6385 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ex5_state_latch | tri_rlmreg_p__parameterized9_6386 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_stg_act_latch | tri_rlmlatch_p_6387 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_thdid_latch | tri_rlmreg_p__parameterized37_6388 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlb_excp_val_latch | tri_rlmreg_p__parameterized37_6389 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlbreq_nonspec_latch | tri_rlmlatch_p_6390 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlbreq_ttype_latch | tri_rlmreg_p__parameterized2_6391 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_tlbreq_val_latch | tri_rlmlatch_p_6392 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_tlbsel_latch | tri_rlmreg_p__parameterized2_6393 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_ttype_latch | tri_rlmreg_p__parameterized227_6394 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_valid_latch | tri_rlmreg_p__parameterized37_6395 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_valid_op_latch | tri_rlmreg_p__parameterized37_6396 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ws_latch | tri_rlmreg_p__parameterized2_6397 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_deen_latch | tri_rlmreg_p__parameterized0_6398 | 5 | 5 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_emq_excp_rpt_latch | tri_rlmreg_p__parameterized9_6399 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_extclass_latch | tri_rlmreg_p__parameterized2_6400 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_itag_latch | tri_rlmreg_p__parameterized13_6401 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex6_pfetch_val_latch | tri_rlmreg_p__parameterized37_6402 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_pid_latch | tri_rlmreg_p__parameterized41_6403 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ex6_state_latch | tri_rlmreg_p__parameterized9_6404 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_stg_act_latch | tri_rlmlatch_p_6405 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_tlb_excp_val_latch | tri_rlmreg_p__parameterized37_6406 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_tlbsel_latch | tri_rlmreg_p__parameterized2_6407 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ttype_latch | tri_rlmreg_p__parameterized227_6408 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_valid_latch | tri_rlmreg_p__parameterized37_6409 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_valid_op_latch | tri_rlmreg_p__parameterized37_6410 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ws_latch | tri_rlmreg_p__parameterized2_6411 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_deen_latch | tri_rlmreg_p__parameterized0_6412 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | ex7_extclass_latch | tri_rlmreg_p__parameterized2_6413 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_pfetch_val_latch | tri_rlmreg_p__parameterized37_6414 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_pid_latch | tri_rlmreg_p__parameterized41_6415 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | | ex7_state_latch | tri_rlmreg_p__parameterized9_6416 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_tlbsel_latch | tri_rlmreg_p__parameterized2_6417 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_ttype_latch | tri_rlmreg_p__parameterized227_6418 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex7_valid_latch | tri_rlmreg_p__parameterized37_6419 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_valid_op_latch | tri_rlmreg_p__parameterized37_6420 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_ws_latch | tri_rlmreg_p__parameterized2_6421 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_pfetch_val_latch | tri_rlmreg_p__parameterized37_6422 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_tlbsel_latch | tri_rlmreg_p__parameterized2_6423 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_ttype_latch | tri_rlmreg_p__parameterized227_6424 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_valid_latch | tri_rlmreg_p__parameterized37_6425 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_valid_op_latch | tri_rlmreg_p__parameterized37_6426 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | isync_val_latch | tri_rlmreg_p__parameterized2_6427 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lq_xu_ord_read_done_latch | tri_rlmlatch_p_6428 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_ord_write_done_latch | tri_rlmlatch_p_6429 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lru_latch | tri_rlmreg_p__parameterized214_6430 | 46 | 46 | 0 | 0 | 31 | 0 | 0 | 0 | | lru_rmt_vec_latch | tri_rlmreg_p__parameterized17_6431 | 180 | 180 | 0 | 0 | 32 | 0 | 0 | 0 | | lru_update_event_latch | tri_rlmreg_p__parameterized6_6432 | 17 | 17 | 0 | 0 | 10 | 0 | 0 | 0 | | mchk_flash_inv_latch | tri_rlmreg_p__parameterized9_6433 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | mm_int_rpt_lratmiss_latch | tri_rlmlatch_p_6434 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_lru_par_err_latch | tri_rlmlatch_p_6435 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_ptfault_latch | tri_rlmlatch_p_6436 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_tlb_multihit_latch | tri_rlmlatch_p_6437 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_tlb_par_err_latch | tri_rlmlatch_p_6438 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_tlbinelig_latch | tri_rlmlatch_p_6439 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_int_rpt_tlbmiss_latch | tri_rlmlatch_p_6440 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmucr1_latch | tri_rlmreg_p__parameterized6_6441 | 227 | 227 | 0 | 0 | 10 | 0 | 0 | 0 | | pc_xu_init_reset_latch | tri_rlmlatch_p_6442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | por_seq_latch | tri_rlmreg_p__parameterized5_6443 | 94 | 94 | 0 | 0 | 3 | 0 | 0 | 0 | | ra_entry_latch | tri_rlmreg_p__parameterized4_6444 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | rel_data_latch | tri_rlmreg_p__parameterized49_6445 | 127 | 127 | 0 | 0 | 127 | 0 | 0 | 0 | | rel_emq_latch | tri_rlmreg_p__parameterized9_6446 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | rel_hit_latch | tri_rlmlatch_p_6447 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel_int_upd_val_latch | tri_rlmreg_p__parameterized9_6448 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | rel_val_latch | tri_rlmreg_p__parameterized9_6449 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | rpn_holdreg[0].rpn_holdreg_latch | tri_rlmreg_p__parameterized33_6450 | 26 | 26 | 0 | 0 | 51 | 0 | 0 | 0 | | rs_data_latch | tri_rlmreg_p__parameterized33_6451 | 142 | 142 | 0 | 0 | 64 | 0 | 0 | 0 | | rv1_binv_val_latch | tri_rlmlatch_p_6452 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_csync_val_latch | tri_rlmlatch_p_6453 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_eplc_wr_val_latch | tri_rlmreg_p__parameterized37_6454 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_epsc_wr_val_latch | tri_rlmreg_p__parameterized37_6455 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_isync_val_latch | tri_rlmlatch_p_6456 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_rel_val_latch | tri_rlmreg_p__parameterized9_6457 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | rv1_snoop_val_latch | tri_rlmlatch_p_6458 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_ttype_latch | tri_rlmreg_p__parameterized9_6459 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | rv1_ttype_val_latch | tri_rlmreg_p__parameterized37_6460 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rw_entry_latch | tri_rlmreg_p__parameterized4_6461 | 76 | 76 | 0 | 0 | 5 | 0 | 0 | 0 | | rw_entry_le_latch | tri_rlmlatch_p_6462 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rw_entry_val_latch | tri_rlmlatch_p_6463 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | snoop_addr_latch | tri_rlmreg_p__parameterized34_6464 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | snoop_attr_latch | tri_rlmreg_p__parameterized48_6465 | 8 | 8 | 0 | 0 | 26 | 0 | 0 | 0 | | snoop_val_latch | tri_rlmreg_p__parameterized5_6466 | 177 | 177 | 0 | 0 | 3 | 0 | 0 | 0 | | snoopp_act_latch | tri_rlmlatch_p_6467 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | snoopp_attr_latch | tri_rlmreg_p__parameterized48_6468 | 26 | 26 | 0 | 0 | 26 | 0 | 0 | 0 | | snoopp_val_latch | tri_rlmlatch_p_6469 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | snoopp_vpn_latch | tri_rlmreg_p__parameterized34_6470 | 52 | 52 | 0 | 0 | 52 | 0 | 0 | 0 | | spr_ccr2_notlb_latch | tri_rlmlatch_p_6471 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_cm_latch | tri_rlmreg_p__parameterized37_6472 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_ds_latch | tri_rlmreg_p__parameterized37_6473 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_hv_latch | tri_rlmreg_p__parameterized37_6474 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_pr_latch | tri_rlmreg_p__parameterized37_6475 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_rel_act_latch | tri_rlmlatch_p_6476 | 129 | 129 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_rel_data_latch | tri_rlmreg_p__parameterized49_6477 | 9 | 9 | 0 | 0 | 127 | 0 | 0 | 0 | | tlb_rel_emq_latch | tri_rlmreg_p__parameterized9_6478 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_rel_val_latch | tri_rlmreg_p__parameterized4_6479 | 91 | 91 | 0 | 0 | 5 | 0 | 0 | 0 | | ttype_latch | tri_rlmreg_p__parameterized9_6480 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ttype_val_latch | tri_rlmreg_p__parameterized37_6481 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | watermark_latch | tri_rlmreg_p__parameterized210 | 22 | 22 | 0 | 0 | 5 | 0 | 0 | 0 | | ws_latch | tri_rlmreg_p__parameterized2_6482 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xu_lq_act_latch | tri_rlmlatch_p_6483 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_is_eratre_latch | tri_rlmlatch_p_6484 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_is_eratsx_latch | tri_rlmlatch_p_6485 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_is_eratwe_latch | tri_rlmlatch_p_6486 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_ra_entry_latch | tri_rlmreg_p__parameterized4_6487 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | xu_lq_rs_data_latch | tri_rlmreg_p__parameterized33_6488 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | xu_lq_val_latch | tri_rlmreg_p__parameterized37_6489 | 75 | 75 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_ws_latch | tri_rlmreg_p__parameterized2_6490 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xucr4_mmu_mchk_latch | tri_rlmlatch_p__parameterized1_6491 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dir | lq_dir | 9013 | 9013 | 0 | 0 | 3128 | 0 | 0 | 0 | | l1dcdl | lq_dir_lru | 2190 | 2190 | 0 | 0 | 777 | 0 | 0 | 0 | | congr_cl_act_reg | tri_rlmlatch_p_6109 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_ex4_ex5_cmp_reg | tri_rlmlatch_p_6110 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_ex6_cmp_reg | tri_rlmlatch_p_6111 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_stq3_cmp_reg | tri_rlmlatch_p_6112 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_stq4_cmp_reg | tri_rlmlatch_p_6113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[0].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6114 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[10].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6115 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[11].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6116 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[12].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6117 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[13].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6118 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[14].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6119 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[15].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6120 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[16].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6121 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[17].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6122 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[18].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6123 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[19].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6124 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[1].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6125 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[20].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6126 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[21].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6127 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[22].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6128 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[23].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6129 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[24].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6130 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[25].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6131 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[26].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6132 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[27].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6133 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[28].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6134 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[29].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6135 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[2].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6136 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[30].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6137 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[31].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6138 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[32].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6139 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[33].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6140 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[34].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6141 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[35].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6142 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[36].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6143 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[37].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6144 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[38].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6145 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[39].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6146 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[3].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6147 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[40].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6148 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[41].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6149 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[42].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6150 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[43].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6151 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[44].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6152 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[45].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6153 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[46].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6154 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[47].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6155 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[48].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6156 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[49].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6157 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[4].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6158 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[50].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6159 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[51].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6160 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[52].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6161 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[53].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6162 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[54].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6163 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[55].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6164 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[56].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6165 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[57].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6166 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[58].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6167 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[59].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6168 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[5].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6169 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[60].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6170 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[61].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6171 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[62].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6172 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[63].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6173 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[6].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6174 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[7].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6175 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[8].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6176 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_lru.congr_cl_lru[9].congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6177 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | congr_cl_stq2_ex5_cmp_reg | tri_rlmlatch_p_6178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_ex6_cmp_reg | tri_rlmlatch_p_6179 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_stq3_cmp_reg | tri_rlmlatch_p_6180 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_stq4_cmp_reg | tri_rlmlatch_p_6181 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_congr_cl_reg | tri_rlmreg_p__parameterized0_6182 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_c_acc_reg | tri_rlmlatch_p_6183 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_congr_cl_reg | tri_rlmreg_p__parameterized0_6184 | 278 | 278 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_lru_upd_reg | tri_rlmlatch_p_6185 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_c_acc_reg | tri_rlmlatch_p_6186 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_congr_cl_reg | tri_rlmreg_p__parameterized0_6187 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_c_acc_reg | tri_rlmlatch_p_6188 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_congr_cl_reg | tri_rlmreg_p__parameterized0_6189 | 908 | 908 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_lru_upd_reg | tri_rlmreg_p__parameterized13_6190 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldst_hit_vector_reg | tri_rlmreg_p__parameterized12_6191 | 40 | 40 | 0 | 0 | 8 | 0 | 0 | 0 | | lq_congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6192 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | rel2_clr_stg_val_reg | tri_rlmlatch_p_6193 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_data_stg_val_reg | tri_rlmlatch_p_6194 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_lock_en_reg | tri_rlmlatch_p_6195 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_rel_tag_reg | tri_rlmreg_p__parameterized9_6196 | 59 | 59 | 0 | 0 | 4 | 0 | 0 | 0 | | rel2_set_stg_val_reg | tri_rlmlatch_p_6197 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_xucr2_rmt_reg | tri_rlmreg_p__parameterized17_6198 | 16 | 16 | 0 | 0 | 32 | 0 | 0 | 0 | | rel3_clr_stg_val_reg | tri_rlmlatch_p_6199 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_data_stg_val_reg | tri_rlmlatch_p_6200 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_lock_en_reg | tri_rlmlatch_p_6201 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_m_q_way_reg | tri_rlmreg_p__parameterized12_6202 | 81 | 81 | 0 | 0 | 8 | 0 | 0 | 0 | | rel3_rel_tag_reg | tri_rlmreg_p__parameterized9_6203 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | rel3_set_stg_val_reg | tri_rlmlatch_p_6204 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_wlock_reg | tri_rlmreg_p__parameterized12_6205 | 14 | 14 | 0 | 0 | 8 | 0 | 0 | 0 | | rel4_dir_way_upd_reg | tri_rlmreg_p__parameterized12_6206 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | rel_congr_cl_lru_reg | tri_rlmreg_p__parameterized13_6207 | 10 | 10 | 0 | 0 | 7 | 0 | 0 | 0 | | rel_val_qsel_reg | tri_rlmlatch_p_6208 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | rel_way_qsel_reg | tri_rlmreg_p__parameterized12_6209 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[0].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6210 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[1].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6211 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[2].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6212 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[3].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6213 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[4].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6214 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[5].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6215 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[6].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6216 | 22 | 22 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_congr_cl.reld_q_congr_cl[7].reld_q_congr_cl_reg | tri_rlmreg_p__parameterized0_6217 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | reld_q_lock_reg | tri_rlmreg_p__parameterized12_6218 | 44 | 44 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_sel_reg | tri_rlmreg_p__parameterized12_6219 | 58 | 58 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_val_reg | tri_rlmreg_p__parameterized12_6220 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[0].reld_q_way_reg | tri_rlmreg_p__parameterized12_6221 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[1].reld_q_way_reg | tri_rlmreg_p__parameterized12_6222 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[2].reld_q_way_reg | tri_rlmreg_p__parameterized12_6223 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[3].reld_q_way_reg | tri_rlmreg_p__parameterized12_6224 | 22 | 22 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[4].reld_q_way_reg | tri_rlmreg_p__parameterized12_6225 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[5].reld_q_way_reg | tri_rlmreg_p__parameterized12_6226 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[6].reld_q_way_reg | tri_rlmreg_p__parameterized12_6227 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | reld_q_way.reld_q_way[7].reld_q_way_reg | tri_rlmreg_p__parameterized12_6228 | 15 | 15 | 0 | 0 | 8 | 0 | 0 | 0 | | spr_xucr0_wlk_reg | tri_rlmlatch_p_6229 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_class_id_reg | tri_rlmreg_p__parameterized2_6230 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | stq2_congr_cl_reg | tri_rlmreg_p__parameterized0_6231 | 278 | 278 | 0 | 0 | 6 | 0 | 0 | 0 | | stq2_val_reg | tri_rlmlatch_p_6232 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_congr_cl_reg | tri_rlmreg_p__parameterized0_6233 | 63 | 63 | 0 | 0 | 6 | 0 | 0 | 0 | | stq3_val_reg | tri_rlmlatch_p_6234 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_congr_cl_reg | tri_rlmreg_p__parameterized0_6235 | 72 | 72 | 0 | 0 | 6 | 0 | 0 | 0 | | stq4_dcarr_way_en_reg | tri_rlmreg_p__parameterized12_6236 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_lru_upd_reg | tri_rlmreg_p__parameterized13_6237 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | stq4_val_wen_reg | tri_rlmlatch_p_6238 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xucr0_clo_reg | tri_rlmlatch_p_6239 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | l1dcdt | lq_dir_tag | 163 | 163 | 0 | 0 | 127 | 0 | 0 | 0 | | (l1dcdt) | lq_dir_tag | 57 | 57 | 0 | 0 | 0 | 0 | 0 | 0 | | ex3_binv_val_reg | tri_rlmlatch_p_6101 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_en_par_chk_reg | tri_rlmreg_p__parameterized12_6102 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | | inj_ddir_ldp_parity_reg | tri_rlmlatch_p_6103 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_ddir_stp_parity_reg | tri_rlmlatch_p_6104 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_addr_reg | tri_rlmreg_p__parameterized52_6105 | 36 | 36 | 0 | 0 | 36 | 0 | 0 | 0 | | stq3_addr_reg | tri_rlmreg_p__parameterized52_6106 | 36 | 36 | 0 | 0 | 36 | 0 | 0 | 0 | | stq3_en_par_chk_reg | tri_rlmreg_p__parameterized12_6107 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_addr_reg | tri_rlmreg_p__parameterized52_6108 | 6 | 6 | 0 | 0 | 36 | 0 | 0 | 0 | | l1dcdv | lq_dir_val | 6649 | 6649 | 0 | 0 | 2221 | 0 | 0 | 0 | | binv5_ex5_dir_val_reg | tri_rlmlatch_p_5356 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | binv6_ex6_dir_data_reg | tri_rlmreg_p__parameterized2_5357 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | binv7_ex7_dir_data_reg | tri_rlmreg_p__parameterized2_5358 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | congr_cl_all_act_reg | tri_rlmlatch_p_5359 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex3_ex4_cmp_reg | tri_rlmlatch_p_5360 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex3_ex5_cmp_reg | tri_rlmlatch_p_5361 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex3_ex6_cmp_reg | tri_rlmlatch_p_5362 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex3_stq4_cmp_reg | tri_rlmlatch_p_5363 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex3_stq5_cmp_reg | tri_rlmlatch_p_5364 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_ex5_cmp_reg | tri_rlmlatch_p_5365 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_ex6_cmp_reg | tri_rlmlatch_p_5366 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex4_ex6_rest_reg | tri_rlmlatch_p_5367 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex5_ex6_cmp_reg | tri_rlmlatch_p_5368 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex5_ex7_cmp_reg | tri_rlmlatch_p_5369 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex5_stq5_cmp_reg | tri_rlmlatch_p_5370 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex5_stq6_cmp_reg | tri_rlmlatch_p_5371 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_ex5_stq7_cmp_reg | tri_rlmlatch_p_5372 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_ex5_cmp_reg | tri_rlmlatch_p_5373 | 49 | 49 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_ex6_cmp_reg | tri_rlmlatch_p_5374 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_stq3_cmp_reg | tri_rlmlatch_p_5375 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_stq4_cmp_reg | tri_rlmlatch_p_5376 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq2_stq5_cmp_reg | tri_rlmlatch_p_5377 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq3_ex5_cmp_reg | tri_rlmlatch_p_5378 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq3_ex6_cmp_reg | tri_rlmlatch_p_5379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq3_stq4_cmp_reg | tri_rlmlatch_p_5380 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_stq4_ex5_cmp_reg | tri_rlmlatch_p_5381 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[0].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5382 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[10].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5383 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[11].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5384 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[12].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5385 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[13].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5386 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[14].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5387 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[15].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5388 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[16].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5389 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[17].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5390 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[18].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5391 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[19].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5392 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[1].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5393 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[20].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5394 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[21].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5395 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[22].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5396 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[23].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5397 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[24].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5398 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[25].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5399 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[26].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5400 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[27].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5401 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[28].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5402 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[29].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5403 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[2].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5404 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[30].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5405 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[31].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5406 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[32].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5407 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[33].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5408 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[34].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5409 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[35].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5410 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[36].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5411 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[37].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5412 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[38].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5413 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[39].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5414 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[3].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5415 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[40].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5416 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[41].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5417 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[42].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5418 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[43].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5419 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[44].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5420 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[45].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5421 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[46].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5422 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[47].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5423 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[48].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5424 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[49].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5425 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[4].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5426 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[50].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5427 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[51].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5428 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[52].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5429 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[53].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5430 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[54].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5431 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[55].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5432 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[56].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5433 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[57].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5434 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[58].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5435 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[59].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5436 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[5].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5437 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[60].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5438 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[61].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5439 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[62].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5440 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[63].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5441 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[6].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5442 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[7].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5443 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[8].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5444 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wA.congr_cl_wA[9].congr_cl_wA_reg | tri_rlmreg_p__parameterized5_5445 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[0].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5446 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[10].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5447 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[11].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5448 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[12].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5449 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[13].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5450 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[14].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5451 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[15].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5452 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[16].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5453 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[17].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5454 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[18].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5455 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[19].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5456 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[1].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5457 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[20].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5458 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[21].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5459 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[22].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5460 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[23].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5461 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[24].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5462 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[25].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5463 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[26].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5464 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[27].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5465 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[28].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5466 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[29].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5467 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[2].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5468 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[30].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5469 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[31].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5470 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[32].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5471 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[33].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5472 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[34].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5473 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[35].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5474 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[36].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5475 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[37].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5476 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[38].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5477 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[39].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5478 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[3].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5479 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[40].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5480 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[41].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5481 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[42].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5482 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[43].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5483 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[44].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5484 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[45].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5485 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[46].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5486 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[47].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5487 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[48].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5488 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[49].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5489 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[4].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5490 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[50].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5491 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[51].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5492 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[52].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5493 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[53].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5494 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[54].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5495 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[55].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5496 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[56].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5497 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[57].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5498 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[58].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5499 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[59].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5500 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[5].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5501 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[60].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5502 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[61].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5503 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[62].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5504 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[63].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5505 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[6].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5506 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[7].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5507 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[8].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5508 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wB.congr_cl_wB[9].congr_cl_wB_reg | tri_rlmreg_p__parameterized5_5509 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[0].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5510 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[10].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5511 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[11].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5512 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[12].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5513 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[13].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5514 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[14].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5515 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[15].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5516 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[16].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5517 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[17].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5518 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[18].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5519 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[19].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5520 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[1].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5521 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[20].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5522 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[21].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5523 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[22].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5524 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[23].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5525 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[24].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5526 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[25].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5527 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[26].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5528 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[27].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5529 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[28].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5530 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[29].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5531 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[2].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5532 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[30].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5533 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[31].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5534 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[32].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5535 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[33].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5536 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[34].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5537 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[35].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5538 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[36].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5539 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[37].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5540 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[38].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5541 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[39].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5542 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[3].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5543 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[40].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5544 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[41].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5545 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[42].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5546 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[43].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5547 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[44].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5548 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[45].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5549 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[46].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5550 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[47].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5551 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[48].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5552 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[49].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5553 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[4].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5554 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[50].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5555 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[51].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5556 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[52].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5557 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[53].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5558 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[54].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5559 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[55].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5560 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[56].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5561 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[57].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5562 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[58].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5563 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[59].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5564 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[5].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5565 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[60].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5566 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[61].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5567 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[62].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5568 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[63].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5569 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[6].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5570 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[7].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5571 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[8].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5572 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wC.congr_cl_wC[9].congr_cl_wC_reg | tri_rlmreg_p__parameterized5_5573 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[0].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5574 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[10].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5575 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[11].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5576 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[12].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5577 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[13].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5578 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[14].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5579 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[15].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5580 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[16].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5581 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[17].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5582 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[18].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5583 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[19].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5584 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[1].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5585 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[20].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5586 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[21].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5587 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[22].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5588 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[23].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5589 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[24].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5590 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[25].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5591 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[26].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5592 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[27].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5593 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[28].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5594 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[29].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5595 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[2].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5596 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[30].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5597 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[31].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5598 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[32].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5599 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[33].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5600 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[34].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5601 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[35].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5602 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[36].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5603 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[37].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5604 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[38].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5605 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[39].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5606 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[3].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5607 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[40].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5608 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[41].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5609 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[42].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5610 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[43].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5611 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[44].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5612 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[45].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5613 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[46].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5614 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[47].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5615 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[48].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5616 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[49].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5617 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[4].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5618 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[50].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5619 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[51].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5620 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[52].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5621 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[53].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5622 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[54].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5623 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[55].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5624 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[56].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5625 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[57].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5626 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[58].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5627 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[59].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5628 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[5].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5629 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[60].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5630 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[61].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5631 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[62].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5632 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[63].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5633 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[6].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5634 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[7].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5635 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[8].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5636 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wD.congr_cl_wD[9].congr_cl_wD_reg | tri_rlmreg_p__parameterized5_5637 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[0].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5638 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[10].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5639 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[11].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5640 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[12].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5641 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[13].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5642 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[14].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5643 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[15].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5644 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[16].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5645 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[17].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5646 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[18].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5647 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[19].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5648 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[1].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5649 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[20].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5650 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[21].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5651 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[22].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5652 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[23].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5653 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[24].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5654 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[25].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5655 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[26].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5656 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[27].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5657 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[28].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5658 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[29].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5659 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[2].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5660 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[30].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5661 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[31].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5662 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[32].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5663 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[33].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5664 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[34].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5665 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[35].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5666 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[36].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5667 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[37].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5668 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[38].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5669 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[39].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5670 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[3].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5671 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[40].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5672 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[41].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5673 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[42].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5674 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[43].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5675 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[44].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5676 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[45].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5677 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[46].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5678 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[47].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5679 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[48].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5680 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[49].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5681 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[4].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5682 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[50].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5683 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[51].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5684 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[52].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5685 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[53].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5686 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[54].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5687 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[55].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5688 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[56].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5689 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[57].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5690 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[58].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5691 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[59].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5692 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[5].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5693 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[60].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5694 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[61].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5695 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[62].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5696 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[63].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5697 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[6].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5698 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[7].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5699 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[8].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5700 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wE.congr_cl_wE[9].congr_cl_wE_reg | tri_rlmreg_p__parameterized5_5701 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[0].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5702 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[10].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5703 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[11].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5704 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[12].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5705 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[13].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5706 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[14].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5707 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[15].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5708 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[16].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5709 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[17].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5710 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[18].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5711 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[19].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5712 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[1].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5713 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[20].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5714 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[21].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5715 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[22].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5716 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[23].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5717 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[24].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5718 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[25].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5719 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[26].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5720 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[27].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5721 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[28].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5722 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[29].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5723 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[2].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5724 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[30].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5725 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[31].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5726 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[32].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5727 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[33].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5728 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[34].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5729 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[35].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5730 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[36].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5731 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[37].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5732 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[38].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5733 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[39].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5734 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[3].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5735 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[40].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5736 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[41].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5737 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[42].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5738 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[43].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5739 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[44].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5740 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[45].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5741 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[46].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5742 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[47].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5743 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[48].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5744 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[49].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5745 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[4].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5746 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[50].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5747 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[51].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5748 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[52].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5749 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[53].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5750 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[54].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5751 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[55].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5752 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[56].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5753 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[57].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5754 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[58].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5755 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[59].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5756 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[5].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5757 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[60].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5758 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[61].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5759 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[62].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5760 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[63].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5761 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[6].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5762 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[7].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5763 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[8].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5764 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wF.congr_cl_wF[9].congr_cl_wF_reg | tri_rlmreg_p__parameterized5_5765 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[0].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5766 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[10].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5767 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[11].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5768 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[12].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5769 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[13].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5770 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[14].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5771 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[15].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5772 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[16].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5773 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[17].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5774 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[18].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5775 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[19].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5776 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[1].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5777 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[20].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5778 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[21].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5779 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[22].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5780 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[23].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5781 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[24].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5782 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[25].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5783 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[26].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5784 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[27].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5785 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[28].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5786 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[29].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5787 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[2].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5788 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[30].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5789 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[31].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5790 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[32].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5791 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[33].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5792 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[34].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5793 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[35].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5794 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[36].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5795 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[37].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5796 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[38].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5797 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[39].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5798 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[3].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5799 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[40].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5800 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[41].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5801 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[42].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5802 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[43].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5803 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[44].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5804 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[45].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5805 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[46].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5806 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[47].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5807 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[48].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5808 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[49].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5809 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[4].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5810 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[50].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5811 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[51].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5812 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[52].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5813 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[53].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5814 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[54].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5815 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[55].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5816 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[56].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5817 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[57].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5818 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[58].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5819 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[59].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5820 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[5].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5821 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[60].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5822 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[61].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5823 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[62].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5824 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[63].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5825 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[6].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5826 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[7].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5827 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[8].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5828 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wG.congr_cl_wG[9].congr_cl_wG_reg | tri_rlmreg_p__parameterized5_5829 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[0].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5830 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[10].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5831 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[11].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5832 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[12].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5833 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[13].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5834 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[14].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5835 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[15].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5836 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[16].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5837 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[17].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5838 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[18].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5839 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[19].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5840 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[1].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5841 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[20].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5842 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[21].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5843 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[22].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5844 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[23].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5845 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[24].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5846 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[25].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5847 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[26].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5848 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[27].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5849 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[28].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5850 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[29].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5851 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[2].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5852 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[30].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5853 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[31].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5854 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[32].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5855 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[33].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5856 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[34].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5857 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[35].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5858 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[36].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5859 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[37].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5860 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[38].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5861 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[39].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5862 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[3].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5863 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[40].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5864 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[41].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5865 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[42].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5866 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[43].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5867 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[44].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5868 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[45].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5869 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[46].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5870 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[47].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5871 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[48].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5872 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[49].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5873 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[4].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5874 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[50].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5875 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[51].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5876 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[52].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5877 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[53].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5878 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[54].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5879 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[55].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5880 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[56].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5881 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[57].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5882 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[58].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5883 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[59].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5884 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[5].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5885 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[60].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5886 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[61].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5887 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[62].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5888 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[63].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5889 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[6].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5890 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[7].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5891 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[8].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5892 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | congr_cl_wH.congr_cl_wH[9].congr_cl_wH_reg | tri_rlmreg_p__parameterized5_5893 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_binv_val_reg | tri_rlmlatch_p_5894 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_congr_cl_reg | tri_regk__parameterized11 | 978 | 978 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_thrd_id_reg | tri_regk__parameterized2_5895 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_binv_val_reg | tri_rlmlatch_p_5896 | 33 | 33 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_cache_acc_reg | tri_rlmlatch_p_5897 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_congr_cl_reg | tri_rlmreg_p__parameterized0_5898 | 16 | 16 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_larx_val_reg | tri_rlmlatch_p_5899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lock_set_reg | tri_rlmlatch_p_5900 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_pfetch_val_reg | tri_rlmlatch_p_5901 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stq2_congr_cl_m_reg | tri_rlmlatch_p_5902 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stq3_set_rel_coll_reg | tri_rlmlatch_p_5903 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stq4_set_rel_coll_reg | tri_rlmlatch_p_5904 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_thrd_id_reg | tri_rlmreg_p__parameterized37_5905 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_watch_set_reg | tri_rlmlatch_p_5906 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[0].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5907 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[1].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5908 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[2].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5909 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[3].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5910 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[4].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5911 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[5].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5912 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[6].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5913 | 13 | 13 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_way_val.ex4_way_val[7].ex4_way_val_reg | tri_rlmreg_p__parameterized5_5914 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_xuop_upd_val_reg | tri_rlmlatch_p_5915 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_binv_val_reg | tri_rlmlatch_p_5916 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_cClass_lock_set_reg | tri_regk__parameterized2_5917 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_cClass_thrd_watch_reg | tri_regk__parameterized2_5918 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_clr_lck_way_reg | tri_regk__parameterized14_5919 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_congr_cl_reg | tri_regk__parameterized11_5920 | 76 | 76 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_cr_watch_reg | tri_regk__parameterized2_5921 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dc_perr_det_reg | tri_rlmlatch_p_5922 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dc_perr_flush_reg | tri_rlmlatch_p_5923 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dir_multihit_val_b_reg | tri_rlmlatch_p_5924 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dir_perr_det_reg | tri_rlmlatch_p_5925 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dir_perr_flush_reg | tri_rlmlatch_p_5926 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[0].ex5_dir_way_reg | tri_regk__parameterized9 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[1].ex5_dir_way_reg | tri_regk__parameterized9_5927 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[2].ex5_dir_way_reg | tri_regk__parameterized9_5928 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[3].ex5_dir_way_reg | tri_regk__parameterized9_5929 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[4].ex5_dir_way_reg | tri_regk__parameterized9_5930 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[5].ex5_dir_way_reg | tri_regk__parameterized9_5931 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[6].ex5_dir_way_reg | tri_regk__parameterized9_5932 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_dir_way.ex5_dir_way[7].ex5_dir_way_reg | tri_regk__parameterized9_5933 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_err_det_way_reg | tri_rlmreg_p__parameterized12_5934 | 72 | 72 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_lock_set_reg | tri_rlmlatch_p_5935 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_lose_watch_reg | tri_regk__parameterized2_5936 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mhit_cacc_reg | tri_rlmlatch_p_5937 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_perr_lock_lost_reg | tri_rlmlatch_p_5938 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_perr_watchlost_reg | tri_rlmreg_p__parameterized37_5939 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_stp_perr_flush_reg | tri_rlmlatch_p_5940 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_watch_set_reg | tri_rlmlatch_p_5941 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_way_hit_reg | tri_regk__parameterized14_5942 | 29 | 29 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_way_perr_det_reg | tri_rlmlatch_p_5943 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_way_upd_reg | tri_regk__parameterized14_5944 | 53 | 53 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[0].ex5_way_val_reg | tri_regk__parameterized9_5945 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[1].ex5_way_val_reg | tri_regk__parameterized9_5946 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[2].ex5_way_val_reg | tri_regk__parameterized9_5947 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[3].ex5_way_val_reg | tri_regk__parameterized9_5948 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[4].ex5_way_val_reg | tri_regk__parameterized9_5949 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[5].ex5_way_val_reg | tri_regk__parameterized9_5950 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[6].ex5_way_val_reg | tri_regk__parameterized9_5951 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_way_val.ex5_way_val[7].ex5_way_val_reg | tri_regk__parameterized9_5952 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_xuop_upd_val_reg | tri_rlmlatch_p_5953 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[0].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5954 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[1].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5955 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[2].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5956 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[3].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5957 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[4].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5958 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[5].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5959 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[6].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5960 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_dir_way.ex6_dir_way[7].ex6_dir_way_reg | tri_rlmreg_p__parameterized5_5961 | 384 | 384 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_watch_set_reg | tri_rlmlatch_p_5962 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_way_upd_reg | tri_rlmreg_p__parameterized12_5963 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[0].ex7_dir_way_reg | tri_regk__parameterized2_5964 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[1].ex7_dir_way_reg | tri_regk__parameterized2_5965 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[2].ex7_dir_way_reg | tri_regk__parameterized2_5966 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[3].ex7_dir_way_reg | tri_regk__parameterized2_5967 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[4].ex7_dir_way_reg | tri_regk__parameterized2_5968 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[5].ex7_dir_way_reg | tri_regk__parameterized2_5969 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[6].ex7_dir_way_reg | tri_regk__parameterized2_5970 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_dir_way.ex7_dir_way[7].ex7_dir_way_reg | tri_regk__parameterized2_5971 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_watch_set_inval_reg | tri_rlmlatch_p_5972 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_way_upd_reg | tri_regk__parameterized14_5973 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | inj_dirmultihit_ldp_reg | tri_rlmlatch_p_5974 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_dirmultihit_stp_reg | tri_rlmlatch_p_5975 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lock_finval_reg | tri_rlmlatch_p_5976 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | p0_congr_cl_act_reg | tri_rlmreg_p__parameterized33_5977 | 286 | 286 | 0 | 0 | 64 | 0 | 0 | 0 | | p0_wren_cpy_reg | tri_rlmlatch_p_5978 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | p0_wren_reg | tri_rlmlatch_p_5979 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | p0_wren_stg_reg | tri_rlmlatch_p_5980 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | p1_congr_cl_act_reg | tri_rlmreg_p__parameterized33_5981 | 259 | 259 | 0 | 0 | 64 | 0 | 0 | 0 | | p1_wren_cpy_reg | tri_rlmlatch_p_5982 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | p1_wren_reg | tri_rlmlatch_p_5983 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_back_inv_reg | tri_rlmlatch_p_5984 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_clr_stg_val_reg | tri_rlmlatch_p_5985 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_lock_set_reg | tri_rlmlatch_p_5986 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_set_stg_val_reg | tri_rlmlatch_p_5987 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_thrd_id_reg | tri_rlmreg_p__parameterized37_5988 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_watch_set_reg | tri_rlmlatch_p_5989 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_back_inv_reg | tri_regk__parameterized2_5990 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_clr_stg_val_reg | tri_rlmlatch_p_5991 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_lock_set_reg | tri_regk__parameterized2_5992 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_set_dir_val_reg | tri_rlmlatch_p_5993 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_set_stg_val_reg | tri_rlmlatch_p_5994 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_thrd_id_reg | tri_regk__parameterized2_5995 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_upd_val_reg | tri_regk__parameterized2_5996 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rel3_watch_set_reg | tri_regk__parameterized2_5997 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | rel4_all_watch_lost_reg | tri_rlmreg_p__parameterized37_5998 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rel4_clr_stg_val_reg | tri_rlmlatch_p_5999 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel4_set_dir_val_reg | tri_rlmlatch_p_6000 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel5_clr_stg_val_reg | tri_rlmlatch_p_6001 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_clfc_reg | tri_rlmlatch_p_6002 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stm_watchlost_state_reg | tri_rlmreg_p__parameterized37_6003 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_cen_acc_reg | tri_rlmlatch_p_6004 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_ci_reg | tri_rlmlatch_p_6005 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_congr_cl_reg | tri_rlmreg_p__parameterized0_6006 | 972 | 972 | 0 | 0 | 6 | 0 | 0 | 0 | | stq2_dci_val_reg | tri_rlmlatch_p_6007 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_inval_op_reg | tri_rlmlatch_p_6008 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_l_fld_b1_reg | tri_rlmlatch_p_6009 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_lock_clr_reg | tri_rlmlatch_p_6010 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_store_val_reg | tri_rlmlatch_p_6011 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_thrd_id_reg | tri_rlmreg_p__parameterized37_6012 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_val_reg | tri_rlmlatch_p_6013 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_watch_clr_all_reg | tri_rlmlatch_p_6014 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_watch_clr_reg | tri_rlmlatch_p_6015 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_congr_cl_reg | tri_regk__parameterized11_6016 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 | | stq3_dci_val_reg | tri_rlmlatch_p_6017 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_dir_upd_val_reg | tri_rlmlatch_p_6018 | 29 | 29 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_ex6_ldp_err_reg | tri_rlmreg_p__parameterized12_6019 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_inval_op_reg | tri_regk__parameterized2_6020 | 26 | 26 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_l_fld_b1_reg | tri_regk__parameterized2_6021 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_lock_clr_reg | tri_regk__parameterized2_6022 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_rel3_val_reg | tri_rlmlatch_p_6023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_store_val_reg | tri_regk__parameterized2_6024 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_stq5_stp_err_reg | tri_rlmreg_p__parameterized12_6025 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_thrd_id_reg | tri_regk__parameterized2_6026 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_val_reg | tri_rlmlatch_p_6027 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_watch_clr_all_reg | tri_regk__parameterized2_6028 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_watch_clr_reg | tri_regk__parameterized2_6029 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[0].stq3_way_val_reg | tri_regk__parameterized9_6030 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[1].stq3_way_val_reg | tri_regk__parameterized9_6031 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[2].stq3_way_val_reg | tri_regk__parameterized9_6032 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[3].stq3_way_val_reg | tri_regk__parameterized9_6033 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[4].stq3_way_val_reg | tri_regk__parameterized9_6034 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[5].stq3_way_val_reg | tri_regk__parameterized9_6035 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[6].stq3_way_val_reg | tri_regk__parameterized9_6036 | 46 | 46 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_way_val.stq3_way_val[7].stq3_way_val_reg | tri_regk__parameterized9_6037 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_cClass_lock_set_reg | tri_rlmlatch_p_6038 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_cClass_thrd_watch_reg | tri_rlmreg_p__parameterized37_6039 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_clr_lck_way_reg | tri_rlmreg_p__parameterized12_6040 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_congr_cl_reg | tri_rlmreg_p__parameterized0_6041 | 82 | 82 | 0 | 0 | 6 | 0 | 0 | 0 | | stq4_dci_val_reg | tri_rlmlatch_p_6042 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_dir_multihit_val_b_reg | tri_rlmlatch_p_6043 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_dir_perr_det_reg | tri_rlmlatch_p_6044 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_dir_upd_val_reg | tri_rlmlatch_p_6045 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[0].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6046 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[1].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6047 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[2].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6048 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[3].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6049 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[4].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6050 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[5].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6051 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[6].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6052 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_dir_way.stq4_dir_way[7].stq4_dir_way_reg | tri_rlmreg_p__parameterized5_6053 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | stq4_err_det_way_reg | tri_rlmreg_p__parameterized12_6054 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_ex6_ldp_err_reg | tri_rlmreg_p__parameterized12_6055 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_ex7_ldp_err_reg | tri_rlmreg_p__parameterized12_6056 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_l_fld_b1_reg | tri_rlmlatch_p_6057 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_lose_watch_reg | tri_rlmlatch_p_6058 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_perr_lock_lost_reg | tri_rlmlatch_p_6059 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_perr_watchlost_reg | tri_rlmreg_p__parameterized37_6060 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_rel4_val_reg | tri_rlmlatch_p_6061 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_rel_way_clr_reg | tri_rlmreg_p__parameterized12_6062 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_stq5_stp_err_reg | tri_rlmreg_p__parameterized12_6063 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_stq6_stp_err_reg | tri_rlmreg_p__parameterized12_6064 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_thrd_id_reg | tri_rlmreg_p__parameterized37_6065 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_val_reg | tri_rlmlatch_p_6066 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_watch_clr_all_reg | tri_rlmlatch_p_6067 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_hit_reg | tri_rlmreg_p__parameterized12_6068 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_way_upd_reg | tri_rlmreg_p__parameterized12_6069 | 42 | 42 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[0].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6070 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[1].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6071 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[2].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6072 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[3].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6073 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[4].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6074 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[5].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6075 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[6].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6076 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_way_val.stq4_way_val[7].stq4_way_val_reg | tri_rlmreg_p__parameterized37_6077 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_congr_cl_reg | tri_regk__parameterized11_6078 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | stq5_dir_err_val_reg | tri_rlmlatch_p_6079 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[0].stq5_dir_way_reg | tri_regk__parameterized9_6080 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[1].stq5_dir_way_reg | tri_regk__parameterized9_6081 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[2].stq5_dir_way_reg | tri_regk__parameterized9_6082 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[3].stq5_dir_way_reg | tri_regk__parameterized9_6083 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[4].stq5_dir_way_reg | tri_regk__parameterized9_6084 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[5].stq5_dir_way_reg | tri_regk__parameterized9_6085 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[6].stq5_dir_way_reg | tri_regk__parameterized9_6086 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_dir_way.stq5_dir_way[7].stq5_dir_way_reg | tri_regk__parameterized9_6087 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | stq5_way_perr_inval_reg | tri_rlmreg_p__parameterized12_6088 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | stq5_way_upd_reg | tri_regk__parameterized14_6089 | 40 | 40 | 0 | 0 | 8 | 0 | 0 | 0 | | stq6_congr_cl_reg | tri_rlmreg_p__parameterized0_6090 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | stq6_dir_data_reg | tri_rlmreg_p__parameterized2_6091 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | stq6_way_upd_reg | tri_rlmreg_p__parameterized12_6092 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | stq6_wren_reg | tri_rlmlatch_p_6093 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_dir_data_reg | tri_rlmreg_p__parameterized2_6094 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | stq7_way_upd_reg | tri_rlmreg_p__parameterized12_6095 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | stq7_wren_reg | tri_rlmlatch_p_6096 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | val_finval_reg | tri_rlmlatch_p_6097 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | watch_finval_reg | tri_rlmreg_p__parameterized37_6098 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | xucr0_cslc_binv_reg | tri_rlmlatch_p_6099 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xucr0_cslc_xuop_reg | tri_rlmlatch_p_6100 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rel4_dir_wr_val_reg | tri_rlmlatch_p_5353 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_cls_reg | tri_rlmlatch_p_5354 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_dcdis_reg | tri_rlmlatch_p_5355 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_1to0_reg | tri_plat__parameterized5 | 498 | 498 | 0 | 0 | 1 | 0 | 0 | 0 | | pf.pfetch | lq_pfetch | 3595 | 3595 | 0 | 0 | 2038 | 0 | 4 | 0 | | (pf.pfetch) | lq_pfetch | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | | byp1_rpt_ary_latch | tri_rlmreg_p__parameterized2_5194 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | byp_rpt_ary_latch | tri_rlmreg_p__parameterized2_5195 | 66 | 66 | 0 | 0 | 2 | 0 | 0 | 0 | | cp_flush2_latch | tri_rlmreg_p__parameterized37_5196 | 48 | 48 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush3_latch | tri_rlmreg_p__parameterized37_5197 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush4_latch | tri_rlmreg_p__parameterized37_5198 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eff_addr_latch | tri_rlmreg_p__parameterized258 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | ex6_iar_latch | tri_rlmreg_p__parameterized227_5199 | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | | ex6_req_val_4pf_latch | tri_rlmreg_p__parameterized37_5200 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_thrd_latch | tri_rlmreg_p__parameterized37_5201 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_eff_addr_latch | tri_rlmreg_p__parameterized258_5202 | 61 | 61 | 0 | 0 | 60 | 0 | 0 | 0 | | ex7_iar_latch | tri_rlmreg_p__parameterized227_5203 | 17 | 17 | 0 | 0 | 12 | 0 | 0 | 0 | | ex7_req_val_4pf_latch | tri_rlmreg_p__parameterized37_5204 | 86 | 86 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_thrd_latch | tri_rlmreg_p__parameterized37_5205 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_burst_cnt_latch | tri_rlmreg_p__parameterized2_5206 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_dup_flag_latch | tri_rlmreg_p__parameterized37_5207 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_eff_addr_latch | tri_rlmreg_p__parameterized258_5208 | 116 | 116 | 0 | 0 | 60 | 0 | 0 | 0 | | ex8_iar_latch | tri_rlmreg_p__parameterized227_5209 | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | | ex8_last_dat_addr_latch | tri_rlmreg_p__parameterized257_5210 | 8 | 8 | 0 | 0 | 22 | 0 | 0 | 0 | | ex8_pf_hits_latch | tri_rlmreg_p__parameterized5_5211 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_pf_state_latch | tri_rlmreg_p__parameterized2_5212 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_pfetch_pe_latch | tri_rlmreg_p__parameterized37_5213 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex8_req_val_4pf_latch | tri_rlmreg_p__parameterized37_5214 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex8_rpt_pe_latch | tri_rlmreg_p__parameterized2_5215 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex8_stride_latch | tri_rlmreg_p__parameterized257_5216 | 22 | 22 | 0 | 0 | 22 | 0 | 0 | 0 | | ex8_thrd_latch | tri_rlmreg_p__parameterized37_5217 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_pfetch_parity_latch | tri_rlmreg_p__parameterized37_5218 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf1_burst_cnt | tri_rlmreg_p__parameterized2_5219 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf1_data_ea | tri_rlmreg_p__parameterized258_5220 | 80 | 80 | 0 | 0 | 60 | 0 | 0 | 0 | | latch_pf1_dup_flag | tri_rlmreg_p__parameterized37_5221 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf1_hits | tri_rlmreg_p__parameterized5_5222 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf1_iar | tri_rlmreg_p__parameterized227_5223 | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | | latch_pf1_new_stride | tri_rlmreg_p__parameterized257_5224 | 7 | 7 | 0 | 0 | 22 | 0 | 0 | 0 | | latch_pf1_pf_state | tri_rlmreg_p__parameterized2_5225 | 46 | 46 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf1_rpt_stride | tri_rlmreg_p__parameterized257_5226 | 3 | 3 | 0 | 0 | 22 | 0 | 0 | 0 | | latch_pf1_same_cline | tri_rlmreg_p__parameterized37_5227 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf1_stride_too_small | tri_rlmreg_p__parameterized37_5228 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf1_thrd | tri_rlmreg_p__parameterized37_5229 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf2_burst_cnt | tri_rlmreg_p__parameterized2_5230 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf2_data_ea | tri_rlmreg_p__parameterized258_5231 | 27 | 27 | 0 | 0 | 22 | 0 | 0 | 0 | | latch_pf2_gen_pfetch | tri_rlmreg_p__parameterized37_5232 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf2_hits | tri_rlmreg_p__parameterized5_5233 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf2_iar | tri_rlmreg_p__parameterized227_5234 | 98 | 98 | 0 | 0 | 12 | 0 | 0 | 0 | | latch_pf2_pf_state | tri_rlmreg_p__parameterized2_5235 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | latch_pf2_rpt_stride | tri_rlmreg_p__parameterized257_5236 | 25 | 25 | 0 | 0 | 22 | 0 | 0 | 0 | | latch_pf2_thrd | tri_rlmreg_p__parameterized37_5237 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf3_req_addr | tri_rlmreg_p__parameterized258_5238 | 64 | 64 | 0 | 0 | 60 | 0 | 0 | 0 | | latch_pf3_req_val | tri_rlmreg_p__parameterized37_5239 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf3_thrd | tri_rlmreg_p__parameterized37_5240 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | latch_pf_count | tri_rlmreg_p__parameterized5_5241 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | latch_pf_iar_tbl_val | tri_rlmreg_p__parameterized3_5242 | 691 | 691 | 0 | 0 | 16 | 0 | 0 | 0 | | latch_pf_state | tri_rlmreg_p__parameterized164_5243 | 13 | 13 | 0 | 0 | 5 | 0 | 0 | 0 | | latch_pfq_dup_flag | tri_rlmreg_p__parameterized259 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | latch_rpt_lru | tri_rlmreg_p__parameterized17_5244 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | odq_report_itag_latch | tri_rlmreg_p__parameterized13_5245 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | odq_report_tid_latch | tri_rlmreg_p__parameterized37_5246 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | odq_resolved_latch | tri_rlmreg_p__parameterized37_5247 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | pf1_req_val_4pf_latch | tri_rlmreg_p__parameterized37_5248 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | pf1_rpt_pe_latch | tri_rlmreg_p__parameterized2_5249 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | pf2_req_val_4pf_latch | tri_rlmreg_p__parameterized37_5250 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pf2_rpt_pe_latch | tri_rlmreg_p__parameterized2_5251 | 73 | 73 | 0 | 0 | 2 | 0 | 0 | 0 | | pf3_stride_latch | tri_rlmreg_p__parameterized257_5252 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | pfq_full_latch | tri_rlmlatch_p_5253 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pfq_rd_ptr_latch | tri_rlmreg_p__parameterized5_5254 | 508 | 508 | 0 | 0 | 11 | 0 | 0 | 0 | | pfq_wrt_ptr_latch | tri_rlmreg_p__parameterized5_5255 | 716 | 716 | 0 | 0 | 3 | 0 | 0 | 0 | | rpt | tri_32x70_2w_1r1w | 234 | 234 | 0 | 0 | 200 | 0 | 4 | 0 | | (rpt) | tri_32x70_2w_1r1w | 0 | 0 | 0 | 0 | 0 | 0 | 4 | 0 | | arrA_bit0_latch | tri_regk__parameterized8 | 14 | 14 | 0 | 0 | 32 | 0 | 0 | 0 | | arrA_bit0_out_latch | tri_regk__parameterized2_5347 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | arrC_bit0_latch | tri_regk__parameterized8_5348 | 14 | 14 | 0 | 0 | 32 | 0 | 0 | 0 | | arrC_bit0_out_latch | tri_regk__parameterized2_5349 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | data_out0_reg | tri_rlmreg_p__parameterized65_5350 | 101 | 101 | 0 | 0 | 66 | 0 | 0 | 0 | | data_out1_reg | tri_rlmreg_p__parameterized65_5351 | 103 | 103 | 0 | 0 | 66 | 0 | 0 | 0 | | rd_act_reg | tri_rlmreg_p__parameterized2_5352 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | rpt_byp_dat1_latch | tri_rlmreg_p__parameterized65 | 156 | 156 | 0 | 0 | 66 | 0 | 0 | 0 | | rpt_byp_dat_latch | tri_rlmreg_p__parameterized65_5256 | 0 | 0 | 0 | 0 | 66 | 0 | 0 | 0 | | rv_i0_ifar_latch | tri_rlmreg_p__parameterized227_5257 | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | | rv_i0_isLoad_latch | tri_rlmreg_p__parameterized37_5258 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_i0_itag_latch | tri_rlmreg_p__parameterized13_5259 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | rv_i0_rte_lq_latch | tri_rlmreg_p__parameterized37_5260 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_i0_vld_latch | tri_rlmreg_p__parameterized37_5261 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_i1_ifar_latch | tri_rlmreg_p__parameterized227_5262 | 12 | 12 | 0 | 0 | 12 | 0 | 0 | 0 | | rv_i1_isLoad_latch | tri_rlmreg_p__parameterized37_5263 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_i1_itag_latch | tri_rlmreg_p__parameterized13_5264 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | rv_i1_rte_lq_latch | tri_rlmreg_p__parameterized37_5265 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_i1_vld_latch | tri_rlmreg_p__parameterized37_5266 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[0].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5267 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[0].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5268 | 18 | 18 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[0].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5269 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[10].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5270 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[10].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5271 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[10].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5272 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[11].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5273 | 4 | 4 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[11].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5274 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[11].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5275 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[12].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5276 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[12].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5277 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[12].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5278 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[13].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5279 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[13].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5280 | 30 | 30 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[13].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5281 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[14].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5282 | 2 | 2 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[14].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5283 | 12 | 12 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[14].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5284 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[15].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5285 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[15].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5286 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[15].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5287 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[1].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5288 | 4 | 4 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[1].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5289 | 4 | 4 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[1].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5290 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[2].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5291 | 3 | 3 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[2].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5292 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[2].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[3].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5294 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[3].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5295 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[3].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5296 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[4].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5297 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[4].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5298 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[4].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5299 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[5].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5300 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[5].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5301 | 12 | 12 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[5].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5302 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[6].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5303 | 3 | 3 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[6].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5304 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[6].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5305 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[7].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5306 | 1 | 1 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[7].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5307 | 10 | 10 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[7].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5308 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[8].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5309 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[8].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5310 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[8].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5311 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl4.pf_iar_table[9].pf_iar_tbl_latch | tri_rlmreg_p__parameterized227_5312 | 2 | 2 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl4.pf_iar_table[9].pf_itag_tbl_latch | tri_rlmreg_p__parameterized13_5313 | 17 | 17 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl4.pf_iar_table[9].pf_tid_tbl_latch | tri_rlmreg_p__parameterized37_5314 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[0].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5315 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[0].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5316 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[0].pfq_stride_latch | tri_rlmreg_p__parameterized257_5317 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[0].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5318 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[1].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5319 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[1].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5320 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[1].pfq_stride_latch | tri_rlmreg_p__parameterized257_5321 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[1].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5322 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[2].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5323 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[2].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5324 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[2].pfq_stride_latch | tri_rlmreg_p__parameterized257_5325 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[2].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5326 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[3].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5327 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[3].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5328 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[3].pfq_stride_latch | tri_rlmreg_p__parameterized257_5329 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[3].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5330 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[4].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5331 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[4].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5332 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[4].pfq_stride_latch | tri_rlmreg_p__parameterized257_5333 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[4].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5334 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[5].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5335 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[5].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5336 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[5].pfq_stride_latch | tri_rlmreg_p__parameterized257_5337 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[5].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5338 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[6].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5339 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[6].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5340 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[6].pfq_stride_latch | tri_rlmreg_p__parameterized257_5341 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[6].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5342 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl7.pfq_gen[7].pfq_data_ea_latch | tri_rlmreg_p__parameterized258_5343 | 0 | 0 | 0 | 0 | 60 | 0 | 0 | 0 | | xhdl7.pfq_gen[7].pfq_dscr_latch | tri_rlmreg_p__parameterized5_5344 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl7.pfq_gen[7].pfq_stride_latch | tri_rlmreg_p__parameterized257_5345 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | xhdl7.pfq_gen[7].pfq_thrd_latch | tri_rlmreg_p__parameterized37_5346 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr | lq_spr | 1554 | 1554 | 0 | 0 | 878 | 0 | 0 | 0 | | flush_latch | tri_rlmreg_p__parameterized37_5133 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_spr_cspr | lq_spr_cspr | 277 | 277 | 0 | 0 | 559 | 0 | 0 | 0 | | dac1_latch_gen.dac1_latch | tri_ser_rlmreg_p__parameterized12_5155 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5193 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | dac2_latch_gen.dac2_latch | tri_ser_rlmreg_p__parameterized12_5156 | 75 | 75 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5192 | 75 | 75 | 0 | 0 | 64 | 0 | 0 | 0 | | dac3_latch | tri_ser_rlmreg_p__parameterized12_5157 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5191 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | dac4_latch | tri_ser_rlmreg_p__parameterized12_5158 | 82 | 82 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5190 | 82 | 82 | 0 | 0 | 64 | 0 | 0 | 0 | | dbcr0_dac1.dbcr0_dac1[0].dbcr0_dac1_latch | tri_rlmreg_p__parameterized2_5159 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | dbcr0_dac2.dbcr0_dac2[0].dbcr0_dac2_latch | tri_rlmreg_p__parameterized2_5160 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | dbcr0_dac3.dbcr0_dac3[0].dbcr0_dac3_latch | tri_rlmreg_p__parameterized2_5161 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | dbcr0_dac4.dbcr0_dac4[0].dbcr0_dac4_latch | tri_rlmreg_p__parameterized2_5162 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | dbcr2_dvc1m_on_latch | tri_rlmreg_p__parameterized37_5163 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbcr2_dvc2m_on_latch | tri_rlmreg_p__parameterized37_5164 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dvc1_latch_gen.dvc1_latch | tri_ser_rlmreg_p__parameterized12_5165 | 18 | 18 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5189 | 18 | 18 | 0 | 0 | 64 | 0 | 0 | 0 | | dvc2_latch_gen.dvc2_latch | tri_ser_rlmreg_p__parameterized12_5166 | 17 | 17 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_5188 | 17 | 17 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_val_latch | tri_rlmreg_p__parameterized37_5167 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dac12m_latch | tri_regk__parameterized14_5168 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_dac34m_latch | tri_regk__parameterized14_5169 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_is_any_load_dac_latch | tri_regk__parameterized2_5170 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_any_store_dac_latch | tri_regk__parameterized2_5171 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_val_latch | tri_rlmreg_p__parameterized37_5172 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_dacrw_cmpr_latch | tri_rlmreg_p__parameterized9_5173 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_data_val_reg | tri_rlmlatch_p_5174 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_val_latch | tri_rlmreg_p__parameterized37_5175 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized2_5176 | 13 | 13 | 0 | 0 | 2 | 0 | 0 | 0 | | lesr1_latch | tri_ser_rlmreg_p__parameterized7 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized7_5187 | 0 | 0 | 0 | 0 | 24 | 0 | 0 | 0 | | lesr2_latch | tri_ser_rlmreg_p__parameterized7_5177 | 32 | 32 | 0 | 0 | 24 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized7 | 32 | 32 | 0 | 0 | 24 | 0 | 0 | 0 | | lsucr0_latch | tri_ser_rlmreg_p__parameterized29 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized29 | 0 | 0 | 0 | 0 | 11 | 0 | 0 | 0 | | msr_ds_latch | tri_rlmreg_p__parameterized37_5178 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_gs_latch | tri_rlmreg_p__parameterized37_5179 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_pr_latch | tri_rlmreg_p__parameterized37_5180 | 19 | 19 | 0 | 0 | 1 | 0 | 0 | 0 | | pesr_latch | tri_ser_rlmreg_p__parameterized6_5181 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_5186 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xucr2_latch | tri_ser_rlmreg_p__parameterized6_5182 | 3 | 3 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_5185 | 3 | 3 | 0 | 0 | 32 | 0 | 0 | 0 | | xudbg0_done_reg | tri_rlmlatch_p_5183 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xudbg0_inprog_reg | tri_rlmlatch_p_5184 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xudbg0_latch | tri_ser_rlmreg_p__parameterized0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized0 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | slowspr_addr_in_latch | tri_rlmreg_p__parameterized6_5134 | 386 | 386 | 0 | 0 | 10 | 0 | 0 | 0 | | slowspr_addr_out_latch | tri_rlmreg_p__parameterized6_5135 | 20 | 20 | 0 | 0 | 10 | 0 | 0 | 0 | | slowspr_data_in_latch | tri_rlmreg_p__parameterized33_5136 | 691 | 691 | 0 | 0 | 64 | 0 | 0 | 0 | | slowspr_data_out_latch | tri_rlmreg_p__parameterized33_5137 | 32 | 32 | 0 | 0 | 64 | 0 | 0 | 0 | | slowspr_done_out_latch | tri_rlmlatch_p_5138 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_etid_in_latch | tri_rlmreg_p__parameterized2_5139 | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | | slowspr_etid_out_latch | tri_rlmreg_p__parameterized2_5140 | 69 | 69 | 0 | 0 | 2 | 0 | 0 | 0 | | slowspr_rw_in_latch | tri_rlmlatch_p_5141 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_rw_out_latch | tri_rlmlatch_p_5142 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_val_in_latch | tri_rlmlatch_p_5143 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | slowspr_val_out_latch | tri_rlmlatch_p_5144 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | thread.thread[0].lq_spr_tspr | lq_spr_tspr | 63 | 63 | 0 | 0 | 161 | 0 | 0 | 0 | | acop_latch_gen.acop_latch | tri_ser_rlmreg_p__parameterized6_5145 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_5154 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | dbcr2_latch_gen.dbcr2_latch | tri_ser_rlmreg_p__parameterized2 | 44 | 44 | 0 | 0 | 29 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized2 | 44 | 44 | 0 | 0 | 29 | 0 | 0 | 0 | | dbcr3_latch | tri_ser_rlmreg_p__parameterized11_5146 | 4 | 4 | 0 | 0 | 10 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized11_5153 | 4 | 4 | 0 | 0 | 10 | 0 | 0 | 0 | | dscr_latch | tri_ser_rlmreg_p__parameterized28 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized28 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | eplc_latch_gen.eplc_latch | tri_ser_rlmreg_p__parameterized27 | 8 | 8 | 0 | 0 | 25 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized27_5152 | 8 | 8 | 0 | 0 | 25 | 0 | 0 | 0 | | eplc_we_reg | tri_rlmlatch_p_5147 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | epsc_latch_gen.epsc_latch | tri_ser_rlmreg_p__parameterized27_5148 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized27 | 0 | 0 | 0 | 0 | 25 | 0 | 0 | 0 | | epsc_we_reg | tri_rlmlatch_p_5149 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hacop_latch_gen.hacop_latch | tri_ser_rlmreg_p__parameterized6_5150 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_5151 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | dat | lq_data | 10279 | 10279 | 0 | 0 | 3311 | 32 | 0 | 0 | | dc32K.tridcarr | tri_256x144_8w_1r1w | 1441 | 1441 | 0 | 0 | 1160 | 32 | 0 | 0 | | (dc32K.tridcarr) | tri_256x144_8w_1r1w | 0 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | | rd_act_reg | tri_rlmreg_p__parameterized12_5124 | 1152 | 1152 | 0 | 0 | 8 | 0 | 0 | 0 | | wayReg[0].data_out_reg | tri_inv_nlats__parameterized8 | 37 | 37 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[1].data_out_reg | tri_inv_nlats__parameterized8_5125 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[2].data_out_reg | tri_inv_nlats__parameterized8_5126 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[3].data_out_reg | tri_inv_nlats__parameterized8_5127 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[4].data_out_reg | tri_inv_nlats__parameterized8_5128 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[5].data_out_reg | tri_inv_nlats__parameterized8_5129 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[6].data_out_reg | tri_inv_nlats__parameterized8_5130 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | wayReg[7].data_out_reg | tri_inv_nlats__parameterized8_5131 | 36 | 36 | 0 | 0 | 144 | 0 | 0 | 0 | | ex2_stg_act_reg | tri_rlmlatch_p_4894 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_stg_act_reg | tri_rlmlatch_p_4895 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_stg_act_reg | tri_rlmlatch_p_4896 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_dcache_parity_reg | tri_rlmlatch_p_4897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | l1dcld | lq_data_ld | 3507 | 3507 | 0 | 0 | 388 | 0 | 0 | 0 | | ex5_ld_hit_data_reg | tri_regk__parameterized1_4954 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[0].sgrp.bits | tri_rot16s_ru | 6 | 6 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5119 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5120 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5121 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5122 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5123 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[1].grp.bits | tri_rot16_ru | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5118 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[2].grp.bits | tri_rot16_ru_4955 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5117 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[3].grp.bits | tri_rot16_ru_4956 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5116 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[4].grp.bits | tri_rot16_ru_4957 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5115 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[5].grp.bits | tri_rot16_ru_4958 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5114 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[6].grp.bits | tri_rot16_ru_4959 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5113 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWA.l1dcrotrWA[7].grp.bits | tri_rot16_ru_4960 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5112 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[0].sgrp.bits | tri_rot16s_ru_4961 | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5107 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5108 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5109 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5110 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5111 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[1].grp.bits | tri_rot16_ru_4962 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5106 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[2].grp.bits | tri_rot16_ru_4963 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5105 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[3].grp.bits | tri_rot16_ru_4964 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5104 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[4].grp.bits | tri_rot16_ru_4965 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5103 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[5].grp.bits | tri_rot16_ru_4966 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5102 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[6].grp.bits | tri_rot16_ru_4967 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5101 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWB.l1dcrotrWB[7].grp.bits | tri_rot16_ru_4968 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5100 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[0].sgrp.bits | tri_rot16s_ru_4969 | 7 | 7 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5095 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5096 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5097 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5098 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5099 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[1].grp.bits | tri_rot16_ru_4970 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5094 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[2].grp.bits | tri_rot16_ru_4971 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5093 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[3].grp.bits | tri_rot16_ru_4972 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5092 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[4].grp.bits | tri_rot16_ru_4973 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5091 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[5].grp.bits | tri_rot16_ru_4974 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5090 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[6].grp.bits | tri_rot16_ru_4975 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5089 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWC.l1dcrotrWC[7].grp.bits | tri_rot16_ru_4976 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5088 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[0].sgrp.bits | tri_rot16s_ru_4977 | 14 | 14 | 0 | 0 | 20 | 0 | 0 | 0 | | be_shx01_gp0_lat | tri_inv_nlats__parameterized11_5082 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5083 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5084 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5085 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5086 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5087 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[1].grp.bits | tri_rot16_ru_4978 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5081 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[2].grp.bits | tri_rot16_ru_4979 | 1895 | 1895 | 0 | 0 | 37 | 0 | 0 | 0 | | be_shx01_gp0_lat | tri_inv_nlats__parameterized11_5076 | 80 | 80 | 0 | 0 | 2 | 0 | 0 | 0 | | be_shx04_gp0_lat | tri_inv_nlats__parameterized10_5077 | 613 | 613 | 0 | 0 | 5 | 0 | 0 | 0 | | bele_gp0_lat | tri_inv_nlats__parameterized9 | 246 | 246 | 0 | 0 | 22 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5078 | 159 | 159 | 0 | 0 | 2 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5079 | 792 | 792 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5080 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[3].grp.bits | tri_rot16_ru_4980 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5075 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[4].grp.bits | tri_rot16_ru_4981 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5074 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[5].grp.bits | tri_rot16_ru_4982 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5073 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[6].grp.bits | tri_rot16_ru_4983 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5072 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWD.l1dcrotrWD[7].grp.bits | tri_rot16_ru_4984 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5071 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[0].sgrp.bits | tri_rot16s_ru_4985 | 221 | 221 | 0 | 0 | 27 | 0 | 0 | 0 | | be_shx01_gp0_lat | tri_inv_nlats__parameterized11_5063 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5064 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5065 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5066 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5067 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5068 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5069 | 209 | 209 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5070 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[1].grp.bits | tri_rot16_ru_4986 | 25 | 25 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx01_gp0_lat | tri_inv_nlats__parameterized11_5060 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5061 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5062 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[2].grp.bits | tri_rot16_ru_4987 | 1314 | 1314 | 0 | 0 | 22 | 0 | 0 | 0 | | be_shx01_gp0_lat | tri_inv_nlats__parameterized11_5055 | 37 | 37 | 0 | 0 | 1 | 0 | 0 | 0 | | be_shx04_gp0_lat | tri_inv_nlats__parameterized10_5056 | 475 | 475 | 0 | 0 | 9 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5057 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5058 | 795 | 795 | 0 | 0 | 8 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5059 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[3].grp.bits | tri_rot16_ru_4988 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5054 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[4].grp.bits | tri_rot16_ru_4989 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5053 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[5].grp.bits | tri_rot16_ru_4990 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5052 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[6].grp.bits | tri_rot16_ru_4991 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5051 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWE.l1dcrotrWE[7].grp.bits | tri_rot16_ru_4992 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5050 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[0].sgrp.bits | tri_rot16s_ru_4993 | 6 | 6 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5045 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5046 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5047 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5048 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5049 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[1].grp.bits | tri_rot16_ru_4994 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5044 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[2].grp.bits | tri_rot16_ru_4995 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5043 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[3].grp.bits | tri_rot16_ru_4996 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5042 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[4].grp.bits | tri_rot16_ru_4997 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5041 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[5].grp.bits | tri_rot16_ru_4998 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5040 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[6].grp.bits | tri_rot16_ru_4999 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5039 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWF.l1dcrotrWF[7].grp.bits | tri_rot16_ru_5000 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5038 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[0].sgrp.bits | tri_rot16s_ru_5001 | 6 | 6 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11_5033 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10_5034 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5035 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5036 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5037 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[1].grp.bits | tri_rot16_ru_5002 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5032 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[2].grp.bits | tri_rot16_ru_5003 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5031 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[3].grp.bits | tri_rot16_ru_5004 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5030 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[4].grp.bits | tri_rot16_ru_5005 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5029 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[5].grp.bits | tri_rot16_ru_5006 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5028 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[6].grp.bits | tri_rot16_ru_5007 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5027 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWG.l1dcrotrWG[7].grp.bits | tri_rot16_ru_5008 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5026 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[0].sgrp.bits | tri_rot16s_ru_5009 | 6 | 6 | 0 | 0 | 18 | 0 | 0 | 0 | | be_shx01_sgn0_lat | tri_inv_nlats__parameterized11 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | be_shx04_sgn0_lat | tri_inv_nlats__parameterized10 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx01_gp0_lat | tri_inv_nlats__parameterized11_5023 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | le_shx04_gp0_lat | tri_inv_nlats__parameterized10_5024 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5025 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[1].grp.bits | tri_rot16_ru_5010 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5022 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[2].grp.bits | tri_rot16_ru_5011 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5021 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[3].grp.bits | tri_rot16_ru_5012 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5020 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[4].grp.bits | tri_rot16_ru_5013 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5019 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[5].grp.bits | tri_rot16_ru_5014 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5018 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[6].grp.bits | tri_rot16_ru_5015 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12_5017 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcrotrWH.l1dcrotrWH[7].grp.bits | tri_rot16_ru_5016 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mask_lat | tri_inv_nlats__parameterized12 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | l1dcst | lq_data_st | 5074 | 5074 | 0 | 0 | 1584 | 0 | 0 | 0 | | (l1dcst) | lq_data_st | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | | rel2_data_val_reg | tri_rlmlatch_p_4906 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rmw | tri_lq_rmw | 3315 | 3315 | 0 | 0 | 928 | 0 | 0 | 0 | | ex3_stq5_rd_addr_reg | tri_rlmreg_p__parameterized12_4933 | 23 | 23 | 0 | 0 | 8 | 0 | 0 | 0 | | stq6_addr_reg | tri_rlmreg_p__parameterized12_4934 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | stq6_arr_wren_reg | tri_rlmlatch_p_4935 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_byp_wr_data_wabcd_reg | tri_rlmreg_p__parameterized251_4936 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | | stq6_byp_wr_data_wefgh_reg | tri_rlmreg_p__parameterized251_4937 | 1 | 1 | 0 | 0 | 144 | 0 | 0 | 0 | | stq6_byte_en_wabcd_reg | tri_rlmreg_p__parameterized3_4938 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | stq6_byte_en_wefgh_reg | tri_rlmreg_p__parameterized3_4939 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | stq6_stg_act_latch | tri_rlmlatch_p_4940 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | stq6_way_en_reg | tri_rlmreg_p__parameterized12_4941 | 1471 | 1471 | 0 | 0 | 8 | 0 | 0 | 0 | | stq7_addr_reg | tri_rlmreg_p__parameterized12_4942 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | stq7_arr_wren_reg | tri_rlmlatch_p_4943 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_byp_val_wabcd_reg | tri_rlmreg_p__parameterized9_4944 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | stq7_byp_val_wefgh_reg | tri_rlmreg_p__parameterized9_4945 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | stq7_stg_act_latch | tri_rlmlatch_p_4946 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | stq7_way_en_reg | tri_rlmreg_p__parameterized12_4947 | 37 | 37 | 0 | 0 | 8 | 0 | 0 | 0 | | stq7_wr_data_wabcd_reg | tri_rlmreg_p__parameterized251_4948 | 871 | 871 | 0 | 0 | 144 | 0 | 0 | 0 | | stq7_wr_data_wefgh_reg | tri_rlmreg_p__parameterized251_4949 | 890 | 890 | 0 | 0 | 144 | 0 | 0 | 0 | | stq8_wr_data_wabcd_reg | tri_rlmreg_p__parameterized251_4950 | 0 | 0 | 0 | 0 | 128 | 0 | 0 | 0 | | stq8_wr_data_wefgh_reg | tri_rlmreg_p__parameterized251_4951 | 0 | 0 | 0 | 0 | 128 | 0 | 0 | 0 | | stq_byp_val_wabcd_reg | tri_rlmreg_p__parameterized9_4952 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | stq_byp_val_wefgh_reg | tri_rlmreg_p__parameterized9_4953 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | stq2_addr_reg | tri_rlmreg_p__parameterized12_4907 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq2_byte_en_reg | tri_rlmreg_p__parameterized3_4908 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | stq2_le_mode_reg | tri_rlmlatch_p_4909 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_mftgpr_val_reg | tri_rlmlatch_p_4910 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_opsize_reg | tri_rlmreg_p__parameterized4_4911 | 12 | 12 | 0 | 0 | 5 | 0 | 0 | 0 | | stq2_rot_addr_reg | tri_rlmreg_p__parameterized4_4912 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | stq2_stg_act_latch | tri_rlmlatch_p_4913 | 134 | 134 | 0 | 0 | 3 | 0 | 0 | 0 | | stq2_upd_val_reg | tri_rlmlatch_p_4914 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_addr_reg | tri_regk__parameterized14 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_blk_req_reg | tri_rlmlatch_p_4915 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_byte_en_reg | tri_regk__parameterized19 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | stq3_opsize_reg | tri_rlmreg_p__parameterized4_4916 | 67 | 67 | 0 | 0 | 5 | 0 | 0 | 0 | | stq3_rot_sel1_reg | tri_regk__parameterized15 | 642 | 642 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_rot_sel2_reg | tri_regk__parameterized16 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_rot_sel3_reg | tri_regk__parameterized16_4917 | 64 | 64 | 0 | 0 | 8 | 0 | 0 | 0 | | stq3_stg_act_latch | tri_rlmlatch_p_4918 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | stq3_store_rel_data_reg | tri_regk__parameterized18 | 432 | 432 | 0 | 0 | 128 | 0 | 0 | 0 | | stq3_store_rel_par_reg | tri_regk__parameterized19_4919 | 44 | 44 | 0 | 0 | 16 | 0 | 0 | 0 | | stq3_upd_val_reg | tri_rlmlatch_p_4920 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_addr_reg | tri_rlmreg_p__parameterized12_4921 | 25 | 25 | 0 | 0 | 8 | 0 | 0 | 0 | | stq4_byte_en_reg | tri_rlmreg_p__parameterized3_4922 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | stq4_dcarr_data_reg | tri_rlmreg_p__parameterized1_4923 | 133 | 133 | 0 | 0 | 128 | 0 | 0 | 0 | | stq4_dcarr_par_reg | tri_rlmreg_p__parameterized3_4924 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | stq4_rot_data_reg | tri_rlmreg_p__parameterized33_4925 | 63 | 63 | 0 | 0 | 64 | 0 | 0 | 0 | | stq4_stg_act_latch | tri_rlmlatch_p_4926 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_upd_val_reg | tri_rlmlatch_p_4927 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_addr_reg | tri_regk__parameterized14_4928 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | stq5_arr_way_en_reg | tri_regk__parameterized15_4929 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | stq5_arr_wren_reg | tri_rlmlatch_p_4930 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_byte_en_reg | tri_regk__parameterized19_4931 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | stq5_dcarr_wrt_data_reg | tri_regk__parameterized17 | 0 | 0 | 0 | 0 | 144 | 0 | 0 | 0 | | stq5_stg_act_latch | tri_rlmlatch_p_4932 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | perv_1to0_reg | tri_plat__parameterized6 | 236 | 236 | 0 | 0 | 26 | 0 | 0 | 0 | | perv_2to1_reg | tri_plat__parameterized6_4898 | 14 | 14 | 0 | 0 | 15 | 0 | 0 | 0 | | spr_xucr0_dcdis_reg | tri_rlmlatch_p_4899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_stg_act_reg | tri_rlmlatch_p_4900 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_stg_act_reg | tri_rlmlatch_p_4901 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_stg_act_reg | tri_rlmlatch_p_4902 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_rot_data_reg | tri_regk__parameterized1_4903 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | stq5_stg_act_reg | tri_rlmlatch_p_4904 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_rot_data_reg | tri_rlmreg_p__parameterized33_4905 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | lq_perv | lq_perv | 1 | 0 | 0 | 1 | 2 | 0 | 0 | 0 | | perv_3to2_reg | tri_plat__parameterized8 | 1 | 0 | 0 | 1 | 2 | 0 | 0 | 0 | | lsq | lq_lsq | 21668 | 21668 | 0 | 0 | 8200 | 8 | 0 | 0 | | an_ac_reld_core_tag_reg | tri_rlmreg_p__parameterized4_3361 | 71 | 71 | 0 | 0 | 5 | 0 | 0 | 0 | | an_ac_reld_crit_qw_reg | tri_rlmlatch_p_3362 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | an_ac_reld_data_reg | tri_rlmreg_p__parameterized1_3363 | 10 | 10 | 0 | 0 | 128 | 0 | 0 | 0 | | an_ac_reld_data_vld_reg | tri_rlmlatch_p_3364 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | an_ac_reld_data_vld_stg1_reg | tri_rlmlatch_p_3365 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | an_ac_reld_qw_reg | tri_rlmreg_p__parameterized2_3366 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | an_ac_req_ld_pop_reg | tri_rlmlatch_p_3367 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | an_ac_req_st_pop_reg | tri_rlmlatch_p_3368 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | arb | lq_arb | 191 | 191 | 0 | 0 | 240 | 0 | 0 | 0 | | ld_cred_blk_cnt_reg | tri_rlmreg_p__parameterized9_4871 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | ld_cred_err_reg | tri_rlmlatch_p_4872 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ld_noCred_hold_reg | tri_rlmlatch_p_4873 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ld_pop_rcvd_reg | tri_rlmlatch_p_4874 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ld_st_noCred_flp_reg | tri_rlmlatch_p_4875 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | load_cred_cnt_reg | tri_rlmreg_p__parameterized164 | 12 | 12 | 0 | 0 | 5 | 0 | 0 | 0 | | mmq2_req_val_reg | tri_rlmlatch_p_4876 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | mmq3_req_val_reg | tri_rlmlatch_p_4877 | 65 | 65 | 0 | 0 | 1 | 0 | 0 | 0 | | req_l2_ld_sent_reg | tri_rlmlatch_p_4878 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | req_l2_val_reg | tri_rlmlatch_p_4879 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | req_sel_byteEn_reg | tri_rlmreg_p__parameterized3_4880 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | req_sel_cTag_reg | tri_rlmreg_p__parameterized4_4881 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | req_sel_p_addr_reg | tri_rlmreg_p__parameterized219_4882 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | req_sel_ttype_reg | tri_rlmreg_p__parameterized0_4883 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | req_sel_wimge_reg | tri_rlmreg_p__parameterized4_4884 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_lsucr0_b2b_reg | tri_rlmlatch_p_4885 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_cls_reg | tri_rlmlatch_p_4886 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_cred_reg | tri_rlmlatch_p_4887 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | st_cred_err_reg | tri_rlmlatch_p_4888 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | st_rej_hold_cred_reg | tri_rlmlatch_p_4889 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | store_cred_cnt_reg | tri_rlmreg_p__parameterized66 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | stq2_req_val_reg | tri_rlmlatch_p_4890 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_store_data_reg | tri_rlmreg_p__parameterized1_4891 | 32 | 32 | 0 | 0 | 128 | 0 | 0 | 0 | | stq4_data_override_reg | tri_rlmlatch_p_4892 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_req_st_data_reg | tri_rlmreg_p__parameterized268 | 47 | 47 | 0 | 0 | 25 | 0 | 0 | 0 | | unit_last_sel_reg | tri_rlmreg_p__parameterized193_4893 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | dc32Kdir64B.arr | tri_64x34_8w_1r1w | 410 | 410 | 0 | 0 | 275 | 8 | 0 | 0 | | (dc32Kdir64B.arr) | tri_64x34_8w_1r1w | 0 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | | data_out_reg | tri_rlmreg_p__parameterized256 | 138 | 138 | 0 | 0 | 272 | 0 | 0 | 0 | | rd_act_reg | tri_rlmlatch_p_4870 | 272 | 272 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_itag_reg | tri_rlmreg_p__parameterized13_3369 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_algebraic_reg | tri_rlmlatch_p_3370 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_byte_en_reg | tri_rlmreg_p__parameterized3_3371 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | ex4_itag_reg | tri_rlmreg_p__parameterized13_3372 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_opsize_reg | tri_rlmreg_p__parameterized5_3373 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_p_addr_reg | tri_rlmreg_p__parameterized0_3374 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_thrd_id_reg | tri_rlmreg_p__parameterized37_3375 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_algebraic_reg | tri_rlmlatch_p_3376 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_byte_en_reg | tri_rlmreg_p__parameterized3_3377 | 121 | 121 | 0 | 0 | 16 | 0 | 0 | 0 | | ex5_dreq_val_reg | tri_rlmlatch_p_3378 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_opsize_reg | tri_rlmreg_p__parameterized5_3379 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_thrd_id_reg | tri_rlmreg_p__parameterized37_3380 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | imq | lq_imq | 382 | 382 | 0 | 0 | 304 | 0 | 0 | 0 | | iu_lq_cTag_reg | tri_rlmreg_p__parameterized2_4822 | 8 | 8 | 0 | 0 | 2 | 0 | 0 | 0 | | iu_lq_ra_reg | tri_rlmreg_p__parameterized61_4823 | 104 | 104 | 0 | 0 | 26 | 0 | 0 | 0 | | iu_lq_request_reg | tri_rlmreg_p__parameterized37_4824 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_lq_wimge_reg | tri_rlmreg_p__parameterized4_4825 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_entry_cTag.iuq_entry_cTag[0].iuq_entry_cTag_reg | tri_rlmreg_p__parameterized2_4826 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | iuq_entry_cTag.iuq_entry_cTag[1].iuq_entry_cTag_reg | tri_rlmreg_p__parameterized2_4827 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | iuq_entry_cTag.iuq_entry_cTag[2].iuq_entry_cTag_reg | tri_rlmreg_p__parameterized2_4828 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | iuq_entry_cTag.iuq_entry_cTag[3].iuq_entry_cTag_reg | tri_rlmreg_p__parameterized2_4829 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | iuq_entry_p_addr.iuq_entry_p_addr[0].iuq_entry_p_addr_reg | tri_rlmreg_p__parameterized61_4830 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | iuq_entry_p_addr.iuq_entry_p_addr[1].iuq_entry_p_addr_reg | tri_rlmreg_p__parameterized61_4831 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | iuq_entry_p_addr.iuq_entry_p_addr[2].iuq_entry_p_addr_reg | tri_rlmreg_p__parameterized61_4832 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | iuq_entry_p_addr.iuq_entry_p_addr[3].iuq_entry_p_addr_reg | tri_rlmreg_p__parameterized61_4833 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | iuq_entry_seq.iuq_entry_seq[0].iuq_entry_seq_reg | tri_rlmreg_p__parameterized5_4834 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_entry_seq.iuq_entry_seq[1].iuq_entry_seq_reg | tri_rlmreg_p__parameterized5_4835 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_entry_seq.iuq_entry_seq[2].iuq_entry_seq_reg | tri_rlmreg_p__parameterized5_4836 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_entry_seq.iuq_entry_seq[3].iuq_entry_seq_reg | tri_rlmreg_p__parameterized5_4837 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_entry_val_reg | tri_rlmreg_p__parameterized9_4838 | 14 | 14 | 0 | 0 | 4 | 0 | 0 | 0 | | iuq_entry_wimge.iuq_entry_wimge[0].iuq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4839 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_entry_wimge.iuq_entry_wimge[1].iuq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4840 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_entry_wimge.iuq_entry_wimge[2].iuq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4841 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_entry_wimge.iuq_entry_wimge[3].iuq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4842 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iuq_seq_rd_reg | tri_rlmreg_p__parameterized5_4843 | 67 | 67 | 0 | 0 | 3 | 0 | 0 | 0 | | iuq_seq_reg | tri_rlmreg_p__parameterized5_4844 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | mm_lq_lsu_addr_reg | tri_rlmreg_p__parameterized219_4845 | 52 | 52 | 0 | 0 | 26 | 0 | 0 | 0 | | mm_lq_lsu_gs_reg | tri_rlmlatch_p_4846 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_lq_lsu_ind_reg | tri_rlmlatch_p_4847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_lq_lsu_lbit_reg | tri_rlmlatch_p_4848 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_lq_lsu_lpid_reg | tri_rlmreg_p__parameterized12_4849 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | mm_lq_lsu_req_reg | tri_rlmreg_p__parameterized37_4850 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_lq_lsu_ttype_reg | tri_rlmreg_p__parameterized2_4851 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | mm_lq_lsu_wimge_reg | tri_rlmreg_p__parameterized4_4852 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | mmq_entry_gs_reg | tri_rlmreg_p__parameterized2_4853 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_ind_reg | tri_rlmreg_p__parameterized2_4854 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_lbit_reg | tri_rlmreg_p__parameterized2_4855 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_lpid.mmq_entry_lpid[0].mmq_entry_lpid_reg | tri_rlmreg_p__parameterized12_4856 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | mmq_entry_lpid.mmq_entry_lpid[1].mmq_entry_lpid_reg | tri_rlmreg_p__parameterized12_4857 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | mmq_entry_p_addr.mmq_entry_p_addr[0].mmq_entry_p_addr_reg | tri_rlmreg_p__parameterized219_4858 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | mmq_entry_p_addr.mmq_entry_p_addr[1].mmq_entry_p_addr_reg | tri_rlmreg_p__parameterized219_4859 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | mmq_entry_seq.mmq_entry_seq[0].mmq_entry_seq_reg | tri_rlmreg_p__parameterized5_4860 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | mmq_entry_seq.mmq_entry_seq[1].mmq_entry_seq_reg | tri_rlmreg_p__parameterized5_4861 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | mmq_entry_ttype.mmq_entry_ttype[0].mmq_entry_ttype_reg | tri_rlmreg_p__parameterized2_4862 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_ttype.mmq_entry_ttype[1].mmq_entry_ttype_reg | tri_rlmreg_p__parameterized2_4863 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_val_reg | tri_rlmreg_p__parameterized2_4864 | 11 | 11 | 0 | 0 | 2 | 0 | 0 | 0 | | mmq_entry_wimge.mmq_entry_wimge[0].mmq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4865 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmq_entry_wimge.mmq_entry_wimge[1].mmq_entry_wimge_reg | tri_rlmreg_p__parameterized4_4866 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmq_ret_token_reg | tri_rlmlatch_p_4867 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmq_seq_rd_reg | tri_rlmreg_p__parameterized5_4868 | 76 | 76 | 0 | 0 | 3 | 0 | 0 | 0 | | mmq_seq_reg | tri_rlmreg_p__parameterized5_4869 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | ldq | lq_ldq | 4965 | 4965 | 0 | 0 | 2044 | 0 | 0 | 0 | | cpl_group_last_sel_reg | tri_rlmreg_p__parameterized200_4454 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | | cpl_grpEntry_last_sel.cpl_grpEntry_last_sel[0].cpl_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4455 | 32 | 32 | 0 | 0 | 4 | 0 | 0 | 0 | | cpl_grpEntry_last_sel.cpl_grpEntry_last_sel[1].cpl_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4456 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | cpl_grpEntry_last_sel.cpl_grpEntry_last_sel[2].cpl_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4457 | 33 | 33 | 0 | 0 | 4 | 0 | 0 | 0 | | cpl_grpEntry_last_sel.cpl_grpEntry_last_sel[3].cpl_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4458 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | dbg_int_en_reg | tri_rlmreg_p__parameterized37_4459 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ldreq_reg | tri_rlmlatch_p_4460 | 36 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_pfetch_val_reg | tri_rlmlatch_p_4461 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_stg_act_reg | tri_rlmlatch_p_4462 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ld_gath_reg | tri_rlmlatch_p_4463 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ldm_hit_reg | tri_rlmreg_p__parameterized12_4464 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_ldq_full_restart_reg | tri_rlmlatch_p_4465 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ldq_hit_reg | tri_rlmlatch_p_4466 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ldq_restart_reg | tri_rlmlatch_p_4467 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ldq_set_hold_reg | tri_rlmlatch_p_4468 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ldqe_set_all_reg | tri_rlmreg_p__parameterized12_4469 | 85 | 85 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_ldqe_set_val_reg | tri_rlmreg_p__parameterized12_4470 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_ldreq_val_reg | tri_rlmlatch_p_4471 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_lgqe_set_all_reg | tri_rlmreg_p__parameterized12_4472 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_lgqe_set_val_reg | tri_rlmreg_p__parameterized12_4473 | 17 | 17 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_odq_ldreq_val_reg | tri_rlmlatch_p_4474 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_othreq_val_reg | tri_rlmlatch_p_4475 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_p_addr_reg | tri_rlmreg_p__parameterized219_4476 | 26 | 26 | 0 | 0 | 26 | 0 | 0 | 0 | | ex5_pfetch_val_reg | tri_rlmlatch_p_4477 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_reserved_taken_reg | tri_rlmlatch_p_4478 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_resv_taken_restart_reg | tri_rlmlatch_p_4479 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_stg_act_reg | tri_rlmlatch_p_4480 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_streq_val_reg | tri_rlmlatch_p_4481 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wimge_reg | tri_rlmreg_p__parameterized4_4482 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ldqe_pfetch_val_reg | tri_rlmreg_p__parameterized12_4483 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ex7_ldqe_pfetch_val_reg | tri_rlmreg_p__parameterized12_4484 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[0].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4485 | 188 | 188 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[1].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4486 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[2].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4487 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[3].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4488 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[4].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4489 | 28 | 28 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[5].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4490 | 28 | 28 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[6].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4491 | 28 | 28 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req.fifo_ldq_req[7].fifo_ldq_req_reg | tri_rlmreg_p__parameterized12_4492 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req_nxt_ptr_reg | tri_rlmreg_p__parameterized266 | 33 | 33 | 0 | 0 | 9 | 0 | 0 | 0 | | fifo_ldq_req_pfetch_reg | tri_rlmreg_p__parameterized12_4493 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[0].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4494 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[1].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4495 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[2].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4496 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[3].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4497 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[4].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4498 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[5].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4499 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[6].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4500 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_tid.fifo_ldq_req_tid[7].fifo_ldq_req_tid_reg | tri_rlmreg_p__parameterized37_4501 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fifo_ldq_req_val_reg | tri_rlmreg_p__parameterized12_4502 | 22 | 22 | 0 | 0 | 8 | 0 | 0 | 0 | | iu_lq_cp_flush_reg | tri_rlmreg_p__parameterized37_4503 | 32 | 32 | 0 | 0 | 3 | 0 | 0 | 0 | | l2_rel0_resp_cTag_reg | tri_rlmreg_p__parameterized9_4504 | 373 | 373 | 0 | 0 | 4 | 0 | 0 | 0 | | l2_rel0_resp_crit_qw_reg | tri_rlmlatch_p_4505 | 19 | 19 | 0 | 0 | 1 | 0 | 0 | 0 | | l2_rel0_resp_ldq_val_reg | tri_rlmlatch_p_4506 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | l2_rel0_resp_qw_reg | tri_rlmreg_p__parameterized5_4507 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ldq_err_inval_rel_reg | tri_rlmlatch_p_4508 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_full_qHit_held_reg | tri_rlmlatch_p_4509 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_hold_tid_reg | tri_rlmreg_p__parameterized37_4510 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_l2_rel0_qHitBlk_reg | tri_rlmlatch_p_4511 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_oth_qHit_clr_reg | tri_rlmlatch_p_4512 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel0_l2_val_reg | tri_rlmreg_p__parameterized12_4513 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel0_upd_gpr_reg | tri_rlmreg_p__parameterized12_4514 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_algEn_reg | tri_rlmlatch_p_4515 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_algebraic_sel_reg | tri_rlmreg_p__parameterized9_4516 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_rel1_arb_val_reg | tri_rlmlatch_p_4517 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_axu_reg | tri_rlmlatch_p_4518 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_byte_swap_reg | tri_rlmlatch_p_4519 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_cTag_reg | tri_rlmreg_p__parameterized9_4520 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_rel1_classID_reg | tri_rlmreg_p__parameterized2_4521 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldq_rel1_data_sel_reg | tri_rlmlatch_p_4522 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_dir_tid_reg | tri_rlmreg_p__parameterized37_4523 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_dvcEn_reg | tri_rlmreg_p__parameterized2_4524 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldq_rel1_entrySent_reg | tri_rlmreg_p__parameterized12_4525 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_gpr_val_reg | tri_rlmlatch_p_4526 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_l2_val_reg | tri_rlmreg_p__parameterized12_4527 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_lockSet_reg | tri_rlmlatch_p_4528 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_opsize_reg | tri_rlmreg_p__parameterized5_4529 | 47 | 47 | 0 | 0 | 3 | 0 | 0 | 0 | | ldq_rel1_p_addr_reg | tri_rlmreg_p__parameterized219_4530 | 38 | 38 | 0 | 0 | 42 | 0 | 0 | 0 | | ldq_rel1_resp_qw_reg | tri_rlmreg_p__parameterized5_4531 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ldq_rel1_rot_sel1_reg | tri_rlmreg_p__parameterized12_4532 | 408 | 408 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_rot_sel2_reg | tri_rlmreg_p__parameterized12_4533 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_rot_sel3_reg | tri_rlmreg_p__parameterized12_4534 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_rel1_tGpr_reg | tri_rlmreg_p__parameterized46_4535 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | ldq_rel1_tid_reg | tri_rlmreg_p__parameterized37_4536 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_upd_gpr_reg | tri_rlmreg_p__parameterized12_4537 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_val_reg | tri_rlmlatch_p_4538 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_watchSet_reg | tri_rlmlatch_p_4539 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_wimge_i_reg | tri_rlmlatch_p_4540 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel2_beats_home_reg | tri_rlmreg_p__parameterized12_4541 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel2_cclass_reg | tri_rlmreg_p__parameterized0_4542 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldq_rel2_entrySent_reg | tri_rlmreg_p__parameterized12_4543 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel2_l2_val_reg | tri_rlmreg_p__parameterized12_4544 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel2_set_val_reg | tri_rlmlatch_p_4545 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel2_tid_reg | tri_rlmreg_p__parameterized37_4546 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel2_upd_gpr_reg | tri_rlmreg_p__parameterized12_4547 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel3_beats_home_reg | tri_rlmreg_p__parameterized12_4548 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel3_cclass_reg | tri_rlmreg_p__parameterized0_4549 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldq_rel3_entrySent_reg | tri_rlmreg_p__parameterized12_4550 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel3_l2_val_reg | tri_rlmreg_p__parameterized12_4551 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel3_set_val_reg | tri_rlmlatch_p_4552 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel3_upd_gpr_reg | tri_rlmreg_p__parameterized12_4553 | 46 | 46 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel4_beats_home_reg | tri_rlmreg_p__parameterized12_4554 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel4_cclass_reg | tri_rlmreg_p__parameterized0_4555 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ldq_rel4_l2_val_reg | tri_rlmreg_p__parameterized12_4556 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel4_odq_cpl_reg | tri_rlmreg_p__parameterized12_4557 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel4_sentL1_reg | tri_rlmreg_p__parameterized12_4558 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel4_set_val_reg | tri_rlmlatch_p_4559 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel5_beats_home_reg | tri_rlmreg_p__parameterized12_4560 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel5_l2_val_reg | tri_rlmreg_p__parameterized12_4561 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel5_odq_cpl_reg | tri_rlmreg_p__parameterized12_4562 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel5_sentL1_reg | tri_rlmreg_p__parameterized12_4563 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel6_req_done_reg | tri_rlmreg_p__parameterized12_4564 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel_qHit_clr_reg | tri_rlmreg_p__parameterized12_4565 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_resv_qHit_held_reg | tri_rlmlatch_p_4566 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_stq_rel1_blk_store_reg | tri_rlmlatch_p_4567 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_algebraic_reg | tri_rlmreg_p__parameterized12_4568 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_axu_reg | tri_rlmreg_p__parameterized12_4569 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[0].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4570 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[1].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4571 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[2].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4572 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[3].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4573 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[4].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4574 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[5].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4575 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[6].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4576 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_beat_cntr.ldqe_beat_cntr[7].ldqe_beat_cntr_reg | tri_rlmreg_p__parameterized9_4577 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_byte_swap_reg | tri_rlmreg_p__parameterized12_4578 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[0].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4579 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[1].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4580 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[2].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4581 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[3].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4582 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[4].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4583 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[5].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4584 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[6].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4585 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_class_id.ldqe_class_id[7].ldqe_class_id_reg | tri_rlmreg_p__parameterized2_4586 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_cntr_reset_reg | tri_rlmreg_p__parameterized12_4587 | 19 | 19 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_dGpr_reg | tri_rlmreg_p__parameterized12_4588 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_dRel_reg | tri_rlmreg_p__parameterized12_4589 | 41 | 41 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[0].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4590 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[1].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4591 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[2].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4592 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[3].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4593 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[4].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4594 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[5].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4595 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[6].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4596 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dacrw.ldqe_dacrw[7].ldqe_dacrw_reg | tri_rlmreg_p__parameterized9_4597 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[0].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4598 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[1].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4599 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[2].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4600 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[3].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4601 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[4].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4602 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[5].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4603 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[6].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4604 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_dvc.ldqe_dvc[7].ldqe_dvc_reg | tri_rlmreg_p__parameterized2_4605 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[0].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4606 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[1].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4607 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[2].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4608 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[3].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4609 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[4].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4610 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[5].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4611 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[6].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4612 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_iTag.ldqe_iTag[7].ldqe_iTag_reg | tri_rlmreg_p__parameterized13_4613 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_lock_set_reg | tri_rlmreg_p__parameterized12_4614 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_mkill_reg | tri_rlmreg_p__parameterized12_4615 | 61 | 61 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_need_cpl_reg | tri_rlmreg_p__parameterized12_4616 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[0].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4617 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[1].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4618 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[2].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4619 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[3].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4620 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[4].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4621 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[5].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4622 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[6].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4623 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_op_size.ldqe_op_size[7].ldqe_op_size_reg | tri_rlmreg_p__parameterized5_4624 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[0].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4625 | 3 | 3 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[1].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4626 | 8 | 8 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[2].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4627 | 6 | 6 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[3].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4628 | 5 | 5 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[4].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4629 | 6 | 6 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[5].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4630 | 4 | 4 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[6].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4631 | 6 | 6 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_p_addr.ldqe_p_addr[7].ldqe_p_addr_reg | tri_rlmreg_p__parameterized219_4632 | 4 | 4 | 0 | 0 | 42 | 0 | 0 | 0 | | ldqe_pfetch_reg | tri_rlmreg_p__parameterized12_4633 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_qHit_held_reg | tri_rlmreg_p__parameterized12_4634 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_rel3_drop_cpl_rpt_reg | tri_rlmreg_p__parameterized12_4635 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_relDir_start_reg | tri_rlmreg_p__parameterized12_4636 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_req_cmpl_reg | tri_rlmreg_p__parameterized12_4637 | 96 | 96 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_reset_cpl_rpt_reg | tri_rlmreg_p__parameterized12_4638 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_resolved_reg | tri_rlmreg_p__parameterized12_4639 | 50 | 50 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_resv_reg | tri_rlmreg_p__parameterized12_4640 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_rst_eccdet_reg | tri_rlmreg_p__parameterized12_4641 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[0].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4642 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[1].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4643 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[2].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4644 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[3].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4645 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[4].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4646 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[5].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4647 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[6].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4648 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sentRel_cntr.ldqe_sentRel_cntr[7].ldqe_sentRel_cntr_reg | tri_rlmreg_p__parameterized9_4649 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_sent_cpl_reg | tri_rlmreg_p__parameterized12_4650 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_state.ldqe_state[0].ldqe_state_reg | tri_rlmreg_p__parameterized265 | 110 | 110 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[1].ldqe_state_reg | tri_rlmreg_p__parameterized265_4651 | 103 | 103 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[2].ldqe_state_reg | tri_rlmreg_p__parameterized265_4652 | 108 | 108 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[3].ldqe_state_reg | tri_rlmreg_p__parameterized265_4653 | 112 | 112 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[4].ldqe_state_reg | tri_rlmreg_p__parameterized265_4654 | 107 | 107 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[5].ldqe_state_reg | tri_rlmreg_p__parameterized265_4655 | 111 | 111 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[6].ldqe_state_reg | tri_rlmreg_p__parameterized265_4656 | 167 | 167 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_state.ldqe_state[7].ldqe_state_reg | tri_rlmreg_p__parameterized265_4657 | 52 | 52 | 0 | 0 | 7 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[0].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4658 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[1].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4659 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[2].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4660 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[3].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4661 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[4].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4662 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[5].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4663 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[6].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4664 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_tgpr.ldqe_tgpr[7].ldqe_tgpr_reg | tri_rlmreg_p__parameterized46_4665 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[0].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4666 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[1].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4667 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[2].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4668 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[3].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4669 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[4].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4670 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[5].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4671 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[6].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4672 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_thrd_id.ldqe_thrd_id[7].ldqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4673 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[0].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4674 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[1].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4675 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[2].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4676 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[3].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4677 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[4].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4678 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[5].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4679 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[6].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4680 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_ttype.ldqe_ttype[7].ldqe_ttype_reg | tri_rlmreg_p__parameterized0_4681 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ldqe_val_reg | tri_rlmreg_p__parameterized12_4682 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_watch_set_reg | tri_rlmreg_p__parameterized12_4683 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[0].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4684 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[1].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4685 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[2].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4686 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[3].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4687 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[4].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4688 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[5].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4689 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[6].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4690 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ldqe_wimge.ldqe_wimge[7].ldqe_wimge_reg | tri_rlmreg_p__parameterized4_4691 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgq_rel0_upd_gpr_reg | tri_rlmreg_p__parameterized12_4692 | 83 | 83 | 0 | 0 | 8 | 0 | 0 | 0 | | lgq_rel1_gpr_val_reg | tri_rlmlatch_p_4693 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | lgq_rel1_upd_gpr_reg | tri_rlmreg_p__parameterized12_4694 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | lgq_rel2_upd_gpr_reg | tri_rlmreg_p__parameterized12_4695 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | | lgq_rel3_upd_gpr_reg | tri_rlmreg_p__parameterized12_4696 | 50 | 50 | 0 | 0 | 8 | 0 | 0 | 0 | | lgq_rel4_upd_gpr_reg | tri_rlmreg_p__parameterized12_4697 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lgq_rel5_upd_gpr_reg | tri_rlmreg_p__parameterized12_4698 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_algebraic_reg | tri_rlmreg_p__parameterized12_4699 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_axu_reg | tri_rlmreg_p__parameterized12_4700 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_byte_swap_reg | tri_rlmreg_p__parameterized12_4701 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[0].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4702 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[1].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4703 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[2].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4704 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[3].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4705 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[4].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4706 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[5].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4707 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[6].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4708 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dacrw.lgqe_dacrw[7].lgqe_dacrw_reg | tri_rlmreg_p__parameterized9_4709 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[0].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4710 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[1].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4711 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[2].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4712 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[3].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4713 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[4].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4714 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[5].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4715 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[6].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4716 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_dvc.lgqe_dvc[7].lgqe_dvc_reg | tri_rlmreg_p__parameterized2_4717 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | lgqe_gpr_done_reg | tri_rlmreg_p__parameterized12_4718 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[0].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4719 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[1].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4720 | 10 | 10 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[2].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4721 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[3].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4722 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[4].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4723 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[5].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4724 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[6].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4725 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_iTag.lgqe_iTag[7].lgqe_iTag_reg | tri_rlmreg_p__parameterized13_4726 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[0].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4727 | 16 | 16 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[1].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4728 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[2].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4729 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[3].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4730 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[4].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4731 | 17 | 17 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[5].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4732 | 15 | 15 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[6].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4733 | 11 | 11 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_ldTag.lgqe_ldTag[7].lgqe_ldTag_reg | tri_rlmreg_p__parameterized9_4734 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_need_cpl_reg | tri_rlmreg_p__parameterized12_4735 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[0].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4736 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[1].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4737 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[2].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4738 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[3].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4739 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[4].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4740 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[5].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4741 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[6].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4742 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_op_size.lgqe_op_size[7].lgqe_op_size_reg | tri_rlmreg_p__parameterized5_4743 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[0].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4744 | 14 | 14 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[1].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4745 | 11 | 11 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[2].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4746 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[3].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4747 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[4].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4748 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[5].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4749 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[6].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4750 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_p_addr.lgqe_p_addr[7].lgqe_p_addr_reg | tri_rlmreg_p__parameterized13_4751 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | lgqe_resolved_reg | tri_rlmreg_p__parameterized12_4752 | 63 | 63 | 0 | 0 | 8 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[0].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4753 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[1].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4754 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[2].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4755 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[3].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4756 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[4].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4757 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[5].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4758 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[6].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4759 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_tgpr.lgqe_tgpr[7].lgqe_tgpr_reg | tri_rlmreg_p__parameterized46_4760 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[0].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4761 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[1].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4762 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[2].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4763 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[3].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4764 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[4].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4765 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[5].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4766 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[6].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4767 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_thrd_id.lgqe_thrd_id[7].lgqe_thrd_id_reg | tri_rlmreg_p__parameterized37_4768 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lgqe_valid_reg | tri_rlmreg_p__parameterized12_4769 | 169 | 169 | 0 | 0 | 8 | 0 | 0 | 0 | | lq1_iu_dacrw_reg | tri_rlmreg_p__parameterized9_4770 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lq1_iu_exception_val_reg | tri_rlmlatch_p_4771 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_iu_execute_vld_reg | tri_rlmreg_p__parameterized37_4772 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_iu_itag_reg | tri_rlmreg_p__parameterized101 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | lq1_iu_n_flush_reg | tri_rlmlatch_p_4773 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq1_iu_np1_flush_reg | tri_rlmlatch_p_4774 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_mm_lmq_stq_empty_reg | tri_rlmlatch_p_4775 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_pc_ldq_quiesce_reg | tri_rlmreg_p__parameterized37_4776 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_pc_pfetch_quiesce_reg | tri_rlmreg_p__parameterized37_4777 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_pc_stq_quiesce_reg | tri_rlmreg_p__parameterized37_4778 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_quiesce_reg | tri_rlmreg_p__parameterized37_4779 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | odq_ldq_n_flush_reg | tri_rlmlatch_p_4780 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | odq_ldq_report_itag_reg | tri_rlmreg_p__parameterized13_4781 | 76 | 76 | 0 | 0 | 7 | 0 | 0 | 0 | | odq_ldq_report_tid_reg | tri_rlmreg_p__parameterized37_4782 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | odq_ldq_resolved_reg | tri_rlmlatch_p_4783 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_blk_req_reg | tri_rlmlatch_p_4784 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_rviss_blk_reg | tri_rlmlatch_p_4785 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | relq | lq_ldq_relq | 208 | 208 | 0 | 0 | 92 | 0 | 0 | 0 | | inj_relq_parity_reg | tri_rlmlatch_p_4793 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel0_arb_cTag_reg | tri_rlmreg_p__parameterized9_4794 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ldq_rel0_arb_qw_reg | tri_rlmreg_p__parameterized5_4795 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ldq_rel0_arb_thresh_reg | tri_rlmlatch_p_4796 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel0_arb_val_reg | tri_rlmlatch_p_4797 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel1_arb_sent_reg | tri_rlmreg_p__parameterized12_4798 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ldq_rel1_beat_upd_reg | tri_rlmreg_p__parameterized12_4799 | 24 | 24 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_rel1_rdat_sel_reg | tri_rlmlatch_p_4800 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_rel2_beat_upd_reg | tri_rlmreg_p__parameterized12_4801 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_rel2_rdat_sel_reg | tri_rlmlatch_p_4802 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[0].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4803 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[1].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4804 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[2].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4805 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[3].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4806 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[4].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4807 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[5].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4808 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[6].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4809 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_relAttempts.ldqe_relAttempts[7].ldqe_relAttempts_reg | tri_rlmreg_p__parameterized192_4810 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[0].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4811 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[1].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4812 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[2].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4813 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[3].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4814 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[4].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4815 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[5].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4816 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[6].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4817 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | ldqe_rel_datRet.ldqe_rel_datRet[7].ldqe_rel_datRet_reg | tri_rlmreg_p__parameterized12_4818 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | rel_group_last_sel_reg | tri_rlmreg_p__parameterized200_4819 | 10 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | | rel_grpEntry_last_sel.rel_grpEntry_last_sel[0].rel_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4820 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | rel_grpEntry_last_sel.rel_grpEntry_last_sel[1].rel_grpEntry_last_sel_reg | tri_rlmreg_p__parameterized200_4821 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | rrotl | lq_ldq_rot | 347 | 347 | 0 | 0 | 74 | 0 | 0 | 0 | | rel2_byte_mask_reg | tri_rlmreg_p__parameterized12_4789 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | rel2_dvc1_val_reg | tri_rlmlatch_p_4790 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_dvc2_val_reg | tri_rlmlatch_p_4791 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | rel2_rot_data_reg | tri_rlmreg_p__parameterized1_4792 | 327 | 327 | 0 | 0 | 64 | 0 | 0 | 0 | | rv_lq_rvs_empty_reg | tri_rlmreg_p__parameterized37_4786 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_lsucr0_lca_reg | tri_rlmreg_p__parameterized5_4787 | 12 | 12 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_lsucr0_lge_reg | tri_rlmlatch_p_4788 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_addr_reg | tri_rlmreg_p__parameterized61 | 36 | 36 | 0 | 0 | 38 | 0 | 0 | 0 | | ldq_odq_cline_chk_reg | tri_rlmlatch_p_3381 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_inv_reg | tri_rlmlatch_p_3382 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_itag_reg | tri_rlmreg_p__parameterized13_3383 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | odq | lq_odq | 4094 | 4094 | 0 | 0 | 1672 | 0 | 0 | 0 | | collision_vector_reg | tri_rlmreg_p__parameterized3_3959 | 54 | 54 | 0 | 0 | 15 | 0 | 0 | 0 | | compress_val_reg | tri_rlmlatch_p_3960 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush2_reg | tri_rlmreg_p__parameterized37_3961 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush3_reg | tri_rlmreg_p__parameterized37_3962 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush4_reg | tri_rlmreg_p__parameterized37_3963 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush5_reg | tri_rlmreg_p__parameterized37_3964 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_3965 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_i0_completed_itag_latch_gen[0].cp_i0_completed_itag_latch | tri_rlmreg_p__parameterized13_3966 | 65 | 65 | 0 | 0 | 7 | 0 | 0 | 0 | | cp_i0_completed_latch | tri_rlmreg_p__parameterized37_3967 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_i1_completed_itag_latch_gen[0].cp_i1_completed_itag_latch | tri_rlmreg_p__parameterized13_3968 | 64 | 64 | 0 | 0 | 7 | 0 | 0 | 0 | | cp_i1_completed_latch | tri_rlmreg_p__parameterized37_3969 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex0_blk_reg | tri_rlmlatch_p_3970 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex1_blk_reg | tri_rlmlatch_p_3971 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex2_blk_reg | tri_rlmlatch_p_3972 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex3_blk_reg | tri_rlmlatch_p_3973 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex4_blk_reg | tri_rlmlatch_p_3974 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex5_blk_reg | tri_rlmlatch_p_3975 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_ex6_blk_reg | tri_rlmlatch_p_3976 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | entry_rv1_blk_reg | tri_rlmlatch_p_3977 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_binv_addr_reg | tri_rlmreg_p__parameterized0_3978 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | ex0_binv_val_reg | tri_rlmlatch_p_3979 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_isLoad_reg | tri_rlmlatch_p_3980 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_isStore_reg | tri_rlmlatch_p_3981 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_itag_reg | tri_rlmreg_p__parameterized13_3982 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_i0_rte_lq_reg | tri_rlmlatch_p_3983 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_rte_sq_reg | tri_rlmlatch_p_3984 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_s3_t_reg | tri_rlmreg_p__parameterized5_3985 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_i0_ucode_preissue_reg | tri_rlmlatch_p_3986 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_vld_reg | tri_rlmreg_p__parameterized37_3987 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_isLoad_reg | tri_rlmlatch_p_3988 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_isStore_reg | tri_rlmlatch_p_3989 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_itag_reg | tri_rlmreg_p__parameterized13_3990 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_i1_rte_lq_reg | tri_rlmlatch_p_3991 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_rte_sq_reg | tri_rlmlatch_p_3992 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_s3_t_reg | tri_rlmreg_p__parameterized5_3993 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_i1_ucode_preissue_reg | tri_rlmlatch_p_3994 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_vld_reg | tri_rlmreg_p__parameterized37_3995 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_binv_addr_reg | tri_rlmreg_p__parameterized0_3996 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_binv_val_reg | tri_rlmlatch_p_3997 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_instq_reg | tri_rlmlatch_p_3998 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_isLoad_reg | tri_rlmlatch_p_3999 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_itag_reg | tri_rlmreg_p__parameterized13_4000 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_i0_pre_reg | tri_rlmlatch_p_4001 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_vld_reg | tri_rlmreg_p__parameterized37_4002 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_instq_reg | tri_rlmlatch_p_4003 | 31 | 31 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_isLoad_reg | tri_rlmlatch_p_4004 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_itag_reg | tri_rlmreg_p__parameterized13_4005 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_i1_pre_reg | tri_rlmlatch_p_4006 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_vld_reg | tri_rlmreg_p__parameterized37_4007 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_binv_addr_reg | tri_rlmreg_p__parameterized0_4008 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_binv_val_reg | tri_rlmlatch_p_4009 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_binv_addr_reg | tri_rlmreg_p__parameterized0_4010 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_binv_val_reg | tri_rlmlatch_p_4011 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_binv_addr_reg | tri_rlmreg_p__parameterized0_4012 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_binv_val_reg | tri_rlmlatch_p_4013 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_binv_addr_reg | tri_rlmreg_p__parameterized0_4014 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_binv_val_reg | tri_rlmlatch_p_4015 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | flushed_credit_count[0].flushed_credit_count_reg | tri_rlmreg_p__parameterized9_4016 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | ldq_odq_cline_chk_reg | tri_rlmlatch_p_4017 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_fwd_reg | tri_rlmlatch_p_4018 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_hit_reg | tri_rlmlatch_p_4019 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_inv_reg | tri_rlmlatch_p_4020 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_itag_reg | tri_rlmreg_p__parameterized13_4021 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ldq_odq_pfetch_vld_ex6_reg | tri_rlmlatch_p_4022 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_tid_reg | tri_rlmreg_p__parameterized37_4023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_vld_reg | tri_rlmlatch_p_4024 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ldq_odq_wimge_i_reg | tri_rlmlatch_p_4025 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_iu_credit_free_reg | tri_rlmreg_p__parameterized37_4026 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | next_fill_ptr_reg | tri_rlmreg_p__parameterized264 | 853 | 853 | 0 | 0 | 17 | 0 | 0 | 0 | | odq_ldq_ex7_pfetch_blk_reg | tri_rlmlatch_p_4027 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4028 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_cmmt_reg | tri_rlmlatch_p_4029 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4030 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[0].orderq_entry_eccue_reg | tri_rlmlatch_p_4031 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_flushed_reg | tri_rlmlatch_p_4032 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_hit_reg | tri_rlmlatch_p_4033 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_instq_reg | tri_rlmlatch_p_4034 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_inuse_reg | tri_rlmlatch_p_4035 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4036 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[0].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4037 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_ld_reg | tri_rlmlatch_p_4038 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_n_flush_reg | tri_rlmlatch_p_4039 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4040 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_pre_reg | tri_rlmlatch_p_4041 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4042 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[0].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4043 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_val2_reg | tri_rlmlatch_p_4044 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[0].orderq_entry_val_reg | tri_rlmlatch_p_4045 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4046 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[10].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4047 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[10].addrq_entry_inuse_reg | tri_rlmlatch_p_4048 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4049 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[10].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4050 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].addrq_entry_val_reg | tri_rlmlatch_p_4051 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4052 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4053 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_cls_op_reg | tri_rlmlatch_p_4054 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_cmmt_reg | tri_rlmlatch_p_4055 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4056 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[10].orderq_entry_eccue_reg | tri_rlmlatch_p_4057 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_flushed_reg | tri_rlmlatch_p_4058 | 109 | 109 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_hit_reg | tri_rlmlatch_p_4059 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_i_reg | tri_rlmlatch_p_4060 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_instq_reg | tri_rlmlatch_p_4061 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_inuse_reg | tri_rlmlatch_p_4062 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4063 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[10].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4064 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_ld_reg | tri_rlmlatch_p_4065 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_n_flush_reg | tri_rlmlatch_p_4066 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4067 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_pre_reg | tri_rlmlatch_p_4068 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4069 | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[10].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4070 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_val2_reg | tri_rlmlatch_p_4071 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[10].orderq_entry_val_reg | tri_rlmlatch_p_4072 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4073 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[11].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4074 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[11].addrq_entry_inuse_reg | tri_rlmlatch_p_4075 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4076 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[11].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4077 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].addrq_entry_val_reg | tri_rlmlatch_p_4078 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4079 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4080 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_cls_op_reg | tri_rlmlatch_p_4081 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_cmmt_reg | tri_rlmlatch_p_4082 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4083 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[11].orderq_entry_eccue_reg | tri_rlmlatch_p_4084 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_flushed_reg | tri_rlmlatch_p_4085 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_hit_reg | tri_rlmlatch_p_4086 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_i_reg | tri_rlmlatch_p_4087 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_instq_reg | tri_rlmlatch_p_4088 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_inuse_reg | tri_rlmlatch_p_4089 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4090 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[11].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4091 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_ld_reg | tri_rlmlatch_p_4092 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_n_flush_reg | tri_rlmlatch_p_4093 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4094 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_pre_reg | tri_rlmlatch_p_4095 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4096 | 22 | 22 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[11].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4097 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_val2_reg | tri_rlmlatch_p_4098 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[11].orderq_entry_val_reg | tri_rlmlatch_p_4099 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4100 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[12].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4101 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[12].addrq_entry_inuse_reg | tri_rlmlatch_p_4102 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4103 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[12].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4104 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].addrq_entry_val_reg | tri_rlmlatch_p_4105 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4106 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4107 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_cls_op_reg | tri_rlmlatch_p_4108 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_cmmt_reg | tri_rlmlatch_p_4109 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4110 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[12].orderq_entry_eccue_reg | tri_rlmlatch_p_4111 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_flushed_reg | tri_rlmlatch_p_4112 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_hit_reg | tri_rlmlatch_p_4113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_i_reg | tri_rlmlatch_p_4114 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_instq_reg | tri_rlmlatch_p_4115 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_inuse_reg | tri_rlmlatch_p_4116 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4117 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[12].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4118 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_ld_reg | tri_rlmlatch_p_4119 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_n_flush_reg | tri_rlmlatch_p_4120 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4121 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_pre_reg | tri_rlmlatch_p_4122 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4123 | 88 | 88 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[12].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4124 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_val2_reg | tri_rlmlatch_p_4125 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[12].orderq_entry_val_reg | tri_rlmlatch_p_4126 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4127 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[13].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4128 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[13].addrq_entry_inuse_reg | tri_rlmlatch_p_4129 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4130 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[13].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4131 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].addrq_entry_val_reg | tri_rlmlatch_p_4132 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4133 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4134 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_cls_op_reg | tri_rlmlatch_p_4135 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_cmmt_reg | tri_rlmlatch_p_4136 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4137 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[13].orderq_entry_eccue_reg | tri_rlmlatch_p_4138 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_flushed_reg | tri_rlmlatch_p_4139 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_hit_reg | tri_rlmlatch_p_4140 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_i_reg | tri_rlmlatch_p_4141 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_instq_reg | tri_rlmlatch_p_4142 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_inuse_reg | tri_rlmlatch_p_4143 | 58 | 58 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4144 | 24 | 24 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[13].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4145 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_ld_reg | tri_rlmlatch_p_4146 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_n_flush_reg | tri_rlmlatch_p_4147 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4148 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_pre_reg | tri_rlmlatch_p_4149 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4150 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[13].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4151 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_val2_reg | tri_rlmlatch_p_4152 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[13].orderq_entry_val_reg | tri_rlmlatch_p_4153 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4154 | 72 | 72 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[14].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4155 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[14].addrq_entry_inuse_reg | tri_rlmlatch_p_4156 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4157 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[14].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4158 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].addrq_entry_val_reg | tri_rlmlatch_p_4159 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4160 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4161 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_cls_op_reg | tri_rlmlatch_p_4162 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_cmmt_reg | tri_rlmlatch_p_4163 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4164 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[14].orderq_entry_eccue_reg | tri_rlmlatch_p_4165 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_flushed_reg | tri_rlmlatch_p_4166 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_hit_reg | tri_rlmlatch_p_4167 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_i_reg | tri_rlmlatch_p_4168 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_instq_reg | tri_rlmlatch_p_4169 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_inuse_reg | tri_rlmlatch_p_4170 | 21 | 21 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4171 | 18 | 18 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[14].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4172 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_ld_reg | tri_rlmlatch_p_4173 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_n_flush_reg | tri_rlmlatch_p_4174 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4175 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_pre_reg | tri_rlmlatch_p_4176 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4177 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[14].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4178 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_val2_reg | tri_rlmlatch_p_4179 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[14].orderq_entry_val_reg | tri_rlmlatch_p_4180 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4181 | 31 | 31 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[15].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4182 | 8 | 8 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[15].addrq_entry_inuse_reg | tri_rlmlatch_p_4183 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4184 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[15].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4185 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].addrq_entry_val_reg | tri_rlmlatch_p_4186 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4187 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4188 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_cls_op_reg | tri_rlmlatch_p_4189 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_cmmt_reg | tri_rlmlatch_p_4190 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4191 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[15].orderq_entry_eccue_reg | tri_rlmlatch_p_4192 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_flushed_reg | tri_rlmlatch_p_4193 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_hit_reg | tri_rlmlatch_p_4194 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_i_reg | tri_rlmlatch_p_4195 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_instq_reg | tri_rlmlatch_p_4196 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_inuse_reg | tri_rlmlatch_p_4197 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4198 | 13 | 13 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[15].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4199 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_ld_reg | tri_rlmlatch_p_4200 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_n_flush_reg | tri_rlmlatch_p_4201 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4202 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_pre_reg | tri_rlmlatch_p_4203 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4204 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[15].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4205 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_val2_reg | tri_rlmlatch_p_4206 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[15].orderq_entry_val_reg | tri_rlmlatch_p_4207 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4208 | 71 | 71 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[1].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4209 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[1].addrq_entry_inuse_reg | tri_rlmlatch_p_4210 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4211 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[1].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4212 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].addrq_entry_val_reg | tri_rlmlatch_p_4213 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4214 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4215 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_cls_op_reg | tri_rlmlatch_p_4216 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_cmmt_reg | tri_rlmlatch_p_4217 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4218 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[1].orderq_entry_eccue_reg | tri_rlmlatch_p_4219 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_flushed_reg | tri_rlmlatch_p_4220 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_hit_reg | tri_rlmlatch_p_4221 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_i_reg | tri_rlmlatch_p_4222 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_instq_reg | tri_rlmlatch_p_4223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_inuse_reg | tri_rlmlatch_p_4224 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4225 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[1].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4226 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_ld_reg | tri_rlmlatch_p_4227 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_n_flush_reg | tri_rlmlatch_p_4228 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4229 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_pre_reg | tri_rlmlatch_p_4230 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4231 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[1].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4232 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_val2_reg | tri_rlmlatch_p_4233 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[1].orderq_entry_val_reg | tri_rlmlatch_p_4234 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4235 | 72 | 72 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[2].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4236 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[2].addrq_entry_inuse_reg | tri_rlmlatch_p_4237 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4238 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[2].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4239 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].addrq_entry_val_reg | tri_rlmlatch_p_4240 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4241 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4242 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_cls_op_reg | tri_rlmlatch_p_4243 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_cmmt_reg | tri_rlmlatch_p_4244 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4245 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[2].orderq_entry_eccue_reg | tri_rlmlatch_p_4246 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_flushed_reg | tri_rlmlatch_p_4247 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_hit_reg | tri_rlmlatch_p_4248 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_i_reg | tri_rlmlatch_p_4249 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_instq_reg | tri_rlmlatch_p_4250 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_inuse_reg | tri_rlmlatch_p_4251 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4252 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[2].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4253 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_ld_reg | tri_rlmlatch_p_4254 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_n_flush_reg | tri_rlmlatch_p_4255 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4256 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_pre_reg | tri_rlmlatch_p_4257 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4258 | 34 | 34 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[2].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4259 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_val2_reg | tri_rlmlatch_p_4260 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[2].orderq_entry_val_reg | tri_rlmlatch_p_4261 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4262 | 72 | 72 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[3].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4263 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[3].addrq_entry_inuse_reg | tri_rlmlatch_p_4264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4265 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[3].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4266 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].addrq_entry_val_reg | tri_rlmlatch_p_4267 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4268 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4269 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_cls_op_reg | tri_rlmlatch_p_4270 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_cmmt_reg | tri_rlmlatch_p_4271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4272 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[3].orderq_entry_eccue_reg | tri_rlmlatch_p_4273 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_flushed_reg | tri_rlmlatch_p_4274 | 19 | 19 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_hit_reg | tri_rlmlatch_p_4275 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_i_reg | tri_rlmlatch_p_4276 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_instq_reg | tri_rlmlatch_p_4277 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_inuse_reg | tri_rlmlatch_p_4278 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4279 | 17 | 17 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[3].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4280 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_ld_reg | tri_rlmlatch_p_4281 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_n_flush_reg | tri_rlmlatch_p_4282 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4283 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_pre_reg | tri_rlmlatch_p_4284 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4285 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[3].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4286 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_val2_reg | tri_rlmlatch_p_4287 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[3].orderq_entry_val_reg | tri_rlmlatch_p_4288 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4289 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[4].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4290 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[4].addrq_entry_inuse_reg | tri_rlmlatch_p_4291 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4292 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[4].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4293 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].addrq_entry_val_reg | tri_rlmlatch_p_4294 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4295 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4296 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_cls_op_reg | tri_rlmlatch_p_4297 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_cmmt_reg | tri_rlmlatch_p_4298 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4299 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[4].orderq_entry_eccue_reg | tri_rlmlatch_p_4300 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_flushed_reg | tri_rlmlatch_p_4301 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_hit_reg | tri_rlmlatch_p_4302 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_i_reg | tri_rlmlatch_p_4303 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_instq_reg | tri_rlmlatch_p_4304 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_inuse_reg | tri_rlmlatch_p_4305 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4306 | 24 | 24 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[4].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4307 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_ld_reg | tri_rlmlatch_p_4308 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_n_flush_reg | tri_rlmlatch_p_4309 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4310 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_pre_reg | tri_rlmlatch_p_4311 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4312 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[4].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4313 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_val2_reg | tri_rlmlatch_p_4314 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[4].orderq_entry_val_reg | tri_rlmlatch_p_4315 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4316 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[5].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4317 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[5].addrq_entry_inuse_reg | tri_rlmlatch_p_4318 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4319 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[5].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4320 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].addrq_entry_val_reg | tri_rlmlatch_p_4321 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4322 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4323 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_cls_op_reg | tri_rlmlatch_p_4324 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_cmmt_reg | tri_rlmlatch_p_4325 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4326 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[5].orderq_entry_eccue_reg | tri_rlmlatch_p_4327 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_flushed_reg | tri_rlmlatch_p_4328 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_hit_reg | tri_rlmlatch_p_4329 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_i_reg | tri_rlmlatch_p_4330 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_instq_reg | tri_rlmlatch_p_4331 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_inuse_reg | tri_rlmlatch_p_4332 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4333 | 20 | 20 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[5].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4334 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_ld_reg | tri_rlmlatch_p_4335 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_n_flush_reg | tri_rlmlatch_p_4336 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4337 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_pre_reg | tri_rlmlatch_p_4338 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4339 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[5].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4340 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_val2_reg | tri_rlmlatch_p_4341 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[5].orderq_entry_val_reg | tri_rlmlatch_p_4342 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4343 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[6].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4344 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[6].addrq_entry_inuse_reg | tri_rlmlatch_p_4345 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4346 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[6].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4347 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].addrq_entry_val_reg | tri_rlmlatch_p_4348 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4349 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4350 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_cls_op_reg | tri_rlmlatch_p_4351 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_cmmt_reg | tri_rlmlatch_p_4352 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4353 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[6].orderq_entry_eccue_reg | tri_rlmlatch_p_4354 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_flushed_reg | tri_rlmlatch_p_4355 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_hit_reg | tri_rlmlatch_p_4356 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_i_reg | tri_rlmlatch_p_4357 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_instq_reg | tri_rlmlatch_p_4358 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_inuse_reg | tri_rlmlatch_p_4359 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4360 | 18 | 18 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[6].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4361 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_ld_reg | tri_rlmlatch_p_4362 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_n_flush_reg | tri_rlmlatch_p_4363 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4364 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_pre_reg | tri_rlmlatch_p_4365 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4366 | 58 | 58 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[6].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4367 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_val2_reg | tri_rlmlatch_p_4368 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[6].orderq_entry_val_reg | tri_rlmlatch_p_4369 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4370 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[7].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4371 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[7].addrq_entry_inuse_reg | tri_rlmlatch_p_4372 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4373 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[7].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4374 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].addrq_entry_val_reg | tri_rlmlatch_p_4375 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4376 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4377 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_cls_op_reg | tri_rlmlatch_p_4378 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_cmmt_reg | tri_rlmlatch_p_4379 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4380 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[7].orderq_entry_eccue_reg | tri_rlmlatch_p_4381 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_flushed_reg | tri_rlmlatch_p_4382 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_hit_reg | tri_rlmlatch_p_4383 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_i_reg | tri_rlmlatch_p_4384 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_instq_reg | tri_rlmlatch_p_4385 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_inuse_reg | tri_rlmlatch_p_4386 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4387 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[7].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4388 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_ld_reg | tri_rlmlatch_p_4389 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_n_flush_reg | tri_rlmlatch_p_4390 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4391 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_pre_reg | tri_rlmlatch_p_4392 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4393 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[7].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4394 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_val2_reg | tri_rlmlatch_p_4395 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[7].orderq_entry_val_reg | tri_rlmlatch_p_4396 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4397 | 69 | 69 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[8].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4398 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[8].addrq_entry_inuse_reg | tri_rlmlatch_p_4399 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4400 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[8].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4401 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].addrq_entry_val_reg | tri_rlmlatch_p_4402 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4403 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4404 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_cls_op_reg | tri_rlmlatch_p_4405 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_cmmt_reg | tri_rlmlatch_p_4406 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4407 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[8].orderq_entry_eccue_reg | tri_rlmlatch_p_4408 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_flushed_reg | tri_rlmlatch_p_4409 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_hit_reg | tri_rlmlatch_p_4410 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_i_reg | tri_rlmlatch_p_4411 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_instq_reg | tri_rlmlatch_p_4412 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_inuse_reg | tri_rlmlatch_p_4413 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4414 | 19 | 19 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[8].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4415 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_ld_reg | tri_rlmlatch_p_4416 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_n_flush_reg | tri_rlmlatch_p_4417 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4418 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_pre_reg | tri_rlmlatch_p_4419 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4420 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[8].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4421 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_val2_reg | tri_rlmlatch_p_4422 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[8].orderq_entry_val_reg | tri_rlmlatch_p_4423 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].addrq_entry_address_reg | tri_rlmreg_p__parameterized61_4424 | 70 | 70 | 0 | 0 | 38 | 0 | 0 | 0 | | oqe[9].addrq_entry_bytemask_reg | tri_rlmreg_p__parameterized3_4425 | 24 | 24 | 0 | 0 | 16 | 0 | 0 | 0 | | oqe[9].addrq_entry_inuse_reg | tri_rlmlatch_p_4426 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].addrq_entry_itag_reg | tri_rlmreg_p__parameterized13_4427 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[9].addrq_entry_tid_reg | tri_rlmreg_p__parameterized37_4428 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].addrq_entry_val_reg | tri_rlmlatch_p_4429 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_bi_flag_reg | tri_rlmlatch_p_4430 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_bi_flush_reg | tri_rlmlatch_p_4431 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_cls_op_reg | tri_rlmlatch_p_4432 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_cmmt_reg | tri_rlmlatch_p_4433 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_dacrw_reg | tri_rlmreg_p__parameterized9_4434 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[9].orderq_entry_eccue_reg | tri_rlmlatch_p_4435 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_flushed_reg | tri_rlmlatch_p_4436 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_hit_reg | tri_rlmlatch_p_4437 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_i_reg | tri_rlmlatch_p_4438 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_instq_reg | tri_rlmlatch_p_4439 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_inuse_reg | tri_rlmlatch_p_4440 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_itag_reg | tri_rlmreg_p__parameterized13_4441 | 18 | 18 | 0 | 0 | 7 | 0 | 0 | 0 | | oqe[9].orderq_entry_ld_chk_reg | tri_rlmlatch_p_4442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_ld_reg | tri_rlmlatch_p_4443 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_n_flush_reg | tri_rlmlatch_p_4444 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_np1_flush_reg | tri_rlmlatch_p_4445 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_pre_reg | tri_rlmlatch_p_4446 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_stTag_reg | tri_rlmreg_p__parameterized9_4447 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | oqe[9].orderq_entry_tid_reg | tri_rlmreg_p__parameterized37_4448 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_val2_reg | tri_rlmlatch_p_4449 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | oqe[9].orderq_entry_val_reg | tri_rlmlatch_p_4450 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_binv_addr_reg | tri_rlmreg_p__parameterized0_4451 | 10 | 10 | 0 | 0 | 6 | 0 | 0 | 0 | | rv1_binv_val_reg | tri_rlmlatch_p_4452 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_spr_xucr0_cls_reg | tri_rlmlatch_p_4453 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_1to0_reg | tri_plat__parameterized7 | 517 | 517 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_2to1_reg | tri_plat__parameterized7_3384 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | rv1_back_inv_addr_reg | tri_rlmreg_p__parameterized52 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xucr0_cls_reg | tri_rlmlatch_p_3385 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq | lq_stq | 10789 | 10789 | 0 | 0 | 3408 | 0 | 0 | 0 | | any_ack_hold_latch | tri_rlmreg_p__parameterized37_3386 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | any_ack_val_ok_latch | tri_rlmreg_p__parameterized37_3387 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | arb_release_itag_vld_latch | tri_rlmreg_p__parameterized37_3388 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_3389 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_i0_completed_latch | tri_rlmreg_p__parameterized37_3390 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_i1_completed_latch | tri_rlmreg_p__parameterized37_3391 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_next_val_latch | tri_rlmreg_p__parameterized37_3392 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cr_ack_latch | tri_rlmreg_p__parameterized37_3393 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cr_wa_latch | tri_rlmreg_p__parameterized4_3394 | 12 | 12 | 0 | 0 | 5 | 0 | 0 | 0 | | cr_wd_latch | tri_rlmreg_p__parameterized9_3395 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | cr_we_latch | tri_rlmlatch_p_3396 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | credit_free_latch | tri_rlmreg_p__parameterized37_3397 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dbg_int_en_latch | tri_rlmreg_p__parameterized37_3398 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_binv_addr_latch | tri_rlmreg_p__parameterized0_3399 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex0_binv_val_latch | tri_rlmlatch_p_3400 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_cr_hole_latch | tri_rlmreg_p__parameterized37_3401 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_dir_rd_val_latch | tri_rlmlatch_p_3402 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_flushed_latch | tri_rlmlatch_p_3403 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i0_itag_latch | tri_rlmreg_p__parameterized13_3404 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_i0_vld_latch | tri_rlmreg_p__parameterized37_3405 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_flushed_latch | tri_rlmlatch_p_3406 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_i1_itag_latch | tri_rlmreg_p__parameterized13_3407 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_i1_vld_latch | tri_rlmreg_p__parameterized37_3408 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_binv_addr_latch | tri_rlmreg_p__parameterized0_3409 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_binv_val_latch | tri_rlmlatch_p_3410 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_flushed_latch | tri_rlmlatch_p_3411 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i0_itag_latch | tri_rlmreg_p__parameterized13_3412 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_i0_vld_latch | tri_rlmreg_p__parameterized37_3413 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_flushed_latch | tri_rlmlatch_p_3414 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_i1_itag_latch | tri_rlmreg_p__parameterized13_3415 | 133 | 133 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_i1_vld_latch | tri_rlmreg_p__parameterized37_3416 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_binv_addr_latch | tri_rlmreg_p__parameterized0_3417 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_binv_val_latch | tri_rlmlatch_p_3418 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_axu_itag_latch | tri_rlmreg_p__parameterized13_3419 | 60 | 60 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_axu_val_latch | tri_rlmreg_p__parameterized37_3420 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_binv_addr_latch | tri_rlmreg_p__parameterized0_3421 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_binv_val_latch | tri_rlmlatch_p_3422 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_fxu1_dvc1_cmp_latch | tri_rlmreg_p__parameterized12_3423 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_fxu1_dvc2_cmp_latch | tri_rlmreg_p__parameterized12_3424 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_fxu1_itag_latch | tri_rlmreg_p__parameterized13_3425 | 51 | 51 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_fxu1_val_latch | tri_rlmreg_p__parameterized37_3426 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_nxt_oldest_latch | tri_rlmreg_p__parameterized227_3427 | 31 | 31 | 0 | 0 | 12 | 0 | 0 | 0 | | ex3_req_itag_latch | tri_rlmreg_p__parameterized13_3428 | 478 | 478 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_req_thrd_id_latch | tri_rlmreg_p__parameterized37_3429 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_streq_val_latch | tri_rlmreg_p__parameterized37_3430 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_axu_data_ptr_latch | tri_rlmreg_p__parameterized227_3431 | 10 | 10 | 0 | 0 | 12 | 0 | 0 | 0 | | ex4_axu_val_latch | tri_rlmreg_p__parameterized37_3432 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_fu_data_latch | tri_rlmreg_p__parameterized33_3433 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_fwd_agecmp_latch | tri_rlmreg_p__parameterized227_3434 | 36 | 36 | 0 | 0 | 12 | 0 | 0 | 0 | | ex4_fxu1_data_ptr_latch | tri_rlmreg_p__parameterized227_3435 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | ex4_fxu1_illeg_lswx_latch | tri_rlmlatch_p_3436 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_fxu1_strg_noop_latch | tri_rlmlatch_p_3437 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_fxu1_val_latch | tri_rlmreg_p__parameterized37_3438 | 1448 | 1448 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ldreq_val_latch | tri_rlmreg_p__parameterized37_3439 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_pfetch_val_latch | tri_rlmlatch_p_3440 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_req_algebraic_latch | tri_rlmlatch_p_3441 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_req_byte_en_latch | tri_rlmreg_p__parameterized3_3442 | 12 | 12 | 0 | 0 | 16 | 0 | 0 | 0 | | ex4_req_opsize_latch | tri_rlmreg_p__parameterized5_3443 | 133 | 133 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_req_p_addr_l_latch | tri_rlmreg_p__parameterized0_3444 | 55 | 55 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_req_thrd_id_latch | tri_rlmreg_p__parameterized37_3445 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_set_stq_latch | tri_rlmreg_p__parameterized227_3446 | 790 | 790 | 0 | 0 | 12 | 0 | 0 | 0 | | ex4_wchkall_val_latch | tri_rlmreg_p__parameterized37_3447 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_fwd_data_latch | tri_rlmreg_p__parameterized33_3448 | 223 | 223 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_fwd_val_latch | tri_rlmlatch_p_3449 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_older_ldmiss_latch | tri_rlmreg_p__parameterized227_3450 | 8 | 8 | 0 | 0 | 12 | 0 | 0 | 0 | | ex5_qHit_set_miss_latch | tri_rlmreg_p__parameterized227_3451 | 13 | 13 | 0 | 0 | 12 | 0 | 0 | 0 | | ex5_qHit_set_oth_latch | tri_rlmreg_p__parameterized227_3452 | 32 | 32 | 0 | 0 | 12 | 0 | 0 | 0 | | ex5_req_thrd_id_latch | tri_rlmreg_p__parameterized37_3453 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_set_stq_latch | tri_rlmreg_p__parameterized227_3454 | 567 | 567 | 0 | 0 | 12 | 0 | 0 | 0 | | ex5_stq_restart_latch | tri_rlmlatch_p_3455 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_stq_restart_miss_latch | tri_rlmlatch_p_3456 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_streq_val_latch | tri_rlmreg_p__parameterized37_3457 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_ack_queue_dacrw_rpt_latch | tri_rlmreg_p__parameterized37_3458 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_ack_queue_stcx_latch | tri_rlmreg_p__parameterized37_3459 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_ack_queue_sync_latch | tri_rlmreg_p__parameterized37_3460 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_ack_queue_v_latch | tri_rlmreg_p__parameterized37_3461 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | icbi_ack_latch | tri_rlmreg_p__parameterized37_3462 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | icbi_addr_latch | tri_rlmreg_p__parameterized52_3463 | 36 | 36 | 0 | 0 | 36 | 0 | 0 | 0 | | icbi_val_latch | tri_rlmreg_p__parameterized37_3464 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ici_val_latch | tri_rlmlatch_p_3465 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | icswxr_ack_dly1_latch | tri_rlmlatch_p_3466 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | icswxr_ack_latch | tri_rlmlatch_p_3467 | 27 | 27 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_icbi_ack_latch | tri_rlmreg_p__parameterized37_3468 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_lq_icbi_complete_latch | tri_rlmreg_p__parameterized37_3469 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | l2_icbi_ack_latch | tri_rlmreg_p__parameterized37_3470 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | local_instr_ack_latch | tri_rlmreg_p__parameterized37_3471 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lwsync_ack_latch | tri_rlmreg_p__parameterized37_3472 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | resv_ack_latch | tri_rlmreg_p__parameterized37_3473 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_cp_flush_latch | tri_rlmreg_p__parameterized37_3474 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_cr_hole_latch | tri_rlmreg_p__parameterized37_3475 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_binv_addr_latch | tri_rlmreg_p__parameterized0_3476 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | rv1_binv_val_latch | tri_rlmlatch_p_3477 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_cp_flush_latch | tri_rlmreg_p__parameterized37_3478 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_cr_hole_latch | tri_rlmreg_p__parameterized37_3479 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_lq_ld_vld_latch | tri_rlmlatch_p_3480 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_lq_vld_latch | tri_rlmlatch_p_3481 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_iucr0_icbi_ack_latch | tri_rlmlatch_p_3482 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_lsucr0_dfwd_latch | tri_rlmlatch_p_3483 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stcx_pass_latch | tri_rlmreg_p__parameterized37_3484 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq1_cmmt_ptr_latch | tri_rlmreg_p__parameterized267 | 1041 | 1041 | 0 | 0 | 24 | 0 | 0 | 0 | | stq2_binv_blk_cclass_latch | tri_rlmlatch_p_3485 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_cmmt_flushed_latch | tri_rlmlatch_p_3486 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3487 | 468 | 468 | 0 | 0 | 12 | 0 | 0 | 0 | | stq2_cmmt_val_latch | tri_rlmlatch_p_3488 | 29 | 29 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_dci_val_latch | tri_rlmlatch_p_3489 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_ici_val_latch | tri_rlmlatch_p_3490 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_mftgpr_val_latch | tri_rlmlatch_p_3491 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_reject_dci_latch | tri_rlmlatch_p_3492 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq2_rtry_cnt_latch | tri_rlmreg_p__parameterized191 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | stq3_cmmt_dci_val_latch | tri_rlmlatch_p_3493 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_cmmt_flushed_latch | tri_rlmlatch_p_3494 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3495 | 357 | 357 | 0 | 0 | 12 | 0 | 0 | 0 | | stq3_cmmt_reject_latch | tri_rlmlatch_p_3496 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq3_cmmt_val_latch | tri_rlmlatch_p_3497 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_cmmt_dci_val_latch | tri_rlmlatch_p_3498 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_cmmt_flushed_latch | tri_rlmlatch_p_3499 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3500 | 28 | 28 | 0 | 0 | 12 | 0 | 0 | 0 | | stq4_cmmt_tag_latch | tri_rlmreg_p__parameterized9_3501 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | stq4_cmmt_val_latch | tri_rlmlatch_p_3502 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq4_xucr0_cul_latch | tri_rlmlatch_p_3503 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_cmmt_dci_val_latch | tri_rlmlatch_p_3504 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_cmmt_flushed_latch | tri_rlmlatch_p_3505 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq5_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3506 | 114 | 114 | 0 | 0 | 12 | 0 | 0 | 0 | | stq5_cmmt_val_latch | tri_rlmlatch_p_3507 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_cmmt_flushed_latch | tri_rlmlatch_p_3508 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stq6_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3509 | 84 | 84 | 0 | 0 | 12 | 0 | 0 | 0 | | stq6_cmmt_val_latch | tri_rlmlatch_p_3510 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_cmmt_flushed_latch | tri_rlmlatch_p_3511 | 172 | 172 | 0 | 0 | 1 | 0 | 0 | 0 | | stq7_cmmt_ptr_latch | tri_rlmreg_p__parameterized227_3512 | 137 | 137 | 0 | 0 | 12 | 0 | 0 | 0 | | stq7_cmmt_val_latch | tri_rlmlatch_p_3513 | 70 | 70 | 0 | 0 | 1 | 0 | 0 | 0 | | stq_cpl_need_hold_reg | tri_rlmlatch_p_3514 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stq_fwd_pri_mask_latch | tri_rlmreg_p__parameterized5_3515 | 227 | 227 | 0 | 0 | 3 | 0 | 0 | 0 | | stq_tag_val_latch | tri_rlmreg_p__parameterized227_3516 | 245 | 245 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_ack_rcvd_latch | tri_rlmreg_p__parameterized227_3517 | 30 | 30 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_addr_val_latch | tri_rlmreg_p__parameterized227_3518 | 31 | 31 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_alloc_latch | tri_rlmreg_p__parameterized227_3519 | 52 | 52 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_alloc_ptr_latch | tri_rlmreg_p__parameterized267_3520 | 255 | 255 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[0].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3521 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[10].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3522 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[11].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3523 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[1].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3524 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[2].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[3].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3526 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[4].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3527 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[5].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3528 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[6].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3529 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[7].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3530 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[8].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3531 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_blk_loads_latch_gen.stqe_blk_loads_latch_gen[9].stqe_blk_loads_latch | tri_rlmreg_p__parameterized37_3532 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | stqe_compl_rcvd_latch | tri_rlmreg_p__parameterized227_3533 | 27 | 27 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_data_nxt_latch | tri_rlmreg_p__parameterized227_3534 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_data_val_latch | tri_rlmreg_p__parameterized227_3535 | 25 | 25 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_flushed_latch | tri_rlmreg_p__parameterized227_3536 | 229 | 229 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_fwd_addr_val_latch | tri_rlmreg_p__parameterized227_3537 | 33 | 33 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_have_cp_next_latch | tri_rlmreg_p__parameterized227_3538 | 4 | 4 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_illeg_lswx_latch | tri_rlmreg_p__parameterized227_3539 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_need_ready_ptr_latch | tri_rlmreg_p__parameterized267_3540 | 154 | 154 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_odq_resolved_latch | tri_rlmreg_p__parameterized227_3541 | 4 | 4 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_ready_sent_latch | tri_rlmreg_p__parameterized227_3542 | 7 | 7 | 0 | 0 | 12 | 0 | 0 | 0 | | stqe_strg_noop_latch | tri_rlmreg_p__parameterized227_3543 | 2 | 2 | 0 | 0 | 12 | 0 | 0 | 0 | | thrd_held_latch | tri_rlmreg_p__parameterized37_3544 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[0].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3545 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[10].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3546 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[11].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3547 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[1].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3548 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[2].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3549 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[3].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3550 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[4].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3551 | 14 | 14 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[5].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3552 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[6].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3553 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[7].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3554 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[8].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3555 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl15.stqe_lmqhit_latch_gen[9].stqe_lmqhit_latch | tri_rlmreg_p__parameterized12_3556 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[0].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3557 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[10].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3558 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[11].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3559 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[1].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3560 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[2].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3561 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[3].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3562 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[4].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3563 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[5].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3564 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[6].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3565 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[7].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3566 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[8].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3567 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl16.stqe_need_ext_ack_latch_gen[9].stqe_need_ext_ack_latch | tri_rlmreg_p__parameterized37_3568 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[0].stqe_itag_latch | tri_rlmreg_p__parameterized13_3569 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[10].stqe_itag_latch | tri_rlmreg_p__parameterized13_3570 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[11].stqe_itag_latch | tri_rlmreg_p__parameterized13_3571 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[1].stqe_itag_latch | tri_rlmreg_p__parameterized13_3572 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[2].stqe_itag_latch | tri_rlmreg_p__parameterized13_3573 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[3].stqe_itag_latch | tri_rlmreg_p__parameterized13_3574 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[4].stqe_itag_latch | tri_rlmreg_p__parameterized13_3575 | 10 | 10 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[5].stqe_itag_latch | tri_rlmreg_p__parameterized13_3576 | 13 | 13 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[6].stqe_itag_latch | tri_rlmreg_p__parameterized13_3577 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[7].stqe_itag_latch | tri_rlmreg_p__parameterized13_3578 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[8].stqe_itag_latch | tri_rlmreg_p__parameterized13_3579 | 12 | 12 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl17.stqe_itag_latch_gen[9].stqe_itag_latch | tri_rlmreg_p__parameterized13_3580 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[0].stqe_addr_latch | tri_rlmreg_p__parameterized219_3581 | 43 | 43 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[10].stqe_addr_latch | tri_rlmreg_p__parameterized219_3582 | 49 | 49 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[11].stqe_addr_latch | tri_rlmreg_p__parameterized219_3583 | 43 | 43 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[1].stqe_addr_latch | tri_rlmreg_p__parameterized219_3584 | 78 | 78 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[2].stqe_addr_latch | tri_rlmreg_p__parameterized219_3585 | 92 | 92 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[3].stqe_addr_latch | tri_rlmreg_p__parameterized219_3586 | 86 | 86 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[4].stqe_addr_latch | tri_rlmreg_p__parameterized219_3587 | 61 | 61 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[5].stqe_addr_latch | tri_rlmreg_p__parameterized219_3588 | 49 | 49 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[6].stqe_addr_latch | tri_rlmreg_p__parameterized219_3589 | 49 | 49 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[7].stqe_addr_latch | tri_rlmreg_p__parameterized219_3590 | 48 | 48 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[8].stqe_addr_latch | tri_rlmreg_p__parameterized219_3591 | 48 | 48 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl18.stqe_addr_latch_gen[9].stqe_addr_latch | tri_rlmreg_p__parameterized219_3592 | 48 | 48 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[0].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3593 | 8 | 8 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[10].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3594 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[11].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3595 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[1].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3596 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[2].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3597 | 3 | 3 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[3].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3598 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[4].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3599 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[5].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3600 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[6].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3601 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[7].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3602 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[8].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3603 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl19.stqe_rotcmp_latch_gen[9].stqe_rotcmp_latch | tri_rlmreg_p__parameterized3_3604 | 9 | 9 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[0].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3605 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[10].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3606 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[11].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3607 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[1].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3608 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[2].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3609 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[3].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3610 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[4].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3611 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[5].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3612 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[6].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3613 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[7].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3614 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[8].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3615 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl20.stqe_cline_chk_latch_gen[9].stqe_cline_chk_latch | tri_rlmreg_p__parameterized37_3616 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[0].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3617 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[10].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3618 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[11].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3619 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[1].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3620 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[2].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3621 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[3].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3622 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[4].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3623 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[5].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3624 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[6].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3625 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[7].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3626 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[8].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3627 | 2 | 2 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl21.stqe_ttype_latch_gen[9].stqe_ttype_latch | tri_rlmreg_p__parameterized0_3628 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[0].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3629 | 19 | 19 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[10].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3630 | 27 | 27 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[11].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3631 | 16 | 16 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[1].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3632 | 18 | 18 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[2].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3633 | 21 | 21 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[3].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3634 | 37 | 37 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[4].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3635 | 26 | 26 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[5].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3636 | 26 | 26 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[6].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3637 | 26 | 26 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[7].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3638 | 27 | 27 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[8].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3639 | 26 | 26 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl22.stqe_byte_en_latch_gen[9].stqe_byte_en_latch | tri_rlmreg_p__parameterized3_3640 | 28 | 28 | 0 | 0 | 16 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[0].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3641 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[10].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3642 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[11].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3643 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[1].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3644 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[2].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3645 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[3].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3646 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[4].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3647 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[5].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3648 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[6].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3649 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[7].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3650 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[8].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3651 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl23.stqe_wimge_latch_gen[9].stqe_wimge_latch | tri_rlmreg_p__parameterized4_3652 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[0].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3653 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[10].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3654 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[11].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3655 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[1].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3656 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[2].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3657 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[3].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3658 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[4].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3659 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[5].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3660 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[6].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3661 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[7].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3662 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[8].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3663 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.stqe_byte_swap_latch_gen[9].stqe_byte_swap_latch | tri_rlmreg_p__parameterized37_3664 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[0].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3665 | 139 | 139 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[10].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3666 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[11].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3667 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[1].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3668 | 121 | 121 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[2].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3669 | 20 | 20 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[3].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3670 | 21 | 21 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[4].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3671 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[5].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3672 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[6].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3673 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[7].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3674 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[8].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3675 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl25.stqe_opsize_latch_gen[9].stqe_opsize_latch | tri_rlmreg_p__parameterized5_3676 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[0].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3677 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[10].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3678 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[11].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3679 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[1].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3680 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[2].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3681 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[3].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3682 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[4].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3683 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[5].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3684 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[6].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3685 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[7].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3686 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[8].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3687 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.stqe_axu_val_latch_gen[9].stqe_axu_val_latch | tri_rlmreg_p__parameterized37_3688 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[0].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3689 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[10].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3690 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[11].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3691 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[1].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3692 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[2].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3693 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[3].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3694 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[4].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3695 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[5].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3696 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[6].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3697 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[7].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3698 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[8].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3699 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.stqe_epid_val_latch_gen[9].stqe_epid_val_latch | tri_rlmreg_p__parameterized37_3700 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[0].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3701 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[10].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3702 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[11].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3703 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[1].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3704 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[2].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3705 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[3].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3706 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[4].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3707 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[5].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3708 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[6].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3709 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[7].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3710 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[8].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3711 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl29.stqe_is_store_latch_gen[9].stqe_is_store_latch | tri_rlmreg_p__parameterized37_3712 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[0].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3713 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[10].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3714 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[11].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3715 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[1].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3716 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[2].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3717 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[3].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3718 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[4].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3719 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[5].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3720 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[6].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3721 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[7].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3722 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[8].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3723 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl30.stqe_is_sync_latch_gen[9].stqe_is_sync_latch | tri_rlmreg_p__parameterized37_3724 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[0].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3725 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[10].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3726 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[11].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3727 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[1].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3728 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[2].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3729 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[3].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3730 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[4].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3731 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[5].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3732 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[6].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3733 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[7].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3734 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[8].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3735 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl31.stqe_is_resv_latch_gen[9].stqe_is_resv_latch | tri_rlmreg_p__parameterized37_3736 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[0].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3737 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[10].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3738 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[11].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3739 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[1].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3740 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[2].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3741 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[3].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3742 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[4].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3743 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[5].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3744 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[6].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3745 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[7].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3746 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[8].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3747 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl33.stqe_is_icbi_latch_gen[9].stqe_is_icbi_latch | tri_rlmreg_p__parameterized37_3748 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[0].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3749 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[10].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3750 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[11].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3751 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[1].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3752 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[2].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3753 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[3].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3754 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[4].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3755 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[5].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3756 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[6].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3757 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[7].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3758 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[8].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3759 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl34.stqe_is_inval_op_latch_gen[9].stqe_is_inval_op_latch | tri_rlmreg_p__parameterized37_3760 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[0].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3761 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[10].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3762 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[11].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3763 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[1].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3764 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[2].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3765 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[3].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3766 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[4].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3767 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[5].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3768 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[6].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3769 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[7].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3770 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[8].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3771 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl35.stqe_dreq_val_latch_gen[9].stqe_dreq_val_latch | tri_rlmreg_p__parameterized37_3772 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[0].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3773 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[10].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3774 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[11].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3775 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[1].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3776 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[2].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3777 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[3].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3778 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[4].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3779 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[5].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3780 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[6].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3781 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[7].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3782 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[8].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3783 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl36.stqe_has_data_latch_gen[9].stqe_has_data_latch | tri_rlmreg_p__parameterized37_3784 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[0].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3785 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[10].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3786 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[11].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3787 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[1].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3788 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[2].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3789 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[3].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3790 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[4].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3791 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[5].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3792 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[6].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3793 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[7].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3794 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[8].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3795 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl37.stqe_send_l2_latch_gen[9].stqe_send_l2_latch | tri_rlmreg_p__parameterized37_3796 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[0].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3797 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[10].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3798 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[11].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3799 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[1].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3800 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[2].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3801 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[3].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3802 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[4].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3803 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[5].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3804 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[6].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3805 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[7].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3806 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[8].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3807 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl38.stqe_lock_clr_latch_gen[9].stqe_lock_clr_latch | tri_rlmreg_p__parameterized37_3808 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[0].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3809 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[10].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3810 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[11].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3811 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[1].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3812 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[2].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3813 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[3].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3814 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[4].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3815 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[5].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3816 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[6].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3817 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[7].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3818 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[8].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3819 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl39.stqe_watch_clr_latch_gen[9].stqe_watch_clr_latch | tri_rlmreg_p__parameterized37_3820 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[0].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3821 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[10].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3822 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[11].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3823 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[1].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3824 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[2].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3825 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[3].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3826 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[4].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3827 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[5].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3828 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[6].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3829 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[7].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3830 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[8].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3831 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl40.stqe_l_fld_latch_gen[9].stqe_l_fld_latch | tri_rlmreg_p__parameterized2_3832 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[0].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3833 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[10].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3834 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[11].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3835 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[1].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3836 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[2].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3837 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[3].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3838 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[4].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3839 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[5].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3840 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[6].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3841 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[7].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3842 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[8].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3843 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl41.stqe_thrd_id_latch_gen[9].stqe_thrd_id_latch | tri_rlmreg_p__parameterized37_3844 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[0].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3845 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[10].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3846 | 3 | 3 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[11].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3847 | 9 | 9 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[1].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3848 | 1 | 1 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[2].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3849 | 2 | 2 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[3].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3850 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[4].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3851 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[5].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3852 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[6].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3853 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[7].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3854 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[8].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3855 | 5 | 5 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl42.stqe_tgpr_latch_gen[9].stqe_tgpr_latch | tri_rlmreg_p__parameterized46_3856 | 2 | 2 | 0 | 0 | 9 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[0].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3857 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[10].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3858 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[11].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3859 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[1].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3860 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[2].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3861 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[3].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3862 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[4].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3863 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[5].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3864 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[6].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3865 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[7].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3866 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[8].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3867 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl43.stqe_dvc_en_latch_gen[9].stqe_dvc_en_latch | tri_rlmreg_p__parameterized2_3868 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[0].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3869 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[10].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3870 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[11].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3871 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[1].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3872 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[2].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3873 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[3].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3874 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[4].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3875 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[5].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3876 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[6].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3877 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[7].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3878 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[8].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3879 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl44.stqe_dacrw_latch_gen[9].stqe_dacrw_latch | tri_rlmreg_p__parameterized9_3880 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[0].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3881 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[10].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3882 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[11].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3883 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[1].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3884 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[2].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3885 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[3].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3886 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[4].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3887 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[5].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3888 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[6].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3889 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[7].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3890 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[8].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3891 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl45.stqe_dvcr_cmpr_latch_gen[9].stqe_dvcr_cmpr_latch | tri_rlmreg_p__parameterized2_3892 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[0].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3893 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[10].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3894 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[11].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3895 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[1].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3896 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[2].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[3].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3898 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[4].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[5].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3900 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[6].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3901 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[7].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3902 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[8].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3903 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl47.stqe_qHit_held_latch_gen[9].stqe_qHit_held_latch | tri_rlmreg_p__parameterized37_3904 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[0].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3905 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[10].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3906 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[11].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3907 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[1].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3908 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[2].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3909 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[3].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3910 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[4].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3911 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[5].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3912 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[6].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3913 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[7].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3914 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[8].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3915 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl48.stqe_held_early_clr_latch_gen[9].stqe_held_early_clr_latch | tri_rlmreg_p__parameterized37_3916 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[0].stqe_data1_latch | tri_rlmreg_p__parameterized33_3917 | 8 | 8 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[10].stqe_data1_latch | tri_rlmreg_p__parameterized33_3918 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[11].stqe_data1_latch | tri_rlmreg_p__parameterized33_3919 | 2 | 2 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[1].stqe_data1_latch | tri_rlmreg_p__parameterized33_3920 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[2].stqe_data1_latch | tri_rlmreg_p__parameterized33_3921 | 40 | 40 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[3].stqe_data1_latch | tri_rlmreg_p__parameterized33_3922 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[4].stqe_data1_latch | tri_rlmreg_p__parameterized33_3923 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[5].stqe_data1_latch | tri_rlmreg_p__parameterized33_3924 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[6].stqe_data1_latch | tri_rlmreg_p__parameterized33_3925 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[7].stqe_data1_latch | tri_rlmreg_p__parameterized33_3926 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[8].stqe_data1_latch | tri_rlmreg_p__parameterized33_3927 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl49.stqe_data1_latch_gen[9].stqe_data1_latch | tri_rlmreg_p__parameterized33_3928 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | xhdl50.cp_next_itag_latch_gen[0].cp_next_itag_latch | tri_rlmreg_p__parameterized13_3929 | 48 | 48 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl51.cp_i0_completed_itag_latch_gen[0].cp_i0_completed_itag_latch | tri_rlmreg_p__parameterized13_3930 | 25 | 25 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl52.cp_i1_completed_itag_latch_gen[0].cp_I1_completed_itag_latch | tri_rlmreg_p__parameterized13_3931 | 28 | 28 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl53.ext_ack_queue_itag_latch_gen[0].ext_ack_queue_itag_latch | tri_rlmreg_p__parameterized13_3932 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl54.ext_ack_queue_cr_wa_latch_gen[0].ext_ack_queue_cr_wa_latch | tri_rlmreg_p__parameterized4_3933 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl55.ext_ack_queue_dacrw_det_latch_gen[0].ext_ack_queue_dacrw_det_latch | tri_rlmreg_p__parameterized9_3934 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[0].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3935 | 14 | 14 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[10].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3936 | 47 | 47 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[11].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3937 | 26 | 26 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[1].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3938 | 17 | 17 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[2].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3939 | 32 | 32 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[3].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3940 | 20 | 20 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[4].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3941 | 21 | 21 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[5].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3942 | 28 | 28 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[6].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3943 | 24 | 24 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[7].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3944 | 18 | 18 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[8].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3945 | 41 | 41 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl56.stq_tag_ptr_latch_gen[9].stq_tag_ptr_latch | tri_rlmreg_p__parameterized227_3946 | 23 | 23 | 0 | 0 | 12 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[0].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3947 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[10].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3948 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[11].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3949 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[1].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3950 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[2].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3951 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[3].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3952 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[4].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3953 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[5].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3954 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[6].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3955 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[7].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3956 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[8].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3957 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl57.stqe_all_thrd_chk_latch_gen[9].stqe_all_thrd_chk_latch | tri_rlmreg_p__parameterized37_3958 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmu0 | mmq | 16042 | 16042 | 0 | 0 | 8156 | 21 | 0 | 0 | | mmq_inval | mmq_inval | 1037 | 1037 | 0 | 0 | 569 | 0 | 0 | 0 | | bus_snoop_hold_done_latch | tri_rlmreg_p__parameterized2_3280 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | bus_snoop_seq_latch | tri_rlmreg_p__parameterized2_3281 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | epcr_dgtmi_latch | tri_regk__parameterized22_3282 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13_3283 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_state_latch | tri_rlmreg_p__parameterized2_3284 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_t_latch | tri_rlmreg_p__parameterized5_3285 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_ttype_latch | tri_rlmreg_p__parameterized9_3286 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_valid_latch | tri_rlmreg_p__parameterized2_3287 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_3288 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_rs_is_latch | tri_rlmreg_p__parameterized46_3289 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_state_latch | tri_rlmreg_p__parameterized2_3290 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_t_latch | tri_rlmreg_p__parameterized5_3291 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_ttype_latch | tri_rlmreg_p__parameterized0_3292 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_valid_latch | tri_rlmreg_p__parameterized2_3293 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ea_latch | tri_rlmreg_p__parameterized33_3294 | 3 | 3 | 0 | 0 | 52 | 0 | 0 | 0 | | ex3_flush_req_latch | tri_rlmreg_p__parameterized2_3295 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_illeg_instr_latch | tri_rlmreg_p__parameterized2_3296 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_ivax_lpid_reject_latch | tri_rlmreg_p__parameterized2_3297 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs_is_latch | tri_rlmreg_p__parameterized46_3298 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_state_latch | tri_rlmreg_p__parameterized2_3299 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_t_latch | tri_rlmreg_p__parameterized5_3300 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_ttype_latch | tri_rlmreg_p__parameterized0_3301 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_valid_latch | tri_rlmreg_p__parameterized2_3302 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_illeg_instr_latch | tri_rlmreg_p__parameterized2_3303 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ivax_lpid_reject_latch | tri_rlmreg_p__parameterized2_3304 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_rs_is_latch | tri_rlmreg_p__parameterized46_3305 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_state_latch | tri_rlmreg_p__parameterized2_3306 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_t_latch | tri_rlmreg_p__parameterized5_3307 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_ttype_latch | tri_rlmreg_p__parameterized0_3308 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_valid_latch | tri_rlmreg_p__parameterized2_3309 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_illeg_instr_latch | tri_rlmreg_p__parameterized2_3310 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_rs_is_latch | tri_rlmreg_p__parameterized46_3311 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | ex5_state_latch | tri_rlmreg_p__parameterized2_3312 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_t_latch | tri_rlmreg_p__parameterized5_3313 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_ttype_latch | tri_rlmreg_p__parameterized0_3314 | 70 | 70 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_valid_latch | tri_rlmreg_p__parameterized2_3315 | 53 | 53 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_gs_latch | tri_rlmlatch_p_3316 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_illeg_instr_latch | tri_rlmreg_p__parameterized2_3317 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ind_latch | tri_rlmlatch_p_3318 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_isel_latch | tri_rlmreg_p__parameterized5_3319 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_lpid_latch | tri_rlmreg_p__parameterized12_3320 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_pid_latch | tri_rlmreg_p__parameterized41_3321 | 3 | 3 | 0 | 0 | 14 | 0 | 0 | 0 | | ex6_size_latch | tri_rlmreg_p__parameterized9_3322 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_ts_latch | tri_rlmlatch_p_3323 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ttype_latch | tri_rlmreg_p__parameterized0_3324 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_valid_latch | tri_rlmreg_p__parameterized2_3325 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex7_illeg_instr_latch | tri_rlmreg_p__parameterized2_3326 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | hold_ack_latch | tri_rlmreg_p__parameterized2_3327 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | hold_done_latch | tri_rlmreg_p__parameterized2_3328 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hold_req_latch | tri_rlmreg_p__parameterized2_3329 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | inv_seq_inprogress_latch | tri_rlmreg_p__parameterized0_3330 | 324 | 324 | 0 | 0 | 6 | 0 | 0 | 0 | | inv_seq_latch | tri_rlmreg_p__parameterized0_3331 | 161 | 161 | 0 | 0 | 5 | 0 | 0 | 0 | | iu_flush_req_latch | tri_rlmreg_p__parameterized2_3332 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | local_barrier_latch | tri_rlmreg_p__parameterized2_3333 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | local_snoop_reject_latch | tri_rlmreg_p__parameterized2_3334 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lpidr_latch | tri_regk__parameterized21 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lsu_addr_latch | tri_rlmreg_p__parameterized219_3335 | 26 | 26 | 0 | 0 | 26 | 0 | 0 | 0 | | lsu_gs_latch | tri_rlmlatch_p_3336 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lsu_ind_latch | tri_rlmlatch_p_3337 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | lsu_lbit_latch | tri_rlmlatch_p_3338 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lsu_lpid_latch | tri_rlmreg_p__parameterized12_3339 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | lsu_req_latch | tri_rlmreg_p__parameterized2_3340 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | lsu_tokens_latch | tri_rlmreg_p__parameterized215 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | | lsu_ttype_latch | tri_rlmreg_p__parameterized2_3341 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lsu_wimge_latch | tri_rlmreg_p__parameterized4_3342 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_pc_quiesce_latch | tri_rlmreg_p__parameterized12_3343 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | mm_xu_itag_latch | tri_rlmreg_p__parameterized13_3344 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | mm_xu_quiesce_latch | tri_rlmreg_p__parameterized2_3345 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmucr1_latch | tri_regk__parameterized21_3346 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ord_read_done_latch | tri_rlmreg_p__parameterized2_3347 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ord_write_done_latch | tri_rlmreg_p__parameterized2_3348 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | power_managed_latch | tri_rlmreg_p__parameterized9_3349 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | snoop_ack_latch | tri_rlmreg_p__parameterized5_3350 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | snoop_attr_clone_latch | tri_rlmreg_p__parameterized48_3351 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | snoop_attr_latch | tri_rlmreg_p__parameterized270_3352 | 0 | 0 | 0 | 0 | 35 | 0 | 0 | 0 | | snoop_attr_tlb_spec_latch | tri_rlmreg_p__parameterized2_3353 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | snoop_coming_latch | tri_rlmreg_p__parameterized4_3354 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | snoop_valid_latch | tri_rlmreg_p__parameterized5_3355 | 78 | 78 | 0 | 0 | 3 | 0 | 0 | 0 | | snoop_vpn_clone_latch | tri_rlmreg_p__parameterized34_3356 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | snoop_vpn_latch | tri_rlmreg_p__parameterized34_3357 | 1 | 1 | 0 | 0 | 52 | 0 | 0 | 0 | | tlbwe_back_inv_addr_latch | tri_rlmreg_p__parameterized34_3358 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | tlbwe_back_inv_attr_latch | tri_rlmreg_p__parameterized270_3359 | 5 | 5 | 0 | 0 | 30 | 0 | 0 | 0 | | tlbwe_back_inv_latch | tri_rlmreg_p__parameterized9_3360 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | xu_mm_ccr2_notlb_latch | tri_rlmreg_p__parameterized273 | 137 | 137 | 0 | 0 | 16 | 0 | 0 | 0 | | mmq_spr | mmq_spr | 2219 | 2219 | 0 | 0 | 1214 | 0 | 0 | 0 | | cat_emf_act_latch | tri_rlmreg_p__parameterized2_3120 | 26 | 26 | 0 | 0 | 2 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized2_3121 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_p1_latch | tri_rlmreg_p__parameterized2_3122 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_mm_except_taken_t0_latch | tri_rlmreg_p__parameterized0_3123 | 50 | 50 | 0 | 0 | 6 | 0 | 0 | 0 | | cswitch_latch | tri_rlmreg_p__parameterized200 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_mmucr1_0_een_latch | tri_rlmreg_p__parameterized4_3124 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | derat_mmucr1_we_pending_latch | tri_rlmreg_p__parameterized2_3125 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | fpga_bcfg_gen.mmucfg_47to48_latch | tri_rlmreg_p__parameterized274 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | fpga_bcfg_gen.tlb0cfg_45to47_latch | tri_rlmreg_p__parameterized192 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ierat_mmucr1_0_een_latch | tri_rlmreg_p__parameterized9_3126 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_mmucr1_we_pending_latch | tri_rlmreg_p__parameterized2_3127 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_mm_ierat_mmucr0_latch | tri_regk__parameterized23 | 3 | 3 | 0 | 0 | 18 | 0 | 0 | 0 | | iu_mm_ierat_mmucr0_we_latch | tri_regk__parameterized22_3128 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_mm_ierat_mmucr1_latch | tri_regk__parameterized24 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | iu_mm_ierat_mmucr1_we_latch | tri_regk__parameterized22_3129 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lper_0_alpn_latch | tri_rlmreg_p__parameterized53_3130 | 13 | 13 | 0 | 0 | 30 | 0 | 0 | 0 | | lper_0_lps_latch | tri_rlmreg_p__parameterized9_3131 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lper_1_alpn_latch | tri_rlmreg_p__parameterized53_3132 | 1 | 1 | 0 | 0 | 30 | 0 | 0 | 0 | | lper_1_lps_latch | tri_rlmreg_p__parameterized9_3133 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lpidr_latch | tri_rlmreg_p__parameterized12_3134 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | mas0_0_atsel_latch | tri_rlmlatch_p_3135 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas0_0_esel_latch | tri_rlmreg_p__parameterized5_3136 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | mas0_0_hes_latch | tri_rlmlatch_p_3137 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas0_0_wq_latch | tri_rlmreg_p__parameterized2_3138 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | mas0_1_atsel_latch | tri_rlmlatch_p_3139 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas0_1_esel_latch | tri_rlmreg_p__parameterized5_3140 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | mas0_1_hes_latch | tri_rlmlatch_p_3141 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas0_1_wq_latch | tri_rlmreg_p__parameterized2_3142 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | mas1_0_ind_latch | tri_rlmlatch_p_3143 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_0_iprot_latch | tri_rlmlatch_p_3144 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_0_tid_latch | tri_rlmreg_p__parameterized41_3145 | 6 | 6 | 0 | 0 | 14 | 0 | 0 | 0 | | mas1_0_ts_latch | tri_rlmlatch_p_3146 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_0_tsize_latch | tri_rlmreg_p__parameterized9_3147 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | mas1_0_v_latch | tri_rlmlatch_p_3148 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_1_ind_latch | tri_rlmlatch_p_3149 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_1_iprot_latch | tri_rlmlatch_p_3150 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_1_tid_latch | tri_rlmreg_p__parameterized41_3151 | 15 | 15 | 0 | 0 | 14 | 0 | 0 | 0 | | mas1_1_ts_latch | tri_rlmlatch_p_3152 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas1_1_tsize_latch | tri_rlmreg_p__parameterized9_3153 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | mas1_1_v_latch | tri_rlmlatch_p_3154 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas2_0_epn_latch | tri_rlmreg_p__parameterized34_3155 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | mas2_0_wimge_latch | tri_rlmreg_p__parameterized4_3156 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | mas2_1_epn_latch | tri_rlmreg_p__parameterized34_3157 | 45 | 45 | 0 | 0 | 52 | 0 | 0 | 0 | | mas2_1_wimge_latch | tri_rlmreg_p__parameterized4_3158 | 6 | 6 | 0 | 0 | 5 | 0 | 0 | 0 | | mas3_0_rpnl_latch | tri_rlmreg_p__parameterized255_3159 | 5 | 5 | 0 | 0 | 21 | 0 | 0 | 0 | | mas3_0_ubits_latch | tri_rlmreg_p__parameterized9_3160 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mas3_0_usxwr_latch | tri_rlmreg_p__parameterized0_3161 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | mas3_1_rpnl_latch | tri_rlmreg_p__parameterized255_3162 | 26 | 26 | 0 | 0 | 21 | 0 | 0 | 0 | | mas3_1_ubits_latch | tri_rlmreg_p__parameterized9_3163 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | mas3_1_usxwr_latch | tri_rlmreg_p__parameterized0_3164 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | | mas4_0_indd_latch | tri_rlmlatch_p_3165 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas4_0_tsized_latch | tri_rlmreg_p__parameterized193 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | mas4_0_wimged_latch | tri_rlmreg_p__parameterized4_3166 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | mas4_1_indd_latch | tri_rlmlatch_p_3167 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas4_1_tsized_latch | tri_rlmreg_p__parameterized193_3168 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | mas4_1_wimged_latch | tri_rlmreg_p__parameterized4_3169 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | mas5_0_sgs_latch | tri_rlmlatch_p_3170 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mas5_0_slpid_latch | tri_rlmreg_p__parameterized12_3171 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | mas5_1_sgs_latch | tri_rlmlatch_p_3172 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mas5_1_slpid_latch | tri_rlmreg_p__parameterized12_3173 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | mas6_0_isize_latch | tri_rlmreg_p__parameterized9_3174 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | mas6_0_sas_latch | tri_rlmlatch_p_3175 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas6_0_sind_latch | tri_rlmlatch_p_3176 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas6_0_spid_latch | tri_rlmreg_p__parameterized41_3177 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | mas6_1_isize_latch | tri_rlmreg_p__parameterized9_3178 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | mas6_1_sas_latch | tri_rlmlatch_p_3179 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mas6_1_sind_latch | tri_rlmlatch_p_3180 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mas6_1_spid_latch | tri_rlmreg_p__parameterized41_3181 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | mas7_0_rpnu_latch | tri_rlmreg_p__parameterized6_3182 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | | mas7_1_rpnu_latch | tri_rlmreg_p__parameterized6_3183 | 3 | 3 | 0 | 0 | 10 | 0 | 0 | 0 | | mas8_0_tgs_latch | tri_rlmlatch_p_3184 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas8_0_tlpid_latch | tri_rlmreg_p__parameterized12_3185 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | mas8_0_vf_latch | tri_rlmlatch_p_3186 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mas8_1_tgs_latch | tri_rlmlatch_p_3187 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mas8_1_tlpid_latch | tri_rlmreg_p__parameterized12_3188 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | mas8_1_vf_latch | tri_rlmlatch_p_3189 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | mesr1_latch | tri_rlmreg_p__parameterized7 | 11 | 11 | 0 | 0 | 24 | 0 | 0 | 0 | | mesr2_latch | tri_rlmreg_p__parameterized7_3190 | 3 | 3 | 0 | 0 | 24 | 0 | 0 | 0 | | mmucr0_0_latch | tri_rlmreg_p__parameterized8_3191 | 30 | 30 | 0 | 0 | 20 | 0 | 0 | 0 | | mmucr0_1_latch | tri_rlmreg_p__parameterized8_3192 | 5 | 5 | 0 | 0 | 20 | 0 | 0 | 0 | | mmucr1_latch | tri_rlmreg_p__parameterized275 | 72 | 72 | 0 | 0 | 32 | 0 | 0 | 0 | | mmucr2_latch | tri_rlmreg_p__parameterized276 | 68 | 68 | 0 | 0 | 32 | 0 | 0 | 0 | | mmucr3_0_latch | tri_rlmreg_p__parameterized277 | 15 | 15 | 0 | 0 | 14 | 0 | 0 | 0 | | mmucr3_1_latch | tri_rlmreg_p__parameterized277_3193 | 5 | 5 | 0 | 0 | 14 | 0 | 0 | 0 | | mmucsr0_tlb0fi_latch | tri_rlmlatch_p_3194 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | pid0_latch | tri_rlmreg_p__parameterized41_3195 | 2 | 2 | 0 | 0 | 14 | 0 | 0 | 0 | | pid1_latch | tri_rlmreg_p__parameterized41_3196 | 2 | 2 | 0 | 0 | 14 | 0 | 0 | 0 | | spr_addr_in_clone_latch | tri_rlmreg_p__parameterized6_3197 | 302 | 302 | 0 | 0 | 10 | 0 | 0 | 0 | | spr_addr_in_latch | tri_rlmreg_p__parameterized6_3198 | 25 | 25 | 0 | 0 | 10 | 0 | 0 | 0 | | spr_addr_int_latch | tri_rlmreg_p__parameterized6_3199 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | spr_addr_out_latch | tri_rlmreg_p__parameterized6_3200 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | spr_ctl_in_latch | tri_rlmreg_p__parameterized5_3201 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_ctl_int_latch | tri_rlmreg_p__parameterized5_3202 | 117 | 117 | 0 | 0 | 8 | 0 | 0 | 0 | | spr_ctl_out_latch | tri_rlmreg_p__parameterized5_3203 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_data_in_latch | tri_rlmreg_p__parameterized33_3204 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | spr_data_int_latch | tri_rlmreg_p__parameterized33_3205 | 571 | 571 | 0 | 0 | 64 | 0 | 0 | 0 | | spr_data_out_latch | tri_rlmreg_p__parameterized33_3206 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | spr_etid_in_latch | tri_rlmreg_p__parameterized2_3207 | 48 | 48 | 0 | 0 | 2 | 0 | 0 | 0 | | spr_etid_int_latch | tri_rlmreg_p__parameterized2_3208 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | spr_etid_out_latch | tri_rlmreg_p__parameterized2_3209 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | spr_mas_data_out_latch | tri_rlmreg_p__parameterized33_3210 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | spr_match_any_mas_latch | tri_rlmlatch_p_3211 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_any_mmu_latch | tri_rlmlatch_p_3212 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_eptcfg_latch | tri_rlmlatch_p_3213 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lper_0_latch | tri_rlmlatch_p_3214 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lper_1_latch | tri_rlmlatch_p_3215 | 38 | 38 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lperu_0_latch | tri_rlmlatch_p_3216 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lperu_1_latch | tri_rlmlatch_p_3217 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lpidr_latch | tri_rlmlatch_p_3218 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lratcfg_latch | tri_rlmlatch_p_3219 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_lratps_latch | tri_rlmlatch_p_3220 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas01_64b_0_latch | tri_rlmlatch_p_3221 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas01_64b_1_latch | tri_rlmlatch_p_3222 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas0_0_latch | tri_rlmlatch_p_3223 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas0_1_latch | tri_rlmlatch_p_3224 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas1_0_latch | tri_rlmlatch_p_3225 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas1_1_latch | tri_rlmlatch_p_3226 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas2_0_latch | tri_rlmlatch_p_3227 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas2_1_latch | tri_rlmlatch_p_3228 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas2u_0_latch | tri_rlmlatch_p_3229 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas2u_1_latch | tri_rlmlatch_p_3230 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas3_0_latch | tri_rlmlatch_p_3231 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas3_1_latch | tri_rlmlatch_p_3232 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas4_0_latch | tri_rlmlatch_p_3233 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas4_1_latch | tri_rlmlatch_p_3234 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas56_64b_0_latch | tri_rlmlatch_p_3235 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas56_64b_1_latch | tri_rlmlatch_p_3236 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas5_0_latch | tri_rlmlatch_p_3237 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas5_1_latch | tri_rlmlatch_p_3238 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas6_0_latch | tri_rlmlatch_p_3239 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas6_1_latch | tri_rlmlatch_p_3240 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas73_64b_0_latch | tri_rlmlatch_p_3241 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas73_64b_1_latch | tri_rlmlatch_p_3242 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas7_0_latch | tri_rlmlatch_p_3243 | 21 | 21 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas7_1_latch | tri_rlmlatch_p_3244 | 21 | 21 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas81_64b_0_latch | tri_rlmlatch_p_3245 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas81_64b_1_latch | tri_rlmlatch_p_3246 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas8_0_latch | tri_rlmlatch_p_3247 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mas8_1_latch | tri_rlmlatch_p_3248 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mesr1_latch | tri_rlmlatch_p_3249 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mesr2_latch | tri_rlmlatch_p_3250 | 29 | 29 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucfg_latch | tri_rlmlatch_p_3251 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr0_0_latch | tri_rlmlatch_p_3252 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr0_1_latch | tri_rlmlatch_p_3253 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr1_latch | tri_rlmlatch_p_3254 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr2_latch | tri_rlmlatch_p_3255 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr3_0_latch | tri_rlmlatch_p_3256 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucr3_1_latch | tri_rlmlatch_p_3257 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_mmucsr0_latch | tri_rlmlatch_p_3258 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_pid0_latch | tri_rlmlatch_p_3259 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_pid1_latch | tri_rlmlatch_p_3260 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_tlb0cfg_latch | tri_rlmlatch_p_3261 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_match_tlb0ps_latch | tri_rlmlatch_p_3262 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_mmu_act_latch | tri_rlmreg_p__parameterized5_3263 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | spr_val_act_latch | tri_rlmreg_p__parameterized9_3264 | 72 | 72 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_lper_0_lpn_latch | tri_rlmreg_p__parameterized53_3265 | 60 | 60 | 0 | 0 | 30 | 0 | 0 | 0 | | tlb_lper_0_lps_latch | tri_rlmreg_p__parameterized9_3266 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_lper_we_pending_latch | tri_rlmreg_p__parameterized2_3267 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_mas1_0_tid_error_latch | tri_rlmreg_p__parameterized41_3268 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tlb_mas1_0_ts_error_latch | tri_rlmlatch_p_3269 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_mas2_0_epn_error_latch | tri_rlmreg_p__parameterized34_3270 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | tlb_mas_dtlb_error_pending_latch | tri_rlmreg_p__parameterized2_3271 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_mas_itlb_error_pending_latch | tri_rlmreg_p__parameterized2_3272 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_mmucr1_0_een_latch | tri_rlmreg_p__parameterized46_3273 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | tlb_mmucr1_we_pending_latch | tri_rlmreg_p__parameterized2_3274 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | tstmode4k_0_latch | tri_rlmreg_p__parameterized9_3275 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | tstmode4k_1_latch | tri_rlmreg_p__parameterized9_3276 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xu_mm_derat_mmucr0_latch | tri_regk__parameterized23_3277 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | xu_mm_derat_mmucr0_we_latch | tri_regk__parameterized22_3278 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_mm_derat_mmucr1_latch | tri_regk__parameterized25 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xu_mm_derat_mmucr1_we_latch | tri_regk__parameterized22_3279 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_gen_instance.lru_array0 | tri_128x16_1r1w_1 | 18 | 18 | 0 | 0 | 20 | 1 | 0 | 0 | | tlb_gen_instance.tlb_array0 | tri_128x168_1w_0 | 180 | 180 | 0 | 0 | 0 | 5 | 0 | 0 | | tlb_gen_instance.tlb_array1 | tri_128x168_1w_0_2720 | 180 | 180 | 0 | 0 | 0 | 5 | 0 | 0 | | tlb_gen_instance.tlb_array2 | tri_128x168_1w_0_2721 | 180 | 180 | 0 | 0 | 0 | 5 | 0 | 0 | | tlb_gen_instance.tlb_array3 | tri_128x168_1w_0_2722 | 180 | 180 | 0 | 0 | 0 | 5 | 0 | 0 | | tlb_gen_logic.mmq_htw | mmq_htw | 2062 | 2062 | 0 | 0 | 1040 | 0 | 0 | 0 | | htw_inptr_latch | tri_rlmreg_p__parameterized2_3064 | 537 | 537 | 0 | 0 | 2 | 0 | 0 | 0 | | htw_lsu_addr_latch | tri_rlmreg_p__parameterized219_3065 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | htw_lsu_thdid_latch | tri_rlmreg_p__parameterized9_3066 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | htw_lsu_ttype_latch | tri_rlmreg_p__parameterized2_3067 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | htw_lsu_wimge_latch | tri_rlmreg_p__parameterized4_3068 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | htw_lsuptr_latch | tri_rlmreg_p__parameterized2_3069 | 86 | 86 | 0 | 0 | 2 | 0 | 0 | 0 | | htw_seq_latch | tri_rlmreg_p__parameterized2_3070 | 18 | 18 | 0 | 0 | 2 | 0 | 0 | 0 | | htw_tag3_latch | tri_rlmreg_p__parameterized269_3071 | 188 | 188 | 0 | 0 | 93 | 0 | 0 | 0 | | htw_tag4_clr_resv_latch | tri_rlmreg_p__parameterized9_3072 | 109 | 109 | 0 | 0 | 4 | 0 | 0 | 0 | | htw_tag5_clr_resv_latch | tri_rlmreg_p__parameterized9_3073 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | pte0_reld_data_tp3_latch | tri_rlmreg_p__parameterized33_3074 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | pte0_score_cl_offset_latch | tri_rlmreg_p__parameterized5_3075 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | pte0_score_dataval_latch | tri_rlmlatch_p_3076 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte0_score_ibit_latch | tri_rlmlatch_p_3077 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte0_score_pending_latch | tri_rlmlatch_p_3078 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte0_score_ptr_latch | tri_rlmreg_p__parameterized2_3079 | 10 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | | pte0_score_qwbeat_latch | tri_rlmreg_p__parameterized9_3080 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | pte0_seq_latch | tri_rlmreg_p__parameterized5_3081 | 71 | 71 | 0 | 0 | 2 | 0 | 0 | 0 | | pte1_reld_data_tp3_latch | tri_rlmreg_p__parameterized33_3082 | 2 | 2 | 0 | 0 | 52 | 0 | 0 | 0 | | pte1_score_cl_offset_latch | tri_rlmreg_p__parameterized5_3083 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | pte1_score_dataval_latch | tri_rlmlatch_p_3084 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte1_score_ibit_latch | tri_rlmlatch_p_3085 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte1_score_pending_latch | tri_rlmlatch_p_3086 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pte1_score_ptr_latch | tri_rlmreg_p__parameterized2_3087 | 253 | 253 | 0 | 0 | 2 | 0 | 0 | 0 | | pte1_score_qwbeat_latch | tri_rlmreg_p__parameterized9_3088 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | pte1_seq_latch | tri_rlmreg_p__parameterized5_3089 | 180 | 180 | 0 | 0 | 2 | 0 | 0 | 0 | | pte_load_ptr_latch | tri_rlmlatch_p_3090 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ptereload_ptr_latch | tri_rlmlatch_p_3091 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_core_tag_t_latch | tri_rlmreg_p__parameterized4_3092 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | reld_core_tag_tm1_latch | tri_rlmreg_p__parameterized4_3093 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | reld_core_tag_tp1_latch | tri_rlmreg_p__parameterized4_3094 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | reld_core_tag_tp2_latch | tri_rlmreg_p__parameterized4_3095 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | reld_crit_qw_t_latch | tri_rlmlatch_p_3096 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_crit_qw_tm1_latch | tri_rlmlatch_p_3097 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_crit_qw_tp1_latch | tri_rlmlatch_p_3098 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_crit_qw_tp2_latch | tri_rlmlatch_p_3099 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_data_tp1_latch | tri_rlmreg_p__parameterized1 | 104 | 104 | 0 | 0 | 104 | 0 | 0 | 0 | | reld_data_tp2_latch | tri_rlmreg_p__parameterized1_3100 | 104 | 104 | 0 | 0 | 104 | 0 | 0 | 0 | | reld_data_vld_t_latch | tri_rlmlatch_p_3101 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_data_vld_tm1_latch | tri_rlmlatch_p_3102 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_data_vld_tp1_latch | tri_rlmlatch_p_3103 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_data_vld_tp2_latch | tri_rlmlatch_p_3104 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | reld_qw_t_latch | tri_rlmreg_p__parameterized2_3105 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_qw_tm1_latch | tri_rlmreg_p__parameterized2_3106 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_qw_tp1_latch | tri_rlmreg_p__parameterized2_3107 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | reld_qw_tp2_latch | tri_rlmreg_p__parameterized2_3108 | 12 | 12 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_htw_req0_tag_latch | tri_rlmreg_p__parameterized269_3109 | 30 | 30 | 0 | 0 | 106 | 0 | 0 | 0 | | tlb_htw_req0_valid_latch | tri_rlmlatch_p_3110 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_htw_req0_way_latch | tri_rlmreg_p__parameterized44 | 12 | 12 | 0 | 0 | 24 | 0 | 0 | 0 | | tlb_htw_req1_tag_latch | tri_rlmreg_p__parameterized269_3111 | 96 | 96 | 0 | 0 | 106 | 0 | 0 | 0 | | tlb_htw_req1_valid_latch | tri_rlmlatch_p_3112 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_htw_req1_way_latch | tri_rlmreg_p__parameterized44_3113 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 | | tlb_htw_req2_tag_latch | tri_rlmreg_p__parameterized269_3114 | 91 | 91 | 0 | 0 | 106 | 0 | 0 | 0 | | tlb_htw_req2_valid_latch | tri_rlmlatch_p_3115 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_htw_req2_way_latch | tri_rlmreg_p__parameterized44_3116 | 7 | 7 | 0 | 0 | 24 | 0 | 0 | 0 | | tlb_htw_req3_tag_latch | tri_rlmreg_p__parameterized269_3117 | 89 | 89 | 0 | 0 | 106 | 0 | 0 | 0 | | tlb_htw_req3_valid_latch | tri_rlmlatch_p_3118 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_htw_req3_way_latch | tri_rlmreg_p__parameterized44_3119 | 8 | 8 | 0 | 0 | 24 | 0 | 0 | 0 | | tlb_gen_logic.mmq_tlb_cmp | mmq_tlb_cmp | 4889 | 4889 | 0 | 0 | 2484 | 0 | 0 | 0 | | (tlb_gen_logic.mmq_tlb_cmp) | mmq_tlb_cmp | 359 | 359 | 0 | 0 | 0 | 0 | 0 | 0 | | cr0_eq_latch | tri_rlmreg_p__parameterized2_3008 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | cr0_eq_valid_latch | tri_rlmreg_p__parameterized2_3009 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | epcr_dmiuh_latch | tri_regk__parameterized22 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | hv_priv_latch | tri_rlmreg_p__parameterized2_3010 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lrat_miss_latch | tri_rlmreg_p__parameterized2_3011 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lru_datain_latch | tri_rlmreg_p__parameterized3_3012 | 13 | 13 | 0 | 0 | 13 | 0 | 0 | 0 | | lru_par_err_latch | tri_rlmreg_p__parameterized2_3013 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | lru_tag3_dataout_latch | tri_rlmreg_p__parameterized3_3014 | 20 | 20 | 0 | 0 | 16 | 0 | 0 | 0 | | lru_tag4_dataout_latch | tri_rlmreg_p__parameterized3_3015 | 99 | 99 | 0 | 0 | 11 | 0 | 0 | 0 | | lru_update_clear_enab_latch | tri_rlmlatch_p_3016 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lru_wr_addr_latch | tri_rlmreg_p__parameterized13_3017 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lru_write_latch | tri_rlmreg_p__parameterized3_3018 | 0 | 0 | 0 | 0 | 16 | 0 | 0 | 0 | | mm_xu_ord_par_mhit_err_latch | tri_rlmreg_p__parameterized5_3019 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | mmucr1_clone_latch | tri_rlmreg_p__parameterized46_3020 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | mmucr1_latch | tri_rlmreg_p__parameterized46_3021 | 0 | 0 | 0 | 0 | 9 | 0 | 0 | 0 | | msr_gs_latch | tri_regk__parameterized22_3022 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msr_pr_latch | tri_regk__parameterized22_3023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | pt_fault_latch | tri_rlmreg_p__parameterized2_3024 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | tag4_parerr_latch | tri_rlmreg_p__parameterized4_3025 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_addr3_latch | tri_rlmreg_p__parameterized13_3026 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | tlb_addr4_latch | tri_rlmreg_p__parameterized13_3027 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | tlb_dataina_latch | tri_rlmreg_p__parameterized272 | 57 | 57 | 0 | 0 | 164 | 0 | 0 | 0 | | tlb_datainb_latch | tri_rlmreg_p__parameterized272_3028 | 57 | 57 | 0 | 0 | 164 | 0 | 0 | 0 | | tlb_erat_dup_latch | tri_rlmreg_p__parameterized257_3029 | 19 | 19 | 0 | 0 | 22 | 0 | 0 | 0 | | tlb_erat_rel_clone_latch | tri_rlmreg_p__parameterized49 | 1 | 1 | 0 | 0 | 128 | 0 | 0 | 0 | | tlb_erat_rel_latch | tri_rlmreg_p__parameterized49_3030 | 1 | 1 | 0 | 0 | 128 | 0 | 0 | 0 | | tlb_erat_val_latch | tri_rlmreg_p__parameterized6_3031 | 17 | 17 | 0 | 0 | 10 | 0 | 0 | 0 | | tlb_inelig_latch | tri_rlmreg_p__parameterized2_3032 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_miss_latch | tri_rlmreg_p__parameterized2_3033 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_multihit_err_latch | tri_rlmreg_p__parameterized2_3034 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_par_err_latch | tri_rlmreg_p__parameterized2_3035 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_tag3_clone1_latch | tri_rlmreg_p__parameterized269_3036 | 587 | 587 | 0 | 0 | 100 | 0 | 0 | 0 | | tlb_tag3_clone2_latch | tri_rlmreg_p__parameterized269_3037 | 585 | 585 | 0 | 0 | 100 | 0 | 0 | 0 | | tlb_tag3_cmpmask_clone_latch | tri_rlmreg_p__parameterized4_3038 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_tag3_cmpmask_latch | tri_rlmreg_p__parameterized4_3039 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_tag3_latch | tri_rlmreg_p__parameterized269_3040 | 126 | 126 | 0 | 0 | 121 | 0 | 0 | 0 | | tlb_tag4_latch | tri_rlmreg_p__parameterized269_3041 | 1209 | 1209 | 0 | 0 | 121 | 0 | 0 | 0 | | tlb_tag4_way_clone_latch | tri_rlmreg_p__parameterized272_3042 | 1175 | 1175 | 0 | 0 | 144 | 0 | 0 | 0 | | tlb_tag4_way_latch | tri_rlmreg_p__parameterized272_3043 | 53 | 53 | 0 | 0 | 144 | 0 | 0 | 0 | | tlb_tag4_way_rw_clone_latch | tri_rlmreg_p__parameterized272_3044 | 212 | 212 | 0 | 0 | 139 | 0 | 0 | 0 | | tlb_tag4_way_rw_latch | tri_rlmreg_p__parameterized272_3045 | 35 | 35 | 0 | 0 | 139 | 0 | 0 | 0 | | tlb_tag4_wayhit_latch | tri_rlmreg_p__parameterized4_3046 | 21 | 21 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_tag5_emq_latch | tri_rlmreg_p__parameterized9_3047 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | tlb_tag5_except_latch | tri_rlmreg_p__parameterized2_3048 | 20 | 20 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_tag5_parerr_zeroize_latch | tri_rlmlatch_p_3049 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_way0_cmpmask_latch | tri_rlmreg_p__parameterized4_3050 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way0_latch | tri_rlmreg_p__parameterized272_3051 | 43 | 43 | 0 | 0 | 168 | 0 | 0 | 0 | | tlb_way0_xbitmask_latch | tri_rlmreg_p__parameterized4_3052 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way1_cmpmask_latch | tri_rlmreg_p__parameterized4_3053 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way1_latch | tri_rlmreg_p__parameterized272_3054 | 43 | 43 | 0 | 0 | 168 | 0 | 0 | 0 | | tlb_way1_xbitmask_latch | tri_rlmreg_p__parameterized4_3055 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way2_cmpmask_latch | tri_rlmreg_p__parameterized4_3056 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way2_latch | tri_rlmreg_p__parameterized272_3057 | 43 | 43 | 0 | 0 | 168 | 0 | 0 | 0 | | tlb_way2_xbitmask_latch | tri_rlmreg_p__parameterized4_3058 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way3_cmpmask_latch | tri_rlmreg_p__parameterized4_3059 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlb_way3_latch | tri_rlmreg_p__parameterized272_3060 | 43 | 43 | 0 | 0 | 168 | 0 | 0 | 0 | | tlb_way3_xbitmask_latch | tri_rlmreg_p__parameterized4_3061 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | tlbwe_tag4_back_inv_attr_latch | tri_rlmreg_p__parameterized2_3062 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlbwe_tag4_back_inv_latch | tri_rlmreg_p__parameterized5_3063 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | tlb_gen_logic.mmq_tlb_ctl | mmq_tlb_ctl | 1908 | 1908 | 0 | 0 | 734 | 0 | 0 | 0 | | derat_taken_latch | tri_rlmlatch_p_2960 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13_2961 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_state_latch | tri_rlmreg_p__parameterized4_2962 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_ttype_latch | tri_rlmreg_p__parameterized4_2963 | 9 | 9 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_valid_latch | tri_rlmreg_p__parameterized2_2964 | 125 | 125 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_flush_latch | tri_rlmreg_p__parameterized2_2965 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_flush_req_latch | tri_rlmreg_p__parameterized2_2966 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_2967 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_state_latch | tri_rlmreg_p__parameterized4_2968 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_ttype_latch | tri_rlmreg_p__parameterized4_2969 | 74 | 74 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_valid_latch | tri_rlmreg_p__parameterized2_2970 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_flush_latch | tri_rlmreg_p__parameterized2_2971 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_state_latch | tri_rlmreg_p__parameterized4_2972 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_ttype_latch | tri_rlmreg_p__parameterized4_2973 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_valid_latch | tri_rlmreg_p__parameterized2_2974 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_flush_latch | tri_rlmreg_p__parameterized2_2975 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_state_latch | tri_rlmreg_p__parameterized4_2976 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_ttype_latch | tri_rlmreg_p__parameterized4_2977 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_valid_latch | tri_rlmreg_p__parameterized2_2978 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_flush_latch | tri_rlmreg_p__parameterized2_2979 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_state_latch | tri_rlmreg_p__parameterized4_2980 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex5_ttype_latch | tri_rlmreg_p__parameterized4_2981 | 8 | 8 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_valid_latch | tri_rlmreg_p__parameterized2_2982 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_flush_latch | tri_rlmreg_p__parameterized2_2983 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_illeg_instr_latch | tri_rlmreg_p__parameterized2_2984 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_state_latch | tri_rlmreg_p__parameterized4_2985 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_ttype_latch | tri_rlmreg_p__parameterized4_2986 | 1 | 1 | 0 | 0 | 5 | 0 | 0 | 0 | | ex6_valid_latch | tri_rlmreg_p__parameterized2_2987 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ptereload_req_pte_latch | tri_rlmreg_p__parameterized33_2988 | 16 | 16 | 0 | 0 | 52 | 0 | 0 | 0 | | snoop_attr_latch | tri_rlmreg_p__parameterized270 | 0 | 0 | 0 | 0 | 34 | 0 | 0 | 0 | | snoop_val_latch | tri_rlmreg_p__parameterized2_2989 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | snoop_vpn_latch | tri_rlmreg_p__parameterized34_2990 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | tlb_addr2_latch | tri_rlmreg_p__parameterized13_2991 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | tlb_addr_latch | tri_rlmreg_p__parameterized13_2992 | 23 | 23 | 0 | 0 | 7 | 0 | 0 | 0 | | tlb_clr_resv_latch | tri_rlmreg_p__parameterized2_2993 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_delayed_act_latch | tri_rlmreg_p__parameterized271 | 26 | 26 | 0 | 0 | 40 | 0 | 0 | 0 | | tlb_resv0_as_latch | tri_rlmlatch_p_2994 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_resv0_class_latch | tri_rlmreg_p__parameterized2_2995 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_resv0_epn_latch | tri_rlmreg_p__parameterized34_2996 | 24 | 24 | 0 | 0 | 52 | 0 | 0 | 0 | | tlb_resv0_gs_latch | tri_rlmlatch_p_2997 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_resv0_ind_latch | tri_rlmlatch_p_2998 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_resv0_lpid_latch | tri_rlmreg_p__parameterized12_2999 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | tlb_resv0_pid_latch | tri_rlmreg_p__parameterized41_3000 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tlb_resv0_tag1_match_latch | tri_regk__parameterized20 | 7 | 7 | 0 | 0 | 11 | 0 | 0 | 0 | | tlb_resv0_valid_latch | tri_rlmlatch_p_3001 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_resv_match_vec_latch | tri_rlmreg_p__parameterized2_3002 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_seq_latch | tri_rlmreg_p__parameterized0_3003 | 394 | 394 | 0 | 0 | 6 | 0 | 0 | 0 | | tlb_tag0_latch | tri_rlmreg_p__parameterized269 | 566 | 566 | 0 | 0 | 120 | 0 | 0 | 0 | | tlb_tag1_latch | tri_rlmreg_p__parameterized269_3004 | 121 | 121 | 0 | 0 | 121 | 0 | 0 | 0 | | tlb_tag2_latch | tri_rlmreg_p__parameterized269_3005 | 415 | 415 | 0 | 0 | 121 | 0 | 0 | 0 | | tlb_write_latch | tri_rlmreg_p__parameterized9_3006 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xucr4_mmu_mchk_latch | tri_rlmlatch_p_3007 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_gen_logic.mmq_tlb_lrat | mmq_tlb_lrat | 1554 | 1554 | 0 | 0 | 908 | 0 | 0 | 0 | | ex4_hv_state_latch | tri_rlmlatch_p_2847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ttype_latch | tri_rlmreg_p__parameterized4_2848 | 12 | 12 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_valid_latch | tri_rlmreg_p__parameterized2_2849 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_atsel_latch | tri_rlmlatch_p_2850 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_esel_latch | tri_rlmreg_p__parameterized5_2851 | 305 | 305 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_hes_latch | tri_rlmlatch_p_2852 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_hv_state_latch | tri_rlmlatch_p_2853 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ttype_latch | tri_rlmreg_p__parameterized4_2854 | 6 | 6 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_valid_latch | tri_rlmreg_p__parameterized2_2855 | 58 | 58 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_wq_latch | tri_rlmreg_p__parameterized2_2856 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_atsel_latch | tri_rlmlatch_p_2857 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_esel_latch | tri_rlmreg_p__parameterized5_2858 | 568 | 568 | 0 | 0 | 3 | 0 | 0 | 0 | | ex6_hes_latch | tri_rlmlatch_p_2859 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_hv_state_latch | tri_rlmlatch_p_2860 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ttype_latch | tri_rlmreg_p__parameterized4_2861 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex6_valid_latch | tri_rlmreg_p__parameterized2_2862 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_wq_latch | tri_rlmreg_p__parameterized2_2863 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | lrat_datain_act_latch | tri_rlmreg_p__parameterized2_2864 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | lrat_datain_lpid_latch | tri_rlmreg_p__parameterized12_2865 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_datain_lpn_latch | tri_rlmreg_p__parameterized257 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_datain_rpn_latch | tri_rlmreg_p__parameterized257_2866 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_datain_size_latch | tri_rlmreg_p__parameterized9_2867 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_datain_valid_latch | tri_rlmlatch_p_2868 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_datain_xbit_latch | tri_rlmlatch_p_2869 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry0_cmpmask_latch | tri_rlmreg_p__parameterized13_2870 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry0_lpid_latch | tri_rlmreg_p__parameterized12_2871 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry0_lpn_latch | tri_rlmreg_p__parameterized257_2872 | 25 | 25 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry0_rpn_latch | tri_rlmreg_p__parameterized257_2873 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry0_size_latch | tri_rlmreg_p__parameterized9_2874 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry0_valid_latch | tri_rlmlatch_p_2875 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry0_xbit_latch | tri_rlmlatch_p_2876 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry0_xbitmask_latch | tri_rlmreg_p__parameterized13_2877 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry1_cmpmask_latch | tri_rlmreg_p__parameterized13_2878 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry1_lpid_latch | tri_rlmreg_p__parameterized12_2879 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry1_lpn_latch | tri_rlmreg_p__parameterized257_2880 | 21 | 21 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry1_rpn_latch | tri_rlmreg_p__parameterized257_2881 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry1_size_latch | tri_rlmreg_p__parameterized9_2882 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry1_valid_latch | tri_rlmlatch_p_2883 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry1_xbit_latch | tri_rlmlatch_p_2884 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry1_xbitmask_latch | tri_rlmreg_p__parameterized13_2885 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry2_cmpmask_latch | tri_rlmreg_p__parameterized13_2886 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry2_lpid_latch | tri_rlmreg_p__parameterized12_2887 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry2_lpn_latch | tri_rlmreg_p__parameterized257_2888 | 17 | 17 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry2_rpn_latch | tri_rlmreg_p__parameterized257_2889 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry2_size_latch | tri_rlmreg_p__parameterized9_2890 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry2_valid_latch | tri_rlmlatch_p_2891 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry2_xbit_latch | tri_rlmlatch_p_2892 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry2_xbitmask_latch | tri_rlmreg_p__parameterized13_2893 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry3_cmpmask_latch | tri_rlmreg_p__parameterized13_2894 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry3_lpid_latch | tri_rlmreg_p__parameterized12_2895 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry3_lpn_latch | tri_rlmreg_p__parameterized257_2896 | 21 | 21 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry3_rpn_latch | tri_rlmreg_p__parameterized257_2897 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry3_size_latch | tri_rlmreg_p__parameterized9_2898 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry3_valid_latch | tri_rlmlatch_p_2899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry3_xbit_latch | tri_rlmlatch_p_2900 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry3_xbitmask_latch | tri_rlmreg_p__parameterized13_2901 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry4_cmpmask_latch | tri_rlmreg_p__parameterized13_2902 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry4_lpid_latch | tri_rlmreg_p__parameterized12_2903 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry4_lpn_latch | tri_rlmreg_p__parameterized257_2904 | 17 | 17 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry4_rpn_latch | tri_rlmreg_p__parameterized257_2905 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry4_size_latch | tri_rlmreg_p__parameterized9_2906 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry4_valid_latch | tri_rlmlatch_p_2907 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry4_xbit_latch | tri_rlmlatch_p_2908 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry4_xbitmask_latch | tri_rlmreg_p__parameterized13_2909 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry5_cmpmask_latch | tri_rlmreg_p__parameterized13_2910 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry5_lpid_latch | tri_rlmreg_p__parameterized12_2911 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry5_lpn_latch | tri_rlmreg_p__parameterized257_2912 | 17 | 17 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry5_rpn_latch | tri_rlmreg_p__parameterized257_2913 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry5_size_latch | tri_rlmreg_p__parameterized9_2914 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry5_valid_latch | tri_rlmlatch_p_2915 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry5_xbit_latch | tri_rlmlatch_p_2916 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry5_xbitmask_latch | tri_rlmreg_p__parameterized13_2917 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry6_cmpmask_latch | tri_rlmreg_p__parameterized13_2918 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry6_lpid_latch | tri_rlmreg_p__parameterized12_2919 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry6_lpn_latch | tri_rlmreg_p__parameterized257_2920 | 17 | 17 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry6_rpn_latch | tri_rlmreg_p__parameterized257_2921 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry6_size_latch | tri_rlmreg_p__parameterized9_2922 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry6_valid_latch | tri_rlmlatch_p_2923 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry6_xbit_latch | tri_rlmlatch_p_2924 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry6_xbitmask_latch | tri_rlmreg_p__parameterized13_2925 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry7_cmpmask_latch | tri_rlmreg_p__parameterized13_2926 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry7_lpid_latch | tri_rlmreg_p__parameterized12_2927 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_entry7_lpn_latch | tri_rlmreg_p__parameterized257_2928 | 25 | 25 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry7_rpn_latch | tri_rlmreg_p__parameterized257_2929 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_entry7_size_latch | tri_rlmreg_p__parameterized9_2930 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_entry7_valid_latch | tri_rlmlatch_p_2931 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry7_xbit_latch | tri_rlmlatch_p_2932 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_entry7_xbitmask_latch | tri_rlmreg_p__parameterized13_2933 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | lrat_entry_act_latch | tri_rlmreg_p__parameterized12_2934 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_mas1_tsize_latch | tri_rlmreg_p__parameterized9_2935 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_mas1_v_latch | tri_rlmlatch_p_2936 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_mas2_epn_latch | tri_rlmreg_p__parameterized53 | 0 | 0 | 0 | 0 | 22 | 0 | 0 | 0 | | lrat_mas3_rpnl_latch | tri_rlmreg_p__parameterized8_2937 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | lrat_mas7_rpnu_latch | tri_rlmreg_p__parameterized6_2938 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | lrat_mas8_tlpid_latch | tri_rlmreg_p__parameterized12_2939 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_mas_act_latch | tri_rlmreg_p__parameterized5_2940 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | lrat_mas_thdid_latch | tri_rlmreg_p__parameterized2_2941 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_mas_tlbre_latch | tri_rlmlatch_p_2942 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_mas_tlbsx_hit_latch | tri_rlmlatch_p_2943 | 20 | 20 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_mas_tlbsx_miss_latch | tri_rlmlatch_p_2944 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_mmucr3_x_latch | tri_rlmlatch_p_2945 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lrat_tag1_lpid_latch | tri_rlmreg_p__parameterized12_2946 | 40 | 40 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_tag1_lpn_latch | tri_rlmreg_p__parameterized53_2947 | 70 | 70 | 0 | 0 | 30 | 0 | 0 | 0 | | lrat_tag1_size_latch | tri_rlmreg_p__parameterized9_2948 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_tag2_entry_size_latch | tri_rlmreg_p__parameterized9_2949 | 60 | 60 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_tag2_lpn_latch | tri_rlmreg_p__parameterized53_2950 | 8 | 8 | 0 | 0 | 30 | 0 | 0 | 0 | | lrat_tag2_matchline_latch | tri_rlmreg_p__parameterized12_2951 | 92 | 92 | 0 | 0 | 8 | 0 | 0 | 0 | | lrat_tag2_size_latch | tri_rlmreg_p__parameterized9_2952 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_tag3_hit_entry_latch | tri_rlmreg_p__parameterized5_2953 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lrat_tag3_hit_status_latch | tri_rlmreg_p__parameterized9_2954 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_tag3_rpn_latch | tri_rlmreg_p__parameterized53_2955 | 30 | 30 | 0 | 0 | 30 | 0 | 0 | 0 | | lrat_tag4_hit_entry_latch | tri_rlmreg_p__parameterized5_2956 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | lrat_tag4_hit_status_latch | tri_rlmreg_p__parameterized9_2957 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | lrat_tag4_rpn_latch | tri_rlmreg_p__parameterized53_2958 | 9 | 9 | 0 | 0 | 30 | 0 | 0 | 0 | | tlb_addr_cap_latch | tri_rlmreg_p__parameterized2_2959 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | tlb_gen_logic.mmq_tlb_req | mmq_tlb_req | 1635 | 1635 | 0 | 0 | 1187 | 0 | 0 | 0 | | derat_ex4_emq_latch | tri_rlmreg_p__parameterized9_2723 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex4_epn_latch | tri_rlmreg_p__parameterized34 | 104 | 104 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_ex4_itag_latch | tri_rlmreg_p__parameterized13_2724 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_ex4_lpid_latch | tri_rlmreg_p__parameterized12_2725 | 24 | 24 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_ex4_nonspec_latch | tri_rlmlatch_p_2726 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex4_pid_latch | tri_rlmreg_p__parameterized41 | 28 | 28 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_ex4_state_latch | tri_rlmreg_p__parameterized9_2727 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex4_thdid_latch | tri_rlmreg_p__parameterized9_2728 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex4_ttype_latch | tri_rlmreg_p__parameterized2_2729 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_ex4_valid_latch | tri_rlmlatch_p_2730 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex5_emq_latch | tri_rlmreg_p__parameterized9_2731 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex5_epn_latch | tri_rlmreg_p__parameterized34_2732 | 72 | 72 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_ex5_itag_latch | tri_rlmreg_p__parameterized13_2733 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_ex5_lpid_latch | tri_rlmreg_p__parameterized12_2734 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_ex5_nonspec_latch | tri_rlmlatch_p_2735 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex5_pid_latch | tri_rlmreg_p__parameterized41_2736 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_ex5_state_latch | tri_rlmreg_p__parameterized9_2737 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex5_thdid_latch | tri_rlmreg_p__parameterized9_2738 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex5_ttype_latch | tri_rlmreg_p__parameterized2_2739 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_ex5_valid_latch | tri_rlmlatch_p_2740 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex6_emq_latch | tri_rlmreg_p__parameterized9_2741 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex6_epn_latch | tri_rlmreg_p__parameterized34_2742 | 1 | 1 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_ex6_itag_latch | tri_rlmreg_p__parameterized13_2743 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_ex6_lpid_latch | tri_rlmreg_p__parameterized12_2744 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_ex6_nonspec_latch | tri_rlmlatch_p_2745 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex6_pid_latch | tri_rlmreg_p__parameterized41_2746 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_ex6_state_latch | tri_rlmreg_p__parameterized9_2747 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_ex6_thdid_latch | tri_rlmreg_p__parameterized9_2748 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_ex6_ttype_latch | tri_rlmreg_p__parameterized2_2749 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_ex6_valid_latch | tri_rlmlatch_p_2750 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_inptr_latch | tri_rlmreg_p__parameterized2_2751 | 383 | 383 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_outptr_latch | tri_rlmreg_p__parameterized2_2752 | 142 | 142 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_req0_dup_latch | tri_rlmreg_p__parameterized2_2753 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req0_emq_latch | tri_rlmreg_p__parameterized9_2754 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req0_epn_latch | tri_rlmreg_p__parameterized34_2755 | 4 | 4 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_req0_itag_latch | tri_rlmreg_p__parameterized13_2756 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_req0_lpid_latch | tri_rlmreg_p__parameterized12_2757 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_req0_nonspec_latch | tri_rlmlatch_p_2758 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req0_pid_latch | tri_rlmreg_p__parameterized41_2759 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_req0_state_latch | tri_rlmreg_p__parameterized9_2760 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req0_thdid_latch | tri_rlmreg_p__parameterized9_2761 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req0_ttype_latch | tri_rlmreg_p__parameterized2_2762 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_req0_valid_latch | tri_rlmlatch_p_2763 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req1_dup_latch | tri_rlmreg_p__parameterized2_2764 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req1_emq_latch | tri_rlmreg_p__parameterized9_2765 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req1_epn_latch | tri_rlmreg_p__parameterized34_2766 | 2 | 2 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_req1_itag_latch | tri_rlmreg_p__parameterized13_2767 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_req1_lpid_latch | tri_rlmreg_p__parameterized12_2768 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_req1_nonspec_latch | tri_rlmlatch_p_2769 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req1_pid_latch | tri_rlmreg_p__parameterized41_2770 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_req1_state_latch | tri_rlmreg_p__parameterized9_2771 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req1_thdid_latch | tri_rlmreg_p__parameterized9_2772 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req1_ttype_latch | tri_rlmreg_p__parameterized2_2773 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_req1_valid_latch | tri_rlmlatch_p_2774 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req2_dup_latch | tri_rlmreg_p__parameterized2_2775 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req2_emq_latch | tri_rlmreg_p__parameterized9_2776 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req2_epn_latch | tri_rlmreg_p__parameterized34_2777 | 21 | 21 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_req2_itag_latch | tri_rlmreg_p__parameterized13_2778 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_req2_lpid_latch | tri_rlmreg_p__parameterized12_2779 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_req2_nonspec_latch | tri_rlmlatch_p_2780 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req2_pid_latch | tri_rlmreg_p__parameterized41_2781 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_req2_state_latch | tri_rlmreg_p__parameterized9_2782 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req2_thdid_latch | tri_rlmreg_p__parameterized9_2783 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req2_ttype_latch | tri_rlmreg_p__parameterized2_2784 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_req2_valid_latch | tri_rlmlatch_p_2785 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req3_dup_latch | tri_rlmreg_p__parameterized2_2786 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req3_emq_latch | tri_rlmreg_p__parameterized9_2787 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req3_epn_latch | tri_rlmreg_p__parameterized34_2788 | 23 | 23 | 0 | 0 | 52 | 0 | 0 | 0 | | derat_req3_itag_latch | tri_rlmreg_p__parameterized13_2789 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | derat_req3_lpid_latch | tri_rlmreg_p__parameterized12_2790 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | derat_req3_nonspec_latch | tri_rlmlatch_p_2791 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req3_pid_latch | tri_rlmreg_p__parameterized41_2792 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | derat_req3_state_latch | tri_rlmreg_p__parameterized9_2793 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | derat_req3_thdid_latch | tri_rlmreg_p__parameterized9_2794 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | derat_req3_ttype_latch | tri_rlmreg_p__parameterized2_2795 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | derat_req3_valid_latch | tri_rlmlatch_p_2796 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_inptr_latch | tri_rlmreg_p__parameterized2_2797 | 232 | 232 | 0 | 0 | 2 | 0 | 0 | 0 | | ierat_iu3_epn_latch | tri_rlmreg_p__parameterized34_2798 | 104 | 104 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_iu3_nonspec_latch | tri_rlmlatch_p_2799 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu3_pid_latch | tri_rlmreg_p__parameterized41_2800 | 28 | 28 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_iu3_state_latch | tri_rlmreg_p__parameterized9_2801 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_iu3_thdid_latch | tri_rlmreg_p__parameterized9_2802 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu3_valid_latch | tri_rlmlatch_p_2803 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu4_epn_latch | tri_rlmreg_p__parameterized34_2804 | 80 | 80 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_iu4_nonspec_latch | tri_rlmlatch_p_2805 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu4_pid_latch | tri_rlmreg_p__parameterized41_2806 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_iu4_state_latch | tri_rlmreg_p__parameterized9_2807 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_iu4_thdid_latch | tri_rlmreg_p__parameterized9_2808 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu4_valid_latch | tri_rlmlatch_p_2809 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu5_epn_latch | tri_rlmreg_p__parameterized34_2810 | 52 | 52 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_iu5_nonspec_latch | tri_rlmlatch_p_2811 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu5_pid_latch | tri_rlmreg_p__parameterized41_2812 | 14 | 14 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_iu5_state_latch | tri_rlmreg_p__parameterized9_2813 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_iu5_thdid_latch | tri_rlmreg_p__parameterized9_2814 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_iu5_valid_latch | tri_rlmlatch_p_2815 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_outptr_latch | tri_rlmreg_p__parameterized2_2816 | 92 | 92 | 0 | 0 | 2 | 0 | 0 | 0 | | ierat_req0_dup_latch | tri_rlmreg_p__parameterized2_2817 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req0_epn_latch | tri_rlmreg_p__parameterized34_2818 | 20 | 20 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_req0_nonspec_latch | tri_rlmlatch_p_2819 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req0_pid_latch | tri_rlmreg_p__parameterized41_2820 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_req0_state_latch | tri_rlmreg_p__parameterized9_2821 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_req0_thdid_latch | tri_rlmreg_p__parameterized9_2822 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req0_valid_latch | tri_rlmlatch_p_2823 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req1_dup_latch | tri_rlmreg_p__parameterized2_2824 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req1_epn_latch | tri_rlmreg_p__parameterized34_2825 | 19 | 19 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_req1_nonspec_latch | tri_rlmlatch_p_2826 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req1_pid_latch | tri_rlmreg_p__parameterized41_2827 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_req1_state_latch | tri_rlmreg_p__parameterized9_2828 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_req1_thdid_latch | tri_rlmreg_p__parameterized9_2829 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req1_valid_latch | tri_rlmlatch_p_2830 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req2_dup_latch | tri_rlmreg_p__parameterized2_2831 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req2_epn_latch | tri_rlmreg_p__parameterized34_2832 | 4 | 4 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_req2_nonspec_latch | tri_rlmlatch_p_2833 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req2_pid_latch | tri_rlmreg_p__parameterized41_2834 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_req2_state_latch | tri_rlmreg_p__parameterized9_2835 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_req2_thdid_latch | tri_rlmreg_p__parameterized9_2836 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req2_valid_latch | tri_rlmlatch_p_2837 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req3_dup_latch | tri_rlmreg_p__parameterized2_2838 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req3_epn_latch | tri_rlmreg_p__parameterized34_2839 | 26 | 26 | 0 | 0 | 52 | 0 | 0 | 0 | | ierat_req3_nonspec_latch | tri_rlmlatch_p_2840 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req3_pid_latch | tri_rlmreg_p__parameterized41_2841 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | ierat_req3_state_latch | tri_rlmreg_p__parameterized9_2842 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ierat_req3_thdid_latch | tri_rlmreg_p__parameterized9_2843 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ierat_req3_valid_latch | tri_rlmlatch_p_2844 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_seq_derat_req_latch | tri_rlmlatch_p_2845 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | tlb_seq_ierat_req_latch | tri_rlmlatch_p_2846 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_rp | c_perv_rp | 156 | 156 | 0 | 0 | 4 | 0 | 0 | 0 | | func2_t0_rp | tri_rlmreg_p__parameterized311 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu_clkstg_4to3 | tri_plat__parameterized14 | 62 | 62 | 0 | 0 | 1 | 0 | 0 | 0 | | perv_1to0_reg | tri_plat__parameterized15 | 92 | 92 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0 | rv | 36254 | 36254 | 0 | 0 | 14119 | 0 | 0 | 0 | | axu0_rvs | rv_axu0_rvs | 5353 | 5353 | 0 | 0 | 1647 | 0 | 0 | 0 | | (axu0_rvs) | rv_axu0_rvs | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | | axu0_rv_itag_abort_reg | tri_rlmlatch_p_2446 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | axu0_rv_itag_reg | tri_rlmreg_p__parameterized13_2447 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | axu0_rv_itag_vld_reg | tri_rlmreg_p__parameterized37_2448 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_2449 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_next_itag_reg | tri_rlmreg_p__parameterized13_2450 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_itag_reg | tri_rlmreg_p__parameterized13_2451 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_ord_reg | tri_rlmlatch_p_2452 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_vld_reg | tri_rlmreg_p__parameterized37_2453 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ord_vld_reg | tri_rlmreg_p__parameterized37_2454 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_vld_reg | tri_rlmreg_p__parameterized37_2455 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ord_flush_reg | tri_rlmreg_p__parameterized37_2456 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rvs | rv_station__parameterized2 | 5305 | 5305 | 0 | 0 | 1618 | 0 | 0 | 0 | | barf | rv_barf__parameterized0_2457 | 418 | 418 | 0 | 0 | 676 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized253_2707 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized253_2708 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized253_2709 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[12].q_dat_q_reg | tri_rlmreg_p__parameterized253_2710 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized253_2711 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized253_2712 | 52 | 52 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized253_2713 | 104 | 104 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized253_2714 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized253_2715 | 1 | 1 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized253_2716 | 156 | 156 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized253_2717 | 104 | 104 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized253_2718 | 1 | 1 | 0 | 0 | 52 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized253_2719 | 0 | 0 | 0 | 0 | 52 | 0 | 0 | 0 | | ex0_barf_addr_reg | tri_rlmreg_p__parameterized9_2458 | 294 | 294 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_credit_free_q_reg | tri_rlmreg_p__parameterized37_2459 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[0].q_cord_q_reg | tri_rlmlatch_p_2460 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[10].q_cord_q_reg | tri_rlmlatch_p_2461 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[11].q_cord_q_reg | tri_rlmlatch_p_2462 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[1].q_cord_q_reg | tri_rlmlatch_p_2463 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[2].q_cord_q_reg | tri_rlmlatch_p_2464 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[3].q_cord_q_reg | tri_rlmlatch_p_2465 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[4].q_cord_q_reg | tri_rlmlatch_p_2466 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[5].q_cord_q_reg | tri_rlmlatch_p_2467 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[6].q_cord_q_reg | tri_rlmlatch_p_2468 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[7].q_cord_q_reg | tri_rlmlatch_p_2469 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[8].q_cord_q_reg | tri_rlmlatch_p_2470 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[9].q_cord_q_reg | tri_rlmlatch_p_2471 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_credit_q_reg | tri_rlmreg_p__parameterized227_2472 | 87 | 87 | 0 | 0 | 12 | 0 | 0 | 0 | | q_ev_q_reg | tri_rlmreg_p__parameterized227_2473 | 1665 | 1665 | 0 | 0 | 13 | 0 | 0 | 0 | | q_flushed_q_reg | tri_rlmreg_p__parameterized227_2474 | 4 | 4 | 0 | 0 | 12 | 0 | 0 | 0 | | q_hold_all_q_reg | tri_rlmlatch_p_2475 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | q_hold_ord_q_reg | tri_rlmreg_p__parameterized37_2476 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[0].q_ord_q_reg | tri_rlmlatch_p_2477 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[10].q_ord_q_reg | tri_rlmlatch_p_2478 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[11].q_ord_q_reg | tri_rlmlatch_p_2479 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[1].q_ord_q_reg | tri_rlmlatch_p_2480 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[2].q_ord_q_reg | tri_rlmlatch_p_2481 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[3].q_ord_q_reg | tri_rlmlatch_p_2482 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[4].q_ord_q_reg | tri_rlmlatch_p_2483 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[5].q_ord_q_reg | tri_rlmlatch_p_2484 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[6].q_ord_q_reg | tri_rlmlatch_p_2485 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[7].q_ord_q_reg | tri_rlmlatch_p_2486 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[8].q_ord_q_reg | tri_rlmlatch_p_2487 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[9].q_ord_q_reg | tri_rlmlatch_p_2488 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_addr_reg | tri_rlmreg_p__parameterized9_2489 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_vld_reg | tri_rlmreg_p__parameterized37_2490 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_addr_reg | tri_rlmreg_p__parameterized9_2491 | 11 | 11 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_vld_reg | tri_rlmreg_p__parameterized37_2492 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_addr_reg | tri_rlmreg_p__parameterized9_2493 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_vld_reg | tri_rlmreg_p__parameterized37_2494 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_addr_reg | tri_rlmreg_p__parameterized9_2495 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_vld_reg | tri_rlmreg_p__parameterized37_2496 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_addr_reg | tri_rlmreg_p__parameterized9_2497 | 18 | 18 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_vld_reg | tri_rlmreg_p__parameterized37_2498 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[0].barf_ev_reg | tri_rlmreg_p__parameterized37_2499 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[10].barf_ev_reg | tri_rlmreg_p__parameterized37_2500 | 55 | 55 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[11].barf_ev_reg | tri_rlmreg_p__parameterized37_2501 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[12].barf_ev_reg | tri_rlmreg_p__parameterized37_2502 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[1].barf_ev_reg | tri_rlmreg_p__parameterized37_2503 | 61 | 61 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[2].barf_ev_reg | tri_rlmreg_p__parameterized37_2504 | 59 | 59 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[3].barf_ev_reg | tri_rlmreg_p__parameterized37_2505 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[4].barf_ev_reg | tri_rlmreg_p__parameterized37_2506 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[5].barf_ev_reg | tri_rlmreg_p__parameterized37_2507 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[6].barf_ev_reg | tri_rlmreg_p__parameterized37_2508 | 752 | 752 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[7].barf_ev_reg | tri_rlmreg_p__parameterized37_2509 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[8].barf_ev_reg | tri_rlmreg_p__parameterized37_2510 | 65 | 65 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[9].barf_ev_reg | tri_rlmreg_p__parameterized37_2511 | 63 | 63 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2512 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_2513 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2514 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_2515 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2516 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2517 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2518 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2519 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_2520 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2521 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized255 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2522 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_itag_q_reg | tri_rlmreg_p__parameterized13_2523 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2524 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_rdy_reg | tri_rlmlatch_p_2525 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_v_q_reg | tri_rlmlatch_p_2526 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2527 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_rdy_reg | tri_rlmlatch_p_2528 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_v_q_reg | tri_rlmlatch_p_2529 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2530 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_rdy_reg | tri_rlmlatch_p_2531 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_v_q_reg | tri_rlmlatch_p_2532 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_tid_q_reg | tri_rlmreg_p__parameterized37_2533 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2534 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized255_2535 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2536 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_issued_q_reg | tri_rlmlatch_p_2537 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_itag_q_reg | tri_rlmreg_p__parameterized13_2538 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2539 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_rdy_reg | tri_rlmlatch_p_2540 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_v_q_reg | tri_rlmlatch_p_2541 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2542 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_rdy_reg | tri_rlmlatch_p_2543 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_v_q_reg | tri_rlmlatch_p_2544 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2545 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_rdy_reg | tri_rlmlatch_p_2546 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_v_q_reg | tri_rlmlatch_p_2547 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_tid_q_reg | tri_rlmreg_p__parameterized37_2548 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2549 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized255_2550 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2551 | 29 | 29 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_issued_q_reg | tri_rlmlatch_p_2552 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_itag_q_reg | tri_rlmreg_p__parameterized13_2553 | 5 | 5 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2554 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_rdy_reg | tri_rlmlatch_p_2555 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_v_q_reg | tri_rlmlatch_p_2556 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2557 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_rdy_reg | tri_rlmlatch_p_2558 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_v_q_reg | tri_rlmlatch_p_2559 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2560 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_rdy_reg | tri_rlmlatch_p_2561 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_v_q_reg | tri_rlmlatch_p_2562 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_tid_q_reg | tri_rlmreg_p__parameterized37_2563 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2564 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized255_2565 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2566 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_itag_q_reg | tri_rlmreg_p__parameterized13_2567 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2568 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_rdy_reg | tri_rlmlatch_p_2569 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_v_q_reg | tri_rlmlatch_p_2570 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2571 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_rdy_reg | tri_rlmlatch_p_2572 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_v_q_reg | tri_rlmlatch_p_2573 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2574 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_rdy_reg | tri_rlmlatch_p_2575 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_v_q_reg | tri_rlmlatch_p_2576 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_tid_q_reg | tri_rlmreg_p__parameterized37_2577 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2578 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized255_2579 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2580 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_itag_q_reg | tri_rlmreg_p__parameterized13_2581 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2582 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_rdy_reg | tri_rlmlatch_p_2583 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_v_q_reg | tri_rlmlatch_p_2584 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2585 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_rdy_reg | tri_rlmlatch_p_2586 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_v_q_reg | tri_rlmlatch_p_2587 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2588 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_rdy_reg | tri_rlmlatch_p_2589 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_v_q_reg | tri_rlmlatch_p_2590 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_tid_q_reg | tri_rlmreg_p__parameterized37_2591 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2592 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized255_2593 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2594 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_itag_q_reg | tri_rlmreg_p__parameterized13_2595 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2596 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_rdy_reg | tri_rlmlatch_p_2597 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_v_q_reg | tri_rlmlatch_p_2598 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2599 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_rdy_reg | tri_rlmlatch_p_2600 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_v_q_reg | tri_rlmlatch_p_2601 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2602 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_rdy_reg | tri_rlmlatch_p_2603 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_v_q_reg | tri_rlmlatch_p_2604 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_tid_q_reg | tri_rlmreg_p__parameterized37_2605 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2606 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized255_2607 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2608 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_issued_q_reg | tri_rlmlatch_p_2609 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_itag_q_reg | tri_rlmreg_p__parameterized13_2610 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2611 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_rdy_reg | tri_rlmlatch_p_2612 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_v_q_reg | tri_rlmlatch_p_2613 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2614 | 39 | 39 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_rdy_reg | tri_rlmlatch_p_2615 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_v_q_reg | tri_rlmlatch_p_2616 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2617 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_rdy_reg | tri_rlmlatch_p_2618 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_v_q_reg | tri_rlmlatch_p_2619 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_tid_q_reg | tri_rlmreg_p__parameterized37_2620 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2621 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized255_2622 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2623 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_issued_q_reg | tri_rlmlatch_p_2624 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_itag_q_reg | tri_rlmreg_p__parameterized13_2625 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2626 | 39 | 39 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_rdy_reg | tri_rlmlatch_p_2627 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_v_q_reg | tri_rlmlatch_p_2628 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2629 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_rdy_reg | tri_rlmlatch_p_2630 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_v_q_reg | tri_rlmlatch_p_2631 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2632 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_rdy_reg | tri_rlmlatch_p_2633 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_v_q_reg | tri_rlmlatch_p_2634 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_tid_q_reg | tri_rlmreg_p__parameterized37_2635 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2636 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized255_2637 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2638 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_issued_q_reg | tri_rlmlatch_p_2639 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_itag_q_reg | tri_rlmreg_p__parameterized13_2640 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2641 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_rdy_reg | tri_rlmlatch_p_2642 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_v_q_reg | tri_rlmlatch_p_2643 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2644 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_rdy_reg | tri_rlmlatch_p_2645 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_v_q_reg | tri_rlmlatch_p_2646 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2647 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_rdy_reg | tri_rlmlatch_p_2648 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_v_q_reg | tri_rlmlatch_p_2649 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_tid_q_reg | tri_rlmreg_p__parameterized37_2650 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2651 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized255_2652 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2653 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_issued_q_reg | tri_rlmlatch_p_2654 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_itag_q_reg | tri_rlmreg_p__parameterized13_2655 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2656 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_rdy_reg | tri_rlmlatch_p_2657 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_v_q_reg | tri_rlmlatch_p_2658 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2659 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_rdy_reg | tri_rlmlatch_p_2660 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_v_q_reg | tri_rlmlatch_p_2661 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2662 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_rdy_reg | tri_rlmlatch_p_2663 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_v_q_reg | tri_rlmlatch_p_2664 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_tid_q_reg | tri_rlmreg_p__parameterized37_2665 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2666 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized255_2667 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2668 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_issued_q_reg | tri_rlmlatch_p_2669 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_itag_q_reg | tri_rlmreg_p__parameterized13_2670 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2671 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_rdy_reg | tri_rlmlatch_p_2672 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_v_q_reg | tri_rlmlatch_p_2673 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2674 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_rdy_reg | tri_rlmlatch_p_2675 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_v_q_reg | tri_rlmlatch_p_2676 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2677 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_rdy_reg | tri_rlmlatch_p_2678 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_v_q_reg | tri_rlmlatch_p_2679 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_tid_q_reg | tri_rlmreg_p__parameterized37_2680 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2681 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized255_2682 | 0 | 0 | 0 | 0 | 21 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2683 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_issued_q_reg | tri_rlmlatch_p_2684 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_itag_q_reg | tri_rlmreg_p__parameterized13_2685 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2686 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_rdy_reg | tri_rlmlatch_p_2687 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_v_q_reg | tri_rlmlatch_p_2688 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2689 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_rdy_reg | tri_rlmlatch_p_2690 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_v_q_reg | tri_rlmlatch_p_2691 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2692 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_rdy_reg | tri_rlmlatch_p_2693 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_v_q_reg | tri_rlmlatch_p_2694 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_tid_q_reg | tri_rlmreg_p__parameterized37_2695 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[10].q_rdy_q_reg | tri_rlmlatch_p_2696 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[11].q_rdy_q_reg | tri_rlmlatch_p_2697 | 140 | 140 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[4].q_rdy_q_reg | tri_rlmlatch_p_2698 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[5].q_rdy_q_reg | tri_rlmlatch_p_2699 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[6].q_rdy_q_reg | tri_rlmlatch_p_2700 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[7].q_rdy_q_reg | tri_rlmlatch_p_2701 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[8].q_rdy_q_reg | tri_rlmlatch_p_2702 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[9].q_rdy_q_reg | tri_rlmlatch_p_2703 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_abort_reg | tri_rlmreg_p__parameterized13_2704 | 6 | 6 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_ex3_abort_reg | tri_rlmlatch_p_2705 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_ex4_abort_reg | tri_rlmlatch_p_2706 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_rvs | rv_fx0_rvs | 9725 | 9725 | 0 | 0 | 3001 | 0 | 0 | 0 | | cp_next_itag_reg | tri_rlmreg_p__parameterized13_2144 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_is_brick_reg | tri_rlmlatch_p_2145 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_itag_reg | tri_rlmreg_p__parameterized13_2146 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_ord_reg | tri_rlmlatch_p_2147 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s1_v_reg | tri_rlmlatch_p_2148 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s2_t_reg | tri_rlmreg_p__parameterized5_2149 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_s2_v_reg | tri_rlmlatch_p_2150 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s3_t_reg | tri_rlmreg_p__parameterized5_2151 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_s3_v_reg | tri_rlmlatch_p_2152 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t1_t_reg | tri_rlmreg_p__parameterized5_2153 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_t1_v_reg | tri_rlmlatch_p_2154 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t2_t_reg | tri_rlmreg_p__parameterized5_2155 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_t2_v_reg | tri_rlmlatch_p_2156 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t3_t_reg | tri_rlmreg_p__parameterized5_2157 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_t3_v_reg | tri_rlmlatch_p_2158 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rvs | rv_station | 9691 | 9691 | 0 | 0 | 2964 | 0 | 0 | 0 | | barf | rv_barf | 2 | 2 | 0 | 0 | 1729 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized251 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized251_2434 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized251_2435 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[12].q_dat_q_reg | tri_rlmreg_p__parameterized251_2436 | 1 | 1 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized251_2437 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized251_2438 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized251_2439 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized251_2440 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized251_2441 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized251_2442 | 1 | 1 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized251_2443 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized251_2444 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized251_2445 | 0 | 0 | 0 | 0 | 133 | 0 | 0 | 0 | | ex0_barf_addr_reg | tri_rlmreg_p__parameterized9_2159 | 1023 | 1023 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_credit_free_q_reg | tri_rlmreg_p__parameterized37_2160 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | flush2_reg | tri_rlmreg_p__parameterized37_2161 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_itag1_rst_vld_reg | tri_rlmreg_p__parameterized37_2162 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.q_hold_brick_cnt_q_reg | tri_rlmreg_p__parameterized5_2163 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | q_brick1_g_gen.q_hold_brick_q_reg | tri_rlmlatch_p_2164 | 73 | 73 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[0].q_brick_q_reg | tri_rlmreg_p__parameterized5_2165 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[0].q_is_brick_q_reg | tri_rlmlatch_p_2166 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[10].q_brick_q_reg | tri_rlmreg_p__parameterized5_2167 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[10].q_is_brick_q_reg | tri_rlmlatch_p_2168 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[11].q_brick_q_reg | tri_rlmreg_p__parameterized5_2169 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[11].q_is_brick_q_reg | tri_rlmlatch_p_2170 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[1].q_brick_q_reg | tri_rlmreg_p__parameterized5_2171 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[1].q_is_brick_q_reg | tri_rlmlatch_p_2172 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[2].q_brick_q_reg | tri_rlmreg_p__parameterized5_2173 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[2].q_is_brick_q_reg | tri_rlmlatch_p_2174 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[3].q_brick_q_reg | tri_rlmreg_p__parameterized5_2175 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[3].q_is_brick_q_reg | tri_rlmlatch_p_2176 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[4].q_brick_q_reg | tri_rlmreg_p__parameterized5_2177 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[4].q_is_brick_q_reg | tri_rlmlatch_p_2178 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[5].q_brick_q_reg | tri_rlmreg_p__parameterized5_2179 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[5].q_is_brick_q_reg | tri_rlmlatch_p_2180 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[6].q_brick_q_reg | tri_rlmreg_p__parameterized5_2181 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[6].q_is_brick_q_reg | tri_rlmlatch_p_2182 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[7].q_brick_q_reg | tri_rlmreg_p__parameterized5_2183 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[7].q_is_brick_q_reg | tri_rlmlatch_p_2184 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[8].q_brick_q_reg | tri_rlmreg_p__parameterized5_2185 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[8].q_is_brick_q_reg | tri_rlmlatch_p_2186 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[9].q_brick_q_reg | tri_rlmreg_p__parameterized5_2187 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[9].q_is_brick_q_reg | tri_rlmlatch_p_2188 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[0].q_cord_q_reg | tri_rlmlatch_p_2189 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[10].q_cord_q_reg | tri_rlmlatch_p_2190 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[11].q_cord_q_reg | tri_rlmlatch_p_2191 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[1].q_cord_q_reg | tri_rlmlatch_p_2192 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[2].q_cord_q_reg | tri_rlmlatch_p_2193 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[3].q_cord_q_reg | tri_rlmlatch_p_2194 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[4].q_cord_q_reg | tri_rlmlatch_p_2195 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[5].q_cord_q_reg | tri_rlmlatch_p_2196 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[6].q_cord_q_reg | tri_rlmlatch_p_2197 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[7].q_cord_q_reg | tri_rlmlatch_p_2198 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[8].q_cord_q_reg | tri_rlmlatch_p_2199 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[9].q_cord_q_reg | tri_rlmlatch_p_2200 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_credit_q_reg | tri_rlmreg_p__parameterized227_2201 | 69 | 69 | 0 | 0 | 12 | 0 | 0 | 0 | | q_ev_q_reg | tri_rlmreg_p__parameterized227_2202 | 2985 | 2985 | 0 | 0 | 15 | 0 | 0 | 0 | | q_flushed_q_reg | tri_rlmreg_p__parameterized227_2203 | 5 | 5 | 0 | 0 | 12 | 0 | 0 | 0 | | q_hold_all_q_reg | tri_rlmlatch_p_2204 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_hold_ord_q_reg | tri_rlmreg_p__parameterized37_2205 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[0].q_ord_q_reg | tri_rlmlatch_p_2206 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[10].q_ord_q_reg | tri_rlmlatch_p_2207 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[11].q_ord_q_reg | tri_rlmlatch_p_2208 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[1].q_ord_q_reg | tri_rlmlatch_p_2209 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[2].q_ord_q_reg | tri_rlmlatch_p_2210 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[3].q_ord_q_reg | tri_rlmlatch_p_2211 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[4].q_ord_q_reg | tri_rlmlatch_p_2212 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[5].q_ord_q_reg | tri_rlmlatch_p_2213 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[6].q_ord_q_reg | tri_rlmlatch_p_2214 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[7].q_ord_q_reg | tri_rlmlatch_p_2215 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[8].q_ord_q_reg | tri_rlmlatch_p_2216 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[9].q_ord_q_reg | tri_rlmlatch_p_2217 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_addr_reg | tri_rlmreg_p__parameterized9_2218 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_vld_reg | tri_rlmreg_p__parameterized37_2219 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_addr_reg | tri_rlmreg_p__parameterized9_2220 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_vld_reg | tri_rlmreg_p__parameterized37_2221 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_addr_reg | tri_rlmreg_p__parameterized9_2222 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_vld_reg | tri_rlmreg_p__parameterized37_2223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_addr_reg | tri_rlmreg_p__parameterized9_2224 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_vld_reg | tri_rlmreg_p__parameterized37_2225 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_addr_reg | tri_rlmreg_p__parameterized9_2226 | 24 | 24 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_vld_reg | tri_rlmreg_p__parameterized37_2227 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[0].barf_ev_reg | tri_rlmreg_p__parameterized37_2228 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[10].barf_ev_reg | tri_rlmreg_p__parameterized37_2229 | 3500 | 3500 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[11].barf_ev_reg | tri_rlmreg_p__parameterized37_2230 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[12].barf_ev_reg | tri_rlmreg_p__parameterized37_2231 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[1].barf_ev_reg | tri_rlmreg_p__parameterized37_2232 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[2].barf_ev_reg | tri_rlmreg_p__parameterized37_2233 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[3].barf_ev_reg | tri_rlmreg_p__parameterized37_2234 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[4].barf_ev_reg | tri_rlmreg_p__parameterized37_2235 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[5].barf_ev_reg | tri_rlmreg_p__parameterized37_2236 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[6].barf_ev_reg | tri_rlmreg_p__parameterized37_2237 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[7].barf_ev_reg | tri_rlmreg_p__parameterized37_2238 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[8].barf_ev_reg | tri_rlmreg_p__parameterized37_2239 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[9].barf_ev_reg | tri_rlmreg_p__parameterized37_2240 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2241 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2242 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2243 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2244 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2245 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_2246 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2247 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized219_2248 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2249 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_itag_q_reg | tri_rlmreg_p__parameterized13_2250 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2251 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_rdy_reg | tri_rlmlatch_p_2252 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_v_q_reg | tri_rlmlatch_p_2253 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2254 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_rdy_reg | tri_rlmlatch_p_2255 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_v_q_reg | tri_rlmlatch_p_2256 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2257 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_rdy_reg | tri_rlmlatch_p_2258 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_v_q_reg | tri_rlmlatch_p_2259 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_tid_q_reg | tri_rlmreg_p__parameterized37_2260 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2261 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized219_2262 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2263 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_issued_q_reg | tri_rlmlatch_p_2264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_itag_q_reg | tri_rlmreg_p__parameterized13_2265 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2266 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_rdy_reg | tri_rlmlatch_p_2267 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_v_q_reg | tri_rlmlatch_p_2268 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2269 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_rdy_reg | tri_rlmlatch_p_2270 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_v_q_reg | tri_rlmlatch_p_2271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2272 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_rdy_reg | tri_rlmlatch_p_2273 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_v_q_reg | tri_rlmlatch_p_2274 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_tid_q_reg | tri_rlmreg_p__parameterized37_2275 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2276 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized219_2277 | 1 | 1 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2278 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_issued_q_reg | tri_rlmlatch_p_2279 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_itag_q_reg | tri_rlmreg_p__parameterized13_2280 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2281 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_rdy_reg | tri_rlmlatch_p_2282 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_v_q_reg | tri_rlmlatch_p_2283 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2284 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_rdy_reg | tri_rlmlatch_p_2285 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_v_q_reg | tri_rlmlatch_p_2286 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2287 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_rdy_reg | tri_rlmlatch_p_2288 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_v_q_reg | tri_rlmlatch_p_2289 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_tid_q_reg | tri_rlmreg_p__parameterized37_2290 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2291 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized219_2292 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2293 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_itag_q_reg | tri_rlmreg_p__parameterized13_2294 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2295 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_rdy_reg | tri_rlmlatch_p_2296 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_v_q_reg | tri_rlmlatch_p_2297 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2298 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_rdy_reg | tri_rlmlatch_p_2299 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_v_q_reg | tri_rlmlatch_p_2300 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2301 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_rdy_reg | tri_rlmlatch_p_2302 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_v_q_reg | tri_rlmlatch_p_2303 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_tid_q_reg | tri_rlmreg_p__parameterized37_2304 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2305 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized219_2306 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2307 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_itag_q_reg | tri_rlmreg_p__parameterized13_2308 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2309 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_rdy_reg | tri_rlmlatch_p_2310 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_v_q_reg | tri_rlmlatch_p_2311 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2312 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_rdy_reg | tri_rlmlatch_p_2313 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_v_q_reg | tri_rlmlatch_p_2314 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2315 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_rdy_reg | tri_rlmlatch_p_2316 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_v_q_reg | tri_rlmlatch_p_2317 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_tid_q_reg | tri_rlmreg_p__parameterized37_2318 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2319 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized219_2320 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2321 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_itag_q_reg | tri_rlmreg_p__parameterized13_2322 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2323 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_rdy_reg | tri_rlmlatch_p_2324 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_v_q_reg | tri_rlmlatch_p_2325 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2326 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_rdy_reg | tri_rlmlatch_p_2327 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_v_q_reg | tri_rlmlatch_p_2328 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2329 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_rdy_reg | tri_rlmlatch_p_2330 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_v_q_reg | tri_rlmlatch_p_2331 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_tid_q_reg | tri_rlmreg_p__parameterized37_2332 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2333 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized219_2334 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2335 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_issued_q_reg | tri_rlmlatch_p_2336 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_itag_q_reg | tri_rlmreg_p__parameterized13_2337 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2338 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_rdy_reg | tri_rlmlatch_p_2339 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_v_q_reg | tri_rlmlatch_p_2340 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2341 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_rdy_reg | tri_rlmlatch_p_2342 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_v_q_reg | tri_rlmlatch_p_2343 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2344 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_rdy_reg | tri_rlmlatch_p_2345 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_v_q_reg | tri_rlmlatch_p_2346 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_tid_q_reg | tri_rlmreg_p__parameterized37_2347 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2348 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized219_2349 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2350 | 16 | 16 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_issued_q_reg | tri_rlmlatch_p_2351 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_itag_q_reg | tri_rlmreg_p__parameterized13_2352 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2353 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_rdy_reg | tri_rlmlatch_p_2354 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_v_q_reg | tri_rlmlatch_p_2355 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2356 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_rdy_reg | tri_rlmlatch_p_2357 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_v_q_reg | tri_rlmlatch_p_2358 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2359 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_rdy_reg | tri_rlmlatch_p_2360 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_v_q_reg | tri_rlmlatch_p_2361 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_tid_q_reg | tri_rlmreg_p__parameterized37_2362 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2363 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized219_2364 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2365 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_issued_q_reg | tri_rlmlatch_p_2366 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_itag_q_reg | tri_rlmreg_p__parameterized13_2367 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2368 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_rdy_reg | tri_rlmlatch_p_2369 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_v_q_reg | tri_rlmlatch_p_2370 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2371 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_rdy_reg | tri_rlmlatch_p_2372 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_v_q_reg | tri_rlmlatch_p_2373 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2374 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_rdy_reg | tri_rlmlatch_p_2375 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_v_q_reg | tri_rlmlatch_p_2376 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_tid_q_reg | tri_rlmreg_p__parameterized37_2377 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2378 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized219_2379 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2380 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_issued_q_reg | tri_rlmlatch_p_2381 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_itag_q_reg | tri_rlmreg_p__parameterized13_2382 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2383 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_rdy_reg | tri_rlmlatch_p_2384 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_v_q_reg | tri_rlmlatch_p_2385 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2386 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_rdy_reg | tri_rlmlatch_p_2387 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_v_q_reg | tri_rlmlatch_p_2388 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2389 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_rdy_reg | tri_rlmlatch_p_2390 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_v_q_reg | tri_rlmlatch_p_2391 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_tid_q_reg | tri_rlmreg_p__parameterized37_2392 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2393 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized219_2394 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2395 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_issued_q_reg | tri_rlmlatch_p_2396 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_itag_q_reg | tri_rlmreg_p__parameterized13_2397 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2398 | 34 | 34 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_rdy_reg | tri_rlmlatch_p_2399 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_v_q_reg | tri_rlmlatch_p_2400 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2401 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_rdy_reg | tri_rlmlatch_p_2402 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_v_q_reg | tri_rlmlatch_p_2403 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2404 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_rdy_reg | tri_rlmlatch_p_2405 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_v_q_reg | tri_rlmlatch_p_2406 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_tid_q_reg | tri_rlmreg_p__parameterized37_2407 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2408 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized219_2409 | 0 | 0 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2410 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_issued_q_reg | tri_rlmlatch_p_2411 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_itag_q_reg | tri_rlmreg_p__parameterized13_2412 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2413 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_rdy_reg | tri_rlmlatch_p_2414 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_v_q_reg | tri_rlmlatch_p_2415 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2416 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_rdy_reg | tri_rlmlatch_p_2417 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_v_q_reg | tri_rlmlatch_p_2418 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2419 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_rdy_reg | tri_rlmlatch_p_2420 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_v_q_reg | tri_rlmlatch_p_2421 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_tid_q_reg | tri_rlmreg_p__parameterized37_2422 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[10].q_rdy_q_reg | tri_rlmlatch_p_2423 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[11].q_rdy_q_reg | tri_rlmlatch_p_2424 | 333 | 333 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[4].q_rdy_q_reg | tri_rlmlatch_p_2425 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[5].q_rdy_q_reg | tri_rlmlatch_p_2426 | 31 | 31 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[6].q_rdy_q_reg | tri_rlmlatch_p_2427 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[7].q_rdy_q_reg | tri_rlmlatch_p_2428 | 57 | 57 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[8].q_rdy_q_reg | tri_rlmlatch_p_2429 | 79 | 79 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[9].q_rdy_q_reg | tri_rlmlatch_p_2430 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_abort_reg | tri_rlmreg_p__parameterized13_2431 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_ex3_abort_reg | tri_rlmlatch_p_2432 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_ex4_abort_reg | tri_rlmlatch_p_2433 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_rvs | rv_fx1_rvs | 6312 | 6312 | 0 | 0 | 1717 | 0 | 0 | 0 | | (fx1_rvs) | rv_fx1_rvs | 24 | 24 | 0 | 0 | 0 | 0 | 0 | 0 | | ex0_itag_reg | tri_rlmreg_p__parameterized13_1887 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_s1_v_reg | tri_rlmlatch_p_1888 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s3_t_reg | tri_rlmreg_p__parameterized5_1889 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex0_t1_v_reg | tri_rlmlatch_p_1890 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t2_v_reg | tri_rlmlatch_p_1891 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t3_v_reg | tri_rlmlatch_p_1892 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rvs | rv_station__parameterized0 | 6284 | 6284 | 0 | 0 | 1703 | 0 | 0 | 0 | | barf | rv_barf__parameterized0 | 395 | 395 | 0 | 0 | 637 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized253 | 1 | 1 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized253_2132 | 99 | 99 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized253_2133 | 98 | 98 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[12].q_dat_q_reg | tri_rlmreg_p__parameterized253_2134 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized253_2135 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized253_2136 | 49 | 49 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized253_2137 | 99 | 99 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized253_2138 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized253_2139 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized253_2140 | 49 | 49 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized253_2141 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized253_2142 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized253_2143 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | ex0_barf_addr_reg | tri_rlmreg_p__parameterized9_1893 | 258 | 258 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_credit_free_q_reg | tri_rlmreg_p__parameterized37_1894 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | flush2_reg | tri_rlmreg_p__parameterized37_1895 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | flush_reg | tri_rlmreg_p__parameterized37_1896 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[10].q_cord_q_reg | tri_rlmlatch_p_1897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[11].q_cord_q_reg | tri_rlmlatch_p_1898 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[1].q_cord_q_reg | tri_rlmlatch_p_1899 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[2].q_cord_q_reg | tri_rlmlatch_p_1900 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[3].q_cord_q_reg | tri_rlmlatch_p_1901 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[4].q_cord_q_reg | tri_rlmlatch_p_1902 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[5].q_cord_q_reg | tri_rlmlatch_p_1903 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[6].q_cord_q_reg | tri_rlmlatch_p_1904 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[7].q_cord_q_reg | tri_rlmlatch_p_1905 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[8].q_cord_q_reg | tri_rlmlatch_p_1906 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[9].q_cord_q_reg | tri_rlmlatch_p_1907 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_credit_q_reg | tri_rlmreg_p__parameterized227_1908 | 86 | 86 | 0 | 0 | 12 | 0 | 0 | 0 | | q_ev_q_reg | tri_rlmreg_p__parameterized227_1909 | 2556 | 2556 | 0 | 0 | 15 | 0 | 0 | 0 | | q_flushed_q_reg | tri_rlmreg_p__parameterized227_1910 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_addr_reg | tri_rlmreg_p__parameterized9_1911 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_vld_reg | tri_rlmreg_p__parameterized37_1912 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_addr_reg | tri_rlmreg_p__parameterized9_1913 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_vld_reg | tri_rlmreg_p__parameterized37_1914 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_addr_reg | tri_rlmreg_p__parameterized9_1915 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_vld_reg | tri_rlmreg_p__parameterized37_1916 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_addr_reg | tri_rlmreg_p__parameterized9_1917 | 20 | 20 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_vld_reg | tri_rlmreg_p__parameterized37_1918 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_addr_reg | tri_rlmreg_p__parameterized9_1919 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_vld_reg | tri_rlmreg_p__parameterized37_1920 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[0].barf_ev_reg | tri_rlmreg_p__parameterized37_1921 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[10].barf_ev_reg | tri_rlmreg_p__parameterized37_1922 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[11].barf_ev_reg | tri_rlmreg_p__parameterized37_1923 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[12].barf_ev_reg | tri_rlmreg_p__parameterized37_1924 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[1].barf_ev_reg | tri_rlmreg_p__parameterized37_1925 | 58 | 58 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[2].barf_ev_reg | tri_rlmreg_p__parameterized37_1926 | 57 | 57 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[3].barf_ev_reg | tri_rlmreg_p__parameterized37_1927 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[4].barf_ev_reg | tri_rlmreg_p__parameterized37_1928 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[5].barf_ev_reg | tri_rlmreg_p__parameterized37_1929 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[6].barf_ev_reg | tri_rlmreg_p__parameterized37_1930 | 808 | 808 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[7].barf_ev_reg | tri_rlmreg_p__parameterized37_1931 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[8].barf_ev_reg | tri_rlmreg_p__parameterized37_1932 | 69 | 69 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[9].barf_ev_reg | tri_rlmreg_p__parameterized37_1933 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1934 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1935 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1936 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1937 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1938 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1939 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1940 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1941 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1942 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1943 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1944 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1945 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_1946 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized252 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1947 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_itag_q_reg | tri_rlmreg_p__parameterized13_1948 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1949 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_rdy_reg | tri_rlmlatch_p_1950 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_v_q_reg | tri_rlmlatch_p_1951 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1952 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_rdy_reg | tri_rlmlatch_p_1953 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_v_q_reg | tri_rlmlatch_p_1954 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1955 | 32 | 32 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_rdy_reg | tri_rlmlatch_p_1956 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s3_v_q_reg | tri_rlmlatch_p_1957 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_tid_q_reg | tri_rlmreg_p__parameterized37_1958 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_1959 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized252_1960 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1961 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_issued_q_reg | tri_rlmlatch_p_1962 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_itag_q_reg | tri_rlmreg_p__parameterized13_1963 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1964 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_rdy_reg | tri_rlmlatch_p_1965 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_v_q_reg | tri_rlmlatch_p_1966 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1967 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_rdy_reg | tri_rlmlatch_p_1968 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_v_q_reg | tri_rlmlatch_p_1969 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1970 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_rdy_reg | tri_rlmlatch_p_1971 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s3_v_q_reg | tri_rlmlatch_p_1972 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_tid_q_reg | tri_rlmreg_p__parameterized37_1973 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_1974 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized252_1975 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1976 | 35 | 35 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_issued_q_reg | tri_rlmlatch_p_1977 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_itag_q_reg | tri_rlmreg_p__parameterized13_1978 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1979 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_rdy_reg | tri_rlmlatch_p_1980 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_v_q_reg | tri_rlmlatch_p_1981 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1982 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_rdy_reg | tri_rlmlatch_p_1983 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_v_q_reg | tri_rlmlatch_p_1984 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1985 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_rdy_reg | tri_rlmlatch_p_1986 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s3_v_q_reg | tri_rlmlatch_p_1987 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_tid_q_reg | tri_rlmreg_p__parameterized37_1988 | 49 | 49 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_1989 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized252_1990 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1991 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_itag_q_reg | tri_rlmreg_p__parameterized13_1992 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1993 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_rdy_reg | tri_rlmlatch_p_1994 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_v_q_reg | tri_rlmlatch_p_1995 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1996 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_rdy_reg | tri_rlmlatch_p_1997 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_v_q_reg | tri_rlmlatch_p_1998 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1999 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_rdy_reg | tri_rlmlatch_p_2000 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s3_v_q_reg | tri_rlmlatch_p_2001 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_tid_q_reg | tri_rlmreg_p__parameterized37_2002 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2003 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized252_2004 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2005 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_itag_q_reg | tri_rlmreg_p__parameterized13_2006 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2007 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_rdy_reg | tri_rlmlatch_p_2008 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_v_q_reg | tri_rlmlatch_p_2009 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2010 | 35 | 35 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_rdy_reg | tri_rlmlatch_p_2011 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_v_q_reg | tri_rlmlatch_p_2012 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2013 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_rdy_reg | tri_rlmlatch_p_2014 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s3_v_q_reg | tri_rlmlatch_p_2015 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_tid_q_reg | tri_rlmreg_p__parameterized37_2016 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2017 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized252_2018 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2019 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_itag_q_reg | tri_rlmreg_p__parameterized13_2020 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2021 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_rdy_reg | tri_rlmlatch_p_2022 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_v_q_reg | tri_rlmlatch_p_2023 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2024 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_rdy_reg | tri_rlmlatch_p_2025 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_v_q_reg | tri_rlmlatch_p_2026 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2027 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_rdy_reg | tri_rlmlatch_p_2028 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s3_v_q_reg | tri_rlmlatch_p_2029 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_tid_q_reg | tri_rlmreg_p__parameterized37_2030 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2031 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized252_2032 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2033 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_issued_q_reg | tri_rlmlatch_p_2034 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_itag_q_reg | tri_rlmreg_p__parameterized13_2035 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2036 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_rdy_reg | tri_rlmlatch_p_2037 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_v_q_reg | tri_rlmlatch_p_2038 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2039 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_rdy_reg | tri_rlmlatch_p_2040 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_v_q_reg | tri_rlmlatch_p_2041 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2042 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_rdy_reg | tri_rlmlatch_p_2043 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s3_v_q_reg | tri_rlmlatch_p_2044 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_tid_q_reg | tri_rlmreg_p__parameterized37_2045 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2046 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized252_2047 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2048 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_issued_q_reg | tri_rlmlatch_p_2049 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_itag_q_reg | tri_rlmreg_p__parameterized13_2050 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2051 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_rdy_reg | tri_rlmlatch_p_2052 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_v_q_reg | tri_rlmlatch_p_2053 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2054 | 33 | 33 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_rdy_reg | tri_rlmlatch_p_2055 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_v_q_reg | tri_rlmlatch_p_2056 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2057 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_rdy_reg | tri_rlmlatch_p_2058 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s3_v_q_reg | tri_rlmlatch_p_2059 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_tid_q_reg | tri_rlmreg_p__parameterized37_2060 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2061 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized252_2062 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2063 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_issued_q_reg | tri_rlmlatch_p_2064 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_itag_q_reg | tri_rlmreg_p__parameterized13_2065 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2066 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_rdy_reg | tri_rlmlatch_p_2067 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_v_q_reg | tri_rlmlatch_p_2068 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2069 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_rdy_reg | tri_rlmlatch_p_2070 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_v_q_reg | tri_rlmlatch_p_2071 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2072 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_rdy_reg | tri_rlmlatch_p_2073 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s3_v_q_reg | tri_rlmlatch_p_2074 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_tid_q_reg | tri_rlmreg_p__parameterized37_2075 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2076 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized252_2077 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2078 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_issued_q_reg | tri_rlmlatch_p_2079 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_itag_q_reg | tri_rlmreg_p__parameterized13_2080 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2081 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_rdy_reg | tri_rlmlatch_p_2082 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_v_q_reg | tri_rlmlatch_p_2083 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2084 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_rdy_reg | tri_rlmlatch_p_2085 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_v_q_reg | tri_rlmlatch_p_2086 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2087 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_rdy_reg | tri_rlmlatch_p_2088 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s3_v_q_reg | tri_rlmlatch_p_2089 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_tid_q_reg | tri_rlmreg_p__parameterized37_2090 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2091 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized252_2092 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2093 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_issued_q_reg | tri_rlmlatch_p_2094 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_itag_q_reg | tri_rlmreg_p__parameterized13_2095 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2096 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_rdy_reg | tri_rlmlatch_p_2097 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_v_q_reg | tri_rlmlatch_p_2098 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2099 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_rdy_reg | tri_rlmlatch_p_2100 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_v_q_reg | tri_rlmlatch_p_2101 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2102 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_rdy_reg | tri_rlmlatch_p_2103 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s3_v_q_reg | tri_rlmlatch_p_2104 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_tid_q_reg | tri_rlmreg_p__parameterized37_2105 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_bard_addr_q_reg | tri_rlmreg_p__parameterized9_2106 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized252_2107 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_ilat_q_reg | tri_rlmreg_p__parameterized9_2108 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_issued_q_reg | tri_rlmlatch_p_2109 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_itag_q_reg | tri_rlmreg_p__parameterized13_2110 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_2111 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_rdy_reg | tri_rlmlatch_p_2112 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_v_q_reg | tri_rlmlatch_p_2113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_2114 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_rdy_reg | tri_rlmlatch_p_2115 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_v_q_reg | tri_rlmlatch_p_2116 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_itag_q_reg | tri_rlmreg_p__parameterized13_2117 | 31 | 31 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_rdy_reg | tri_rlmlatch_p_2118 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s3_v_q_reg | tri_rlmlatch_p_2119 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_tid_q_reg | tri_rlmreg_p__parameterized37_2120 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[10].q_rdy_q_reg | tri_rlmlatch_p_2121 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[11].q_rdy_q_reg | tri_rlmlatch_p_2122 | 378 | 378 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[4].q_rdy_q_reg | tri_rlmlatch_p_2123 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[5].q_rdy_q_reg | tri_rlmlatch_p_2124 | 29 | 29 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[6].q_rdy_q_reg | tri_rlmlatch_p_2125 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[7].q_rdy_q_reg | tri_rlmlatch_p_2126 | 44 | 44 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[8].q_rdy_q_reg | tri_rlmlatch_p_2127 | 65 | 65 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[9].q_rdy_q_reg | tri_rlmlatch_p_2128 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_abort_reg | tri_rlmreg_p__parameterized13_2129 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_ex3_abort_reg | tri_rlmlatch_p_2130 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_ex4_abort_reg | tri_rlmlatch_p_2131 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq0_rvs | rv_lq_rvs | 7967 | 7967 | 0 | 0 | 2174 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_1501 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_next_itag_reg | tri_rlmreg_p__parameterized13_1502 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_itag_reg | tri_rlmreg_p__parameterized13_1503 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_s1_itag_reg | tri_rlmreg_p__parameterized13_1504 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_s1_v_reg | tri_rlmlatch_p_1505 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s2_itag_reg | tri_rlmreg_p__parameterized13_1506 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex0_s2_v_reg | tri_rlmlatch_p_1507 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_t1_v_reg | tri_rlmlatch_p_1508 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_ext_itag0_abort_reg | tri_rlmlatch_p_1509 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_ext_itag0_reg | tri_rlmreg_p__parameterized13_1510 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | lq_rv_ext_itag0_vld_reg | tri_rlmreg_p__parameterized37_1511 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_ext_itag1_abort_reg | tri_rlmlatch_p_1512 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_ext_itag1_reg | tri_rlmreg_p__parameterized13_1513 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | lq_rv_ext_itag1_vld_reg | tri_rlmreg_p__parameterized37_1514 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_ext_itag2_reg | tri_rlmreg_p__parameterized13_1515 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | lq_rv_ext_itag2_vld_reg | tri_rlmreg_p__parameterized37_1516 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rvs | rv_station__parameterized1 | 7894 | 7894 | 0 | 0 | 2116 | 0 | 0 | 0 | | barf | rv_barf__parameterized1 | 3 | 3 | 0 | 0 | 833 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized254 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized254_1871 | 2 | 2 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized254_1872 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[12].q_dat_q_reg | tri_rlmreg_p__parameterized254_1873 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[13].q_dat_q_reg | tri_rlmreg_p__parameterized254_1874 | 1 | 1 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[14].q_dat_q_reg | tri_rlmreg_p__parameterized254_1875 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[15].q_dat_q_reg | tri_rlmreg_p__parameterized254_1876 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[16].q_dat_q_reg | tri_rlmreg_p__parameterized254_1877 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized254_1878 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized254_1879 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized254_1880 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized254_1881 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized254_1882 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized254_1883 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized254_1884 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized254_1885 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | xhdl2.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized254_1886 | 0 | 0 | 0 | 0 | 49 | 0 | 0 | 0 | | ex0_barf_addr_reg | tri_rlmreg_p__parameterized4_1517 | 580 | 580 | 0 | 0 | 5 | 0 | 0 | 0 | | flush2_reg | tri_rlmreg_p__parameterized37_1518 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | flush_reg | tri_rlmreg_p__parameterized37_1519 | 27 | 27 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_rv_itag1_rst_reg | tri_rlmreg_p__parameterized13_1520 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | lq_rv_itag1_rst_vld_reg | tri_rlmreg_p__parameterized37_1521 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.q_hold_brick_cnt_q_reg | tri_rlmreg_p__parameterized5_1522 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | q_brick1_g_gen.q_hold_brick_q_reg | tri_rlmlatch_p_1523 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[0].q_brick_q_reg | tri_rlmreg_p__parameterized5_1524 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[0].q_is_brick_q_reg | tri_rlmlatch_p_1525 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[10].q_brick_q_reg | tri_rlmreg_p__parameterized5_1526 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[10].q_is_brick_q_reg | tri_rlmlatch_p_1527 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[11].q_brick_q_reg | tri_rlmreg_p__parameterized5_1528 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[11].q_is_brick_q_reg | tri_rlmlatch_p_1529 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[12].q_brick_q_reg | tri_rlmreg_p__parameterized5_1530 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[12].q_is_brick_q_reg | tri_rlmlatch_p_1531 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[13].q_brick_q_reg | tri_rlmreg_p__parameterized5_1532 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[13].q_is_brick_q_reg | tri_rlmlatch_p_1533 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[14].q_brick_q_reg | tri_rlmreg_p__parameterized5_1534 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[14].q_is_brick_q_reg | tri_rlmlatch_p_1535 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[15].q_brick_q_reg | tri_rlmreg_p__parameterized5_1536 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[15].q_is_brick_q_reg | tri_rlmlatch_p_1537 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[1].q_brick_q_reg | tri_rlmreg_p__parameterized5_1538 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[1].q_is_brick_q_reg | tri_rlmlatch_p_1539 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[2].q_brick_q_reg | tri_rlmreg_p__parameterized5_1540 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[2].q_is_brick_q_reg | tri_rlmlatch_p_1541 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[3].q_brick_q_reg | tri_rlmreg_p__parameterized5_1542 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[3].q_is_brick_q_reg | tri_rlmlatch_p_1543 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[4].q_brick_q_reg | tri_rlmreg_p__parameterized5_1544 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[4].q_is_brick_q_reg | tri_rlmlatch_p_1545 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[5].q_brick_q_reg | tri_rlmreg_p__parameterized5_1546 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[5].q_is_brick_q_reg | tri_rlmlatch_p_1547 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[6].q_brick_q_reg | tri_rlmreg_p__parameterized5_1548 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[6].q_is_brick_q_reg | tri_rlmlatch_p_1549 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[7].q_brick_q_reg | tri_rlmreg_p__parameterized5_1550 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[7].q_is_brick_q_reg | tri_rlmlatch_p_1551 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[8].q_brick_q_reg | tri_rlmreg_p__parameterized5_1552 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[8].q_is_brick_q_reg | tri_rlmlatch_p_1553 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[9].q_brick_q_reg | tri_rlmreg_p__parameterized5_1554 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | q_brick1_g_gen.xhdl9b.q_bricklat_gen[9].q_is_brick_q_reg | tri_rlmlatch_p_1555 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[0].q_cord_q_reg | tri_rlmlatch_p_1556 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[10].q_cord_q_reg | tri_rlmlatch_p_1557 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[11].q_cord_q_reg | tri_rlmlatch_p_1558 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[12].q_cord_q_reg | tri_rlmlatch_p_1559 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[13].q_cord_q_reg | tri_rlmlatch_p_1560 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[14].q_cord_q_reg | tri_rlmlatch_p_1561 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[15].q_cord_q_reg | tri_rlmlatch_p_1562 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[1].q_cord_q_reg | tri_rlmlatch_p_1563 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[2].q_cord_q_reg | tri_rlmlatch_p_1564 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[3].q_cord_q_reg | tri_rlmlatch_p_1565 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[4].q_cord_q_reg | tri_rlmlatch_p_1566 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[5].q_cord_q_reg | tri_rlmlatch_p_1567 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[6].q_cord_q_reg | tri_rlmlatch_p_1568 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[7].q_cord_q_reg | tri_rlmlatch_p_1569 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[8].q_cord_q_reg | tri_rlmlatch_p_1570 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_cord1_g_gen.xhdl6.q_cord_nxt_gen[9].q_cord_q_reg | tri_rlmlatch_p_1571 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_credit_q_reg | tri_rlmreg_p__parameterized3 | 6 | 6 | 0 | 0 | 16 | 0 | 0 | 0 | | q_ev_q_reg | tri_rlmreg_p__parameterized3_1572 | 3323 | 3323 | 0 | 0 | 16 | 0 | 0 | 0 | | q_flushed_q_reg | tri_rlmreg_p__parameterized3_1573 | 149 | 149 | 0 | 0 | 16 | 0 | 0 | 0 | | q_hold_all_q_reg | tri_rlmlatch_p_1574 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | q_hold_ord_q_reg | tri_rlmreg_p__parameterized37_1575 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.lq_rv_clr_hold_reg | tri_rlmreg_p__parameterized37_1576 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.lq_rv_itag1_cord_reg | tri_rlmlatch_p_1577 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.lq_rv_itag1_hold_reg | tri_rlmlatch_p_1578 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.lq_rv_itag1_restart_reg | tri_rlmlatch_p_1579 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[0].q_spec_q_reg | tri_rlmlatch_p_1580 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[10].q_spec_q_reg | tri_rlmlatch_p_1581 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[11].q_spec_q_reg | tri_rlmlatch_p_1582 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[12].q_spec_q_reg | tri_rlmlatch_p_1583 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[13].q_spec_q_reg | tri_rlmlatch_p_1584 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[14].q_spec_q_reg | tri_rlmlatch_p_1585 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[15].q_spec_q_reg | tri_rlmlatch_p_1586 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[1].q_spec_q_reg | tri_rlmlatch_p_1587 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[2].q_spec_q_reg | tri_rlmlatch_p_1588 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[3].q_spec_q_reg | tri_rlmlatch_p_1589 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[4].q_spec_q_reg | tri_rlmlatch_p_1590 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[5].q_spec_q_reg | tri_rlmlatch_p_1591 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[6].q_spec_q_reg | tri_rlmlatch_p_1592 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[7].q_spec_q_reg | tri_rlmlatch_p_1593 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[8].q_spec_q_reg | tri_rlmlatch_p_1594 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl15.q_spec_nxt_gen[9].q_spec_q_reg | tri_rlmlatch_p_1595 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[0].q_e_miss_q_reg | tri_rlmlatch_p_1596 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[10].q_e_miss_q_reg | tri_rlmlatch_p_1597 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[11].q_e_miss_q_reg | tri_rlmlatch_p_1598 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[12].q_e_miss_q_reg | tri_rlmlatch_p_1599 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[13].q_e_miss_q_reg | tri_rlmlatch_p_1600 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[14].q_e_miss_q_reg | tri_rlmlatch_p_1601 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[15].q_e_miss_q_reg | tri_rlmlatch_p_1602 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[1].q_e_miss_q_reg | tri_rlmlatch_p_1603 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[2].q_e_miss_q_reg | tri_rlmlatch_p_1604 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[3].q_e_miss_q_reg | tri_rlmlatch_p_1605 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[4].q_e_miss_q_reg | tri_rlmlatch_p_1606 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[5].q_e_miss_q_reg | tri_rlmlatch_p_1607 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[6].q_e_miss_q_reg | tri_rlmlatch_p_1608 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[7].q_e_miss_q_reg | tri_rlmlatch_p_1609 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[8].q_e_miss_q_reg | tri_rlmlatch_p_1610 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_lq1_g_gen.xhdl27.q_e_miss_nxt_gen[9].q_e_miss_q_reg | tri_rlmlatch_p_1611 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[0].q_ord_q_reg | tri_rlmlatch_p_1612 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[10].q_ord_q_reg | tri_rlmlatch_p_1613 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[11].q_ord_q_reg | tri_rlmlatch_p_1614 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[12].q_ord_q_reg | tri_rlmlatch_p_1615 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[13].q_ord_q_reg | tri_rlmlatch_p_1616 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[14].q_ord_q_reg | tri_rlmlatch_p_1617 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[15].q_ord_q_reg | tri_rlmlatch_p_1618 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[1].q_ord_q_reg | tri_rlmlatch_p_1619 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[2].q_ord_q_reg | tri_rlmlatch_p_1620 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[3].q_ord_q_reg | tri_rlmlatch_p_1621 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[4].q_ord_q_reg | tri_rlmlatch_p_1622 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[5].q_ord_q_reg | tri_rlmlatch_p_1623 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[6].q_ord_q_reg | tri_rlmlatch_p_1624 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[7].q_ord_q_reg | tri_rlmlatch_p_1625 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[8].q_ord_q_reg | tri_rlmlatch_p_1626 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | q_ord1_g_gen.xhdl4.q_ord_nxt_gen[9].q_ord_q_reg | tri_rlmlatch_p_1627 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rvs_empty_q_reg | tri_rlmreg_p__parameterized37_1628 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_addr_reg | tri_rlmreg_p__parameterized9_1629 | 14 | 14 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[0].issued_vld_reg | tri_rlmreg_p__parameterized37_1630 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_addr_reg | tri_rlmreg_p__parameterized9_1631 | 14 | 14 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[1].issued_vld_reg | tri_rlmreg_p__parameterized37_1632 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_addr_reg | tri_rlmreg_p__parameterized9_1633 | 14 | 14 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[2].issued_vld_reg | tri_rlmreg_p__parameterized37_1634 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_addr_reg | tri_rlmreg_p__parameterized9_1635 | 37 | 37 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[3].issued_vld_reg | tri_rlmreg_p__parameterized37_1636 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_addr_reg | tri_rlmreg_p__parameterized9_1637 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | x5ia4.isa_gen[4].issued_vld_reg | tri_rlmreg_p__parameterized37_1638 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[0].barf_ev_reg | tri_rlmreg_p__parameterized37_1639 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[10].barf_ev_reg | tri_rlmreg_p__parameterized37_1640 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[11].barf_ev_reg | tri_rlmreg_p__parameterized37_1641 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[12].barf_ev_reg | tri_rlmreg_p__parameterized37_1642 | 23 | 23 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[13].barf_ev_reg | tri_rlmreg_p__parameterized37_1643 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[14].barf_ev_reg | tri_rlmreg_p__parameterized37_1644 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[15].barf_ev_reg | tri_rlmreg_p__parameterized37_1645 | 1700 | 1700 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[16].barf_ev_reg | tri_rlmreg_p__parameterized37_1646 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[1].barf_ev_reg | tri_rlmreg_p__parameterized37_1647 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[2].barf_ev_reg | tri_rlmreg_p__parameterized37_1648 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[3].barf_ev_reg | tri_rlmreg_p__parameterized37_1649 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[4].barf_ev_reg | tri_rlmreg_p__parameterized37_1650 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[5].barf_ev_reg | tri_rlmreg_p__parameterized37_1651 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[6].barf_ev_reg | tri_rlmreg_p__parameterized37_1652 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[7].barf_ev_reg | tri_rlmreg_p__parameterized37_1653 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[8].barf_ev_reg | tri_rlmreg_p__parameterized37_1654 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl555.q_bev_gen[9].barf_ev_reg | tri_rlmreg_p__parameterized37_1655 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1656 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[0].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1657 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1658 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[1].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1659 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1660 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[2].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1661 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1662 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[3].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1663 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1664 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[4].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1665 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_itag_reg | tri_rlmreg_p__parameterized13_1666 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5xx.xx_gen[5].xx_rv_rel_vld_reg | tri_rlmreg_p__parameterized37_1667 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1668 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_dat_q_reg | tri_rlmreg_p__parameterized48_1669 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1670 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_itag_q_reg | tri_rlmreg_p__parameterized13_1671 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1672 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_rdy_reg | tri_rlmlatch_p_1673 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s1_v_q_reg | tri_rlmlatch_p_1674 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1675 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_rdy_reg | tri_rlmlatch_p_1676 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_s2_v_q_reg | tri_rlmlatch_p_1677 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[0].q_tid_q_reg | tri_rlmreg_p__parameterized37_1678 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1679 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_dat_q_reg | tri_rlmreg_p__parameterized48_1680 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1681 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_issued_q_reg | tri_rlmlatch_p_1682 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_itag_q_reg | tri_rlmreg_p__parameterized13_1683 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1684 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_rdy_reg | tri_rlmlatch_p_1685 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s1_v_q_reg | tri_rlmlatch_p_1686 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1687 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_rdy_reg | tri_rlmlatch_p_1688 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_s2_v_q_reg | tri_rlmlatch_p_1689 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[10].q_tid_q_reg | tri_rlmreg_p__parameterized37_1690 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1691 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_dat_q_reg | tri_rlmreg_p__parameterized48_1692 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1693 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_issued_q_reg | tri_rlmlatch_p_1694 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_itag_q_reg | tri_rlmreg_p__parameterized13_1695 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1696 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_rdy_reg | tri_rlmlatch_p_1697 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s1_v_q_reg | tri_rlmlatch_p_1698 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1699 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_rdy_reg | tri_rlmlatch_p_1700 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_s2_v_q_reg | tri_rlmlatch_p_1701 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[11].q_tid_q_reg | tri_rlmreg_p__parameterized37_1702 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1703 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_dat_q_reg | tri_rlmreg_p__parameterized48_1704 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1705 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_issued_q_reg | tri_rlmlatch_p_1706 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_itag_q_reg | tri_rlmreg_p__parameterized13_1707 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1708 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s1_rdy_reg | tri_rlmlatch_p_1709 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s1_v_q_reg | tri_rlmlatch_p_1710 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1711 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s2_rdy_reg | tri_rlmlatch_p_1712 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_s2_v_q_reg | tri_rlmlatch_p_1713 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[12].q_tid_q_reg | tri_rlmreg_p__parameterized37_1714 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1715 | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_dat_q_reg | tri_rlmreg_p__parameterized48_1716 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1717 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_issued_q_reg | tri_rlmlatch_p_1718 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_itag_q_reg | tri_rlmreg_p__parameterized13_1719 | 63 | 63 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1720 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s1_rdy_reg | tri_rlmlatch_p_1721 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s1_v_q_reg | tri_rlmlatch_p_1722 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1723 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s2_rdy_reg | tri_rlmlatch_p_1724 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_s2_v_q_reg | tri_rlmlatch_p_1725 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[13].q_tid_q_reg | tri_rlmreg_p__parameterized37_1726 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1727 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_dat_q_reg | tri_rlmreg_p__parameterized48_1728 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1729 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_issued_q_reg | tri_rlmlatch_p_1730 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_itag_q_reg | tri_rlmreg_p__parameterized13_1731 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1732 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s1_rdy_reg | tri_rlmlatch_p_1733 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s1_v_q_reg | tri_rlmlatch_p_1734 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1735 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s2_rdy_reg | tri_rlmlatch_p_1736 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_s2_v_q_reg | tri_rlmlatch_p_1737 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[14].q_tid_q_reg | tri_rlmreg_p__parameterized37_1738 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1739 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_dat_q_reg | tri_rlmreg_p__parameterized48_1740 | 1 | 1 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1741 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_issued_q_reg | tri_rlmlatch_p_1742 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_itag_q_reg | tri_rlmreg_p__parameterized13_1743 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1744 | 38 | 38 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s1_rdy_reg | tri_rlmlatch_p_1745 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s1_v_q_reg | tri_rlmlatch_p_1746 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1747 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s2_rdy_reg | tri_rlmlatch_p_1748 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_s2_v_q_reg | tri_rlmlatch_p_1749 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[15].q_tid_q_reg | tri_rlmreg_p__parameterized37_1750 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1751 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_dat_q_reg | tri_rlmreg_p__parameterized48_1752 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1753 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_itag_q_reg | tri_rlmreg_p__parameterized13_1754 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1755 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_rdy_reg | tri_rlmlatch_p_1756 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s1_v_q_reg | tri_rlmlatch_p_1757 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1758 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_rdy_reg | tri_rlmlatch_p_1759 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_s2_v_q_reg | tri_rlmlatch_p_1760 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[1].q_tid_q_reg | tri_rlmreg_p__parameterized37_1761 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1762 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_dat_q_reg | tri_rlmreg_p__parameterized48_1763 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1764 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_itag_q_reg | tri_rlmreg_p__parameterized13_1765 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1766 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_rdy_reg | tri_rlmlatch_p_1767 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s1_v_q_reg | tri_rlmlatch_p_1768 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1769 | 37 | 37 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_rdy_reg | tri_rlmlatch_p_1770 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_s2_v_q_reg | tri_rlmlatch_p_1771 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[2].q_tid_q_reg | tri_rlmreg_p__parameterized37_1772 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1773 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_dat_q_reg | tri_rlmreg_p__parameterized48_1774 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1775 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_itag_q_reg | tri_rlmreg_p__parameterized13_1776 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1777 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_rdy_reg | tri_rlmlatch_p_1778 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s1_v_q_reg | tri_rlmlatch_p_1779 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1780 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_rdy_reg | tri_rlmlatch_p_1781 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_s2_v_q_reg | tri_rlmlatch_p_1782 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[3].q_tid_q_reg | tri_rlmreg_p__parameterized37_1783 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1784 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_dat_q_reg | tri_rlmreg_p__parameterized48_1785 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1786 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_issued_q_reg | tri_rlmlatch_p_1787 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_itag_q_reg | tri_rlmreg_p__parameterized13_1788 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1789 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_rdy_reg | tri_rlmlatch_p_1790 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s1_v_q_reg | tri_rlmlatch_p_1791 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1792 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_rdy_reg | tri_rlmlatch_p_1793 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_s2_v_q_reg | tri_rlmlatch_p_1794 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[4].q_tid_q_reg | tri_rlmreg_p__parameterized37_1795 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1796 | 18 | 18 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_dat_q_reg | tri_rlmreg_p__parameterized48_1797 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1798 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_issued_q_reg | tri_rlmlatch_p_1799 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_itag_q_reg | tri_rlmreg_p__parameterized13_1800 | 46 | 46 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1801 | 65 | 65 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_rdy_reg | tri_rlmlatch_p_1802 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s1_v_q_reg | tri_rlmlatch_p_1803 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1804 | 64 | 64 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_rdy_reg | tri_rlmlatch_p_1805 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_s2_v_q_reg | tri_rlmlatch_p_1806 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[5].q_tid_q_reg | tri_rlmreg_p__parameterized37_1807 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1808 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_dat_q_reg | tri_rlmreg_p__parameterized48_1809 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1810 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_issued_q_reg | tri_rlmlatch_p_1811 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_itag_q_reg | tri_rlmreg_p__parameterized13_1812 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1813 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_rdy_reg | tri_rlmlatch_p_1814 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s1_v_q_reg | tri_rlmlatch_p_1815 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1816 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_rdy_reg | tri_rlmlatch_p_1817 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_s2_v_q_reg | tri_rlmlatch_p_1818 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[6].q_tid_q_reg | tri_rlmreg_p__parameterized37_1819 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1820 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_dat_q_reg | tri_rlmreg_p__parameterized48_1821 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1822 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_issued_q_reg | tri_rlmlatch_p_1823 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_itag_q_reg | tri_rlmreg_p__parameterized13_1824 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1825 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_rdy_reg | tri_rlmlatch_p_1826 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s1_v_q_reg | tri_rlmlatch_p_1827 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1828 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_rdy_reg | tri_rlmlatch_p_1829 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_s2_v_q_reg | tri_rlmlatch_p_1830 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[7].q_tid_q_reg | tri_rlmreg_p__parameterized37_1831 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1832 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_dat_q_reg | tri_rlmreg_p__parameterized48_1833 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1834 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_issued_q_reg | tri_rlmlatch_p_1835 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_itag_q_reg | tri_rlmreg_p__parameterized13_1836 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1837 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_rdy_reg | tri_rlmlatch_p_1838 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s1_v_q_reg | tri_rlmlatch_p_1839 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1840 | 36 | 36 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_rdy_reg | tri_rlmlatch_p_1841 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_s2_v_q_reg | tri_rlmlatch_p_1842 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[8].q_tid_q_reg | tri_rlmreg_p__parameterized37_1843 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_bard_addr_q_reg | tri_rlmreg_p__parameterized4_1844 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_dat_q_reg | tri_rlmreg_p__parameterized48_1845 | 0 | 0 | 0 | 0 | 26 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_ilat_q_reg | tri_rlmreg_p__parameterized9_1846 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_issued_q_reg | tri_rlmlatch_p_1847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_itag_q_reg | tri_rlmreg_p__parameterized13_1848 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1849 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_rdy_reg | tri_rlmlatch_p_1850 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s1_v_q_reg | tri_rlmlatch_p_1851 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1852 | 50 | 50 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_rdy_reg | tri_rlmlatch_p_1853 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_s2_v_q_reg | tri_rlmlatch_p_1854 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999.q_x_q_gen[9].q_tid_q_reg | tri_rlmreg_p__parameterized37_1855 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[10].q_rdy_q_reg | tri_rlmlatch_p_1856 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[11].q_rdy_q_reg | tri_rlmlatch_p_1857 | 103 | 103 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[12].q_rdy_q_reg | tri_rlmlatch_p_1858 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[13].q_rdy_q_reg | tri_rlmlatch_p_1859 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[14].q_rdy_q_reg | tri_rlmlatch_p_1860 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[15].q_rdy_q_reg | tri_rlmlatch_p_1861 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[4].q_rdy_q_reg | tri_rlmlatch_p_1862 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[5].q_rdy_q_reg | tri_rlmlatch_p_1863 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[6].q_rdy_q_reg | tri_rlmlatch_p_1864 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[7].q_rdy_q_reg | tri_rlmlatch_p_1865 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[8].q_rdy_q_reg | tri_rlmlatch_p_1866 | 27 | 27 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl999i.q_x_q_gen[9].q_rdy_q_reg | tri_rlmlatch_p_1867 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_abort_reg | tri_rlmreg_p__parameterized13_1868 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_ex3_abort_reg | tri_rlmlatch_p_1869 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xx_rv_ex4_abort_reg | tri_rlmlatch_p_1870 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lqrf | tri_144x78_2r4w_1166 | 2176 | 2176 | 0 | 0 | 4272 | 0 | 0 | 0 | | rf_byp | rv_rf_byp | 2300 | 2300 | 0 | 0 | 712 | 0 | 0 | 0 | | (rf_byp) | rv_rf_byp | 1666 | 1666 | 0 | 0 | 0 | 0 | 0 | 0 | | fx0_ex0_ilat_reg | tri_rlmreg_p__parameterized9_1282 | 28 | 28 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex0_ord_reg | tri_rlmlatch_p_1283 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex0_s1_itag_latch | tri_rlmreg_p__parameterized13_1284 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | fx0_ex0_s2_itag_latch | tri_rlmreg_p__parameterized13_1285 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | fx0_ex0_s3_itag_latch | tri_rlmreg_p__parameterized13_1286 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | fx0_ex1_ilat_reg | tri_rlmreg_p__parameterized9_1287 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex1_ord_reg | tri_rlmlatch_p_1288 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex2_ilat_reg | tri_rlmreg_p__parameterized9_1289 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex2_ord_reg | tri_rlmlatch_p_1290 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex3_ilat_reg | tri_rlmreg_p__parameterized9_1291 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex3_ord_flush_reg | tri_rlmlatch_p_1292 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex3_ord_rel_reg | tri_rlmreg_p__parameterized37_1293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex4_ilat_reg | tri_rlmreg_p__parameterized9_1294 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex4_ord_rel_reg | tri_rlmreg_p__parameterized37_1295 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex5_ilat_reg | tri_rlmreg_p__parameterized9_1296 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex5_recircd_reg | tri_rlmlatch_p_1297 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex6_ilat_reg | tri_rlmreg_p__parameterized9_1298 | 13 | 13 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex6_recircd_reg | tri_rlmlatch_p_1299 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex7_ilat_reg | tri_rlmreg_p__parameterized9_1300 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ex7_recircd_reg | tri_rlmlatch_p_1301 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ex8_ilat_reg | tri_rlmreg_p__parameterized9_1302 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | fx0_ext_itag0_sel_reg | tri_rlmlatch_p_1303 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ext_rel_itag_abort_reg | tri_rlmlatch_p_1304 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_ext_rel_itag_reg | tri_rlmreg_p__parameterized13_1305 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | fx0_ext_rel_itag_vld_reg | tri_rlmreg_p__parameterized37_1306 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_need_rel_reg | tri_rlmreg_p__parameterized4_1307 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | fx0_rel_itag_abort_reg | tri_rlmlatch_p_1308 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_rel_itag_reg | tri_rlmreg_p__parameterized13_1309 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | fx0_rel_itag_vld_reg | tri_rlmreg_p__parameterized37_1310 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_release_ord_hold_reg | tri_rlmreg_p__parameterized37_1311 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx0_sched_rel_pri_or_reg | tri_rlmlatch_p_1312 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex0_ilat_reg | tri_rlmreg_p__parameterized5_1313 | 24 | 24 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex0_need_rel_reg | tri_rlmlatch_p_1314 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex0_s1_itag_latch | tri_rlmreg_p__parameterized13_1315 | 19 | 19 | 0 | 0 | 7 | 0 | 0 | 0 | | fx1_ex0_s2_itag_latch | tri_rlmreg_p__parameterized13_1316 | 6 | 6 | 0 | 0 | 7 | 0 | 0 | 0 | | fx1_ex0_s3_itag_latch | tri_rlmreg_p__parameterized13_1317 | 2 | 2 | 0 | 0 | 7 | 0 | 0 | 0 | | fx1_ex1_ilat_reg | tri_rlmreg_p__parameterized5_1318 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex1_need_rel_reg | tri_rlmlatch_p_1319 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex1_stq_pipe_reg | tri_rlmlatch_p_1320 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex2_ilat_reg | tri_rlmreg_p__parameterized5_1321 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex2_need_rel_reg | tri_rlmlatch_p_1322 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex2_stq_pipe_reg | tri_rlmlatch_p_1323 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex3_ilat_reg | tri_rlmreg_p__parameterized5_1324 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex3_need_rel_reg | tri_rlmlatch_p_1325 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ex4_ilat_reg | tri_rlmreg_p__parameterized5_1326 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex5_ilat_reg | tri_rlmreg_p__parameterized5_1327 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ex6_ilat_reg | tri_rlmreg_p__parameterized5_1328 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | fx1_ext_itag0_sel_reg | tri_rlmlatch_p_1329 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ext_rel_itag_abort_reg | tri_rlmlatch_p_1330 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_ext_rel_itag_reg | tri_rlmreg_p__parameterized13_1331 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | fx1_ext_rel_itag_vld_reg | tri_rlmreg_p__parameterized37_1332 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_rel_itag_abort_reg | tri_rlmlatch_p_1333 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_rel_itag_reg | tri_rlmreg_p__parameterized13_1334 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | fx1_rel_itag_vld_reg | tri_rlmreg_p__parameterized37_1335 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fx1_sched_rel_pri_or_reg | tri_rlmlatch_p_1336 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | fxu0_s1_latch | tri_rlmreg_p__parameterized9_1337 | 10 | 10 | 0 | 0 | 4 | 0 | 0 | 0 | | fxu0_s2_latch | tri_rlmreg_p__parameterized9_1338 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | fxu0_s3_latch | tri_rlmreg_p__parameterized9_1339 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | fxu1_s1_latch | tri_rlmreg_p__parameterized9_1340 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | fxu1_s2_latch | tri_rlmreg_p__parameterized9_1341 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | fxu1_s3_latch | tri_rlmreg_p__parameterized9_1342 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[0].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1343 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[10].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1344 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[11].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1345 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[12].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1346 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[1].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1347 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[2].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1348 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[3].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1349 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[4].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1350 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[5].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1351 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[6].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1352 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[7].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1353 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[8].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1354 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | genblk24.fxu0_t3_gen[9].fxu0_t3_latch | tri_rlmreg_p__parameterized9_1355 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | lq_s1_latch | tri_rlmreg_p__parameterized9_1356 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | lq_s2_latch | tri_rlmreg_p__parameterized9_1357 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xab0.fx0xab[3].fx0_abort_reg | tri_rlmlatch_p_1358 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xab0.fx0xab[4].fx0_abort_reg | tri_rlmlatch_p_1359 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xab1.fx1xab[3].fx0_abort_reg | tri_rlmlatch_p_1360 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[0].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1361 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[10].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1362 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[11].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1363 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[12].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1364 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[1].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1365 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[2].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1366 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[3].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1367 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[4].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1368 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[5].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1369 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[6].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1370 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[7].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1371 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[8].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1372 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl21.fxu0_t1_gen[9].fxu0_t1_latch | tri_rlmreg_p__parameterized9_1373 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[0].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1374 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[10].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1375 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[11].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1376 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[12].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1377 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[1].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1378 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[2].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1379 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[3].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1380 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[4].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1381 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[5].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1382 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[6].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1383 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[7].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1384 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[8].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1385 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl22.fxu0_t2_gen[9].fxu0_t2_latch | tri_rlmreg_p__parameterized9_1386 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[0].lq_t1_latch | tri_rlmreg_p__parameterized9_1387 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[1].lq_t1_latch | tri_rlmreg_p__parameterized9_1388 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[2].lq_t1_latch | tri_rlmreg_p__parameterized9_1389 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[3].lq_t1_latch | tri_rlmreg_p__parameterized9_1390 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[4].lq_t1_latch | tri_rlmreg_p__parameterized9_1391 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[5].lq_t1_latch | tri_rlmreg_p__parameterized9_1392 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[6].lq_t1_latch | tri_rlmreg_p__parameterized9_1393 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[7].lq_t1_latch | tri_rlmreg_p__parameterized9_1394 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl24.lq_t1_gen[8].lq_t1_latch | tri_rlmreg_p__parameterized9_1395 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[0].lq_t3_latch | tri_rlmreg_p__parameterized9_1396 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[1].lq_t3_latch | tri_rlmreg_p__parameterized9_1397 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[2].lq_t3_latch | tri_rlmreg_p__parameterized9_1398 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[3].lq_t3_latch | tri_rlmreg_p__parameterized9_1399 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[4].lq_t3_latch | tri_rlmreg_p__parameterized9_1400 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[5].lq_t3_latch | tri_rlmreg_p__parameterized9_1401 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[6].lq_t3_latch | tri_rlmreg_p__parameterized9_1402 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[7].lq_t3_latch | tri_rlmreg_p__parameterized9_1403 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl26.lq_t3_gen[8].lq_t3_latch | tri_rlmreg_p__parameterized9_1404 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[0].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1405 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[1].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1406 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[2].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1407 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[3].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1408 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[4].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1409 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[5].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1410 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[6].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1411 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl27.fxu1_t1_gen[7].fxu1_t1_latch | tri_rlmreg_p__parameterized9_1412 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[0].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1413 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[1].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1414 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[2].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1415 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[3].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1416 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[4].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1417 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[5].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1418 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[6].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1419 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl28.fxu1_t2_gen[7].fxu1_t2_latch | tri_rlmreg_p__parameterized9_1420 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[0].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1421 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[1].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1422 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[2].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1423 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[3].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1424 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[4].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1425 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[5].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1426 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[6].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1427 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl29.fxu1_t3_gen[7].fxu1_t3_latch | tri_rlmreg_p__parameterized9_1428 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[0].fx1_itag_reg | tri_rlmreg_p__parameterized13_1429 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[1].fx1_itag_reg | tri_rlmreg_p__parameterized13_1430 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[2].fx1_itag_reg | tri_rlmreg_p__parameterized13_1431 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[3].fx1_itag_reg | tri_rlmreg_p__parameterized13_1432 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[4].fx1_itag_reg | tri_rlmreg_p__parameterized13_1433 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[5].fx1_itag_reg | tri_rlmreg_p__parameterized13_1434 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[6].fx1_itag_reg | tri_rlmreg_p__parameterized13_1435 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70.fxu1_itag_gen[7].fx1_itag_reg | tri_rlmreg_p__parameterized13_1436 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[0].fx1_vld_reg | tri_rlmreg_p__parameterized37_1437 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[1].fx1_vld_reg | tri_rlmreg_p__parameterized37_1438 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[2].fx1_vld_reg | tri_rlmreg_p__parameterized37_1439 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[3].fx1_vld_reg | tri_rlmreg_p__parameterized37_1440 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[4].fx1_vld_reg | tri_rlmreg_p__parameterized37_1441 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[5].fx1_vld_reg | tri_rlmreg_p__parameterized37_1442 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl70v.fxu1_vld_gen[6].fx1_vld_reg | tri_rlmreg_p__parameterized37_1443 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl77.rel_gen[0].rel_itag_latch | tri_rlmreg_p__parameterized13_1444 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl77.rel_gen[0].rel_vld_latch | tri_rlmreg_p__parameterized37_1445 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl77.rel_gen[1].rel_itag_latch | tri_rlmreg_p__parameterized13_1446 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl77.rel_gen[1].rel_vld_latch | tri_rlmreg_p__parameterized37_1447 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl77.rel_gen[2].rel_itag_latch | tri_rlmreg_p__parameterized13_1448 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl77.rel_gen[2].rel_vld_latch | tri_rlmreg_p__parameterized37_1449 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl77.rel_gen[3].rel_itag_latch | tri_rlmreg_p__parameterized13_1450 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl77.rel_gen[3].rel_vld_latch | tri_rlmreg_p__parameterized37_1451 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[1].fx0_is_brick_reg | tri_rlmlatch_p_1452 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[2].fx0_is_brick_reg | tri_rlmlatch_p_1453 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[3].fx0_is_brick_reg | tri_rlmlatch_p_1454 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[4].fx0_is_brick_reg | tri_rlmlatch_p_1455 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[5].fx0_is_brick_reg | tri_rlmlatch_p_1456 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[6].fx0_is_brick_reg | tri_rlmlatch_p_1457 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78b.fxu0_itagv_gen[7].fx0_is_brick_reg | tri_rlmlatch_p_1458 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[0].fx0_itag_reg | tri_rlmreg_p__parameterized13_1459 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[10].fx0_itag_reg | tri_rlmreg_p__parameterized13_1460 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[11].fx0_itag_reg | tri_rlmreg_p__parameterized13_1461 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[12].fx0_itag_reg | tri_rlmreg_p__parameterized13_1462 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[1].fx0_itag_reg | tri_rlmreg_p__parameterized13_1463 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[2].fx0_itag_reg | tri_rlmreg_p__parameterized13_1464 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[3].fx0_itag_reg | tri_rlmreg_p__parameterized13_1465 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[4].fx0_itag_reg | tri_rlmreg_p__parameterized13_1466 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[5].fx0_itag_reg | tri_rlmreg_p__parameterized13_1467 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[6].fx0_itag_reg | tri_rlmreg_p__parameterized13_1468 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[7].fx0_itag_reg | tri_rlmreg_p__parameterized13_1469 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[8].fx0_itag_reg | tri_rlmreg_p__parameterized13_1470 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78i.fxu0_itag_gen[9].fx0_itag_reg | tri_rlmreg_p__parameterized13_1471 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[0].fx0_vld_reg | tri_rlmreg_p__parameterized37_1472 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[10].fx0_vld_reg | tri_rlmreg_p__parameterized37_1473 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[11].fx0_vld_reg | tri_rlmreg_p__parameterized37_1474 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[1].fx0_vld_reg | tri_rlmreg_p__parameterized37_1475 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[2].fx0_vld_reg | tri_rlmreg_p__parameterized37_1476 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[3].fx0_vld_reg | tri_rlmreg_p__parameterized37_1477 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[4].fx0_vld_reg | tri_rlmreg_p__parameterized37_1478 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[5].fx0_vld_reg | tri_rlmreg_p__parameterized37_1479 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[6].fx0_vld_reg | tri_rlmreg_p__parameterized37_1480 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[7].fx0_vld_reg | tri_rlmreg_p__parameterized37_1481 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[8].fx0_vld_reg | tri_rlmreg_p__parameterized37_1482 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl78v.fxu0_itagv_gen[9].fx0_vld_reg | tri_rlmreg_p__parameterized37_1483 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[0].lq_vld_latch | tri_rlmreg_p__parameterized37_1484 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[1].lq_vld_latch | tri_rlmreg_p__parameterized37_1485 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[2].lq_vld_latch | tri_rlmreg_p__parameterized37_1486 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[3].lq_vld_latch | tri_rlmreg_p__parameterized37_1487 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[4].lq_vld_latch | tri_rlmreg_p__parameterized37_1488 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[5].lq_vld_latch | tri_rlmreg_p__parameterized37_1489 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[6].lq_vld_latch | tri_rlmreg_p__parameterized37_1490 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl80.lq_vld_gen[7].lq_vld_latch | tri_rlmreg_p__parameterized37_1491 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[0].lq_itag_reg | tri_rlmreg_p__parameterized13_1492 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[1].lq_itag_reg | tri_rlmreg_p__parameterized13_1493 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[2].lq_itag_reg | tri_rlmreg_p__parameterized13_1494 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[3].lq_itag_reg | tri_rlmreg_p__parameterized13_1495 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[4].lq_itag_reg | tri_rlmreg_p__parameterized13_1496 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[5].lq_itag_reg | tri_rlmreg_p__parameterized13_1497 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[6].lq_itag_reg | tri_rlmreg_p__parameterized13_1498 | 9 | 9 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[7].lq_itag_reg | tri_rlmreg_p__parameterized13_1499 | 8 | 8 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl81.lq_itag_gen[8].lq_itag_reg | tri_rlmreg_p__parameterized13_1500 | 1 | 1 | 0 | 0 | 7 | 0 | 0 | 0 | | rv_deps0 | rv_deps | 2421 | 2421 | 0 | 0 | 596 | 0 | 0 | 0 | | cp_flush_reg | tri_rlmreg_p__parameterized37_1167 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_instr_i0_flushed_reg | tri_rlmreg_p__parameterized37_1168 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_instr_i1_flushed_reg | tri_rlmreg_p__parameterized37_1169 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_2ucode_q_reg | tri_rlmlatch_p_1170 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_branch_q_reg | tri_rlmreg_p__parameterized33_1171 | 0 | 0 | 0 | 0 | 63 | 0 | 0 | 0 | | rv0_t0_i0_cord_q_reg | tri_rlmlatch_p_1172 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_ifar_q_reg | tri_rlmreg_p__parameterized8_1173 | 12 | 12 | 0 | 0 | 20 | 0 | 0 | 0 | | rv0_t0_i0_ilat_q_reg | tri_rlmreg_p__parameterized9_1174 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | rv0_t0_i0_instr_q_reg | tri_rlmreg_p__parameterized17_1175 | 11 | 11 | 0 | 0 | 32 | 0 | 0 | 0 | | rv0_t0_i0_isLoad_q_reg | tri_rlmlatch_p_1176 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_isStore_q_reg | tri_rlmlatch_p_1177 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_itag_q_reg | tri_rlmreg_p__parameterized13_1178 | 16 | 16 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i0_ord_q_reg | tri_rlmlatch_p_1179 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_rte_axu0_q_reg | tri_rlmlatch_p_1180 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_rte_fx0_q_reg | tri_rlmlatch_p_1181 | 182 | 182 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_rte_fx1_q_reg | tri_rlmlatch_p_1182 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_rte_lq_q_reg | tri_rlmlatch_p_1183 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_rte_sq_q_reg | tri_rlmlatch_p_1184 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1185 | 125 | 125 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i0_s1_p_q_reg | tri_rlmreg_p__parameterized0_1186 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_s1_t_q_reg | tri_rlmreg_p__parameterized5_1187 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_s1_v_q_reg | tri_rlmlatch_p_1188 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1189 | 153 | 153 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i0_s2_p_q_reg | tri_rlmreg_p__parameterized0_1190 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_s2_t_q_reg | tri_rlmreg_p__parameterized5_1191 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_s2_v_q_reg | tri_rlmlatch_p_1192 | 12 | 12 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1193 | 184 | 184 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i0_s3_p_q_reg | tri_rlmreg_p__parameterized0_1194 | 22 | 22 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_s3_t_q_reg | tri_rlmreg_p__parameterized5_1195 | 14 | 14 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_s3_v_q_reg | tri_rlmlatch_p_1196 | 13 | 13 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_spec_q_reg | tri_rlmlatch_p_1197 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_t1_p_q_reg | tri_rlmreg_p__parameterized0_1198 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_t1_t_q_reg | tri_rlmreg_p__parameterized5_1199 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_t1_v_q_reg | tri_rlmlatch_p_1200 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_t2_p_q_reg | tri_rlmreg_p__parameterized0_1201 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_t2_t_q_reg | tri_rlmreg_p__parameterized5_1202 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_t2_v_q_reg | tri_rlmlatch_p_1203 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_t3_p_q_reg | tri_rlmreg_p__parameterized0_1204 | 1 | 1 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i0_t3_t_q_reg | tri_rlmreg_p__parameterized5_1205 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_t3_v_q_reg | tri_rlmlatch_p_1206 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i0_ucode_cnt_q_reg | tri_rlmreg_p__parameterized5_1207 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_ucode_q_reg | tri_rlmreg_p__parameterized5_1208 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i0_vld_reg | tri_rlmlatch_p_1209 | 24 | 24 | 0 | 0 | 2 | 0 | 0 | 0 | | rv0_t0_i1_branch_q_reg | tri_rlmreg_p__parameterized33_1210 | 1 | 1 | 0 | 0 | 63 | 0 | 0 | 0 | | rv0_t0_i1_cord_q_reg | tri_rlmlatch_p_1211 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_ifar_q_reg | tri_rlmreg_p__parameterized8_1212 | 12 | 12 | 0 | 0 | 20 | 0 | 0 | 0 | | rv0_t0_i1_ilat_q_reg | tri_rlmreg_p__parameterized9_1213 | 18 | 18 | 0 | 0 | 4 | 0 | 0 | 0 | | rv0_t0_i1_instr_q_reg | tri_rlmreg_p__parameterized17_1214 | 15 | 15 | 0 | 0 | 32 | 0 | 0 | 0 | | rv0_t0_i1_isLoad_q_reg | tri_rlmlatch_p_1215 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_isStore_q_reg | tri_rlmlatch_p_1216 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_itag_q_reg | tri_rlmreg_p__parameterized13_1217 | 22 | 22 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i1_ord_q_reg | tri_rlmlatch_p_1218 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_rte_axu0_q_reg | tri_rlmlatch_p_1219 | 526 | 526 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_rte_fx0_q_reg | tri_rlmlatch_p_1220 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_rte_fx1_q_reg | tri_rlmlatch_p_1221 | 22 | 22 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_rte_lq_q_reg | tri_rlmlatch_p_1222 | 11 | 11 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_rte_sq_q_reg | tri_rlmlatch_p_1223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s1_dep_hit_q_reg | tri_rlmlatch_p_1224 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s1_itag_q_reg | tri_rlmreg_p__parameterized13_1225 | 134 | 134 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i1_s1_p_q_reg | tri_rlmreg_p__parameterized0_1226 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_s1_t_q_reg | tri_rlmreg_p__parameterized5_1227 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_s1_v_q_reg | tri_rlmlatch_p_1228 | 18 | 18 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s2_dep_hit_q_reg | tri_rlmlatch_p_1229 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s2_itag_q_reg | tri_rlmreg_p__parameterized13_1230 | 178 | 178 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i1_s2_p_q_reg | tri_rlmreg_p__parameterized0_1231 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_s2_t_q_reg | tri_rlmreg_p__parameterized5_1232 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_s2_v_q_reg | tri_rlmlatch_p_1233 | 21 | 21 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s3_dep_hit_q_reg | tri_rlmlatch_p_1234 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_s3_itag_q_reg | tri_rlmreg_p__parameterized13_1235 | 170 | 170 | 0 | 0 | 7 | 0 | 0 | 0 | | rv0_t0_i1_s3_p_q_reg | tri_rlmreg_p__parameterized0_1236 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_s3_t_q_reg | tri_rlmreg_p__parameterized5_1237 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_s3_v_q_reg | tri_rlmlatch_p_1238 | 19 | 19 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_spec_q_reg | tri_rlmlatch_p_1239 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_t1_p_q_reg | tri_rlmreg_p__parameterized0_1240 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_t1_t_q_reg | tri_rlmreg_p__parameterized5_1241 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_t1_v_q_reg | tri_rlmlatch_p_1242 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_t2_p_q_reg | tri_rlmreg_p__parameterized0_1243 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_t2_t_q_reg | tri_rlmreg_p__parameterized5_1244 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_t2_v_q_reg | tri_rlmlatch_p_1245 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_t3_p_q_reg | tri_rlmreg_p__parameterized0_1246 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | rv0_t0_i1_t3_t_q_reg | tri_rlmreg_p__parameterized5_1247 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_t3_v_q_reg | tri_rlmlatch_p_1248 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv0_t0_i1_ucode_cnt_q_reg | tri_rlmreg_p__parameterized5_1249 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_ucode_q_reg | tri_rlmreg_p__parameterized5_1250 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | rv0_t0_i1_vld_reg | tri_rlmlatch_p_1251 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_2ucode_reg | tri_rlmlatch_p_1252 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_ifar_reg | tri_rlmreg_p__parameterized227_1253 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | rv1_lq_instr_i0_isLoad_reg | tri_rlmlatch_p_1254 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_isStore_reg | tri_rlmlatch_p_1255 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_itag_reg | tri_rlmreg_p__parameterized13_1256 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | rv1_lq_instr_i0_rte_lq_reg | tri_rlmlatch_p_1257 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_rte_sq_reg | tri_rlmlatch_p_1258 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_s3_t_reg | tri_rlmreg_p__parameterized5_1259 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | rv1_lq_instr_i0_ucode_cnt_reg | tri_rlmreg_p__parameterized5_1260 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv1_lq_instr_i0_ucode_preissue_reg | tri_rlmlatch_p_1261 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i0_vld_reg | tri_rlmreg_p__parameterized37_1262 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_ifar_reg | tri_rlmreg_p__parameterized227_1263 | 0 | 0 | 0 | 0 | 12 | 0 | 0 | 0 | | rv1_lq_instr_i1_isLoad_reg | tri_rlmlatch_p_1264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_isStore_reg | tri_rlmlatch_p_1265 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_itag_reg | tri_rlmreg_p__parameterized13_1266 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | rv1_lq_instr_i1_rte_lq_reg | tri_rlmlatch_p_1267 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_rte_sq_reg | tri_rlmlatch_p_1268 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_s3_t_reg | tri_rlmreg_p__parameterized5_1269 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | rv1_lq_instr_i1_ucode_cnt_reg | tri_rlmreg_p__parameterized5_1270 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | rv1_lq_instr_i1_ucode_preissue_reg | tri_rlmlatch_p_1271 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv1_lq_instr_i1_vld_reg | tri_rlmreg_p__parameterized37_1272 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rv_dep0 | rv_dep | 292 | 292 | 0 | 0 | 73 | 0 | 0 | 0 | | sc | rv_dep_scard | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | scorecard_reg | tri_rlmreg_p__parameterized17_1281 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xx_rv_itag_abort_reg | tri_rlmreg_p__parameterized13_1273 | 3 | 3 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary0_q_reg | tri_rlmreg_p__parameterized4_1274 | 29 | 29 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary1_q_reg | tri_rlmreg_p__parameterized4_1275 | 61 | 61 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary2_q_reg | tri_rlmreg_p__parameterized4_1276 | 24 | 24 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary3_q_reg | tri_rlmreg_p__parameterized4_1277 | 104 | 104 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary4_q_reg | tri_rlmreg_p__parameterized4_1278 | 38 | 38 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_ary5_q_reg | tri_rlmreg_p__parameterized4_1279 | 29 | 29 | 0 | 0 | 5 | 0 | 0 | 0 | | xx_rv_itag_v_reg | tri_rlmreg_p__parameterized13_1280 | 4 | 4 | 0 | 0 | 6 | 0 | 0 | 0 | | xu0 | xu | 37048 | 37048 | 0 | 0 | 15173 | 1 | 0 | 0 | | (xu0) | xu | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | cr | xu_rf | 804 | 804 | 0 | 0 | 184 | 0 | 0 | 0 | | entry[0].reg_latch | tri_regk_1115 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[10].reg_latch | tri_regk_1116 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[11].reg_latch | tri_regk_1117 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[12].reg_latch | tri_regk_1118 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[13].reg_latch | tri_regk_1119 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[14].reg_latch | tri_regk_1120 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[15].reg_latch | tri_regk_1121 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[16].reg_latch | tri_regk_1122 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[17].reg_latch | tri_regk_1123 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[18].reg_latch | tri_regk_1124 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[19].reg_latch | tri_regk_1125 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[1].reg_latch | tri_regk_1126 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[20].reg_latch | tri_regk_1127 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[21].reg_latch | tri_regk_1128 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[22].reg_latch | tri_regk_1129 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[23].reg_latch | tri_regk_1130 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[2].reg_latch | tri_regk_1131 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[3].reg_latch | tri_regk_1132 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[4].reg_latch | tri_regk_1133 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[5].reg_latch | tri_regk_1134 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[6].reg_latch | tri_regk_1135 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[7].reg_latch | tri_regk_1136 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[8].reg_latch | tri_regk_1137 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | entry[9].reg_latch | tri_regk_1138 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | r0a_latch | tri_rlmreg_p__parameterized4_1139 | 58 | 58 | 0 | 0 | 5 | 0 | 0 | 0 | | r0d_latch | tri_rlmreg_p__parameterized9_1140 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | r0e_latch | tri_rlmlatch_p_1141 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r1_gen1.r1a_latch | tri_rlmreg_p__parameterized4_1142 | 76 | 76 | 0 | 0 | 5 | 0 | 0 | 0 | | r1_gen1.r1d_latch | tri_rlmreg_p__parameterized9_1143 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | r1_gen1.r1e_latch | tri_rlmlatch_p_1144 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | r2_gen1.r2a_latch | tri_rlmreg_p__parameterized4_1145 | 77 | 77 | 0 | 0 | 5 | 0 | 0 | 0 | | r2_gen1.r2d_latch | tri_rlmreg_p__parameterized9_1146 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | r2_gen1.r2e_latch | tri_rlmlatch_p_1147 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | r3_gen1.r3a_latch | tri_rlmreg_p__parameterized4_1148 | 79 | 79 | 0 | 0 | 5 | 0 | 0 | 0 | | r3_gen1.r3d_latch | tri_rlmreg_p__parameterized9_1149 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | r3_gen1.r3e_latch | tri_rlmlatch_p_1150 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | w0a_latch | tri_rlmreg_p__parameterized4_1151 | 63 | 63 | 0 | 0 | 5 | 0 | 0 | 0 | | w0d_latch | tri_rlmreg_p__parameterized9_1152 | 25 | 25 | 0 | 0 | 4 | 0 | 0 | 0 | | w0e_latch | tri_rlmlatch_p_1153 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | w1_gen1.w1a_latch | tri_rlmreg_p__parameterized4_1154 | 59 | 59 | 0 | 0 | 5 | 0 | 0 | 0 | | w1_gen1.w1d_latch | tri_rlmreg_p__parameterized9_1155 | 21 | 21 | 0 | 0 | 4 | 0 | 0 | 0 | | w1_gen1.w1e_latch | tri_rlmlatch_p_1156 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | w2_gen1.w2a_latch | tri_rlmreg_p__parameterized4_1157 | 84 | 84 | 0 | 0 | 5 | 0 | 0 | 0 | | w2_gen1.w2d_latch | tri_rlmreg_p__parameterized9_1158 | 30 | 30 | 0 | 0 | 2 | 0 | 0 | 0 | | w2_gen1.w2e_latch | tri_rlmlatch_p_1159 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | w3_gen1.w3a_latch | tri_rlmreg_p__parameterized4_1160 | 64 | 64 | 0 | 0 | 5 | 0 | 0 | 0 | | w3_gen1.w3d_latch | tri_rlmreg_p__parameterized9_1161 | 32 | 32 | 0 | 0 | 4 | 0 | 0 | 0 | | w3_gen1.w3e_latch | tri_rlmlatch_p_1162 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | w4_gen1.w4a_latch | tri_rlmreg_p__parameterized4_1163 | 39 | 39 | 0 | 0 | 5 | 0 | 0 | 0 | | w4_gen1.w4d_latch | tri_rlmreg_p__parameterized9_1164 | 68 | 68 | 0 | 0 | 4 | 0 | 0 | 0 | | w4_gen1.w4e_latch | tri_rlmlatch_p_1165 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ctr | xu_rf__parameterized2 | 775 | 775 | 0 | 0 | 648 | 0 | 0 | 0 | | entry[0].reg_latch | tri_regk__parameterized1_1101 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[1].reg_latch | tri_regk__parameterized1_1102 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[2].reg_latch | tri_regk__parameterized1_1103 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[3].reg_latch | tri_regk__parameterized1_1104 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[4].reg_latch | tri_regk__parameterized1_1105 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[5].reg_latch | tri_regk__parameterized1_1106 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[6].reg_latch | tri_regk__parameterized1_1107 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[7].reg_latch | tri_regk__parameterized1_1108 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | r0a_latch | tri_rlmreg_p__parameterized5_1109 | 128 | 128 | 0 | 0 | 3 | 0 | 0 | 0 | | r0d_latch | tri_rlmreg_p__parameterized33_1110 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | r0e_latch | tri_rlmlatch_p_1111 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | w0a_latch | tri_rlmreg_p__parameterized5_1112 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | w0d_latch | tri_rlmreg_p__parameterized33_1113 | 640 | 640 | 0 | 0 | 64 | 0 | 0 | 0 | | w0e_latch | tri_rlmlatch_p_1114 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gpr | xu_gpr | 4353 | 4353 | 0 | 0 | 4455 | 0 | 0 | 0 | | gpr0 | tri_144x78_2r4w | 68 | 68 | 0 | 0 | 240 | 0 | 0 | 0 | | gpr1 | tri_144x78_2r4w_1098 | 4284 | 4284 | 0 | 0 | 4208 | 0 | 0 | 0 | | r4a_latch | tri_rlmreg_p__parameterized0_1099 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | r4e_latch | tri_rlmlatch_p_1100 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_gpr_ex6_wa_latch | tri_rlmreg_p__parameterized0 | 3046 | 3046 | 0 | 0 | 6 | 0 | 0 | 0 | | lq_xu_gpr_ex6_wd_latch | tri_rlmreg_p__parameterized33 | 188 | 188 | 0 | 0 | 64 | 0 | 0 | 0 | | lq_xu_gpr_ex6_we_latch | tri_rlmlatch_p | 607 | 607 | 0 | 0 | 1 | 0 | 0 | 0 | | lr | xu_rf__parameterized1 | 1024 | 1024 | 0 | 0 | 714 | 0 | 0 | 0 | | entry[0].reg_latch | tri_regk__parameterized1 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[1].reg_latch | tri_regk__parameterized1_1082 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[2].reg_latch | tri_regk__parameterized1_1083 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[3].reg_latch | tri_regk__parameterized1_1084 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[4].reg_latch | tri_regk__parameterized1_1085 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[5].reg_latch | tri_regk__parameterized1_1086 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[6].reg_latch | tri_regk__parameterized1_1087 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | entry[7].reg_latch | tri_regk__parameterized1_1088 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | r0a_latch | tri_rlmreg_p__parameterized5_1089 | 128 | 128 | 0 | 0 | 3 | 0 | 0 | 0 | | r0d_latch | tri_rlmreg_p__parameterized33_1090 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | r0e_latch | tri_rlmlatch_p_1091 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r1_gen1.r1a_latch | tri_rlmreg_p__parameterized5_1092 | 124 | 124 | 0 | 0 | 3 | 0 | 0 | 0 | | r1_gen1.r1d_latch | tri_rlmreg_p__parameterized33_1093 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | r1_gen1.r1e_latch | tri_rlmlatch_p_1094 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | w0a_latch | tri_rlmreg_p__parameterized5_1095 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | w0d_latch | tri_rlmreg_p__parameterized33_1096 | 764 | 764 | 0 | 0 | 64 | 0 | 0 | 0 | | w0e_latch | tri_rlmlatch_p_1097 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr | xu_spr | 4198 | 4198 | 0 | 0 | 2240 | 1 | 0 | 0 | | int_rest_ifar_latch_gen.thread[0].int_rest_ifar_latch | tri_rlmreg_p__parameterized40_855 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | threads.thread[0].xu_spr_tspr | xu_spr_tspr | 2477 | 2477 | 0 | 0 | 1294 | 0 | 0 | 0 | | ccr3_latch | tri_ser_rlmreg_p__parameterized16_973 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized16_1081 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | csrr0_latch_gen.csrr0_latch | tri_ser_rlmreg_p__parameterized8 | 25 | 25 | 0 | 0 | 62 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized8_1080 | 25 | 25 | 0 | 0 | 62 | 0 | 0 | 0 | | csrr1_latch_gen.csrr1_latch | tri_ser_rlmreg_p__parameterized9 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9_1079 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | dbcr0_latch | tri_ser_rlmreg_p__parameterized19 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized19 | 1 | 1 | 0 | 0 | 21 | 0 | 0 | 0 | | dbcr1_latch | tri_ser_rlmreg_p__parameterized20 | 11 | 11 | 0 | 0 | 18 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized20 | 11 | 11 | 0 | 0 | 18 | 0 | 0 | 0 | | dbsr_latch | tri_ser_rlmreg_p__parameterized21 | 11 | 11 | 0 | 0 | 20 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized21 | 11 | 11 | 0 | 0 | 20 | 0 | 0 | 0 | | dbsr_mrr_latch | tri_rlmreg_p__parameterized2_974 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | dear_latch | tri_ser_rlmreg_p__parameterized12 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_1078 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | dec_interrupt_latch | tri_rlmlatch_p_975 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dec_latch | tri_ser_rlmreg_p__parameterized10 | 107 | 107 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized10_1077 | 107 | 107 | 0 | 0 | 32 | 0 | 0 | 0 | | decar_latch_gen.decar_latch | tri_ser_rlmreg_p__parameterized10_976 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized10_1076 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | dnhdr_latch | tri_ser_rlmreg_p__parameterized15 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized15_1075 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | | epcr_latch_gen.epcr_latch | tri_ser_rlmreg_p__parameterized11 | 2 | 2 | 0 | 0 | 10 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized11_1074 | 2 | 2 | 0 | 0 | 10 | 0 | 0 | 0 | | err_llbust_attempt_latch | tri_rlmlatch_p_977 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | err_llbust_failed_latch | tri_rlmlatch_p_978 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | err_wdt_reset_latch | tri_rlmlatch_p_979 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | esr_latch | tri_ser_rlmreg_p__parameterized13 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized13_1073 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | | ex2_dnh_latch | tri_regk__parameterized2_980 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_instr_latch | tri_regk__parameterized3 | 606 | 606 | 0 | 0 | 15 | 0 | 0 | 0 | | ex2_is_mfmsr_latch | tri_regk__parameterized2_981 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtmsr_latch | tri_regk__parameterized2_982 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtspr_latch | tri_regk__parameterized2_983 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_wrtee_latch | tri_regk__parameterized2_984 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_wrteei_latch | tri_regk__parameterized2_985 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dnh_latch | tri_rlmlatch_p_986 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dnh_val_latch | tri_rlmlatch_p_987 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_instr_latch | tri_rlmreg_p__parameterized243 | 224 | 224 | 0 | 0 | 15 | 0 | 0 | 0 | | ex3_is_mtmsr_latch | tri_rlmlatch_p_988 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_mtspr_latch | tri_rlmlatch_p_989 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_spr_wd_latch | tri_rlmreg_p__parameterized33_990 | 353 | 353 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_tid_rpwr_latch | tri_rlmreg_p__parameterized12_991 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_tspr_rt_latch | tri_rlmreg_p__parameterized33_992 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_wrtee_latch | tri_rlmlatch_p_993 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wrteei_latch | tri_rlmlatch_p_994 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized242 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | fit_interrupt_latch | tri_rlmlatch_p_995 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | fit_tb_tap_latch | tri_rlmlatch_p_996 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gdear_latch_gen.gdear_latch | tri_ser_rlmreg_p__parameterized12_997 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12_1072 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | gdec_interrupt_latch | tri_rlmlatch_p_998 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gdec_latch_gen.gdec_latch | tri_ser_rlmreg_p__parameterized10_999 | 106 | 106 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized10_1071 | 106 | 106 | 0 | 0 | 32 | 0 | 0 | 0 | | gdecar_latch_gen.gdecar_latch | tri_ser_rlmreg_p__parameterized10_1000 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized10_1070 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | gesr_latch_gen.gesr_latch | tri_ser_rlmreg_p__parameterized13_1001 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized13 | 0 | 0 | 0 | 0 | 17 | 0 | 0 | 0 | | gfit_interrupt_latch | tri_rlmlatch_p_1002 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gfit_tb_tap_latch | tri_rlmlatch_p_1003 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gpir_latch_gen.gpir_latch | tri_ser_rlmreg_p__parameterized6_1004 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_1069 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | gsrr0_latch_gen.gsrr0_latch | tri_ser_rlmreg_p__parameterized8_1005 | 40 | 40 | 0 | 0 | 62 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized8_1068 | 40 | 40 | 0 | 0 | 62 | 0 | 0 | 0 | | gsrr1_latch_gen.gsrr1_latch | tri_ser_rlmreg_p__parameterized9_1006 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9_1067 | 7 | 7 | 0 | 0 | 14 | 0 | 0 | 0 | | gtcr_latch_gen.gtcr_latch | tri_ser_rlmreg_p__parameterized11_1007 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized11 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | gtsr_latch_gen.gtsr_latch | tri_ser_rlmreg_p__parameterized14_1008 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized14_1066 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | gwdog_interrupt_latch | tri_rlmlatch_p_1009 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gwdog_tb_tap_latch | tri_rlmlatch_p_1010 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac1_en_latch | tri_rlmlatch_p_1011 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac2_en_latch | tri_rlmlatch_p_1012 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iac3_en_latch | tri_rlmlatch_p_1013 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iac4_en_latch | tri_rlmlatch_p_1014 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_llbust_attempt_latch | tri_rlmlatch_p_1015 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_llbust_failed_latch | tri_rlmlatch_p_1016 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_cint_latch | tri_rlmlatch_p_1017 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_dbsr_ide_latch | tri_rlmlatch_p_1018 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_dbsr_latch | tri_rlmreg_p__parameterized204 | 5 | 5 | 0 | 0 | 19 | 0 | 0 | 0 | | iu_dbsr_ude_latch | tri_rlmlatch_p_1019 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_dbsr_update_latch | tri_rlmlatch_p_1020 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_dear_latch | tri_rlmreg_p__parameterized33_1021 | 161 | 161 | 0 | 0 | 64 | 0 | 0 | 0 | | iu_dear_update_latch | tri_rlmlatch_p_1022 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_esr_latch | tri_rlmreg_p__parameterized51 | 1 | 1 | 0 | 0 | 17 | 0 | 0 | 0 | | iu_esr_update_latch | tri_rlmlatch_p_1023 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_force_gsrr_latch | tri_rlmlatch_p_1024 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_gint_latch | tri_rlmlatch_p_1025 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_int_latch | tri_rlmlatch_p_1026 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_mcint_latch | tri_rlmlatch_p_1027 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_mcsr_latch | tri_rlmreg_p__parameterized43_1028 | 15 | 15 | 0 | 0 | 15 | 0 | 0 | 0 | | iu_nia_latch | tri_rlmreg_p__parameterized40_1029 | 374 | 374 | 0 | 0 | 62 | 0 | 0 | 0 | | iu_rfci_latch | tri_rlmlatch_p_1030 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_rfgi_latch | tri_rlmlatch_p_1031 | 35 | 35 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_rfi_latch | tri_rlmlatch_p_1032 | 32 | 32 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_rfmci_latch | tri_rlmlatch_p_1033 | 31 | 31 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_xu_act_latch | tri_rlmlatch_p_1034 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | llcnt_latch | tri_rlmreg_p__parameterized2_1035 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | lltap_latch | tri_rlmlatch_p_1036 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | mcsr_latch_gen.mcsr_latch | tri_ser_rlmreg_p__parameterized15_1037 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized15 | 0 | 0 | 0 | 0 | 15 | 0 | 0 | 0 | | mcsrr0_latch_gen.mcsrr0_latch | tri_ser_rlmreg_p__parameterized8_1038 | 48 | 48 | 0 | 0 | 62 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized8_1065 | 48 | 48 | 0 | 0 | 62 | 0 | 0 | 0 | | mcsrr1_latch_gen.mcsrr1_latch | tri_ser_rlmreg_p__parameterized9_1039 | 2 | 2 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9_1064 | 2 | 2 | 0 | 0 | 14 | 0 | 0 | 0 | | msr_latch | tri_ser_rlmreg_p__parameterized9_1040 | 108 | 108 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9_1063 | 108 | 108 | 0 | 0 | 14 | 0 | 0 | 0 | | msrovride_de_latch | tri_rlmlatch_p_1041 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | msrovride_gs_latch | tri_rlmlatch_p_1042 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msrovride_pr_latch | tri_rlmlatch_p_1043 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msrp_latch_gen.msrp_latch | tri_ser_rlmreg_p__parameterized16_1044 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized16_1062 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | mux_msr_gs_latch | tri_rlmreg_p__parameterized5_1045 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | mux_msr_pr_latch | tri_rlmlatch_p_1046 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | raise_iss_pri_2_latch | tri_rlmlatch_p_1047 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | raise_iss_pri_latch | tri_rlmlatch_p_1048 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ram_active_latch | tri_rlmlatch_p_1049 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | siar_latch | tri_ser_rlmreg_p__parameterized12_1050 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized12 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | single_instr_mode_2_latch | tri_rlmlatch_p_1051 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | single_instr_mode_latch | tri_rlmlatch_p_1052 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | srr0_latch | tri_ser_rlmreg_p__parameterized8_1053 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized8 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | srr1_latch | tri_ser_rlmreg_p__parameterized9_1054 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized9 | 0 | 0 | 0 | 0 | 14 | 0 | 0 | 0 | | tcr_latch_gen.tcr_latch | tri_ser_rlmreg_p__parameterized17 | 3 | 3 | 0 | 0 | 12 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized17 | 3 | 3 | 0 | 0 | 12 | 0 | 0 | 0 | | timebase_taps_latch | tri_rlmreg_p__parameterized6_1055 | 18 | 18 | 0 | 0 | 10 | 0 | 0 | 0 | | tsr_latch_gen.tsr_latch | tri_ser_rlmreg_p__parameterized18 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized18_1061 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | udec_interrupt_latch | tri_rlmlatch_p_1056 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | udec_latch_gen.udec_latch | tri_ser_rlmreg_p__parameterized10_1057 | 74 | 74 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized10 | 74 | 74 | 0 | 0 | 32 | 0 | 0 | 0 | | wdog_interrupt_latch | tri_rlmlatch_p_1058 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | wdog_tb_tap_latch | tri_rlmlatch_p_1059 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xucr1_latch | tri_ser_rlmreg_p__parameterized18_1060 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized18 | 2 | 2 | 0 | 0 | 5 | 0 | 0 | 0 | | xu_spr_aspr | tri_64x72_1r1w | 2 | 2 | 0 | 0 | 76 | 1 | 0 | 0 | | xu_spr_cspr | xu_spr_cspr | 1719 | 1719 | 0 | 0 | 808 | 0 | 0 | 0 | | bx_quiesce_latch | tri_rlmreg_p__parameterized37_856 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ccr0_latch | tri_ser_rlmreg_p__parameterized16 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized16 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ccr0_we_latch | tri_ser_rlmreg_p__parameterized4 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4_972 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ccr1_latch | tri_ser_rlmreg_p__parameterized22 | 5 | 5 | 0 | 0 | 24 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized22 | 5 | 5 | 0 | 0 | 24 | 0 | 0 | 0 | | ccr2_latch | tri_ser_rlmreg_p__parameterized23 | 5 | 5 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized23 | 5 | 5 | 0 | 0 | 32 | 0 | 0 | 0 | | ccr4_latch | tri_ser_rlmreg_p__parameterized4_857 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized4 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cdbell_interrupt_latch | tri_rlmreg_p__parameterized37_858 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cdbell_present_latch | tri_rlmreg_p__parameterized37_859 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cpl_cdbell_taken_latch | tri_rlmreg_p__parameterized37_860 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cpl_dbell_taken_latch | tri_rlmreg_p__parameterized37_861 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cpl_gcdbell_taken_latch | tri_rlmreg_p__parameterized37_862 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cpl_gdbell_taken_latch | tri_rlmreg_p__parameterized37_863 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | cpl_gmcdbell_taken_latch | tri_rlmreg_p__parameterized37_864 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dbell_interrupt_latch | tri_rlmreg_p__parameterized37_865 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | dbell_present_latch | tri_rlmreg_p__parameterized37_866 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | dec_dbg_dis_latch | tri_rlmreg_p__parameterized37_867 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_val_latch | tri_rlmreg_p__parameterized37_868 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ifar_latch | tri_rlmreg_p__parameterized250 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | ex1_instr_latch | tri_rlmreg_p__parameterized17_869 | 98 | 98 | 0 | 0 | 31 | 0 | 0 | 0 | | ex1_msr_gs_latch | tri_rlmlatch_p_870 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_val_latch | tri_rlmreg_p__parameterized37_871 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_aspr_addr_latch | tri_rlmreg_p__parameterized9_872 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_aspr_re_latch | tri_regk__parameterized6 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ccr0_we_latch | tri_regk__parameterized2 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dnh_latch | tri_rlmlatch_p_873 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_hypv_instr_latch | tri_regk__parameterized2_874 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ifar_latch | tri_rlmreg_p__parameterized250_875 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex2_instr_latch | tri_regk__parameterized5 | 359 | 359 | 0 | 0 | 10 | 0 | 0 | 0 | | ex2_is_mfspr_latch | tri_regk__parameterized2_876 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mftb_latch | tri_regk__parameterized2_877 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_msgclr_latch | tri_regk__parameterized2_878 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtmsr_latch | tri_regk__parameterized2_879 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtspr_latch | tri_regk__parameterized2_880 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_wait_latch | tri_regk__parameterized2_881 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_msr_gs_latch | tri_regk__parameterized2_882 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_priv_instr_latch | tri_regk__parameterized2_883 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tenc_we_latch | tri_regk__parameterized2_884 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_val_latch | tri_rlmreg_p__parameterized37_885 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_val_rd_latch | tri_rlmlatch_p_886 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_val_wr_latch | tri_rlmlatch_p_887 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_wait_wc_latch | tri_regk__parameterized4 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_aspr_addr_latch | tri_rlmreg_p__parameterized9_888 | 1 | 1 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_aspr_ce_addr_latch | tri_rlmreg_p__parameterized9_889 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_aspr_rdata_latch | tri_rlmreg_p__parameterized245 | 201 | 201 | 0 | 0 | 72 | 0 | 0 | 0 | | ex3_aspr_re_latch | tri_rlmreg_p__parameterized2_890 | 6 | 6 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_aspr_we_latch | tri_rlmlatch_p_891 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cspr_rt_latch | tri_rlmreg_p__parameterized33_892 | 128 | 128 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_hypv_spr_latch | tri_rlmlatch_p_893 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_illeg_spr_latch | tri_rlmlatch_p_894 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_instr_latch | tri_rlmreg_p__parameterized247 | 34 | 34 | 0 | 0 | 10 | 0 | 0 | 0 | | ex3_is_msgclr_latch | tri_rlmlatch_p_895 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_mtspr_latch | tri_rlmlatch_p_896 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_np1_flush_latch | tri_rlmlatch_p_897 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_priv_spr_latch | tri_rlmlatch_p_898 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rt_latch | tri_rlmreg_p__parameterized245_899 | 140 | 140 | 0 | 0 | 72 | 0 | 0 | 0 | | ex3_spr_we_latch | tri_rlmlatch_p_900 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sspr_rd_val_latch | tri_rlmlatch_p_901 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sspr_wr_val_latch | tri_rlmlatch_p_902 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_val_latch | tri_rlmreg_p__parameterized37_903 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_val_rd_latch | tri_rlmlatch_p_904 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wait_flush_latch | tri_rlmlatch_p_905 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wait_latch | tri_rlmlatch_p_906 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_wait_wc_latch | tri_rlmreg_p__parameterized246 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_aspr_ce_addr_latch | tri_regk | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_aspr_re_latch | tri_rlmreg_p__parameterized2_907 | 77 | 77 | 0 | 0 | 2 | 0 | 0 | 0 | | ex4_corr_rdata_latch | tri_rlmreg_p__parameterized33_908 | 40 | 40 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_hypv_spr_latch | tri_regk__parameterized2_909 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_illeg_spr_latch | tri_regk__parameterized2_910 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_np1_flush_latch | tri_regk__parameterized2_911 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_priv_spr_latch | tri_regk__parameterized2_912 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_spr_rt_latch | tri_rlmreg_p__parameterized33_913 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_sprg_ce_latch | tri_regk__parameterized7 | 129 | 129 | 0 | 0 | 9 | 0 | 0 | 0 | | ex4_sprg_ue_latch | tri_regk__parameterized2_914 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_sspr_val_latch | tri_rlmlatch_p_915 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_val_latch | tri_rlmreg_p__parameterized37_916 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_wait_flush_latch | tri_rlmlatch_p_917 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_sprg_ce_latch | tri_rlmreg_p__parameterized37_918 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_sprg_ue_latch | tri_rlmreg_p__parameterized37_919 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ext_dbg_dis_latch | tri_rlmreg_p__parameterized37_920 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized244 | 9 | 9 | 0 | 0 | 5 | 0 | 0 | 0 | | flush_latch | tri_rlmreg_p__parameterized37_921 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | gcdbell_interrupt_latch | tri_rlmreg_p__parameterized37_922 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gcdbell_present_latch | tri_rlmreg_p__parameterized37_923 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gdbell_interrupt_latch | tri_rlmreg_p__parameterized37_924 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | gdbell_present_latch | tri_rlmreg_p__parameterized37_925 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | gmcdbell_interrupt_latch | tri_rlmreg_p__parameterized37_926 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | gmcdbell_present_latch | tri_rlmreg_p__parameterized37_927 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | inj_sprg_ecc_latch | tri_rlmreg_p__parameterized37_928 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | instr_trace_mode_latch | tri_rlmlatch_p_929 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_icache_quiesce_latch | tri_rlmreg_p__parameterized37_930 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_quiesce_latch | tri_rlmreg_p__parameterized37_931 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_run_thread_latch | tri_rlmreg_p__parameterized37_932 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | llpri_latch | tri_rlmreg_p__parameterized42 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_dbell_brdcast_latch | tri_rlmlatch_p_933 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_dbell_lpid_match_latch | tri_rlmlatch_p_934 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lq_xu_dbell_pirtag_latch | tri_rlmreg_p__parameterized249 | 20 | 20 | 0 | 0 | 14 | 0 | 0 | 0 | | lq_xu_dbell_type_latch | tri_rlmreg_p__parameterized4_935 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | lq_xu_dbell_val_latch | tri_rlmlatch_p_936 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | lsu_quiesce_latch | tri_rlmreg_p__parameterized37_937 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mm_quiesce_latch | tri_rlmreg_p__parameterized37_938 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msrovride_enab_2_latch | tri_rlmreg_p__parameterized37_939 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msrovride_enab_3_latch | tri_rlmreg_p__parameterized37_940 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | msrovride_enab_latch | tri_rlmlatch_p_941 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | pc_xu_pm_hold_thread_latch | tri_rlmlatch_p_942 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | power_savings_on_latch | tri_rlmlatch_p_943 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | quiesce_latch | tri_rlmreg_p__parameterized37_944 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | quiesced_fctr | xu_fctr | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | threads_gen[0].delay_latch | tri_rlmreg_p__parameterized9_971 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | quiesced_latch | tri_rlmreg_p__parameterized37_945 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ram_active_latch | tri_rlmreg_p__parameterized37_946 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | running_latch | tri_rlmreg_p__parameterized37_947 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | set_xucr0_clo_latch | tri_rlmlatch_p_948 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | set_xucr0_cslc_latch | tri_rlmlatch_p_949 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | set_xucr0_cul_latch | tri_rlmlatch_p_950 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xu_ord_read_done_latch | tri_rlmlatch_p_951 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_xu_ord_write_done_latch | tri_rlmlatch_p_952 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tb_act_latch | tri_rlmlatch_p_953 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tb_dbg_dis_latch | tri_rlmlatch_p_954 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | tb_update_enable_latch | tri_rlmlatch_p_955 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tb_update_pulse_1_latch | tri_rlmlatch_p_956 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tb_update_pulse_latch | tri_rlmlatch_p_957 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | tbl_latch | tri_ser_rlmreg_p__parameterized6 | 71 | 71 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_970 | 71 | 71 | 0 | 0 | 32 | 0 | 0 | 0 | | tbu_latch | tri_ser_rlmreg_p__parameterized6_958 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_969 | 64 | 64 | 0 | 0 | 32 | 0 | 0 | 0 | | tens_latch | tri_ser_rlmreg_p__parameterized24 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized24 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | timer_div_latch | tri_rlmreg_p__parameterized4_959 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | timer_update_latch | tri_rlmlatch_p_960 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | waitimpl_val_latch | tri_rlmreg_p__parameterized37_961 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | waitrsv_val_latch | tri_rlmreg_p__parameterized37_962 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xesr1_latch | tri_ser_rlmreg_p__parameterized6_963 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6_968 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xesr2_latch | tri_ser_rlmreg_p__parameterized6_964 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized6 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | xu_spr_ord_ready_latch | tri_rlmlatch_p_965 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_spr_rd_eccgen | tri_eccgen | 50 | 50 | 0 | 0 | 0 | 0 | 0 | 0 | | xu_spr_wr_eccgen | tri_eccgen_966 | 47 | 47 | 0 | 0 | 0 | 0 | 0 | 0 | | xucr0_clfc_latch | tri_rlmlatch_p_967 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xucr0_latch | tri_ser_rlmreg_p__parameterized25 | 70 | 70 | 0 | 0 | 25 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized25 | 70 | 70 | 0 | 0 | 25 | 0 | 0 | 0 | | xucr4_latch | tri_ser_rlmreg_p__parameterized14 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | tri_ser_rlmreg_p | tri_aoi22_nlats_wlcb__parameterized14 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | xer | xu_rf__parameterized0 | 524 | 524 | 0 | 0 | 201 | 0 | 0 | 0 | | entry[0].reg_latch | tri_regk__parameterized0 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[10].reg_latch | tri_regk__parameterized0_826 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[11].reg_latch | tri_regk__parameterized0_827 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[1].reg_latch | tri_regk__parameterized0_828 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[2].reg_latch | tri_regk__parameterized0_829 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[3].reg_latch | tri_regk__parameterized0_830 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[4].reg_latch | tri_regk__parameterized0_831 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[5].reg_latch | tri_regk__parameterized0_832 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[6].reg_latch | tri_regk__parameterized0_833 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[7].reg_latch | tri_regk__parameterized0_834 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[8].reg_latch | tri_regk__parameterized0_835 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | entry[9].reg_latch | tri_regk__parameterized0_836 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | r0a_latch | tri_rlmreg_p__parameterized9_837 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | | r0d_latch | tri_rlmreg_p__parameterized6_838 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | r0e_latch | tri_rlmlatch_p_839 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r1_gen1.r1a_latch | tri_rlmreg_p__parameterized9_840 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | | r1_gen1.r1d_latch | tri_rlmreg_p__parameterized6_841 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | r1_gen1.r1e_latch | tri_rlmlatch_p_842 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r2_gen1.r2a_latch | tri_rlmreg_p__parameterized9_843 | 69 | 69 | 0 | 0 | 4 | 0 | 0 | 0 | | r2_gen1.r2d_latch | tri_rlmreg_p__parameterized6_844 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | r2_gen1.r2e_latch | tri_rlmlatch_p_845 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r3_gen1.r3a_latch | tri_rlmreg_p__parameterized9_846 | 15 | 15 | 0 | 0 | 4 | 0 | 0 | 0 | | r3_gen1.r3d_latch | tri_rlmreg_p__parameterized6_847 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | r3_gen1.r3e_latch | tri_rlmlatch_p_848 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | w0a_latch | tri_rlmreg_p__parameterized9_849 | 264 | 264 | 0 | 0 | 4 | 0 | 0 | 0 | | w0d_latch | tri_rlmreg_p__parameterized6_850 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | w0e_latch | tri_rlmlatch_p_851 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | w1_gen1.w1a_latch | tri_rlmreg_p__parameterized9_852 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | w1_gen1.w1d_latch | tri_rlmreg_p__parameterized6_853 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | w1_gen1.w1e_latch | tri_rlmlatch_p_854 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu0 | xu0 | 13805 | 13805 | 0 | 0 | 5373 | 0 | 0 | 0 | | (xu0) | xu0 | 473 | 473 | 0 | 0 | 0 | 0 | 0 | 0 | | alu | xu_alu_167 | 1239 | 1239 | 0 | 0 | 295 | 0 | 0 | 0 | | add | xu_alu_add_760 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_rs0_inv_b_latch | tri_inv_nlats_825 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | cmp | xu_alu_cmp_761 | 12 | 12 | 0 | 0 | 13 | 0 | 0 | 0 | | ex2_msb_64b_sel_latch | tri_rlmlatch_p_816 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_diff_sign_latch | tri_rlmlatch_p_817 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_instr_latch | tri_rlmreg_p__parameterized4_818 | 4 | 4 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_msb_64b_sel_latch | tri_rlmlatch_p_819 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs1_trm1_latch | tri_rlmlatch_p_820 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs2_trm1_latch | tri_rlmlatch_p_821 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_cmp_latch | tri_rlmlatch_p_822 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_cmpl_latch | tri_rlmlatch_p_823 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_trap_latch | tri_rlmlatch_p_824 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_act_latch | tri_rlmlatch_p_762 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_instr_6to10_latch | tri_rlmreg_p__parameterized4_763 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_msb_64b_sel_latch | tri_rlmlatch_p_764 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_cmp_latch | tri_rlmlatch_p_765 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_cmpl_latch | tri_rlmlatch_p_766 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_isel_latch | tri_rlmlatch_p_767 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_trap_latch | tri_rlmlatch_p_768 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ca_en_latch | tri_rlmlatch_p_769 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ov_en_latch | tri_rlmlatch_p_770 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_add_ca_latch | tri_rlmlatch_p_771 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_add_ovf_latch | tri_rlmlatch_p_772 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_rot_log_latch | tri_rlmlatch_p_773 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_ca_en_latch | tri_rlmlatch_p_774 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_latch | tri_rlmreg_p__parameterized6_775 | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 | | ex3_xer_ov_en_latch | tri_rlmlatch_p_776 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rot | tri_st_rot_777 | 1213 | 1213 | 0 | 0 | 250 | 0 | 0 | 0 | | (rot) | tri_st_rot_777 | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | | ex2_act_latch | tri_rlmlatch_p_778 | 32 | 32 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_chk_shov_dw_latch | tri_rlmlatch_p_779 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_chk_shov_wd_latch | tri_rlmlatch_p_780 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cmp_byte_latch | tri_rlmlatch_p_781 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ins_prtyd_latch | tri_rlmlatch_p_782 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ins_prtyw_latch | tri_rlmlatch_p_783 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_log_fcn_latch | tri_rlmreg_p__parameterized9_784 | 148 | 148 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_mb_gt_me_latch | tri_rlmlatch_p_785 | 162 | 162 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mb_ins_latch | tri_rlmreg_p__parameterized0_786 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_me_ins_b_latch | tri_rlmreg_p__parameterized0_787 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_sel_rot_log_latch | tri_rlmlatch_p_788 | 77 | 77 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_byte_latch | tri_rlmlatch_p_789 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_half_latch | tri_rlmlatch_p_790 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_wd_latch | tri_rlmlatch_p_791 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sh_amt_latch | tri_rlmreg_p__parameterized0_792 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_sh_right_latch | tri_rlmreg_p__parameterized5_793 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_sh_word_latch | tri_rlmreg_p__parameterized2_794 | 295 | 295 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_sra_dw_latch | tri_rlmlatch_p_795 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sra_wd_latch | tri_rlmlatch_p_796 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_ins_hi_latch | tri_rlmlatch_p_797 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_ins_lo_latch | tri_rlmlatch_p_798 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_rb_hi_latch | tri_rlmlatch_p_799 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_rb_lo_latch | tri_rlmlatch_p_800 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_ins_hi_latch | tri_rlmlatch_p_801 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_ins_lo_latch | tri_rlmlatch_p_802 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_rb_hi_latch | tri_rlmlatch_p_803 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_rb_lo_latch | tri_rlmlatch_p_804 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_rb_amt_hi_latch | tri_rlmlatch_p_805 | 292 | 292 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_rb_amt_lo_latch | tri_rlmlatch_p_806 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_sh_amt_hi_latch | tri_rlmlatch_p_807 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_sh_amt_lo_latch | tri_rlmlatch_p_808 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_zm_ins_latch | tri_rlmlatch_p_809 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sh_word_latch | tri_rlmlatch_p_810 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sra_se_latch | tri_rlmreg_p__parameterized37_811 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msk_lat | tri_inv_nlats_812 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | or3232 | tri_st_or3232_b_813 | 32 | 32 | 0 | 0 | 0 | 0 | 0 | 0 | | res_lat | tri_inv_nlats__parameterized0_814 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | rot_lat | tri_inv_nlats_815 | 2 | 2 | 0 | 0 | 64 | 0 | 0 | 0 | | bcd | xu0_bcd | 211 | 211 | 0 | 0 | 60 | 0 | 0 | 0 | | ex2_is_addg6s_latch | tri_rlmlatch_p_755 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_cdtbcd_latch | tri_rlmlatch_p_756 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_val_latch | tri_rlmlatch_p_757 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_bcd_rt_latch | tri_rlmreg_p__parameterized33_758 | 189 | 189 | 0 | 0 | 56 | 0 | 0 | 0 | | ex3_val_latch | tri_rlmlatch_p_759 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | br | xu0_br | 1448 | 1448 | 0 | 0 | 974 | 0 | 0 | 0 | | ex0_vld_latch | tri_rlmreg_p__parameterized37_643 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_bta_val_latch | tri_rlmlatch_p_644 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_fusion_latch | tri_rlmlatch_p_645 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_gshare_latch | tri_rlmreg_p__parameterized14 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | ex1_ifar_latch | tri_rlmreg_p__parameterized8 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex1_instr_latch | tri_rlmreg_p__parameterized17_646 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13_647 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_ls_ptr_latch | tri_rlmreg_p__parameterized5_648 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_pred_bta_latch | tri_rlmreg_p__parameterized8_649 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex1_pred_latch | tri_rlmlatch_p_650 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_vld_latch | tri_rlmreg_p__parameterized37_651 | 100 | 100 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_bta_val_latch | tri_rlmlatch_p_652 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_fusion_latch | tri_rlmlatch_p_653 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_gshare_latch | tri_rlmreg_p__parameterized14_654 | 18 | 18 | 0 | 0 | 18 | 0 | 0 | 0 | | ex2_ifar_latch | tri_rlmreg_p__parameterized8_655 | 22 | 22 | 0 | 0 | 20 | 0 | 0 | 0 | | ex2_instr_latch | tri_rlmreg_p__parameterized17_656 | 175 | 175 | 0 | 0 | 32 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_657 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_ls_ptr_latch | tri_rlmreg_p__parameterized5_658 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_pred_bta_latch | tri_rlmreg_p__parameterized8_659 | 20 | 20 | 0 | 0 | 20 | 0 | 0 | 0 | | ex2_pred_latch | tri_rlmlatch_p_660 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_slow_latch | tri_rlmlatch_p_661 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_vld_latch | tri_rlmreg_p__parameterized37_662 | 284 | 284 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_bta_latch | tri_rlmreg_p__parameterized40 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex3_bta_val_latch | tri_rlmlatch_p_663 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cr1_latch | tri_rlmreg_p__parameterized9_664 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_cr2_latch | tri_rlmreg_p__parameterized9_665 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_cr3_latch | tri_rlmreg_p__parameterized9_666 | 9 | 9 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_ctr_latch | tri_rlmreg_p__parameterized33_667 | 257 | 257 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_fusion_latch | tri_rlmlatch_p_668 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_gshare_latch | tri_rlmreg_p__parameterized14_669 | 32 | 32 | 0 | 0 | 18 | 0 | 0 | 0 | | ex3_ifar_latch | tri_rlmreg_p__parameterized8_670 | 5 | 5 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_instr_latch | tri_rlmreg_p__parameterized48 | 41 | 41 | 0 | 0 | 26 | 0 | 0 | 0 | | ex3_is_b_latch | tri_rlmlatch_p_671 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_bc_latch | tri_rlmlatch_p_672 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_bcctr_latch | tri_rlmlatch_p_673 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_bclr_latch | tri_rlmlatch_p_674 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_bctar_latch | tri_rlmlatch_p_675 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crand_latch | tri_rlmlatch_p_676 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crandc_latch | tri_rlmlatch_p_677 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_creqv_latch | tri_rlmlatch_p_678 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crnand_latch | tri_rlmlatch_p_679 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crnor_latch | tri_rlmlatch_p_680 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_cror_latch | tri_rlmlatch_p_681 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crorc_latch | tri_rlmlatch_p_682 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_crxor_latch | tri_rlmlatch_p_683 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_mcrf_latch | tri_rlmlatch_p_684 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_itag_latch | tri_rlmreg_p__parameterized13_685 | 11 | 11 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_lr1_latch | tri_rlmreg_p__parameterized33_686 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex3_lr2_latch | tri_rlmreg_p__parameterized33_687 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex3_ls_ptr_latch | tri_rlmreg_p__parameterized5_688 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_nia_latch | tri_rlmreg_p__parameterized40_689 | 144 | 144 | 0 | 0 | 62 | 0 | 0 | 0 | | ex3_pred_bta_latch | tri_rlmreg_p__parameterized8_690 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex3_pred_latch | tri_rlmlatch_p_691 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_slow_latch | tri_rlmlatch_p_692 | 203 | 203 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_vld_latch | tri_rlmreg_p__parameterized37_693 | 87 | 87 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_bta_latch | tri_rlmreg_p__parameterized40_694 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex4_cr_wd_latch | tri_rlmreg_p__parameterized9_695 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_cr_we_latch | tri_rlmlatch_p_696 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ctr_wd_latch | tri_rlmreg_p__parameterized33_697 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_ctr_we_latch | tri_rlmlatch_p_698 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_gshare_latch | tri_rlmreg_p__parameterized14_699 | 0 | 0 | 0 | 0 | 18 | 0 | 0 | 0 | | ex4_itag_latch | tri_rlmreg_p__parameterized13_700 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_itag_saved_val_latch | tri_rlmreg_p__parameterized37_701 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_lr_wd_latch | tri_rlmreg_p__parameterized33_702 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex4_lr_we_latch | tri_rlmlatch_p_703 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ls_data_latch | tri_rlmreg_p__parameterized8_704 | 0 | 0 | 0 | 0 | 20 | 0 | 0 | 0 | | ex4_ls_ptr_latch | tri_rlmreg_p__parameterized5_705 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_ls_update_latch | tri_rlmlatch_p_706 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_redirect_latch | tri_rlmreg_p__parameterized37_707 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_slow_latch | tri_rlmlatch_p_708 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_taken_latch | tri_rlmlatch_p_709 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_vld_latch | tri_rlmreg_p__parameterized37_710 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_br_flush_latch | tri_rlmreg_p__parameterized37_711 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_cm_latch | tri_rlmreg_p__parameterized37_712 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].ex4_itag_saved_latch | tri_rlmreg_p__parameterized13_713 | 3 | 3 | 0 | 0 | 7 | 0 | 0 | 0 | | xhdl5.thread_regs[0].iu_br_flush_ifar_latch | tri_rlmreg_p__parameterized219 | 10 | 10 | 0 | 0 | 42 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[0].br_upper_ifar_latch | tri_rlmlatch_p_714 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[10].br_upper_ifar_latch | tri_rlmlatch_p_715 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[11].br_upper_ifar_latch | tri_rlmlatch_p_716 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[12].br_upper_ifar_latch | tri_rlmlatch_p_717 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[13].br_upper_ifar_latch | tri_rlmlatch_p_718 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[14].br_upper_ifar_latch | tri_rlmlatch_p_719 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[15].br_upper_ifar_latch | tri_rlmlatch_p_720 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[16].br_upper_ifar_latch | tri_rlmlatch_p_721 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[17].br_upper_ifar_latch | tri_rlmlatch_p_722 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[18].br_upper_ifar_latch | tri_rlmlatch_p_723 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[19].br_upper_ifar_latch | tri_rlmlatch_p_724 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[1].br_upper_ifar_latch | tri_rlmlatch_p_725 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[20].br_upper_ifar_latch | tri_rlmlatch_p_726 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[21].br_upper_ifar_latch | tri_rlmlatch_p_727 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[22].br_upper_ifar_latch | tri_rlmlatch_p_728 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[23].br_upper_ifar_latch | tri_rlmlatch_p_729 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[24].br_upper_ifar_latch | tri_rlmlatch_p_730 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[25].br_upper_ifar_latch | tri_rlmlatch_p_731 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[26].br_upper_ifar_latch | tri_rlmlatch_p_732 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[27].br_upper_ifar_latch | tri_rlmlatch_p_733 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[28].br_upper_ifar_latch | tri_rlmlatch_p_734 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[29].br_upper_ifar_latch | tri_rlmlatch_p_735 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[2].br_upper_ifar_latch | tri_rlmlatch_p_736 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[30].br_upper_ifar_latch | tri_rlmlatch_p_737 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[31].br_upper_ifar_latch | tri_rlmlatch_p_738 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[32].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[33].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_739 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[34].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_740 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[35].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_741 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[36].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_742 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[37].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_743 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[38].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_744 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[39].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_745 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[3].br_upper_ifar_latch | tri_rlmlatch_p_746 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[40].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_747 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[41].br_upper_ifar_latch | tri_rlmlatch_p__parameterized1_748 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[4].br_upper_ifar_latch | tri_rlmlatch_p_749 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[5].br_upper_ifar_latch | tri_rlmlatch_p_750 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[6].br_upper_ifar_latch | tri_rlmlatch_p_751 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[7].br_upper_ifar_latch | tri_rlmlatch_p_752 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[8].br_upper_ifar_latch | tri_rlmlatch_p_753 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xhdl5.thread_regs[0].q_depth_gen[9].br_upper_ifar_latch | tri_rlmlatch_p_754 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | byp | xu0_byp | 4556 | 4556 | 0 | 0 | 1951 | 0 | 0 | 0 | | ex1_abt_s1_lq_sel_latch | tri_rlmlatch_p_503 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_abt_s1_xu0_sel_latch | tri_rlmreg_p__parameterized224_504 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s1_xu1_sel_latch | tri_rlmreg_p__parameterized223_505 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_abt_s2_lq_sel_latch | tri_rlmlatch_p_506 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_abt_s2_xu0_sel_latch | tri_rlmreg_p__parameterized224_507 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s2_xu1_sel_latch | tri_rlmreg_p__parameterized223_508 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_abt_s3_lq_sel_latch | tri_rlmreg_p__parameterized222_509 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_abt_s3_xu0_sel_latch | tri_rlmreg_p__parameterized224_510 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s3_xu1_sel_latch | tri_rlmreg_p__parameterized223_511 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[5].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_512 | 30 | 30 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[6].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_513 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[7].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_514 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[8].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_515 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_reg_sel_latch | tri_rlmreg_p__parameterized12_516 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_rel_sel_gen.ex1_gpr_s1_rel_sel_entry[3].ex1_gpr_s1_rel_sel_latch | tri_rlmreg_p__parameterized12_517 | 19 | 19 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_rel_sel_gen.ex1_gpr_s1_rel_sel_entry[4].ex1_gpr_s1_rel_sel_latch | tri_rlmreg_p__parameterized12_518 | 25 | 25 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[2].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_519 | 45 | 45 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[3].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_520 | 126 | 126 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[4].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_521 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[5].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_522 | 29 | 29 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[6].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_523 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[7].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_524 | 25 | 25 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[8].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_525 | 21 | 21 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[2].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_526 | 33 | 33 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[3].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_527 | 26 | 26 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[4].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_528 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[5].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_529 | 19 | 19 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_imm_sel_latch | tri_rlmreg_p__parameterized12_530 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[5].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_531 | 29 | 29 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[6].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_532 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[7].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_533 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[8].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_534 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_reg_sel_latch | tri_rlmreg_p__parameterized12_535 | 13 | 13 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_rel_sel_gen.ex1_gpr_s2_rel_sel_entry[3].ex1_gpr_s2_rel_sel_latch | tri_rlmreg_p__parameterized12_536 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_rel_sel_gen.ex1_gpr_s2_rel_sel_entry[4].ex1_gpr_s2_rel_sel_latch | tri_rlmreg_p__parameterized12_537 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[2].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_538 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[3].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_539 | 109 | 109 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[4].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_540 | 22 | 22 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[5].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_541 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[6].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_542 | 21 | 21 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[7].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_543 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[8].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_544 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[2].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_545 | 14 | 14 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[3].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_546 | 18 | 18 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[4].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_547 | 7 | 7 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[5].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_548 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_s1_v_latch | tri_rlmlatch_p_549 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s2_v_latch | tri_rlmlatch_p_550 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s3_v_latch | tri_rlmlatch_p_551 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s1_lq_sel_gen.ex1_spr_s1_lq_sel_entry[5].ex1_spr_s1_lq_sel_latch | tri_rlmreg_p__parameterized37_552 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s1_lq_sel_gen.ex1_spr_s1_lq_sel_entry[6].ex1_spr_s1_lq_sel_latch | tri_rlmreg_p__parameterized37_553 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s1_reg_sel_latch | tri_rlmreg_p__parameterized5_554 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_spr_s1_xu0_sel_gen.ex1_spr_s1_xu0_sel_entry[3].ex1_spr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized5_555 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_spr_s1_xu0_sel_gen.ex1_spr_s1_xu0_sel_entry[4].ex1_spr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized5_556 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_spr_s1_xu0_sel_gen.ex1_spr_s1_xu0_sel_entry[5].ex1_spr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized5_557 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_spr_s1_xu0_sel_gen.ex1_spr_s1_xu0_sel_entry[6].ex1_spr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized5_558 | 139 | 139 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_spr_s1_xu1_sel_gen.ex1_spr_s1_xu1_sel_entry[3].ex1_spr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized37_559 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s2_lq_sel_gen.ex1_spr_s2_lq_sel_entry[5].ex1_spr_s2_lq_sel_latch | tri_rlmreg_p__parameterized37_560 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s2_lq_sel_gen.ex1_spr_s2_lq_sel_entry[6].ex1_spr_s2_lq_sel_latch | tri_rlmreg_p__parameterized37_561 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s2_reg_sel_latch | tri_rlmreg_p__parameterized0_562 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_spr_s2_xu0_sel_gen.ex1_spr_s2_xu0_sel_entry[3].ex1_spr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized0_563 | 22 | 22 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_spr_s2_xu0_sel_gen.ex1_spr_s2_xu0_sel_entry[4].ex1_spr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized0_564 | 9 | 9 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_spr_s2_xu0_sel_gen.ex1_spr_s2_xu0_sel_entry[5].ex1_spr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized0_565 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_spr_s2_xu0_sel_gen.ex1_spr_s2_xu0_sel_entry[6].ex1_spr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized0_566 | 260 | 260 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_spr_s2_xu1_sel_gen.ex1_spr_s2_xu1_sel_entry[3].ex1_spr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized2_567 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_lq_sel_gen.ex1_spr_s3_lq_sel_entry[5].ex1_spr_s3_lq_sel_latch | tri_rlmreg_p__parameterized37_568 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_lq_sel_gen.ex1_spr_s3_lq_sel_entry[6].ex1_spr_s3_lq_sel_latch | tri_rlmreg_p__parameterized37_569 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_reg_sel_latch | tri_rlmreg_p__parameterized2_570 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[3].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_571 | 26 | 26 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[4].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_572 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[5].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_573 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[6].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_574 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[7].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_575 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[8].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized2_576 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[3].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized2_577 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[4].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized2_578 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[5].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized2_579 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cr1_latch | tri_rlmreg_p__parameterized9_580 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_cr2_latch | tri_rlmreg_p__parameterized9_581 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_cr3_latch | tri_rlmreg_p__parameterized9_582 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_cr_bit_latch | tri_rlmlatch_p_583 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cr_sel_latch | tri_rlmreg_p__parameterized225 | 68 | 68 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ctr2_latch | tri_rlmreg_p__parameterized33_584 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_is_mfcr_latch | tri_rlmreg_p__parameterized12_585 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_is_mfcr_sel_latch | tri_rlmlatch_p_586 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mfctr_latch | tri_rlmlatch_p_587 | 67 | 67 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mflr_latch | tri_rlmlatch_p_588 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mfxer_latch | tri_rlmlatch_p_589 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtcr_latch | tri_rlmreg_p__parameterized12_590 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_is_mtxer_latch | tri_rlmlatch_p_591 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_lr1_latch | tri_rlmreg_p__parameterized33_592 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_lr2_latch | tri_rlmreg_p__parameterized33_593 | 0 | 0 | 0 | 0 | 62 | 0 | 0 | 0 | | ex2_ra_capt_latch | tri_rlmlatch_p_594 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs1_abort_latch | tri_rlmlatch_p_595 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs1_latch | tri_rlmreg_p__parameterized33_596 | 911 | 911 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_rs2_abort_latch | tri_rlmlatch_p_597 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs2_latch | tri_rlmreg_p__parameterized33_598 | 298 | 298 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_rs2_noimm_latch | tri_rlmreg_p__parameterized226 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_rs3_abort_latch | tri_rlmlatch_p_599 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs_capt_latch | tri_rlmlatch_p_600 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer2_latch | tri_rlmreg_p__parameterized6_601 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | ex2_xer3_latch | tri_rlmreg_p__parameterized6_602 | 5 | 5 | 0 | 0 | 10 | 0 | 0 | 0 | | ex2_xer_sel_latch | tri_rlmreg_p__parameterized225_603 | 10 | 10 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_cnt_rt_latch | tri_rlmreg_p__parameterized228 | 10 | 10 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_dlm_cr_latch | tri_rlmreg_p__parameterized9_604 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_dlm_rt_latch | tri_rlmreg_p__parameterized230 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_dlm_xer_latch | tri_rlmreg_p__parameterized6_605 | 15 | 15 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_is_mtxer_latch | tri_rlmlatch_p_606 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mfspr_rt_latch | tri_rlmreg_p__parameterized33_607 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_mfspr_sel_latch | tri_rlmlatch_p_608 | 60 | 60 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mtcr_latch | tri_rlmreg_p__parameterized9_609 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_mtcr_sel_latch | tri_rlmlatch_p_610 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_prm_rt_latch | tri_rlmreg_p__parameterized229 | 9 | 9 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_ra_capt_latch | tri_rlmlatch_p_611 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs1_latch | tri_rlmreg_p__parameterized33_612 | 3 | 3 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_xer3_latch | tri_rlmlatch_p_613 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ra_capt_latch | tri_rlmlatch_p_614 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xu0_cr_latch | tri_rlmreg_p__parameterized9_615 | 7 | 7 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_xu0_ctr_latch | tri_rlmreg_p__parameterized33_616 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_xu0_lr_latch | tri_rlmreg_p__parameterized33_617 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_xu0_rt_latch | tri_rlmreg_p__parameterized33_618 | 197 | 197 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_xu0_xer_latch | tri_rlmreg_p__parameterized6_619 | 18 | 18 | 0 | 0 | 10 | 0 | 0 | 0 | | ex5_xu0_cr_latch | tri_rlmreg_p__parameterized9_620 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_xu0_rt_latch | tri_rlmreg_p__parameterized33_621 | 85 | 85 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_xu0_xer_latch | tri_rlmreg_p__parameterized6_622 | 4 | 4 | 0 | 0 | 10 | 0 | 0 | 0 | | ex6_lq_cr_latch | tri_rlmreg_p__parameterized9_623 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_lq_rt_latch | tri_rlmreg_p__parameterized33_624 | 124 | 124 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_mul_abort_latch | tri_rlmlatch_p_625 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_mul_done_latch | tri_rlmreg_p__parameterized46 | 199 | 199 | 0 | 0 | 9 | 0 | 0 | 0 | | ex6_mul_ord_done_latch | tri_rlmlatch_p_626 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xu0_cr_latch | tri_rlmreg_p__parameterized9_627 | 3 | 3 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_xu0_rt_latch | tri_rlmreg_p__parameterized33_628 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_xu0_xer_latch | tri_rlmreg_p__parameterized6_629 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | ex7_lq_rt_latch | tri_rlmreg_p__parameterized33_630 | 117 | 117 | 0 | 0 | 64 | 0 | 0 | 0 | | ex7_xu0_rt_latch | tri_rlmreg_p__parameterized33_631 | 125 | 125 | 0 | 0 | 64 | 0 | 0 | 0 | | ex8_lq_rt_latch | tri_rlmreg_p__parameterized33_632 | 45 | 45 | 0 | 0 | 64 | 0 | 0 | 0 | | ex8_xu0_rt_latch | tri_rlmreg_p__parameterized33_633 | 68 | 68 | 0 | 0 | 64 | 0 | 0 | 0 | | exx_lq_abort_latch | tri_rlmreg_p__parameterized233_634 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | exx_lq_act_latch | tri_rlmreg_p__parameterized221 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | exx_rel3_act_latch | tri_rlmlatch_p_635 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_rel3_rt_latch | tri_rlmreg_p__parameterized33_636 | 98 | 98 | 0 | 0 | 64 | 0 | 0 | 0 | | exx_rel4_rt_latch | tri_rlmreg_p__parameterized33_637 | 68 | 68 | 0 | 0 | 64 | 0 | 0 | 0 | | exx_xu0_abort_latch | tri_rlmreg_p__parameterized231 | 28 | 28 | 0 | 0 | 11 | 0 | 0 | 0 | | exx_xu0_act_latch | tri_rlmreg_p__parameterized220 | 384 | 384 | 0 | 0 | 10 | 0 | 0 | 0 | | exx_xu1_abort_latch | tri_rlmreg_p__parameterized232 | 4 | 4 | 0 | 0 | 5 | 0 | 0 | 0 | | mm_data_latch | tri_rlmreg_p__parameterized33_638 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | mm_ra_entry_latch | tri_rlmreg_p__parameterized227 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | mm_rs_is_latch | tri_rlmreg_p__parameterized46_639 | 8 | 8 | 0 | 0 | 8 | 0 | 0 | 0 | | ord_cr_data_latch | tri_rlmreg_p__parameterized9_640 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ord_rt_data_latch | tri_rlmreg_p__parameterized33_641 | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | ord_xer_data_latch | tri_rlmreg_p__parameterized6_642 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | dec | xu0_dec | 1565 | 1565 | 0 | 0 | 551 | 0 | 0 | 0 | | (dec) | xu0_dec | 10 | 10 | 0 | 0 | 0 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_296 | 28 | 28 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_val_latch | tri_rlmreg_p__parameterized37_297 | 168 | 168 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_instr_latch | tri_rlmreg_p__parameterized17_298 | 463 | 463 | 0 | 0 | 32 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13_299 | 21 | 21 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_ord_complete_latch | tri_rlmlatch_p_300 | 16 | 16 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ord_latch | tri_rlmlatch_p_301 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ord_val_latch | tri_rlmreg_p__parameterized37_302 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s2_t_latch | tri_rlmreg_p__parameterized5_303 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_s2_v_latch | tri_rlmlatch_p_304 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s3_t_latch | tri_rlmreg_p__parameterized5_305 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_s3_v_latch | tri_rlmlatch_p_306 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t1_p_latch | tri_rlmreg_p__parameterized0_307 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_t1_t_latch | tri_rlmreg_p__parameterized5_308 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_t1_v_latch | tri_rlmlatch_p_309 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t2_p_latch | tri_rlmreg_p__parameterized9_310 | 8 | 8 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_t2_t_latch | tri_rlmreg_p__parameterized5_311 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_t2_v_latch | tri_rlmlatch_p_312 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t3_p_latch | tri_rlmreg_p__parameterized4_313 | 10 | 10 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_t3_t_latch | tri_rlmreg_p__parameterized5_314 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_t3_v_latch | tri_rlmlatch_p_315 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ucode_latch | tri_rlmreg_p__parameterized5_316 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_val_latch | tri_rlmreg_p__parameterized37_317 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_add_ci_sel_latch | tri_rlmreg_p__parameterized2_318 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_any_cntlz_latch | tri_rlmlatch_p_319 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_any_popcnt_latch | tri_rlmlatch_p_320 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_flush2ucode_latch | tri_rlmlatch_p_321 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_hyp_priv_excep_latch | tri_rlmlatch_p_322 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_illegal_op_latch | tri_rlmlatch_p_323 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_instr_latch | tri_rlmreg_p__parameterized17_324 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ex2_is_bpermd_latch | tri_rlmlatch_p_325 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_dlmzb_latch | tri_rlmlatch_p_326 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_ehpriv_latch | tri_rlmlatch_p_327 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_erativax_latch | tri_rlmlatch_p_328 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtiar_latch | tri_rlmlatch_p_329 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_mtspr_latch | tri_rlmlatch_p_330 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_331 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_mul_2c_latch | tri_rlmlatch_p_332 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_3c_latch | tri_rlmlatch_p_333 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_4c_latch | tri_rlmlatch_p_334 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_multicyc_latch | tri_rlmlatch_p_335 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_complete_latch | tri_rlmlatch_p_336 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_eratilx_latch | tri_rlmlatch_p_337 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_erativax_latch | tri_rlmlatch_p_338 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_eratre_latch | tri_rlmlatch_p_339 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_eratsx_latch | tri_rlmlatch_p_340 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_eratwe_latch | tri_rlmlatch_p_341 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbilx_latch | tri_rlmlatch_p_342 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbivax_latch | tri_rlmlatch_p_343 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbre_latch | tri_rlmlatch_p_344 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbsrx_latch | tri_rlmlatch_p_345 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbsx_latch | tri_rlmlatch_p_346 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbsxr_latch | tri_rlmlatch_p_347 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_is_tlbwe_latch | tri_rlmlatch_p_348 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_itag_latch | tri_rlmreg_p__parameterized13_349 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_ord_tid_latch | tri_rlmreg_p__parameterized37_350 | 84 | 84 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ord_tlb_t_latch | tri_rlmreg_p__parameterized237 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_ord_tlb_ws_latch | tri_rlmreg_p__parameterized236 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_ord_val_latch | tri_rlmreg_p__parameterized37_351 | 8 | 8 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_priv_excep_latch | tri_rlmlatch_p_352 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_t1_p_latch | tri_rlmreg_p__parameterized0_353 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_t1_t_latch | tri_rlmreg_p__parameterized5_354 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_t1_v_latch | tri_rlmlatch_p_355 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_t2_p_latch | tri_rlmreg_p__parameterized9_356 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_t2_t_latch | tri_rlmreg_p__parameterized5_357 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_t2_v_latch | tri_rlmlatch_p_358 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_t3_p_latch | tri_rlmreg_p__parameterized4_359 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_t3_t_latch | tri_rlmreg_p__parameterized5_360 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_t3_v_latch | tri_rlmlatch_p_361 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_tlb_illeg_latch | tri_rlmlatch_p_362 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ucode_latch | tri_rlmreg_p__parameterized5_363 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_val_latch | tri_rlmreg_p__parameterized37_364 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_any_cntlz_latch | tri_rlmlatch_p_365 | 36 | 36 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_any_popcnt_latch | tri_rlmlatch_p_366 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_flush2ucode_latch | tri_rlmlatch_p_367 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_hyp_priv_excep_latch | tri_rlmlatch_p_368 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_illegal_op_latch | tri_rlmlatch_p_369 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_instr_latch | tri_rlmreg_p__parameterized17_370 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ex3_is_bpermd_latch | tri_rlmlatch_p_371 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_dlmzb_latch | tri_rlmlatch_p_372 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_ehpriv_latch | tri_rlmlatch_p_373 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_is_mtspr_latch | tri_rlmlatch_p_374 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_itag_latch | tri_rlmreg_p__parameterized13_375 | 14 | 14 | 0 | 0 | 7 | 0 | 0 | 0 | | ex3_mtiar_sel_latch | tri_rlmlatch_p_376 | 75 | 75 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_2c_latch | tri_rlmlatch_p_377 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_3c_latch | tri_rlmlatch_p_378 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_4c_latch | tri_rlmlatch_p_379 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_multicyc_latch | tri_rlmlatch_p_380 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ord_complete_latch | tri_rlmlatch_p_381 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_ord_val_latch | tri_rlmreg_p__parameterized37_382 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_priv_excep_latch | tri_rlmlatch_p_383 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_t1_p_latch | tri_rlmreg_p__parameterized0_384 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_t1_t_latch | tri_rlmreg_p__parameterized5_385 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_t1_v_latch | tri_rlmlatch_p_386 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_t2_p_latch | tri_rlmreg_p__parameterized9_387 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_t2_t_latch | tri_rlmreg_p__parameterized5_388 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_t2_v_latch | tri_rlmlatch_p_389 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_t3_p_latch | tri_rlmreg_p__parameterized4_390 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_t3_t_latch | tri_rlmreg_p__parameterized5_391 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_t3_v_latch | tri_rlmlatch_p_392 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_val_latch | tri_rlmreg_p__parameterized37_393 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_any_popcnt_latch | tri_rlmlatch_p_394 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_br_val_latch | tri_rlmreg_p__parameterized37_395 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ctr_we_latch | tri_rlmlatch_p_396 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_excep_val_latch | tri_rlmlatch_p_397 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_excep_vector_latch | tri_rlmreg_p__parameterized4_398 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_flush2ucode_latch | tri_rlmlatch_p_399 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_hpriv_latch | tri_rlmlatch_p_400 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_instr_latch | tri_rlmreg_p__parameterized17_401 | 0 | 0 | 0 | 0 | 32 | 0 | 0 | 0 | | ex4_itag_latch | tri_rlmreg_p__parameterized13_402 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex4_lr_we_latch | tri_rlmlatch_p_403 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mul_2c_latch | tri_rlmlatch_p_404 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mul_3c_latch | tri_rlmlatch_p_405 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mul_4c_latch | tri_rlmlatch_p_406 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_n_flush_latch | tri_rlmlatch_p_407 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_np1_flush_latch | tri_rlmlatch_p_408 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ord_complete_latch | tri_rlmlatch_p_409 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_ord_val_latch | tri_rlmreg_p__parameterized37_410 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_t1_p_latch | tri_rlmreg_p__parameterized0_411 | 12 | 12 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_t1_t_latch | tri_rlmreg_p__parameterized5_412 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_t1_v_latch | tri_rlmlatch_p_413 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_t2_p_latch | tri_rlmreg_p__parameterized235 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_t2_t_latch | tri_rlmreg_p__parameterized5_414 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_t2_v_latch | tri_rlmlatch_p_415 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_t3_p_latch | tri_rlmreg_p__parameterized234 | 15 | 15 | 0 | 0 | 5 | 0 | 0 | 0 | | ex4_t3_t_latch | tri_rlmreg_p__parameterized5_416 | 6 | 6 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_t3_v_latch | tri_rlmlatch_p_417 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_val_latch | tri_rlmreg_p__parameterized37_418 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mul_3c_latch | tri_rlmlatch_p_419 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mul_4c_latch | tri_rlmlatch_p_420 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ord_complete_latch | tri_rlmlatch_p_421 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ord_t1_p_latch | tri_rlmreg_p__parameterized0_422 | 18 | 18 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_ord_t1_t_latch | tri_rlmreg_p__parameterized5_423 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_ord_t1_v_latch | tri_rlmlatch_p_424 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ord_t2_p_latch | tri_rlmreg_p__parameterized235_425 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_ord_t2_t_latch | tri_rlmreg_p__parameterized5_426 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_ord_t2_v_latch | tri_rlmlatch_p_427 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_ord_t3_p_latch | tri_rlmreg_p__parameterized234_428 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_ord_t3_t_latch | tri_rlmreg_p__parameterized5_429 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_ord_t3_v_latch | tri_rlmlatch_p_430 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_t1_p_latch | tri_rlmreg_p__parameterized0_431 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex5_t1_t_latch | tri_rlmreg_p__parameterized5_432 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_t1_v_latch | tri_rlmlatch_p_433 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_t2_p_latch | tri_rlmreg_p__parameterized235_434 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_t2_t_latch | tri_rlmreg_p__parameterized5_435 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_t2_v_latch | tri_rlmlatch_p_436 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_t3_p_latch | tri_rlmreg_p__parameterized234_437 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex5_t3_t_latch | tri_rlmreg_p__parameterized5_438 | 1 | 1 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_t3_v_latch | tri_rlmlatch_p_439 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_val_latch | tri_rlmreg_p__parameterized37_440 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cr_wa_latch | tri_rlmreg_p__parameterized234_441 | 14 | 14 | 0 | 0 | 5 | 0 | 0 | 0 | | ex6_cr_we_latch | tri_rlmlatch_p_442 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_gpr_we_latch | tri_rlmlatch_p_443 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_mul_4c_latch | tri_rlmlatch_p_444 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ord_complete_latch | tri_rlmlatch_p_445 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ram_active_latch | tri_rlmlatch_p_446 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_t1_p_latch | tri_rlmreg_p__parameterized0_447 | 99 | 99 | 0 | 0 | 6 | 0 | 0 | 0 | | ex6_t2_p_latch | tri_rlmreg_p__parameterized235_448 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_val_latch | tri_rlmreg_p__parameterized37_449 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xer_we_latch | tri_rlmlatch_p_450 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized234_451 | 21 | 21 | 0 | 0 | 5 | 0 | 0 | 0 | | exx_mul_tid_latch | tri_rlmreg_p__parameterized37_452 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | iu_ord_n_flush_req_latch | tri_rlmreg_p__parameterized2_453 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | iu_xu_credits_returned_latch | tri_rlmlatch_p_454 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | mmu_ord_n_flush_req_latch | tri_rlmreg_p__parameterized2_455 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ord_async_credit_wait_latch | tri_rlmlatch_p_456 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_derat_par_err_latch | tri_rlmlatch_p_457 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_done_latch | tri_rlmlatch_p_458 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_ex3_np1_flush_latch | tri_rlmlatch_p_459 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_hold_lq_latch | tri_rlmlatch_p_460 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_hv_priv_latch | tri_rlmlatch_p_461 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_hyp_priv_latch | tri_rlmlatch_p_462 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_hyp_priv_spr_latch | tri_rlmlatch_p_463 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_ierat_par_err_latch | tri_rlmlatch_p_464 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_ill_tlb_latch | tri_rlmlatch_p_465 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_illeg_mmu_latch | tri_rlmlatch_p_466 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_instr_latch | tri_rlmreg_p__parameterized17_467 | 32 | 32 | 0 | 0 | 32 | 0 | 0 | 0 | | ord_is_cp_next_latch | tri_rlmlatch_p_468 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_local_snoop_reject_latch | tri_rlmlatch_p_469 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_lrat_miss_latch | tri_rlmlatch_p_470 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_mmu_req_sent_latch | tri_rlmlatch_p_471 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_mtiar_latch | tri_rlmlatch_p_472 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_outstanding_latch | tri_rlmlatch_p_473 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_priv_latch | tri_rlmlatch_p_474 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_spr_illegal_spr_latch | tri_rlmlatch_p_475 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_spr_priv_latch | tri_rlmlatch_p_476 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_timeout_latch | tri_rlmreg_p__parameterized2_477 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | ord_timer_latch | tri_rlmreg_p__parameterized0_478 | 8 | 8 | 0 | 0 | 6 | 0 | 0 | 0 | | ord_tlb_inelig_latch | tri_rlmlatch_p_479 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_tlb_lru_par_err_latch | tri_rlmlatch_p_480 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_tlb_multihit_latch | tri_rlmlatch_p_481 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ord_tlb_par_err_latch | tri_rlmlatch_p_482 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_en_attn_latch | tri_rlmlatch_p_483 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr2_notlb_latch | tri_rlmlatch_p_484 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_ccr4_en_dnh_latch | tri_rlmlatch_p_485 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_epcr_dgtmi_latch | tri_rlmreg_p__parameterized37_486 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_mmucr0_tlbsel_gen.spr_mmucr0_tlbsel_entry[0].spr_mmucr0_tlbsel_latch | tri_rlmreg_p__parameterized2_487 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | spr_msr_cm_latch | tri_rlmreg_p__parameterized37_488 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_gs_latch | tri_rlmreg_p__parameterized37_489 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | spr_msr_pr_latch | tri_rlmreg_p__parameterized37_490 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu0_iu_mtiar_latch | tri_rlmreg_p__parameterized37_491 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_hold_val_latch | tri_rlmlatch_p_492 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_pri_latch | tri_rlmreg_p__parameterized5_493 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | xu_iu_pri_val_latch | tri_rlmreg_p__parameterized37_494 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_val_2_latch | tri_rlmreg_p__parameterized37_495 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_iu_val_latch | tri_rlmlatch_p_496 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_hold_val_latch | tri_rlmlatch_p_497 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_val_2_latch | tri_rlmreg_p__parameterized37_498 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_lq_val_latch | tri_rlmlatch_p_499 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_mm_hold_val_latch | tri_rlmlatch_p_500 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_mm_val_2_latch | tri_rlmreg_p__parameterized37_501 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_mm_val_latch | tri_rlmlatch_p_502 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | div | xu0_div_r4 | 2154 | 2154 | 0 | 0 | 656 | 0 | 0 | 0 | | (div) | xu0_div_r4 | 441 | 441 | 0 | 0 | 0 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_255 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_div_ctr_latch | tri_rlmreg_p__parameterized12_256 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_div_extd_latch | tri_rlmlatch_p_257 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_div_sign_latch | tri_rlmlatch_p_258 | 34 | 34 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_div_size_latch | tri_rlmlatch_p_259 | 63 | 63 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_div_tid_latch | tri_rlmreg_p__parameterized37_260 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_div_val_latch | tri_rlmlatch_p_261 | 115 | 115 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_spr_msr_cm_latch | tri_rlmlatch_p_262 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ov_update_latch | tri_rlmlatch_p_263 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_2s_rslt_latch | tri_rlmlatch_p_264 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_PR_carry_latch | tri_rlmreg_p__parameterized218 | 452 | 452 | 0 | 0 | 67 | 0 | 0 | 0 | | ex3_PR_sum_latch | tri_rlmreg_p__parameterized218_265 | 88 | 88 | 0 | 0 | 67 | 0 | 0 | 0 | | ex3_QM_latch | tri_rlmreg_p__parameterized33_266 | 32 | 32 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_Q_latch | tri_rlmreg_p__parameterized33_267 | 33 | 33 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_cycle_act_latch | tri_rlmlatch_p_268 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cycles_latch | tri_rlmreg_p__parameterized12_269 | 79 | 79 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_denom_latch | tri_rlmreg_p__parameterized217 | 376 | 376 | 0 | 0 | 66 | 0 | 0 | 0 | | ex3_div_done_latch | tri_rlmlatch_p_270 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_div_extd_latch | tri_rlmlatch_p_271 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_div_ovf_latch | tri_rlmlatch_p_272 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_div_sign_latch | tri_rlmlatch_p_273 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_div_size_latch | tri_rlmlatch_p_274 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_div_val_latch | tri_rlmlatch_p_275 | 65 | 65 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_divrunning_latch | tri_rlmlatch_p_276 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_dmask_latch | tri_rlmreg_p__parameterized217_277 | 84 | 84 | 0 | 0 | 66 | 0 | 0 | 0 | | ex3_numer_eq_zero_latch | tri_rlmlatch_p_278 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_numer_latch | tri_rlmreg_p__parameterized218_279 | 36 | 36 | 0 | 0 | 67 | 0 | 0 | 0 | | ex3_oddshift_latch | tri_rlmlatch_p_280 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_quotient_correction_latch | tri_rlmlatch_p_281 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_ov_update_latch | tri_rlmlatch_p_282 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_2s_rslt_latch | tri_rlmlatch_p_283 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_div_done_latch | tri_rlmlatch_p_284 | 17 | 17 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_div_ovf_cond3_latch | tri_rlmlatch_p_285 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_div_ovf_latch | tri_rlmlatch_p_286 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_div_rt_latch | tri_rlmreg_p__parameterized33_287 | 147 | 147 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_div_size_latch | tri_rlmlatch_p_288 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_div_val_latch | tri_rlmlatch_p_289 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_divrunning_act_latch | tri_rlmlatch_p_290 | 57 | 57 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_quot_watch_latch | tri_rlmlatch_p_291 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_quotient_latch | tri_rlmreg_p__parameterized33_292 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | ex4_xer_ov_update_latch | tri_rlmlatch_p_293 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_div_done_latch | tri_rlmlatch_p_294 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | xersrc_latch | tri_rlmreg_p__parameterized6_295 | 12 | 12 | 0 | 0 | 10 | 0 | 0 | 0 | | mult | tri_st_mult | 2099 | 2099 | 0 | 0 | 800 | 0 | 0 | 0 | | all0_lo_dly1_latch | tri_rlmlatch_p_182 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | all0_lo_dly2_latch | tri_rlmlatch_p_183 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | all0_lo_dly3_latch | tri_rlmlatch_p_184 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | carry_32_dly1_latch | tri_rlmlatch_p_185 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37_186 | 4 | 4 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_is_ord_latch | tri_rlmlatch_p_187 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_sign_latch | tri_rlmlatch_p_188 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_size_latch | tri_rlmlatch_p_189 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_tid_latch | tri_rlmreg_p__parameterized37_190 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mul_val_latch | tri_rlmlatch_p_191 | 2 | 2 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_retsel_latch | tri_rlmreg_p__parameterized5_192 | 3 | 3 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_spr_msr_cm_latch | tri_rlmlatch_p_193 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ov_update_latch | tri_rlmlatch_p_194 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_bd_lo_sign_latch | tri_rlmlatch_p_195 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_bs_lo_sign_latch | tri_rlmlatch_p_196 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_is_ord_latch | tri_rlmlatch_p_197 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mul_tid_latch | tri_rlmreg_p__parameterized37_198 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_mulsrc_0_latch | tri_rlmreg_p__parameterized33_199 | 186 | 186 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_mulsrc_1_latch | tri_rlmreg_p__parameterized33_200 | 621 | 621 | 0 | 0 | 64 | 0 | 0 | 0 | | ex3_mulstage_latch | tri_rlmreg_p__parameterized9_201 | 141 | 141 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_retsel_latch | tri_rlmreg_p__parameterized5_202 | 4 | 4 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_spr_msr_cm_latch | tri_rlmlatch_p_203 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_ov_update_latch | tri_rlmlatch_p_204 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_src_latch | tri_rlmreg_p__parameterized6_205 | 20 | 20 | 0 | 0 | 10 | 0 | 0 | 0 | | ex4_mul_done_latch | tri_rlmlatch_p_206 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mul_is_ord_latch | tri_rlmlatch_p_207 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mul_tid_latch | tri_rlmreg_p__parameterized37_208 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_mulstage_latch | tri_rlmreg_p__parameterized9_209 | 177 | 177 | 0 | 0 | 4 | 0 | 0 | 0 | | ex4_retsel_latch | tri_rlmreg_p__parameterized5_210 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_spr_msr_cm_latch | tri_rlmlatch_p_211 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xer_ov_update_latch | tri_rlmlatch_p_212 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex4_xer_src_latch | tri_rlmreg_p__parameterized6_213 | 10 | 10 | 0 | 0 | 10 | 0 | 0 | 0 | | ex5_ci_latch | tri_rlmlatch_p_214 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mul_done_latch | tri_rlmlatch_p_215 | 15 | 15 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mul_is_ord_latch | tri_rlmlatch_p_216 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mul_tid_latch | tri_rlmreg_p__parameterized37_217 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_mulstage_latch | tri_rlmreg_p__parameterized9_218 | 60 | 60 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_retsel_latch | tri_rlmreg_p__parameterized5_219 | 22 | 22 | 0 | 0 | 3 | 0 | 0 | 0 | | ex5_spr_msr_cm_latch | tri_rlmlatch_p_220 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xer_ov_update_latch | tri_rlmlatch_p_221 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex5_xer_src_latch | tri_rlmreg_p__parameterized6_222 | 0 | 0 | 0 | 0 | 10 | 0 | 0 | 0 | | ex6_all0_hi_latch | tri_rlmlatch_p_223 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_all0_latch | tri_rlmlatch_p_224 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_all0_lo_latch | tri_rlmlatch_p_225 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_all1_hi_latch | tri_rlmlatch_p_226 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_all1_latch | tri_rlmlatch_p_227 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cmp0_sel_reshi_latch | tri_rlmlatch_p_228 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cmp0_sel_reslo_latch | tri_rlmlatch_p_229 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cmp0_sel_reslodly2_latch | tri_rlmlatch_p_230 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cmp0_sel_reslodly_latch | tri_rlmlatch_p_231 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_cmp0_undef_latch | tri_rlmlatch_p_232 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_b_latch | tri_rlmlatch_p_233 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_hi_b_latch | tri_rlmlatch_p_234 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_lo1_b_latch | tri_rlmlatch_p_235 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_lo2_b_latch | tri_rlmlatch_p_236 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_lo3_b_latch | tri_rlmlatch_p_237 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_eq_sel_all0_lo_b_latch | tri_rlmlatch_p_238 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_mulstage_latch | tri_rlmreg_p__parameterized9_239 | 33 | 33 | 0 | 0 | 2 | 0 | 0 | 0 | | ex6_res_latch | tri_rlmreg_p__parameterized33_240 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_ret_mulldo_latch | tri_rlmlatch_p_241 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_ret_mullw_latch | tri_rlmlatch_p_242 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_rslt_hw_latch | tri_rlmreg_p__parameterized12_243 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex6_rslt_ld_li_latch | tri_rlmreg_p__parameterized12_244 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_rslt_ldo_latch | tri_rlmreg_p__parameterized12_245 | 32 | 32 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_rslt_lw_hd_latch | tri_rlmreg_p__parameterized12_246 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex6_xer_ov_update_latch | tri_rlmlatch_p_247 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex6_xer_src_latch | tri_rlmreg_p__parameterized6_248 | 1 | 1 | 0 | 0 | 10 | 0 | 0 | 0 | | exx_mul_abort_latch | tri_rlmreg_p__parameterized0_249 | 3 | 3 | 0 | 0 | 6 | 0 | 0 | 0 | | mcore | tri_st_mult_core | 623 | 623 | 0 | 0 | 393 | 0 | 0 | 0 | | ex4_pp2_0c_lat | tri_inv_nlats__parameterized2 | 27 | 27 | 0 | 0 | 40 | 0 | 0 | 0 | | ex4_pp2_0s_lat | tri_inv_nlats__parameterized1 | 38 | 38 | 0 | 0 | 44 | 0 | 0 | 0 | | ex4_pp2_1c_lat | tri_inv_nlats__parameterized1_253 | 18 | 18 | 0 | 0 | 42 | 0 | 0 | 0 | | ex4_pp2_1s_lat | tri_inv_nlats__parameterized3 | 49 | 49 | 0 | 0 | 46 | 0 | 0 | 0 | | ex4_pp2_2c_lat | tri_inv_nlats__parameterized4 | 60 | 60 | 0 | 0 | 42 | 0 | 0 | 0 | | ex4_pp2_2s_lat | tri_inv_nlats__parameterized1_254 | 5 | 5 | 0 | 0 | 44 | 0 | 0 | 0 | | ex5_pp5_0c_lat | tri_inv_nlats__parameterized6 | 138 | 138 | 0 | 0 | 67 | 0 | 0 | 0 | | ex5_pp5_0s_lat | tri_inv_nlats__parameterized5 | 288 | 288 | 0 | 0 | 68 | 0 | 0 | 0 | | rslt_lo_act_latch | tri_rlmlatch_p_250 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | rslt_lo_dly_latch | tri_rlmreg_p__parameterized17_251 | 2 | 2 | 0 | 0 | 32 | 0 | 0 | 0 | | rslt_lo_latch | tri_rlmreg_p__parameterized17_252 | 33 | 33 | 0 | 0 | 32 | 0 | 0 | 0 | | pop | tri_st_popcnt | 60 | 60 | 0 | 0 | 86 | 0 | 0 | 0 | | ex2_instr_latch | tri_rlmreg_p__parameterized2_168 | 2 | 2 | 0 | 0 | 2 | 0 | 0 | 0 | | ex3_b0_latch | tri_rlmreg_p__parameterized12_169 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_b1_latch | tri_rlmreg_p__parameterized12_170 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_b2_latch | tri_rlmreg_p__parameterized12_171 | 4 | 4 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_b3_latch | tri_rlmreg_p__parameterized12_172 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ex3_popcnt_sel_latch | tri_rlmreg_p__parameterized5_173 | 0 | 0 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_b0_latch | tri_rlmreg_p__parameterized12_174 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_b1_latch | tri_rlmreg_p__parameterized12_175 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_b2_latch | tri_rlmreg_p__parameterized12_176 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_b3_latch | tri_rlmreg_p__parameterized12_177 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex4_popcnt_sel_latch | tri_rlmreg_p__parameterized5_178 | 10 | 10 | 0 | 0 | 3 | 0 | 0 | 0 | | ex4_word0_latch | tri_rlmreg_p__parameterized0_179 | 7 | 7 | 0 | 0 | 6 | 0 | 0 | 0 | | ex4_word1_latch | tri_rlmreg_p__parameterized0_180 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized2_181 | 1 | 1 | 0 | 0 | 2 | 0 | 0 | 0 | | xu1 | xu1 | 7658 | 7658 | 0 | 0 | 1222 | 0 | 0 | 0 | | (xu1) | xu1 | 1 | 1 | 0 | 0 | 0 | 0 | 0 | 0 | | alu | xu_alu | 3959 | 3959 | 0 | 0 | 282 | 0 | 0 | 0 | | add | xu_alu_add | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_rs0_inv_b_latch | tri_inv_nlats_166 | 10 | 10 | 0 | 0 | 1 | 0 | 0 | 0 | | cmp | xu_alu_cmp | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_msb_64b_sel_latch | tri_rlmlatch_p_158 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_diff_sign_latch | tri_rlmlatch_p_159 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_msb_64b_sel_latch | tri_rlmlatch_p_160 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs1_trm1_latch | tri_rlmlatch_p_161 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_rs2_trm1_latch | tri_rlmlatch_p_162 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_cmp_latch | tri_rlmlatch_p_163 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_cmpl_latch | tri_rlmlatch_p_164 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_trap_latch | tri_rlmlatch_p_165 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_act_latch | tri_rlmlatch_p_109 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_msb_64b_sel_latch | tri_rlmlatch_p_110 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_cmp_latch | tri_rlmlatch_p_111 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_cmpl_latch | tri_rlmlatch_p_112 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_isel_latch | tri_rlmlatch_p_113 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sel_trap_latch | tri_rlmlatch_p_114 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ca_en_latch | tri_rlmlatch_p_115 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_ov_en_latch | tri_rlmlatch_p_116 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_add_ca_latch | tri_rlmlatch_p_117 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_add_ovf_latch | tri_rlmlatch_p_118 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sel_rot_log_latch | tri_rlmlatch_p_119 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_ca_en_latch | tri_rlmlatch_p_120 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_latch | tri_rlmreg_p__parameterized6_121 | 20 | 20 | 0 | 0 | 10 | 0 | 0 | 0 | | ex3_xer_ov_en_latch | tri_rlmlatch_p_122 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | rot | tri_st_rot | 3904 | 3904 | 0 | 0 | 250 | 0 | 0 | 0 | | (rot) | tri_st_rot | 2 | 2 | 0 | 0 | 0 | 0 | 0 | 0 | | ex2_act_latch | tri_rlmlatch_p_123 | 32 | 32 | 0 | 0 | 3 | 0 | 0 | 0 | | ex2_chk_shov_dw_latch | tri_rlmlatch_p_124 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_chk_shov_wd_latch | tri_rlmlatch_p_125 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cmp_byte_latch | tri_rlmlatch_p_126 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ins_prtyd_latch | tri_rlmlatch_p_127 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_ins_prtyw_latch | tri_rlmlatch_p_128 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_log_fcn_latch | tri_rlmreg_p__parameterized9_129 | 154 | 154 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_mb_gt_me_latch | tri_rlmlatch_p_130 | 162 | 162 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_mb_ins_latch | tri_rlmreg_p__parameterized0_131 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_me_ins_b_latch | tri_rlmreg_p__parameterized0_132 | 23 | 23 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_sel_rot_log_latch | tri_rlmlatch_p_133 | 80 | 80 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_byte_latch | tri_rlmlatch_p_134 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_half_latch | tri_rlmlatch_p_135 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sgnxtd_wd_latch | tri_rlmlatch_p_136 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sh_amt_latch | tri_rlmreg_p__parameterized0_137 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_sh_right_latch | tri_rlmreg_p__parameterized5_138 | 12 | 12 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_sh_word_latch | tri_rlmreg_p__parameterized2_139 | 291 | 291 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_sra_dw_latch | tri_rlmlatch_p_140 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_sra_wd_latch | tri_rlmlatch_p_141 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_ins_hi_latch | tri_rlmlatch_p_142 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_ins_lo_latch | tri_rlmlatch_p_143 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_rb_hi_latch | tri_rlmlatch_p_144 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_mb_rb_lo_latch | tri_rlmlatch_p_145 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_ins_hi_latch | tri_rlmlatch_p_146 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_ins_lo_latch | tri_rlmlatch_p_147 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_rb_hi_latch | tri_rlmlatch_p_148 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_me_rb_lo_latch | tri_rlmlatch_p_149 | 9 | 9 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_rb_amt_hi_latch | tri_rlmlatch_p_150 | 291 | 291 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_rb_amt_lo_latch | tri_rlmlatch_p_151 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_sh_amt_hi_latch | tri_rlmlatch_p_152 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_use_sh_amt_lo_latch | tri_rlmlatch_p_153 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_zm_ins_latch | tri_rlmlatch_p_154 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sh_word_latch | tri_rlmlatch_p_155 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_sra_se_latch | tri_rlmreg_p__parameterized37_156 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | msk_lat | tri_inv_nlats | 0 | 0 | 0 | 0 | 64 | 0 | 0 | 0 | | or3232 | tri_st_or3232_b | 33 | 33 | 0 | 0 | 0 | 0 | 0 | 0 | | res_lat | tri_inv_nlats__parameterized0 | 2752 | 2752 | 0 | 0 | 64 | 0 | 0 | 0 | | rot_lat | tri_inv_nlats_157 | 1 | 1 | 0 | 0 | 64 | 0 | 0 | 0 | | byp | xu1_byp | 1721 | 1721 | 0 | 0 | 777 | 0 | 0 | 0 | | ex0_s1_v_latch | tri_rlmlatch_p_34 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s2_v_latch | tri_rlmlatch_p_35 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_s3_v_latch | tri_rlmlatch_p_36 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_abt_s1_lq_sel_latch | tri_rlmlatch_p_37 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_abt_s1_xu0_sel_latch | tri_rlmreg_p__parameterized224 | 2 | 2 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s1_xu1_sel_latch | tri_rlmreg_p__parameterized223 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_abt_s2_lq_sel_latch | tri_rlmlatch_p_38 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_abt_s2_xu0_sel_latch | tri_rlmreg_p__parameterized224_39 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s2_xu1_sel_latch | tri_rlmreg_p__parameterized223_40 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_abt_s3_lq_sel_latch | tri_rlmreg_p__parameterized222 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_abt_s3_xu0_sel_latch | tri_rlmreg_p__parameterized224_41 | 5 | 5 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_abt_s3_xu1_sel_latch | tri_rlmreg_p__parameterized223_42 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[5].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_43 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[6].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_44 | 16 | 16 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[7].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_45 | 36 | 36 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_lq_sel_gen.ex1_gpr_s1_lq_sel_entry[8].ex1_gpr_s1_lq_sel_latch | tri_rlmreg_p__parameterized12_46 | 20 | 20 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_reg_sel_latch | tri_rlmreg_p__parameterized12_47 | 49 | 49 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_rel_sel_gen.ex1_gpr_s1_rel_sel_entry[3].ex1_gpr_s1_rel_sel_latch | tri_rlmreg_p__parameterized12_48 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_rel_sel_gen.ex1_gpr_s1_rel_sel_entry[4].ex1_gpr_s1_rel_sel_latch | tri_rlmreg_p__parameterized12_49 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[2].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_50 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[3].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_51 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[4].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_52 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[5].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_53 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[6].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_54 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[7].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_55 | 64 | 64 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu0_sel_gen.ex1_gpr_s1_xu0_sel_entry[8].ex1_gpr_s1_xu0_sel_latch | tri_rlmreg_p__parameterized12_56 | 29 | 29 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[2].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_57 | 11 | 11 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[3].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_58 | 38 | 38 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[4].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_59 | 58 | 58 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s1_xu1_sel_gen.ex1_gpr_s1_xu1_sel_entry[5].ex1_gpr_s1_xu1_sel_latch | tri_rlmreg_p__parameterized12_60 | 5 | 5 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_imm_sel_latch | tri_rlmreg_p__parameterized12_61 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[5].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_62 | 37 | 37 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[6].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_63 | 28 | 28 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[7].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_64 | 6 | 6 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_lq_sel_gen.ex1_gpr_s2_lq_sel_entry[8].ex1_gpr_s2_lq_sel_latch | tri_rlmreg_p__parameterized12_65 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_reg_sel_latch | tri_rlmreg_p__parameterized12_66 | 66 | 66 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_rel_sel_gen.ex1_gpr_s2_rel_sel_entry[3].ex1_gpr_s2_rel_sel_latch | tri_rlmreg_p__parameterized12_67 | 43 | 43 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_rel_sel_gen.ex1_gpr_s2_rel_sel_entry[4].ex1_gpr_s2_rel_sel_latch | tri_rlmreg_p__parameterized12_68 | 3 | 3 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[2].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_69 | 21 | 21 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[3].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_70 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[4].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_71 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[5].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_72 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[6].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_73 | 1 | 1 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[7].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_74 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu0_sel_gen.ex1_gpr_s2_xu0_sel_entry[8].ex1_gpr_s2_xu0_sel_latch | tri_rlmreg_p__parameterized12_75 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[2].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_76 | 43 | 43 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[3].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_77 | 48 | 48 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[4].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_78 | 0 | 0 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_gpr_s2_xu1_sel_gen.ex1_gpr_s2_xu1_sel_entry[5].ex1_gpr_s2_xu1_sel_latch | tri_rlmreg_p__parameterized12_79 | 12 | 12 | 0 | 0 | 8 | 0 | 0 | 0 | | ex1_s1_v_latch | tri_rlmlatch_p_80 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s2_v_latch | tri_rlmlatch_p_81 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_s3_v_latch | tri_rlmlatch_p_82 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_lq_sel_gen.ex1_spr_s3_lq_sel_entry[5].ex1_spr_s3_lq_sel_latch | tri_rlmreg_p__parameterized37_83 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_lq_sel_gen.ex1_spr_s3_lq_sel_entry[6].ex1_spr_s3_lq_sel_latch | tri_rlmreg_p__parameterized37_84 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_reg_sel_latch | tri_rlmreg_p__parameterized2_85 | 4 | 4 | 0 | 0 | 2 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[3].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_86 | 3 | 3 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[4].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_87 | 7 | 7 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[5].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_88 | 5 | 5 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[6].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_89 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[7].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_90 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu0_sel_gen.ex1_spr_s3_xu0_sel_entry[8].ex1_spr_s3_xu0_sel_latch | tri_rlmreg_p__parameterized37_91 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[3].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized37_92 | 14 | 14 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[4].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized37_93 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_spr_s3_xu1_sel_gen.ex1_spr_s3_xu1_sel_entry[5].ex1_spr_s3_xu1_sel_latch | tri_rlmreg_p__parameterized37_94 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_cr_bit_latch | tri_rlmlatch_p_95 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs1_abort_latch | tri_rlmlatch_p_96 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs1_latch | tri_rlmreg_p__parameterized33_97 | 327 | 327 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_rs2_abort_latch | tri_rlmlatch_p_98 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_rs2_latch | tri_rlmreg_p__parameterized33_99 | 138 | 138 | 0 | 0 | 64 | 0 | 0 | 0 | | ex2_rs3_abort_latch | tri_rlmlatch_p_100 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer3_latch | tri_rlmreg_p__parameterized6 | 11 | 11 | 0 | 0 | 10 | 0 | 0 | 0 | | ex4_xu1_rt_latch | tri_rlmreg_p__parameterized33_101 | 219 | 219 | 0 | 0 | 64 | 0 | 0 | 0 | | ex5_xu0_cr_latch | tri_rlmreg_p__parameterized9_102 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex5_xu0_xer_latch | tri_rlmreg_p__parameterized6_103 | 17 | 17 | 0 | 0 | 10 | 0 | 0 | 0 | | ex5_xu1_rt_latch | tri_rlmreg_p__parameterized33_104 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | ex6_lq_cr_latch | tri_rlmreg_p__parameterized9_105 | 0 | 0 | 0 | 0 | 2 | 0 | 0 | 0 | | exx_lq_abort_latch | tri_rlmreg_p__parameterized233 | 6 | 6 | 0 | 0 | 4 | 0 | 0 | 0 | | exx_rel3_act_latch | tri_rlmlatch_p_106 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_rel3_rt_latch | tri_rlmreg_p__parameterized33_107 | 109 | 109 | 0 | 0 | 64 | 0 | 0 | 0 | | exx_rel4_rt_latch | tri_rlmreg_p__parameterized33_108 | 47 | 47 | 0 | 0 | 64 | 0 | 0 | 0 | | exx_xu0_abort_latch | tri_rlmreg_p__parameterized240 | 13 | 13 | 0 | 0 | 9 | 0 | 0 | 0 | | exx_xu0_act_latch | tri_rlmreg_p__parameterized238 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_xu1_abort_latch | tri_rlmreg_p__parameterized241 | 13 | 13 | 0 | 0 | 6 | 0 | 0 | 0 | | exx_xu1_act_latch | tri_rlmreg_p__parameterized239 | 35 | 35 | 0 | 0 | 4 | 0 | 0 | 0 | | dec | xu1_dec | 1977 | 1977 | 0 | 0 | 163 | 0 | 0 | 0 | | cp_flush_latch | tri_rlmreg_p__parameterized37 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex0_val_latch | tri_rlmreg_p__parameterized37_2 | 197 | 197 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_instr_latch | tri_rlmreg_p__parameterized17 | 236 | 236 | 0 | 0 | 32 | 0 | 0 | 0 | | ex1_itag_latch | tri_rlmreg_p__parameterized13 | 7 | 7 | 0 | 0 | 7 | 0 | 0 | 0 | | ex1_s3_type_latch | tri_rlmreg_p__parameterized5 | 5 | 5 | 0 | 0 | 3 | 0 | 0 | 0 | | ex1_t1_p_latch | tri_rlmreg_p__parameterized0_3 | 6 | 6 | 0 | 0 | 6 | 0 | 0 | 0 | | ex1_t1_v_latch | tri_rlmlatch_p_4 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t2_p_latch | tri_rlmreg_p__parameterized9 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex1_t2_v_latch | tri_rlmlatch_p_5 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_t3_p_latch | tri_rlmreg_p__parameterized4 | 5 | 5 | 0 | 0 | 5 | 0 | 0 | 0 | | ex1_t3_v_latch | tri_rlmlatch_p_6 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_ucode_latch | tri_rlmreg_p__parameterized37_7 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex1_val_latch | tri_rlmreg_p__parameterized37_8 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_add_ci_sel_latch | tri_rlmreg_p__parameterized2 | 3 | 3 | 0 | 0 | 2 | 0 | 0 | 0 | | ex2_cr_we_latch | tri_rlmlatch_p_9 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_dvc_mask_latch | tri_rlmreg_p__parameterized12 | 2 | 2 | 0 | 0 | 8 | 0 | 0 | 0 | | ex2_gpr_we_latch | tri_rlmlatch_p_10 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_instr_latch | tri_rlmreg_p__parameterized43 | 15 | 15 | 0 | 0 | 15 | 0 | 0 | 0 | | ex2_is_lswx_latch | tri_rlmlatch_p_11 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_is_stswx_latch | tri_rlmlatch_p_12 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_itag_latch | tri_rlmreg_p__parameterized13_13 | 0 | 0 | 0 | 0 | 7 | 0 | 0 | 0 | | ex2_stq_val_latch | tri_rlmreg_p__parameterized37_14 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_t1_p_latch | tri_rlmreg_p__parameterized0_15 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex2_t2_p_latch | tri_rlmreg_p__parameterized9_16 | 0 | 0 | 0 | 0 | 4 | 0 | 0 | 0 | | ex2_t3_p_latch | tri_rlmreg_p__parameterized4_17 | 0 | 0 | 0 | 0 | 5 | 0 | 0 | 0 | | ex2_val_latch | tri_rlmreg_p__parameterized37_18 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_val_latch | tri_rlmlatch_p_19 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex2_xer_we_latch | tri_rlmlatch_p_20 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_cr_we_latch | tri_rlmlatch_p_21 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_gpr_we_latch | tri_rlmlatch_p_22 | 7 | 7 | 0 | 0 | 3 | 0 | 0 | 0 | | ex3_illeg_lswx_latch | tri_rlmlatch_p_23 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_itag_latch | tri_rlmreg_p__parameterized13_24 | 0 | 0 | 0 | 0 | 6 | 0 | 0 | 0 | | ex3_ram_active_latch | tri_rlmlatch_p_25 | 2 | 2 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_strg_noop_latch | tri_rlmlatch_p_26 | 0 | 0 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_t1_p_latch | tri_rlmreg_p__parameterized0_27 | 1451 | 1451 | 0 | 0 | 12 | 0 | 0 | 0 | | ex3_t2_p_latch | tri_rlmreg_p__parameterized9_28 | 4 | 4 | 0 | 0 | 4 | 0 | 0 | 0 | | ex3_t3_p_latch | tri_rlmreg_p__parameterized4_29 | 7 | 7 | 0 | 0 | 5 | 0 | 0 | 0 | | ex3_val_latch | tri_rlmreg_p__parameterized37_30 | 6 | 6 | 0 | 0 | 1 | 0 | 0 | 0 | | ex3_xer_we_latch | tri_rlmlatch_p_31 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | exx_act_latch | tri_rlmreg_p__parameterized5_32 | 8 | 8 | 0 | 0 | 3 | 0 | 0 | 0 | | msr_cm_latch | tri_rlmreg_p__parameterized37_33 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | xu_pc_ram_data_latch | tri_rlmreg_p__parameterized33_0 | 64 | 64 | 0 | 0 | 64 | 0 | 0 | 0 | | xu_pc_ram_done_latch | tri_rlmlatch_p_1 | 1 | 1 | 0 | 0 | 1 | 0 | 0 | 0 | | n0 | a2l2wb | 489 | 489 | 0 | 0 | 721 | 0 | 0 | 0 | +-----------------------------------------------------------------------------------------+--------------------------------------------+------------+------------+---------+------+-------+--------+--------+------------+