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470 lines
22 KiB
Verilog
470 lines
22 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//********************************************************************
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//*
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//* TITLE: D-ERAT CAM Match Line Logic for Functional Model
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//*
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//* NAME: tri_cam_32x143_1r1w1c_matchline
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//*
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//*********************************************************************
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module tri_cam_32x143_1r1w1c_matchline(
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addr_in,
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addr_enable,
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comp_pgsize,
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pgsize_enable,
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entry_size,
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entry_cmpmask,
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entry_xbit,
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entry_xbitmask,
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entry_epn,
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comp_class,
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entry_class,
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class_enable,
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comp_extclass,
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entry_extclass,
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extclass_enable,
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comp_state,
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entry_hv,
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entry_ds,
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state_enable,
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entry_thdid,
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comp_thdid,
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thdid_enable,
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entry_pid,
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comp_pid,
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pid_enable,
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entry_v,
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comp_invalidate,
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match
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);
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parameter HAVE_XBIT = 1;
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parameter NUM_PGSIZES = 5;
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parameter HAVE_CMPMASK = 1;
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parameter CMPMASK_WIDTH = 4;
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// @{default:nclk}@
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input [0:51] addr_in;
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input [0:1] addr_enable;
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input [0:2] comp_pgsize;
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input pgsize_enable;
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input [0:2] entry_size;
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input [0:CMPMASK_WIDTH-1] entry_cmpmask;
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input entry_xbit;
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input [0:CMPMASK_WIDTH-1] entry_xbitmask;
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input [0:51] entry_epn;
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input [0:1] comp_class;
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input [0:1] entry_class;
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input [0:2] class_enable;
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input [0:1] comp_extclass;
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input [0:1] entry_extclass;
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input [0:1] extclass_enable;
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input [0:1] comp_state;
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input entry_hv;
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input entry_ds;
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input [0:1] state_enable;
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input [0:3] entry_thdid;
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input [0:3] comp_thdid;
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input [0:1] thdid_enable;
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input [0:7] entry_pid;
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input [0:7] comp_pid;
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input pid_enable;
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input entry_v;
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input comp_invalidate;
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output match;
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// tri_cam_32x143_1r1w1c_matchline
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//----------------------------------------------------------------------
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// Signals
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//----------------------------------------------------------------------
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wire [34:51] entry_epn_b;
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wire function_50_51;
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wire function_48_51;
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wire function_46_51;
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wire function_44_51;
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wire function_40_51;
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wire function_36_51;
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wire function_34_51;
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wire pgsize_eq_16K;
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wire pgsize_eq_64K;
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wire pgsize_eq_256K;
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wire pgsize_eq_1M;
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wire pgsize_eq_16M;
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wire pgsize_eq_256M;
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wire pgsize_eq_1G;
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wire pgsize_gte_16K;
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wire pgsize_gte_64K;
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wire pgsize_gte_256K;
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wire pgsize_gte_1M;
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wire pgsize_gte_16M;
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wire pgsize_gte_256M;
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wire pgsize_gte_1G;
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wire comp_or_34_35;
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wire comp_or_34_39;
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wire comp_or_36_39;
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wire comp_or_40_43;
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wire comp_or_44_45;
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wire comp_or_44_47;
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wire comp_or_46_47;
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wire comp_or_48_49;
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wire comp_or_48_51;
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wire comp_or_50_51;
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wire [0:72] match_line;
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wire pgsize_match;
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wire addr_match;
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wire class_match;
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wire extclass_match;
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wire state_match;
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wire thdid_match;
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wire pid_match;
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(* analysis_not_referenced="true" *)
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wire [0:2] unused;
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assign match_line[0:72] = (~({entry_epn[0:51], entry_size[0:2], entry_class[0:1], entry_extclass[0:1], entry_hv, entry_ds, entry_pid[0:7], entry_thdid[0:3]} ^
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{addr_in[0:51], comp_pgsize[0:2], comp_class[0:1], comp_extclass[0:1], comp_state[0:1], comp_pid[0:7], comp_thdid[0:3]}));
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generate
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if (NUM_PGSIZES == 8)
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begin : numpgsz8
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// tie off unused signals
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assign comp_or_34_39 = 1'b0;
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assign comp_or_44_47 = 1'b0;
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assign comp_or_48_51 = 1'b0;
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assign unused[0] = |{comp_or_34_39, comp_or_44_47, comp_or_48_51};
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assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
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if (HAVE_CMPMASK == 0)
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begin
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assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
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assign pgsize_eq_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
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assign pgsize_eq_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
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assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2])));
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assign pgsize_eq_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
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assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2])));
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assign pgsize_eq_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]);
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assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & entry_size[2]);
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assign pgsize_gte_256M = ( entry_size[0] & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_1G;
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assign pgsize_gte_16M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_256M;
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assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & (~(entry_size[2]))) | pgsize_gte_16M;
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assign pgsize_gte_256K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
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assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & (~(entry_size[2]))) | pgsize_gte_256K;
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assign pgsize_gte_16K = ((~(entry_size[0])) & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_64K;
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assign unused[1] = |{entry_cmpmask, entry_xbitmask};
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end
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if (HAVE_CMPMASK == 1)
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begin
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// size entry_cmpmask: 0123456
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// 1GB 0000000
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// 256MB 1000000
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// 16MB 1100000
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// 1MB 1110000
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// 256KB 1111000
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// 64KB 1111100
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// 16KB 1111110
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// 4KB 1111111
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assign pgsize_gte_1G = (~entry_cmpmask[0]);
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assign pgsize_gte_256M = (~entry_cmpmask[1]);
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assign pgsize_gte_16M = (~entry_cmpmask[2]);
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assign pgsize_gte_1M = (~entry_cmpmask[3]);
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assign pgsize_gte_256K = (~entry_cmpmask[4]);
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assign pgsize_gte_64K = (~entry_cmpmask[5]);
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assign pgsize_gte_16K = (~entry_cmpmask[6]);
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// size entry_xbitmask: 0123456
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// 1GB 1000000
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// 256MB 0100000
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// 16MB 0010000
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// 1MB 0001000
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// 256KB 0000100
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// 64KB 0000010
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// 16KB 0000001
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// 4KB 0000000
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assign pgsize_eq_1G = entry_xbitmask[0];
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assign pgsize_eq_256M = entry_xbitmask[1];
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assign pgsize_eq_16M = entry_xbitmask[2];
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assign pgsize_eq_1M = entry_xbitmask[3];
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assign pgsize_eq_256K = entry_xbitmask[4];
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assign pgsize_eq_64K = entry_xbitmask[5];
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assign pgsize_eq_16K = entry_xbitmask[6];
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assign unused[1] = 1'b0;
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end
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if (HAVE_XBIT == 0)
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begin
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assign function_34_51 = 1'b0;
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assign function_36_51 = 1'b0;
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assign function_40_51 = 1'b0;
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assign function_44_51 = 1'b0;
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assign function_46_51 = 1'b0;
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assign function_48_51 = 1'b0;
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assign function_50_51 = 1'b0;
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assign unused[2] = |{function_34_51, function_36_51, function_40_51, function_44_51,
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function_46_51, function_48_51, function_50_51, entry_xbit,
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entry_epn_b, pgsize_eq_1G, pgsize_eq_256M, pgsize_eq_16M,
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pgsize_eq_1M, pgsize_eq_256K, pgsize_eq_64K, pgsize_eq_16K};
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end
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if (HAVE_XBIT != 0)
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begin
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assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
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assign function_36_51 = (~(entry_xbit)) | (~(pgsize_eq_256M)) | (|(entry_epn_b[36:51] & addr_in[36:51]));
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assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
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assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
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assign function_46_51 = (~(entry_xbit)) | (~(pgsize_eq_256K)) | (|(entry_epn_b[46:51] & addr_in[46:51]));
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assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
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assign function_50_51 = (~(entry_xbit)) | (~(pgsize_eq_16K)) | (|(entry_epn_b[50:51] & addr_in[50:51]));
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assign unused[2] = 1'b0;
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end
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assign comp_or_50_51 = (&(match_line[50:51])) | pgsize_gte_16K;
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assign comp_or_48_49 = (&(match_line[48:49])) | pgsize_gte_64K;
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assign comp_or_46_47 = (&(match_line[46:47])) | pgsize_gte_256K;
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assign comp_or_44_45 = (&(match_line[44:45])) | pgsize_gte_1M;
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assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
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assign comp_or_36_39 = (&(match_line[36:39])) | pgsize_gte_256M;
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assign comp_or_34_35 = (&(match_line[34:35])) | pgsize_gte_1G;
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if (HAVE_XBIT == 0)
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begin
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assign addr_match = (comp_or_34_35 & // Ignore functions based on page size
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comp_or_36_39 &
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comp_or_40_43 &
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comp_or_44_45 &
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comp_or_46_47 &
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comp_or_48_49 &
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comp_or_50_51 &
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(&(match_line[31:33])) & // Regular compare largest page size
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((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
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(~(addr_enable[0])); // Include address as part of compare,
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// should never ignore for regular compare/read.
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// Could ignore for compare/invalidate
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end
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if (HAVE_XBIT != 0)
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begin
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assign addr_match = (function_50_51 & // Exclusion functions
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function_48_51 &
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function_46_51 &
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function_44_51 &
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function_40_51 &
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function_36_51 &
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function_34_51 &
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comp_or_34_35 & // Ignore functions based on page size
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comp_or_36_39 &
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comp_or_40_43 &
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comp_or_44_45 &
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comp_or_46_47 &
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comp_or_48_49 &
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comp_or_50_51 &
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(&(match_line[31:33])) & // Regular compare largest page size
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(&(match_line[0:30]) | (~(addr_enable[1])))) | // ignored part of epn
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(~(addr_enable[0])); // Include address as part of compare,
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// should never ignore for regular compare/read.
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// Could ignore for compare/invalidate
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end
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end // numpgsz8: NUM_PGSIZES = 8
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if (NUM_PGSIZES == 5)
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begin : numpgsz5
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// tie off unused signals
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assign function_50_51 = 1'b0;
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assign function_46_51 = 1'b0;
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assign function_36_51 = 1'b0;
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assign pgsize_eq_16K = 1'b0;
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assign pgsize_eq_256K = 1'b0;
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assign pgsize_eq_256M = 1'b0;
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assign pgsize_gte_16K = 1'b0;
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assign pgsize_gte_256K = 1'b0;
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assign pgsize_gte_256M = 1'b0;
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assign comp_or_34_35 = 1'b0;
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assign comp_or_36_39 = 1'b0;
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assign comp_or_44_45 = 1'b0;
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assign comp_or_46_47 = 1'b0;
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assign comp_or_48_49 = 1'b0;
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assign comp_or_50_51 = 1'b0;
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assign unused[0] = |{function_50_51, function_46_51, function_36_51,
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pgsize_eq_16K, pgsize_eq_256K, pgsize_eq_256M,
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pgsize_gte_16K, pgsize_gte_256K, pgsize_gte_256M,
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comp_or_34_35, comp_or_36_39, comp_or_44_45,
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comp_or_46_47, comp_or_48_49, comp_or_50_51};
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assign entry_epn_b[34:51] = (~(entry_epn[34:51]));
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if (HAVE_CMPMASK == 0)
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begin
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// 110
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assign pgsize_eq_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
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// 111
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assign pgsize_eq_16M = ( entry_size[0] & entry_size[1] & entry_size[2]);
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// 101
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assign pgsize_eq_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]);
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// 011
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assign pgsize_eq_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]);
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assign pgsize_gte_1G = ( entry_size[0] & entry_size[1] & (~(entry_size[2])));
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assign pgsize_gte_16M = ( entry_size[0] & entry_size[1] & entry_size[2]) | pgsize_gte_1G;
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assign pgsize_gte_1M = ( entry_size[0] & (~(entry_size[1])) & entry_size[2]) | pgsize_gte_16M;
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assign pgsize_gte_64K = ((~(entry_size[0])) & entry_size[1] & entry_size[2]) | pgsize_gte_1M;
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assign unused[1] = |{entry_cmpmask, entry_xbitmask};
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end
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if (HAVE_CMPMASK == 1)
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begin
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// size entry_cmpmask: 0123
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// 1GB 0000
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// 16MB 1000
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// 1MB 1100
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// 64KB 1110
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// 4KB 1111
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assign pgsize_gte_1G = (~entry_cmpmask[0]);
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assign pgsize_gte_16M = (~entry_cmpmask[1]);
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assign pgsize_gte_1M = (~entry_cmpmask[2]);
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assign pgsize_gte_64K = (~entry_cmpmask[3]);
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// size entry_xbitmask: 0123
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// 1GB 1000
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// 16MB 0100
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// 1MB 0010
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// 64KB 0001
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// 4KB 0000
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assign pgsize_eq_1G = entry_xbitmask[0];
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assign pgsize_eq_16M = entry_xbitmask[1];
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assign pgsize_eq_1M = entry_xbitmask[2];
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assign pgsize_eq_64K = entry_xbitmask[3];
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assign unused[1] = 1'b0;
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end
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if (HAVE_XBIT == 0)
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begin
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assign function_34_51 = 1'b0;
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assign function_40_51 = 1'b0;
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assign function_44_51 = 1'b0;
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assign function_48_51 = 1'b0;
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assign unused[2] = |{function_34_51, function_40_51, function_44_51,
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function_48_51, entry_xbit, entry_epn_b,
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pgsize_eq_1G, pgsize_eq_16M, pgsize_eq_1M, pgsize_eq_64K};
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end
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if (HAVE_XBIT != 0)
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begin
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// 1G
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assign function_34_51 = (~(entry_xbit)) | (~(pgsize_eq_1G)) | (|(entry_epn_b[34:51] & addr_in[34:51]));
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// 16M
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assign function_40_51 = (~(entry_xbit)) | (~(pgsize_eq_16M)) | (|(entry_epn_b[40:51] & addr_in[40:51]));
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// 1M
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assign function_44_51 = (~(entry_xbit)) | (~(pgsize_eq_1M)) | (|(entry_epn_b[44:51] & addr_in[44:51]));
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// 64K
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assign function_48_51 = (~(entry_xbit)) | (~(pgsize_eq_64K)) | (|(entry_epn_b[48:51] & addr_in[48:51]));
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assign unused[2] = 1'b0;
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end
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assign comp_or_48_51 = (&(match_line[48:51])) | pgsize_gte_64K;
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assign comp_or_44_47 = (&(match_line[44:47])) | pgsize_gte_1M;
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assign comp_or_40_43 = (&(match_line[40:43])) | pgsize_gte_16M;
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assign comp_or_34_39 = (&(match_line[34:39])) | pgsize_gte_1G;
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|
|
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if (HAVE_XBIT == 0)
|
|
begin
|
|
assign addr_match = (comp_or_34_39 & // Ignore functions based on page size
|
|
comp_or_40_43 &
|
|
comp_or_44_47 &
|
|
comp_or_48_51 &
|
|
(&(match_line[31:33])) & // Regular compare largest page size
|
|
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
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|
(~(addr_enable[0])); // Include address as part of compare,
|
|
// should never ignore for regular compare/read.
|
|
// Could ignore for compare/invalidate
|
|
end
|
|
|
|
if (HAVE_XBIT != 0)
|
|
begin
|
|
assign addr_match = (function_48_51 &
|
|
function_44_51 &
|
|
function_40_51 &
|
|
function_34_51 &
|
|
comp_or_34_39 & // Ignore functions based on page size
|
|
comp_or_40_43 &
|
|
comp_or_44_47 &
|
|
comp_or_48_51 &
|
|
(&(match_line[31:33])) & // Regular compare largest page size
|
|
((&(match_line[0:30])) | (~(addr_enable[1])))) | // ignored part of epn
|
|
(~(addr_enable[0])); // Include address as part of compare,
|
|
// should never ignore for regular compare/read.
|
|
// Could ignore for compare/invalidate
|
|
end
|
|
end // numpgsz5: NUM_PGSIZES = 5
|
|
|
|
|
|
assign pgsize_match = (&(match_line[52:54])) | (~(pgsize_enable));
|
|
|
|
assign class_match = (match_line[55] | (~(class_enable[0]))) &
|
|
(match_line[56] | (~(class_enable[1]))) &
|
|
((&(match_line[55:56])) | (~(class_enable[2])) |
|
|
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit
|
|
|
|
assign extclass_match = (match_line[57] | (~(extclass_enable[0]))) & // iprot bit
|
|
(match_line[58] | (~(extclass_enable[1]))); // pid_nz bit
|
|
|
|
assign state_match = (match_line[59] | (~(state_enable[0]))) &
|
|
(match_line[60] | (~(state_enable[1])));
|
|
|
|
assign thdid_match = (|(entry_thdid[0:3] & comp_thdid[0:3]) | (~(thdid_enable[0]))) &
|
|
(&(match_line[69:72]) | (~(thdid_enable[1])) |
|
|
((~(entry_extclass[1])) & (~comp_invalidate))); // pid_nz bit
|
|
|
|
assign pid_match = (&(match_line[61:68])) |
|
|
// entry_pid=0 ignores pid match for compares,
|
|
// but not for invalidates.
|
|
((~(entry_extclass[1])) & (~comp_invalidate)) | // pid_nz bit
|
|
(~(pid_enable));
|
|
|
|
assign match = addr_match & // Address compare
|
|
pgsize_match & // Size compare
|
|
class_match & // Class compare
|
|
extclass_match & // ExtClass compare
|
|
state_match & // State compare
|
|
thdid_match & // ThdID compare
|
|
pid_match & // PID compare
|
|
entry_v; // Valid
|
|
endgenerate
|
|
endmodule
|