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323 lines
12 KiB
Verilog
323 lines
12 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module tri_fu_mul(
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vdd,
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gnd,
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clkoff_b,
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act_dis,
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flush,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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sg_1,
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thold_1,
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fpu_enable,
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nclk,
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f_mul_si,
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f_mul_so,
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ex2_act,
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f_fmt_ex2_a_frac,
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f_fmt_ex2_a_frac_17,
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f_fmt_ex2_a_frac_35,
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f_fmt_ex2_c_frac,
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f_mul_ex3_sum,
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f_mul_ex3_car
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);
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inout vdd;
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inout gnd;
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input clkoff_b; // tiup
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input act_dis; // ??tidn??
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input flush; // ??tidn??
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input delay_lclkr; // tidn,
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input mpw1_b; // tidn,
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input mpw2_b; // tidn,
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input sg_1;
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input thold_1;
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input fpu_enable; //dc_act
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input [0:`NCLK_WIDTH-1] nclk;
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input f_mul_si; //perv
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output f_mul_so; //perv
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input ex2_act; //act
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input [0:52] f_fmt_ex2_a_frac; // implicit bit already generated
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input f_fmt_ex2_a_frac_17; // new port for replicated bit
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input f_fmt_ex2_a_frac_35; // new port for replicated bit
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input [0:53] f_fmt_ex2_c_frac; // implicit bit already generated
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output [1:108] f_mul_ex3_sum;
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output [1:108] f_mul_ex3_car;
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// ENTITY
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parameter tiup = 1'b1;
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parameter tidn = 1'b0;
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wire thold_0_b;
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wire thold_0;
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wire force_t;
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wire sg_0;
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wire [0:3] spare_unused;
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//--------------------------------------
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wire [0:3] act_so; //SCAN
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wire [0:3] act_si;
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wire m92_0_so;
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wire m92_1_so;
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wire m92_2_so;
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//--------------------------------------
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wire [36:108] pp3_05;
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wire [35:108] pp3_04;
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wire [18:90] pp3_03;
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wire [17:90] pp3_02;
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wire [0:72] pp3_01;
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wire [0:72] pp3_00;
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wire hot_one_msb_unused;
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wire hot_one_74;
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wire hot_one_92;
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wire xtd_unused;
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wire [1:108] pp5_00;
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wire [1:108] pp5_01;
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////################################################################
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////# pervasive
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////################################################################
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tri_plat thold_reg_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(flush),
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.din(thold_1),
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.q(thold_0)
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);
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tri_plat sg_reg_0(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.flush(flush),
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.din(sg_1),
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.q(sg_0)
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);
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tri_lcbor lcbor_0(
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.clkoff_b(clkoff_b),
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.thold(thold_0),
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.sg(sg_0),
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.act_dis(act_dis),
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.force_t(force_t),
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.thold_b(thold_0_b)
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);
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////################################################################
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////# act
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////################################################################
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tri_rlmreg_p #(.WIDTH(4), .NEEDS_SRESET(0)) act_lat(
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.force_t(force_t), //i-- tidn,
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr), //i-- tidn,
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.mpw1_b(mpw1_b), //i-- tidn,
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.mpw2_b(mpw2_b), //i-- tidn,
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(fpu_enable),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.scout(act_so),
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.scin(act_si),
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//-----------------
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.din({ spare_unused[0],
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spare_unused[1],
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spare_unused[2],
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spare_unused[3]}),
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//-----------------
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.dout({spare_unused[0],
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spare_unused[1],
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spare_unused[2],
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spare_unused[3]})
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);
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assign act_si[0:3] = {act_so[1:3], m92_2_so};
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assign f_mul_so = act_so[0];
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////################################################################
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////# ex2 logic
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////################################################################
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////# NUMBERING SYSTEM RELATIVE TO COMPRESSOR TREE
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////#
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////# 0000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000000111111111
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////# 0000000000111111111122222222223333333333444444444455555555556666666666777777777788888888889999999999000000000
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////# 0123456789012345678901234567890123456789012345678901234567890123456789012345678901234567890123456789012345678
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////# 0 ..DdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................................
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////# 1 ..1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................................
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////# 2 ....1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................................
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////# 3 ......1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................................
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////# 4 ........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................................
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////# 5 ..........1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................................
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////# 6 ............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................................
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////# 7 ..............1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................................
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////# 8 ................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................................
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////# 9 ..................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................................
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////# 10 ....................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............................
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////# 11 ......................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............................
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////# 12 ........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........................
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////# 13 ..........................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........................
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////# 14 ............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......................
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////# 15 ..............................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....................
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////# 16 ................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..................
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////# 17 ..................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s................
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////# 18 ....................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..............
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////# 19 ......................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s............
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////# 20 ........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..........
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////# 21 ..........................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s........
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////# 22 ............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s......
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////# 23 ..............................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s....
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////# 24 ................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s..
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////# 25 ..................................................1aDdddddddddddddddddddddddddddddddddddddddddddddddddddddD0s
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////# 26 ...................................................assDdddddddddddddddddddddddddddddddddddddddddddddddddddddD
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tri_fu_mul_92 #(.inst(2)) m92_2(
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.vdd(vdd), //i--
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.gnd(gnd), //i--
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.nclk(nclk), //i--
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.force_t(force_t), //i--
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.lcb_delay_lclkr(delay_lclkr), //i-- tidn
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.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
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.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
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.thold_b(thold_0_b), //i--
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.lcb_sg(sg_0), //i--
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.si(f_mul_si), //i--
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.so(m92_0_so), //o--
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.ex2_act(ex2_act), //i--
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//--------------------
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.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
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.a_frac({f_fmt_ex2_a_frac[35:52], //i-- Multiplier (recode me)
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tidn}), //i-- Multiplier (recode me)
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.hot_one_out(hot_one_92), //o--
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.sum92(pp3_05[36:108]), //o--
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.car92(pp3_04[35:108]) //o--
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);
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tri_fu_mul_92 #(.inst(1)) m92_1(
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.vdd(vdd), //i--
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.gnd(gnd), //i--
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.nclk(nclk), //i--
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.force_t(force_t), //i--
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.lcb_delay_lclkr(delay_lclkr), //i-- tidn
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.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
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.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
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.thold_b(thold_0_b), //i--
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.lcb_sg(sg_0), //i--
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.si(m92_0_so), //i--
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.so(m92_1_so), //o-- v
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.ex2_act(ex2_act), //i--
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//-------------------
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.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
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.a_frac({f_fmt_ex2_a_frac[17:34], //i-- Multiplier (recode me)
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f_fmt_ex2_a_frac_35}), //i-- Multiplier (recode me)
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.hot_one_out(hot_one_74), //o--
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.sum92(pp3_03[18:90]), //o--
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.car92(pp3_02[17:90]) //o--
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);
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tri_fu_mul_92 #(.inst(0)) m92_0(
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.vdd(vdd), //i--
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.gnd(gnd), //i--
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.nclk(nclk), //i--
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.force_t(force_t), //i--
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.lcb_delay_lclkr(delay_lclkr), //i-- tidn
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.lcb_mpw1_b(mpw1_b), //i-- mpw1_b others=0
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.lcb_mpw2_b(mpw2_b), //i-- mpw2_b others=0
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.thold_b(thold_0_b), //i--
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.lcb_sg(sg_0), //i--
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.si(m92_1_so), //i--
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.so(m92_2_so), //o--
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.ex2_act(ex2_act), //i--
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//-------------------
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.c_frac(f_fmt_ex2_c_frac[0:53]), //i-- Multiplicand (shift me)
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.a_frac({tidn, //i-- Multiplier (recode me)
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f_fmt_ex2_a_frac[0:16], //i-- Multiplier (recode me)
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f_fmt_ex2_a_frac_17}), //i-- Multiplier (recode me)
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.hot_one_out(hot_one_msb_unused), //o--
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.sum92(pp3_01[0:72]), //o--
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.car92({xtd_unused, //o--
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pp3_00[0:72]}) //o--
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);
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////##################################################
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////# Compressor Level 4 , 5
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////##################################################
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tri_fu_mul_62 m62(
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.vdd(vdd),
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.gnd(gnd),
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.hot_one_92(hot_one_92), //i--
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.hot_one_74(hot_one_74), //i--
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.pp3_05(pp3_05[36:108]), //i--
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.pp3_04(pp3_04[35:108]), //i--
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.pp3_03(pp3_03[18:90]), //i--
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.pp3_02(pp3_02[17:90]), //i--
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.pp3_01(pp3_01[0:72]), //i--
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.pp3_00(pp3_00[0:72]), //i--
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.sum62(pp5_01[1:108]), //o--
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.car62(pp5_00[1:108]) //o--
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);
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////################################################################
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////# ex3 logic
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////################################################################
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assign f_mul_ex3_sum[1:108] = pp5_01[1:108]; //output
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assign f_mul_ex3_car[1:108] = pp5_00[1:108]; //output
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endmodule
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