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84 lines
2.7 KiB
Verilog
84 lines
2.7 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_lcbcntl_mac.v
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// *! DESCRIPTION : Used to generate control signals for LCBs
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_lcbcntl_mac(
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vdd,
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gnd,
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sg,
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nclk,
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scan_in,
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scan_diag_dc,
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thold,
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clkoff_dc_b,
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delay_lclkr_dc,
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act_dis_dc,
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d_mode_dc,
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mpw1_dc_b,
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mpw2_dc_b,
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scan_out
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);
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inout vdd;
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inout gnd;
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input sg;
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input [0:`NCLK_WIDTH-1] nclk;
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input scan_in;
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input scan_diag_dc;
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input thold;
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output clkoff_dc_b;
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output [0:4] delay_lclkr_dc;
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output act_dis_dc;
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output d_mode_dc;
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output [0:4] mpw1_dc_b;
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output mpw2_dc_b;
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output scan_out;
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// tri_lcbcntl_mac
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(* analysis_not_referenced="true" *)
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wire unused;
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assign clkoff_dc_b = 1'b1;
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assign delay_lclkr_dc = 5'b00000;
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assign act_dis_dc = 1'b0;
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assign d_mode_dc = 1'b0;
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assign mpw1_dc_b = 5'b11111;
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assign mpw2_dc_b = 1'b1;
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assign scan_out = 1'b0;
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assign unused = vdd | gnd | sg | (|nclk) | scan_in | scan_diag_dc | thold;
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endmodule
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