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813 lines
29 KiB
Verilog
813 lines
29 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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//*****************************************************************************
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//*
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//* TITLE: TRI_PARITY_RECOVERY
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//*
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//* NAME: tri_parity_recovery
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//*
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//*****************************************************************************
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`include "tri_a2o.vh"
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module tri_parity_recovery(
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perr_si,
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perr_so,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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nclk,
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force_t,
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thold_0_b,
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sg_0,
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gnd,
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vdd,
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ex3_hangcounter_trigger,
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ex3_a_parity_check,
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ex3_b_parity_check,
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ex3_c_parity_check,
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ex3_s_parity_check,
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rf0_instr_fra,
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rf0_instr_frb,
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rf0_instr_frc,
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rf0_tid,
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rf0_dcd_fra,
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rf0_dcd_frb,
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rf0_dcd_frc,
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rf0_dcd_tid,
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ex1_instr_fra,
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ex1_instr_frb,
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ex1_instr_frc,
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ex1_instr_frs,
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ex3_fra_v,
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ex3_frb_v,
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ex3_frc_v,
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ex3_str_v,
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ex3_frs_byp,
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ex3_fdivsqrt_start,
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ex3_instr_v,
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msr_fp_act,
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cp_flush_1d,
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ex7_is_fixperr,
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xx_ex4_regfile_err_det,
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xx_ex5_regfile_err_det,
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xx_ex6_regfile_err_det,
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xx_ex7_regfile_err_det,
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xx_ex8_regfile_err_det,
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xx_ex1_perr_sm_instr_v,
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xx_ex2_perr_sm_instr_v,
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xx_ex3_perr_sm_instr_v,
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xx_ex4_perr_sm_instr_v,
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xx_ex5_perr_sm_instr_v,
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xx_ex6_perr_sm_instr_v,
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xx_ex7_perr_sm_instr_v,
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xx_ex8_perr_sm_instr_v,
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xx_perr_sm_running,
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xx_ex2_perr_force_c,
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xx_ex2_perr_fsel_ovrd,
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xx_perr_tid_l2,
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xx_perr_sm_l2,
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xx_perr_addr_l2,
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ex3_sto_parity_err,
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xx_rv_hold_all,
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xx_ex0_regfile_ue,
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xx_ex0_regfile_ce,
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xx_pc_err_regfile_parity,
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xx_pc_err_regfile_ue
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);
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//parameter THREADS = 2;
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input perr_si;
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output perr_so;
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input [0:9] delay_lclkr;
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input [0:9] mpw1_b;
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input [0:1] mpw2_b;
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input [0:`NCLK_WIDTH-1] nclk;
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input force_t;
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input thold_0_b;
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input sg_0;
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inout gnd;
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inout vdd;
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input ex3_hangcounter_trigger;
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input ex3_a_parity_check;
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input ex3_b_parity_check;
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input ex3_c_parity_check;
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input ex3_s_parity_check;
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input [0:5] rf0_instr_fra;
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input [0:5] rf0_instr_frb;
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input [0:5] rf0_instr_frc;
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input [0:1] rf0_tid;
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output [0:5] rf0_dcd_fra;
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output [0:5] rf0_dcd_frb;
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output [0:5] rf0_dcd_frc;
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output [0:1] rf0_dcd_tid;
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input [0:5] ex1_instr_fra;
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input [0:5] ex1_instr_frb;
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input [0:5] ex1_instr_frc;
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input [0:5] ex1_instr_frs;
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input ex3_fra_v;
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input ex3_frb_v;
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input ex3_frc_v;
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input ex3_str_v;
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input ex3_frs_byp;
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input [0:1] ex3_fdivsqrt_start;
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input [0:1] ex3_instr_v;
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input msr_fp_act;
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input [0:1] cp_flush_1d;
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output ex7_is_fixperr;
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output [0:1] xx_ex4_regfile_err_det;
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output [0:1] xx_ex5_regfile_err_det;
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output [0:1] xx_ex6_regfile_err_det;
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output [0:1] xx_ex7_regfile_err_det;
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output [0:1] xx_ex8_regfile_err_det;
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output xx_ex1_perr_sm_instr_v;
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output xx_ex2_perr_sm_instr_v;
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output xx_ex3_perr_sm_instr_v;
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output xx_ex4_perr_sm_instr_v;
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output xx_ex5_perr_sm_instr_v;
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output xx_ex6_perr_sm_instr_v;
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output xx_ex7_perr_sm_instr_v;
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output xx_ex8_perr_sm_instr_v;
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output xx_perr_sm_running;
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output xx_ex2_perr_force_c;
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output xx_ex2_perr_fsel_ovrd;
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output [0:1] xx_perr_tid_l2;
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output [0:2] xx_perr_sm_l2;
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output [0:5] xx_perr_addr_l2;
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output ex3_sto_parity_err;
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output xx_rv_hold_all;
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output xx_ex0_regfile_ue;
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output xx_ex0_regfile_ce;
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output [0:`THREADS-1] xx_pc_err_regfile_parity;
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output [0:`THREADS-1] xx_pc_err_regfile_ue;
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// parity err ---------
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(* analysis_not_referenced="TRUE" *) // unused
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wire [0:2] spare_unused;
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wire perr_sm_running;
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wire [0:23] ex3_perr_si;
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wire [0:23] ex3_perr_so;
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wire [0:1] ex3_fpr_perr;
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wire [0:1] ex3_fpr_reg_perr;
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wire ex3_regfile_err_det_any;
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wire ex3_capture_addr;
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wire [0:1] ex4_regfile_err_det_din;
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wire [0:1] ex5_regfile_err_det_din;
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wire [0:1] ex6_regfile_err_det_din;
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wire [0:1] ex7_regfile_err_det_din;
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wire regfile_seq_beg;
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wire regfile_seq_end;
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wire ex4_regfile_err_det_any;
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wire ex5_regfile_err_det_any;
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wire ex6_regfile_err_det_any;
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wire [0:1] ex4_sto_err_det;
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wire [0:1] ex4_regfile_err_det;
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wire [0:1] ex5_regfile_err_det;
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wire [0:1] ex6_regfile_err_det;
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wire [0:1] ex7_regfile_err_det;
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wire [0:1] ex8_regfile_err_det;
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wire ex3_f0a_perr;
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wire ex3_f0c_perr;
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wire ex3_f1b_perr;
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wire ex3_f1s_perr;
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wire [0:1] ex3_sto_perr;
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wire [0:0] holdall_si;
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wire [0:0] holdall_so;
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wire rv_hold_all_din;
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wire rv_hold_all_q;
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wire [0:1] err_regfile_parity;
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wire [0:1] err_regfile_ue;
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wire [0:1] ex3_abc_perr;
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wire [0:1] ex3_abc_perr_x;
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wire [0:1] ex3_abc_perr_y;
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wire ex1_perr_move_f0_to_f1;
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wire ex1_perr_move_f1_to_f0;
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wire ex0_regfile_ce;
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wire ex0_regfile_ue;
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wire [0:23] ex2_perr_si;
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wire [0:23] ex2_perr_so;
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wire [0:5] ex3_instr_fra;
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wire [0:5] ex3_instr_frb;
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wire [0:5] ex3_instr_frc;
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wire [0:5] ex3_instr_frs;
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wire [0:5] ex2_instr_fra;
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wire [0:5] ex2_instr_frb;
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wire [0:5] ex2_instr_frc;
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wire [0:5] ex2_instr_frs;
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wire new_perr_sm_instr_v;
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wire rf0_perr_sm_instr_v;
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wire rf0_perr_sm_instr_v_b;
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wire ex0_perr_sm_instr_v;
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wire ex1_perr_sm_instr_v;
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wire ex2_perr_sm_instr_v;
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wire ex3_perr_sm_instr_v;
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wire ex4_perr_sm_instr_v;
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wire ex5_perr_sm_instr_v;
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wire ex6_perr_sm_instr_v;
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wire ex7_perr_sm_instr_v;
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wire ex8_perr_sm_instr_v;
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wire rf0_perr_move_f0_to_f1;
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wire rf0_perr_move_f1_to_f0;
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wire rf0_perr_fixed_itself;
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wire perr_move_f0_to_f1_l2;
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wire perr_move_f1_to_f0_l2;
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wire rf0_perr_force_c;
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wire ex0_perr_force_c;
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wire ex1_perr_force_c;
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wire ex2_perr_force_c;
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wire [0:5] perr_addr_din;
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wire [0:5] perr_addr_l2;
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wire [0:30] perr_ctl_si;
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wire [0:30] perr_ctl_so;
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wire perr_move_f0_to_f1;
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wire perr_move_f1_to_f0;
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wire [0:2] perr_sm_din;
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wire [0:2] perr_sm_l2;
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wire [0:2] perr_sm_ns;
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wire [0:2] perr_sm_si;
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wire [0:2] perr_sm_so;
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wire [0:1] perr_tid_din;
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wire [0:1] perr_tid_l2;
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wire rf0_regfile_ce;
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wire rf0_regfile_ue;
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wire [0:3] ex4_ctl_perr_si;
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wire [0:3] ex4_ctl_perr_so;
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wire [0:8] exx_regfile_err_det_si;
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wire [0:8] exx_regfile_err_det_so;
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wire [0:5] rf0_frb_iu_x_b;
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wire [0:5] rf0_frb_perr_x_b;
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wire [0:5] rf0_frc_iu_x_b;
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wire [0:5] rf0_frc_perr_x_b;
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wire ex3_a_perr_check;
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wire ex3_b_perr_check;
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wire ex3_c_perr_check;
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wire ex3_s_perr_check;
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//------------- end parity
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wire tilo;
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wire tihi;
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wire tidn;
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wire tiup;
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//-------------------------------------------------------------------------------------------------
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assign tilo = 1'b0;
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assign tihi = 1'b1;
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assign tidn = 1'b0;
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assign tiup = 1'b1;
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//----------------------------------------------------------------------
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// Parity State Machine / parity section
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assign xx_ex4_regfile_err_det = ex4_regfile_err_det;
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assign xx_ex5_regfile_err_det = ex5_regfile_err_det;
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assign xx_ex6_regfile_err_det = ex6_regfile_err_det;
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assign xx_ex7_regfile_err_det = ex7_regfile_err_det;
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assign xx_ex8_regfile_err_det = ex8_regfile_err_det;
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assign xx_ex1_perr_sm_instr_v = ex1_perr_sm_instr_v;
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assign xx_ex2_perr_sm_instr_v = ex2_perr_sm_instr_v;
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assign xx_ex3_perr_sm_instr_v = ex3_perr_sm_instr_v;
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assign xx_ex4_perr_sm_instr_v = ex4_perr_sm_instr_v;
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assign xx_ex5_perr_sm_instr_v = ex5_perr_sm_instr_v;
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assign xx_ex6_perr_sm_instr_v = ex6_perr_sm_instr_v;
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assign xx_ex7_perr_sm_instr_v = ex7_perr_sm_instr_v;
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assign xx_ex8_perr_sm_instr_v = ex8_perr_sm_instr_v;
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assign xx_perr_tid_l2 = perr_tid_l2;
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assign xx_perr_sm_l2 = perr_sm_l2;
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assign ex4_regfile_err_det_din[0:1] = ex4_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
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assign ex5_regfile_err_det_din[0:1] = ex5_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
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assign ex6_regfile_err_det_din[0:1] = ex6_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
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assign ex7_regfile_err_det_din[0:1] = ex7_regfile_err_det[0:1] & (~cp_flush_1d[0:1]);
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assign xx_ex0_regfile_ue = ex0_regfile_ue;
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assign xx_ex0_regfile_ce = ex0_regfile_ce;
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assign xx_perr_addr_l2 = perr_addr_l2;
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tri_rlmreg_p #(.INIT(0), .WIDTH(9)) exx_regfile_err_det_lat(
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.nclk(nclk),
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.act(tihi),
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.force_t(force_t),
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr[9]),
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.mpw1_b(mpw1_b[9]),
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.mpw2_b(mpw2_b[1]),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.vd(vdd),
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.gd(gnd),
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.scin(exx_regfile_err_det_si[0:8]),
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.scout(exx_regfile_err_det_so[0:8]),
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//-------------------------------------------
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.din({ ex4_regfile_err_det_din[0:1],
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ex5_regfile_err_det_din[0:1],
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ex6_regfile_err_det_din[0:1],
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ex7_regfile_err_det_din[0:1],
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ex6_perr_sm_instr_v
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}),
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//-------------------------------------------
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.dout({ ex5_regfile_err_det[0:1],
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ex6_regfile_err_det[0:1],
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ex7_regfile_err_det[0:1],
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ex8_regfile_err_det[0:1],
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ex7_is_fixperr
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})
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);
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//-------------------------------------------
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tri_rlmreg_p #(.INIT(0), .WIDTH(4)) ex4_ctl_perr(
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.nclk(nclk),
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.act(tihi),
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.force_t(force_t),
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr[4]),
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.mpw1_b(mpw1_b[4]),
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.mpw2_b(mpw2_b[0]),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.vd(vdd),
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.gd(gnd),
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.scin(ex4_ctl_perr_si[0:3]),
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.scout(ex4_ctl_perr_so[0:3]),
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//-------------------------------------------
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.din({
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ex3_fpr_reg_perr[0:1],
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ex3_sto_perr[0:1]
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}),
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//-------------------------------------------
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.dout( {
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ex4_regfile_err_det[0:1],
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ex4_sto_err_det[0:1]
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})
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);
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//-------------------------------------------
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tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex2_perr(
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.nclk(nclk),
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.act(tiup),
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.force_t(force_t),
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.d_mode(tiup),
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.delay_lclkr(delay_lclkr[2]),
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.mpw1_b(mpw1_b[2]),
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.mpw2_b(mpw2_b[0]),
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.thold_b(thold_0_b),
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.sg(sg_0),
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.vd(vdd),
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.gd(gnd),
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.scin(ex2_perr_si[0:23]),
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.scout(ex2_perr_so[0:23]),
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.din({ex1_instr_frs[0:5],
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ex1_instr_fra[0:5],
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ex1_instr_frb[0:5],
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ex1_instr_frc[0:5]
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}),
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//-------------------------------------------
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.dout({ex2_instr_frs[0:5],
|
|
ex2_instr_fra[0:5],
|
|
ex2_instr_frb[0:5],
|
|
ex2_instr_frc[0:5]
|
|
})
|
|
);
|
|
|
|
//-------------------------------------------
|
|
tri_rlmreg_p #(.INIT(0), .WIDTH(24)) ex3_perr(
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(force_t),
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[3]),
|
|
.mpw1_b(mpw1_b[3]),
|
|
.mpw2_b(mpw2_b[0]),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.scin(ex3_perr_si[0:23]),
|
|
.scout(ex3_perr_so[0:23]),
|
|
.din({ex2_instr_frs[0:5],
|
|
ex2_instr_fra[0:5],
|
|
ex2_instr_frb[0:5],
|
|
ex2_instr_frc[0:5]
|
|
}),
|
|
//-------------------------------------------
|
|
.dout( {ex3_instr_frs[0:5],
|
|
ex3_instr_fra[0:5],
|
|
ex3_instr_frb[0:5],
|
|
ex3_instr_frc[0:5]
|
|
})
|
|
);
|
|
//-------------------------------------------
|
|
|
|
|
|
// Parity Checking
|
|
|
|
assign ex3_a_perr_check = ex3_a_parity_check;
|
|
assign ex3_b_perr_check = ex3_b_parity_check;
|
|
assign ex3_c_perr_check = ex3_c_parity_check;
|
|
assign ex3_s_perr_check = ex3_s_parity_check;
|
|
|
|
|
|
assign ex3_sto_perr[0:1] = {2{(ex3_s_perr_check & ex3_str_v & ~ex3_frs_byp)}} & ex3_instr_v[0:1];
|
|
|
|
assign ex3_sto_parity_err = |(ex3_sto_perr);
|
|
|
|
assign ex3_abc_perr_x = {2{((ex3_a_perr_check & ex3_fra_v) |
|
|
(ex3_b_perr_check & ex3_frb_v) |
|
|
(ex3_c_perr_check & ex3_frc_v)) }};
|
|
|
|
assign ex3_abc_perr_y = (ex3_instr_v[0:1] | ex3_fdivsqrt_start[0:1]);
|
|
|
|
|
|
assign ex3_abc_perr[0:1] = ex3_abc_perr_x[0:1] & ex3_abc_perr_y[0:1];
|
|
|
|
|
|
assign ex3_fpr_perr[0:1] = (ex3_sto_perr[0:1] | ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}};
|
|
|
|
assign ex3_regfile_err_det_any = |(ex3_fpr_perr);
|
|
|
|
assign ex3_fpr_reg_perr[0:1] = ( ex3_abc_perr[0:1]) & (~cp_flush_1d[0:1]) & {2{msr_fp_act}};
|
|
|
|
|
|
assign ex3_f0a_perr = ex3_a_perr_check & ex3_fra_v;
|
|
assign ex3_f0c_perr = ex3_c_perr_check & (ex3_frc_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v));
|
|
assign ex3_f1b_perr = ex3_b_perr_check & (ex3_frb_v | (perr_sm_l2[1] & ex3_perr_sm_instr_v));
|
|
|
|
|
|
assign ex3_f1s_perr = ex3_s_perr_check & ex3_str_v;
|
|
|
|
|
|
assign ex4_regfile_err_det_any = |(ex4_regfile_err_det[0:1]) | |(ex4_sto_err_det[0:1]);
|
|
|
|
|
|
tri_rlmreg_p #(.INIT(4), .WIDTH(3)) perr_sm(
|
|
.nclk(nclk),
|
|
.act(tihi),
|
|
.force_t(force_t),
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[9]),
|
|
.mpw1_b(mpw1_b[9]),
|
|
.mpw2_b(mpw2_b[1]),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.scin(perr_sm_si[0:2]),
|
|
.scout(perr_sm_so[0:2]),
|
|
.din(perr_sm_din[0:2]),
|
|
//-------------------------------------------
|
|
.dout( perr_sm_l2[0:2])
|
|
);
|
|
//-------------------------------------------
|
|
|
|
tri_rlmreg_p #(.INIT(0), .WIDTH(31)) perr_ctl(
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.force_t(force_t),
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[9]),
|
|
.mpw1_b(mpw1_b[9]),
|
|
.mpw2_b(mpw2_b[1]),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.scin(perr_ctl_si[0:30]),
|
|
.scout(perr_ctl_so[0:30]),
|
|
.din({ perr_addr_din[0:5],
|
|
perr_tid_din[0:1],
|
|
spare_unused[0:1],
|
|
perr_move_f0_to_f1,
|
|
perr_move_f1_to_f0,
|
|
rf0_perr_force_c,
|
|
ex0_perr_force_c,
|
|
ex1_perr_force_c,
|
|
new_perr_sm_instr_v,
|
|
rf0_perr_sm_instr_v,
|
|
ex0_perr_sm_instr_v,
|
|
ex1_perr_sm_instr_v,
|
|
ex2_perr_sm_instr_v,
|
|
ex3_perr_sm_instr_v,
|
|
ex4_perr_sm_instr_v,
|
|
ex5_perr_sm_instr_v,
|
|
ex6_perr_sm_instr_v,
|
|
ex7_perr_sm_instr_v,
|
|
ex4_regfile_err_det_any,
|
|
ex5_regfile_err_det_any, // ex3_regfile_err_det, //xu_fu_regfile_seq_beg, // need extra cycles for holdall to take effect
|
|
ex6_regfile_err_det_any,
|
|
regfile_seq_end,
|
|
rf0_regfile_ue,
|
|
rf0_regfile_ce}),
|
|
//-------------------------------------------
|
|
.dout({ perr_addr_l2[0:5],
|
|
perr_tid_l2[0:1],
|
|
spare_unused[0:1],
|
|
perr_move_f0_to_f1_l2,
|
|
perr_move_f1_to_f0_l2,
|
|
ex0_perr_force_c,
|
|
ex1_perr_force_c,
|
|
ex2_perr_force_c,
|
|
rf0_perr_sm_instr_v,
|
|
ex0_perr_sm_instr_v,
|
|
ex1_perr_sm_instr_v,
|
|
ex2_perr_sm_instr_v,
|
|
ex3_perr_sm_instr_v,
|
|
ex4_perr_sm_instr_v,
|
|
ex5_perr_sm_instr_v,
|
|
ex6_perr_sm_instr_v,
|
|
ex7_perr_sm_instr_v,
|
|
ex8_perr_sm_instr_v,
|
|
ex5_regfile_err_det_any,
|
|
ex6_regfile_err_det_any,
|
|
regfile_seq_beg,
|
|
spare_unused[2],
|
|
ex0_regfile_ue,
|
|
ex0_regfile_ce})
|
|
);
|
|
//-------------------------------------------
|
|
|
|
assign rf0_perr_sm_instr_v_b = (~rf0_perr_sm_instr_v);
|
|
|
|
// State 0 = 100 = Default, no parity error
|
|
// State 1 = 010 = Parity error detected. Flush System, and read out both entries
|
|
// State 2 = 001 = Move good to bad, or UE
|
|
|
|
assign perr_sm_running = (~perr_sm_l2[0]);
|
|
assign xx_perr_sm_running = (~perr_sm_l2[0]);
|
|
|
|
// Goto State0 at the end of the sequence. That's either after a UE, or writeback is done
|
|
assign perr_sm_ns[0] = (perr_sm_l2[2] & rf0_regfile_ue) | (perr_sm_l2[2] & ex7_perr_sm_instr_v);
|
|
assign regfile_seq_end = perr_sm_ns[0];
|
|
|
|
// Goto State1 when a parity error is detected.
|
|
assign perr_sm_ns[1] = perr_sm_l2[0] & regfile_seq_beg;
|
|
|
|
// Goto State2 when both sets of data have been read out
|
|
assign perr_sm_ns[2] = perr_sm_l2[1] & ex7_perr_sm_instr_v;
|
|
|
|
// set move decision. Both means Uncorrectable Error
|
|
assign perr_move_f0_to_f1 = (ex3_f1b_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) |
|
|
(perr_move_f0_to_f1_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v)));
|
|
|
|
assign perr_move_f1_to_f0 = (ex3_f0c_perr & ( (perr_sm_l2[1] & ex3_perr_sm_instr_v))) |
|
|
(perr_move_f1_to_f0_l2 & (~(perr_sm_l2[1] & ex3_perr_sm_instr_v)));
|
|
|
|
|
|
assign rf0_perr_move_f0_to_f1 = perr_move_f0_to_f1_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v);
|
|
assign rf0_perr_move_f1_to_f0 = perr_move_f1_to_f0_l2 & (perr_sm_l2[2] & rf0_perr_sm_instr_v);
|
|
assign rf0_perr_fixed_itself = (~(perr_move_f1_to_f0_l2 | perr_move_f0_to_f1_l2)) & (perr_sm_l2[2] & rf0_perr_sm_instr_v); // this is for the case where initially a parity error was detected, but when re-read out of the regfile both copies are correct. We still want to report this.
|
|
|
|
assign rf0_perr_force_c = rf0_perr_move_f0_to_f1 & (~rf0_perr_move_f1_to_f0);
|
|
|
|
assign xx_ex2_perr_force_c = ex2_perr_force_c;
|
|
assign xx_ex2_perr_fsel_ovrd = ex2_perr_sm_instr_v & perr_sm_l2[2]; //cyc // perr_insert
|
|
|
|
|
|
assign perr_sm_din[0:2] = (3'b100 & {3{perr_sm_ns[0]}}) |
|
|
(3'b010 & {3{perr_sm_ns[1]}}) |
|
|
(3'b001 & {3{perr_sm_ns[2]}}) |
|
|
(perr_sm_l2 & {3{(~(|(perr_sm_ns[0:2])))}});
|
|
|
|
// Send a dummy instruction down the pipe for reading or writing the regfiles
|
|
assign new_perr_sm_instr_v = perr_sm_ns[1] | perr_sm_ns[2];
|
|
|
|
// Save the offending address and tid on any parity error and hold.
|
|
assign ex3_capture_addr = ex3_regfile_err_det_any & perr_sm_l2[0] &
|
|
(~ex4_regfile_err_det_any) &
|
|
(~ex5_regfile_err_det_any) & // need to cover the cycles while waiting for rv to hold_all
|
|
(~ex6_regfile_err_det_any) & // safety cycle
|
|
(~regfile_seq_beg);
|
|
|
|
|
|
assign perr_addr_din[0:5] = ((ex3_f0a_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_fra[0:5] :
|
|
((ex3_f1b_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frb[0:5] :
|
|
((ex3_f0c_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frc[0:5] :
|
|
((ex3_f1s_perr & ex3_capture_addr) == 1'b1) ? ex3_instr_frs[0:5] :
|
|
perr_addr_l2[0:5];
|
|
|
|
assign perr_tid_din[0:1] = (ex3_fpr_perr[0:1] & {2{ (ex3_capture_addr)}}) |
|
|
(perr_tid_l2[0:1] & {2{~(ex3_capture_addr)}});
|
|
|
|
//Mux into the FPR address
|
|
// perr_insert
|
|
|
|
assign rf0_frc_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}}));
|
|
|
|
assign rf0_frc_iu_x_b[0:5] = (~(rf0_instr_frc[0:5] & {6{rf0_perr_sm_instr_v_b}}));
|
|
|
|
assign rf0_dcd_frc[0:5] = (~(rf0_frc_perr_x_b[0:5] & rf0_frc_iu_x_b[0:5]));
|
|
|
|
|
|
assign rf0_frb_perr_x_b[0:5] = (~(perr_addr_l2[0:5] & {6{rf0_perr_sm_instr_v}}));
|
|
|
|
assign rf0_frb_iu_x_b[0:5] = (~(rf0_instr_frb[0:5] & {6{rf0_perr_sm_instr_v_b}}));
|
|
|
|
assign rf0_dcd_frb[0:5] = (~(rf0_frb_perr_x_b[0:5] & rf0_frb_iu_x_b[0:5]));
|
|
|
|
assign rf0_dcd_fra[0:5] = rf0_instr_fra[0:5];
|
|
|
|
assign rf0_dcd_tid[0:1] = (rf0_tid[0:1] & {2{rf0_perr_sm_instr_v_b}}) |
|
|
(perr_tid_l2[0:1] & {2{rf0_perr_sm_instr_v}});
|
|
|
|
|
|
// Determine if we have a ue or ce to report to PC
|
|
// state prefixes are for the recirc, not relevant to PC
|
|
assign rf0_regfile_ce = (rf0_perr_move_f0_to_f1 | rf0_perr_move_f1_to_f0 | rf0_perr_fixed_itself) & (~(rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0));
|
|
assign rf0_regfile_ue = rf0_perr_move_f0_to_f1 & rf0_perr_move_f1_to_f0;
|
|
|
|
assign err_regfile_parity[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ce}};
|
|
assign err_regfile_ue[0:1] = perr_tid_l2[0:1] & {2{ex0_regfile_ue}};
|
|
|
|
generate
|
|
if (`THREADS == 1)
|
|
begin : dcd_err_rpt_thr1
|
|
|
|
tri_direct_err_rpt #(.WIDTH(2)) fu_err_rpt(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.err_in({ err_regfile_parity[0],
|
|
err_regfile_ue[0]}),
|
|
.err_out({xx_pc_err_regfile_parity[0],
|
|
xx_pc_err_regfile_ue[0] })
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (`THREADS == 2)
|
|
begin : dcd_err_rpt_thr2
|
|
|
|
tri_direct_err_rpt #(.WIDTH(4)) fu_err_rpt(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.err_in({ err_regfile_parity[0],
|
|
err_regfile_parity[1],
|
|
|
|
err_regfile_ue[0],
|
|
err_regfile_ue[1]
|
|
}),
|
|
.err_out({xx_pc_err_regfile_parity[0],
|
|
xx_pc_err_regfile_parity[1],
|
|
|
|
xx_pc_err_regfile_ue[0],
|
|
xx_pc_err_regfile_ue[1] })
|
|
);
|
|
|
|
end
|
|
endgenerate
|
|
|
|
|
|
|
|
|
|
|
|
|
|
//----------------------------------------------------------------------
|
|
|
|
|
|
assign rv_hold_all_din = ex3_hangcounter_trigger |
|
|
ex3_regfile_err_det_any |
|
|
ex4_regfile_err_det_any |
|
|
ex5_regfile_err_det_any |
|
|
ex6_regfile_err_det_any |
|
|
regfile_seq_beg | perr_sm_running;
|
|
|
|
|
|
tri_rlmreg_p #(.INIT(0), .WIDTH(1)) holdall_lat(
|
|
.nclk(nclk),
|
|
.act(tihi),
|
|
.force_t(force_t),
|
|
.d_mode(tiup),
|
|
.delay_lclkr(delay_lclkr[9]),
|
|
.mpw1_b(mpw1_b[9]),
|
|
.mpw2_b(mpw2_b[1]),
|
|
.thold_b(thold_0_b),
|
|
.sg(sg_0),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.scin(holdall_si[0:0]),
|
|
.scout(holdall_so[0:0]),
|
|
|
|
.din(rv_hold_all_din),
|
|
//-------------------------------------------
|
|
.dout(rv_hold_all_q)
|
|
);
|
|
//-------------------------------------------
|
|
|
|
|
|
assign xx_rv_hold_all = rv_hold_all_q;
|
|
|
|
//-------------------------------------------
|
|
|
|
// perr
|
|
assign ex2_perr_si[0:23] = {ex2_perr_so[1:23], perr_si};
|
|
assign ex3_perr_si[0:23] = {ex3_perr_so[1:23], ex2_perr_so[0]};
|
|
assign perr_sm_si[0:2] = {perr_sm_so[1:2], ex3_perr_so[0]};
|
|
assign perr_ctl_si[0:30] = {perr_ctl_so[1:30], perr_sm_so[0]};
|
|
assign ex4_ctl_perr_si[0:3] = {ex4_ctl_perr_so[1:3], perr_ctl_so[0]};
|
|
assign holdall_si[0] = {ex4_ctl_perr_so[0]};
|
|
assign exx_regfile_err_det_si[0:8] = {exx_regfile_err_det_so[1:8], holdall_so[0]};
|
|
|
|
assign perr_so = exx_regfile_err_det_so[0];
|
|
|
|
// end perr
|
|
|
|
|
|
endmodule
|