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228 lines
7.3 KiB
Verilog
228 lines
7.3 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// Description: Adder Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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// input phase is important
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// (change X (B) by switching xor/xnor )
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module tri_st_add_glbglbci(
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g08,
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t08,
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ci,
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c64_b
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);
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input [0:7] g08;
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input [0:7] t08;
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input ci;
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output [0:7] c64_b;
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wire [0:3] b0_g16_b;
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wire [0:2] b0_t16_b;
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wire [0:1] b0_g32;
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wire [0:0] b0_t32;
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wire [0:3] b1_g16_b;
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wire [0:2] b1_t16_b;
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wire [0:1] b1_g32;
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wire [0:0] b1_t32;
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wire [0:3] b2_g16_b;
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wire [0:2] b2_t16_b;
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wire [0:1] b2_g32;
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wire [0:0] b2_t32;
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wire [0:3] b3_g16_b;
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wire [0:2] b3_t16_b;
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wire [0:1] b3_g32;
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wire [0:0] b3_t32;
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wire [0:3] b4_g16_b;
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wire [0:2] b4_t16_b;
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wire [0:1] b4_g32;
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wire [0:0] b4_t32;
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wire [0:2] b5_g16_b;
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wire [0:1] b5_t16_b;
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wire [0:1] b5_g32;
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wire [0:0] b5_t32;
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wire [0:1] b6_g16_b;
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wire [0:0] b6_t16_b;
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wire [0:0] b6_g32;
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wire [0:0] b7_g16_b;
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wire [0:0] b7_g32;
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wire b0_g56_b;
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wire b0_c64;
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wire [0:0] g08_b;
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wire [0:0] t08_b;
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////#############################
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////## byte 0 <for CO only ??
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////#############################
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assign b0_g16_b[0] = (~(g08[1] | (t08[1] & g08[2])));
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assign b0_g16_b[1] = (~(g08[3] | (t08[3] & g08[4])));
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assign b0_g16_b[2] = (~(g08[5] | (t08[5] & g08[6])));
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assign b0_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
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assign b0_t16_b[0] = (~(t08[1] & t08[2]));
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assign b0_t16_b[1] = (~(t08[3] & t08[4]));
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assign b0_t16_b[2] = (~(t08[5] & t08[6]));
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assign b0_g32[0] = (~(b0_g16_b[0] & (b0_t16_b[0] | b0_g16_b[1])));
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assign b0_g32[1] = (~(b0_g16_b[2] & (b0_t16_b[2] | b0_g16_b[3])));
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assign b0_t32[0] = (~(b0_t16_b[0] | b0_t16_b[1]));
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assign g08_b[0] = (~g08[0]);
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assign t08_b[0] = (~t08[0]);
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assign b0_g56_b = (~(b0_g32[0] | (b0_t32[0] & b0_g32[1]))); //output--
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assign b0_c64 = (~(g08_b[0] & (t08_b[0] | b0_g56_b)));
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assign c64_b[0] = (~(b0_c64));
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////#############################
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////## byte 1
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////#############################
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assign b1_g16_b[0] = (~(g08[1] | (t08[1] & g08[2])));
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assign b1_g16_b[1] = (~(g08[3] | (t08[3] & g08[4])));
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assign b1_g16_b[2] = (~(g08[5] | (t08[5] & g08[6])));
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assign b1_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
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assign b1_t16_b[0] = (~(t08[1] & t08[2]));
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assign b1_t16_b[1] = (~(t08[3] & t08[4]));
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assign b1_t16_b[2] = (~(t08[5] & t08[6]));
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assign b1_g32[0] = (~(b1_g16_b[0] & (b1_t16_b[0] | b1_g16_b[1])));
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assign b1_g32[1] = (~(b1_g16_b[2] & (b1_t16_b[2] | b1_g16_b[3])));
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assign b1_t32[0] = (~(b1_t16_b[0] | b1_t16_b[1]));
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assign c64_b[1] = (~(b1_g32[0] | (b1_t32[0] & b1_g32[1]))); //output--
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////#############################
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////## byte 2
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////#############################
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assign b2_g16_b[0] = (~(g08[2] | (t08[2] & g08[3])));
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assign b2_g16_b[1] = (~(g08[4] | (t08[4] & g08[5])));
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assign b2_g16_b[2] = (~(g08[6]));
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assign b2_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
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assign b2_t16_b[0] = (~(t08[2] & t08[3]));
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assign b2_t16_b[1] = (~(t08[4] & t08[5]));
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assign b2_t16_b[2] = (~(t08[6]));
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assign b2_g32[0] = (~(b2_g16_b[0] & (b2_t16_b[0] | b2_g16_b[1])));
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assign b2_g32[1] = (~(b2_g16_b[2] & (b2_t16_b[2] | b2_g16_b[3])));
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assign b2_t32[0] = (~(b2_t16_b[0] | b2_t16_b[1]));
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assign c64_b[2] = (~(b2_g32[0] | (b2_t32[0] & b2_g32[1]))); //output--
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////#############################
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////## byte 3
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////#############################
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assign b3_g16_b[0] = (~(g08[3] | (t08[3] & g08[4])));
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assign b3_g16_b[1] = (~(g08[5]));
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assign b3_g16_b[2] = (~(g08[6]));
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assign b3_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
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assign b3_t16_b[0] = (~(t08[3] & t08[4]));
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assign b3_t16_b[1] = (~(t08[5]));
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assign b3_t16_b[2] = (~(t08[6]));
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assign b3_g32[0] = (~(b3_g16_b[0] & (b3_t16_b[0] | b3_g16_b[1])));
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assign b3_g32[1] = (~(b3_g16_b[2] & (b3_t16_b[2] | b3_g16_b[3])));
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assign b3_t32[0] = (~(b3_t16_b[0] | b3_t16_b[1]));
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assign c64_b[3] = (~(b3_g32[0] | (b3_t32[0] & b3_g32[1]))); //output--
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////#############################
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////## byte 4
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////#############################
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assign b4_g16_b[0] = (~(g08[4]));
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assign b4_g16_b[1] = (~(g08[5]));
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assign b4_g16_b[2] = (~(g08[6]));
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assign b4_g16_b[3] = (~(g08[7] | (t08[7] & ci)));
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assign b4_t16_b[0] = (~(t08[4]));
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assign b4_t16_b[1] = (~(t08[5]));
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assign b4_t16_b[2] = (~(t08[6]));
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assign b4_g32[0] = (~(b4_g16_b[0] & (b4_t16_b[0] | b4_g16_b[1])));
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assign b4_g32[1] = (~(b4_g16_b[2] & (b4_t16_b[2] | b4_g16_b[3])));
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assign b4_t32[0] = (~(b4_t16_b[0] | b4_t16_b[1]));
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assign c64_b[4] = (~(b4_g32[0] | (b4_t32[0] & b4_g32[1]))); //output--
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////#############################
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////## byte 5
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////#############################
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assign b5_g16_b[0] = (~(g08[5]));
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assign b5_g16_b[1] = (~(g08[6]));
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assign b5_g16_b[2] = (~(g08[7] | (t08[7] & ci)));
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assign b5_t16_b[0] = (~(t08[5]));
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assign b5_t16_b[1] = (~(t08[6]));
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assign b5_g32[0] = (~(b5_g16_b[0] & (b5_t16_b[0] | b5_g16_b[1])));
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assign b5_g32[1] = (~(b5_g16_b[2]));
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assign b5_t32[0] = (~(b5_t16_b[0] | b5_t16_b[1]));
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assign c64_b[5] = (~(b5_g32[0] | (b5_t32[0] & b5_g32[1]))); //output--
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////#############################
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////## byte 6
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////#############################
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assign b6_g16_b[0] = (~(g08[6]));
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assign b6_g16_b[1] = (~(g08[7] | (t08[7] & ci)));
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assign b6_t16_b[0] = (~(t08[6]));
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assign b6_g32[0] = (~(b6_g16_b[0] & (b6_t16_b[0] | b6_g16_b[1])));
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assign c64_b[6] = (~(b6_g32[0])); //output--
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////#############################
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////## byte 7
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////#############################
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assign b7_g16_b[0] = (~(g08[7] | (t08[7] & ci)));
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assign b7_g32[0] = (~(b7_g16_b[0]));
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assign c64_b[7] = (~(b7_g32[0])); //output--
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endmodule
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