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121 lines
5.1 KiB
Verilog
121 lines
5.1 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU ALU or reduce component
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//
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//*****************************************************************************
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module tri_st_or3232(
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d,
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or_hi_b,
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or_lo_b
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);
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input [0:63] d; //data
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output or_hi_b; // upper 32 ORed together
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output or_lo_b; // lower 32 ORed together
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wire [0:31] or_lv1_b;
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wire [0:15] or_lv2;
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wire [0:7] or_lv3_b;
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wire [0:3] or_lv4;
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wire [0:1] or_lv5_b;
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assign or_lv1_b[0] = (~(d[0] | d[1]));
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assign or_lv1_b[1] = (~(d[2] | d[3]));
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assign or_lv1_b[2] = (~(d[4] | d[5]));
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assign or_lv1_b[3] = (~(d[6] | d[7]));
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assign or_lv1_b[4] = (~(d[8] | d[9]));
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assign or_lv1_b[5] = (~(d[10] | d[11]));
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assign or_lv1_b[6] = (~(d[12] | d[13]));
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assign or_lv1_b[7] = (~(d[14] | d[15]));
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assign or_lv1_b[8] = (~(d[16] | d[17]));
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assign or_lv1_b[9] = (~(d[18] | d[19]));
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assign or_lv1_b[10] = (~(d[20] | d[21]));
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assign or_lv1_b[11] = (~(d[22] | d[23]));
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assign or_lv1_b[12] = (~(d[24] | d[25]));
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assign or_lv1_b[13] = (~(d[26] | d[27]));
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assign or_lv1_b[14] = (~(d[28] | d[29]));
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assign or_lv1_b[15] = (~(d[30] | d[31]));
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assign or_lv1_b[16] = (~(d[32] | d[33]));
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assign or_lv1_b[17] = (~(d[34] | d[35]));
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assign or_lv1_b[18] = (~(d[36] | d[37]));
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assign or_lv1_b[19] = (~(d[38] | d[39]));
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assign or_lv1_b[20] = (~(d[40] | d[41]));
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assign or_lv1_b[21] = (~(d[42] | d[43]));
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assign or_lv1_b[22] = (~(d[44] | d[45]));
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assign or_lv1_b[23] = (~(d[46] | d[47]));
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assign or_lv1_b[24] = (~(d[48] | d[49]));
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assign or_lv1_b[25] = (~(d[50] | d[51]));
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assign or_lv1_b[26] = (~(d[52] | d[53]));
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assign or_lv1_b[27] = (~(d[54] | d[55]));
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assign or_lv1_b[28] = (~(d[56] | d[57]));
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assign or_lv1_b[29] = (~(d[58] | d[59]));
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assign or_lv1_b[30] = (~(d[60] | d[61]));
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assign or_lv1_b[31] = (~(d[62] | d[63]));
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assign or_lv2[0] = (~(or_lv1_b[0] & or_lv1_b[1]));
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assign or_lv2[1] = (~(or_lv1_b[2] & or_lv1_b[3]));
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assign or_lv2[2] = (~(or_lv1_b[4] & or_lv1_b[5]));
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assign or_lv2[3] = (~(or_lv1_b[6] & or_lv1_b[7]));
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assign or_lv2[4] = (~(or_lv1_b[8] & or_lv1_b[9]));
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assign or_lv2[5] = (~(or_lv1_b[10] & or_lv1_b[11]));
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assign or_lv2[6] = (~(or_lv1_b[12] & or_lv1_b[13]));
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assign or_lv2[7] = (~(or_lv1_b[14] & or_lv1_b[15]));
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assign or_lv2[8] = (~(or_lv1_b[16] & or_lv1_b[17]));
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assign or_lv2[9] = (~(or_lv1_b[18] & or_lv1_b[19]));
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assign or_lv2[10] = (~(or_lv1_b[20] & or_lv1_b[21]));
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assign or_lv2[11] = (~(or_lv1_b[22] & or_lv1_b[23]));
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assign or_lv2[12] = (~(or_lv1_b[24] & or_lv1_b[25]));
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assign or_lv2[13] = (~(or_lv1_b[26] & or_lv1_b[27]));
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assign or_lv2[14] = (~(or_lv1_b[28] & or_lv1_b[29]));
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assign or_lv2[15] = (~(or_lv1_b[30] & or_lv1_b[31]));
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assign or_lv3_b[0] = (~(or_lv2[0] | or_lv2[1]));
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assign or_lv3_b[1] = (~(or_lv2[2] | or_lv2[3]));
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assign or_lv3_b[2] = (~(or_lv2[4] | or_lv2[5]));
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assign or_lv3_b[3] = (~(or_lv2[6] | or_lv2[7]));
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assign or_lv3_b[4] = (~(or_lv2[8] | or_lv2[9]));
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assign or_lv3_b[5] = (~(or_lv2[10] | or_lv2[11]));
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assign or_lv3_b[6] = (~(or_lv2[12] | or_lv2[13]));
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assign or_lv3_b[7] = (~(or_lv2[14] | or_lv2[15]));
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assign or_lv4[0] = (~(or_lv3_b[0] & or_lv3_b[1]));
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assign or_lv4[1] = (~(or_lv3_b[2] & or_lv3_b[3]));
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assign or_lv4[2] = (~(or_lv3_b[4] & or_lv3_b[5]));
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assign or_lv4[3] = (~(or_lv3_b[6] & or_lv3_b[7]));
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assign or_lv5_b[0] = (~(or_lv4[0] | or_lv4[1]));
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assign or_lv5_b[1] = (~(or_lv4[2] | or_lv4[3]));
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assign or_hi_b = or_lv5_b[0]; // rename --output--
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assign or_lo_b = or_lv5_b[1]; // rename --output--
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endmodule
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