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283 lines
11 KiB
Verilog
283 lines
11 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU Rotate - Insert Component
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//
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//*****************************************************************************
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module tri_st_rot_ins(
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ins_log_fcn,
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ins_cmp_byt,
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ins_sra_wd,
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ins_sra_dw,
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ins_xtd_byte,
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ins_xtd_half,
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ins_xtd_wd,
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ins_prtyw,
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ins_prtyd,
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data0_i,
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data1_i,
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mrg_byp_log,
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res_ins
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);
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input [0:3] ins_log_fcn; // use pass ra for rlwimi
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// rs, ra/rb
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// 0000 => "0"
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// 0001 => rs AND rb
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// 0010 => rs AND !rb
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// 0011 => rs
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// 0100 => !rs and RB
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// 0101 => RB
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// 0110 => rs xor RB
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// 0111 => rs or RB
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// 1000 => rs nor RB
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// 1001 => rs xnor RB (use for cmp-byt)
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// 1010 => !RB
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// 1011 => rs or !rb
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// 1100 => !rs
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// 1101 => rs nand !rb, !rs or rb
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// 1110 => rs nand rb ...
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// 1111 => "1"
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input ins_cmp_byt;
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input ins_sra_wd;
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input ins_sra_dw;
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input ins_xtd_byte; // use with xtd
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input ins_xtd_half; // use with xtd
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input ins_xtd_wd; // use with xtd, sra
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input ins_prtyw;
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input ins_prtyd;
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input [0:63] data0_i; //data input (rs)
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input [0:63] data1_i; //data input (ra|rb)
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output [0:63] mrg_byp_log;
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output [0:63] res_ins; //insert data (also result of logicals)
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wire [0:63] mrg_byp_log_b;
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wire [0:63] res_log;
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wire [0:7] byt_cmp;
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wire [0:7] byt_cmp_b;
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wire [0:63] byt_cmp_bus;
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wire [0:63] sign_xtd_bus;
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wire [0:63] xtd_byte_bus;
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wire [0:63] xtd_half_bus;
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wire [0:63] xtd_wd_bus;
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wire [0:63] sra_dw_bus;
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wire [0:63] sra_wd_bus;
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wire [0:63] res_ins0_b;
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wire [0:63] res_ins1_b;
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wire [0:63] res_ins2_b;
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wire [0:63] res_log0_b;
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wire [0:63] res_log1_b;
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wire [0:63] res_log2_b;
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wire [0:63] res_log3_b;
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wire [0:63] res_log_o0;
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wire [0:63] res_log_o1;
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wire [0:63] res_log_b;
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wire [0:63] res_log2;
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wire [0:3] byt0_cmp2_b;
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wire [0:3] byt1_cmp2_b;
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wire [0:3] byt2_cmp2_b;
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wire [0:3] byt3_cmp2_b;
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wire [0:3] byt4_cmp2_b;
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wire [0:3] byt5_cmp2_b;
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wire [0:3] byt6_cmp2_b;
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wire [0:3] byt7_cmp2_b;
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wire [0:1] byt0_cmp4;
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wire [0:1] byt1_cmp4;
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wire [0:1] byt2_cmp4;
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wire [0:1] byt3_cmp4;
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wire [0:1] byt4_cmp4;
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wire [0:1] byt5_cmp4;
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wire [0:1] byt6_cmp4;
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wire [0:1] byt7_cmp4;
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wire [0:63] sel_cmp_byt;
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wire [0:63] sel_cmp_byt_b;
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wire [0:63] data0_b;
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wire [0:63] data1_b;
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wire [0:63] data0;
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wire [0:63] data1;
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wire prtyhw0;
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wire prtyhw1;
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wire prtyhw2;
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wire prtyhw3;
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wire prtyw0;
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wire prtyw1;
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wire prtyd;
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wire prty0;
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wire prty1;
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assign data0_b = (~data0_i);
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assign data1_b = (~data1_i);
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assign data0 = (~data0_b);
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assign data1 = (~data1_b);
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assign prtyhw0 = data0_i[7] ^ data0_i[15];
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assign prtyhw1 = data0_i[23] ^ data0_i[31];
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assign prtyhw2 = data0_i[39] ^ data0_i[47];
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assign prtyhw3 = data0_i[55] ^ data0_i[63];
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assign prtyw0 = prtyhw0 ^ prtyhw1;
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assign prtyw1 = prtyhw2 ^ prtyhw3;
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assign prtyd = prtyw0 ^ prtyw1;
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assign prty1 = (prtyw1 & ins_prtyw) | (prtyd & ins_prtyd);
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assign prty0 = (prtyw0 & ins_prtyw);
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assign res_log2[31] = res_log[31] | prty0;
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assign res_log2[63] = res_log[63] | prty1;
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assign res_log2[0:30] = res_log[0:30];
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assign res_log2[32:62] = res_log[32:62];
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assign res_log0_b[0:63] = (~({64{ins_log_fcn[0]}} & data0_b[0:63] & data1_b[0:63]));
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assign res_log1_b[0:63] = (~({64{ins_log_fcn[1]}} & data0_b[0:63] & data1[0:63]));
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assign res_log2_b[0:63] = (~({64{ins_log_fcn[2]}} & data0[0:63] & data1_b[0:63]));
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assign res_log3_b[0:63] = (~({64{ins_log_fcn[3]}} & data0[0:63] & data1[0:63]));
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assign res_log_o0[0:63] = (~(res_log0_b[0:63] & res_log1_b[0:63]));
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assign res_log_o1[0:63] = (~(res_log2_b[0:63] & res_log3_b[0:63]));
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assign res_log_b[0:63] = (~(res_log_o0[0:63] | res_log_o1[0:63]));
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assign res_log[0:63] = (~(res_log_b[0:63]));
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assign mrg_byp_log_b[0:63] = (~(res_log[0:63]));
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assign mrg_byp_log[0:63] = (~(mrg_byp_log_b[0:63]));
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assign byt0_cmp2_b[0] = (~(res_log[0] & res_log[1]));
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assign byt0_cmp2_b[1] = (~(res_log[2] & res_log[3]));
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assign byt0_cmp2_b[2] = (~(res_log[4] & res_log[5]));
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assign byt0_cmp2_b[3] = (~(res_log[6] & res_log[7]));
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assign byt1_cmp2_b[0] = (~(res_log[8] & res_log[9]));
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assign byt1_cmp2_b[1] = (~(res_log[10] & res_log[11]));
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assign byt1_cmp2_b[2] = (~(res_log[12] & res_log[13]));
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assign byt1_cmp2_b[3] = (~(res_log[14] & res_log[15]));
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assign byt2_cmp2_b[0] = (~(res_log[16] & res_log[17]));
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assign byt2_cmp2_b[1] = (~(res_log[18] & res_log[19]));
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assign byt2_cmp2_b[2] = (~(res_log[20] & res_log[21]));
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assign byt2_cmp2_b[3] = (~(res_log[22] & res_log[23]));
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assign byt3_cmp2_b[0] = (~(res_log[24] & res_log[25]));
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assign byt3_cmp2_b[1] = (~(res_log[26] & res_log[27]));
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assign byt3_cmp2_b[2] = (~(res_log[28] & res_log[29]));
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assign byt3_cmp2_b[3] = (~(res_log[30] & res_log[31]));
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assign byt4_cmp2_b[0] = (~(res_log[32] & res_log[33]));
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assign byt4_cmp2_b[1] = (~(res_log[34] & res_log[35]));
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assign byt4_cmp2_b[2] = (~(res_log[36] & res_log[37]));
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assign byt4_cmp2_b[3] = (~(res_log[38] & res_log[39]));
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assign byt5_cmp2_b[0] = (~(res_log[40] & res_log[41]));
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assign byt5_cmp2_b[1] = (~(res_log[42] & res_log[43]));
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assign byt5_cmp2_b[2] = (~(res_log[44] & res_log[45]));
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assign byt5_cmp2_b[3] = (~(res_log[46] & res_log[47]));
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assign byt6_cmp2_b[0] = (~(res_log[48] & res_log[49]));
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assign byt6_cmp2_b[1] = (~(res_log[50] & res_log[51]));
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assign byt6_cmp2_b[2] = (~(res_log[52] & res_log[53]));
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assign byt6_cmp2_b[3] = (~(res_log[54] & res_log[55]));
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assign byt7_cmp2_b[0] = (~(res_log[56] & res_log[57]));
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assign byt7_cmp2_b[1] = (~(res_log[58] & res_log[59]));
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assign byt7_cmp2_b[2] = (~(res_log[60] & res_log[61]));
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assign byt7_cmp2_b[3] = (~(res_log[62] & res_log[63]));
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assign byt0_cmp4[0] = (~(byt0_cmp2_b[0] | byt0_cmp2_b[1]));
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assign byt0_cmp4[1] = (~(byt0_cmp2_b[2] | byt0_cmp2_b[3]));
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assign byt1_cmp4[0] = (~(byt1_cmp2_b[0] | byt1_cmp2_b[1]));
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assign byt1_cmp4[1] = (~(byt1_cmp2_b[2] | byt1_cmp2_b[3]));
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assign byt2_cmp4[0] = (~(byt2_cmp2_b[0] | byt2_cmp2_b[1]));
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assign byt2_cmp4[1] = (~(byt2_cmp2_b[2] | byt2_cmp2_b[3]));
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assign byt3_cmp4[0] = (~(byt3_cmp2_b[0] | byt3_cmp2_b[1]));
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assign byt3_cmp4[1] = (~(byt3_cmp2_b[2] | byt3_cmp2_b[3]));
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assign byt4_cmp4[0] = (~(byt4_cmp2_b[0] | byt4_cmp2_b[1]));
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assign byt4_cmp4[1] = (~(byt4_cmp2_b[2] | byt4_cmp2_b[3]));
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assign byt5_cmp4[0] = (~(byt5_cmp2_b[0] | byt5_cmp2_b[1]));
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assign byt5_cmp4[1] = (~(byt5_cmp2_b[2] | byt5_cmp2_b[3]));
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assign byt6_cmp4[0] = (~(byt6_cmp2_b[0] | byt6_cmp2_b[1]));
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assign byt6_cmp4[1] = (~(byt6_cmp2_b[2] | byt6_cmp2_b[3]));
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assign byt7_cmp4[0] = (~(byt7_cmp2_b[0] | byt7_cmp2_b[1]));
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assign byt7_cmp4[1] = (~(byt7_cmp2_b[2] | byt7_cmp2_b[3]));
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assign byt_cmp_b[0] = (~(byt0_cmp4[0] & byt0_cmp4[1]));
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assign byt_cmp_b[1] = (~(byt1_cmp4[0] & byt1_cmp4[1]));
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assign byt_cmp_b[2] = (~(byt2_cmp4[0] & byt2_cmp4[1]));
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assign byt_cmp_b[3] = (~(byt3_cmp4[0] & byt3_cmp4[1]));
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assign byt_cmp_b[4] = (~(byt4_cmp4[0] & byt4_cmp4[1]));
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assign byt_cmp_b[5] = (~(byt5_cmp4[0] & byt5_cmp4[1]));
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assign byt_cmp_b[6] = (~(byt6_cmp4[0] & byt6_cmp4[1]));
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assign byt_cmp_b[7] = (~(byt7_cmp4[0] & byt7_cmp4[1]));
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assign byt_cmp[0] = (~(byt_cmp_b[0]));
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assign byt_cmp[1] = (~(byt_cmp_b[1]));
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assign byt_cmp[2] = (~(byt_cmp_b[2]));
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assign byt_cmp[3] = (~(byt_cmp_b[3]));
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assign byt_cmp[4] = (~(byt_cmp_b[4]));
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assign byt_cmp[5] = (~(byt_cmp_b[5]));
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assign byt_cmp[6] = (~(byt_cmp_b[6]));
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assign byt_cmp[7] = (~(byt_cmp_b[7]));
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assign byt_cmp_bus[0:7] = {8{byt_cmp[0]}};
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assign byt_cmp_bus[8:15] = {8{byt_cmp[1]}};
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assign byt_cmp_bus[16:23] = {8{byt_cmp[2]}};
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assign byt_cmp_bus[24:31] = {8{byt_cmp[3]}};
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assign byt_cmp_bus[32:39] = {8{byt_cmp[4]}};
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assign byt_cmp_bus[40:47] = {8{byt_cmp[5]}};
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assign byt_cmp_bus[48:55] = {8{byt_cmp[6]}};
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assign byt_cmp_bus[56:63] = {8{byt_cmp[7]}};
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assign xtd_byte_bus[0:63] = {{57{data0[56]}}, data0[57:63]};
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assign xtd_half_bus[0:63] = {{49{data0[48]}}, data0[49:63]};
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assign xtd_wd_bus[0:63] = {{33{data0[32]}}, data0[33:63]};
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assign sra_wd_bus[0:63] = {64{data0[32]}}; // all the bits for sra
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assign sra_dw_bus[0:63] = {64{data0[0]}}; // all the bits for sra
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assign sign_xtd_bus[0:63] = ({64{ins_xtd_byte}} & xtd_byte_bus[0:63]) |
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({64{ins_xtd_half}} & xtd_half_bus[0:63]) |
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({64{ins_xtd_wd}} & xtd_wd_bus[0:63]) |
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({64{ins_sra_wd}} & sra_wd_bus[0:63]) |
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({64{ins_sra_dw}} & sra_dw_bus[0:63]);
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assign sel_cmp_byt = {64{ins_cmp_byt}};
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assign sel_cmp_byt_b = ~{64{ins_cmp_byt}};
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assign res_ins0_b[0:63] = (~(sel_cmp_byt & byt_cmp_bus[0:63]));
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assign res_ins1_b[0:63] = (~(sel_cmp_byt_b & res_log2[0:63]));
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assign res_ins2_b[0:63] = (~(sign_xtd_bus[0:63]));
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assign res_ins[0:63] = (~(res_ins0_b[0:63] & res_ins1_b[0:63] & res_ins2_b[0:63])); //output--
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endmodule
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