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260 lines
11 KiB
Verilog
260 lines
11 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// Description: XU Rotate - Rotate Component
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//
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//*****************************************************************************
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module tri_st_rot_rol64(
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word,
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right,
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amt,
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data_i,
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res_rot
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);
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input [0:1] word; // PPC word mode rotate <2 copies>
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input [0:2] right; // emulate a shift right with a rotate left <2 copies>
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input [0:5] amt; // shift amout [0:63]
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input [0:63] data_i; // data to be shifted
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output [0:63] res_rot; // mask shows which rotator bits to keep in the result.
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wire [0:2] right_b;
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wire [0:5] amt_b;
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wire [0:1] word_b;
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wire [0:31] word_bus;
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wire [0:31] word_bus_b;
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wire [0:31] data_i0_adj_b;
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wire [0:63] data_i_adj;
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wire [0:63] data_i1_adj_b;
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wire [0:63] rolx16_0;
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wire [0:63] rolx16_1;
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wire [0:63] rolx16_2;
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wire [0:63] rolx16_3;
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wire [0:63] rolx04_0;
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wire [0:63] rolx04_1;
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wire [0:63] rolx04_2;
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wire [0:63] rolx04_3;
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wire [0:63] rolx01_0;
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wire [0:63] rolx01_1;
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wire [0:63] rolx01_2;
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wire [0:63] rolx01_3;
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wire [0:63] rolx01_4;
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wire [0:63] shd16;
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wire [0:63] shd16_0_b;
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wire [0:63] shd16_1_b;
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wire [0:63] shd04;
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wire [0:63] shd04_0_b;
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wire [0:63] shd04_1_b;
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wire [0:63] shd01_0_b;
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wire [0:63] shd01_1_b;
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wire [0:63] shd01_2_b;
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wire [0:3] x16_lft_b;
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wire [0:3] x16_rgt_b;
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wire [0:3] lftx16;
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wire [0:3] x04_lft_b;
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wire [0:3] x04_rgt_b;
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wire [0:3] lftx04;
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wire [0:3] x01_lft_b;
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wire [0:3] x01_rgt_b;
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wire [0:4] lftx01;
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wire [0:4] lftx01_inv;
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wire [0:4] lftx01_buf0;
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wire [0:4] lftx01_buf1;
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wire [0:3] lftx04_inv;
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wire [0:3] lftx04_buf0;
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wire [0:3] lftx04_buf1;
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wire [0:3] lftx16_inv;
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wire [0:3] lftx16_buf0;
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wire [0:3] lftx16_buf1;
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wire [0:63] lftx16_0_bus;
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wire [0:63] lftx16_1_bus;
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wire [0:63] lftx16_2_bus;
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wire [0:63] lftx16_3_bus;
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wire [0:63] lftx04_0_bus;
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wire [0:63] lftx04_1_bus;
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wire [0:63] lftx04_2_bus;
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wire [0:63] lftx04_3_bus;
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wire [0:63] lftx01_0_bus;
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wire [0:63] lftx01_1_bus;
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wire [0:63] lftx01_2_bus;
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wire [0:63] lftx01_3_bus;
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wire [0:63] lftx01_4_bus;
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// -------------------------------------------------------------
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// how the ppc emulates a rot32 using rot64 hardware.
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// this makes the wrapping corect for the low order 32 bits.
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// upper 32 result bits a garbage
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//--------------------------------------------------------------
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assign word_b[0:1] = (~word[0:1]);
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assign word_bus_b[0:15] = {16{word_b[0]}};
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assign word_bus_b[16:31] = {16{word_b[1]}};
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assign word_bus[0:15] = {16{word[0]}};
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assign word_bus[16:31] = {16{word[1]}};
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assign data_i0_adj_b[0:31] = (~(data_i[0:31] & word_bus_b[0:31]));
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assign data_i1_adj_b[0:31] = (~(data_i[32:63] & word_bus[0:31]));
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assign data_i_adj[0:31] = (~(data_i0_adj_b[0:31] & data_i1_adj_b[0:31]));
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assign data_i1_adj_b[32:63] = (~(data_i[32:63]));
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assign data_i_adj[32:63] = (~(data_i1_adj_b[32:63]));
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//---------------------------------------------------------------
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// decoder without the adder
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//---------------------------------------------------------------
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//rotate right by [n] == rotate_left by width -[n] == !n + 1
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assign right_b[0:2] = (~right[0:2]);
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assign amt_b[0:5] = (~amt[0:5]);
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assign x16_lft_b[0] = (~(right_b[0] & amt_b[0] & amt_b[1]));
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assign x16_lft_b[1] = (~(right_b[0] & amt_b[0] & amt[1]));
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assign x16_lft_b[2] = (~(right_b[0] & amt[0] & amt_b[1]));
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assign x16_lft_b[3] = (~(right_b[0] & amt[0] & amt[1]));
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assign x16_rgt_b[0] = (~(right[0] & amt_b[0] & amt_b[1]));
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assign x16_rgt_b[1] = (~(right[0] & amt_b[0] & amt[1]));
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assign x16_rgt_b[2] = (~(right[0] & amt[0] & amt_b[1]));
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assign x16_rgt_b[3] = (~(right[0] & amt[0] & amt[1]));
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assign lftx16[0] = (~(x16_lft_b[0] & x16_rgt_b[3]));
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assign lftx16[1] = (~(x16_lft_b[1] & x16_rgt_b[2]));
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assign lftx16[2] = (~(x16_lft_b[2] & x16_rgt_b[1]));
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assign lftx16[3] = (~(x16_lft_b[3] & x16_rgt_b[0]));
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assign x04_lft_b[0] = (~(right_b[1] & amt_b[2] & amt_b[3]));
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assign x04_lft_b[1] = (~(right_b[1] & amt_b[2] & amt[3]));
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assign x04_lft_b[2] = (~(right_b[1] & amt[2] & amt_b[3]));
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assign x04_lft_b[3] = (~(right_b[1] & amt[2] & amt[3]));
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assign x04_rgt_b[0] = (~(right[1] & amt_b[2] & amt_b[3]));
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assign x04_rgt_b[1] = (~(right[1] & amt_b[2] & amt[3]));
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assign x04_rgt_b[2] = (~(right[1] & amt[2] & amt_b[3]));
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assign x04_rgt_b[3] = (~(right[1] & amt[2] & amt[3]));
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assign lftx04[0] = (~(x04_lft_b[0] & x04_rgt_b[3]));
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assign lftx04[1] = (~(x04_lft_b[1] & x04_rgt_b[2]));
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assign lftx04[2] = (~(x04_lft_b[2] & x04_rgt_b[1]));
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assign lftx04[3] = (~(x04_lft_b[3] & x04_rgt_b[0]));
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assign x01_lft_b[0] = (~(right_b[2] & amt_b[4] & amt_b[5]));
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assign x01_lft_b[1] = (~(right_b[2] & amt_b[4] & amt[5]));
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assign x01_lft_b[2] = (~(right_b[2] & amt[4] & amt_b[5]));
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assign x01_lft_b[3] = (~(right_b[2] & amt[4] & amt[5]));
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assign x01_rgt_b[0] = (~(right[2] & amt_b[4] & amt_b[5]));
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assign x01_rgt_b[1] = (~(right[2] & amt_b[4] & amt[5]));
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assign x01_rgt_b[2] = (~(right[2] & amt[4] & amt_b[5]));
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assign x01_rgt_b[3] = (~(right[2] & amt[4] & amt[5]));
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assign lftx01[0] = (~(x01_lft_b[0])); // the shift is like the +1
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assign lftx01[1] = (~(x01_lft_b[1] & x01_rgt_b[3]));
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assign lftx01[2] = (~(x01_lft_b[2] & x01_rgt_b[2]));
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assign lftx01[3] = (~(x01_lft_b[3] & x01_rgt_b[1]));
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assign lftx01[4] = (~(x01_rgt_b[0]));
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assign lftx16_inv[0:3] = (~(lftx16[0:3]));
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assign lftx16_buf0[0:3] = (~(lftx16_inv[0:3]));
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assign lftx16_buf1[0:3] = (~(lftx16_inv[0:3]));
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assign lftx04_inv[0:3] = (~(lftx04[0:3]));
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assign lftx04_buf0[0:3] = (~(lftx04_inv[0:3]));
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assign lftx04_buf1[0:3] = (~(lftx04_inv[0:3]));
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assign lftx01_inv[0:4] = (~(lftx01[0:4]));
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assign lftx01_buf0[0:4] = (~(lftx01_inv[0:4]));
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assign lftx01_buf1[0:4] = (~(lftx01_inv[0:4]));
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assign lftx16_0_bus[0:31] = {32{lftx16_buf0[0]}};
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assign lftx16_0_bus[32:63] = {32{lftx16_buf1[0]}};
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assign lftx16_1_bus[0:31] = {32{lftx16_buf0[1]}};
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assign lftx16_1_bus[32:63] = {32{lftx16_buf1[1]}};
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assign lftx16_2_bus[0:31] = {32{lftx16_buf0[2]}};
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assign lftx16_2_bus[32:63] = {32{lftx16_buf1[2]}};
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assign lftx16_3_bus[0:31] = {32{lftx16_buf0[3]}};
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assign lftx16_3_bus[32:63] = {32{lftx16_buf1[3]}};
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assign lftx04_0_bus[0:31] = {32{lftx04_buf0[0]}};
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assign lftx04_0_bus[32:63] = {32{lftx04_buf1[0]}};
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assign lftx04_1_bus[0:31] = {32{lftx04_buf0[1]}};
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assign lftx04_1_bus[32:63] = {32{lftx04_buf1[1]}};
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assign lftx04_2_bus[0:31] = {32{lftx04_buf0[2]}};
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assign lftx04_2_bus[32:63] = {32{lftx04_buf1[2]}};
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assign lftx04_3_bus[0:31] = {32{lftx04_buf0[3]}};
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assign lftx04_3_bus[32:63] = {32{lftx04_buf1[3]}};
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assign lftx01_0_bus[0:31] = {32{lftx01_buf0[0]}};
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assign lftx01_0_bus[32:63] = {32{lftx01_buf1[0]}};
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assign lftx01_1_bus[0:31] = {32{lftx01_buf0[1]}};
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assign lftx01_1_bus[32:63] = {32{lftx01_buf1[1]}};
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assign lftx01_2_bus[0:31] = {32{lftx01_buf0[2]}};
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assign lftx01_2_bus[32:63] = {32{lftx01_buf1[2]}};
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assign lftx01_3_bus[0:31] = {32{lftx01_buf0[3]}};
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assign lftx01_3_bus[32:63] = {32{lftx01_buf1[3]}};
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assign lftx01_4_bus[0:31] = {32{lftx01_buf0[4]}};
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assign lftx01_4_bus[32:63] = {32{lftx01_buf1[4]}};
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//---------------------------------------------------------------
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// the shifter
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//---------------------------------------------------------------
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assign rolx16_0[0:63] = data_i_adj[0:63];
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assign rolx16_1[0:63] = {data_i_adj[16:63], data_i_adj[0:15]};
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assign rolx16_2[0:63] = {data_i_adj[32:63], data_i_adj[0:31]};
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assign rolx16_3[0:63] = {data_i_adj[48:63], data_i_adj[0:47]};
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assign shd16_0_b[0:63] = (~((lftx16_0_bus[0:63] & rolx16_0[0:63]) | (lftx16_1_bus[0:63] & rolx16_1[0:63])));
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assign shd16_1_b[0:63] = (~((lftx16_2_bus[0:63] & rolx16_2[0:63]) | (lftx16_3_bus[0:63] & rolx16_3[0:63])));
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assign shd16[0:63] = (~(shd16_0_b[0:63] & shd16_1_b[0:63]));
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assign rolx04_0[0:63] = shd16[0:63];
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assign rolx04_1[0:63] = {shd16[4:63], shd16[0:3]};
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assign rolx04_2[0:63] = {shd16[8:63], shd16[0:7]};
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assign rolx04_3[0:63] = {shd16[12:63], shd16[0:11]};
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assign shd04_0_b[0:63] = (~((lftx04_0_bus[0:63] & rolx04_0[0:63]) | (lftx04_1_bus[0:63] & rolx04_1[0:63])));
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assign shd04_1_b[0:63] = (~((lftx04_2_bus[0:63] & rolx04_2[0:63]) | (lftx04_3_bus[0:63] & rolx04_3[0:63])));
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assign shd04[0:63] = (~(shd04_0_b[0:63] & shd04_1_b[0:63]));
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assign rolx01_0[0:63] = shd04[0:63];
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assign rolx01_1[0:63] = {shd04[1:63], shd04[0]};
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assign rolx01_2[0:63] = {shd04[2:63], shd04[0:1]};
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assign rolx01_3[0:63] = {shd04[3:63], shd04[0:2]};
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assign rolx01_4[0:63] = {shd04[4:63], shd04[0:3]};
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assign shd01_0_b[0:63] = (~((lftx01_0_bus[0:63] & rolx01_0[0:63]) | (lftx01_1_bus[0:63] & rolx01_1[0:63])));
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assign shd01_1_b[0:63] = (~((lftx01_2_bus[0:63] & rolx01_2[0:63]) | (lftx01_3_bus[0:63] & rolx01_3[0:63])));
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assign shd01_2_b[0:63] = (~(lftx01_4_bus[0:63] & rolx01_4[0:63]));
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assign res_rot[0:63] = (~(shd01_0_b[0:63] & shd01_1_b[0:63] & shd01_2_b[0:63]));
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endmodule
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