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35 lines
690 B
Verilog
35 lines
690 B
Verilog
`timescale 1 ps / 1 ps
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module RAM64X1D #(
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parameter [63:0] INIT = 64'h0
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) (
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input WCLK,
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input WE,
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input A0, A1, A2, A3, A4, A5,
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input D,
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output SPO,
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input DPRA0, DPRA1, DPRA2, DPRA3, DPRA4, DPRA5,
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output DPO
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);
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reg [63:0] mem;
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wire [5:0] A;
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wire [5:0] DPRA;
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assign A = {A5, A4, A3, A2, A1, A0};
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assign DPO = mem[{DPRA5, DPRA4, DPRA3, DPRA2, DPRA1, DPRA0}];
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initial begin : INIT_STATE
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mem = INIT;
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end
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always @(posedge WCLK) begin
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if (WE == 1'b1) begin
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mem[A] <= D;
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end
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end
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assign SPO = mem[A];
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endmodule
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