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29 lines
870 B
Verilog
29 lines
870 B
Verilog
(* blackbox *)
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module RAMB36 #(
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parameter integer READ_WIDTH_A = 0,
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parameter integer READ_WIDTH_B = 0,
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parameter SIM_COLLISION_CHECK = "ALL",
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parameter WRITE_MODE_A = "WRITE_FIRST",
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parameter WRITE_MODE_B = "WRITE_FIRST",
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parameter integer WRITE_WIDTH_A = 0,
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parameter integer WRITE_WIDTH_B = 0
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) (
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input ENA, CLKA, SSRA, CASCADEINLATA, CASCADEINREGA, REGCEA,
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input [3:0] WEA,
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input [15:0] ADDRA,
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input [31:0] DIA,
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input [3:0] DIPA,
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output [31:0] DOA,
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output [3:0] DOPA,
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output [3:0] DOPB,
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input ENB, CLKB, SSRB, CASCADEINLATB, CASCADEINREGB, REGCEB,
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input [15:0] ADDRB,
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input [31:0] DIB,
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input [3:0] DIPB,
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input [3:0] WEB,
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output [31:0] DOB,
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output CASCADEOUTLATA, CASCADEOUTREGA,
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output CASCADEOUTLATB, CASCADEOUTREGB
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);
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endmodule
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