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37 lines
698 B
Makefile
37 lines
698 B
Makefile
# a2o - litex
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SIM_BUILD ?= build_node
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SIM ?= icarus
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# icarus
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VERILOG_ROOT = ../../verilog
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# litex version
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NODE = $(VERILOG_ROOT)/a2o_litex
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COMPILE_ARGS = -I$(NODE) -I$(VERILOG_ROOT)/trilib -I$(VERILOG_ROOT)/work -y$(NODE) -y$(VERILOG_ROOT)/unisims -y$(VERILOG_ROOT)/trilib_clk1x -y$(VERILOG_ROOT)/trilib -y$(VERILOG_ROOT)/work
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# other options
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# rtl
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TOPLEVEL_LANG = verilog
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# top-level to enable trace, etc.
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VERILOG_SOURCES = ./cocotb_litex.v
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TOPLEVEL = cocotb
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# python test
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MODULE = tb_node
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TESTCASE = tb_litex
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# cocotb make rules
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include $(shell cocotb-config --makefiles)/Makefile.sim
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build: clean sim fst
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run: sim fst
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vcd: sim
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fst:
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vcd2fst a2olitex.vcd a2olitex.fst
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rm a2olitex.vcd
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