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259 lines
11 KiB
Verilog
259 lines
11 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *!****************************************************************
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// *! FILENAME : tri_128x168_1w_0.v
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// *! DESCRIPTION : 128 Entry x 168 bit x 1 way array
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// *!
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// *!****************************************************************
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`include "tri_a2o.vh"
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module tri_128x168_1w_0(
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gnd,
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vdd,
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vcs,
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nclk,
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act,
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ccflush_dc,
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scan_dis_dc_b,
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scan_diag_dc,
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abst_scan_in,
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repr_scan_in,
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time_scan_in,
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abst_scan_out,
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repr_scan_out,
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time_scan_out,
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lcb_d_mode_dc,
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lcb_clkoff_dc_b,
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lcb_act_dis_dc,
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lcb_mpw1_dc_b,
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lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc,
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lcb_sg_1,
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lcb_time_sg_0,
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lcb_repr_sg_0,
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lcb_abst_sl_thold_0,
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lcb_repr_sl_thold_0,
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lcb_time_sl_thold_0,
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lcb_ary_nsl_thold_0,
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lcb_bolt_sl_thold_0,
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tc_lbist_ary_wrt_thru_dc,
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abist_en_1,
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din_abist,
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abist_cmp_en,
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abist_raw_b_dc,
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data_cmp_abist,
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addr_abist,
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r_wb_abist,
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pc_bo_enable_2,
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pc_bo_reset,
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pc_bo_unload,
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pc_bo_repair,
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pc_bo_shdata,
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pc_bo_select,
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bo_pc_failout,
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bo_pc_diagloop,
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tri_lcb_mpw1_dc_b,
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tri_lcb_mpw2_dc_b,
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tri_lcb_delay_lclkr_dc,
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tri_lcb_clkoff_dc_b,
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tri_lcb_act_dis_dc,
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write_enable,
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addr,
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data_in,
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data_out
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);
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parameter addressable_ports = 128; // number of addressable register in this array
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parameter addressbus_width = 7; // width of the bus to address all ports (2^addressbus_width >= addressable_ports)
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parameter port_bitwidth = 168; // bitwidth of ports
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parameter ways = 1; // number of ways
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// POWER PINS
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inout gnd;
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inout vdd;
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inout vcs;
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// CLOCK and CLOCKCONTROL ports
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input [0:`NCLK_WIDTH-1] nclk;
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input act;
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input ccflush_dc;
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input scan_dis_dc_b;
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input scan_diag_dc;
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input abst_scan_in;
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input repr_scan_in;
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input time_scan_in;
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output abst_scan_out;
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output repr_scan_out;
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output time_scan_out;
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input lcb_d_mode_dc;
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input lcb_clkoff_dc_b;
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input lcb_act_dis_dc;
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input [0:4] lcb_mpw1_dc_b;
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input lcb_mpw2_dc_b;
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input [0:4] lcb_delay_lclkr_dc;
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input lcb_sg_1;
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input lcb_time_sg_0;
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input lcb_repr_sg_0;
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input lcb_abst_sl_thold_0;
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input lcb_repr_sl_thold_0;
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input lcb_time_sl_thold_0;
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input lcb_ary_nsl_thold_0;
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input lcb_bolt_sl_thold_0; // thold for any regs inside backend
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input tc_lbist_ary_wrt_thru_dc;
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input abist_en_1;
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input [0:3] din_abist;
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input abist_cmp_en;
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input abist_raw_b_dc;
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input [0:3] data_cmp_abist;
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input [0:6] addr_abist;
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input r_wb_abist;
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// BOLT-ON
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input pc_bo_enable_2; // general bolt-on enable, probably DC
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input pc_bo_reset; // execute sticky bit decode
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input pc_bo_unload;
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input pc_bo_repair; // load repair reg
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input pc_bo_shdata; // shift data for timing write
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input pc_bo_select; // select for mask and hier writes
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output bo_pc_failout; // fail/no-fix reg
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output bo_pc_diagloop;
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input tri_lcb_mpw1_dc_b;
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input tri_lcb_mpw2_dc_b;
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input tri_lcb_delay_lclkr_dc;
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input tri_lcb_clkoff_dc_b;
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input tri_lcb_act_dis_dc;
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// PORTS
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input write_enable;
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input [0:addressbus_width-1] addr;
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input [0:port_bitwidth-1] data_in;
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output [0:port_bitwidth-1] data_out;
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// tri_128x168_1w_0
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parameter ramb_base_width = 36;
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parameter ramb_base_addr = 9;
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parameter ramb_width_mult = (port_bitwidth - 1)/ramb_base_width + 1; // # of RAMB's per way
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// Configuration Statement for NCsim
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//for all:RAMB16_S36_S36 use entity unisim.RAMB16_S36_S36;
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wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_in;
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wire [0:(ramb_base_width*ramb_width_mult-1)] ramb_data_out[0:ways-1];
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wire [0:ramb_base_addr-1] ramb_addr;
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wire [0:ways-1] write;
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wire tidn;
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(* analysis_not_referenced="true" *)
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wire unused;
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wire [0:(ramb_base_width*ramb_width_mult-1)] unused_dob;
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generate
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begin
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assign tidn = 1'b0;
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if (addressbus_width < ramb_base_addr)
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begin
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assign ramb_addr[0:(ramb_base_addr - addressbus_width - 1)] = {(ramb_base_addr-addressbus_width){1'b0}};
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assign ramb_addr[ramb_base_addr - addressbus_width:ramb_base_addr - 1] = addr;
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end
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if (addressbus_width >= ramb_base_addr)
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begin
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assign ramb_addr = addr[addressbus_width - ramb_base_addr:addressbus_width - 1];
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end
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genvar i;
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for (i = 0; i < (ramb_base_width * ramb_width_mult); i = i + 1)
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begin : din
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if (i < port_bitwidth)
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begin
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assign ramb_data_in[i] = data_in[i];
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end
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if (i >= port_bitwidth)
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begin
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assign ramb_data_in[i] = 1'b0;
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end
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end
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genvar w;
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for (w = 0; w < ways; w = w + 1)
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begin : aw
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assign write[w] = write_enable;
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genvar x;
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for (x = 0; x < ramb_width_mult; x = x + 1)
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begin : ax
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RAMB16_S36_S36
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#(.SIM_COLLISION_CHECK("NONE")) // all, none, warning_only, generate_x_only
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ram(
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.DOA(ramb_data_out[w][x * ramb_base_width:x * ramb_base_width + 31]),
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.DOB(unused_dob[x * ramb_base_width:x * ramb_base_width + 31]),
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.DOPA(ramb_data_out[w][x * ramb_base_width + 32:x * ramb_base_width + 35]),
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.DOPB(unused_dob[x * ramb_base_width + 32:x * ramb_base_width + 35]),
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.ADDRA(ramb_addr),
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.ADDRB(ramb_addr),
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.CLKA(nclk[0]),
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.CLKB(tidn),
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.DIA(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
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.DIB(ramb_data_in[x * ramb_base_width:x * ramb_base_width + 31]),
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.DIPA(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
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.DIPB(ramb_data_in[x * ramb_base_width + 32:x * ramb_base_width + 35]),
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.ENA(act),
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.ENB(tidn),
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.SSRA(nclk[1]),
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.SSRB(tidn),
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.WEA(write[w]),
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.WEB(tidn)
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);
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end //ax
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assign data_out[w * port_bitwidth:((w + 1) * port_bitwidth) - 1] = ramb_data_out[w][0:port_bitwidth - 1];
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end //aw
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end
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endgenerate
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assign abst_scan_out = abst_scan_in;
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assign repr_scan_out = repr_scan_in;
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assign time_scan_out = time_scan_in;
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assign bo_pc_failout = 1'b0;
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assign bo_pc_diagloop = 1'b0;
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assign unused = |({ramb_data_out[0][port_bitwidth:ramb_base_width * ramb_width_mult - 1], ccflush_dc, scan_dis_dc_b, scan_diag_dc, lcb_d_mode_dc, lcb_clkoff_dc_b, lcb_act_dis_dc, lcb_mpw1_dc_b, lcb_mpw2_dc_b, lcb_delay_lclkr_dc, lcb_sg_1, lcb_time_sg_0, lcb_repr_sg_0, lcb_abst_sl_thold_0, lcb_repr_sl_thold_0, lcb_time_sl_thold_0, lcb_ary_nsl_thold_0, lcb_bolt_sl_thold_0, tc_lbist_ary_wrt_thru_dc, abist_en_1, din_abist, abist_cmp_en, abist_raw_b_dc, data_cmp_abist, addr_abist, r_wb_abist, pc_bo_enable_2, pc_bo_reset, pc_bo_unload, pc_bo_repair, pc_bo_shdata, pc_bo_select, tri_lcb_mpw1_dc_b, tri_lcb_mpw2_dc_b, tri_lcb_delay_lclkr_dc, tri_lcb_clkoff_dc_b, tri_lcb_act_dis_dc, gnd, vdd, vcs, nclk, unused_dob});
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endmodule
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