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337 lines
14 KiB
Verilog
337 lines
14 KiB
Verilog
// © IBM Corp. 2022
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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// A2L2 bridge
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// 1. interface to a sim mem[]
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// 2. interface to wb (could use mem for l2 also)
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a2l2wb n0(
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parameter MEM_QW = 16384;
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)
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(
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input clk,
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input rst,
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input ac_an_req_pwr_token,
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input ac_an_req,
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input [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra,
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input [0:5] ac_an_req_ttype,
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input [0:2] ac_an_req_thread,
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input [0:4] ac_an_req_ld_core_tag,
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input [0:2] ac_an_req_ld_xfr_len,
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input ac_an_req_wimg_w,
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input ac_an_req_wimg_i,
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input ac_an_req_wimg_m,
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input ac_an_req_wimg_g,
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input ac_an_req_endian,
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input [0:3] ac_an_req_user_defined,
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input [0:3] ac_an_req_spare_ctrl_a0,
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input ac_an_st_data_pwr_token,
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input [0:31] ac_an_st_byte_enbl,
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input [0:255] ac_an_st_data,
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output an_ac_reld_data_vld,
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output [0:4] an_ac_reld_core_tag,
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output [0:127] an_ac_reld_data,
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output [58:59] an_ac_reld_qw,
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output an_ac_reld_ecc_err,
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output an_ac_reld_ecc_err_ue,
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output an_ac_reld_data_coming,
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output an_ac_reld_ditc,
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output an_ac_reld_crit_qw,
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output an_ac_reld_l1_dump,
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output [0:3] an_ac_req_spare_ctrl_a1,
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output [0:`THREADS-1] an_ac_sync_ack,
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output an_ac_req_ld_pop,
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output an_ac_req_st_pop,
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output an_ac_req_st_gather,
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output [0:`THREADS-1] an_ac_stcx_complete,
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output [0:`THREADS-1] an_ac_stcx_pass,
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output [0:`THREADS-1] an_ac_reservation_vld,
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output an_ac_icbi_ack,
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output [0:1] an_ac_icbi_ack_thread,
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output an_ac_back_inv,
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output [64-`REAL_IFAR_WIDTH:63] an_ac_back_inv_addr,
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output [0:4] an_ac_back_inv_target,
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output an_ac_back_inv_local,
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output an_ac_back_inv_lbit,
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output an_ac_back_inv_gs,
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output an_ac_back_inv_ind,
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output [0:7] an_ac_back_inv_lpar_id,
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input ac_an_back_inv_reject,
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input [0:7] ac_an_lpar_id,
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output [0:31] mem_adr,
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input [0:127] mem_dat,
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output mem_wr_val,
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output [0:127] mem_wr_dat,
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output wb_i_stb,
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output wb_i_cyc,
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output [31:0] wb_i_adr,
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input wb_i_ack,
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input [31:0] wb_i_datr,
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output wb_d_stb,
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output wb_d_cyc,
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output [31:0] wb_d_adr,
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output wb_d_we,
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output [3:0] wb_d_sel,
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output [31:0] wb_d_datw,
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input wb_d_ack,
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input [31:0] wb_d_datr
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);
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// unsupported right now
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assign an_ac_sync_ack = 0;
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assign an_ac_stcx_complete = 0;
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assign an_ac_stcx_pass = 0;
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assign an_ac_reservation_vld = 0;
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assign an_ac_icbi_ack = 0;
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assign an_ac_icbi_ack_thread = 0;
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assign an_ac_back_inv = 0;
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assign an_ac_back_inv_addr = 0;
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assign an_ac_back_inv_target = 0;
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assign an_ac_back_inv_local = 0;
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assign an_ac_back_inv_lbit = 0;
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assign an_ac_back_inv_gs = 0;
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assign an_ac_back_inv_ind = 0;
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assign an_ac_back_inv_lpar_id = 0;
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assign an_ac_req_st_gather = 0;
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assign an_ac_req_spare_ctrl_a1 = 0;
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assign an_ac_reld_l1_dump = 0;
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wire [0:4] cmdseq_d;
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reg [0:4] cmdseq_q;
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wire [0:31+`REAL_IFAR_WIDTH] req_d;
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reg [0:31+`REAL_IFAR_WIDTH] req_q;
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wire [0:31+256] std_d;
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reg [0:31+256] std_q;
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reg std_q
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reg req_tkn_q;
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reg std_tkn_q;
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wire [0:255] rld_d;
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reg [0:255] rld_q;
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wire req_ld_val;
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wire req_st_val;
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wire [64-`REAL_IFAR_WIDTH:63] req_adr;
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wire [0:127] st_alg_data;
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wire [0:127] st_mask;
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wire rld_coming;
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wire rld_valid;
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wire rld_done;
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wire [0:1] rld_qw;
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wire idle;
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//reg [0:127] mem[MEM_QW];
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// todo
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/*
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input ac_an_req_pwr_token,
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input ac_an_req,
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input [64-`REAL_IFAR_WIDTH:63] ac_an_req_ra,
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input [0:5] ac_an_req_ttype,
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input [0:2] ac_an_req_thread,
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input [0:4] ac_an_req_ld_core_tag,
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input [0:2] ac_an_req_ld_xfr_len,
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input ac_an_req_wimg_w,
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input ac_an_req_wimg_i,
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input ac_an_req_wimg_m,
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input ac_an_req_wimg_g,
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input ac_an_req_endian,
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input [0:3] ac_an_req_user_defined,
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input [0:3] ac_an_req_spare_ctrl_a0,
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input ac_an_st_data_pwr_token,
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input [0:31] ac_an_st_byte_enbl,
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input [0:255] ac_an_st_data
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*/
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// FF
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always @(posedge clk) begin
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if (rst) begin
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cmdseq_q = 'b11111;
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req_q = 0;
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std_q = 0;
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req_tkn_q = 0;
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std_tkn_q = 0;
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end else begin
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cmdseq_q = cmdseq_d;
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req_q = req_d;
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std_q = std_d;
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req_tkn_q = ac_an_req_pwr_token;
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std_tkn_q = ac_an_st_data_pwr_token;
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end
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end
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// Mem
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/*
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always @(posedge clk) begin
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if (do_store) begin
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mem[req_adr] = st_rmw_data;
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end
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end
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assign mem_dat = mem[mem_adr];
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*/
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assign mem_adr = req_adr >> 4;
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// clkgate
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assign req_d = req_tkn_q ? {ac_an_req,
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ac_an_req_thread, // 0:2
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ac_an_req_ttype, // 0:5
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ac_an_req_ld_core_tag, // 0:2
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ac_an_req_ra, //
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ac_an_req_ld_xfr_len, // 0:2
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ac_an_req_wimg_w,
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ac_an_req_wimg_i,
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ac_an_req_wimg_m,
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ac_an_req_wimg_g,
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ac_an_req_wimg_endian,
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ac_an_req_user_defined, // 0:3
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ac_an_req_spare_ctrl_a0 // 0:3
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} : 0;
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assign std_d = std_tkn_q ? {ac_an_st_byte_enbl, // 0:31
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ac_an_st_data // 0:255
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} : 0;
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// request
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assign req_ld_val = req_q[0] & (
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(req_q[4:9] == 'b000000) | // if
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(req_q[4:9] == 'b001000) | // ld
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(req_q[4:9] == 'b100010) | // ditc
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(req_q[4:9] == 'b001001) | // larx
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(req_q[4:9] == 'b001011); // larx hint
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);
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assign req_st_val = req_q[0] & (
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(req_q[4:9] == 'b100000) | // st
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(req_q[4:9] == 'b101001) // stcx
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);
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assign req_tag = req_q[10:12];
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assign req_adr = req_q[14+64-`REAL_IFAR_WIDTH:14+63];
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// coming --- ---
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// valid --- --- --- --- (and qw, crit)
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// data --- --- --- ---
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//tbl cmdseq
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//n cmdseq_q cmdseq_d
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//n | | rld_coming
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//n | ld_req_val | |rld_valid
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//n | |st_req_val | ||do_store
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//n | ||ld_ready | |||rld_done
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//n | |||st_ready | ||||
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//n | ||||ld_ieq1 | |||| idle
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//n | ||||| | |||| |
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//n | ||||| | |||| |
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//b 01234 ||||| 01234 |||| |
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//t iiiii iiiii ooooo oooo o
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//*----------------------------------------------------------------------
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//* Idle ****************************************************************
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//s 11111 ----- ----- 0000 1
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//s 11111 00--- 11111 0000 - * ...zzz...
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//s 11111 1---- 00001 0000 -
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//s 11111 -1--- 10000 0000 -
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//* Load ****************************************************************
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//* 00001 --0-- 00001 0000 0
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//* 00001 --1-- 00010 1000 0
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//* Reload V0 *********************************************************** * val 0
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//* 00010 ----1 00011 0100 0
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//* 00011 ----0 00100 0100 0
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//* Reload D0 (I=1) ****************************************************** * dat 0
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//* 00011 ----- 11111 0001 0
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//* Reload D0 ************************************************************ * val 1, dat 0
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//* 00100 ----- 00101 1100 0
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//* Reload D1 ************************************************************ * val 2, dat 1
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//* 00101 ----- 00110 0100 0
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//* Reload D2 ************************************************************ * val 3, dat 2
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//* 00110 ----- 00111 0100 0
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//* Reload D3 ************************************************************ * dat 3
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//* 00111 ----- 11111 0001 0
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//* Store ***************************************************************
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//* 10000 ---0- 10000 0000 0
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//* 10000 ---1- 11111 0010 0
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//*----------------------------------------------------------------------
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//tbl cmdseq
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assign reld_qw = cmdseq_q[3:4];
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// response
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assign an_ac_reld_ecc_err = 0;
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assign an_ac_reld_ecc_err_ue = 0;
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assign an_ac_reld_ditc = 0;
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// loads
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assign an_ac_reld_data_coming = rld_coming;
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assign an_ac_reld_data_vld = rld_valid;
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assign an_ac_reld_core_tag = req_tag;
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assign an_ac_reld_qw = reld_qw;
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assign an_ac_reld_crit_qw = req_ieq1 | (req_adr[58:59] == reld_qw);
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assign an_ac_reld_data = mem[{req_adr[64-`REAL_IFAR_WIDTH:59], reld_qw}];
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assign an_ac_req_ld_pop = rld_done;
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// stores
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assign st_ready = 1; // random delay, or future functional stuff
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assign an_ac_req_st_pop = st_ready;
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assign st_mask = {
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{8{std_q[0]}}, {8{std_q[1]}}, {8{std_q[2]}}, {8{std_q[3]}},
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{8{std_q[4]}}, {8{std_q[5]}}, {8{std_q[6]}}, {8{std_q[7]}},
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{8{std_q[8]}}, {8{std_q[9]}}, {8{std_q[10]}}, {8{std_q[11]}},
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{8{std_q[12]}}, {8{std_q[13]}}, {8{std_q[14]}}, {8{std_q[15]}},
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{8{std_q[16]}}, {8{std_q[17]}}, {8{std_q[18]}}, {8{std_q[19]}},
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{8{std_q[20]}}, {8{std_q[21]}}, {8{std_q[22]}}, {8{std_q[23]}},
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{8{std_q[24]}}, {8{std_q[25]}}, {8{std_q[26]}}, {8{std_q[27]}},
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{8{std_q[28]}}, {8{std_q[29]}}, {8{std_q[30]}}, {8{std_q[31]}}
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};
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// BE, 16B max store
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assign st_alg_data = req_q[32:32+127]; // no shift needed?
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assign mem_wr_val = do_store;
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assign mem_wr_dat = (mem_dat & st_mask) | (st_alg_data & ~st_mask);
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//vtable cmdseq
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//vtable cmdseq
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