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67 lines
1.4 KiB
Verilog
67 lines
1.4 KiB
Verilog
`timescale 1 ps / 1 ps
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module bram_model (DIA, DIB, ENA, ENB, WEA, WEB, SSRA, SSRB, CLKA, CLKB, ADDRA, ADDRB, DOA, DOB);
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parameter data_w = 2;
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parameter addr_w = 13;
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input [data_w-1:0] DIA;
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input [data_w-1:0] DIB;
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input ENA;
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input ENB;
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input WEA;
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input WEB;
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input SSRA;
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input SSRB;
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input CLKA;
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input CLKB;
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input [addr_w-1:0] ADDRA;
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input [addr_w-1:0] ADDRB;
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output [data_w-1:0] DOA;
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output [data_w-1:0] DOB;
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reg [data_w-1:0] MEM[2**addr_w-1:0];
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reg [data_w-1:0] DOA_q;
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reg [data_w-1:0] DOB_q;
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initial begin: init
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integer i;
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for (i = 0; i < 2**addr_w; i = i + 1)
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MEM[i] = 0;
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end
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always @(posedge CLKA) begin: BRAM_MODEL
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if (ENA) begin
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if (WEA) begin
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MEM[ADDRA] <= DIA;
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end
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end
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end
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always @(posedge CLKB) begin: BRAM_MODEL_B
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if (ENB) begin
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if (WEB) begin
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MEM[ADDRB] <= DIB;
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end
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end
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end
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always @(posedge CLKA) begin
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if (SSRA)
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DOA_q <= {data_w{1'b0}};
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else
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DOA_q <= MEM[ADDRA];
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end
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always @(posedge CLKB) begin
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if (SSRB)
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DOB_q <= {data_w{1'b0}};
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else
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DOB_q <= MEM[ADDRB];
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end
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assign DOA = DOA_q;
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assign DOB = DOB_q;
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endmodule
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