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589 lines
20 KiB
Verilog
589 lines
20 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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//
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// Description: Generic Local FIR Component
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//
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//*****************************************************************************
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`timescale 1 ns / 1 ns
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`include "tri_a2o.vh"
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module pcq_local_fir2(
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// Include model build parameters
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`include "tri_a2o.vh"
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clk,
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rst,
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vdd,
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gnd,
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lcb_clkoff_dc_b,
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lcb_mpw1_dc_b,
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lcb_mpw2_dc_b,
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lcb_delay_lclkr_dc,
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lcb_act_dis_dc,
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lcb_sg_0,
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lcb_func_slp_sl_thold_0,
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lcb_cfg_slp_sl_thold_0,
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mode_scan_siv,
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mode_scan_sov,
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func_scan_siv,
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func_scan_sov,
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sys_xstop_in,
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error_in,
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xstop_err,
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recov_err,
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lxstop_mchk,
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trace_error,
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recov_reset,
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fir_out,
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act0_out,
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act1_out,
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mask_out,
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sc_parity_error_inject,
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sc_active,
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sc_wr_q,
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sc_addr_v,
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sc_wdata,
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sc_rdata,
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fir_parity_check
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);
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parameter WIDTH = 1; // this must be >=1 and <=64
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parameter IMPL_LXSTOP_MCHK = 1'b1; // generate local checkstop /machine check output
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parameter USE_RECOV_RESET = 1'b0; // this adds a reset feature without the second wof register.
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parameter [0:WIDTH-1] FIR_INIT = 1'b0; // init value for fir register; length = width !
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parameter [0:WIDTH-1] FIR_MASK_INIT = 1'b0; // init value for fir mask register; length = width !
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parameter FIR_MASK_PAR_INIT = 1'b0; // init value for fir mask register even parity
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parameter [0:WIDTH-1] FIR_ACTION0_INIT = 1'b0; // init value for fir action0 register; length = width !
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parameter FIR_ACTION0_PAR_INIT = 1'b0; // init value for fir action0 register even parity
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parameter [0:WIDTH-1] FIR_ACTION1_INIT = 1'b0; // init value for fir action1 register; length = width !
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parameter FIR_ACTION1_PAR_INIT = 1'b0; // init value for fir action1 register even parity
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//=====================================================================
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// Port Definitions
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//=====================================================================
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// Global lines for clocking and scan control
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inout vdd;
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inout gnd;
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input clk;
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input rst;
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input lcb_clkoff_dc_b; //from lcb_cntl external to component
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input lcb_mpw1_dc_b; //from lcb_cntl external to component
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input lcb_mpw2_dc_b; //from lcb_cntl external to component
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input lcb_delay_lclkr_dc; //from lcb_cntl external to component
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input lcb_act_dis_dc; //from lcb_cntl external to component
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input lcb_sg_0;
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input lcb_func_slp_sl_thold_0;
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input lcb_cfg_slp_sl_thold_0;
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input [0:3*(WIDTH+1)+WIDTH-1] mode_scan_siv; // scan vector in
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output [0:3*(WIDTH+1)+WIDTH-1] mode_scan_sov; // scan vector out
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input [0:4] func_scan_siv; // scan vector in
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output [0:4] func_scan_sov; // scan vector out
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// External interface
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input sys_xstop_in; // freeze FIR on system checkstop from chip GEM
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input [0:WIDTH-1] error_in; // needs to be directly off a latch for timing
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output xstop_err; // checkstop output to Global FIR
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output recov_err; // recoverable output to Global FIR
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output lxstop_mchk; // use ONLY if IMPL_LXSTOP_MCHK = true
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output trace_error; // connect to error_input of closest trdata macro
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input recov_reset; // only needed if USE_RECOV_RESET = true
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output [0:WIDTH-1] fir_out; // output of current FIR state if needed
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output [0:WIDTH-1] act0_out; // output of current FIR Act0 state if needed
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output [0:WIDTH-1] act1_out; // output of current FIR Act1 state if needed
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output [0:WIDTH-1] mask_out; // output of current FIR Mask state if needed
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// SCOM register connections
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input sc_parity_error_inject; // Force parity error
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input sc_active;
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input sc_wr_q;
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input [0:8] sc_addr_v;
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input [0:WIDTH-1] sc_wdata;
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output [0:WIDTH-1] sc_rdata;
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output [0:2] fir_parity_check; // Action0, Action1, Mask reg parity checks
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//=====================================================================
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// Signal Declarations
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//=====================================================================
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// Clocks
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wire func_d1clk;
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wire func_d2clk;
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//wire [0:`NCLK_WIDTH-1] func_lclk;
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wire func_lclk;
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wire mode_d1clk;
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wire mode_d2clk;
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//wire [0:`NCLK_WIDTH-1] mode_lclk;
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wire scom_mode_d1clk;
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wire scom_mode_d2clk;
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//wire [0:`NCLK_WIDTH-1] scom_mode_lclk;
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wire func_thold_b;
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wire func_force;
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wire mode_thold_b;
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wire mode_force;
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// FIR regs
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wire [0:WIDTH-1] data_ones;
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wire [0:WIDTH-1] or_fir;
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wire [0:WIDTH-1] and_fir;
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wire [0:WIDTH-1] or_mask;
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wire [0:WIDTH-1] and_mask;
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wire [0:WIDTH-1] fir_mask_in;
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wire [0:WIDTH-1] fir_mask_lt;
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wire [0:WIDTH-1] masked;
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wire fir_mask_par_in;
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wire fir_mask_par_lt;
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wire fir_mask_par_err;
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wire [0:WIDTH-1] fir_action0_in;
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wire [0:WIDTH-1] fir_action0_lt;
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wire fir_action0_par_in;
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wire fir_action0_par_lt;
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wire fir_action0_par_err;
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wire [0:WIDTH-1] fir_action1_in;
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wire [0:WIDTH-1] fir_action1_lt;
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wire fir_action1_par_in;
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wire fir_action1_par_lt;
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wire fir_action1_par_err;
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wire [0:WIDTH-1] fir_reset;
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wire [0:WIDTH-1] error_input;
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wire [0:WIDTH-1] fir_error_in_reef;
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wire [0:WIDTH-1] fir_in;
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wire [0:WIDTH-1] fir_lt;
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wire fir_act;
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wire block_fir;
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wire or_fir_load;
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wire and_fir_ones;
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wire and_fir_load;
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wire or_mask_load;
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wire and_mask_ones;
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wire and_mask_load;
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// Error report
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wire sys_xstop_lt;
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wire recov_in;
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wire recov_lt;
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wire xstop_in;
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wire xstop_lt;
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wire trace_error_in;
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wire trace_error_lt;
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// Other
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wire tieup;
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// Scan chain hookups
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wire [0:3*(WIDTH+1)+WIDTH-1] mode_si;
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wire [0:3*(WIDTH+1)+WIDTH-1] mode_so;
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wire [0:4] func_si;
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wire [0:4] func_so;
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(* analysis_not_referenced="true" *)
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wire unused_signals;
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assign unused_signals = recov_reset | sc_addr_v[5];
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assign tieup = 1'b1;
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assign data_ones = {WIDTH {1'b1}};
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//******************************************************
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//* LCB driver, LCB and Register Instantiations
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//******************************************************
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// functional ring regs; NOT power managed
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tri_lcbor func_lcbor(
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.clkoff_b(lcb_clkoff_dc_b),
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.thold(lcb_func_slp_sl_thold_0),
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.sg(lcb_sg_0),
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.act_dis(lcb_act_dis_dc),
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.force_t(func_force),
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.thold_b(func_thold_b)
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);
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tri_lcbnd func_lcb(
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.act(tieup), // not power managed
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.vd(vdd),
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.gd(gnd),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.clk(clk),
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.rst(rst),
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.force_t(func_force),
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.sg(lcb_sg_0),
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.thold_b(func_thold_b),
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.d1clk(func_d1clk),
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.d2clk(func_d2clk),
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.lclk(func_lclk)
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);
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// config ring regs; NOT power managed
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tri_lcbor mode_lcbor(
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.clkoff_b(lcb_clkoff_dc_b),
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.thold(lcb_cfg_slp_sl_thold_0),
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.sg(lcb_sg_0),
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.act_dis(lcb_act_dis_dc),
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.force_t(mode_force),
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.thold_b(mode_thold_b)
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);
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assign fir_act = sc_active | (|error_in);
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/*
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tri_lcbnd mode_lcb(
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.act(fir_act), // active during scom access or FIR error input
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.vd(vdd),
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.gd(gnd),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.clk(clk),
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.rst(rst),
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.force_t(mode_force),
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.sg(lcb_sg_0),
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.thold_b(mode_thold_b),
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.d1clk(mode_d1clk),
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.d2clk(mode_d2clk),
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.lclk(mode_lclk)
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);
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tri_lcbnd scom_mode_lcb(
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.act(sc_active), // active during scom access
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.vd(vdd),
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.gd(gnd),
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.delay_lclkr(lcb_delay_lclkr_dc),
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.mpw1_b(lcb_mpw1_dc_b),
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.mpw2_b(lcb_mpw2_dc_b),
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.clk(clk),
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.rst(rst),
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.force_t(mode_force),
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.sg(lcb_sg_0),
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.thold_b(mode_thold_b),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.lclk(scom_mode_lclk)
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);
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*/
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//--------------------------------------------------------------------
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// Mode Registers
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//--------------------------------------------------------------------
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tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION0_INIT)) fir_action0(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[0:WIDTH - 1]),
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.scan_out(mode_so[0:WIDTH - 1]),
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.din(fir_action0_in),
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.q(fir_action0_lt)
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);
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tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION0_PAR_INIT)) fir_action0_par(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[WIDTH:WIDTH]),
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.scan_out(mode_so[WIDTH:WIDTH]),
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.din(fir_action0_par_in),
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.q(fir_action0_par_lt)
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);
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tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_ACTION1_INIT)) fir_action1(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[(WIDTH + 1):(2*WIDTH)]),
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.scan_out(mode_so[(WIDTH + 1):(2*WIDTH)]),
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.din(fir_action1_in),
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.q(fir_action1_lt)
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);
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tri_nlat_scan #(.WIDTH(1), .INIT(FIR_ACTION1_PAR_INIT)) fir_action1_par(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[(2*WIDTH + 1):(2*WIDTH + 1)]),
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.scan_out(mode_so[(2*WIDTH + 1):(2*WIDTH + 1)]),
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.din(fir_action1_par_in),
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.q(fir_action1_par_lt)
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);
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tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_MASK_INIT)) fir_mask(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[(2*WIDTH + 2):(3*WIDTH + 1)]),
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.scan_out(mode_so[(2*WIDTH + 2):(3*WIDTH + 1)]),
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.din(fir_mask_in),
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.q(fir_mask_lt)
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);
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tri_nlat_scan #(.WIDTH(1), .INIT(FIR_MASK_PAR_INIT)) fir_mask_par(
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.vd(vdd),
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.gd(gnd),
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.d1clk(scom_mode_d1clk),
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.d2clk(scom_mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[(3*WIDTH + 2):(3*WIDTH + 2)]),
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.scan_out(mode_so[(3*WIDTH + 2):(3*WIDTH + 2)]),
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.din(fir_mask_par_in),
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.q(fir_mask_par_lt)
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);
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tri_nlat_scan #(.WIDTH(WIDTH), .INIT(FIR_INIT)) fir(
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.vd(vdd),
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.gd(gnd),
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.d1clk(mode_d1clk),
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.d2clk(mode_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in( mode_si[(3*WIDTH + 3):(4*WIDTH + 2)]),
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.scan_out(mode_so[(3*WIDTH + 3):(4*WIDTH + 2)]),
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.din(fir_in),
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.q(fir_lt)
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);
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//--------------------------------------------------------------------
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// Func Registers with no power savings
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//--------------------------------------------------------------------
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tri_nlat #(.WIDTH(1), .INIT(1'b0)) sys_xstop(
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.vd(vdd),
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.gd(gnd),
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.d1clk(func_d1clk),
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.d2clk(func_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in(func_si[1]),
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.scan_out(func_so[1]),
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.din(sys_xstop_in),
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.q(sys_xstop_lt)
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);
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tri_nlat #(.WIDTH(1), .INIT(1'b0)) recov(
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.vd(vdd),
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.gd(gnd),
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.d1clk(func_d1clk),
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.d2clk(func_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in(func_si[2]),
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.scan_out(func_so[2]),
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.din(recov_in),
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.q(recov_lt)
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);
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tri_nlat #(.WIDTH(1), .INIT(1'b0)) xstop(
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.vd(vdd),
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.gd(gnd),
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.d1clk(func_d1clk),
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.d2clk(func_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in(func_si[3]),
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.scan_out(func_so[3]),
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.din(xstop_in),
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.q(xstop_lt)
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);
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tri_nlat #(.WIDTH(1), .INIT(1'b0)) trace_err(
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.vd(vdd),
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.gd(gnd),
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.d1clk(func_d1clk),
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.d2clk(func_d2clk),
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.clk(clk),
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.rst(rst),
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.scan_in(func_si[4]),
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.scan_out(func_so[4]),
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.din(trace_error_in),
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.q(trace_error_lt)
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);
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//******************************************************
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//* Optional Recovery Reset
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//******************************************************
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generate
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if (USE_RECOV_RESET == 1'b1)
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begin : use_recov_reset_yes
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assign fir_reset = (~({WIDTH {recov_reset}} & (~fir_action0_lt) & fir_action1_lt));
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end
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endgenerate
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generate
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if (USE_RECOV_RESET == 1'b0)
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begin : use_recov_reset_no
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assign fir_reset = {WIDTH {1'b1}};
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end
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endgenerate
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//******************************************************
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//* FIR
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//******************************************************
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// write to x'0' to write FIR directly
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// write to x'1' to And-Mask FIR
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// write to x'2' to Or-Mask FIR
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assign or_fir_load = (sc_addr_v[0] | sc_addr_v[2]) & sc_wr_q;
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assign and_fir_ones = (~((sc_addr_v[0] | sc_addr_v[1]) & sc_wr_q));
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assign and_fir_load = sc_addr_v[1] & sc_wr_q;
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assign or_fir = ({WIDTH {or_fir_load}} & sc_wdata);
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assign and_fir = ({WIDTH {and_fir_load}} & sc_wdata) | ({WIDTH {and_fir_ones}} & data_ones);
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assign fir_in = ({WIDTH {~block_fir}} & error_input) | or_fir | (fir_lt & and_fir & fir_reset);
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assign fir_error_in_reef = error_in; // does a signal rename for the reef tool
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assign error_input = fir_error_in_reef;
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//******************************************************
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//* FIR Mask
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//******************************************************
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// write to x'6' to write FIR-MASK directly
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// write to x'7' to And-Mask FIR-MASK
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// write to x'8' to Or-Mask FIR-MASK
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assign or_mask_load = (sc_addr_v[6] | sc_addr_v[8]) & sc_wr_q;
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assign and_mask_ones = (~((sc_addr_v[6] | sc_addr_v[7]) & sc_wr_q));
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assign and_mask_load = sc_addr_v[7] & sc_wr_q;
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assign or_mask = ({WIDTH {or_mask_load}} & sc_wdata);
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assign and_mask = ({WIDTH {and_mask_load}} & sc_wdata) | ({WIDTH {and_mask_ones}} & data_ones);
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assign fir_mask_in = or_mask | (fir_mask_lt & and_mask);
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assign fir_mask_par_in = ((sc_wr_q & (|sc_addr_v[6:8])) == 1'b1) ? (^fir_mask_in) : fir_mask_par_lt;
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assign fir_mask_par_err = ((^fir_mask_lt) ^ fir_mask_par_lt) | (sc_wr_q & (|sc_addr_v[6:8]) & sc_parity_error_inject);
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assign masked = fir_mask_lt;
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//******************************************************
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//* Action Registers
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//******************************************************
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// write to x'3' to write FIR-Action0 directly
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assign fir_action0_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? sc_wdata : fir_action0_lt;
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assign fir_action0_par_in = ((sc_wr_q & sc_addr_v[3]) == 1'b1) ? (^fir_action0_in) : fir_action0_par_lt;
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assign fir_action0_par_err = ((^fir_action0_lt) ^ fir_action0_par_lt) | (sc_wr_q & sc_addr_v[3] & sc_parity_error_inject);
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// write to x'4' to write FIR-Action1 directly
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assign fir_action1_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? sc_wdata : fir_action1_lt;
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assign fir_action1_par_in = ((sc_wr_q & sc_addr_v[4]) == 1'b1) ? (^fir_action1_in) : fir_action1_par_lt;
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assign fir_action1_par_err = ((^fir_action1_lt) ^ fir_action1_par_lt) | (sc_wr_q & sc_addr_v[4] & sc_parity_error_inject);
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//******************************************************
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//* Summary
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//******************************************************
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assign xstop_in = (|(fir_lt & fir_action0_lt & (~fir_action1_lt) & (~masked))); // fir_action = 10
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assign recov_in = (|(fir_lt & (~fir_action0_lt) & fir_action1_lt & (~masked))); // fir_action = 01
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assign block_fir = xstop_lt | sys_xstop_lt;
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assign xstop_err = xstop_lt;
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assign recov_err = recov_lt;
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assign trace_error = trace_error_lt;
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assign fir_out = fir_lt;
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assign act0_out = fir_action0_lt;
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assign act1_out = fir_action1_lt;
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assign mask_out = fir_mask_lt;
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assign fir_parity_check = {fir_action0_par_err, fir_action1_par_err, fir_mask_par_err};
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//******************************************************
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//* SCOM read logic
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//******************************************************
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assign sc_rdata = ({WIDTH {sc_addr_v[0]}} & fir_lt) |
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({WIDTH {sc_addr_v[3]}} & fir_action0_lt) |
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({WIDTH {sc_addr_v[4]}} & fir_action1_lt) |
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({WIDTH {sc_addr_v[6]}} & fir_mask_lt) ;
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|
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//******************************************************
|
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//* Optional MCHK Enable Register and Output
|
|
//******************************************************
|
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generate
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if (IMPL_LXSTOP_MCHK == 1'b1)
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|
begin : mchkgen
|
|
wire lxstop_mchk_in;
|
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wire lxstop_mchk_lt;
|
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assign lxstop_mchk_in = (|(fir_lt & fir_action0_lt & fir_action1_lt & (~masked))); // fir_action = 11
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assign lxstop_mchk = lxstop_mchk_lt;
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|
|
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assign trace_error_in = xstop_in | recov_in | lxstop_mchk_in;
|
|
|
|
tri_nlat #(.WIDTH(1), .INIT(1'b0)) mchk(
|
|
.d1clk(func_d1clk),
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.clk(clk),
|
|
.rst(rst),
|
|
.d2clk(func_d2clk),
|
|
.scan_in(func_si[0]),
|
|
.scan_out(func_so[0]),
|
|
.din(lxstop_mchk_in),
|
|
.q(lxstop_mchk_lt)
|
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);
|
|
end
|
|
endgenerate
|
|
|
|
generate
|
|
if (IMPL_LXSTOP_MCHK == 1'b0)
|
|
begin : nomchk
|
|
assign trace_error_in = xstop_in | recov_in;
|
|
assign lxstop_mchk = 1'b0;
|
|
assign func_so[0] = func_si[0];
|
|
end
|
|
endgenerate
|
|
|
|
//******************************************************
|
|
// Scan Chain Connections
|
|
//******************************************************
|
|
assign mode_si = mode_scan_siv;
|
|
assign mode_scan_sov = mode_so;
|
|
|
|
assign func_si = func_scan_siv;
|
|
assign func_scan_sov = func_so;
|
|
|
|
|
|
endmodule
|