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66 lines
1.7 KiB
Verilog
66 lines
1.7 KiB
Verilog
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`include "tri_a2o.vh"
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`timescale 1ns/1ps
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module cocotb (
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input clk_1x,
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input clk_2x,
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input rst,
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input [0:31] cfg_dat,
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input cfg_wr,
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output [0:31] status,
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input timerInterrupt,
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input externalInterrupt,
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input softwareInterrupt,
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input externalInterruptS,
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output wb_stb,
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output wb_cyc,
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output [31:0] wb_adr,
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output wb_we,
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output [3:0] wb_sel,
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output [31:0] wb_datw,
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input wb_ack,
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input [31:0] wb_datr
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);
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a2owb c0 (
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.clk_1x(clk_1x),
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.clk_2x(clk_2x),
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.rst(rst),
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.cfg_wr(cfg_wr),
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.cfg_dat(cfg_dat),
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.status(status),
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.timerInterrupt(timerInterrupt),
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.externalInterrupt(externalInterrupt),
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.softwareInterrupt(softwareInterrupt),
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.externalInterruptS(externalInterruptS),
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.wb_stb(wb_stb),
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.wb_cyc(wb_cyc),
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.wb_adr(wb_adr),
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.wb_we(wb_we),
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.wb_ack(wb_ack),
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.wb_sel(wb_sel),
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.wb_datr(wb_datr),
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.wb_datw(wb_datw)
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);
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initial begin
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$dumpfile ("a2olitex.vcd");
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// you can do it by levels and also by module so could prune down
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$dumpvars;
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// need to explicitly specify arrays for icarus
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// guess not: $dumpvars cannot dump a vpiMemory
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//$dumpvars(0, c0.iuq0.iuq_slice_top0.slice0.iuq_ibuf0.buffer_data_q);
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#1;
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end
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endmodule |