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33 lines
846 B
Markdown
33 lines
846 B
Markdown
# Cocotb Sim Experiments
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## Core-only version with partial implementation of Python A2L2 interface
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* testbench provides memory using A2 core-L2 interface
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```
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make -f Makefile.st build |& grep -v Anac
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```
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## Core+wrapper version with partial implementation of A2Node (direct memory)
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* testbench provides memory using simple RAM interface
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```
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make -f Makefile.node build |& grep -v Anac
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```
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## Core+wrapper version with implementation of A2Node (Wishbone system bus)
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* testbench provides 4B Wishbone memory interface (using cocoext-wishbone for now)
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```
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make -f Makefile.wb build |& grep -v Anac
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``
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* update wrapper to include normal Litex, etc. I/O (WB plus ints, config, etc.)
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* add Litex core definition (migen)
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* can add L2 mem
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* can add multiple core intefaces (SMP)
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* can add multicore+heterogeneous cores (mixed A2L2, WB-1, WB-2)
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