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Copyright 1986-2020 Xilinx, Inc. All Rights Reserved.
--------------------------------------------------------------------------------------------------------------
| Tool Version : Vivado v.2020.1 (lin64) Build 2902540 Wed May 27 19:54:35 MDT 2020
| Date : Wed Aug 3 19:38:35 2022
| Host : gridl294.pok.ibm.com running 64-bit Red Hat Enterprise Linux Workstation release 7.9 (Maipo)
| Command : report_timing_summary -file cmod7_timing_synth.rpt
| Design : cmod7
| Device : 7k410t-ffv676
| Speed File : -1 PRODUCTION 1.12 2017-02-17
--------------------------------------------------------------------------------------------------------------
Timing Summary Report
------------------------------------------------------------------------------------------------
| Timer Settings
| --------------
------------------------------------------------------------------------------------------------
Enable Multi Corner Analysis : Yes
Enable Pessimism Removal : Yes
Pessimism Removal Resolution : Nearest Common Node
Enable Input Delay Default Clock : No
Enable Preset / Clear Arcs : No
Disable Flight Delays : No
Ignore I/O Paths : No
Timing Early Launch at Borrowing Latches : No
Borrow Time for Max Delay Exceptions : Yes
Merge Timing Exceptions : Yes
Corner Analyze Analyze
Name Max Paths Min Paths
------ --------- ---------
Slow Yes Yes
Fast Yes Yes
check_timing report
Table of Contents
-----------------
1. checking no_clock (0)
2. checking constant_clock (0)
3. checking pulse_width_clock (0)
4. checking unconstrained_internal_endpoints (1624)
5. checking no_input_delay (3)
6. checking no_output_delay (3)
7. checking multiple_clock (0)
8. checking generated_clocks (0)
9. checking loops (0)
10. checking partial_input_delay (0)
11. checking partial_output_delay (0)
12. checking latch_loops (0)
1. checking no_clock (0)
------------------------
There are 0 register/latch pins with no clock.
2. checking constant_clock (0)
------------------------------
There are 0 register/latch pins with constant_clock.
3. checking pulse_width_clock (0)
---------------------------------
There are 0 register/latch pins which need pulse_width check
4. checking unconstrained_internal_endpoints (1624)
---------------------------------------------------
There are 0 pins that are not constrained for maximum delay.
There are 1624 pins that are not constrained for maximum delay due to constant clock. (MEDIUM)
5. checking no_input_delay (3)
------------------------------
There are 3 input ports with no input delay specified. (HIGH)
There are 0 input ports with no input delay but user has a false path constraint.
6. checking no_output_delay (3)
-------------------------------
There are 3 ports with no output delay specified. (HIGH)
There are 0 ports with no output delay but user has a false path constraint
There are 0 ports with no output delay but with a timing clock defined on it or propagating through it
7. checking multiple_clock (0)
------------------------------
There are 0 register/latch pins with multiple clocks.
8. checking generated_clocks (0)
--------------------------------
There are 0 generated clocks that are not connected to a clock source.
9. checking loops (0)
---------------------
There are 0 combinational loops in the design.
10. checking partial_input_delay (0)
------------------------------------
There are 0 input ports with partial input delay specified.
11. checking partial_output_delay (0)
-------------------------------------
There are 0 ports with partial output delay specified.
12. checking latch_loops (0)
----------------------------
There are 0 combinational latch loops in the design through latch input
------------------------------------------------------------------------------------------------
| Design Timing Summary
| ---------------------
------------------------------------------------------------------------------------------------
WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
1.099 0.000 0 139626 -0.053 -70.544 1378 139626 0.264 0.000 0 97489
Timing constraints are not met.
------------------------------------------------------------------------------------------------
| Clock Summary
| -------------
------------------------------------------------------------------------------------------------
Clock Waveform(ns) Period(ns) Frequency(MHz)
----- ------------ ---------- --------------
clk12 {0.000 41.666} 83.333 12.000
basesoc_mmcm_fb {0.000 41.666} 83.333 12.000
crg_clkout0 {0.000 10.000} 20.000 50.000
crg_clkout1 {0.000 5.000} 10.000 100.000
crg_clkout2 {0.000 2.500} 5.000 200.001
------------------------------------------------------------------------------------------------
| Intra Clock Table
| -----------------
------------------------------------------------------------------------------------------------
Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints WPWS(ns) TPWS(ns) TPWS Failing Endpoints TPWS Total Endpoints
----- ------- ------- --------------------- ------------------- ------- ------- --------------------- ------------------- -------- -------- ---------------------- --------------------
clk12 82.503 0.000 0 7 0.070 0.000 0 7 16.667 0.000 0 10
basesoc_mmcm_fb 16.667 0.000 0 2
crg_clkout0 1.099 0.000 0 139302 -0.053 -70.544 1378 139302 9.090 0.000 0 97260
crg_clkout1 5.647 0.000 0 303 0.102 0.000 0 303 4.650 0.000 0 207
crg_clkout2 1.153 0.000 0 14 0.001 0.000 0 14 0.264 0.000 0 10
------------------------------------------------------------------------------------------------
| Inter Clock Table
| -----------------
------------------------------------------------------------------------------------------------
From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Other Path Groups Table
| -----------------------
------------------------------------------------------------------------------------------------
Path Group From Clock To Clock WNS(ns) TNS(ns) TNS Failing Endpoints TNS Total Endpoints WHS(ns) THS(ns) THS Failing Endpoints THS Total Endpoints
---------- ---------- -------- ------- ------- --------------------- ------------------- ------- ------- --------------------- -------------------
------------------------------------------------------------------------------------------------
| Timing Details
| --------------
------------------------------------------------------------------------------------------------
---------------------------------------------------------------------------------------------------
From Clock: clk12
To Clock: clk12
Setup : 0 Failing Endpoints, Worst Slack 82.503ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.070ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 82.503ns (required time - arrival time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Path Group: clk12
Path Type: Setup (Max at Slow Process Corner)
Requirement: 83.333ns (clk12 rise@83.333ns - clk12 rise@0.000ns)
Data Path Delay: 0.550ns (logic 0.308ns (56.000%) route 0.242ns (44.000%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 3.126ns = ( 86.459 - 83.333 )
Source Clock Delay (SCD): 3.605ns
Clock Pessimism Removal (CPR): 0.334ns
Clock Uncertainty: 0.035ns ((TSJ^2 + TIJ^2)^1/2 + DJ) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Total Input Jitter (TIJ): 0.000ns
Discrete Jitter (DJ): 0.000ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.308 3.913 r FDCE/Q
net (fo=1, unplaced) 0.242 4.155 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 83.333 83.333 r
L17 0.000 83.333 r clk12 (IN)
net (fo=0) 0.000 83.333 clk12
L17 IBUF (Prop_ibuf_I_O) 1.539 84.872 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 85.426 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 85.539 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 85.978 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 86.020 r clk12_inst/O
net (fo=9, unplaced) 0.439 86.459 crg_clkin
FDCE r FDCE_1/C
clock pessimism 0.334 86.793
clock uncertainty -0.035 86.758
FDCE (Setup_fdce_C_D) -0.100 86.658 FDCE_1
-------------------------------------------------------------------
required time 86.658
arrival time -4.155
-------------------------------------------------------------------
slack 82.503
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.070ns (arrival time - required time)
Source: FDCE/C
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Destination: FDCE_1/D
(rising edge-triggered cell FDCE clocked by clk12 {rise@0.000ns fall@41.667ns period=83.333ns})
Path Group: clk12
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (clk12 rise@0.000ns - clk12 rise@0.000ns)
Data Path Delay: 0.220ns (logic 0.118ns (53.634%) route 0.102ns (46.366%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 1.449ns
Source Clock Delay (SCD): 0.940ns
Clock Pessimism Removal (CPR): 0.365ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
FDCE r FDCE/C
------------------------------------------------------------------- -------------------
FDCE (Prop_fdce_C_Q) 0.118 1.058 r FDCE/Q
net (fo=1, unplaced) 0.102 1.160 basesoc_reset0
FDCE r FDCE_1/D
------------------------------------------------------------------- -------------------
(clock clk12 rise edge) 0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
FDCE r FDCE_1/C
clock pessimism -0.365 1.085
FDCE (Hold_fdce_C_D) 0.005 1.090 FDCE_1
-------------------------------------------------------------------
required time -1.090
arrival time 1.160
-------------------------------------------------------------------
slack 0.070
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: clk12
Waveform(ns): { 0.000 41.667 }
Period(ns): 83.333
Sources: { clk12 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a BUFG/I n/a 1.600 83.333 81.733 clk12_IBUF_BUFG_inst/I
Max Period n/a MMCME2_ADV/CLKIN1 n/a 100.000 83.333 16.667 MMCME2_ADV/CLKIN1
Low Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.667 31.667 MMCME2_ADV/CLKIN1
High Pulse Width Slow MMCME2_ADV/CLKIN1 n/a 10.000 41.666 31.666 MMCME2_ADV/CLKIN1
---------------------------------------------------------------------------------------------------
From Clock: basesoc_mmcm_fb
To Clock: basesoc_mmcm_fb
Setup : NA Failing Endpoints, Worst Slack NA , Total Violation NA
Hold : NA Failing Endpoints, Worst Slack NA , Total Violation NA
PW : 0 Failing Endpoints, Worst Slack 16.667ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: basesoc_mmcm_fb
Waveform(ns): { 0.000 41.667 }
Period(ns): 83.333
Sources: { MMCME2_ADV/CLKFBOUT }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a MMCME2_ADV/CLKFBOUT n/a 1.249 83.333 82.084 MMCME2_ADV/CLKFBOUT
Max Period n/a MMCME2_ADV/CLKFBIN n/a 100.000 83.333 16.667 MMCME2_ADV/CLKFBIN
---------------------------------------------------------------------------------------------------
From Clock: crg_clkout0
To Clock: crg_clkout0
Setup : 0 Failing Endpoints, Worst Slack 1.099ns, Total Violation 0.000ns
Hold : 1378 Failing Endpoints, Worst Slack -0.053ns, Total Violation -70.544ns
PW : 0 Failing Endpoints, Worst Slack 9.090ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.099ns (required time - arrival time)
Source: FDPE/C
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: FDPE_1/D
(rising edge-triggered cell FDPE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: crg_clkout0
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.425ns (logic 0.281ns (66.118%) route 0.144ns (33.882%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.315ns
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.300ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.597ns
Phase Error (PE): 0.000ns
Timing Exception: MaxDelay Path 2.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.088 3.693 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.584 4.277 crg_clkout0
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG/O
net (fo=97258, unplaced) 0.584 4.981 sys_clk
FDPE r FDPE/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.281 5.262 r FDPE/Q
net (fo=1, unplaced) 0.144 5.406 xilinxasyncresetsynchronizerimpl0_rst_meta
FDPE r FDPE_1/D
------------------------------------------------------------------- -------------------
max delay 2.000 2.000
L17 0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.539 3.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 4.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 4.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 4.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.083 5.209 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.554 5.763 crg_clkout0
BUFG (Prop_bufg_I_O) 0.113 5.876 r BUFG/O
net (fo=97258, unplaced) 0.439 6.315 sys_clk
FDPE r FDPE_1/C
clock pessimism 0.520 6.836
clock uncertainty -0.300 6.535
FDPE (Setup_fdpe_C_D) -0.031 6.504 FDPE_1
-------------------------------------------------------------------
required time 6.504
arrival time -5.406
-------------------------------------------------------------------
slack 1.099
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (VIOLATED) : -0.053ns (arrival time - required time)
Source: a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/C
(rising edge-triggered cell FDRE clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Destination: a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/DIADI[0]
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout0 {rise@0.000ns fall@10.000ns period=20.000ns})
Path Group: crg_clkout0
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout0 rise@0.000ns - crg_clkout0 rise@0.000ns)
Data Path Delay: 0.350ns (logic 0.104ns (29.715%) route 0.246ns (70.285%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.050 0.990 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.246 1.236 crg_clkout0
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG/O
net (fo=97258, unplaced) 0.114 1.376 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/out
FDRE r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.104 1.480 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_miss0/reld_data_latch/int_dout_reg[31]/Q
net (fo=13, unplaced) 0.246 1.726 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/icm_icd_reload_data[31]
RAMB36E1 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/DIADI[0]
------------------------------------------------------------------- -------------------
(clock crg_clkout0 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT0)
0.053 1.502 r MMCME2_ADV/CLKOUT0
net (fo=1, unplaced) 0.259 1.761 crg_clkout0
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG/O
net (fo=97258, unplaced) 0.259 2.050 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/out
RAMB36E1 r a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr/CLKARDCLK
clock pessimism -0.530 1.521
RAMB36E1 (Hold_ramb36e1_CLKARDCLK_DIADI[0])
0.258 1.779 a2owb/c0/iuq0/iuq_ifetch0/iuq_ic0/iuq_ic_dir0/idata/genblk1.aw[0].ax[0].arr
-------------------------------------------------------------------
required time -1.779
arrival time 1.726
-------------------------------------------------------------------
slack -0.053
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout0
Waveform(ns): { 0.000 10.000 }
Period(ns): 20.000
Sources: { MMCME2_ADV/CLKOUT0 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.495 20.000 17.505 a2owb/c0/lq0/dat/dc32K.tridcarr/Nways[6].Narrs[3].wayArr/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT0 n/a 213.360 20.000 193.360 MMCME2_ADV/CLKOUT0
Low Pulse Width Slow RAMD64E/CLK n/a 0.910 10.000 9.090 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
High Pulse Width Slow RAMD64E/CLK n/a 0.910 10.000 9.090 a2owb/c0/iuq0/iuq_cpl_top0/iuq_cpl0/iuq_cpl_arr/xhdl0.array_gen0[0].RAM64X1D0/DP/CLK
---------------------------------------------------------------------------------------------------
From Clock: crg_clkout1
To Clock: crg_clkout1
Setup : 0 Failing Endpoints, Worst Slack 5.647ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.102ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 4.650ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 5.647ns (required time - arrival time)
Source: a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
(rising edge-triggered cell RAMB36E1 clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: crg_clkout1
Path Type: Setup (Max at Slow Process Corner)
Requirement: 10.000ns (crg_clkout1 rise@10.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 3.312ns (logic 2.145ns (64.762%) route 1.167ns (35.238%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.315ns = ( 14.315 - 10.000 )
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.272ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.539ns
Phase Error (PE): 0.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.088 3.693 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.584 4.277 crg_clkout1
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG_1/O
net (fo=205, unplaced) 0.584 4.981 a2owb/c0/iuq0/bht2/bht0/CLK
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
------------------------------------------------------------------- -------------------
RAMB36E1 (Prop_ramb36e1_CLKARDCLK_DOADO[16])
2.080 7.061 r a2owb/c0/iuq0/bht2/bht0/bram0a/DOADO[16]
net (fo=1, unplaced) 0.584 7.644 a2owb/c0/iuq0/bht2/bht0/r_data_out_0_bram[20]
LUT2 (Prop_lut2_I0_O) 0.065 7.709 r a2owb/c0/iuq0/bht2/bht0/bram0a_i_17__1/O
net (fo=1, unplaced) 0.584 8.293 a2owb/c0/iuq0/bht2/bht0/w_data_in_0[15]
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/DIADI[16]
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
10.000 10.000 r
L17 0.000 10.000 r clk12 (IN)
net (fo=0) 0.000 10.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.539 11.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 12.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 12.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 12.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 12.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 13.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.083 13.209 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.554 13.763 crg_clkout1
BUFG (Prop_bufg_I_O) 0.113 13.876 r BUFG_1/O
net (fo=205, unplaced) 0.439 14.315 a2owb/c0/iuq0/bht2/bht0/CLK
RAMB36E1 r a2owb/c0/iuq0/bht2/bht0/bram0a/CLKARDCLK
clock pessimism 0.520 14.836
clock uncertainty -0.272 14.564
RAMB36E1 (Setup_ramb36e1_CLKARDCLK_DIADI[16])
-0.624 13.940 a2owb/c0/iuq0/bht2/bht0/bram0a
-------------------------------------------------------------------
required time 13.940
arrival time -8.293
-------------------------------------------------------------------
slack 5.647
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.102ns (arrival time - required time)
Source: a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Destination: a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
(rising edge-triggered cell FDRE clocked by crg_clkout1 {rise@0.000ns fall@5.000ns period=10.000ns})
Path Group: crg_clkout1
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout1 rise@0.000ns - crg_clkout1 rise@0.000ns)
Data Path Delay: 0.316ns (logic 0.168ns (53.243%) route 0.148ns (46.757%))
Logic Levels: 1 (LUT2=1)
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.050 0.990 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.246 1.236 crg_clkout1
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG_1/O
net (fo=205, unplaced) 0.114 1.376 a2owb/c0/iuq0/bht0/bht0/CLK
FDRE r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/C
------------------------------------------------------------------- -------------------
FDRE (Prop_fdre_C_Q) 0.104 1.480 r a2owb/c0/iuq0/bht0/bht0/toggle2x_q_reg/Q
net (fo=1, unplaced) 0.148 1.627 a2owb/c0/iuq0/bht0/bht0/toggle2x_q
LUT2 (Prop_lut2_I0_O) 0.064 1.691 r a2owb/c0/iuq0/bht0/bht0/gate_fq_i_1__1/O
net (fo=1, unplaced) 0.000 1.691 a2owb/c0/iuq0/bht0/bht0/gate_d
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/D
------------------------------------------------------------------- -------------------
(clock crg_clkout1 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT1)
0.053 1.502 r MMCME2_ADV/CLKOUT1
net (fo=1, unplaced) 0.259 1.761 crg_clkout1
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG_1/O
net (fo=205, unplaced) 0.259 2.050 a2owb/c0/iuq0/bht0/bht0/CLK
FDRE r a2owb/c0/iuq0/bht0/bht0/gate_fq_reg/C
clock pessimism -0.530 1.521
FDRE (Hold_fdre_C_D) 0.069 1.590 a2owb/c0/iuq0/bht0/bht0/gate_fq_reg
-------------------------------------------------------------------
required time -1.590
arrival time 1.691
-------------------------------------------------------------------
slack 0.102
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout1
Waveform(ns): { 0.000 5.000 }
Period(ns): 10.000
Sources: { MMCME2_ADV/CLKOUT1 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a RAMB36E1/CLKARDCLK n/a 2.183 10.000 7.817 a2owb/c0/lq0/ctl/derat/derat_cam/bram0/CLKARDCLK
Max Period n/a MMCME2_ADV/CLKOUT1 n/a 213.360 10.000 203.360 MMCME2_ADV/CLKOUT1
Low Pulse Width Slow FDRE/C n/a 0.350 5.000 4.650 a2owb/c0/mmu0/tlb_gen_instance.lru_array0/gate_fq_reg/C
High Pulse Width Fast FDRE/C n/a 0.350 5.000 4.650 a2owb/c0/mmu0/tlb_gen_instance.lru_array0/gate_fq_reg/C
---------------------------------------------------------------------------------------------------
From Clock: crg_clkout2
To Clock: crg_clkout2
Setup : 0 Failing Endpoints, Worst Slack 1.153ns, Total Violation 0.000ns
Hold : 0 Failing Endpoints, Worst Slack 0.001ns, Total Violation 0.000ns
PW : 0 Failing Endpoints, Worst Slack 0.264ns, Total Violation 0.000ns
---------------------------------------------------------------------------------------------------
Max Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 1.153ns (required time - arrival time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: crg_clkout2
Path Type: Setup (Max at Slow Process Corner)
Requirement: 2.000ns (MaxDelay Path 2.000ns)
Data Path Delay: 0.425ns (logic 0.281ns (66.118%) route 0.144ns (33.882%))
Logic Levels: 0
Clock Path Skew: -0.145ns (DCD - SCD + CPR)
Destination Clock Delay (DCD): 4.315ns
Source Clock Delay (SCD): 4.981ns
Clock Pessimism Removal (CPR): 0.520ns
Clock Uncertainty: 0.246ns ((TSJ^2 + DJ^2)^1/2) / 2 + PE
Total System Jitter (TSJ): 0.071ns
Discrete Jitter (DJ): 0.487ns
Phase Error (PE): 0.000ns
Timing Exception: MaxDelay Path 2.000ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.680 1.680 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.584 2.264 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.120 2.384 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.584 2.968 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.053 3.021 r clk12_inst/O
net (fo=9, unplaced) 0.584 3.605 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.088 3.693 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.584 4.277 crg_clkout2
BUFG (Prop_bufg_I_O) 0.120 4.397 r BUFG_2/O
net (fo=8, unplaced) 0.584 4.981 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.281 5.262 r FDPE_4/Q
net (fo=1, unplaced) 0.144 5.406 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------
max delay 2.000 2.000
L17 0.000 2.000 r clk12 (IN)
net (fo=0) 0.000 2.000 clk12
L17 IBUF (Prop_ibuf_I_O) 1.539 3.539 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.554 4.093 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.113 4.206 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.439 4.645 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.042 4.687 r clk12_inst/O
net (fo=9, unplaced) 0.439 5.126 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.083 5.209 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.554 5.763 crg_clkout2
BUFG (Prop_bufg_I_O) 0.113 5.876 r BUFG_2/O
net (fo=8, unplaced) 0.439 6.315 idelay_clk
FDPE r FDPE_5/C
clock pessimism 0.520 6.836
clock uncertainty -0.246 6.589
FDPE (Setup_fdpe_C_D) -0.031 6.558 FDPE_5
-------------------------------------------------------------------
required time 6.558
arrival time -5.406
-------------------------------------------------------------------
slack 1.153
Min Delay Paths
--------------------------------------------------------------------------------------
Slack (MET) : 0.001ns (arrival time - required time)
Source: FDPE_4/C
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Destination: FDPE_5/D
(rising edge-triggered cell FDPE clocked by crg_clkout2 {rise@0.000ns fall@2.500ns period=5.000ns})
Path Group: crg_clkout2
Path Type: Hold (Min at Fast Process Corner)
Requirement: 0.000ns (crg_clkout2 rise@0.000ns - crg_clkout2 rise@0.000ns)
Data Path Delay: 0.165ns (logic 0.104ns (63.146%) route 0.061ns (36.854%))
Logic Levels: 0
Clock Path Skew: 0.145ns (DCD - SCD - CPR)
Destination Clock Delay (DCD): 2.050ns
Source Clock Delay (SCD): 1.376ns
Clock Pessimism Removal (CPR): 0.530ns
Location Delay type Incr(ns) Path(ns) Netlist Resource(s)
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.412 0.412 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.246 0.658 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.026 0.684 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.114 0.798 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.028 0.826 r clk12_inst/O
net (fo=9, unplaced) 0.114 0.940 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.050 0.990 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.246 1.236 crg_clkout2
BUFG (Prop_bufg_I_O) 0.026 1.262 r BUFG_2/O
net (fo=8, unplaced) 0.114 1.376 idelay_clk
FDPE r FDPE_4/C
------------------------------------------------------------------- -------------------
FDPE (Prop_fdpe_C_Q) 0.104 1.480 r FDPE_4/Q
net (fo=1, unplaced) 0.061 1.540 xilinxasyncresetsynchronizerimpl2_rst_meta
FDPE r FDPE_5/D
------------------------------------------------------------------- -------------------
(clock crg_clkout2 rise edge)
0.000 0.000 r
L17 0.000 0.000 r clk12 (IN)
net (fo=0) 0.000 0.000 clk12
L17 IBUF (Prop_ibuf_I_O) 0.607 0.607 r clk12_IBUF_inst/O
net (fo=1, unplaced) 0.259 0.866 clk12_IBUF
BUFG (Prop_bufg_I_O) 0.030 0.896 r clk12_IBUF_BUFG_inst/O
net (fo=1, unplaced) 0.259 1.155 clk12_IBUF_BUFG
LUT1 (Prop_lut1_I0_O) 0.035 1.190 r clk12_inst/O
net (fo=9, unplaced) 0.259 1.449 crg_clkin
MMCME2_ADV (Prop_mmcme2_adv_CLKIN1_CLKOUT2)
0.053 1.502 r MMCME2_ADV/CLKOUT2
net (fo=1, unplaced) 0.259 1.761 crg_clkout2
BUFG (Prop_bufg_I_O) 0.030 1.791 r BUFG_2/O
net (fo=8, unplaced) 0.259 2.050 idelay_clk
FDPE r FDPE_5/C
clock pessimism -0.530 1.521
FDPE (Hold_fdpe_C_D) 0.019 1.540 FDPE_5
-------------------------------------------------------------------
required time -1.540
arrival time 1.540
-------------------------------------------------------------------
slack 0.001
Pulse Width Checks
--------------------------------------------------------------------------------------
Clock Name: crg_clkout2
Waveform(ns): { 0.000 2.500 }
Period(ns): 5.000
Sources: { MMCME2_ADV/CLKOUT2 }
Check Type Corner Lib Pin Reference Pin Required(ns) Actual(ns) Slack(ns) Location Pin
Min Period n/a IDELAYCTRL/REFCLK n/a 3.225 5.000 1.775 IDELAYCTRL/REFCLK
Max Period n/a IDELAYCTRL/REFCLK n/a 5.264 5.000 0.264 IDELAYCTRL/REFCLK
Low Pulse Width Fast FDPE/C n/a 0.350 2.500 2.150 FDPE_4/C
High Pulse Width Fast FDPE/C n/a 0.350 2.500 2.150 FDPE_4/C