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578 lines
19 KiB
Verilog
578 lines
19 KiB
Verilog
// © IBM Corp. 2020
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// Licensed under the Apache License, Version 2.0 (the "License"), as modified by
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// the terms below; you may not use the files in this repository except in
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// compliance with the License as modified.
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// You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0
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//
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// Modified Terms:
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//
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// 1) For the purpose of the patent license granted to you in Section 3 of the
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// License, the "Work" hereby includes implementations of the work of authorship
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// in physical form.
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//
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// 2) Notwithstanding any terms to the contrary in the License, any licenses
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// necessary for implementation of the Work that are available from OpenPOWER
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// via the Power ISA End User License Agreement (EULA) are explicitly excluded
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// hereunder, and may be obtained from OpenPOWER under the terms and conditions
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// of the EULA.
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//
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// Unless required by applicable law or agreed to in writing, the reference design
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// distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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// WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License
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// for the specific language governing permissions and limitations under the License.
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//
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// Additional rights, including the ability to physically implement a softcore that
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// is compliant with the required sections of the Power ISA Specification, are
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// available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be
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// obtained (along with the Power ISA) here: https://openpowerfoundation.org.
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`timescale 1 ns / 1 ns
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// *********************************************************************
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//
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// This is the ENTITY for tri_bht_512x4_1r1w
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//
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// *********************************************************************
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(* block_type="soft" *)
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(* recursive_synthesis="2" *)
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(* pin_default_power_domain="vdd" *)
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(* pin_default_ground_domain ="gnd" *)
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`include "tri_a2o.vh"
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module tri_bht_512x4_1r1w(
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gnd,
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vdd,
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vcs,
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nclk,
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pc_iu_func_sl_thold_2,
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pc_iu_sg_2,
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pc_iu_time_sl_thold_2,
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pc_iu_abst_sl_thold_2,
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pc_iu_ary_nsl_thold_2,
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pc_iu_repr_sl_thold_2,
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pc_iu_bolt_sl_thold_2,
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tc_ac_ccflush_dc,
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tc_ac_scan_dis_dc_b,
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clkoff_b,
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scan_diag_dc,
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act_dis,
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d_mode,
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delay_lclkr,
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mpw1_b,
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mpw2_b,
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g8t_clkoff_b,
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g8t_d_mode,
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g8t_delay_lclkr,
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g8t_mpw1_b,
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g8t_mpw2_b,
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func_scan_in,
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time_scan_in,
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abst_scan_in,
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repr_scan_in,
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func_scan_out,
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time_scan_out,
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abst_scan_out,
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repr_scan_out,
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pc_iu_abist_di_0,
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pc_iu_abist_g8t_bw_1,
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pc_iu_abist_g8t_bw_0,
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pc_iu_abist_waddr_0,
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pc_iu_abist_g8t_wenb,
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pc_iu_abist_raddr_0,
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pc_iu_abist_g8t1p_renb_0,
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an_ac_lbist_ary_wrt_thru_dc,
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pc_iu_abist_ena_dc,
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pc_iu_abist_wl128_comp_ena,
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pc_iu_abist_raw_dc_b,
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pc_iu_abist_g8t_dcomp,
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pc_iu_bo_enable_2,
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pc_iu_bo_reset,
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pc_iu_bo_unload,
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pc_iu_bo_repair,
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pc_iu_bo_shdata,
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pc_iu_bo_select,
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iu_pc_bo_fail,
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iu_pc_bo_diagout,
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r_act,
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w_act,
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r_addr,
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w_addr,
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data_in,
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data_out0,
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data_out1,
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data_out2,
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data_out3,
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pc_iu_init_reset
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);
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// power pins
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inout gnd;
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inout vdd;
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inout vcs;
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// clock and clockcontrol ports
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input [0:`NCLK_WIDTH-1] nclk;
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input pc_iu_func_sl_thold_2;
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input pc_iu_sg_2;
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input pc_iu_time_sl_thold_2;
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input pc_iu_abst_sl_thold_2;
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input pc_iu_ary_nsl_thold_2;
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input pc_iu_repr_sl_thold_2;
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input pc_iu_bolt_sl_thold_2;
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input tc_ac_ccflush_dc;
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input tc_ac_scan_dis_dc_b;
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input clkoff_b;
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input scan_diag_dc;
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input act_dis;
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input d_mode;
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input delay_lclkr;
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input mpw1_b;
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input mpw2_b;
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input g8t_clkoff_b;
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input g8t_d_mode;
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input [0:4] g8t_delay_lclkr;
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input [0:4] g8t_mpw1_b;
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input g8t_mpw2_b;
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input func_scan_in;
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input time_scan_in;
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input abst_scan_in;
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input repr_scan_in;
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output func_scan_out;
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output time_scan_out;
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output abst_scan_out;
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output repr_scan_out;
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input [0:3] pc_iu_abist_di_0;
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input pc_iu_abist_g8t_bw_1;
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input pc_iu_abist_g8t_bw_0;
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input [3:9] pc_iu_abist_waddr_0;
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input pc_iu_abist_g8t_wenb;
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input [3:9] pc_iu_abist_raddr_0;
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input pc_iu_abist_g8t1p_renb_0;
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input an_ac_lbist_ary_wrt_thru_dc;
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input pc_iu_abist_ena_dc;
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input pc_iu_abist_wl128_comp_ena;
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input pc_iu_abist_raw_dc_b;
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input [0:3] pc_iu_abist_g8t_dcomp;
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// BOLT-ON
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input pc_iu_bo_enable_2; // general bolt-on enable
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input pc_iu_bo_reset; // reset
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input pc_iu_bo_unload; // unload sticky bits
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input pc_iu_bo_repair; // execute sticky bit decode
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input pc_iu_bo_shdata; // shift data for timing write and diag loop
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input pc_iu_bo_select; // select for mask and hier writes
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output iu_pc_bo_fail; // fail/no-fix reg
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output iu_pc_bo_diagout;
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// ports
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input r_act;
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input [0:3] w_act;
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input [0:8] r_addr;
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input [0:8] w_addr;
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input data_in;
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output data_out0;
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output data_out1;
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output data_out2;
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output data_out3;
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input pc_iu_init_reset;
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//--------------------------
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// constants
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//--------------------------
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parameter data_in_offset = 0;
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parameter w_act_offset = data_in_offset + 1;
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parameter r_act_offset = w_act_offset + 4;
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parameter w_addr_offset = r_act_offset + 1;
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parameter r_addr_offset = w_addr_offset + 9;
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parameter data_out_offset = r_addr_offset + 9;
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parameter reset_w_addr_offset = data_out_offset + 4;
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parameter array_offset = reset_w_addr_offset + 9;
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parameter scan_right = array_offset + 1 - 1;
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//--------------------------
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// signals
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//--------------------------
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wire pc_iu_func_sl_thold_1;
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wire pc_iu_func_sl_thold_0;
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wire pc_iu_func_sl_thold_0_b;
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wire pc_iu_time_sl_thold_1;
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wire pc_iu_time_sl_thold_0;
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wire pc_iu_ary_nsl_thold_1;
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wire pc_iu_ary_nsl_thold_0;
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wire pc_iu_abst_sl_thold_1;
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wire pc_iu_abst_sl_thold_0;
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wire pc_iu_repr_sl_thold_1;
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wire pc_iu_repr_sl_thold_0;
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wire pc_iu_bolt_sl_thold_1;
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wire pc_iu_bolt_sl_thold_0;
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wire pc_iu_sg_1;
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wire pc_iu_sg_0;
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wire force_t;
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wire [0:scan_right] siv;
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wire [0:scan_right] sov /*verilator split_var*/;
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wire tiup;
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wire [0:3] data_out_d;
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wire [0:3] data_out_q;
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wire ary_w_en;
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wire [0:8] ary_w_addr;
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wire [0:15] ary_w_sel;
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wire [0:15] ary_w_data;
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wire ary_r_en;
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wire [0:8] ary_r_addr;
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wire [0:15] ary_r_data;
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wire [0:3] data_out;
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wire [0:3] write_thru;
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wire data_in_d;
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wire data_in_q;
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wire [0:3] w_act_d;
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wire [0:3] w_act_q;
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wire r_act_d;
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wire r_act_q;
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wire [0:8] w_addr_d;
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wire [0:8] w_addr_q;
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wire [0:8] r_addr_d;
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wire [0:8] r_addr_q;
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wire lat_wi_act;
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wire lat_ri_act;
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wire lat_ro_act;
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wire reset_act;
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wire [0:8] reset_w_addr_d;
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wire [0:8] reset_w_addr_q;
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assign tiup = 1'b1;
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assign reset_act = pc_iu_init_reset;
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assign reset_w_addr_d[0:8] = reset_w_addr_q[0:8] + 9'b000000001;
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assign data_out0 = data_out_q[0];
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assign data_out1 = data_out_q[1];
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assign data_out2 = data_out_q[2];
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assign data_out3 = data_out_q[3];
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assign ary_w_en = reset_act | (|(w_act[0:3]) & (~((w_addr[0:8] == r_addr[0:8]) & r_act == 1'b1)));
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assign ary_w_addr[0:8] = reset_act ? reset_w_addr_q[0:8] : w_addr[0:8];
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assign ary_w_sel[0] = reset_act ? 1'b1 : w_act[0];
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assign ary_w_sel[1] = reset_act ? 1'b1 : w_act[1];
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assign ary_w_sel[2] = reset_act ? 1'b1 : w_act[2];
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assign ary_w_sel[3] = reset_act ? 1'b1 : w_act[3];
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assign ary_w_sel[4] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[5] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[6] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[7] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[8] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[9] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[10] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[11] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[12] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[13] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[14] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_sel[15] = reset_act ? 1'b1 : 1'b0;
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assign ary_w_data[0:15] = reset_act ? 16'b0000000000000000:
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{data_in, data_in, data_in, data_in, 12'b000000000000};
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assign ary_r_en = r_act;
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assign ary_r_addr[0:8] = r_addr[0:8];
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assign data_out[0:3] = ary_r_data[0:3];
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//write through support
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assign data_in_d = data_in;
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assign w_act_d[0:3] = w_act[0:3];
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assign r_act_d = r_act;
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assign w_addr_d[0:8] = w_addr[0:8];
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assign r_addr_d[0:8] = r_addr[0:8];
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assign write_thru[0:3] = ((w_addr_q[0:8] == r_addr_q[0:8]) & r_act_q == 1'b1) ? w_act_q[0:3] :
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4'b0000;
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assign data_out_d[0] = (write_thru[0] == 1'b1) ? data_in_q :
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data_out[0];
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assign data_out_d[1] = (write_thru[1] == 1'b1) ? data_in_q :
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data_out[1];
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assign data_out_d[2] = (write_thru[2] == 1'b1) ? data_in_q :
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data_out[2];
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assign data_out_d[3] = (write_thru[3] == 1'b1) ? data_in_q :
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data_out[3];
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//latch acts
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assign lat_wi_act = |(w_act[0:3]);
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assign lat_ri_act = r_act;
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assign lat_ro_act = r_act_q;
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//-----------------------------------------------
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// array
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//-----------------------------------------------
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tri_512x16_1r1w_1 bht0(
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.gnd(gnd),
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.vdd(vdd),
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.vcs(vcs),
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.nclk(nclk),
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.rd_act(ary_r_en),
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.wr_act(ary_w_en),
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.lcb_d_mode_dc(g8t_d_mode),
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.lcb_clkoff_dc_b(g8t_clkoff_b),
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.lcb_mpw1_dc_b(g8t_mpw1_b),
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.lcb_mpw2_dc_b(g8t_mpw2_b),
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.lcb_delay_lclkr_dc(g8t_delay_lclkr),
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.ccflush_dc(tc_ac_ccflush_dc),
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.scan_dis_dc_b(tc_ac_scan_dis_dc_b),
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.scan_diag_dc(scan_diag_dc),
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.func_scan_in(siv[array_offset]),
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.func_scan_out(sov[array_offset]),
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.lcb_sg_0(pc_iu_sg_0),
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.lcb_sl_thold_0_b(pc_iu_func_sl_thold_0_b),
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.lcb_time_sl_thold_0(pc_iu_time_sl_thold_0),
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.lcb_abst_sl_thold_0(pc_iu_abst_sl_thold_0),
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.lcb_ary_nsl_thold_0(pc_iu_ary_nsl_thold_0),
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.lcb_repr_sl_thold_0(pc_iu_repr_sl_thold_0),
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.time_scan_in(time_scan_in),
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.time_scan_out(time_scan_out),
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.abst_scan_in(abst_scan_in),
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.abst_scan_out(abst_scan_out),
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.repr_scan_in(repr_scan_in),
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.repr_scan_out(repr_scan_out),
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.abist_di(pc_iu_abist_di_0),
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.abist_bw_odd(pc_iu_abist_g8t_bw_1),
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.abist_bw_even(pc_iu_abist_g8t_bw_0),
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.abist_wr_adr(pc_iu_abist_waddr_0),
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.wr_abst_act(pc_iu_abist_g8t_wenb),
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.abist_rd0_adr(pc_iu_abist_raddr_0),
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.rd0_abst_act(pc_iu_abist_g8t1p_renb_0),
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.tc_lbist_ary_wrt_thru_dc(an_ac_lbist_ary_wrt_thru_dc),
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.abist_ena_1(pc_iu_abist_ena_dc),
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.abist_g8t_rd0_comp_ena(pc_iu_abist_wl128_comp_ena),
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.abist_raw_dc_b(pc_iu_abist_raw_dc_b),
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.obs0_abist_cmp(pc_iu_abist_g8t_dcomp),
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.lcb_bolt_sl_thold_0(pc_iu_bolt_sl_thold_0),
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.pc_bo_enable_2(pc_iu_bo_enable_2),
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.pc_bo_reset(pc_iu_bo_reset),
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.pc_bo_unload(pc_iu_bo_unload),
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.pc_bo_repair(pc_iu_bo_repair),
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.pc_bo_shdata(pc_iu_bo_shdata),
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.pc_bo_select(pc_iu_bo_select),
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.bo_pc_failout(iu_pc_bo_fail),
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.bo_pc_diagloop(iu_pc_bo_diagout),
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.tri_lcb_mpw1_dc_b(mpw1_b),
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.tri_lcb_mpw2_dc_b(mpw2_b),
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.tri_lcb_delay_lclkr_dc(delay_lclkr),
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.tri_lcb_clkoff_dc_b(clkoff_b),
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.tri_lcb_act_dis_dc(act_dis),
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.bw(ary_w_sel),
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.wr_adr(ary_w_addr),
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.rd_adr(ary_r_addr),
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.di(ary_w_data),
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.dout(ary_r_data)
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);
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//-----------------------------------------------
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// latches
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//-----------------------------------------------
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tri_rlmlatch_p #(.INIT(0)) data_in_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(lat_wi_act),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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.mpw1_b(mpw1_b),
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.mpw2_b(mpw2_b),
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.d_mode(d_mode),
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.scin(siv[data_in_offset:data_in_offset]),
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.scout(sov[data_in_offset:data_in_offset]),
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.din(data_in_d),
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.dout(data_in_q)
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);
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tri_rlmreg_p #(.WIDTH(4), .INIT(0)) w_act_reg(
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.vd(vdd),
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.gd(gnd),
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.nclk(nclk),
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.act(tiup),
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.thold_b(pc_iu_func_sl_thold_0_b),
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.sg(pc_iu_sg_0),
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.force_t(force_t),
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.delay_lclkr(delay_lclkr),
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|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[w_act_offset:w_act_offset + 4 - 1]),
|
|
.scout(sov[w_act_offset:w_act_offset + 4 - 1]),
|
|
.din(w_act_d),
|
|
.dout(w_act_q)
|
|
);
|
|
|
|
|
|
tri_rlmlatch_p #(.INIT(0)) r_act_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(tiup),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[r_act_offset]),
|
|
.scout(sov[r_act_offset]),
|
|
.din(r_act_d),
|
|
.dout(r_act_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) w_addr_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(lat_wi_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[w_addr_offset:w_addr_offset + 9 - 1]),
|
|
.scout(sov[w_addr_offset:w_addr_offset + 9 - 1]),
|
|
.din(w_addr_d),
|
|
.dout(w_addr_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) r_addr_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(lat_ri_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[r_addr_offset:r_addr_offset + 9 - 1]),
|
|
.scout(sov[r_addr_offset:r_addr_offset + 9 - 1]),
|
|
.din(r_addr_d),
|
|
.dout(r_addr_q)
|
|
);
|
|
|
|
|
|
tri_rlmreg_p #(.WIDTH(4), .INIT(0)) data_out_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(lat_ro_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[data_out_offset:data_out_offset + 4 - 1]),
|
|
.scout(sov[data_out_offset:data_out_offset + 4 - 1]),
|
|
.din(data_out_d),
|
|
.dout(data_out_q)
|
|
);
|
|
|
|
tri_rlmreg_p #(.WIDTH(9), .INIT(0)) reset_w_addr_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.act(reset_act),
|
|
.thold_b(pc_iu_func_sl_thold_0_b),
|
|
.sg(pc_iu_sg_0),
|
|
.force_t(force_t),
|
|
.delay_lclkr(delay_lclkr),
|
|
.mpw1_b(mpw1_b),
|
|
.mpw2_b(mpw2_b),
|
|
.d_mode(d_mode),
|
|
.scin(siv[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
|
|
.scout(sov[reset_w_addr_offset:reset_w_addr_offset + 9 - 1]),
|
|
.din(reset_w_addr_d),
|
|
.dout(reset_w_addr_q)
|
|
);
|
|
|
|
//-----------------------------------------------
|
|
// pervasive
|
|
//-----------------------------------------------
|
|
|
|
|
|
tri_plat #(.WIDTH(7)) perv_2to1_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(tc_ac_ccflush_dc),
|
|
.din({pc_iu_func_sl_thold_2, pc_iu_sg_2, pc_iu_time_sl_thold_2, pc_iu_abst_sl_thold_2, pc_iu_ary_nsl_thold_2, pc_iu_repr_sl_thold_2, pc_iu_bolt_sl_thold_2}),
|
|
.q({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1})
|
|
);
|
|
|
|
|
|
tri_plat #(.WIDTH(7)) perv_1to0_reg(
|
|
.vd(vdd),
|
|
.gd(gnd),
|
|
.nclk(nclk),
|
|
.flush(tc_ac_ccflush_dc),
|
|
.din({pc_iu_func_sl_thold_1, pc_iu_sg_1, pc_iu_time_sl_thold_1, pc_iu_abst_sl_thold_1, pc_iu_ary_nsl_thold_1, pc_iu_repr_sl_thold_1, pc_iu_bolt_sl_thold_1}),
|
|
.q({pc_iu_func_sl_thold_0, pc_iu_sg_0, pc_iu_time_sl_thold_0, pc_iu_abst_sl_thold_0, pc_iu_ary_nsl_thold_0, pc_iu_repr_sl_thold_0, pc_iu_bolt_sl_thold_0})
|
|
);
|
|
|
|
|
|
tri_lcbor perv_lcbor(
|
|
.clkoff_b(clkoff_b),
|
|
.thold(pc_iu_func_sl_thold_0),
|
|
.sg(pc_iu_sg_0),
|
|
.act_dis(act_dis),
|
|
.force_t(force_t),
|
|
.thold_b(pc_iu_func_sl_thold_0_b)
|
|
);
|
|
|
|
//-----------------------------------------------
|
|
// scan
|
|
//-----------------------------------------------
|
|
|
|
assign siv[0:scan_right] = {func_scan_in, sov[0:scan_right - 1]};
|
|
assign func_scan_out = sov[scan_right];
|
|
|
|
|
|
endmodule
|