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118 lines
3.0 KiB
Python
118 lines
3.0 KiB
Python
# OP Environment
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import cocotb
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from cocotb.triggers import Timer
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from cocotb.handle import Force
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from cocotb.handle import Release
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from dotmap import DotMap
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# ------------------------------------------------------------------------------------------------
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# Classes
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class Sim(DotMap):
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def msg(self, m):
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self.dut._log.info(f'[{self.cycle:08d}] {m}') #wtf do multiline if /n in m
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def __init__(self, dut, cfg=None):
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super().__init__()
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self.dut = dut
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# defaults
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self.memFiles = ['../mem/boot_ieq1.bin.hex'] #wtf cmdline parm
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self.threads = None
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self.resetCycle = 10
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self.hbCycles = 100
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self.clk2x = True
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self.clk4x = False
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self.resetAddr = 0xFFFFFFFC
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self.resetOp = 0x48000002
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self.maxCycles = 500
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self.memFiles = None
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self.config = DotMap()
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self.config.core = DotMap({
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'creditsLd': None,
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'creditsSt': None,
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'creditsLdStSingle': False
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})
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self.config.a2l2 = DotMap({
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'badAddr': [('E0','E0', 'IRW')]
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})
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# json
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if cfg is not None:
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pass
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# runtime
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self.cycle = 0
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self.ok = True
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self.fail = None
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self.done = False
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if self.threads is None:
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try:
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v = dut.an_ac_pm_thread_stop[1].value
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self.threads = 2
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except:
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self.threads = 1
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self.msg(f'Set threads={self.threads}.')
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class TransQ(DotMap):
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def __init__(self):
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super().__init__()
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class Memory(DotMap):
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def __init__(self, sim, default=0, logStores=True):
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super().__init__()
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self.sim = sim
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self.data = {}
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self.le = False
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self.default = default # default word data for unloaded
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self.logStores = logStores
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def loadFile(self, filename, format='ascii', addr=0, le=0):
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# format # binary, ascii, ascii w/addr
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# le: reverse bytes
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try:
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if format == 'ascii':
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with open(filename, 'r') as f:
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lines = f.readlines()
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for line in lines:
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self.data[addr] = int(line, 16) # key is int
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addr += 4
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elif format == 'binary':
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pass
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elif format == 'addrdata':
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pass
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except Exception as e:
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self.sim.msg(f'Error reading {filename}:\n{e}')
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raise IOError
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# word-aligned byte address
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def read(self, addr):
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try:
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addr = addr + 0
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except:
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addr = int(addr, 16)
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if addr in self.data:
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return self.data[addr]
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else:
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return self.default
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# word-aligned byte address + data
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def write(self, addr, data):
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try:
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addr = addr + 0
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except:
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addr = int(addr, 16)
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try:
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data = data + 0
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except:
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data = int(data, 16)
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if self.logStores:
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if addr not in self.data:
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self.sim.msg(f'Mem Update: @{addr:08X} XXXXXXXX->{data:08X}')
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else:
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self.sim.msg(f'Mem Update: @{addr:08X} {self.data[addr]:08X}->{data:08X}')
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self.data[addr] = data
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