OpenROAD v2.0-1901-g6157d4945 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223]     Created 11 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225]     Created 437 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0094] 		Created 200000 Insts
[INFO ODB-0094] 		Created 300000 Insts
[INFO ODB-0094] 		Created 400000 Insts
[INFO ODB-0094] 		Created 500000 Insts
[INFO ODB-0094] 		Created 600000 Insts
[INFO ODB-0094] 		Created 700000 Insts
[INFO ODB-0094] 		Created 800000 Insts
[INFO ODB-0094] 		Created 900000 Insts
[INFO ODB-0094] 		Created 1000000 Insts
[INFO ODB-0094] 		Created 1100000 Insts
[INFO ODB-0094] 		Created 1200000 Insts
[INFO ODB-0094] 		Created 1300000 Insts
[INFO ODB-0094] 		Created 1400000 Insts
[INFO ODB-0094] 		Created 1500000 Insts
[INFO ODB-0094] 		Created 1600000 Insts
[INFO ODB-0094] 		Created 1700000 Insts
[INFO ODB-0094] 		Created 1800000 Insts
[INFO ODB-0094] 		Created 1900000 Insts
[INFO ODB-0094] 		Created 2000000 Insts
[INFO ODB-0094] 		Created 2100000 Insts
[INFO ODB-0094] 		Created 2200000 Insts
[INFO ODB-0094] 		Created 2300000 Insts
[INFO ODB-0094] 		Created 2400000 Insts
[INFO ODB-0094] 		Created 2500000 Insts
[INFO ODB-0094] 		Created 2600000 Insts
[INFO ODB-0097] 		Created 100000 Nets
[INFO ODB-0097] 		Created 200000 Nets
[INFO ODB-0097] 		Created 300000 Nets
[INFO ODB-0130]     Created 254 pins.
[INFO ODB-0131]     Created 2697583 components and 6814077 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 5395166 connections.
[INFO ODB-0133]     Created 378585 nets and 1412715 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   A2P_WB
Die area:                 ( 0 0 ) ( 5200000 4609140 )
Number of track patterns: 12
Number of DEF vias:       4
Number of components:     2697583
Number of terminals:      254
Number of snets:          2
Number of nets:           378585

[INFO DRT-0151] Reading guide.
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.
[INFO DRT-0156] guideIn read 500000 guides.
[INFO DRT-0156] guideIn read 600000 guides.
[INFO DRT-0156] guideIn read 700000 guides.
[INFO DRT-0156] guideIn read 800000 guides.
[INFO DRT-0156] guideIn read 900000 guides.
[INFO DRT-0157] guideIn read 1000000 guides.
[INFO DRT-0157] guideIn read 2000000 guides.
[INFO DRT-0157] guideIn read 3000000 guides.

Number of guides:     3438877

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR_MR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
  Complete 400000 instances.
  Complete 500000 instances.
  Complete 600000 instances.
  Complete 700000 instances.
  Complete 800000 instances.
  Complete 900000 instances.
  Complete 1000000 instances.
  Complete 1100000 instances.
  Complete 1200000 instances.
  Complete 1300000 instances.
  Complete 1400000 instances.
  Complete 1500000 instances.
  Complete 1600000 instances.
  Complete 1700000 instances.
  Complete 1800000 instances.
  Complete 1900000 instances.
  Complete 2000000 instances.
  Complete 2100000 instances.
  Complete 2200000 instances.
  Complete 2300000 instances.
  Complete 2400000 instances.
  Complete 2500000 instances.
  Complete 2600000 instances.
[INFO DRT-0164] Number of unique instances = 490.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0019]   Complete 400000 insts.
[INFO DRT-0019]   Complete 500000 insts.
[INFO DRT-0019]   Complete 600000 insts.
[INFO DRT-0019]   Complete 700000 insts.
[INFO DRT-0019]   Complete 800000 insts.
[INFO DRT-0019]   Complete 900000 insts.
[INFO DRT-0019]   Complete 1000000 insts.
[INFO DRT-0019]   Complete 1100000 insts.
[INFO DRT-0019]   Complete 1200000 insts.
[INFO DRT-0019]   Complete 1300000 insts.
[INFO DRT-0019]   Complete 1400000 insts.
[INFO DRT-0019]   Complete 1500000 insts.
[INFO DRT-0019]   Complete 1600000 insts.
[INFO DRT-0019]   Complete 1700000 insts.
[INFO DRT-0019]   Complete 1800000 insts.
[INFO DRT-0019]   Complete 1900000 insts.
[INFO DRT-0019]   Complete 2000000 insts.
[INFO DRT-0019]   Complete 2100000 insts.
[INFO DRT-0019]   Complete 2200000 insts.
[INFO DRT-0019]   Complete 2300000 insts.
[INFO DRT-0019]   Complete 2400000 insts.
[INFO DRT-0019]   Complete 2500000 insts.
[INFO DRT-0019]   Complete 2600000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete FR_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 21301010.
[INFO DRT-0033] mcon shape region query size = 830235.
[INFO DRT-0033] met1 shape region query size = 7752521.
[INFO DRT-0033] via shape region query size = 1351680.
[INFO DRT-0033] met2 shape region query size = 540893.
[INFO DRT-0033] via2 shape region query size = 1081344.
[INFO DRT-0033] met3 shape region query size = 540705.
[INFO DRT-0033] via3 shape region query size = 1081344.
[INFO DRT-0033] met4 shape region query size = 324544.
[INFO DRT-0033] via4 shape region query size = 53856.
[INFO DRT-0033] met5 shape region query size = 54162.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0077]   Complete 2000 pins.
[INFO DRT-0078]   Complete 2115 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0081]   Complete 480 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0083]   Complete 20000 groups.
[INFO DRT-0083]   Complete 30000 groups.
[INFO DRT-0083]   Complete 40000 groups.
[INFO DRT-0083]   Complete 50000 groups.
[INFO DRT-0083]   Complete 60000 groups.
[INFO DRT-0083]   Complete 70000 groups.
[INFO DRT-0083]   Complete 80000 groups.
[INFO DRT-0083]   Complete 90000 groups.
[INFO DRT-0083]   Complete 100000 groups.
[INFO DRT-0083]   Complete 110000 groups.
[INFO DRT-0083]   Complete 120000 groups.
[INFO DRT-0083]   Complete 130000 groups.
[INFO DRT-0083]   Complete 140000 groups.
[INFO DRT-0083]   Complete 150000 groups.
[INFO DRT-0083]   Complete 160000 groups.
[INFO DRT-0083]   Complete 170000 groups.
[INFO DRT-0083]   Complete 180000 groups.
[INFO DRT-0083]   Complete 190000 groups.
[INFO DRT-0083]   Complete 200000 groups.
[INFO DRT-0083]   Complete 210000 groups.
[INFO DRT-0083]   Complete 220000 groups.
[INFO DRT-0083]   Complete 230000 groups.
[INFO DRT-0083]   Complete 240000 groups.
[INFO DRT-0083]   Complete 250000 groups.
[INFO DRT-0083]   Complete 260000 groups.
[INFO DRT-0083]   Complete 270000 groups.
[INFO DRT-0083]   Complete 280000 groups.
[INFO DRT-0083]   Complete 290000 groups.
[INFO DRT-0083]   Complete 300000 groups.
[INFO DRT-0083]   Complete 310000 groups.
[INFO DRT-0083]   Complete 320000 groups.
[INFO DRT-0083]   Complete 330000 groups.
[INFO DRT-0083]   Complete 340000 groups.
[INFO DRT-0083]   Complete 350000 groups.
[INFO DRT-0083]   Complete 360000 groups.
[INFO DRT-0083]   Complete 370000 groups.
[INFO DRT-0083]   Complete 380000 groups.
[INFO DRT-0083]   Complete 390000 groups.
[INFO DRT-0083]   Complete 400000 groups.
[INFO DRT-0083]   Complete 410000 groups.
[INFO DRT-0083]   Complete 420000 groups.
[INFO DRT-0083]   Complete 430000 groups.
[INFO DRT-0083]   Complete 440000 groups.
[INFO DRT-0084]   Complete 449429 groups.
#scanned instances     = 2697583
#unique  instances     = 490
#stdCellGenAp          = 17527
#stdCellValidPlanarAp  = 358
#stdCellValidViaAp     = 12598
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 1412715
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:04, memory = 6445.11 (MB), peak = 6863.20 (MB)
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 667 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 753 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0026]   Complete 50000 origin guides.
[INFO DRT-0026]   Complete 60000 origin guides.
[INFO DRT-0026]   Complete 70000 origin guides.
[INFO DRT-0026]   Complete 80000 origin guides.
[INFO DRT-0026]   Complete 90000 origin guides.
[INFO DRT-0027]   Complete 100000 origin guides.
[INFO DRT-0027]   Complete 200000 origin guides.
[INFO DRT-0027]   Complete 300000 origin guides.
[INFO DRT-0027]   Complete 400000 origin guides.
[INFO DRT-0027]   Complete 500000 origin guides.
[INFO DRT-0027]   Complete 600000 origin guides.
[INFO DRT-0027]   Complete 700000 origin guides.
[INFO DRT-0027]   Complete 800000 origin guides.
[INFO DRT-0027]   Complete 900000 origin guides.
[INFO DRT-0027]   Complete 1000000 origin guides.
[INFO DRT-0027]   Complete 1100000 origin guides.
[INFO DRT-0027]   Complete 1200000 origin guides.
[INFO DRT-0027]   Complete 1300000 origin guides.
[INFO DRT-0027]   Complete 1400000 origin guides.
[INFO DRT-0027]   Complete 1500000 origin guides.
[INFO DRT-0027]   Complete 1600000 origin guides.
[INFO DRT-0027]   Complete 1700000 origin guides.
[INFO DRT-0027]   Complete 1800000 origin guides.
[INFO DRT-0027]   Complete 1900000 origin guides.
[INFO DRT-0027]   Complete 2000000 origin guides.
[INFO DRT-0027]   Complete 2100000 origin guides.
[INFO DRT-0027]   Complete 2200000 origin guides.
[INFO DRT-0027]   Complete 2300000 origin guides.
[INFO DRT-0027]   Complete 2400000 origin guides.
[INFO DRT-0027]   Complete 2500000 origin guides.
[INFO DRT-0027]   Complete 2600000 origin guides.
[INFO DRT-0027]   Complete 2700000 origin guides.
[INFO DRT-0027]   Complete 2800000 origin guides.
[INFO DRT-0027]   Complete 2900000 origin guides.
[INFO DRT-0027]   Complete 3000000 origin guides.
[INFO DRT-0027]   Complete 3100000 origin guides.
[INFO DRT-0027]   Complete 3200000 origin guides.
[INFO DRT-0027]   Complete 3300000 origin guides.
[INFO DRT-0027]   Complete 3400000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete FR_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
  complete 10000 nets.
  complete 20000 nets.
  complete 30000 nets.
  complete 40000 nets.
  complete 50000 nets.
  complete 60000 nets.
  complete 70000 nets.
  complete 80000 nets.
  complete 90000 nets.
  complete 100000 nets.
  complete 200000 nets.
  complete 300000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029]   Complete 10000 nets (guide).
[INFO DRT-0029]   Complete 20000 nets (guide).
[INFO DRT-0029]   Complete 30000 nets (guide).
[INFO DRT-0029]   Complete 40000 nets (guide).
[INFO DRT-0029]   Complete 50000 nets (guide).
[INFO DRT-0029]   Complete 60000 nets (guide).
[INFO DRT-0029]   Complete 70000 nets (guide).
[INFO DRT-0029]   Complete 80000 nets (guide).
[INFO DRT-0029]   Complete 90000 nets (guide).
[INFO DRT-0030]   Complete 100000 nets (guide).
[INFO DRT-0030]   Complete 200000 nets (guide).
[INFO DRT-0030]   Complete 300000 nets (guide).
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete FR_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 1203352.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 1051108.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 648253.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 25242.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 7198.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 57.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 1858803 vertical wires in 16 frboxes and 1076407 horizontal wires in 14 frboxes.
[INFO DRT-0186] Done with 286870 vertical wires in 16 frboxes and 280825 horizontal wires in 14 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:07:24, elapsed time = 00:01:48, memory = 10737.52 (MB), peak = 11458.43 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 10737.52 (MB), peak = 11458.43 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 12167 violations.
    elapsed time = 00:02:03, memory = 16918.98 (MB).
    Completing 20% with 29770 violations.
    elapsed time = 00:04:21, memory = 18092.52 (MB).
    Completing 30% with 35905 violations.
    elapsed time = 00:05:49, memory = 18092.52 (MB).
    Completing 40% with 47661 violations.
    elapsed time = 00:08:33, memory = 18197.21 (MB).
    Completing 50% with 63480 violations.
    elapsed time = 00:10:24, memory = 18836.65 (MB).
    Completing 60% with 80957 violations.
    elapsed time = 00:13:47, memory = 18887.63 (MB).
    Completing 70% with 96555 violations.
    elapsed time = 00:16:52, memory = 19349.36 (MB).
    Completing 80% with 101093 violations.
    elapsed time = 00:18:53, memory = 19368.30 (MB).
    Completing 90% with 111495 violations.
    elapsed time = 00:23:07, memory = 19440.02 (MB).
    Completing 100% with 130135 violations.
    elapsed time = 00:25:19, memory = 20028.93 (MB).
[INFO DRT-0199]   Number of violations = 394551.
[INFO DRT-0267] cpu time = 02:27:31, elapsed time = 00:25:33, memory = 20028.93 (MB), peak = 20028.93 (MB)
Total wire length = 23091697 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10121629 um.
Total wire length on LAYER met2 = 10181715 um.
Total wire length on LAYER met3 = 1734151 um.
Total wire length on LAYER met4 = 1043202 um.
Total wire length on LAYER met5 = 10997 um.
Total number of vias = 3267530.
Up-via summary (total 3267530):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400319
           met1    1812376
           met2      41630
           met3      13108
           met4         97
--------------------------
                   3267530


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 359715 violations.
    elapsed time = 00:01:19, memory = 20028.93 (MB).
    Completing 20% with 317669 violations.
    elapsed time = 00:03:03, memory = 20028.93 (MB).
    Completing 30% with 301649 violations.
    elapsed time = 00:04:03, memory = 20028.93 (MB).
    Completing 40% with 269407 violations.
    elapsed time = 00:05:54, memory = 20028.93 (MB).
    Completing 50% with 229775 violations.
    elapsed time = 00:07:19, memory = 20045.95 (MB).
    Completing 60% with 176877 violations.
    elapsed time = 00:08:50, memory = 19999.26 (MB).
    Completing 70% with 133860 violations.
    elapsed time = 00:10:39, memory = 20037.16 (MB).
    Completing 80% with 118833 violations.
    elapsed time = 00:11:41, memory = 20037.42 (MB).
    Completing 90% with 82534 violations.
    elapsed time = 00:13:41, memory = 20037.42 (MB).
    Completing 100% with 28489 violations.
    elapsed time = 00:15:09, memory = 20111.15 (MB).
[INFO DRT-0199]   Number of violations = 28533.
[INFO DRT-0267] cpu time = 01:25:32, elapsed time = 00:15:25, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22870086 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10025064 um.
Total wire length on LAYER met2 = 10066905 um.
Total wire length on LAYER met3 = 1728309 um.
Total wire length on LAYER met4 = 1038887 um.
Total wire length on LAYER met5 = 10919 um.
Total number of vias = 3245188.
Up-via summary (total 3245188):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399916
           met1    1790124
           met2      42119
           met3      12935
           met4         94
--------------------------
                   3245188


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 28089 violations.
    elapsed time = 00:01:01, memory = 20090.49 (MB).
    Completing 20% with 27306 violations.
    elapsed time = 00:02:35, memory = 20090.49 (MB).
    Completing 30% with 27004 violations.
    elapsed time = 00:03:19, memory = 20090.49 (MB).
    Completing 40% with 26394 violations.
    elapsed time = 00:04:52, memory = 20090.49 (MB).
    Completing 50% with 25260 violations.
    elapsed time = 00:06:07, memory = 20090.49 (MB).
    Completing 60% with 24945 violations.
    elapsed time = 00:07:06, memory = 20090.49 (MB).
    Completing 70% with 24254 violations.
    elapsed time = 00:08:34, memory = 20090.49 (MB).
    Completing 80% with 22460 violations.
    elapsed time = 00:09:25, memory = 20090.49 (MB).
    Completing 90% with 21574 violations.
    elapsed time = 00:10:53, memory = 20090.49 (MB).
    Completing 100% with 19438 violations.
    elapsed time = 00:12:07, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 19514.
[INFO DRT-0267] cpu time = 01:08:00, elapsed time = 00:12:23, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22790296 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9992789 um.
Total wire length on LAYER met2 = 10019692 um.
Total wire length on LAYER met3 = 1727014 um.
Total wire length on LAYER met4 = 1039892 um.
Total wire length on LAYER met5 = 10907 um.
Total number of vias = 3231333.
Up-via summary (total 3231333):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1776923
           met2      41475
           met3      12924
           met4         94
--------------------------
                   3231333


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 18290 violations.
    elapsed time = 00:00:18, memory = 20090.49 (MB).
    Completing 20% with 15799 violations.
    elapsed time = 00:00:57, memory = 20090.49 (MB).
    Completing 30% with 15072 violations.
    elapsed time = 00:01:18, memory = 20090.49 (MB).
    Completing 40% with 13820 violations.
    elapsed time = 00:01:51, memory = 20090.49 (MB).
    Completing 50% with 11255 violations.
    elapsed time = 00:02:18, memory = 20090.49 (MB).
    Completing 60% with 9053 violations.
    elapsed time = 00:02:41, memory = 20090.49 (MB).
    Completing 70% with 6548 violations.
    elapsed time = 00:03:20, memory = 20090.49 (MB).
    Completing 80% with 5799 violations.
    elapsed time = 00:03:36, memory = 20090.49 (MB).
    Completing 90% with 4438 violations.
    elapsed time = 00:04:14, memory = 20090.49 (MB).
    Completing 100% with 883 violations.
    elapsed time = 00:04:47, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 889.
[INFO DRT-0267] cpu time = 00:24:38, elapsed time = 00:04:51, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782902 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9945065 um.
Total wire length on LAYER met2 = 10020430 um.
Total wire length on LAYER met3 = 1766182 um.
Total wire length on LAYER met4 = 1040331 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240237.
Up-via summary (total 3240237):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399918
           met1    1780553
           met2      46682
           met3      12990
           met4         94
--------------------------
                   3240237


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 857 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 20% with 739 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 30% with 725 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 40% with 701 violations.
    elapsed time = 00:00:10, memory = 20090.49 (MB).
    Completing 50% with 623 violations.
    elapsed time = 00:00:13, memory = 20090.49 (MB).
    Completing 60% with 543 violations.
    elapsed time = 00:00:14, memory = 20090.49 (MB).
    Completing 70% with 383 violations.
    elapsed time = 00:00:19, memory = 20090.49 (MB).
    Completing 80% with 336 violations.
    elapsed time = 00:00:20, memory = 20090.49 (MB).
    Completing 90% with 297 violations.
    elapsed time = 00:00:24, memory = 20090.49 (MB).
    Completing 100% with 144 violations.
    elapsed time = 00:00:30, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 144.
[INFO DRT-0267] cpu time = 00:01:54, elapsed time = 00:00:31, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782613 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943857 um.
Total wire length on LAYER met2 = 10020384 um.
Total wire length on LAYER met3 = 1767093 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240368.
Up-via summary (total 3240368):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780550
           met2      46812
           met3      12995
           met4         94
--------------------------
                   3240368


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 144 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 136 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 30% with 136 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 40% with 136 violations.
    elapsed time = 00:00:04, memory = 20090.49 (MB).
    Completing 50% with 127 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 60% with 125 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 70% with 114 violations.
    elapsed time = 00:00:09, memory = 20090.49 (MB).
    Completing 80% with 110 violations.
    elapsed time = 00:00:10, memory = 20090.49 (MB).
    Completing 90% with 110 violations.
    elapsed time = 00:00:10, memory = 20090.49 (MB).
    Completing 100% with 102 violations.
    elapsed time = 00:00:16, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 102.
[INFO DRT-0267] cpu time = 00:00:37, elapsed time = 00:00:17, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782605 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943759 um.
Total wire length on LAYER met2 = 10020398 um.
Total wire length on LAYER met3 = 1767170 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240386.
Up-via summary (total 3240386):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780551
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240386


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 102 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 93 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 30% with 93 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 40% with 93 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 50% with 92 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 60% with 83 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 70% with 75 violations.
    elapsed time = 00:00:08, memory = 20090.49 (MB).
    Completing 80% with 75 violations.
    elapsed time = 00:00:08, memory = 20090.49 (MB).
    Completing 90% with 73 violations.
    elapsed time = 00:00:08, memory = 20090.49 (MB).
    Completing 100% with 66 violations.
    elapsed time = 00:00:11, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 66.
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:12, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782589 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943737 um.
Total wire length on LAYER met2 = 10020399 um.
Total wire length on LAYER met3 = 1767174 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240395.
Up-via summary (total 3240395):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780556
           met2      46833
           met3      12995
           met4         94
--------------------------
                   3240395


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 66 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 61 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 30% with 61 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 40% with 61 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 50% with 55 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 60% with 55 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 70% with 55 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 80% with 49 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 90% with 49 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 100% with 48 violations.
    elapsed time = 00:00:09, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 48.
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:09, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782584 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943721 um.
Total wire length on LAYER met2 = 10020397 um.
Total wire length on LAYER met3 = 1767186 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240395.
Up-via summary (total 3240395):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780552
           met2      46837
           met3      12995
           met4         94
--------------------------
                   3240395


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 48 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 44 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 30% with 44 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 40% with 44 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 50% with 44 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 60% with 44 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 70% with 44 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 80% with 44 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 90% with 44 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 100% with 44 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 44.
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:07, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782587 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943760 um.
Total wire length on LAYER met2 = 10020419 um.
Total wire length on LAYER met3 = 1767129 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240397.
Up-via summary (total 3240397):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780560
           met2      46831
           met3      12995
           met4         94
--------------------------
                   3240397


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 44 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 44 violations.
    elapsed time = 00:00:04, memory = 20090.49 (MB).
    Completing 30% with 44 violations.
    elapsed time = 00:00:04, memory = 20090.49 (MB).
    Completing 40% with 44 violations.
    elapsed time = 00:00:04, memory = 20090.49 (MB).
    Completing 50% with 44 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 60% with 44 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 70% with 44 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 80% with 44 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 90% with 44 violations.
    elapsed time = 00:00:07, memory = 20090.49 (MB).
    Completing 100% with 44 violations.
    elapsed time = 00:00:08, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 44.
[INFO DRT-0267] cpu time = 00:00:13, elapsed time = 00:00:08, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782587 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943760 um.
Total wire length on LAYER met2 = 10020419 um.
Total wire length on LAYER met3 = 1767129 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240397.
Up-via summary (total 3240397):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780560
           met2      46831
           met3      12995
           met4         94
--------------------------
                   3240397


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 44 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 44 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 44 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 40% with 44 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:04, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:04, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782575 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943769 um.
Total wire length on LAYER met2 = 10020412 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240393.
Up-via summary (total 3240393):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780558
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240393


[INFO DRT-0195] Start 11th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 12th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 70% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 13th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 70% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 14th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 70% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 15th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 50% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 70% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 80% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 16th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 39 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 60% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 70% with 39 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 80% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 90% with 39 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 100% with 39 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 39.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22782572 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943764 um.
Total wire length on LAYER met2 = 10020413 um.
Total wire length on LAYER met3 = 1767116 um.
Total wire length on LAYER met4 = 1040385 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240390.
Up-via summary (total 3240390):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780555
           met2      46829
           met3      12995
           met4         94
--------------------------
                   3240390


[INFO DRT-0195] Start 17th optimization iteration.
    Completing 10% with 33 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 28 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 30% with 28 violations.
    elapsed time = 00:00:01, memory = 20090.49 (MB).
    Completing 40% with 18 violations.
    elapsed time = 00:00:02, memory = 20090.49 (MB).
    Completing 50% with 19 violations.
    elapsed time = 00:00:03, memory = 20090.49 (MB).
    Completing 60% with 10 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 70% with 10 violations.
    elapsed time = 00:00:05, memory = 20090.49 (MB).
    Completing 80% with 9 violations.
    elapsed time = 00:00:06, memory = 20090.49 (MB).
    Completing 90% with 10 violations.
    elapsed time = 00:00:08, memory = 20090.49 (MB).
    Completing 100% with 9 violations.
    elapsed time = 00:00:09, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 9.
[INFO DRT-0267] cpu time = 00:00:22, elapsed time = 00:00:10, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781421 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941671 um.
Total wire length on LAYER met2 = 10020598 um.
Total wire length on LAYER met3 = 1768233 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240307.
Up-via summary (total 3240307):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46905
           met3      12971
           met4         94
--------------------------
                   3240307


[INFO DRT-0195] Start 18th optimization iteration.
    Completing 10% with 7 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 7 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 7 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 7 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 7 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 1 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 1 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 1 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0195] Start 25th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0195] Start 33rd optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0195] Start 41st optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0195] Start 49th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0195] Start 57th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20090.49 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20090.49 (MB), peak = 20111.15 (MB)
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0198] Complete detail routing.
Total wire length = 22781418 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9941665 um.
Total wire length on LAYER met2 = 10020595 um.
Total wire length on LAYER met3 = 1768240 um.
Total wire length on LAYER met4 = 1040024 um.
Total wire length on LAYER met5 = 10891 um.
Total number of vias = 3240309.
Up-via summary (total 3240309):.

--------------------------
 FR_MASTERSLICE          0
            li1    1399917
           met1    1780420
           met2      46907
           met3      12971
           met4         94
--------------------------
                   3240309


[INFO DRT-0267] cpu time = 05:31:06, elapsed time = 01:00:44, memory = 20090.49 (MB), peak = 20111.15 (MB)

[INFO DRT-0180] Post processing.
Elapsed time: 1:03:46[h:]min:sec. CPU time: user 20382.63 sys 12.77 (532%). Peak memory: 20593820KB.
