OpenROAD v2.0-1901-g6157d4945 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223]     Created 11 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225]     Created 437 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0094] 		Created 200000 Insts
[INFO ODB-0094] 		Created 300000 Insts
[INFO ODB-0094] 		Created 400000 Insts
[INFO ODB-0094] 		Created 500000 Insts
[INFO ODB-0094] 		Created 600000 Insts
[INFO ODB-0094] 		Created 700000 Insts
[INFO ODB-0094] 		Created 800000 Insts
[INFO ODB-0094] 		Created 900000 Insts
[INFO ODB-0094] 		Created 1000000 Insts
[INFO ODB-0094] 		Created 1100000 Insts
[INFO ODB-0094] 		Created 1200000 Insts
[INFO ODB-0094] 		Created 1300000 Insts
[INFO ODB-0094] 		Created 1400000 Insts
[INFO ODB-0094] 		Created 1500000 Insts
[INFO ODB-0094] 		Created 1600000 Insts
[INFO ODB-0094] 		Created 1700000 Insts
[INFO ODB-0094] 		Created 1800000 Insts
[INFO ODB-0094] 		Created 1900000 Insts
[INFO ODB-0094] 		Created 2000000 Insts
[INFO ODB-0094] 		Created 2100000 Insts
[INFO ODB-0094] 		Created 2200000 Insts
[INFO ODB-0094] 		Created 2300000 Insts
[INFO ODB-0094] 		Created 2400000 Insts
[INFO ODB-0094] 		Created 2500000 Insts
[INFO ODB-0094] 		Created 2600000 Insts
[INFO ODB-0097] 		Created 100000 Nets
[INFO ODB-0097] 		Created 200000 Nets
[INFO ODB-0097] 		Created 300000 Nets
[INFO ODB-0130]     Created 254 pins.
[INFO ODB-0131]     Created 2697656 components and 6814609 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 5395312 connections.
[INFO ODB-0133]     Created 378778 nets and 1413101 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   A2P_WB
Die area:                 ( 0 0 ) ( 5200000 4609140 )
Number of track patterns: 12
Number of DEF vias:       4
Number of components:     2697656
Number of terminals:      254
Number of snets:          2
Number of nets:           378778

[INFO DRT-0151] Reading guide.
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.
[INFO DRT-0156] guideIn read 500000 guides.
[INFO DRT-0156] guideIn read 600000 guides.
[INFO DRT-0156] guideIn read 700000 guides.
[INFO DRT-0156] guideIn read 800000 guides.
[INFO DRT-0156] guideIn read 900000 guides.
[INFO DRT-0157] guideIn read 1000000 guides.
[INFO DRT-0157] guideIn read 2000000 guides.
[INFO DRT-0157] guideIn read 3000000 guides.

Number of guides:     3440631

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR_MR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
  Complete 400000 instances.
  Complete 500000 instances.
  Complete 600000 instances.
  Complete 700000 instances.
  Complete 800000 instances.
  Complete 900000 instances.
  Complete 1000000 instances.
  Complete 1100000 instances.
  Complete 1200000 instances.
  Complete 1300000 instances.
  Complete 1400000 instances.
  Complete 1500000 instances.
  Complete 1600000 instances.
  Complete 1700000 instances.
  Complete 1800000 instances.
  Complete 1900000 instances.
  Complete 2000000 instances.
  Complete 2100000 instances.
  Complete 2200000 instances.
  Complete 2300000 instances.
  Complete 2400000 instances.
  Complete 2500000 instances.
  Complete 2600000 instances.
[INFO DRT-0164] Number of unique instances = 497.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0019]   Complete 400000 insts.
[INFO DRT-0019]   Complete 500000 insts.
[INFO DRT-0019]   Complete 600000 insts.
[INFO DRT-0019]   Complete 700000 insts.
[INFO DRT-0019]   Complete 800000 insts.
[INFO DRT-0019]   Complete 900000 insts.
[INFO DRT-0019]   Complete 1000000 insts.
[INFO DRT-0019]   Complete 1100000 insts.
[INFO DRT-0019]   Complete 1200000 insts.
[INFO DRT-0019]   Complete 1300000 insts.
[INFO DRT-0019]   Complete 1400000 insts.
[INFO DRT-0019]   Complete 1500000 insts.
[INFO DRT-0019]   Complete 1600000 insts.
[INFO DRT-0019]   Complete 1700000 insts.
[INFO DRT-0019]   Complete 1800000 insts.
[INFO DRT-0019]   Complete 1900000 insts.
[INFO DRT-0019]   Complete 2000000 insts.
[INFO DRT-0019]   Complete 2100000 insts.
[INFO DRT-0019]   Complete 2200000 insts.
[INFO DRT-0019]   Complete 2300000 insts.
[INFO DRT-0019]   Complete 2400000 insts.
[INFO DRT-0019]   Complete 2500000 insts.
[INFO DRT-0019]   Complete 2600000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete FR_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 21307421.
[INFO DRT-0033] mcon shape region query size = 830235.
[INFO DRT-0033] met1 shape region query size = 7752667.
[INFO DRT-0033] via shape region query size = 1351680.
[INFO DRT-0033] met2 shape region query size = 540893.
[INFO DRT-0033] via2 shape region query size = 1081344.
[INFO DRT-0033] met3 shape region query size = 540705.
[INFO DRT-0033] via3 shape region query size = 1081344.
[INFO DRT-0033] met4 shape region query size = 324544.
[INFO DRT-0033] via4 shape region query size = 53856.
[INFO DRT-0033] met5 shape region query size = 54162.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0077]   Complete 2000 pins.
[INFO DRT-0078]   Complete 2129 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0081]   Complete 487 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0083]   Complete 20000 groups.
[INFO DRT-0083]   Complete 30000 groups.
[INFO DRT-0083]   Complete 40000 groups.
[INFO DRT-0083]   Complete 50000 groups.
[INFO DRT-0083]   Complete 60000 groups.
[INFO DRT-0083]   Complete 70000 groups.
[INFO DRT-0083]   Complete 80000 groups.
[INFO DRT-0083]   Complete 90000 groups.
[INFO DRT-0083]   Complete 100000 groups.
[INFO DRT-0083]   Complete 110000 groups.
[INFO DRT-0083]   Complete 120000 groups.
[INFO DRT-0083]   Complete 130000 groups.
[INFO DRT-0083]   Complete 140000 groups.
[INFO DRT-0083]   Complete 150000 groups.
[INFO DRT-0083]   Complete 160000 groups.
[INFO DRT-0083]   Complete 170000 groups.
[INFO DRT-0083]   Complete 180000 groups.
[INFO DRT-0083]   Complete 190000 groups.
[INFO DRT-0083]   Complete 200000 groups.
[INFO DRT-0083]   Complete 210000 groups.
[INFO DRT-0083]   Complete 220000 groups.
[INFO DRT-0083]   Complete 230000 groups.
[INFO DRT-0083]   Complete 240000 groups.
[INFO DRT-0083]   Complete 250000 groups.
[INFO DRT-0083]   Complete 260000 groups.
[INFO DRT-0083]   Complete 270000 groups.
[INFO DRT-0083]   Complete 280000 groups.
[INFO DRT-0083]   Complete 290000 groups.
[INFO DRT-0083]   Complete 300000 groups.
[INFO DRT-0083]   Complete 310000 groups.
[INFO DRT-0083]   Complete 320000 groups.
[INFO DRT-0083]   Complete 330000 groups.
[INFO DRT-0083]   Complete 340000 groups.
[INFO DRT-0083]   Complete 350000 groups.
[INFO DRT-0083]   Complete 360000 groups.
[INFO DRT-0083]   Complete 370000 groups.
[INFO DRT-0083]   Complete 380000 groups.
[INFO DRT-0083]   Complete 390000 groups.
[INFO DRT-0083]   Complete 400000 groups.
[INFO DRT-0083]   Complete 410000 groups.
[INFO DRT-0083]   Complete 420000 groups.
[INFO DRT-0083]   Complete 430000 groups.
[INFO DRT-0083]   Complete 440000 groups.
[INFO DRT-0084]   Complete 449622 groups.
#scanned instances     = 2697656
#unique  instances     = 497
#stdCellGenAp          = 17629
#stdCellValidPlanarAp  = 358
#stdCellValidViaAp     = 12670
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 1413101
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:15, elapsed time = 00:00:04, memory = 6446.40 (MB), peak = 6864.96 (MB)
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 667 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 753 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0026]   Complete 50000 origin guides.
[INFO DRT-0026]   Complete 60000 origin guides.
[INFO DRT-0026]   Complete 70000 origin guides.
[INFO DRT-0026]   Complete 80000 origin guides.
[INFO DRT-0026]   Complete 90000 origin guides.
[INFO DRT-0027]   Complete 100000 origin guides.
[INFO DRT-0027]   Complete 200000 origin guides.
[INFO DRT-0027]   Complete 300000 origin guides.
[INFO DRT-0027]   Complete 400000 origin guides.
[INFO DRT-0027]   Complete 500000 origin guides.
[INFO DRT-0027]   Complete 600000 origin guides.
[INFO DRT-0027]   Complete 700000 origin guides.
[INFO DRT-0027]   Complete 800000 origin guides.
[INFO DRT-0027]   Complete 900000 origin guides.
[INFO DRT-0027]   Complete 1000000 origin guides.
[INFO DRT-0027]   Complete 1100000 origin guides.
[INFO DRT-0027]   Complete 1200000 origin guides.
[INFO DRT-0027]   Complete 1300000 origin guides.
[INFO DRT-0027]   Complete 1400000 origin guides.
[INFO DRT-0027]   Complete 1500000 origin guides.
[INFO DRT-0027]   Complete 1600000 origin guides.
[INFO DRT-0027]   Complete 1700000 origin guides.
[INFO DRT-0027]   Complete 1800000 origin guides.
[INFO DRT-0027]   Complete 1900000 origin guides.
[INFO DRT-0027]   Complete 2000000 origin guides.
[INFO DRT-0027]   Complete 2100000 origin guides.
[INFO DRT-0027]   Complete 2200000 origin guides.
[INFO DRT-0027]   Complete 2300000 origin guides.
[INFO DRT-0027]   Complete 2400000 origin guides.
[INFO DRT-0027]   Complete 2500000 origin guides.
[INFO DRT-0027]   Complete 2600000 origin guides.
[INFO DRT-0027]   Complete 2700000 origin guides.
[INFO DRT-0027]   Complete 2800000 origin guides.
[INFO DRT-0027]   Complete 2900000 origin guides.
[INFO DRT-0027]   Complete 3000000 origin guides.
[INFO DRT-0027]   Complete 3100000 origin guides.
[INFO DRT-0027]   Complete 3200000 origin guides.
[INFO DRT-0027]   Complete 3300000 origin guides.
[INFO DRT-0027]   Complete 3400000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete FR_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
  complete 10000 nets.
  complete 20000 nets.
  complete 30000 nets.
  complete 40000 nets.
  complete 50000 nets.
  complete 60000 nets.
  complete 70000 nets.
  complete 80000 nets.
  complete 90000 nets.
  complete 100000 nets.
  complete 200000 nets.
  complete 300000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029]   Complete 10000 nets (guide).
[INFO DRT-0029]   Complete 20000 nets (guide).
[INFO DRT-0029]   Complete 30000 nets (guide).
[INFO DRT-0029]   Complete 40000 nets (guide).
[INFO DRT-0029]   Complete 50000 nets (guide).
[INFO DRT-0029]   Complete 60000 nets (guide).
[INFO DRT-0029]   Complete 70000 nets (guide).
[INFO DRT-0029]   Complete 80000 nets (guide).
[INFO DRT-0029]   Complete 90000 nets (guide).
[INFO DRT-0030]   Complete 100000 nets (guide).
[INFO DRT-0030]   Complete 200000 nets (guide).
[INFO DRT-0030]   Complete 300000 nets (guide).
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete FR_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 1203828.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 1051753.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 648703.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 25418.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 7282.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 68.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 1859813 vertical wires in 16 frboxes and 1077239 horizontal wires in 14 frboxes.
[INFO DRT-0186] Done with 287141 vertical wires in 16 frboxes and 281261 horizontal wires in 14 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:07:23, elapsed time = 00:01:48, memory = 11515.08 (MB), peak = 11812.35 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 11515.08 (MB), peak = 11812.35 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 12056 violations.
    elapsed time = 00:02:01, memory = 16922.07 (MB).
    Completing 20% with 29718 violations.
    elapsed time = 00:04:20, memory = 18097.44 (MB).
    Completing 30% with 35991 violations.
    elapsed time = 00:05:48, memory = 18097.44 (MB).
    Completing 40% with 47972 violations.
    elapsed time = 00:08:33, memory = 18097.44 (MB).
    Completing 50% with 63932 violations.
    elapsed time = 00:10:23, memory = 18676.64 (MB).
    Completing 60% with 81724 violations.
    elapsed time = 00:13:45, memory = 18787.11 (MB).
    Completing 70% with 97159 violations.
    elapsed time = 00:16:49, memory = 19383.55 (MB).
    Completing 80% with 101739 violations.
    elapsed time = 00:18:51, memory = 19414.29 (MB).
    Completing 90% with 112166 violations.
    elapsed time = 00:23:04, memory = 19682.77 (MB).
    Completing 100% with 130658 violations.
    elapsed time = 00:25:16, memory = 20007.86 (MB).
[INFO DRT-0199]   Number of violations = 395266.
[INFO DRT-0267] cpu time = 02:27:14, elapsed time = 00:25:30, memory = 20007.86 (MB), peak = 20016.42 (MB)
Total wire length = 23120253 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10123179 um.
Total wire length on LAYER met2 = 10175971 um.
Total wire length on LAYER met3 = 1747722 um.
Total wire length on LAYER met4 = 1058431 um.
Total wire length on LAYER met5 = 14947 um.
Total number of vias = 3268015.
Up-via summary (total 3268015):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400708
           met1    1811971
           met2      41970
           met3      13239
           met4        127
--------------------------
                   3268015


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 360020 violations.
    elapsed time = 00:01:20, memory = 20007.86 (MB).
    Completing 20% with 318084 violations.
    elapsed time = 00:03:03, memory = 20047.90 (MB).
    Completing 30% with 301988 violations.
    elapsed time = 00:04:04, memory = 20047.90 (MB).
    Completing 40% with 269880 violations.
    elapsed time = 00:05:54, memory = 20047.90 (MB).
    Completing 50% with 229873 violations.
    elapsed time = 00:07:18, memory = 20082.04 (MB).
    Completing 60% with 177134 violations.
    elapsed time = 00:08:49, memory = 20082.04 (MB).
    Completing 70% with 134497 violations.
    elapsed time = 00:10:38, memory = 20082.04 (MB).
    Completing 80% with 119145 violations.
    elapsed time = 00:11:40, memory = 20082.04 (MB).
    Completing 90% with 82565 violations.
    elapsed time = 00:13:39, memory = 20052.35 (MB).
    Completing 100% with 28615 violations.
    elapsed time = 00:15:08, memory = 20052.35 (MB).
[INFO DRT-0199]   Number of violations = 28657.
[INFO DRT-0267] cpu time = 01:25:26, elapsed time = 00:15:24, memory = 20052.35 (MB), peak = 20082.04 (MB)
Total wire length = 22900234 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10026872 um.
Total wire length on LAYER met2 = 10061815 um.
Total wire length on LAYER met3 = 1742066 um.
Total wire length on LAYER met4 = 1054599 um.
Total wire length on LAYER met5 = 14878 um.
Total number of vias = 3247012.
Up-via summary (total 3247012):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400303
           met1    1791189
           met2      42348
           met3      13055
           met4        117
--------------------------
                   3247012


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 28216 violations.
    elapsed time = 00:01:01, memory = 20052.35 (MB).
    Completing 20% with 27420 violations.
    elapsed time = 00:02:37, memory = 20052.35 (MB).
    Completing 30% with 27136 violations.
    elapsed time = 00:03:22, memory = 20052.35 (MB).
    Completing 40% with 26474 violations.
    elapsed time = 00:04:56, memory = 20052.35 (MB).
    Completing 50% with 25558 violations.
    elapsed time = 00:06:13, memory = 20052.35 (MB).
    Completing 60% with 25230 violations.
    elapsed time = 00:07:12, memory = 20052.35 (MB).
    Completing 70% with 24328 violations.
    elapsed time = 00:08:40, memory = 20052.35 (MB).
    Completing 80% with 22799 violations.
    elapsed time = 00:09:35, memory = 20052.35 (MB).
    Completing 90% with 21817 violations.
    elapsed time = 00:11:02, memory = 20052.35 (MB).
    Completing 100% with 19958 violations.
    elapsed time = 00:12:16, memory = 20052.35 (MB).
[INFO DRT-0199]   Number of violations = 19995.
[INFO DRT-0267] cpu time = 01:08:48, elapsed time = 00:12:32, memory = 20052.35 (MB), peak = 20082.04 (MB)
Total wire length = 22820996 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9993518 um.
Total wire length on LAYER met2 = 10017876 um.
Total wire length on LAYER met3 = 1739763 um.
Total wire length on LAYER met4 = 1054945 um.
Total wire length on LAYER met5 = 14891 um.
Total number of vias = 3233193.
Up-via summary (total 3233193):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400299
           met1    1778194
           met2      41594
           met3      12991
           met4        115
--------------------------
                   3233193


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 18961 violations.
    elapsed time = 00:00:16, memory = 20052.35 (MB).
    Completing 20% with 16249 violations.
    elapsed time = 00:00:50, memory = 20052.35 (MB).
    Completing 30% with 15511 violations.
    elapsed time = 00:01:08, memory = 20052.35 (MB).
    Completing 40% with 14378 violations.
    elapsed time = 00:01:37, memory = 20052.35 (MB).
    Completing 50% with 11536 violations.
    elapsed time = 00:02:05, memory = 20052.35 (MB).
    Completing 60% with 9367 violations.
    elapsed time = 00:02:30, memory = 20052.35 (MB).
    Completing 70% with 6568 violations.
    elapsed time = 00:03:11, memory = 20052.58 (MB).
    Completing 80% with 5789 violations.
    elapsed time = 00:03:27, memory = 20052.58 (MB).
    Completing 90% with 4424 violations.
    elapsed time = 00:04:01, memory = 20052.58 (MB).
    Completing 100% with 845 violations.
    elapsed time = 00:04:35, memory = 20052.58 (MB).
[INFO DRT-0199]   Number of violations = 866.
[INFO DRT-0267] cpu time = 00:23:40, elapsed time = 00:04:39, memory = 20052.58 (MB), peak = 20082.04 (MB)
Total wire length = 22813835 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9945983 um.
Total wire length on LAYER met2 = 10018487 um.
Total wire length on LAYER met3 = 1778574 um.
Total wire length on LAYER met4 = 1055915 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242546.
Up-via summary (total 3242546):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782126
           met2      46901
           met3      13098
           met4        115
--------------------------
                   3242546


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 850 violations.
    elapsed time = 00:00:01, memory = 20052.58 (MB).
    Completing 20% with 717 violations.
    elapsed time = 00:00:08, memory = 20052.58 (MB).
    Completing 30% with 696 violations.
    elapsed time = 00:00:09, memory = 20052.58 (MB).
    Completing 40% with 675 violations.
    elapsed time = 00:00:12, memory = 20052.58 (MB).
    Completing 50% with 547 violations.
    elapsed time = 00:00:16, memory = 20052.58 (MB).
    Completing 60% with 474 violations.
    elapsed time = 00:00:20, memory = 20052.58 (MB).
    Completing 70% with 378 violations.
    elapsed time = 00:00:23, memory = 20052.58 (MB).
    Completing 80% with 336 violations.
    elapsed time = 00:00:24, memory = 20052.58 (MB).
    Completing 90% with 300 violations.
    elapsed time = 00:00:26, memory = 20052.58 (MB).
    Completing 100% with 127 violations.
    elapsed time = 00:00:34, memory = 20052.58 (MB).
[INFO DRT-0199]   Number of violations = 127.
[INFO DRT-0267] cpu time = 00:01:53, elapsed time = 00:00:34, memory = 20052.58 (MB), peak = 20082.04 (MB)
Total wire length = 22813611 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944883 um.
Total wire length on LAYER met2 = 10018408 um.
Total wire length on LAYER met3 = 1779577 um.
Total wire length on LAYER met4 = 1055867 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242707.
Up-via summary (total 3242707):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782180
           met2      47014
           met3      13092
           met4        115
--------------------------
                   3242707


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 124 violations.
    elapsed time = 00:00:00, memory = 20052.58 (MB).
    Completing 20% with 113 violations.
    elapsed time = 00:00:04, memory = 20052.58 (MB).
    Completing 30% with 110 violations.
    elapsed time = 00:00:04, memory = 20052.58 (MB).
    Completing 40% with 110 violations.
    elapsed time = 00:00:05, memory = 20052.58 (MB).
    Completing 50% with 109 violations.
    elapsed time = 00:00:09, memory = 20052.58 (MB).
    Completing 60% with 104 violations.
    elapsed time = 00:00:10, memory = 20052.58 (MB).
    Completing 70% with 87 violations.
    elapsed time = 00:00:14, memory = 20052.58 (MB).
    Completing 80% with 87 violations.
    elapsed time = 00:00:20, memory = 20052.58 (MB).
    Completing 90% with 87 violations.
    elapsed time = 00:00:20, memory = 20052.58 (MB).
    Completing 100% with 71 violations.
    elapsed time = 00:00:23, memory = 20052.58 (MB).
[INFO DRT-0199]   Number of violations = 71.
[INFO DRT-0267] cpu time = 00:00:39, elapsed time = 00:00:23, memory = 20052.58 (MB), peak = 20082.04 (MB)
Total wire length = 22813600 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944867 um.
Total wire length on LAYER met2 = 10018347 um.
Total wire length on LAYER met3 = 1779643 um.
Total wire length on LAYER met4 = 1055867 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242692.
Up-via summary (total 3242692):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782159
           met2      47020
           met3      13092
           met4        115
--------------------------
                   3242692


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 71 violations.
    elapsed time = 00:00:00, memory = 20052.58 (MB).
    Completing 20% with 65 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 30% with 64 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 40% with 64 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 50% with 61 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 60% with 61 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 70% with 61 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 80% with 60 violations.
    elapsed time = 00:00:06, memory = 20055.93 (MB).
    Completing 90% with 60 violations.
    elapsed time = 00:00:06, memory = 20055.93 (MB).
    Completing 100% with 58 violations.
    elapsed time = 00:00:09, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 58.
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:09, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813611 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944827 um.
Total wire length on LAYER met2 = 10018355 um.
Total wire length on LAYER met3 = 1779686 um.
Total wire length on LAYER met4 = 1055867 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242706.
Up-via summary (total 3242706):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782170
           met2      47023
           met3      13092
           met4        115
--------------------------
                   3242706


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 58 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 58 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 30% with 58 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 40% with 58 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 50% with 58 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 60% with 58 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 70% with 58 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 80% with 58 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 90% with 54 violations.
    elapsed time = 00:00:05, memory = 20055.93 (MB).
    Completing 100% with 51 violations.
    elapsed time = 00:00:08, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 51.
[INFO DRT-0267] cpu time = 00:00:13, elapsed time = 00:00:08, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813620 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944831 um.
Total wire length on LAYER met2 = 10018381 um.
Total wire length on LAYER met3 = 1779688 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242712.
Up-via summary (total 3242712):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47025
           met3      13090
           met4        115
--------------------------
                   3242712


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 51 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 51 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 30% with 51 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 40% with 51 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 50% with 51 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 60% with 51 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 70% with 51 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 80% with 51 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 90% with 51 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 100% with 51 violations.
    elapsed time = 00:00:06, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 51.
[INFO DRT-0267] cpu time = 00:00:14, elapsed time = 00:00:06, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813620 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944831 um.
Total wire length on LAYER met2 = 10018381 um.
Total wire length on LAYER met3 = 1779688 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242712.
Up-via summary (total 3242712):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47025
           met3      13090
           met4        115
--------------------------
                   3242712


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 51 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 51 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 30% with 51 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 40% with 51 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 48 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 60% with 48 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 100% with 45 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 45.
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:04, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813611 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944850 um.
Total wire length on LAYER met2 = 10018382 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242713.
Up-via summary (total 3242713):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782178
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242713


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 45 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 30% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 40% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 60% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 70% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 80% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 44 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 100% with 44 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 44.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:04, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813607 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944846 um.
Total wire length on LAYER met2 = 10018382 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 11th optimization iteration.
    Completing 10% with 44 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 44 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 44 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 44 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 70% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 80% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 44 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 12th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:03, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 13th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:03, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 14th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:03, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 15th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:03, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 16th optimization iteration.
    Completing 10% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 43 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 60% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 70% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 80% with 43 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 90% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 100% with 43 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 43.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22813608 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9944845 um.
Total wire length on LAYER met2 = 10018383 um.
Total wire length on LAYER met3 = 1779659 um.
Total wire length on LAYER met4 = 1055844 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242711.
Up-via summary (total 3242711):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782176
           met2      47024
           met3      13090
           met4        115
--------------------------
                   3242711


[INFO DRT-0195] Start 17th optimization iteration.
    Completing 10% with 39 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 37 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 30% with 37 violations.
    elapsed time = 00:00:01, memory = 20055.93 (MB).
    Completing 40% with 26 violations.
    elapsed time = 00:00:02, memory = 20055.93 (MB).
    Completing 50% with 25 violations.
    elapsed time = 00:00:03, memory = 20055.93 (MB).
    Completing 60% with 14 violations.
    elapsed time = 00:00:04, memory = 20055.93 (MB).
    Completing 70% with 13 violations.
    elapsed time = 00:00:06, memory = 20055.93 (MB).
    Completing 80% with 12 violations.
    elapsed time = 00:00:06, memory = 20055.93 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:07, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:08, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:17, elapsed time = 00:00:09, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0195] Start 25th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0195] Start 33rd optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0195] Start 41st optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0195] Start 49th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0195] Start 57th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20055.93 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20055.93 (MB), peak = 20082.04 (MB)
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0198] Complete detail routing.
Total wire length = 22812699 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9943503 um.
Total wire length on LAYER met2 = 10018504 um.
Total wire length on LAYER met3 = 1780312 um.
Total wire length on LAYER met4 = 1055503 um.
Total wire length on LAYER met5 = 14875 um.
Total number of vias = 3242608.
Up-via summary (total 3242608):.

--------------------------
 FR_MASTERSLICE          0
            li1    1400306
           met1    1782027
           met2      47083
           met3      13077
           met4        115
--------------------------
                   3242608


[INFO DRT-0267] cpu time = 05:30:15, elapsed time = 01:00:35, memory = 20055.93 (MB), peak = 20082.04 (MB)

[INFO DRT-0180] Post processing.
Elapsed time: 1:03:36[h:]min:sec. CPU time: user 20330.95 sys 12.30 (533%). Peak memory: 20564004KB.
