OpenROAD v2.0-1901-g6157d4945 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223]     Created 11 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225]     Created 437 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/4_cts.def
[INFO ODB-0128] Design: top
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0094] 		Created 200000 Insts
[INFO ODB-0094] 		Created 300000 Insts
[INFO ODB-0094] 		Created 400000 Insts
[INFO ODB-0094] 		Created 500000 Insts
[INFO ODB-0094] 		Created 600000 Insts
[INFO ODB-0094] 		Created 700000 Insts
[INFO ODB-0094] 		Created 800000 Insts
[INFO ODB-0094] 		Created 900000 Insts
[INFO ODB-0094] 		Created 1000000 Insts
[INFO ODB-0094] 		Created 1100000 Insts
[INFO ODB-0094] 		Created 1200000 Insts
[INFO ODB-0094] 		Created 1300000 Insts
[INFO ODB-0094] 		Created 1400000 Insts
[INFO ODB-0094] 		Created 1500000 Insts
[INFO ODB-0094] 		Created 1600000 Insts
[INFO ODB-0094] 		Created 1700000 Insts
[INFO ODB-0094] 		Created 1800000 Insts
[INFO ODB-0094] 		Created 1900000 Insts
[INFO ODB-0094] 		Created 2000000 Insts
[INFO ODB-0094] 		Created 2100000 Insts
[INFO ODB-0094] 		Created 2200000 Insts
[INFO ODB-0094] 		Created 2300000 Insts
[INFO ODB-0094] 		Created 2400000 Insts
[INFO ODB-0094] 		Created 2500000 Insts
[INFO ODB-0094] 		Created 2600000 Insts
[INFO ODB-0094] 		Created 2700000 Insts
[INFO ODB-0097] 		Created 100000 Nets
[INFO ODB-0097] 		Created 200000 Nets
[INFO ODB-0097] 		Created 300000 Nets
[INFO ODB-0130]     Created 533 pins.
[INFO ODB-0131]     Created 2716855 components and 6901098 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 5433710 connections.
[INFO ODB-0133]     Created 395413 nets and 1465023 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p_litex/output/20211125124450/base/4_cts.def
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   top
Die area:                 ( 0 0 ) ( 5200000 4609140 )
Number of track patterns: 12
Number of DEF vias:       4
Number of components:     2716855
Number of terminals:      533
Number of snets:          2
Number of nets:           395413

[INFO DRT-0151] Reading guide.
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.
[INFO DRT-0156] guideIn read 500000 guides.
[INFO DRT-0156] guideIn read 600000 guides.
[INFO DRT-0156] guideIn read 700000 guides.
[INFO DRT-0156] guideIn read 800000 guides.
[INFO DRT-0156] guideIn read 900000 guides.
[INFO DRT-0157] guideIn read 1000000 guides.
[INFO DRT-0157] guideIn read 2000000 guides.
[INFO DRT-0157] guideIn read 3000000 guides.

Number of guides:     3573169

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR_MR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR_MR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
  Complete 400000 instances.
  Complete 500000 instances.
  Complete 600000 instances.
  Complete 700000 instances.
  Complete 800000 instances.
  Complete 900000 instances.
  Complete 1000000 instances.
  Complete 1100000 instances.
  Complete 1200000 instances.
  Complete 1300000 instances.
  Complete 1400000 instances.
  Complete 1500000 instances.
  Complete 1600000 instances.
  Complete 1700000 instances.
  Complete 1800000 instances.
  Complete 1900000 instances.
  Complete 2000000 instances.
  Complete 2100000 instances.
  Complete 2200000 instances.
  Complete 2300000 instances.
  Complete 2400000 instances.
  Complete 2500000 instances.
  Complete 2600000 instances.
  Complete 2700000 instances.
[INFO DRT-0164] Number of unique instances = 511.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0019]   Complete 400000 insts.
[INFO DRT-0019]   Complete 500000 insts.
[INFO DRT-0019]   Complete 600000 insts.
[INFO DRT-0019]   Complete 700000 insts.
[INFO DRT-0019]   Complete 800000 insts.
[INFO DRT-0019]   Complete 900000 insts.
[INFO DRT-0019]   Complete 1000000 insts.
[INFO DRT-0019]   Complete 1100000 insts.
[INFO DRT-0019]   Complete 1200000 insts.
[INFO DRT-0019]   Complete 1300000 insts.
[INFO DRT-0019]   Complete 1400000 insts.
[INFO DRT-0019]   Complete 1500000 insts.
[INFO DRT-0019]   Complete 1600000 insts.
[INFO DRT-0019]   Complete 1700000 insts.
[INFO DRT-0019]   Complete 1800000 insts.
[INFO DRT-0019]   Complete 1900000 insts.
[INFO DRT-0019]   Complete 2000000 insts.
[INFO DRT-0019]   Complete 2100000 insts.
[INFO DRT-0019]   Complete 2200000 insts.
[INFO DRT-0019]   Complete 2300000 insts.
[INFO DRT-0019]   Complete 2400000 insts.
[INFO DRT-0019]   Complete 2500000 insts.
[INFO DRT-0019]   Complete 2600000 insts.
[INFO DRT-0019]   Complete 2700000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete FR_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 21474468.
[INFO DRT-0033] mcon shape region query size = 829672.
[INFO DRT-0033] met1 shape region query size = 7791013.
[INFO DRT-0033] via shape region query size = 1351680.
[INFO DRT-0033] met2 shape region query size = 541199.
[INFO DRT-0033] via2 shape region query size = 1081344.
[INFO DRT-0033] met3 shape region query size = 540678.
[INFO DRT-0033] via3 shape region query size = 1081344.
[INFO DRT-0033] met4 shape region query size = 324544.
[INFO DRT-0033] via4 shape region query size = 53856.
[INFO DRT-0033] met5 shape region query size = 54162.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0077]   Complete 2000 pins.
[INFO DRT-0078]   Complete 2206 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0079]   Complete 500 unique inst patterns.
[INFO DRT-0081]   Complete 501 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0083]   Complete 20000 groups.
[INFO DRT-0083]   Complete 30000 groups.
[INFO DRT-0083]   Complete 40000 groups.
[INFO DRT-0083]   Complete 50000 groups.
[INFO DRT-0083]   Complete 60000 groups.
[INFO DRT-0083]   Complete 70000 groups.
[INFO DRT-0083]   Complete 80000 groups.
[INFO DRT-0083]   Complete 90000 groups.
[INFO DRT-0083]   Complete 100000 groups.
[INFO DRT-0083]   Complete 110000 groups.
[INFO DRT-0083]   Complete 120000 groups.
[INFO DRT-0083]   Complete 130000 groups.
[INFO DRT-0083]   Complete 140000 groups.
[INFO DRT-0083]   Complete 150000 groups.
[INFO DRT-0083]   Complete 160000 groups.
[INFO DRT-0083]   Complete 170000 groups.
[INFO DRT-0083]   Complete 180000 groups.
[INFO DRT-0083]   Complete 190000 groups.
[INFO DRT-0083]   Complete 200000 groups.
[INFO DRT-0083]   Complete 210000 groups.
[INFO DRT-0083]   Complete 220000 groups.
[INFO DRT-0083]   Complete 230000 groups.
[INFO DRT-0083]   Complete 240000 groups.
[INFO DRT-0083]   Complete 250000 groups.
[INFO DRT-0083]   Complete 260000 groups.
[INFO DRT-0083]   Complete 270000 groups.
[INFO DRT-0083]   Complete 280000 groups.
[INFO DRT-0083]   Complete 290000 groups.
[INFO DRT-0083]   Complete 300000 groups.
[INFO DRT-0083]   Complete 310000 groups.
[INFO DRT-0083]   Complete 320000 groups.
[INFO DRT-0083]   Complete 330000 groups.
[INFO DRT-0083]   Complete 340000 groups.
[INFO DRT-0083]   Complete 350000 groups.
[INFO DRT-0083]   Complete 360000 groups.
[INFO DRT-0083]   Complete 370000 groups.
[INFO DRT-0083]   Complete 380000 groups.
[INFO DRT-0083]   Complete 390000 groups.
[INFO DRT-0083]   Complete 400000 groups.
[INFO DRT-0083]   Complete 410000 groups.
[INFO DRT-0083]   Complete 420000 groups.
[INFO DRT-0083]   Complete 430000 groups.
[INFO DRT-0083]   Complete 440000 groups.
[INFO DRT-0083]   Complete 450000 groups.
[INFO DRT-0083]   Complete 460000 groups.
[INFO DRT-0084]   Complete 465607 groups.
#scanned instances     = 2716855
#unique  instances     = 511
#stdCellGenAp          = 18030
#stdCellValidPlanarAp  = 340
#stdCellValidViaAp     = 13042
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 1465023
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:04, memory = 6521.41 (MB), peak = 6948.29 (MB)
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 667 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 753 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0026]   Complete 50000 origin guides.
[INFO DRT-0026]   Complete 60000 origin guides.
[INFO DRT-0026]   Complete 70000 origin guides.
[INFO DRT-0026]   Complete 80000 origin guides.
[INFO DRT-0026]   Complete 90000 origin guides.
[INFO DRT-0027]   Complete 100000 origin guides.
[INFO DRT-0027]   Complete 200000 origin guides.
[INFO DRT-0027]   Complete 300000 origin guides.
[INFO DRT-0027]   Complete 400000 origin guides.
[INFO DRT-0027]   Complete 500000 origin guides.
[INFO DRT-0027]   Complete 600000 origin guides.
[INFO DRT-0027]   Complete 700000 origin guides.
[INFO DRT-0027]   Complete 800000 origin guides.
[INFO DRT-0027]   Complete 900000 origin guides.
[INFO DRT-0027]   Complete 1000000 origin guides.
[INFO DRT-0027]   Complete 1100000 origin guides.
[INFO DRT-0027]   Complete 1200000 origin guides.
[INFO DRT-0027]   Complete 1300000 origin guides.
[INFO DRT-0027]   Complete 1400000 origin guides.
[INFO DRT-0027]   Complete 1500000 origin guides.
[INFO DRT-0027]   Complete 1600000 origin guides.
[INFO DRT-0027]   Complete 1700000 origin guides.
[INFO DRT-0027]   Complete 1800000 origin guides.
[INFO DRT-0027]   Complete 1900000 origin guides.
[INFO DRT-0027]   Complete 2000000 origin guides.
[INFO DRT-0027]   Complete 2100000 origin guides.
[INFO DRT-0027]   Complete 2200000 origin guides.
[INFO DRT-0027]   Complete 2300000 origin guides.
[INFO DRT-0027]   Complete 2400000 origin guides.
[INFO DRT-0027]   Complete 2500000 origin guides.
[INFO DRT-0027]   Complete 2600000 origin guides.
[INFO DRT-0027]   Complete 2700000 origin guides.
[INFO DRT-0027]   Complete 2800000 origin guides.
[INFO DRT-0027]   Complete 2900000 origin guides.
[INFO DRT-0027]   Complete 3000000 origin guides.
[INFO DRT-0027]   Complete 3100000 origin guides.
[INFO DRT-0027]   Complete 3200000 origin guides.
[INFO DRT-0027]   Complete 3300000 origin guides.
[INFO DRT-0027]   Complete 3400000 origin guides.
[INFO DRT-0027]   Complete 3500000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete FR_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
  complete 10000 nets.
  complete 20000 nets.
  complete 30000 nets.
  complete 40000 nets.
  complete 50000 nets.
  complete 60000 nets.
  complete 70000 nets.
  complete 80000 nets.
  complete 90000 nets.
  complete 100000 nets.
  complete 200000 nets.
  complete 300000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029]   Complete 10000 nets (guide).
[INFO DRT-0029]   Complete 20000 nets (guide).
[INFO DRT-0029]   Complete 30000 nets (guide).
[INFO DRT-0029]   Complete 40000 nets (guide).
[INFO DRT-0029]   Complete 50000 nets (guide).
[INFO DRT-0029]   Complete 60000 nets (guide).
[INFO DRT-0029]   Complete 70000 nets (guide).
[INFO DRT-0029]   Complete 80000 nets (guide).
[INFO DRT-0029]   Complete 90000 nets (guide).
[INFO DRT-0030]   Complete 100000 nets (guide).
[INFO DRT-0030]   Complete 200000 nets (guide).
[INFO DRT-0030]   Complete 300000 nets (guide).
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete FR_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 1246198.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 1089813.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 675513.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 30957.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 9007.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 66.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 1930718 vertical wires in 16 frboxes and 1120836 horizontal wires in 14 frboxes.
[INFO DRT-0186] Done with 295988 vertical wires in 16 frboxes and 294282 horizontal wires in 14 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:07:48, elapsed time = 00:01:52, memory = 11741.54 (MB), peak = 12192.17 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:02, elapsed time = 00:00:02, memory = 11741.54 (MB), peak = 12192.17 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 13509 violations.
    elapsed time = 00:02:19, memory = 17546.17 (MB).
    Completing 20% with 32417 violations.
    elapsed time = 00:04:53, memory = 18179.23 (MB).
    Completing 30% with 38648 violations.
    elapsed time = 00:06:27, memory = 18179.27 (MB).
    Completing 40% with 51223 violations.
    elapsed time = 00:09:12, memory = 18333.97 (MB).
    Completing 50% with 69170 violations.
    elapsed time = 00:11:30, memory = 18794.88 (MB).
    Completing 60% with 87500 violations.
    elapsed time = 00:15:03, memory = 19029.57 (MB).
    Completing 70% with 103311 violations.
    elapsed time = 00:18:16, memory = 19559.66 (MB).
    Completing 80% with 108066 violations.
    elapsed time = 00:20:29, memory = 19567.26 (MB).
    Completing 90% with 119845 violations.
    elapsed time = 00:24:22, memory = 19724.07 (MB).
    Completing 100% with 138863 violations.
    elapsed time = 00:27:08, memory = 20131.93 (MB).
[INFO DRT-0199]   Number of violations = 407920.
[INFO DRT-0267] cpu time = 02:38:14, elapsed time = 00:27:25, memory = 20131.93 (MB), peak = 20131.93 (MB)
Total wire length = 24902106 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10753666 um.
Total wire length on LAYER met2 = 10613545 um.
Total wire length on LAYER met3 = 2325994 um.
Total wire length on LAYER met4 = 1196056 um.
Total wire length on LAYER met5 = 12843 um.
Total number of vias = 3406267.
Up-via summary (total 3406267):.

--------------------------
 FR_MASTERSLICE          0
            li1    1452255
           met1    1887014
           met2      50330
           met3      16569
           met4         99
--------------------------
                   3406267


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 371295 violations.
    elapsed time = 00:01:27, memory = 20131.93 (MB).
    Completing 20% with 326496 violations.
    elapsed time = 00:03:22, memory = 20131.93 (MB).
    Completing 30% with 311440 violations.
    elapsed time = 00:04:31, memory = 20132.96 (MB).
    Completing 40% with 277029 violations.
    elapsed time = 00:06:21, memory = 20132.96 (MB).
    Completing 50% with 235523 violations.
    elapsed time = 00:08:04, memory = 20134.77 (MB).
    Completing 60% with 182119 violations.
    elapsed time = 00:09:44, memory = 20134.77 (MB).
    Completing 70% with 137052 violations.
    elapsed time = 00:11:45, memory = 20166.99 (MB).
    Completing 80% with 123445 violations.
    elapsed time = 00:12:53, memory = 20150.95 (MB).
    Completing 90% with 87587 violations.
    elapsed time = 00:14:47, memory = 20150.95 (MB).
    Completing 100% with 32387 violations.
    elapsed time = 00:16:33, memory = 20142.98 (MB).
[INFO DRT-0199]   Number of violations = 32504.
[INFO DRT-0267] cpu time = 01:33:47, elapsed time = 00:16:51, memory = 20142.98 (MB), peak = 20196.81 (MB)
Total wire length = 24675981 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10653452 um.
Total wire length on LAYER met2 = 10497891 um.
Total wire length on LAYER met3 = 2319459 um.
Total wire length on LAYER met4 = 1192365 um.
Total wire length on LAYER met5 = 12812 um.
Total number of vias = 3383181.
Up-via summary (total 3383181):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451939
           met1    1864074
           met2      50795
           met3      16278
           met4         95
--------------------------
                   3383181


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 32008 violations.
    elapsed time = 00:01:09, memory = 20147.62 (MB).
    Completing 20% with 31138 violations.
    elapsed time = 00:02:54, memory = 20150.20 (MB).
    Completing 30% with 30793 violations.
    elapsed time = 00:03:47, memory = 20150.97 (MB).
    Completing 40% with 30105 violations.
    elapsed time = 00:05:16, memory = 20150.97 (MB).
    Completing 50% with 29256 violations.
    elapsed time = 00:06:48, memory = 20151.23 (MB).
    Completing 60% with 28944 violations.
    elapsed time = 00:07:52, memory = 20151.23 (MB).
    Completing 70% with 27861 violations.
    elapsed time = 00:09:35, memory = 20151.48 (MB).
    Completing 80% with 26421 violations.
    elapsed time = 00:10:36, memory = 20151.48 (MB).
    Completing 90% with 25459 violations.
    elapsed time = 00:12:07, memory = 20151.48 (MB).
    Completing 100% with 23798 violations.
    elapsed time = 00:13:39, memory = 20151.48 (MB).
[INFO DRT-0199]   Number of violations = 23909.
[INFO DRT-0267] cpu time = 01:16:58, elapsed time = 00:13:56, memory = 20151.48 (MB), peak = 20196.81 (MB)
Total wire length = 24592177 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10620876 um.
Total wire length on LAYER met2 = 10450077 um.
Total wire length on LAYER met3 = 2315556 um.
Total wire length on LAYER met4 = 1192899 um.
Total wire length on LAYER met5 = 12767 um.
Total number of vias = 3370281.
Up-via summary (total 3370281):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451946
           met1    1852012
           met2      49966
           met3      16264
           met4         93
--------------------------
                   3370281


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 22392 violations.
    elapsed time = 00:00:20, memory = 20151.48 (MB).
    Completing 20% with 19134 violations.
    elapsed time = 00:01:06, memory = 20163.60 (MB).
    Completing 30% with 18155 violations.
    elapsed time = 00:01:23, memory = 20163.60 (MB).
    Completing 40% with 16907 violations.
    elapsed time = 00:01:50, memory = 20163.60 (MB).
    Completing 50% with 13635 violations.
    elapsed time = 00:02:29, memory = 20163.60 (MB).
    Completing 60% with 10937 violations.
    elapsed time = 00:02:54, memory = 20163.60 (MB).
    Completing 70% with 7775 violations.
    elapsed time = 00:03:38, memory = 20166.81 (MB).
    Completing 80% with 6822 violations.
    elapsed time = 00:04:01, memory = 20166.81 (MB).
    Completing 90% with 5365 violations.
    elapsed time = 00:04:31, memory = 20166.81 (MB).
    Completing 100% with 946 violations.
    elapsed time = 00:05:16, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 968.
[INFO DRT-0267] cpu time = 00:27:31, elapsed time = 00:05:21, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583487 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10561034 um.
Total wire length on LAYER met2 = 10451604 um.
Total wire length on LAYER met3 = 2364254 um.
Total wire length on LAYER met4 = 1193807 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382081.
Up-via summary (total 3382081):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857289
           met2      56387
           met3      16361
           met4         93
--------------------------
                   3382081


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 942 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 20% with 798 violations.
    elapsed time = 00:00:04, memory = 20167.84 (MB).
    Completing 30% with 772 violations.
    elapsed time = 00:00:05, memory = 20167.84 (MB).
    Completing 40% with 722 violations.
    elapsed time = 00:00:08, memory = 20167.84 (MB).
    Completing 50% with 577 violations.
    elapsed time = 00:00:11, memory = 20167.84 (MB).
    Completing 60% with 485 violations.
    elapsed time = 00:00:13, memory = 20167.84 (MB).
    Completing 70% with 347 violations.
    elapsed time = 00:00:22, memory = 20167.84 (MB).
    Completing 80% with 301 violations.
    elapsed time = 00:00:27, memory = 20167.84 (MB).
    Completing 90% with 256 violations.
    elapsed time = 00:00:28, memory = 20167.84 (MB).
    Completing 100% with 74 violations.
    elapsed time = 00:00:33, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 74.
[INFO DRT-0267] cpu time = 00:01:52, elapsed time = 00:00:33, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583128 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559434 um.
Total wire length on LAYER met2 = 10451769 um.
Total wire length on LAYER met3 = 2365402 um.
Total wire length on LAYER met4 = 1193735 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382226.
Up-via summary (total 3382226):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857297
           met2      56529
           met3      16356
           met4         93
--------------------------
                   3382226


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 71 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 70 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 30% with 70 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 40% with 66 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 65 violations.
    elapsed time = 00:00:03, memory = 20167.84 (MB).
    Completing 60% with 62 violations.
    elapsed time = 00:00:03, memory = 20167.84 (MB).
    Completing 70% with 60 violations.
    elapsed time = 00:00:07, memory = 20167.84 (MB).
    Completing 80% with 58 violations.
    elapsed time = 00:00:07, memory = 20167.84 (MB).
    Completing 90% with 58 violations.
    elapsed time = 00:00:07, memory = 20167.84 (MB).
    Completing 100% with 53 violations.
    elapsed time = 00:00:09, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 53.
[INFO DRT-0267] cpu time = 00:00:18, elapsed time = 00:00:09, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583107 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559379 um.
Total wire length on LAYER met2 = 10451745 um.
Total wire length on LAYER met3 = 2365458 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857296
           met2      56534
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 53 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 50 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 30% with 50 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 40% with 50 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 50 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 60% with 50 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 70% with 50 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 50 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 50 violations.
    elapsed time = 00:00:03, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:05, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:10, elapsed time = 00:00:05, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 11th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 12th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 13th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 14th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 15th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:03, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:08, elapsed time = 00:00:03, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 16th optimization iteration.
    Completing 10% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 46 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 50% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 60% with 46 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 70% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 80% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 90% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
    Completing 100% with 46 violations.
    elapsed time = 00:00:02, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 46.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24583114 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10559381 um.
Total wire length on LAYER met2 = 10451768 um.
Total wire length on LAYER met3 = 2365441 um.
Total wire length on LAYER met4 = 1193736 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382230.
Up-via summary (total 3382230):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857299
           met2      56531
           met3      16356
           met4         93
--------------------------
                   3382230


[INFO DRT-0195] Start 17th optimization iteration.
    Completing 10% with 44 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 42 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 30% with 42 violations.
    elapsed time = 00:00:01, memory = 20167.84 (MB).
    Completing 40% with 32 violations.
    elapsed time = 00:00:03, memory = 20167.84 (MB).
    Completing 50% with 30 violations.
    elapsed time = 00:00:04, memory = 20167.84 (MB).
    Completing 60% with 20 violations.
    elapsed time = 00:00:06, memory = 20167.84 (MB).
    Completing 70% with 19 violations.
    elapsed time = 00:00:06, memory = 20167.84 (MB).
    Completing 80% with 19 violations.
    elapsed time = 00:00:06, memory = 20167.84 (MB).
    Completing 90% with 11 violations.
    elapsed time = 00:00:08, memory = 20167.84 (MB).
    Completing 100% with 6 violations.
    elapsed time = 00:00:08, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 6.
[INFO DRT-0267] cpu time = 00:00:21, elapsed time = 00:00:09, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581956 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557422 um.
Total wire length on LAYER met2 = 10451600 um.
Total wire length on LAYER met3 = 2366650 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382118.
Up-via summary (total 3382118):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857075
           met2      56649
           met3      16350
           met4         93
--------------------------
                   3382118


[INFO DRT-0195] Start 18th optimization iteration.
    Completing 10% with 6 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 6 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 6 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 4 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 4 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 4 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 4 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 4 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0195] Start 25th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0195] Start 33rd optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0195] Start 41st optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0195] Start 49th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0195] Start 57th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20167.84 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20167.84 (MB), peak = 20196.81 (MB)
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0198] Complete detail routing.
Total wire length = 24581941 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 10557386 um.
Total wire length on LAYER met2 = 10451597 um.
Total wire length on LAYER met3 = 2366673 um.
Total wire length on LAYER met4 = 1193497 um.
Total wire length on LAYER met5 = 12786 um.
Total number of vias = 3382120.
Up-via summary (total 3382120):.

--------------------------
 FR_MASTERSLICE          0
            li1    1451951
           met1    1857074
           met2      56652
           met3      16350
           met4         93
--------------------------
                   3382120


[INFO DRT-0267] cpu time = 06:01:06, elapsed time = 01:05:35, memory = 20167.84 (MB), peak = 20196.81 (MB)

[INFO DRT-0180] Post processing.
Elapsed time: 1:08:45[h:]min:sec. CPU time: user 22208.98 sys 13.91 (538%). Peak memory: 20681536KB.
