#--------------------------------------------------------------------------------
# Auto-generated by Migen (7507a2b) & LiteX (feca1c47) on 2021-11-11 13:01:55
#--------------------------------------------------------------------------------
csr_base,ctrl,0xfff00800,,
csr_base,identifier_mem,0xfff01000,,
csr_base,timer0,0xfff01800,,
csr_base,uart,0xfff02000,,
csr_register,ctrl_reset,0xfff00800,1,rw
csr_register,ctrl_scratch,0xfff00804,1,rw
csr_register,ctrl_bus_errors,0xfff00808,1,ro
csr_register,timer0_load,0xfff01800,1,rw
csr_register,timer0_reload,0xfff01804,1,rw
csr_register,timer0_en,0xfff01808,1,rw
csr_register,timer0_update_value,0xfff0180c,1,rw
csr_register,timer0_value,0xfff01810,1,ro
csr_register,timer0_ev_status,0xfff01814,1,ro
csr_register,timer0_ev_pending,0xfff01818,1,rw
csr_register,timer0_ev_enable,0xfff0181c,1,rw
csr_register,uart_rxtx,0xfff02000,1,rw
csr_register,uart_txfull,0xfff02004,1,ro
csr_register,uart_rxempty,0xfff02008,1,ro
csr_register,uart_ev_status,0xfff0200c,1,ro
csr_register,uart_ev_pending,0xfff02010,1,rw
csr_register,uart_ev_enable,0xfff02014,1,rw
csr_register,uart_txempty,0xfff02018,1,ro
csr_register,uart_rxfull,0xfff0201c,1,ro
constant,config_clock_frequency,100000000,,
constant,config_cpu_has_interrupt,None,,
constant,config_cpu_reset_addr,0,,
constant,config_cpu_type_a2p,None,,
constant,config_cpu_variant_standard,None,,
constant,config_cpu_human_name,a2p_wb,,
constant,config_cpu_nop,nop,,
constant,config_with_build_time,None,,
constant,uart_polling,None,,
constant,config_csr_data_width,32,,
constant,config_csr_alignment,32,,
constant,config_bus_standard,wishbone,,
constant,config_bus_data_width,32,,
constant,config_bus_address_width,32,,
constant,timer0_interrupt,1,,
constant,uart_interrupt,0,,
memory_region,rom,0x00000000,65536,cached
memory_region,sram,0x00100000,524288,cached
memory_region,csr,0xfff00000,65536,io
