OpenROAD v2.0-1901-g6157d4945 
This program is licensed under the BSD-3 license. See the LICENSE file for details.
Components of this program may be licensed under more restrictive licenses which must be honored.
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0223]     Created 11 technology layers
[INFO ODB-0224]     Created 25 technology vias
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd.tlef
[INFO ODB-0222] Reading LEF file: ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0225]     Created 437 library cells
[INFO ODB-0226] Finished LEF file:  ./platforms/sky130hd/lef/sky130_fd_sc_hd_merged.lef
[INFO ODB-0127] Reading DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ODB-0128] Design: A2P_WB
[INFO ODB-0094] 		Created 100000 Insts
[INFO ODB-0094] 		Created 200000 Insts
[INFO ODB-0094] 		Created 300000 Insts
[INFO ODB-0094] 		Created 400000 Insts
[INFO ODB-0094] 		Created 500000 Insts
[INFO ODB-0094] 		Created 600000 Insts
[INFO ODB-0094] 		Created 700000 Insts
[INFO ODB-0094] 		Created 800000 Insts
[INFO ODB-0094] 		Created 900000 Insts
[INFO ODB-0094] 		Created 1000000 Insts
[INFO ODB-0094] 		Created 1100000 Insts
[INFO ODB-0094] 		Created 1200000 Insts
[INFO ODB-0094] 		Created 1300000 Insts
[INFO ODB-0094] 		Created 1400000 Insts
[INFO ODB-0094] 		Created 1500000 Insts
[INFO ODB-0094] 		Created 1600000 Insts
[INFO ODB-0094] 		Created 1700000 Insts
[INFO ODB-0094] 		Created 1800000 Insts
[INFO ODB-0094] 		Created 1900000 Insts
[INFO ODB-0094] 		Created 2000000 Insts
[INFO ODB-0094] 		Created 2100000 Insts
[INFO ODB-0094] 		Created 2200000 Insts
[INFO ODB-0094] 		Created 2300000 Insts
[INFO ODB-0094] 		Created 2400000 Insts
[INFO ODB-0094] 		Created 2500000 Insts
[INFO ODB-0094] 		Created 2600000 Insts
[INFO ODB-0097] 		Created 100000 Nets
[INFO ODB-0097] 		Created 200000 Nets
[INFO ODB-0097] 		Created 300000 Nets
[INFO ODB-0130]     Created 254 pins.
[INFO ODB-0131]     Created 2690076 components and 6760992 component-terminals.
[INFO ODB-0132]     Created 2 special nets and 5380152 connections.
[INFO ODB-0133]     Created 366270 nets and 1375112 connections.
[INFO ODB-0134] Finished DEF file: ./results/sky130hd/a2p/base/4_cts.def
[INFO ORD-0030] Using 6 thread(s).
[INFO DRT-0149] Reading tech and libs.

Units:                1000
Number of layers:     13
Number of macros:     437
Number of vias:       25
Number of viarulegen: 25

[INFO DRT-0150] Reading design.

Design:                   A2P_WB
Die area:                 ( 0 0 ) ( 5200000 4609140 )
Number of track patterns: 12
Number of DEF vias:       4
Number of components:     2690076
Number of terminals:      254
Number of snets:          2
Number of nets:           366270

[INFO DRT-0151] Reading guide.
[INFO DRT-0156] guideIn read 100000 guides.
[INFO DRT-0156] guideIn read 200000 guides.
[INFO DRT-0156] guideIn read 300000 guides.
[INFO DRT-0156] guideIn read 400000 guides.
[INFO DRT-0156] guideIn read 500000 guides.
[INFO DRT-0156] guideIn read 600000 guides.
[INFO DRT-0156] guideIn read 700000 guides.
[INFO DRT-0156] guideIn read 800000 guides.
[INFO DRT-0156] guideIn read 900000 guides.
[INFO DRT-0157] guideIn read 1000000 guides.
[INFO DRT-0157] guideIn read 2000000 guides.
[INFO DRT-0157] guideIn read 3000000 guides.

Number of guides:     3345769

[INFO DRT-0167] List of default vias:
  Layer mcon
    default via: L1M1_PR
  Layer via
    default via: M1M2_PR
  Layer via2
    default via: M2M3_PR
  Layer via3
    default via: M3M4_PR
  Layer via4
    default via: M4M5_PR_MR
[INFO DRT-0162] Library cell analysis.
[INFO DRT-0163] Instance analysis.
  Complete 10000 instances.
  Complete 20000 instances.
  Complete 30000 instances.
  Complete 40000 instances.
  Complete 50000 instances.
  Complete 60000 instances.
  Complete 70000 instances.
  Complete 80000 instances.
  Complete 90000 instances.
  Complete 100000 instances.
  Complete 200000 instances.
  Complete 300000 instances.
  Complete 400000 instances.
  Complete 500000 instances.
  Complete 600000 instances.
  Complete 700000 instances.
  Complete 800000 instances.
  Complete 900000 instances.
  Complete 1000000 instances.
  Complete 1100000 instances.
  Complete 1200000 instances.
  Complete 1300000 instances.
  Complete 1400000 instances.
  Complete 1500000 instances.
  Complete 1600000 instances.
  Complete 1700000 instances.
  Complete 1800000 instances.
  Complete 1900000 instances.
  Complete 2000000 instances.
  Complete 2100000 instances.
  Complete 2200000 instances.
  Complete 2300000 instances.
  Complete 2400000 instances.
  Complete 2500000 instances.
  Complete 2600000 instances.
[INFO DRT-0164] Number of unique instances = 506.
[INFO DRT-0168] Init region query.
[INFO DRT-0018]   Complete 10000 insts.
[INFO DRT-0018]   Complete 20000 insts.
[INFO DRT-0018]   Complete 30000 insts.
[INFO DRT-0018]   Complete 40000 insts.
[INFO DRT-0018]   Complete 50000 insts.
[INFO DRT-0018]   Complete 60000 insts.
[INFO DRT-0018]   Complete 70000 insts.
[INFO DRT-0018]   Complete 80000 insts.
[INFO DRT-0018]   Complete 90000 insts.
[INFO DRT-0019]   Complete 100000 insts.
[INFO DRT-0019]   Complete 200000 insts.
[INFO DRT-0019]   Complete 300000 insts.
[INFO DRT-0019]   Complete 400000 insts.
[INFO DRT-0019]   Complete 500000 insts.
[INFO DRT-0019]   Complete 600000 insts.
[INFO DRT-0019]   Complete 700000 insts.
[INFO DRT-0019]   Complete 800000 insts.
[INFO DRT-0019]   Complete 900000 insts.
[INFO DRT-0019]   Complete 1000000 insts.
[INFO DRT-0019]   Complete 1100000 insts.
[INFO DRT-0019]   Complete 1200000 insts.
[INFO DRT-0019]   Complete 1300000 insts.
[INFO DRT-0019]   Complete 1400000 insts.
[INFO DRT-0019]   Complete 1500000 insts.
[INFO DRT-0019]   Complete 1600000 insts.
[INFO DRT-0019]   Complete 1700000 insts.
[INFO DRT-0019]   Complete 1800000 insts.
[INFO DRT-0019]   Complete 1900000 insts.
[INFO DRT-0019]   Complete 2000000 insts.
[INFO DRT-0019]   Complete 2100000 insts.
[INFO DRT-0019]   Complete 2200000 insts.
[INFO DRT-0019]   Complete 2300000 insts.
[INFO DRT-0019]   Complete 2400000 insts.
[INFO DRT-0019]   Complete 2500000 insts.
[INFO DRT-0019]   Complete 2600000 insts.
[INFO DRT-0024]   Complete FR_MASTERSLICE.
[INFO DRT-0024]   Complete FR_VIA.
[INFO DRT-0024]   Complete li1.
[INFO DRT-0024]   Complete mcon.
[INFO DRT-0024]   Complete met1.
[INFO DRT-0024]   Complete via.
[INFO DRT-0024]   Complete met2.
[INFO DRT-0024]   Complete via2.
[INFO DRT-0024]   Complete met3.
[INFO DRT-0024]   Complete via3.
[INFO DRT-0024]   Complete met4.
[INFO DRT-0024]   Complete via4.
[INFO DRT-0024]   Complete met5.
[INFO DRT-0033] FR_MASTERSLICE shape region query size = 0.
[INFO DRT-0033] FR_VIA shape region query size = 0.
[INFO DRT-0033] li1 shape region query size = 20948213.
[INFO DRT-0033] mcon shape region query size = 829663.
[INFO DRT-0033] met1 shape region query size = 7734660.
[INFO DRT-0033] via shape region query size = 1351680.
[INFO DRT-0033] met2 shape region query size = 540893.
[INFO DRT-0033] via2 shape region query size = 1081344.
[INFO DRT-0033] met3 shape region query size = 540705.
[INFO DRT-0033] via3 shape region query size = 1081344.
[INFO DRT-0033] met4 shape region query size = 324544.
[INFO DRT-0033] via4 shape region query size = 53856.
[INFO DRT-0033] met5 shape region query size = 54162.
[INFO DRT-0165] Start pin access.
[INFO DRT-0076]   Complete 100 pins.
[INFO DRT-0076]   Complete 200 pins.
[INFO DRT-0076]   Complete 300 pins.
[INFO DRT-0076]   Complete 400 pins.
[INFO DRT-0076]   Complete 500 pins.
[INFO DRT-0076]   Complete 600 pins.
[INFO DRT-0076]   Complete 700 pins.
[INFO DRT-0076]   Complete 800 pins.
[INFO DRT-0076]   Complete 900 pins.
[INFO DRT-0077]   Complete 1000 pins.
[INFO DRT-0077]   Complete 2000 pins.
[INFO DRT-0078]   Complete 2182 pins.
[INFO DRT-0079]   Complete 100 unique inst patterns.
[INFO DRT-0079]   Complete 200 unique inst patterns.
[INFO DRT-0079]   Complete 300 unique inst patterns.
[INFO DRT-0079]   Complete 400 unique inst patterns.
[INFO DRT-0081]   Complete 496 unique inst patterns.
[INFO DRT-0082]   Complete 1000 groups.
[INFO DRT-0082]   Complete 2000 groups.
[INFO DRT-0082]   Complete 3000 groups.
[INFO DRT-0082]   Complete 4000 groups.
[INFO DRT-0082]   Complete 5000 groups.
[INFO DRT-0082]   Complete 6000 groups.
[INFO DRT-0082]   Complete 7000 groups.
[INFO DRT-0082]   Complete 8000 groups.
[INFO DRT-0082]   Complete 9000 groups.
[INFO DRT-0083]   Complete 10000 groups.
[INFO DRT-0083]   Complete 20000 groups.
[INFO DRT-0083]   Complete 30000 groups.
[INFO DRT-0083]   Complete 40000 groups.
[INFO DRT-0083]   Complete 50000 groups.
[INFO DRT-0083]   Complete 60000 groups.
[INFO DRT-0083]   Complete 70000 groups.
[INFO DRT-0083]   Complete 80000 groups.
[INFO DRT-0083]   Complete 90000 groups.
[INFO DRT-0083]   Complete 100000 groups.
[INFO DRT-0083]   Complete 110000 groups.
[INFO DRT-0083]   Complete 120000 groups.
[INFO DRT-0083]   Complete 130000 groups.
[INFO DRT-0083]   Complete 140000 groups.
[INFO DRT-0083]   Complete 150000 groups.
[INFO DRT-0083]   Complete 160000 groups.
[INFO DRT-0083]   Complete 170000 groups.
[INFO DRT-0083]   Complete 180000 groups.
[INFO DRT-0083]   Complete 190000 groups.
[INFO DRT-0083]   Complete 200000 groups.
[INFO DRT-0083]   Complete 210000 groups.
[INFO DRT-0083]   Complete 220000 groups.
[INFO DRT-0083]   Complete 230000 groups.
[INFO DRT-0083]   Complete 240000 groups.
[INFO DRT-0083]   Complete 250000 groups.
[INFO DRT-0083]   Complete 260000 groups.
[INFO DRT-0083]   Complete 270000 groups.
[INFO DRT-0083]   Complete 280000 groups.
[INFO DRT-0083]   Complete 290000 groups.
[INFO DRT-0083]   Complete 300000 groups.
[INFO DRT-0083]   Complete 310000 groups.
[INFO DRT-0083]   Complete 320000 groups.
[INFO DRT-0083]   Complete 330000 groups.
[INFO DRT-0083]   Complete 340000 groups.
[INFO DRT-0083]   Complete 350000 groups.
[INFO DRT-0083]   Complete 360000 groups.
[INFO DRT-0083]   Complete 370000 groups.
[INFO DRT-0083]   Complete 380000 groups.
[INFO DRT-0083]   Complete 390000 groups.
[INFO DRT-0083]   Complete 400000 groups.
[INFO DRT-0083]   Complete 410000 groups.
[INFO DRT-0083]   Complete 420000 groups.
[INFO DRT-0083]   Complete 430000 groups.
[INFO DRT-0084]   Complete 434425 groups.
#scanned instances     = 2690076
#unique  instances     = 506
#stdCellGenAp          = 18124
#stdCellValidPlanarAp  = 358
#stdCellValidViaAp     = 13048
#stdCellPinNoAp        = 0
#stdCellPinCnt         = 1375112
#instTermValidViaApCnt = 0
#macroGenAp            = 0
#macroValidPlanarAp    = 0
#macroValidViaAp       = 0
#macroNoAp             = 0
[INFO DRT-0166] Complete pin access.
[INFO DRT-0267] cpu time = 00:00:16, elapsed time = 00:00:04, memory = 6381.46 (MB), peak = 6779.47 (MB)
[INFO DRT-0169] Post process guides.
[INFO DRT-0176] GCELLGRID X 0 DO 667 STEP 6900 ;
[INFO DRT-0177] GCELLGRID Y 0 DO 753 STEP 6900 ;
[INFO DRT-0026]   Complete 10000 origin guides.
[INFO DRT-0026]   Complete 20000 origin guides.
[INFO DRT-0026]   Complete 30000 origin guides.
[INFO DRT-0026]   Complete 40000 origin guides.
[INFO DRT-0026]   Complete 50000 origin guides.
[INFO DRT-0026]   Complete 60000 origin guides.
[INFO DRT-0026]   Complete 70000 origin guides.
[INFO DRT-0026]   Complete 80000 origin guides.
[INFO DRT-0026]   Complete 90000 origin guides.
[INFO DRT-0027]   Complete 100000 origin guides.
[INFO DRT-0027]   Complete 200000 origin guides.
[INFO DRT-0027]   Complete 300000 origin guides.
[INFO DRT-0027]   Complete 400000 origin guides.
[INFO DRT-0027]   Complete 500000 origin guides.
[INFO DRT-0027]   Complete 600000 origin guides.
[INFO DRT-0027]   Complete 700000 origin guides.
[INFO DRT-0027]   Complete 800000 origin guides.
[INFO DRT-0027]   Complete 900000 origin guides.
[INFO DRT-0027]   Complete 1000000 origin guides.
[INFO DRT-0027]   Complete 1100000 origin guides.
[INFO DRT-0027]   Complete 1200000 origin guides.
[INFO DRT-0027]   Complete 1300000 origin guides.
[INFO DRT-0027]   Complete 1400000 origin guides.
[INFO DRT-0027]   Complete 1500000 origin guides.
[INFO DRT-0027]   Complete 1600000 origin guides.
[INFO DRT-0027]   Complete 1700000 origin guides.
[INFO DRT-0027]   Complete 1800000 origin guides.
[INFO DRT-0027]   Complete 1900000 origin guides.
[INFO DRT-0027]   Complete 2000000 origin guides.
[INFO DRT-0027]   Complete 2100000 origin guides.
[INFO DRT-0027]   Complete 2200000 origin guides.
[INFO DRT-0027]   Complete 2300000 origin guides.
[INFO DRT-0027]   Complete 2400000 origin guides.
[INFO DRT-0027]   Complete 2500000 origin guides.
[INFO DRT-0027]   Complete 2600000 origin guides.
[INFO DRT-0027]   Complete 2700000 origin guides.
[INFO DRT-0027]   Complete 2800000 origin guides.
[INFO DRT-0027]   Complete 2900000 origin guides.
[INFO DRT-0027]   Complete 3000000 origin guides.
[INFO DRT-0027]   Complete 3100000 origin guides.
[INFO DRT-0027]   Complete 3200000 origin guides.
[INFO DRT-0027]   Complete 3300000 origin guides.
[INFO DRT-0028]   Complete FR_MASTERSLICE.
[INFO DRT-0028]   Complete FR_VIA.
[INFO DRT-0028]   Complete li1.
[INFO DRT-0028]   Complete mcon.
[INFO DRT-0028]   Complete met1.
[INFO DRT-0028]   Complete via.
[INFO DRT-0028]   Complete met2.
[INFO DRT-0028]   Complete via2.
[INFO DRT-0028]   Complete met3.
[INFO DRT-0028]   Complete via3.
[INFO DRT-0028]   Complete met4.
[INFO DRT-0028]   Complete via4.
[INFO DRT-0028]   Complete met5.
  complete 10000 nets.
  complete 20000 nets.
  complete 30000 nets.
  complete 40000 nets.
  complete 50000 nets.
  complete 60000 nets.
  complete 70000 nets.
  complete 80000 nets.
  complete 90000 nets.
  complete 100000 nets.
  complete 200000 nets.
  complete 300000 nets.
[INFO DRT-0178] Init guide query.
[INFO DRT-0029]   Complete 10000 nets (guide).
[INFO DRT-0029]   Complete 20000 nets (guide).
[INFO DRT-0029]   Complete 30000 nets (guide).
[INFO DRT-0029]   Complete 40000 nets (guide).
[INFO DRT-0029]   Complete 50000 nets (guide).
[INFO DRT-0029]   Complete 60000 nets (guide).
[INFO DRT-0029]   Complete 70000 nets (guide).
[INFO DRT-0029]   Complete 80000 nets (guide).
[INFO DRT-0029]   Complete 90000 nets (guide).
[INFO DRT-0030]   Complete 100000 nets (guide).
[INFO DRT-0030]   Complete 200000 nets (guide).
[INFO DRT-0030]   Complete 300000 nets (guide).
[INFO DRT-0035]   Complete FR_MASTERSLICE (guide).
[INFO DRT-0035]   Complete FR_VIA (guide).
[INFO DRT-0035]   Complete li1 (guide).
[INFO DRT-0035]   Complete mcon (guide).
[INFO DRT-0035]   Complete met1 (guide).
[INFO DRT-0035]   Complete via (guide).
[INFO DRT-0035]   Complete met2 (guide).
[INFO DRT-0035]   Complete via2 (guide).
[INFO DRT-0035]   Complete met3 (guide).
[INFO DRT-0035]   Complete via3 (guide).
[INFO DRT-0035]   Complete met4 (guide).
[INFO DRT-0035]   Complete via4 (guide).
[INFO DRT-0035]   Complete met5 (guide).
[INFO DRT-0036] FR_MASTERSLICE guide region query size = 0.
[INFO DRT-0036] FR_VIA guide region query size = 0.
[INFO DRT-0036] li1 guide region query size = 1172392.
[INFO DRT-0036] mcon guide region query size = 0.
[INFO DRT-0036] met1 guide region query size = 1020452.
[INFO DRT-0036] via guide region query size = 0.
[INFO DRT-0036] met2 guide region query size = 627764.
[INFO DRT-0036] via2 guide region query size = 0.
[INFO DRT-0036] met3 guide region query size = 24597.
[INFO DRT-0036] via3 guide region query size = 0.
[INFO DRT-0036] met4 guide region query size = 7063.
[INFO DRT-0036] via4 guide region query size = 0.
[INFO DRT-0036] met5 guide region query size = 65.
[INFO DRT-0179] Init gr pin query.
[INFO DRT-0185] Post process initialize RPin region query.
[INFO DRT-0181] Start track assignment.
[INFO DRT-0184] Done with 1807219 vertical wires in 16 frboxes and 1045114 horizontal wires in 14 frboxes.
[INFO DRT-0186] Done with 277381 vertical wires in 16 frboxes and 276460 horizontal wires in 14 frboxes.
[INFO DRT-0182] Complete track assignment.
[INFO DRT-0267] cpu time = 00:07:16, elapsed time = 00:01:46, memory = 11248.45 (MB), peak = 11508.95 (MB)
[INFO DRT-0187] Start routing data preparation.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:01, memory = 11248.45 (MB), peak = 11508.95 (MB)
[INFO DRT-0194] Start detail routing.
[INFO DRT-0195] Start 0th optimization iteration.
    Completing 10% with 11613 violations.
    elapsed time = 00:02:07, memory = 16475.86 (MB).
    Completing 20% with 29373 violations.
    elapsed time = 00:04:35, memory = 18189.11 (MB).
    Completing 30% with 34793 violations.
    elapsed time = 00:05:58, memory = 18189.11 (MB).
    Completing 40% with 45883 violations.
    elapsed time = 00:08:54, memory = 18189.11 (MB).
    Completing 50% with 62406 violations.
    elapsed time = 00:10:47, memory = 18725.36 (MB).
    Completing 60% with 77981 violations.
    elapsed time = 00:14:10, memory = 18725.36 (MB).
    Completing 70% with 93530 violations.
    elapsed time = 00:17:15, memory = 19367.76 (MB).
    Completing 80% with 97812 violations.
    elapsed time = 00:19:14, memory = 19386.17 (MB).
    Completing 90% with 107807 violations.
    elapsed time = 00:23:29, memory = 19394.99 (MB).
    Completing 100% with 126016 violations.
    elapsed time = 00:25:40, memory = 19973.93 (MB).
[INFO DRT-0199]   Number of violations = 396689.
[INFO DRT-0267] cpu time = 02:29:11, elapsed time = 00:25:55, memory = 19941.99 (MB), peak = 19985.88 (MB)
Total wire length = 22448368 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9799889 um.
Total wire length on LAYER met2 = 9803165 um.
Total wire length on LAYER met3 = 1789134 um.
Total wire length on LAYER met4 = 1043020 um.
Total wire length on LAYER met5 = 13157 um.
Total number of vias = 3181714.
Up-via summary (total 3181714):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362815
           met1    1764895
           met2      40967
           met3      12919
           met4        118
--------------------------
                   3181714


[INFO DRT-0195] Start 1st optimization iteration.
    Completing 10% with 361330 violations.
    elapsed time = 00:01:18, memory = 19893.35 (MB).
    Completing 20% with 317648 violations.
    elapsed time = 00:03:04, memory = 19902.72 (MB).
    Completing 30% with 302619 violations.
    elapsed time = 00:03:59, memory = 19907.04 (MB).
    Completing 40% with 269968 violations.
    elapsed time = 00:05:51, memory = 19893.52 (MB).
    Completing 50% with 227996 violations.
    elapsed time = 00:07:14, memory = 19954.67 (MB).
    Completing 60% with 176227 violations.
    elapsed time = 00:08:43, memory = 19954.67 (MB).
    Completing 70% with 132118 violations.
    elapsed time = 00:10:35, memory = 20104.63 (MB).
    Completing 80% with 118563 violations.
    elapsed time = 00:11:33, memory = 20107.66 (MB).
    Completing 90% with 82546 violations.
    elapsed time = 00:13:34, memory = 20107.66 (MB).
    Completing 100% with 28053 violations.
    elapsed time = 00:15:02, memory = 20065.69 (MB).
[INFO DRT-0199]   Number of violations = 28112.
[INFO DRT-0267] cpu time = 01:24:55, elapsed time = 00:15:18, memory = 20065.69 (MB), peak = 20114.63 (MB)
Total wire length = 22235630 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9704563 um.
Total wire length on LAYER met2 = 9696703 um.
Total wire length on LAYER met3 = 1781865 um.
Total wire length on LAYER met4 = 1039320 um.
Total wire length on LAYER met5 = 13177 um.
Total number of vias = 3160131.
Up-via summary (total 3160131):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362452
           met1    1743697
           met2      41138
           met3      12735
           met4        109
--------------------------
                   3160131


[INFO DRT-0195] Start 2nd optimization iteration.
    Completing 10% with 27624 violations.
    elapsed time = 00:00:58, memory = 20065.69 (MB).
    Completing 20% with 26934 violations.
    elapsed time = 00:02:34, memory = 20002.30 (MB).
    Completing 30% with 26643 violations.
    elapsed time = 00:03:14, memory = 20002.30 (MB).
    Completing 40% with 26103 violations.
    elapsed time = 00:04:40, memory = 20002.30 (MB).
    Completing 50% with 25175 violations.
    elapsed time = 00:05:58, memory = 20002.30 (MB).
    Completing 60% with 24978 violations.
    elapsed time = 00:06:56, memory = 20002.30 (MB).
    Completing 70% with 24180 violations.
    elapsed time = 00:08:26, memory = 20002.30 (MB).
    Completing 80% with 22547 violations.
    elapsed time = 00:09:15, memory = 20002.30 (MB).
    Completing 90% with 21707 violations.
    elapsed time = 00:10:45, memory = 20002.30 (MB).
    Completing 100% with 19879 violations.
    elapsed time = 00:12:01, memory = 20002.30 (MB).
[INFO DRT-0199]   Number of violations = 19893.
[INFO DRT-0267] cpu time = 01:07:39, elapsed time = 00:12:18, memory = 20002.30 (MB), peak = 20114.63 (MB)
Total wire length = 22159113 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9673589 um.
Total wire length on LAYER met2 = 9654055 um.
Total wire length on LAYER met3 = 1778898 um.
Total wire length on LAYER met4 = 1039431 um.
Total wire length on LAYER met5 = 13138 um.
Total number of vias = 3147581.
Up-via summary (total 3147581):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362439
           met1    1731764
           met2      40492
           met3      12781
           met4        105
--------------------------
                   3147581


[INFO DRT-0195] Start 3rd optimization iteration.
    Completing 10% with 18796 violations.
    elapsed time = 00:00:17, memory = 20002.30 (MB).
    Completing 20% with 15982 violations.
    elapsed time = 00:01:00, memory = 20010.80 (MB).
    Completing 30% with 15115 violations.
    elapsed time = 00:01:21, memory = 20010.80 (MB).
    Completing 40% with 13971 violations.
    elapsed time = 00:01:56, memory = 20010.80 (MB).
    Completing 50% with 11432 violations.
    elapsed time = 00:02:29, memory = 20010.80 (MB).
    Completing 60% with 9524 violations.
    elapsed time = 00:02:49, memory = 20010.80 (MB).
    Completing 70% with 6673 violations.
    elapsed time = 00:03:32, memory = 20011.32 (MB).
    Completing 80% with 5882 violations.
    elapsed time = 00:03:47, memory = 20011.32 (MB).
    Completing 90% with 4667 violations.
    elapsed time = 00:04:34, memory = 20011.32 (MB).
    Completing 100% with 930 violations.
    elapsed time = 00:05:10, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 938.
[INFO DRT-0267] cpu time = 00:24:52, elapsed time = 00:05:15, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22151115 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9623594 um.
Total wire length on LAYER met2 = 9654534 um.
Total wire length on LAYER met3 = 1819740 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157352.
Up-via summary (total 3157352):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362443
           met1    1735762
           met2      46183
           met3      12859
           met4        105
--------------------------
                   3157352


[INFO DRT-0195] Start 4th optimization iteration.
    Completing 10% with 927 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 20% with 813 violations.
    elapsed time = 00:00:04, memory = 20011.32 (MB).
    Completing 30% with 802 violations.
    elapsed time = 00:00:05, memory = 20011.32 (MB).
    Completing 40% with 769 violations.
    elapsed time = 00:00:07, memory = 20011.32 (MB).
    Completing 50% with 619 violations.
    elapsed time = 00:00:16, memory = 20011.32 (MB).
    Completing 60% with 508 violations.
    elapsed time = 00:00:18, memory = 20011.32 (MB).
    Completing 70% with 409 violations.
    elapsed time = 00:00:24, memory = 20011.32 (MB).
    Completing 80% with 397 violations.
    elapsed time = 00:00:27, memory = 20011.32 (MB).
    Completing 90% with 347 violations.
    elapsed time = 00:00:31, memory = 20011.32 (MB).
    Completing 100% with 121 violations.
    elapsed time = 00:00:40, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 121.
[INFO DRT-0267] cpu time = 00:02:02, elapsed time = 00:00:40, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150820 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621963 um.
Total wire length on LAYER met2 = 9654589 um.
Total wire length on LAYER met3 = 1821017 um.
Total wire length on LAYER met4 = 1040124 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157590.
Up-via summary (total 3157590):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735852
           met2      46330
           met3      12861
           met4        105
--------------------------
                   3157590


[INFO DRT-0195] Start 5th optimization iteration.
    Completing 10% with 121 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 97 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 30% with 97 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 40% with 96 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 82 violations.
    elapsed time = 00:00:04, memory = 20011.32 (MB).
    Completing 60% with 80 violations.
    elapsed time = 00:00:04, memory = 20011.32 (MB).
    Completing 70% with 73 violations.
    elapsed time = 00:00:09, memory = 20011.32 (MB).
    Completing 80% with 73 violations.
    elapsed time = 00:00:09, memory = 20011.32 (MB).
    Completing 90% with 73 violations.
    elapsed time = 00:00:09, memory = 20011.32 (MB).
    Completing 100% with 63 violations.
    elapsed time = 00:00:11, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 63.
[INFO DRT-0267] cpu time = 00:00:23, elapsed time = 00:00:11, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150822 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621997 um.
Total wire length on LAYER met2 = 9654595 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157583.
Up-via summary (total 3157583):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735844
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157583


[INFO DRT-0195] Start 6th optimization iteration.
    Completing 10% with 63 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 63 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 63 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 63 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 57 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 60% with 57 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:03, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:03, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:03, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:03, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:09, elapsed time = 00:00:03, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 7th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 8th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 9th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 10th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 11th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 12th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 13th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 14th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 15th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:07, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 16th optimization iteration.
    Completing 10% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 56 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 50% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 60% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 70% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 80% with 56 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 90% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 100% with 56 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 56.
[INFO DRT-0267] cpu time = 00:00:06, elapsed time = 00:00:02, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150825 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9621980 um.
Total wire length on LAYER met2 = 9654615 um.
Total wire length on LAYER met3 = 1820984 um.
Total wire length on LAYER met4 = 1040119 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157587.
Up-via summary (total 3157587):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362442
           met1    1735848
           met2      46332
           met3      12860
           met4        105
--------------------------
                   3157587


[INFO DRT-0195] Start 17th optimization iteration.
    Completing 10% with 45 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 20% with 45 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 30% with 45 violations.
    elapsed time = 00:00:01, memory = 20011.32 (MB).
    Completing 40% with 26 violations.
    elapsed time = 00:00:02, memory = 20011.32 (MB).
    Completing 50% with 22 violations.
    elapsed time = 00:00:03, memory = 20011.32 (MB).
    Completing 60% with 17 violations.
    elapsed time = 00:00:07, memory = 20011.32 (MB).
    Completing 70% with 13 violations.
    elapsed time = 00:00:08, memory = 20011.32 (MB).
    Completing 80% with 13 violations.
    elapsed time = 00:00:08, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:08, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:09, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:20, elapsed time = 00:00:10, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 18th optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 19th optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 20th optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 21st optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 22nd optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 23rd optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 24th optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 3.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150055 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620914 um.
Total wire length on LAYER met2 = 9654428 um.
Total wire length on LAYER met3 = 1821526 um.
Total wire length on LAYER met4 = 1040061 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157605.
Up-via summary (total 3157605):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735814
           met2      46381
           met3      12861
           met4        105
--------------------------
                   3157605


[INFO DRT-0195] Start 25th optimization iteration.
    Completing 10% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 3 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 2 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 2 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 2 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 2 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:01, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0195] Start 33rd optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0195] Start 41st optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0195] Start 49th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0195] Start 57th optimization iteration.
    Completing 10% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 20% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 30% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 40% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 50% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 60% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 70% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 80% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 90% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
    Completing 100% with 0 violations.
    elapsed time = 00:00:00, memory = 20011.32 (MB).
[INFO DRT-0199]   Number of violations = 0.
[INFO DRT-0267] cpu time = 00:00:00, elapsed time = 00:00:00, memory = 20011.32 (MB), peak = 20114.63 (MB)
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0198] Complete detail routing.
Total wire length = 22150044 um.
Total wire length on LAYER li1 = 0 um.
Total wire length on LAYER met1 = 9620900 um.
Total wire length on LAYER met2 = 9654445 um.
Total wire length on LAYER met3 = 1821529 um.
Total wire length on LAYER met4 = 1040044 um.
Total wire length on LAYER met5 = 13125 um.
Total number of vias = 3157600.
Up-via summary (total 3157600):.

--------------------------
 FR_MASTERSLICE          0
            li1    1362444
           met1    1735810
           met2      46382
           met3      12859
           met4        105
--------------------------
                   3157600


[INFO DRT-0267] cpu time = 05:31:25, elapsed time = 01:00:58, memory = 20011.32 (MB), peak = 20114.63 (MB)

[INFO DRT-0180] Post processing.
Elapsed time: 1:03:57[h:]min:sec. CPU time: user 20392.72 sys 12.90 (531%). Peak memory: 20597380KB.
