From 20b16f1810b6d7e316a8ece39261359343df1f74 Mon Sep 17 00:00:00 2001 From: openpowerwtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Sat, 27 Aug 2022 11:23:46 -0500 Subject: [PATCH] testing full litex software build --- build/litex/a2p_a2o_32.py | 227 + build/litex/a2p_new/__init__.py | 1 + build/litex/a2p_new/boot-helper.S | 50 + build/litex/a2p_new/core.py | 150 + build/litex/a2p_new/crt0.S | 261 + build/litex/a2p_new/crtsavres.s | 129 + build/litex/a2p_new/defines.s | 146 + build/litex/a2p_new/irq.h | 18 + build/litex/a2p_new/system.h | 67 + build/litex/a2p_new/verilog/A2P_WB.v | 14250 ++++++++++++++++++++ build/litex/bin2init | 27 + sim/soc/A2P_WB.v | 14250 ++++++++++++++++++++ sim/soc/bios.s | 17887 +++++++++++++++++++++++++ sim/soc/cmod7_rom.init | 6199 +++++++++ sim/soc/readme.md | 52 + sim/soc/soc.v | 1958 +++ sim/soc/tb_litex_soc.cpp | 455 + sim/soc/unisims/BUFG.v | 4 + sim/soc/unisims/DNA_PORT.v | 10 + sim/soc/unisims/FD.v | 21 + sim/soc/unisims/FDCE.v | 24 + sim/soc/unisims/FDPE.v | 24 + sim/soc/unisims/IDELAYCTRL.v | 10 + sim/soc/unisims/IDELAYE2.v | 24 + sim/soc/unisims/IOBUF.v | 13 + sim/soc/unisims/IOBUFDS.v | 13 + sim/soc/unisims/ISERDESE2.v | 31 + sim/soc/unisims/MMCME2_ADV.v | 95 + sim/soc/unisims/OBUFDS.v | 12 + sim/soc/unisims/OSERDESE2.v | 33 + sim/soc/unisims/XADC.v | 93 + sim/soc/wbuart32 | 1 + 32 files changed, 56535 insertions(+) create mode 100755 build/litex/a2p_a2o_32.py create mode 100644 build/litex/a2p_new/__init__.py create mode 100644 build/litex/a2p_new/boot-helper.S create mode 100644 build/litex/a2p_new/core.py create mode 100644 build/litex/a2p_new/crt0.S create mode 100644 build/litex/a2p_new/crtsavres.s create mode 100644 build/litex/a2p_new/defines.s create mode 100644 build/litex/a2p_new/irq.h create mode 100644 build/litex/a2p_new/system.h create mode 100644 build/litex/a2p_new/verilog/A2P_WB.v create mode 100755 build/litex/bin2init create mode 100644 sim/soc/A2P_WB.v create mode 100644 sim/soc/bios.s create mode 100644 sim/soc/cmod7_rom.init create mode 100644 sim/soc/readme.md create mode 100644 sim/soc/soc.v create mode 100644 sim/soc/tb_litex_soc.cpp create mode 100644 sim/soc/unisims/BUFG.v create mode 100644 sim/soc/unisims/DNA_PORT.v create mode 100644 sim/soc/unisims/FD.v create mode 100644 sim/soc/unisims/FDCE.v create mode 100644 sim/soc/unisims/FDPE.v create mode 100644 sim/soc/unisims/IDELAYCTRL.v create mode 100644 sim/soc/unisims/IDELAYE2.v create mode 100644 sim/soc/unisims/IOBUF.v create mode 100644 sim/soc/unisims/IOBUFDS.v create mode 100644 sim/soc/unisims/ISERDESE2.v create mode 100644 sim/soc/unisims/MMCME2_ADV.v create mode 100644 sim/soc/unisims/OBUFDS.v create mode 100644 sim/soc/unisims/OSERDESE2.v create mode 100644 sim/soc/unisims/XADC.v create mode 120000 sim/soc/wbuart32 diff --git a/build/litex/a2p_a2o_32.py b/build/litex/a2p_a2o_32.py new file mode 100755 index 0000000..305bc5f --- /dev/null +++ b/build/litex/a2p_a2o_32.py @@ -0,0 +1,227 @@ +#!/usr/bin/python3 + +# A2P Test from A2O 32BE Test (minimal changes to see if litex software compile works with a2p) +# a2p_a2o_32.py --csr-csv csr.csv +# a2p_a2o_32.py --csr-csv csr.csv --build [--sys-clk-freq 50e6] +# + +import os +import argparse + +from migen import * + +# wtf - use local platform +from platforms import cmod7 +#from platforms import cmod7_kintex + +# wtf - use local core (not built into litex) +# help python find package +# not needed anymore +#import sys +#binPath = os.path.dirname(os.path.realpath(__file__)) +#sys.path.append(os.path.join(binPath, 'a2o')) # dir with core package; core.py defines core source location +# get core def +from a2p_new import A2P +# add to litex dict +from litex.soc.cores import cpu +cpu.CPUS['a2p'] = A2P + +from litex.soc.cores.clock import * +from litex.soc.integration.soc import SoCRegion +from litex.soc.integration.soc_core import * +from litex.soc.integration.builder import * + +from litex.soc.cores.led import LedChaser +from litex.soc.cores import dna, xadc +from litex.soc.cores.gpio import GPIOIn +from litex.soc.cores.gpio import GPIOOut +from litex.soc.cores.bitbang import I2CMaster + +from litex.soc.interconnect import wishbone + +from litex.soc.cores import uart +from litex.soc.cores.uart import UART +from litex.soc.cores.uart import UARTPHY +from litex.soc.cores.uart import UARTWishboneBridge +from litescope import LiteScopeAnalyzer + +# CRG ---------------------------------------------------------------------------------------------- + +class _CRG(Module): + def __init__(self, platform, sys_clk_freq): + self.rst = Signal() + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys2x = ClockDomain(reset_less=True) + self.clock_domains.cd_idelay = ClockDomain() + + self.submodules.pll = pll = S7MMCM(speedgrade=-1) + #wtf how do you add btn to reset sig? + #x = platform.request('user_btn',0) + self.comb += pll.reset.eq(self.rst) + #self.comb += pll.reset.eq(self.rst) + pll.register_clkin(platform.request('clk12'), 12e6) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys2x, 2*sys_clk_freq) + pll.create_clkout(self.cd_idelay, 200e6) + platform.add_false_path_constraints(self.cd_sys.clk, pll.clkin) # Ignore sys_clk to pll.clkin path created by SoC's rst. + + self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_idelay) + +def _to_signal(obj): + return obj.raw_bits() if isinstance(obj, Record) else obj + +class BaseSoC(SoCCore): + + def __init__(self, sys_clk_freq=int(50e6), + with_analyzer=False, + uart_baudrate=115200, + **kwargs): + + coreUART = True + #romSize = 128*1024 + #ramSize = 128*1024 + romSize = 64 * 1024; + ramSize = 64 * 1024; + ddrSize = 16*1024*1024 + + + # try build using different fpga's + platform = cmod7.Platform() + #platform = cmod7.Platform(fpga='xc7a200t-SBG484-1') # arty-200 + #platform = cmod7_kintex.Platform(fpga='xc7k325t-ffv676-1 ) # kintex-325 + #platform = cmod7_kintex.Platform(fpga='xc7k410t-ffv676-1') # kintex-410 + + SoCCore.__init__(self, platform, sys_clk_freq, csr_data_width=32, + #with_uart=coreUART, integrated_rom_size=romSize, integrated_sram_size=ramSize, don't set rom/ram if doing it below!!!!! + with_uart=coreUART, integrated_rom_size=0, integrated_sram_size=0, + ident='A2P', ident_version=True, uart_baudrate=uart_baudrate, + cpu_type='a2p', cpu_variant='WB') + + print(f'Building variant={self.cpu.variant}.') + + # no irq yet, but should be able to connect; need irq handler in crt0.s + self.add_constant('UART_POLLING') + # skip bios crc for sim + #self.add_constant('CONFIG_BIOS_NO_CRC') # doesnt work? + #self.add_config("BIOS_NO_CRC") # doesnt work? + #had to -DCONFIG_BIOS_NO_CRC=1 in GCC_FLAGS + + # this appears to be how to set up fixed csr order but not sure it works this way. https://github.com/litex-hub/linux-on-litex-vexriscv/blob/master/soc_linux.py + #SoCCore.csr_map + #self.csr_map = {**SoCCore.csr_map, **{ + #self.csr_map = { + # 'ctrl': 0, + # 'dna' : 1, + # 'uart': 2, + # 'i2c': 3, + # 'leds': 4 + #}} + #interrupt_map = {**soc_cls.interrupt_map, **{ + # 'uart': 0, + # 'timer0': 1, + #}} + self.mem_map = { + 'rom': 0x00000000, + 'ram': 0x00010000, + 'main_ram': 0x01000000, + 'csr': 0xFFF00000 + } + + # CRG -------------------------------------------------------------------------------------- + self.submodules.crg = _CRG(platform, sys_clk_freq) + + if not coreUART: + self.submodules.serial_bridge = UARTWishboneBridge(platform.request('serial'), sys_clk_freq) + self.add_wb_master(self.serial_bridge.wishbone) + + self.add_csr('node_ctl') + self.add_csr('node_config') + self.add_csr('node_status') + + # ON-BOARD MEM ------------------------------------------------------------------------------ + + with open('rom.init', 'r') as file: + hexdata = file.read().replace('\n', '') + + #a2o how will this work for a2o? should allow 32BE or 64LE to load kernel+bios + # 1. core resets to 32BE + # 2. probably want to link kernel+bios in same mode, so have kernel deal with possible mode switch + # 3. load mem here in proper mode based on variant (A2O_32BE or A2O64_LE) + + outFile = open('mem_init', 'w') # write data immediately so available even if not building (sim) + # this seems to work (specified in BE in rom.init, instructions are decoded properly) + # BUT, vivado wants each line to be 4B to match width (at least for sim) + bytedata = [] + for i in range(0, len(hexdata), 8): + data = int(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2], 16) # BE->LE + bytedata.append(data) + outFile.write(hexdata[i+6:i+8] + hexdata[i+4:i+6] + hexdata[i+2:i+4] + hexdata[i:i+2] + '\n') + #bytedata.append(int(hexdata[i:i+2] + hexdata[i+2:i+4] + hexdata[i+4:i+6] + hexdata[i+6:i+8], 16)) + romdata = bytedata + print('Read ' + str(len(romdata)) + ' bytes for ROM data.') + outFile.close() + print('Wrote mem.init') + + self.add_rom('rom', origin=self.mem_map['rom'], size=romSize, contents=romdata) # name, origin, size, contents=[], mode='r' + # make this sram to match what linker expects + self.add_ram('sram', origin=self.mem_map['ram'], size=ramSize) # name, origin, size, contents=[], mode='rw' + + # External Mem ----------------------------------------------------------------------------- + self.add_ram('main_ram', origin=self.mem_map['main_ram'], size=ddrSize) + + # Leds ------------------------------------------------------------------------------------- + self.submodules.leds = LedChaser( + pads = platform.request_all('user_led'), + sys_clk_freq = sys_clk_freq + ) + self.add_csr('leds') + + # Buttons + self.submodules.buttons = GPIOIn( + pads = platform.request_all('user_btn') + ) + self.add_csr('buttons') + + # Analyzer --------------------------------------------------------------------------------- + if with_analyzer: + analyzer_signals = [ + self.cpu.wb_stb, + self.cpu.wb_cyc, + self.cpu.wb_adr, + self.cpu.wb_we, + self.cpu.wb_ack, + self.cpu.wb_sel, + self.cpu.wb_datw, + self.cpu.wb.datr, + ] + self.submodules.analyzer = LiteScopeAnalyzer(analyzer_signals, + depth = 512, + clock_domain = 'sys', + csr_csv = 'analyzer.csv') + self.add_csr('analyzer') + + + +# Build -------------------------------------------------------------------------------------------- + +def main(): + + parser = argparse.ArgumentParser(description='A2O Test') + parser.add_argument('--build', action='store_true', help='Build bitstream') + parser.add_argument('--load', action='store_true', help='Load bitstream') + parser.add_argument('--sys-clk-freq', default=100e6, help='System clock frequency (default: 100MHz)') + parser.add_argument('--with-analyzer', action='store_true', help='Include analyzer') + + builder_args(parser) + args = parser.parse_args() + + soc = BaseSoC( + sys_clk_freq = int(float(args.sys_clk_freq)), + with_analyzer = args.with_analyzer, + ) + + builder = Builder(soc, **builder_argdict(args)) + builder.build(run=args.build) + +if __name__ == '__main__': + main() diff --git a/build/litex/a2p_new/__init__.py b/build/litex/a2p_new/__init__.py new file mode 100644 index 0000000..a06708a --- /dev/null +++ b/build/litex/a2p_new/__init__.py @@ -0,0 +1 @@ +from .core import A2P \ No newline at end of file diff --git a/build/litex/a2p_new/boot-helper.S b/build/litex/a2p_new/boot-helper.S new file mode 100644 index 0000000..bc4863f --- /dev/null +++ b/build/litex/a2p_new/boot-helper.S @@ -0,0 +1,50 @@ +.section .text, "ax", @progbits +# called by bios boot commands to do the jump to code (r1,r2,r3 can be specified in terminal 'boot' command) + +.include "defines.s" + +.global boot_helper +# extern void boot_helper(unsigned long r1, unsigned long r2, unsigned long r3, unsigned long addr); + +.align 4 +boot_helper: + lis r3,_fstack@h + ori r3,r3,_fstack@l # top o mem + mtctr r6 + bctr # jump to callee + + # play with stack. what could go wrong? + # r1 = new top + # orig lr 20(r1) + # ancient r1 16(r1) + # local1 12(r1) + # local2 8(r1) + # (next lr) 4(r1) + # orig r1 0(r1) + # doesnt help...getting a bad op, probably blr to wrong address off stack, within calls to do a putchar + stwu r1,-32(r1) + mflr r0 + stw r0,36(r1) + stw r3,8(r1) + stw r4,12(r1) + stw r5,16(r1) + stw r6,20(r1) + li r3,'w' + slwi r3,r3,8 + ori r3,r3,'t' + slwi r3,r3,8 + ori r3,r3,'f' + slwi r3,r3,8 + ori r3,r3,'!' + stw r3,24(r1) + stw r3,28(r1) + lwz r0,36(r1) + mtlr r6 + addi r1,r1,32 + blr + + #addi r1,r1,32 # leave frame on stack + #mtctr r6 + #bctrl # jump to callee + + b . diff --git a/build/litex/a2p_new/core.py b/build/litex/a2p_new/core.py new file mode 100644 index 0000000..43b271a --- /dev/null +++ b/build/litex/a2p_new/core.py @@ -0,0 +1,150 @@ +# + +import os + +from migen import * + +from litex import get_data_mod +from litex.soc.interconnect import wishbone +from litex.soc.interconnect.csr import * +from litex.soc.cores.cpu import CPU + +dir = os.path.dirname(os.path.realpath(__file__)) + +# these select the top RTL file for each variant name +CPU_VARIANTS = { + 'WB': 'A2P', + 'standard': 'A2P' #wtf litex does this as default +} + +GCC_FLAGS = { + 'WB' : '-m32 -mbig-endian -mno-multiple -msoft-float -fno-stack-protector -Xassembler -defsym -Xassembler BIOS_32=1' +} + +class A2P(CPU, AutoCSR): + name = 'a2p' + human_name = 'a2p' + variants = CPU_VARIANTS + + family = 'powerpc' + data_width = 32 + endianness = 'big' + gcc_triple = 'powerpc-linux-gnu' + linker_output_format = 'elf32-powerpc' + + nop = 'nop' + io_regions = {0x80000000: 0x80000000} # origin, length + + @property + def mem_map(self): + return { + 'rom': 0x00000000, + 'sram': 0x00004000, + 'main_ram': 0x40000000, + 'csr': 0xf0000000, + } + + @property + def gcc_flags(self): + flags = GCC_FLAGS[self.variant] + flags += ' -D__a2p__' + flags += ' -DCONFIG_BIOS_NO_BOOT=1 -DCONFIG_BIOS_NO_CRC=1 -DCONFIG_MAIN_RAM_INIT=1' #wtf skip crc and ram memtest for now! + return flags + + def __init__(self, platform, variant='WB'): + + if variant == 'standard': + variant = 'WB' + + self.platform = platform + self.variant = variant + self.human_name = 'a2p' + self.external_variant = None + self.reset = Signal() + self.interrupt = Signal(32) + self.interruptS = Signal() + self.ibus = ibus = wishbone.Interface() + self.dbus = dbus = wishbone.Interface() + self.periph_buses = [ibus, dbus] + self.memory_buses = [] + self.enableDebug = False + self.enableJTAG = False + self.externalResetVector = 0 + + # # # + + self.cpu_params = dict( + i_clk = ClockSignal(), + i_reset = ResetSignal() | self.reset, + + i_externalInterrupt = self.interrupt[0], + i_externalInterruptS = self.interruptS, + i_timerInterrupt = 0, + i_softwareInterrupt = 0, + + #wtf i guess you get these names from the Inteface() def - but what about other sigs? + o_iBusWB_ADR = ibus.adr, + o_iBusWB_DAT_MOSI = ibus.dat_w, + o_iBusWB_SEL = ibus.sel, + o_iBusWB_CYC = ibus.cyc, + o_iBusWB_STB = ibus.stb, + o_iBusWB_WE = ibus.we, + o_iBusWB_CTI = ibus.cti, + o_iBusWB_BTE = ibus.bte, + i_iBusWB_DAT_MISO = ibus.dat_r, + i_iBusWB_ACK = ibus.ack, + i_iBusWB_ERR = ibus.err, + + o_dBusWB_ADR = dbus.adr, + o_dBusWB_DAT_MOSI = dbus.dat_w, + o_dBusWB_SEL = dbus.sel, + o_dBusWB_CYC = dbus.cyc, + o_dBusWB_STB = dbus.stb, + o_dBusWB_WE = dbus.we, + o_dBusWB_CTI = dbus.cti, + o_dBusWB_BTE = dbus.bte, + i_dBusWB_DAT_MISO = dbus.dat_r, + i_dBusWB_ACK = dbus.ack, + i_dBusWB_ERR = dbus.err + ) + + self.cpu_params['i_externalResetVector'] = self.externalResetVector + + # these need to connect to top nets + if self.enableDebug: + self.cpu_params['i_debugReset'] = 0 + self.cpu_params['o_debug_resetOut'] = 0 + self.cpu_params['i_debug_bus_cmd_valid'] = 0 + self.cpu_params['i_debug_bus_cmd_ready'] = 0 + self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0 + self.cpu_params['i_debug_bus_cmd_payload_address'] = 0 + self.cpu_params['i_debug_bus_cmd_payload_data'] = 0 + self.cpu_params['o_debug_bus_rsp_data'] = 0 + + if self.enableJTAG: + self.cpu_params['i_jtag_tms'] = 0 + self.cpu_params['i_jtag_tck'] = 0 + self.cpu_params['i_jtag_tdi'] = 0 + self.cpu_params['o_jtag_tdo'] = 0 + + def set_reset_address(self, reset_address): + assert not hasattr(self, 'reset_address') + self.reset_address = reset_address + self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address)) + + @staticmethod + def add_sources(platform, variant='WB'): + cpu_filename = CPU_VARIANTS[variant] + '.v' + #vdir = get_data_mod('cpu', 'a2p').data_location + vdir = os.path.join(dir, 'verilog') + platform.add_source(os.path.join(vdir, cpu_filename)) + + def use_external_variant(self, variant_filename): + self.external_variant = True + self.platform.add_source(variant_filename) + + def do_finalize(self): + assert hasattr(self, 'reset_address') + if not self.external_variant: + self.add_sources(self.platform, self.variant) + self.specials += Instance('A2P', **self.cpu_params) diff --git a/build/litex/a2p_new/crt0.S b/build/litex/a2p_new/crt0.S new file mode 100644 index 0000000..e2f08f1 --- /dev/null +++ b/build/litex/a2p_new/crt0.S @@ -0,0 +1,261 @@ +.include "defines.s" + +.set DEBUG,1 + +.macro load32 rx,v + li \rx,0 + oris \rx,\rx,\v>>16 + ori \rx,\rx,\v&0x0000FFFF +.endm + +.macro load16swiz rx,v + li \rx,0 + ori \rx,\rx,(\v<<8)&0xFF00 + ori \rx,\rx,(\v>>8)&0x00FF +.endm + +.macro delayr rx + mtctr \rx + bdnz . +.endm + +.macro delay rx,v + li \rx,0 + oris \rx,\rx,\v>>16 + ori \rx,\rx,\v&0x0000FFFF + mtctr \rx + bdnz . +.endm + +.section .text + +.global _start + +.org 0x0000 + +_start: + b boot_start + +.set REGSAVE,0x04 +regsave: + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + .long 0 + +.org 0x0100 +int_100: + b . + +# mck +.align 8 +int_200: + b . + +# dsi +.align 8 +int_300: + b . + +# dseg +.align 7 +int_380: + b . + +# isi +.align 8 +int_400: + b . + +# iseg +.align 7 +int_480: + b . + +.ifndef DEBUG +# external +.align 8 +int_500: + b . + +# alignment +.align 8 +int_600: + b . + +# program +.align 8 +int_700: + b . + +# fp unavailable +.align 8 +int_800: + b . + +# dec +.align 8 +int_900: + b . + +# dec hyp +.align 7 +int_980: + b . + +# doorbell +.align 8 +int_C00: + b . + +# trace +.align 8 +int_D00: + b . + +# dsi hyp +.align 8 +int_E00: + b . + +# isi hyp +.align 5 +int_E20: + b . + +# emulation hyp +.align 5 +int_E40: + b . + +# maintenance hyp +.align 5 +int_E60: + b . + +# doorbell hyp +.align 5 +int_E80: + b . + +# virtualization hyp +.align 5 +int_EA0: + b . + +# reserved +.align 5 +int_EC0: + b . + +# reserved +.align 5 +int_EE0: + b . + +# perfmon +.align 5 +int_F00: + b . + +# vector unavailable +.align 5 +int_F20: + b . + +# vsx unavailable +.align 5 +int_F40: + b . + +# facility unavailable +.align 5 +int_F60: + b . + +# facility unavailable hyp +.align 5 +int_F80: + b . + +.endif + +# ------------------------------------------------------------------------------------------------------------------------------ +# init facilities and memories before blastoff +# + +.ifdef DEBUG +.org 0x4E4 # match up close to a2o version +.else +.org 0x1000 +.endif + +boot_start: + +rominit: + +######################################################################################################################################## +# VMA/LMA: copy .data, clear .bss + + # get the linker script symbols needed... + lis r1,_fdata_rom@h + ori r1,r1,_fdata_rom@l + lis r2,_fdata@h + ori r2,r2,_fdata@l + lis r3,_edata_rom@h + ori r3,r3,_edata_rom@l + lis r4,_fbss@h + ori r4,r4,_fbss@l + lis r5,_ebss@h + ori r5,r5,_ebss@l + + subf r9,r1,r3 + srwi. r9,r9,2 + beq romcopy_done + mtctr r9 + addi r1,r1,-4 + addi r2,r2,-4 + +romcopy: + lwzu r9,4(r1) + stwu r9,4(r2) + bdnz romcopy + +romcopy_done: + subf r9,r4,r5 + srwi. r9,r9,2 + beq romclear_done + + mtctr r9 + addi r4,r4,-4 + li r9,0 + +romclear: + stwu r9,4(r4) + bdnz romclear + +romclear_done: + +######################################################################################################################################## + +######################################################################################################################################## + +process_start: + +jump2main: + lis r1,_fstack@h + ori r1,r1,_fstack@l + addi r1,r1,-16 + li r3, 0 # parm 1 + b main + + +.align 4 +.ifdef BIOS_32 +.include "crtsavres.s" +.endif + diff --git a/build/litex/a2p_new/crtsavres.s b/build/litex/a2p_new/crtsavres.s new file mode 100644 index 0000000..3d3e6f0 --- /dev/null +++ b/build/litex/a2p_new/crtsavres.s @@ -0,0 +1,129 @@ +# save/restore for 32b libc + +.macro GLOBAL n + .type \n,@function + .global \n +\n: +.endm + +# saves + +GLOBAL _savegpr_16 + stw 16,-64(11) + +GLOBAL _savegpr_17 + stw 17,-60(11) + +GLOBAL _savegpr_18 + stw 18,-56(11) + +GLOBAL _savegpr_19 + stw 19,-52(11) + +GLOBAL _savegpr_20 + stw 20,-48(11) + +GLOBAL _savegpr_21 + stw 21,-44(11) + +GLOBAL _savegpr_22 + stw 22,-40(11) + +GLOBAL _savegpr_23 + stw 23,-36(11) + +GLOBAL _savegpr_24 + stw 24,-32(11) + +GLOBAL _savegpr_25 + stw 25,-28(11) + +GLOBAL _savegpr_26 + stw 26,-24(11) + +GLOBAL _savegpr_27 + stw 27,-20(11) + +GLOBAL _savegpr_28 + stw 28,-16(11) + +GLOBAL _savegpr_29 + stw 29,-12(11) + +GLOBAL _savegpr_30 + stw 30,-8(11) + +GLOBAL _savegpr_31 + stw 31,-4(11) + blr + +# restores + +GLOBAL _restgpr_16_x +GLOBAL _rest32gpr_16_x + lwz 16,-64(11) + +GLOBAL _restgpr_17_x +GLOBAL _rest32gpr_17_x + lwz 17,-60(11) + +GLOBAL _restgpr_18_x +GLOBAL _rest32gpr_18_x + lwz 18,-56(11) + +GLOBAL _restgpr_19_x +GLOBAL _rest32gpr_19_x + lwz 19,-52(11) + +GLOBAL _restgpr_20_x +GLOBAL _rest32gpr_20_x + lwz 20,-48(11) + +GLOBAL _restgpr_21_x +GLOBAL _rest32gpr_21_x + lwz 21,-44(11) + +GLOBAL _restgpr_22_x +GLOBAL _rest32gpr_22_x + lwz 22,-40(11) + +GLOBAL _restgpr_23_x +GLOBAL _rest32gpr_23_x + lwz 23,-36(11) + +GLOBAL _restgpr_24_x +GLOBAL _rest32gpr_24_x + lwz 24,-32(11) + +GLOBAL _restgpr_25_x +GLOBAL _rest32gpr_25_x + lwz 25,-28(11) + +GLOBAL _restgpr_26_x +GLOBAL _rest32gpr_26_x + lwz 26,-24(11) + +GLOBAL _restgpr_27_x +GLOBAL _rest32gpr_27_x + lwz 27,-20(11) + +GLOBAL _restgpr_28_x +GLOBAL _rest32gpr_28_x + lwz 28,-16(11) + +GLOBAL _restgpr_29_x +GLOBAL _rest32gpr_29_x + lwz 29,-12(11) + +GLOBAL _restgpr_30_x +GLOBAL _rest32gpr_30_x + lwz 30,-8(11) + +GLOBAL _restgpr_31_x +GLOBAL _rest32gpr_31_x + lwz 0,4(11) + lwz 31,-4(11) + mtlr 0 + mr 1,11 + blr + diff --git a/build/litex/a2p_new/defines.s b/build/litex/a2p_new/defines.s new file mode 100644 index 0000000..9a8275d --- /dev/null +++ b/build/litex/a2p_new/defines.s @@ -0,0 +1,146 @@ +# © IBM Corp. 2020 +# Licensed under and subject to the terms of the CC-BY 4.0 +# license (https://creativecommons.org/licenses/by/4.0/legalcode). +# Additional rights, including the right to physically implement a softcore +# that is compliant with the required sections of the Power ISA +# Specification, will be available at no cost via the OpenPOWER Foundation. +# This README will be updated with additional information when OpenPOWER's +# license is available. + +#----------------------------------------- +# Defines +#----------------------------------------- + +# Regs + +.set r0, 0 +.set r1, 1 +.set r2, 2 +.set r3, 3 +.set r4, 4 +.set r5, 5 +.set r6, 6 +.set r7, 7 +.set r8, 8 +.set r9, 9 +.set r10,10 +.set r11,11 +.set r12,12 +.set r13,13 +.set r14,14 +.set r15,15 +.set r16,16 +.set r17,17 +.set r18,18 +.set r19,19 +.set r20,20 +.set r21,21 +.set r22,22 +.set r23,23 +.set r24,24 +.set r25,25 +.set r26,26 +.set r27,27 +.set r28,28 +.set r29,29 +.set r30,30 +.set r31,31 + +.set f0, 0 +.set f1, 1 +.set f2, 2 +.set f3, 3 +.set f4, 4 +.set f5, 5 +.set f6, 6 +.set f7, 7 +.set f8, 8 +.set f9, 9 +.set f10,10 +.set f11,11 +.set f12,12 +.set f13,13 +.set f14,14 +.set f15,15 +.set f16,16 +.set f17,17 +.set f18,18 +.set f19,19 +.set f20,20 +.set f21,21 +.set f22,22 +.set f23,23 +.set f24,24 +.set f25,25 +.set f26,26 +.set f27,27 +.set f28,28 +.set f29,29 +.set f30,30 +.set f31,31 + +.set cr0, 0 +.set cr1, 1 +.set cr2, 2 +.set cr3, 3 +.set cr4, 4 +.set cr5, 5 +.set cr6, 6 +.set cr7, 7 + +# SPR numbers + +.set srr0, 26 +.set srr1, 27 +.set epcr, 307 +.set tar, 815 +.set dsisr, 18 +.set dar, 19 + +.set dbsr, 304 +.set dbcr0, 308 +.set dbcr1, 309 +.set dbcr2, 310 +.set dbcr3, 848 + +.set ivpr, 63 + +.set iucr0, 1011 +.set iucr1, 883 +.set iucr2, 884 + +.set iudbg0, 888 +.set iudbg1, 889 +.set iudbg2, 890 +.set iulfsr, 891 +.set iullcr, 892 + +.set mmucr0, 1020 +.set mmucr1, 1021 +.set mmucr2, 1022 +.set mmucr3, 1023 + +.set tb, 268 +.set tbl, 284 +.set tbh, 285 + +.set dec, 22 +.set udec, 550 +.set tsr, 336 +.set tcr, 340 + +.set xucr0, 1014 +.set xucr1, 851 +.set xucr2, 1016 +.set xucr3, 852 +.set xucr4, 853 + +.set tens, 438 +.set tenc, 439 +.set tensr, 437 + +.set pid, 48 +.set pir, 286 +.set pvr, 287 +.set tir, 446 + diff --git a/build/litex/a2p_new/irq.h b/build/litex/a2p_new/irq.h new file mode 100644 index 0000000..aa99301 --- /dev/null +++ b/build/litex/a2p_new/irq.h @@ -0,0 +1,18 @@ +#ifndef __IRQ_H +#define __IRQ_H + +static inline void irq_setmask(unsigned int mask) { +} + +static inline unsigned int irq_getmask(void) { + return 0; +} + +static inline unsigned int irq_pending(void) { + return 0; +} + +static inline void irq_setie(unsigned int mask) { +} + +#endif \ No newline at end of file diff --git a/build/litex/a2p_new/system.h b/build/litex/a2p_new/system.h new file mode 100644 index 0000000..0a8fbe3 --- /dev/null +++ b/build/litex/a2p_new/system.h @@ -0,0 +1,67 @@ +// a2p +// changed to NOT + +#ifndef __SYSTEM_H +#define __SYSTEM_H + +#include + +/* +void flush_l2_cache(void) { +} +*/ +static void flush_cpu_icache(void); +static void flush_cpu_dcache(void); + +static void flush_cpu_icache(void) { +} +static void flush_cpu_dcache(void) { +} + + +/* CSRs are stored in subregister slices of CONFIG_CSR_DATA_WIDTH (native + * endianness), with the least significant slice at the lowest aligned + * (base) address. */ + +/* CSR subregisters (a.k.a. "simple CSRs") are embedded inside uint32_t + * aligned locations: */ + +/* +#define CSR_ACCESSORS_DEFINED + + +#ifdef __ASSEMBLER__ +#define MMPTR(x) x +#else + +#include +#if !defined(CONFIG_CSR_DATA_WIDTH) +#error CSR_DATA_WIDTH MUST be set before including this file! +#endif + +#define MMPTR(a) (*((volatile uint32_t *)(a))) + +static inline unsigned long swizzle(unsigned long v); + +static inline unsigned long swizzle(unsigned long v) { + //return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24); + return v; +} + +static inline void csr_write_simple(unsigned long v, unsigned long a) +{ + //MMPTR(a) = v; + MMPTR(a) = swizzle(v); +} + +static inline unsigned long csr_read_simple(unsigned long a) +{ + //return MMPTR(a); + return swizzle(MMPTR(a)); +} + +#endif +*/ + +#endif /* __SYSTEM_H */ + diff --git a/build/litex/a2p_new/verilog/A2P_WB.v b/build/litex/a2p_new/verilog/A2P_WB.v new file mode 100644 index 0000000..751355c --- /dev/null +++ b/build/litex/a2p_new/verilog/A2P_WB.v @@ -0,0 +1,14250 @@ +// Generator : SpinalHDL v1.4.0 git head : ecb5a80b713566f417ea3ea061f9969e73770a7f +// Date : 27/08/2022, 10:55:10 +// Component : A2P_4K1W + + +`define TgtCtrlEnum_defaultEncoding_type [0:0] +`define TgtCtrlEnum_defaultEncoding_RT 1'b0 +`define TgtCtrlEnum_defaultEncoding_RA 1'b1 + +`define Src1CtrlEnum_defaultEncoding_type [2:0] +`define Src1CtrlEnum_defaultEncoding_RA 3'b000 +`define Src1CtrlEnum_defaultEncoding_RA_N 3'b001 +`define Src1CtrlEnum_defaultEncoding_RA_NIA 3'b010 +`define Src1CtrlEnum_defaultEncoding_RA_0 3'b011 +`define Src1CtrlEnum_defaultEncoding_RS 3'b100 + +`define Src2CtrlEnum_defaultEncoding_type [2:0] +`define Src2CtrlEnum_defaultEncoding_RB 3'b000 +`define Src2CtrlEnum_defaultEncoding_RB_0 3'b001 +`define Src2CtrlEnum_defaultEncoding_RB_M1 3'b010 +`define Src2CtrlEnum_defaultEncoding_RB_UI 3'b011 +`define Src2CtrlEnum_defaultEncoding_RB_SI 3'b100 +`define Src2CtrlEnum_defaultEncoding_RB_SH 3'b101 +`define Src2CtrlEnum_defaultEncoding_RB_PCISD 3'b110 +`define Src2CtrlEnum_defaultEncoding_RA 3'b111 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD 2'b00 +`define AluCtrlEnum_defaultEncoding_BIT_1 2'b01 +`define AluCtrlEnum_defaultEncoding_RIMI 2'b10 +`define AluCtrlEnum_defaultEncoding_SPEC 2'b11 + +`define Src3CtrlEnum_defaultEncoding_type [1:0] +`define Src3CtrlEnum_defaultEncoding_CA 2'b00 +`define Src3CtrlEnum_defaultEncoding_CA_0 2'b01 +`define Src3CtrlEnum_defaultEncoding_CA_1 2'b10 + +`define DataSizeEnum_defaultEncoding_type [1:0] +`define DataSizeEnum_defaultEncoding_B 2'b00 +`define DataSizeEnum_defaultEncoding_H 2'b01 +`define DataSizeEnum_defaultEncoding_HA 2'b10 +`define DataSizeEnum_defaultEncoding_W 2'b11 + +`define CRMoveCtrlEnum_defaultEncoding_type [1:0] +`define CRMoveCtrlEnum_defaultEncoding_MCRF 2'b00 +`define CRMoveCtrlEnum_defaultEncoding_MCRXRX 2'b01 +`define CRMoveCtrlEnum_defaultEncoding_MTCRF 2'b10 + +`define EndianEnum_defaultEncoding_type [0:0] +`define EndianEnum_defaultEncoding_BE 1'b0 +`define EndianEnum_defaultEncoding_LE 1'b1 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [3:0] +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 4'b0000 +`define AluBitwiseCtrlEnum_defaultEncoding_ANDC 4'b0001 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 4'b0010 +`define AluBitwiseCtrlEnum_defaultEncoding_ORC 4'b0011 +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 4'b0100 +`define AluBitwiseCtrlEnum_defaultEncoding_XORC 4'b0101 +`define AluBitwiseCtrlEnum_defaultEncoding_EQV 4'b0110 +`define AluBitwiseCtrlEnum_defaultEncoding_NAND_1 4'b0111 +`define AluBitwiseCtrlEnum_defaultEncoding_NOR_1 4'b1000 +`define AluBitwiseCtrlEnum_defaultEncoding_EXTSB 4'b1001 +`define AluBitwiseCtrlEnum_defaultEncoding_EXTSH 4'b1010 + +`define CRBusCmdEnum_defaultEncoding_type [4:0] +`define CRBusCmdEnum_defaultEncoding_NOP 5'b00000 +`define CRBusCmdEnum_defaultEncoding_CR0 5'b00001 +`define CRBusCmdEnum_defaultEncoding_CR1 5'b00010 +`define CRBusCmdEnum_defaultEncoding_CR6 5'b00011 +`define CRBusCmdEnum_defaultEncoding_CMP 5'b00100 +`define CRBusCmdEnum_defaultEncoding_AND_1 5'b00101 +`define CRBusCmdEnum_defaultEncoding_OR_1 5'b00110 +`define CRBusCmdEnum_defaultEncoding_XOR_1 5'b00111 +`define CRBusCmdEnum_defaultEncoding_NAND_1 5'b01000 +`define CRBusCmdEnum_defaultEncoding_NOR_1 5'b01001 +`define CRBusCmdEnum_defaultEncoding_EQV 5'b01010 +`define CRBusCmdEnum_defaultEncoding_ANDC 5'b01011 +`define CRBusCmdEnum_defaultEncoding_ORC 5'b01100 +`define CRBusCmdEnum_defaultEncoding_MCRF 5'b01101 +`define CRBusCmdEnum_defaultEncoding_MCRXRX 5'b01110 +`define CRBusCmdEnum_defaultEncoding_MTOCRF 5'b01111 +`define CRBusCmdEnum_defaultEncoding_MTCRF 5'b10000 +`define CRBusCmdEnum_defaultEncoding_DEC 5'b10001 +`define CRBusCmdEnum_defaultEncoding_LNK 5'b10010 +`define CRBusCmdEnum_defaultEncoding_DECLNK 5'b10011 + +`define AluSpecCtrlEnum_defaultEncoding_type [2:0] +`define AluSpecCtrlEnum_defaultEncoding_CNTLZW 3'b000 +`define AluSpecCtrlEnum_defaultEncoding_CNTTZW 3'b001 +`define AluSpecCtrlEnum_defaultEncoding_POPCNTB 3'b010 +`define AluSpecCtrlEnum_defaultEncoding_POPCNTW 3'b011 +`define AluSpecCtrlEnum_defaultEncoding_CMPB 3'b100 +`define AluSpecCtrlEnum_defaultEncoding_PRTYW 3'b101 + +`define AluRimiCtrlEnum_defaultEncoding_type [2:0] +`define AluRimiCtrlEnum_defaultEncoding_ROT 3'b000 +`define AluRimiCtrlEnum_defaultEncoding_INS 3'b001 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTL 3'b010 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTR 3'b011 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTRA 3'b100 + +`define CRLogCtrlEnum_defaultEncoding_type [2:0] +`define CRLogCtrlEnum_defaultEncoding_AND_1 3'b000 +`define CRLogCtrlEnum_defaultEncoding_OR_1 3'b001 +`define CRLogCtrlEnum_defaultEncoding_XOR_1 3'b010 +`define CRLogCtrlEnum_defaultEncoding_NAND_1 3'b011 +`define CRLogCtrlEnum_defaultEncoding_NOR_1 3'b100 +`define CRLogCtrlEnum_defaultEncoding_EQV 3'b101 +`define CRLogCtrlEnum_defaultEncoding_ANDC 3'b110 +`define CRLogCtrlEnum_defaultEncoding_ORC 3'b111 + +`define BranchCtrlEnum_defaultEncoding_type [2:0] +`define BranchCtrlEnum_defaultEncoding_NONE 3'b000 +`define BranchCtrlEnum_defaultEncoding_BU 3'b001 +`define BranchCtrlEnum_defaultEncoding_BC 3'b010 +`define BranchCtrlEnum_defaultEncoding_BCLR 3'b011 +`define BranchCtrlEnum_defaultEncoding_BCCTR 3'b100 +`define BranchCtrlEnum_defaultEncoding_BCTAR 3'b101 + +`define EnvCtrlEnum_defaultEncoding_type [3:0] +`define EnvCtrlEnum_defaultEncoding_NONE 4'b0000 +`define EnvCtrlEnum_defaultEncoding_MFMSR 4'b0001 +`define EnvCtrlEnum_defaultEncoding_MTMSR 4'b0010 +`define EnvCtrlEnum_defaultEncoding_SC 4'b0011 +`define EnvCtrlEnum_defaultEncoding_SCV 4'b0100 +`define EnvCtrlEnum_defaultEncoding_RFI 4'b0101 +`define EnvCtrlEnum_defaultEncoding_RFSCV 4'b0110 +`define EnvCtrlEnum_defaultEncoding_TW 4'b0111 +`define EnvCtrlEnum_defaultEncoding_TWI 4'b1000 + +`define AluRimiAmtEnum_defaultEncoding_type [0:0] +`define AluRimiAmtEnum_defaultEncoding_IMM 1'b0 +`define AluRimiAmtEnum_defaultEncoding_RB 1'b1 + +`define ExcpEnum_defaultEncoding_type [4:0] +`define ExcpEnum_defaultEncoding_NONE 5'b00000 +`define ExcpEnum_defaultEncoding_SC 5'b00001 +`define ExcpEnum_defaultEncoding_SCV 5'b00010 +`define ExcpEnum_defaultEncoding_TRAP 5'b00011 +`define ExcpEnum_defaultEncoding_RFI 5'b00100 +`define ExcpEnum_defaultEncoding_RFSCV 5'b00101 +`define ExcpEnum_defaultEncoding_DSI 5'b00110 +`define ExcpEnum_defaultEncoding_DSI_PROT 5'b00111 +`define ExcpEnum_defaultEncoding_DSS 5'b01000 +`define ExcpEnum_defaultEncoding_ISI 5'b01001 +`define ExcpEnum_defaultEncoding_ISI_PROT 5'b01010 +`define ExcpEnum_defaultEncoding_ISS 5'b01011 +`define ExcpEnum_defaultEncoding_ALG 5'b01100 +`define ExcpEnum_defaultEncoding_PGM_ILL 5'b01101 +`define ExcpEnum_defaultEncoding_PGM_PRV 5'b01110 +`define ExcpEnum_defaultEncoding_FP 5'b01111 +`define ExcpEnum_defaultEncoding_VEC 5'b10000 +`define ExcpEnum_defaultEncoding_VSX 5'b10001 +`define ExcpEnum_defaultEncoding_FAC 5'b10010 +`define ExcpEnum_defaultEncoding_SR 5'b10011 +`define ExcpEnum_defaultEncoding_MC 5'b10100 +`define ExcpEnum_defaultEncoding_EXT 5'b10101 +`define ExcpEnum_defaultEncoding_DEC 5'b10110 +`define ExcpEnum_defaultEncoding_TR 5'b10111 +`define ExcpEnum_defaultEncoding_PM 5'b11000 + + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_spr_valid, + output [9:0] io_cpu_fetch_mmuBus_spr_payload_id, + output [31:0] io_cpu_fetch_mmuBus_spr_payload_data, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output [3:0] io_cpu_fetch_exceptionType, + input io_cpu_fetch_bypassTranslation, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + output [3:0] io_cpu_decode_exceptionType, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_spr_valid, + input [9:0] io_spr_payload_id, + input [31:0] io_spr_payload_data, + input clk, + input reset +); + reg [21:0] _zz_11_; + reg [31:0] _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [21:0] _zz_17_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + (* syn_keep , keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* syn_keep , keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [6:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_7_; + wire [9:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [19:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + reg [31:0] _zz_10_; + wire [31:0] decodeStage_hit_data; + wire decodeStage_protError; + reg [21:0] ways_0_tags [0:127]; + reg [31:0] ways_0_datas [0:1023]; + + assign _zz_13_ = (! lineLoader_flushCounter[7]); + assign _zz_14_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15_ = _zz_7_[0 : 0]; + assign _zz_16_ = _zz_7_[1 : 1]; + assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_11_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_12_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_11_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_12_; + assign io_cpu_fetch_data = fetchStage_read_waysValues_0_data; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = io_cpu_fetch_bypassTranslation; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_mmuBus_spr_valid = io_spr_valid; + assign io_cpu_fetch_mmuBus_spr_payload_id = io_spr_payload_id; + assign io_cpu_fetch_mmuBus_spr_payload_data = io_spr_payload_data; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 12])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); + assign decodeStage_hit_data = _zz_10_; + assign io_cpu_decode_data = decodeStage_hit_data; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_tags_0_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_exception); + assign decodeStage_protError = (io_cpu_decode_isValid && ((! decodeStage_mmuRsp_refilling) && ((! decodeStage_mmuRsp_allowRead) || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_exceptionType = {{{decodeStage_mmuRsp_allowRead,decodeStage_mmuRsp_allowWrite},decodeStage_mmuRsp_allowExecute},decodeStage_protError}; + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk or posedge reset) begin + if (reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3_ <= lineLoader_flushCounter[7]; + if(_zz_14_)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_10_ <= fetchStage_read_waysValues_0_data; + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + input io_cpu_memory_isRemoved, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + output io_cpu_memory_mmuBus_cmd_isValid, + output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, + output io_cpu_memory_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, + input io_cpu_memory_mmuBus_rsp_isIoAccess, + input io_cpu_memory_mmuBus_rsp_allowRead, + input io_cpu_memory_mmuBus_rsp_allowWrite, + input io_cpu_memory_mmuBus_rsp_allowExecute, + input io_cpu_memory_mmuBus_rsp_exception, + input io_cpu_memory_mmuBus_rsp_refilling, + output io_cpu_memory_mmuBus_spr_valid, + output [9:0] io_cpu_memory_mmuBus_spr_payload_id, + output [31:0] io_cpu_memory_mmuBus_spr_payload_data, + output io_cpu_memory_mmuBus_end, + input io_cpu_memory_mmuBus_busy, + input io_cpu_memory_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output [3:0] io_cpu_writeBack_exceptionType, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output reg io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire _zz_15_; + wire _zz_16_; + wire [0:0] _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [2:0] _zz_20_; + wire [1:0] _zz_21_; + wire [21:0] _zz_22_; + reg _zz_1_; + reg _zz_2_; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3_; + wire DC_DIR_tagsReadRsp_valid; + wire DC_DIR_tagsReadRsp_error; + wire [19:0] DC_DIR_tagsReadRsp_address; + wire [21:0] _zz_4_; + wire _zz_5_; + wire [31:0] DC_DIR_dataReadRsp; + reg [3:0] _zz_6_; + wire [3:0] stage0_mask; + wire [0:0] stage0_colisions; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg [3:0] stageA_mask; + wire stageA_wayHits_0; + reg [0:0] stage0_colisions_regNextWhen; + wire [0:0] _zz_7_; + wire [0:0] stageA_colisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + wire [0:0] _zz_8_; + reg [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg [0:0] stageB_colisions; + reg stageB_loaderValid; + reg stageB_flusher_valid; + reg stageB_flusher_start; + wire [31:0] stageB_requestDataBypass; + wire stageB_isAmo; + reg stageB_memCmdSent; + wire stageB_protError; + wire [0:0] _zz_9_; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + reg [21:0] DC_DIR_tags [0:127]; + reg [7:0] DC_DIR_data_symbol0 [0:1023]; + reg [7:0] DC_DIR_data_symbol1 [0:1023]; + reg [7:0] DC_DIR_data_symbol2 [0:1023]; + reg [7:0] DC_DIR_data_symbol3 [0:1023]; + reg [7:0] _zz_23_; + reg [7:0] _zz_24_; + reg [7:0] _zz_25_; + reg [7:0] _zz_26_; + + assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13_ = ((((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess) || stageB_protError); + assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); + assign _zz_15_ = (loader_valid && io_mem_rsp_valid); + assign _zz_16_ = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_17_ = _zz_4_[0 : 0]; + assign _zz_18_ = _zz_4_[1 : 1]; + assign _zz_19_ = loader_counter_willIncrement; + assign _zz_20_ = {2'd0, _zz_19_}; + assign _zz_21_ = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_22_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3_) begin + _zz_10_ <= DC_DIR_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2_) begin + DC_DIR_tags[tagsWriteCmd_payload_address] <= _zz_22_; + end + end + + always @ (*) begin + _zz_11_ = {_zz_26_, _zz_25_, _zz_24_, _zz_23_}; + end + always @ (posedge clk) begin + if(_zz_5_) begin + _zz_23_ <= DC_DIR_data_symbol0[dataReadCmd_payload]; + _zz_24_ <= DC_DIR_data_symbol1[dataReadCmd_payload]; + _zz_25_ <= DC_DIR_data_symbol2[dataReadCmd_payload]; + _zz_26_ <= DC_DIR_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1_) begin + DC_DIR_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1_) begin + DC_DIR_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1_) begin + DC_DIR_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1_) begin + DC_DIR_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2_ = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4_ = _zz_10_; + assign DC_DIR_tagsReadRsp_valid = _zz_17_[0]; + assign DC_DIR_tagsReadRsp_error = _zz_18_[0]; + assign DC_DIR_tagsReadRsp_address = _zz_4_[21 : 2]; + assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign DC_DIR_dataReadRsp = _zz_11_; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12_)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12_)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12_)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12_)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13_)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = (1'bx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = (1'b1); + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_15_)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = (1'bx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_data = stageB_requestDataBypass; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = (4'bxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_mask = stageB_mask; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_mask = (4'b1111); + end + end + + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6_ = (4'b1000); + end + 2'b01 : begin + _zz_6_ = (4'b1100); + end + default : begin + _zz_6_ = (4'b1111); + end + endcase + end + + assign stage0_mask = (_zz_6_ >>> io_cpu_execute_address[1 : 0]); + assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; + assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; + assign io_cpu_memory_mmuBus_cmd_bypassTranslation = io_cpu_memory_bypassTranslation; + assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); + assign io_cpu_memory_mmuBus_spr_valid = 1'b0; + assign io_cpu_memory_mmuBus_spr_payload_id = 10'h0; + assign io_cpu_memory_mmuBus_spr_payload_data = 32'h0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == DC_DIR_tagsReadRsp_address) && DC_DIR_tagsReadRsp_valid); + assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign _zz_8_[0] = stageA_wayHits_0; + assign stageB_waysHit = (stageB_waysHits != (1'b0)); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + if(_zz_13_)begin + stageB_loaderValid = 1'b0; + end + end + + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_14_)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + if(_zz_13_)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_requestDataBypass = stageB_request_data; + assign stageB_isAmo = 1'b0; + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin + io_cpu_redo = 1'b1; + end + end + end + end + if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && stageB_mmuRsp_exception); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + assign stageB_protError = (io_cpu_writeBack_isValid && ((! stageB_mmuRsp_refilling) && (((! stageB_mmuRsp_allowRead) && (! stageB_request_wr)) || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)))); + assign io_cpu_writeBack_exceptionType = {{{stageB_mmuRsp_allowRead,stageB_mmuRsp_allowWrite},stageB_mmuRsp_allowExecute},stageB_protError}; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_valid = (! stageB_memCmdSent); + end else begin + if(_zz_14_)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! stageB_memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = 32'h0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = (3'bxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + io_mem_cmd_payload_length = (3'b111); + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_last = 1'bx; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + io_mem_cmd_payload_last = 1'b1; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + always @ (*) begin + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_data = io_mem_rsp_payload_data; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9_[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_15_)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_20_); + if(loader_counter_willClear)begin + loader_counter_valueNext = (3'b000); + end + end + + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stage0_colisions_regNextWhen <= stage0_colisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= DC_DIR_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= DC_DIR_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= DC_DIR_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= DC_DIR_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHits <= _zz_8_; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_colisions <= stageA_colisions; + end + if(stageB_flusher_valid)begin + if(_zz_16_)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + end + + always @ (posedge clk or posedge reset) begin + if (reset) begin + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_memCmdSent <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= (3'b000); + loader_waysAllocator <= (1'b1); + loader_error <= 1'b0; + end else begin + if(stageB_flusher_valid)begin + if(! _zz_16_) begin + stageB_flusher_valid <= 1'b0; + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + if(io_mem_cmd_ready)begin + stageB_memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_memCmdSent <= 1'b0; + end + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(_zz_15_)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_counter_willOverflow)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_21_[0:0]; + end + end + end + + +endmodule + +module A2P_WB ( + input [31:0] externalResetVector, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input externalInterruptS, + output reg iBusWB_CYC /* verilator public */ , + output reg iBusWB_STB /* verilator public */ , + input iBusWB_ACK /* verilator public */ , + output iBusWB_WE /* verilator public */ , + output [29:0] iBusWB_ADR /* verilator public */ , + input [31:0] iBusWB_DAT_MISO /* verilator public */ , + output [31:0] iBusWB_DAT_MOSI /* verilator public */ , + output [3:0] iBusWB_SEL /* verilator public */ , + input iBusWB_ERR /* verilator public */ , + output [1:0] iBusWB_BTE /* verilator public */ , + output [2:0] iBusWB_CTI /* verilator public */ , + output dBusWB_CYC /* verilator public */ , + output dBusWB_STB /* verilator public */ , + input dBusWB_ACK /* verilator public */ , + output dBusWB_WE /* verilator public */ , + output [29:0] dBusWB_ADR /* verilator public */ , + input [31:0] dBusWB_DAT_MISO /* verilator public */ , + output [31:0] dBusWB_DAT_MOSI /* verilator public */ , + output [3:0] dBusWB_SEL /* verilator public */ , + input dBusWB_ERR /* verilator public */ , + output [1:0] dBusWB_BTE /* verilator public */ , + output [2:0] dBusWB_CTI /* verilator public */ , + input clk, + input reset +); + wire _zz_367_; + wire _zz_368_; + wire _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire _zz_372_; + wire _zz_373_; + wire _zz_374_; + reg _zz_375_; + wire [9:0] _zz_376_; + wire _zz_377_; + wire [31:0] _zz_378_; + reg [31:0] _zz_379_; + wire _zz_380_; + wire [31:0] _zz_381_; + reg _zz_382_; + wire _zz_383_; + wire _zz_384_; + wire _zz_385_; + wire [31:0] _zz_386_; + wire _zz_387_; + wire _zz_388_; + reg [53:0] _zz_389_; + reg [31:0] _zz_390_; + reg [31:0] _zz_391_; + reg [31:0] _zz_392_; + reg [31:0] _zz_393_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire [3:0] IBusCachedPlugin_cache_io_cpu_fetch_exceptionType; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid; + wire [9:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire [3:0] IBusCachedPlugin_cache_io_cpu_decode_exceptionType; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1__io_cpu_memory_isWrite; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + wire dataCache_1__io_cpu_memory_mmuBus_end; + wire dataCache_1__io_cpu_memory_mmuBus_spr_valid; + wire [9:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_id; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_data; + wire dataCache_1__io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1__io_cpu_writeBack_data; + wire dataCache_1__io_cpu_writeBack_mmuException; + wire dataCache_1__io_cpu_writeBack_unalignedAccess; + wire dataCache_1__io_cpu_writeBack_accessError; + wire dataCache_1__io_cpu_writeBack_isWrite; + wire [3:0] dataCache_1__io_cpu_writeBack_exceptionType; + wire dataCache_1__io_cpu_flush_ready; + wire dataCache_1__io_cpu_redo; + wire dataCache_1__io_mem_cmd_valid; + wire dataCache_1__io_mem_cmd_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_payload_length; + wire dataCache_1__io_mem_cmd_payload_last; + wire _zz_394_; + wire _zz_395_; + wire _zz_396_; + wire _zz_397_; + wire _zz_398_; + wire _zz_399_; + wire _zz_400_; + wire _zz_401_; + wire _zz_402_; + wire _zz_403_; + wire _zz_404_; + wire _zz_405_; + wire _zz_406_; + wire _zz_407_; + wire _zz_408_; + wire _zz_409_; + wire _zz_410_; + wire _zz_411_; + wire _zz_412_; + wire _zz_413_; + wire _zz_414_; + wire _zz_415_; + wire _zz_416_; + wire _zz_417_; + wire _zz_418_; + wire _zz_419_; + wire _zz_420_; + wire _zz_421_; + wire _zz_422_; + wire _zz_423_; + wire _zz_424_; + wire _zz_425_; + wire _zz_426_; + wire _zz_427_; + wire _zz_428_; + wire _zz_429_; + wire _zz_430_; + wire _zz_431_; + wire _zz_432_; + wire _zz_433_; + wire _zz_434_; + wire _zz_435_; + wire _zz_436_; + wire _zz_437_; + wire _zz_438_; + wire _zz_439_; + wire _zz_440_; + wire [7:0] _zz_441_; + wire [2:0] _zz_442_; + wire [2:0] _zz_443_; + wire [1:0] _zz_444_; + wire [1:0] _zz_445_; + wire [2:0] _zz_446_; + wire [0:0] _zz_447_; + wire [0:0] _zz_448_; + wire [0:0] _zz_449_; + wire [0:0] _zz_450_; + wire [0:0] _zz_451_; + wire [0:0] _zz_452_; + wire [0:0] _zz_453_; + wire [0:0] _zz_454_; + wire [0:0] _zz_455_; + wire [0:0] _zz_456_; + wire [0:0] _zz_457_; + wire [0:0] _zz_458_; + wire [0:0] _zz_459_; + wire [0:0] _zz_460_; + wire [0:0] _zz_461_; + wire [0:0] _zz_462_; + wire [0:0] _zz_463_; + wire [0:0] _zz_464_; + wire [0:0] _zz_465_; + wire [0:0] _zz_466_; + wire [0:0] _zz_467_; + wire [51:0] _zz_468_; + wire [51:0] _zz_469_; + wire [51:0] _zz_470_; + wire [32:0] _zz_471_; + wire [51:0] _zz_472_; + wire [49:0] _zz_473_; + wire [51:0] _zz_474_; + wire [49:0] _zz_475_; + wire [51:0] _zz_476_; + wire [0:0] _zz_477_; + wire [0:0] _zz_478_; + wire [0:0] _zz_479_; + wire [0:0] _zz_480_; + wire [0:0] _zz_481_; + wire [0:0] _zz_482_; + wire [0:0] _zz_483_; + wire [0:0] _zz_484_; + wire [0:0] _zz_485_; + wire [0:0] _zz_486_; + wire [0:0] _zz_487_; + wire [0:0] _zz_488_; + wire [0:0] _zz_489_; + wire [0:0] _zz_490_; + wire [0:0] _zz_491_; + wire [0:0] _zz_492_; + wire [0:0] _zz_493_; + wire [0:0] _zz_494_; + wire [0:0] _zz_495_; + wire [0:0] _zz_496_; + wire [0:0] _zz_497_; + wire [2:0] _zz_498_; + wire [2:0] _zz_499_; + wire [31:0] _zz_500_; + wire [9:0] _zz_501_; + wire [29:0] _zz_502_; + wire [9:0] _zz_503_; + wire [19:0] _zz_504_; + wire [1:0] _zz_505_; + wire [0:0] _zz_506_; + wire [1:0] _zz_507_; + wire [0:0] _zz_508_; + wire [1:0] _zz_509_; + wire [1:0] _zz_510_; + wire [0:0] _zz_511_; + wire [1:0] _zz_512_; + wire [0:0] _zz_513_; + wire [1:0] _zz_514_; + wire [2:0] _zz_515_; + wire [2:0] _zz_516_; + wire [10:0] _zz_517_; + wire [31:0] _zz_518_; + wire [10:0] _zz_519_; + wire [31:0] _zz_520_; + wire [31:0] _zz_521_; + wire [31:0] _zz_522_; + wire [31:0] _zz_523_; + wire [31:0] _zz_524_; + wire [31:0] _zz_525_; + wire [31:0] _zz_526_; + wire [5:0] _zz_527_; + wire [5:0] _zz_528_; + wire [31:0] _zz_529_; + wire [31:0] _zz_530_; + wire [31:0] _zz_531_; + wire [31:0] _zz_532_; + wire [31:0] _zz_533_; + wire [31:0] _zz_534_; + wire [31:0] _zz_535_; + wire [31:0] _zz_536_; + wire [31:0] _zz_537_; + wire [31:0] _zz_538_; + wire [31:0] _zz_539_; + wire [31:0] _zz_540_; + wire [31:0] _zz_541_; + wire [31:0] _zz_542_; + wire [31:0] _zz_543_; + wire [31:0] _zz_544_; + wire [31:0] _zz_545_; + wire [31:0] _zz_546_; + wire [31:0] _zz_547_; + wire [31:0] _zz_548_; + wire [31:0] _zz_549_; + wire [31:0] _zz_550_; + wire [31:0] _zz_551_; + wire [31:0] _zz_552_; + wire [31:0] _zz_553_; + wire [4:0] _zz_554_; + wire [2:0] _zz_555_; + wire [31:0] _zz_556_; + wire [31:0] _zz_557_; + wire [31:0] _zz_558_; + wire [32:0] _zz_559_; + wire [32:0] _zz_560_; + wire [31:0] _zz_561_; + wire [31:0] _zz_562_; + wire [65:0] _zz_563_; + wire [65:0] _zz_564_; + wire [31:0] _zz_565_; + wire [31:0] _zz_566_; + wire [0:0] _zz_567_; + wire [5:0] _zz_568_; + wire [32:0] _zz_569_; + wire [31:0] _zz_570_; + wire [31:0] _zz_571_; + wire [32:0] _zz_572_; + wire [32:0] _zz_573_; + wire [32:0] _zz_574_; + wire [32:0] _zz_575_; + wire [0:0] _zz_576_; + wire [32:0] _zz_577_; + wire [0:0] _zz_578_; + wire [32:0] _zz_579_; + wire [0:0] _zz_580_; + wire [31:0] _zz_581_; + wire [4:0] _zz_582_; + wire [4:0] _zz_583_; + wire [4:0] _zz_584_; + wire [4:0] _zz_585_; + wire [4:0] _zz_586_; + wire [4:0] _zz_587_; + wire [4:0] _zz_588_; + wire [4:0] _zz_589_; + wire [4:0] _zz_590_; + wire [4:0] _zz_591_; + wire [4:0] _zz_592_; + wire [4:0] _zz_593_; + wire [4:0] _zz_594_; + wire [4:0] _zz_595_; + wire [4:0] _zz_596_; + wire [4:0] _zz_597_; + wire [4:0] _zz_598_; + wire [4:0] _zz_599_; + wire [4:0] _zz_600_; + wire [4:0] _zz_601_; + wire [4:0] _zz_602_; + wire [4:0] _zz_603_; + wire [4:0] _zz_604_; + wire [4:0] _zz_605_; + wire [31:0] _zz_606_; + wire [31:0] _zz_607_; + wire [31:0] _zz_608_; + wire [31:0] _zz_609_; + wire [1:0] _zz_610_; + wire [4:0] _zz_611_; + wire [1:0] _zz_612_; + wire [4:0] _zz_613_; + wire [4:0] _zz_614_; + wire [1:0] _zz_615_; + wire [4:0] _zz_616_; + wire [4:0] _zz_617_; + wire [1:0] _zz_618_; + wire [4:0] _zz_619_; + wire [4:0] _zz_620_; + wire [1:0] _zz_621_; + wire [4:0] _zz_622_; + wire [3:0] _zz_623_; + wire [1:0] _zz_624_; + wire [3:0] _zz_625_; + wire [3:0] _zz_626_; + wire [1:0] _zz_627_; + wire [3:0] _zz_628_; + wire [2:0] _zz_629_; + wire [1:0] _zz_630_; + wire [2:0] _zz_631_; + wire [1:0] _zz_632_; + wire [1:0] _zz_633_; + wire [1:0] _zz_634_; + wire [1:0] _zz_635_; + wire [31:0] _zz_636_; + wire [31:0] _zz_637_; + wire [31:0] _zz_638_; + wire [31:0] _zz_639_; + wire [31:0] _zz_640_; + wire [31:0] _zz_641_; + wire [31:0] _zz_642_; + wire [31:0] _zz_643_; + wire [0:0] _zz_644_; + wire [0:0] _zz_645_; + wire [0:0] _zz_646_; + wire [0:0] _zz_647_; + wire [0:0] _zz_648_; + wire [0:0] _zz_649_; + wire [0:0] _zz_650_; + wire [0:0] _zz_651_; + wire [0:0] _zz_652_; + wire [0:0] _zz_653_; + wire [0:0] _zz_654_; + wire [0:0] _zz_655_; + wire [0:0] _zz_656_; + wire [26:0] _zz_657_; + wire [53:0] _zz_658_; + wire _zz_659_; + wire _zz_660_; + wire _zz_661_; + wire [1:0] _zz_662_; + wire [0:0] _zz_663_; + wire [92:0] _zz_664_; + wire [0:0] _zz_665_; + wire [84:0] _zz_666_; + wire [31:0] _zz_667_; + wire _zz_668_; + wire [0:0] _zz_669_; + wire [75:0] _zz_670_; + wire [31:0] _zz_671_; + wire [31:0] _zz_672_; + wire _zz_673_; + wire [0:0] _zz_674_; + wire [68:0] _zz_675_; + wire [31:0] _zz_676_; + wire [31:0] _zz_677_; + wire [31:0] _zz_678_; + wire _zz_679_; + wire [0:0] _zz_680_; + wire [62:0] _zz_681_; + wire [31:0] _zz_682_; + wire [31:0] _zz_683_; + wire [31:0] _zz_684_; + wire _zz_685_; + wire [0:0] _zz_686_; + wire [56:0] _zz_687_; + wire [31:0] _zz_688_; + wire [31:0] _zz_689_; + wire [31:0] _zz_690_; + wire _zz_691_; + wire [0:0] _zz_692_; + wire [50:0] _zz_693_; + wire [31:0] _zz_694_; + wire [31:0] _zz_695_; + wire [31:0] _zz_696_; + wire _zz_697_; + wire [0:0] _zz_698_; + wire [44:0] _zz_699_; + wire [31:0] _zz_700_; + wire [31:0] _zz_701_; + wire [31:0] _zz_702_; + wire _zz_703_; + wire [0:0] _zz_704_; + wire [38:0] _zz_705_; + wire [31:0] _zz_706_; + wire [31:0] _zz_707_; + wire [31:0] _zz_708_; + wire _zz_709_; + wire [0:0] _zz_710_; + wire [32:0] _zz_711_; + wire [31:0] _zz_712_; + wire [31:0] _zz_713_; + wire [31:0] _zz_714_; + wire _zz_715_; + wire [0:0] _zz_716_; + wire [26:0] _zz_717_; + wire [31:0] _zz_718_; + wire [31:0] _zz_719_; + wire [31:0] _zz_720_; + wire _zz_721_; + wire [0:0] _zz_722_; + wire [20:0] _zz_723_; + wire [31:0] _zz_724_; + wire [31:0] _zz_725_; + wire [31:0] _zz_726_; + wire _zz_727_; + wire [0:0] _zz_728_; + wire [14:0] _zz_729_; + wire [31:0] _zz_730_; + wire [31:0] _zz_731_; + wire [31:0] _zz_732_; + wire _zz_733_; + wire [0:0] _zz_734_; + wire [8:0] _zz_735_; + wire [31:0] _zz_736_; + wire [31:0] _zz_737_; + wire [31:0] _zz_738_; + wire _zz_739_; + wire [0:0] _zz_740_; + wire [2:0] _zz_741_; + wire [31:0] _zz_742_; + wire [31:0] _zz_743_; + wire _zz_744_; + wire [0:0] _zz_745_; + wire [0:0] _zz_746_; + wire _zz_747_; + wire _zz_748_; + wire [3:0] _zz_749_; + wire [3:0] _zz_750_; + wire _zz_751_; + wire [0:0] _zz_752_; + wire [73:0] _zz_753_; + wire [31:0] _zz_754_; + wire [0:0] _zz_755_; + wire [0:0] _zz_756_; + wire _zz_757_; + wire [0:0] _zz_758_; + wire [5:0] _zz_759_; + wire [0:0] _zz_760_; + wire [18:0] _zz_761_; + wire [0:0] _zz_762_; + wire [0:0] _zz_763_; + wire _zz_764_; + wire [0:0] _zz_765_; + wire [70:0] _zz_766_; + wire [31:0] _zz_767_; + wire [31:0] _zz_768_; + wire [31:0] _zz_769_; + wire [31:0] _zz_770_; + wire [31:0] _zz_771_; + wire _zz_772_; + wire [0:0] _zz_773_; + wire [3:0] _zz_774_; + wire [31:0] _zz_775_; + wire [31:0] _zz_776_; + wire [0:0] _zz_777_; + wire [16:0] _zz_778_; + wire [31:0] _zz_779_; + wire [31:0] _zz_780_; + wire _zz_781_; + wire [19:0] _zz_782_; + wire [19:0] _zz_783_; + wire _zz_784_; + wire [0:0] _zz_785_; + wire [68:0] _zz_786_; + wire [31:0] _zz_787_; + wire [31:0] _zz_788_; + wire [31:0] _zz_789_; + wire _zz_790_; + wire [0:0] _zz_791_; + wire [1:0] _zz_792_; + wire [0:0] _zz_793_; + wire [14:0] _zz_794_; + wire [31:0] _zz_795_; + wire _zz_796_; + wire [0:0] _zz_797_; + wire [17:0] _zz_798_; + wire [3:0] _zz_799_; + wire [3:0] _zz_800_; + wire _zz_801_; + wire [0:0] _zz_802_; + wire [66:0] _zz_803_; + wire [31:0] _zz_804_; + wire [31:0] _zz_805_; + wire [31:0] _zz_806_; + wire _zz_807_; + wire _zz_808_; + wire [0:0] _zz_809_; + wire [12:0] _zz_810_; + wire [31:0] _zz_811_; + wire [31:0] _zz_812_; + wire [31:0] _zz_813_; + wire _zz_814_; + wire [0:0] _zz_815_; + wire [15:0] _zz_816_; + wire _zz_817_; + wire [0:0] _zz_818_; + wire [1:0] _zz_819_; + wire [0:0] _zz_820_; + wire [2:0] _zz_821_; + wire [3:0] _zz_822_; + wire [3:0] _zz_823_; + wire _zz_824_; + wire [0:0] _zz_825_; + wire [64:0] _zz_826_; + wire [31:0] _zz_827_; + wire [31:0] _zz_828_; + wire [0:0] _zz_829_; + wire [10:0] _zz_830_; + wire [31:0] _zz_831_; + wire [0:0] _zz_832_; + wire [13:0] _zz_833_; + wire [31:0] _zz_834_; + wire _zz_835_; + wire _zz_836_; + wire [0:0] _zz_837_; + wire [0:0] _zz_838_; + wire [0:0] _zz_839_; + wire [1:0] _zz_840_; + wire [0:0] _zz_841_; + wire [0:0] _zz_842_; + wire [8:0] _zz_843_; + wire [8:0] _zz_844_; + wire _zz_845_; + wire [0:0] _zz_846_; + wire [62:0] _zz_847_; + wire [0:0] _zz_848_; + wire [8:0] _zz_849_; + wire [0:0] _zz_850_; + wire [11:0] _zz_851_; + wire [31:0] _zz_852_; + wire [31:0] _zz_853_; + wire [31:0] _zz_854_; + wire [31:0] _zz_855_; + wire [31:0] _zz_856_; + wire [31:0] _zz_857_; + wire _zz_858_; + wire [0:0] _zz_859_; + wire [6:0] _zz_860_; + wire [0:0] _zz_861_; + wire [1:0] _zz_862_; + wire [24:0] _zz_863_; + wire [24:0] _zz_864_; + wire _zz_865_; + wire [0:0] _zz_866_; + wire [60:0] _zz_867_; + wire [0:0] _zz_868_; + wire [6:0] _zz_869_; + wire _zz_870_; + wire [0:0] _zz_871_; + wire [9:0] _zz_872_; + wire [31:0] _zz_873_; + wire [31:0] _zz_874_; + wire [31:0] _zz_875_; + wire _zz_876_; + wire [0:0] _zz_877_; + wire [4:0] _zz_878_; + wire [31:0] _zz_879_; + wire [31:0] _zz_880_; + wire _zz_881_; + wire _zz_882_; + wire _zz_883_; + wire [0:0] _zz_884_; + wire [22:0] _zz_885_; + wire [0:0] _zz_886_; + wire [0:0] _zz_887_; + wire [1:0] _zz_888_; + wire [1:0] _zz_889_; + wire _zz_890_; + wire [0:0] _zz_891_; + wire [58:0] _zz_892_; + wire [0:0] _zz_893_; + wire [5:0] _zz_894_; + wire [31:0] _zz_895_; + wire [31:0] _zz_896_; + wire _zz_897_; + wire [0:0] _zz_898_; + wire [8:0] _zz_899_; + wire [31:0] _zz_900_; + wire [31:0] _zz_901_; + wire [31:0] _zz_902_; + wire _zz_903_; + wire [0:0] _zz_904_; + wire [3:0] _zz_905_; + wire [31:0] _zz_906_; + wire [31:0] _zz_907_; + wire [31:0] _zz_908_; + wire [31:0] _zz_909_; + wire [31:0] _zz_910_; + wire [31:0] _zz_911_; + wire [31:0] _zz_912_; + wire [0:0] _zz_913_; + wire [21:0] _zz_914_; + wire _zz_915_; + wire _zz_916_; + wire [0:0] _zz_917_; + wire [0:0] _zz_918_; + wire [2:0] _zz_919_; + wire [2:0] _zz_920_; + wire _zz_921_; + wire [0:0] _zz_922_; + wire [57:0] _zz_923_; + wire [0:0] _zz_924_; + wire [4:0] _zz_925_; + wire [31:0] _zz_926_; + wire [31:0] _zz_927_; + wire [31:0] _zz_928_; + wire _zz_929_; + wire [0:0] _zz_930_; + wire [7:0] _zz_931_; + wire [31:0] _zz_932_; + wire [31:0] _zz_933_; + wire [31:0] _zz_934_; + wire _zz_935_; + wire [0:0] _zz_936_; + wire [2:0] _zz_937_; + wire [31:0] _zz_938_; + wire [31:0] _zz_939_; + wire [31:0] _zz_940_; + wire _zz_941_; + wire [0:0] _zz_942_; + wire [20:0] _zz_943_; + wire [31:0] _zz_944_; + wire [31:0] _zz_945_; + wire [31:0] _zz_946_; + wire [31:0] _zz_947_; + wire _zz_948_; + wire [0:0] _zz_949_; + wire [1:0] _zz_950_; + wire [0:0] _zz_951_; + wire [0:0] _zz_952_; + wire _zz_953_; + wire [0:0] _zz_954_; + wire [56:0] _zz_955_; + wire [0:0] _zz_956_; + wire [3:0] _zz_957_; + wire [31:0] _zz_958_; + wire [31:0] _zz_959_; + wire [31:0] _zz_960_; + wire _zz_961_; + wire [0:0] _zz_962_; + wire [6:0] _zz_963_; + wire [31:0] _zz_964_; + wire [31:0] _zz_965_; + wire [31:0] _zz_966_; + wire _zz_967_; + wire [0:0] _zz_968_; + wire [1:0] _zz_969_; + wire [31:0] _zz_970_; + wire [31:0] _zz_971_; + wire _zz_972_; + wire [0:0] _zz_973_; + wire [19:0] _zz_974_; + wire [31:0] _zz_975_; + wire [31:0] _zz_976_; + wire [31:0] _zz_977_; + wire [31:0] _zz_978_; + wire [0:0] _zz_979_; + wire [0:0] _zz_980_; + wire _zz_981_; + wire [4:0] _zz_982_; + wire [4:0] _zz_983_; + wire _zz_984_; + wire [0:0] _zz_985_; + wire [55:0] _zz_986_; + wire _zz_987_; + wire [0:0] _zz_988_; + wire [1:0] _zz_989_; + wire [31:0] _zz_990_; + wire [31:0] _zz_991_; + wire [31:0] _zz_992_; + wire _zz_993_; + wire [0:0] _zz_994_; + wire [4:0] _zz_995_; + wire [31:0] _zz_996_; + wire [31:0] _zz_997_; + wire [31:0] _zz_998_; + wire _zz_999_; + wire _zz_1000_; + wire [31:0] _zz_1001_; + wire _zz_1002_; + wire [0:0] _zz_1003_; + wire [17:0] _zz_1004_; + wire [31:0] _zz_1005_; + wire [31:0] _zz_1006_; + wire [31:0] _zz_1007_; + wire [0:0] _zz_1008_; + wire [2:0] _zz_1009_; + wire [0:0] _zz_1010_; + wire [0:0] _zz_1011_; + wire [8:0] _zz_1012_; + wire [8:0] _zz_1013_; + wire _zz_1014_; + wire [0:0] _zz_1015_; + wire [53:0] _zz_1016_; + wire [31:0] _zz_1017_; + wire [31:0] _zz_1018_; + wire _zz_1019_; + wire [0:0] _zz_1020_; + wire [0:0] _zz_1021_; + wire [31:0] _zz_1022_; + wire [31:0] _zz_1023_; + wire [31:0] _zz_1024_; + wire _zz_1025_; + wire [0:0] _zz_1026_; + wire [3:0] _zz_1027_; + wire [31:0] _zz_1028_; + wire [31:0] _zz_1029_; + wire [31:0] _zz_1030_; + wire [31:0] _zz_1031_; + wire [31:0] _zz_1032_; + wire [31:0] _zz_1033_; + wire [31:0] _zz_1034_; + wire [0:0] _zz_1035_; + wire [16:0] _zz_1036_; + wire [31:0] _zz_1037_; + wire [0:0] _zz_1038_; + wire [1:0] _zz_1039_; + wire _zz_1040_; + wire [0:0] _zz_1041_; + wire [7:0] _zz_1042_; + wire [4:0] _zz_1043_; + wire [4:0] _zz_1044_; + wire _zz_1045_; + wire [0:0] _zz_1046_; + wire [52:0] _zz_1047_; + wire [31:0] _zz_1048_; + wire [31:0] _zz_1049_; + wire [31:0] _zz_1050_; + wire [31:0] _zz_1051_; + wire [31:0] _zz_1052_; + wire [31:0] _zz_1053_; + wire _zz_1054_; + wire [0:0] _zz_1055_; + wire [1:0] _zz_1056_; + wire [0:0] _zz_1057_; + wire [14:0] _zz_1058_; + wire [31:0] _zz_1059_; + wire [0:0] _zz_1060_; + wire [5:0] _zz_1061_; + wire _zz_1062_; + wire [0:0] _zz_1063_; + wire [2:0] _zz_1064_; + wire [0:0] _zz_1065_; + wire [4:0] _zz_1066_; + wire [0:0] _zz_1067_; + wire [0:0] _zz_1068_; + wire _zz_1069_; + wire [0:0] _zz_1070_; + wire [50:0] _zz_1071_; + wire [31:0] _zz_1072_; + wire [31:0] _zz_1073_; + wire [31:0] _zz_1074_; + wire _zz_1075_; + wire _zz_1076_; + wire [0:0] _zz_1077_; + wire [12:0] _zz_1078_; + wire _zz_1079_; + wire [0:0] _zz_1080_; + wire [3:0] _zz_1081_; + wire [31:0] _zz_1082_; + wire [0:0] _zz_1083_; + wire [0:0] _zz_1084_; + wire [31:0] _zz_1085_; + wire [31:0] _zz_1086_; + wire [0:0] _zz_1087_; + wire [2:0] _zz_1088_; + wire [2:0] _zz_1089_; + wire [2:0] _zz_1090_; + wire _zz_1091_; + wire [0:0] _zz_1092_; + wire [48:0] _zz_1093_; + wire [31:0] _zz_1094_; + wire [31:0] _zz_1095_; + wire [31:0] _zz_1096_; + wire [31:0] _zz_1097_; + wire _zz_1098_; + wire [0:0] _zz_1099_; + wire [10:0] _zz_1100_; + wire [31:0] _zz_1101_; + wire [31:0] _zz_1102_; + wire [31:0] _zz_1103_; + wire _zz_1104_; + wire [0:0] _zz_1105_; + wire [1:0] _zz_1106_; + wire [0:0] _zz_1107_; + wire [0:0] _zz_1108_; + wire [0:0] _zz_1109_; + wire [0:0] _zz_1110_; + wire [0:0] _zz_1111_; + wire [1:0] _zz_1112_; + wire [14:0] _zz_1113_; + wire [14:0] _zz_1114_; + wire _zz_1115_; + wire [0:0] _zz_1116_; + wire [46:0] _zz_1117_; + wire [31:0] _zz_1118_; + wire [0:0] _zz_1119_; + wire [8:0] _zz_1120_; + wire [31:0] _zz_1121_; + wire [31:0] _zz_1122_; + wire [31:0] _zz_1123_; + wire _zz_1124_; + wire _zz_1125_; + wire [31:0] _zz_1126_; + wire [31:0] _zz_1127_; + wire [31:0] _zz_1128_; + wire [31:0] _zz_1129_; + wire _zz_1130_; + wire _zz_1131_; + wire [0:0] _zz_1132_; + wire [12:0] _zz_1133_; + wire [0:0] _zz_1134_; + wire [0:0] _zz_1135_; + wire [1:0] _zz_1136_; + wire [1:0] _zz_1137_; + wire _zz_1138_; + wire [0:0] _zz_1139_; + wire [44:0] _zz_1140_; + wire [0:0] _zz_1141_; + wire [6:0] _zz_1142_; + wire [31:0] _zz_1143_; + wire [31:0] _zz_1144_; + wire [31:0] _zz_1145_; + wire [31:0] _zz_1146_; + wire [0:0] _zz_1147_; + wire [10:0] _zz_1148_; + wire [31:0] _zz_1149_; + wire [31:0] _zz_1150_; + wire [0:0] _zz_1151_; + wire [2:0] _zz_1152_; + wire [1:0] _zz_1153_; + wire [1:0] _zz_1154_; + wire _zz_1155_; + wire [0:0] _zz_1156_; + wire [42:0] _zz_1157_; + wire [0:0] _zz_1158_; + wire [4:0] _zz_1159_; + wire _zz_1160_; + wire [0:0] _zz_1161_; + wire [8:0] _zz_1162_; + wire [0:0] _zz_1163_; + wire [0:0] _zz_1164_; + wire [0:0] _zz_1165_; + wire [6:0] _zz_1166_; + wire [0:0] _zz_1167_; + wire [0:0] _zz_1168_; + wire _zz_1169_; + wire [0:0] _zz_1170_; + wire [40:0] _zz_1171_; + wire [0:0] _zz_1172_; + wire [2:0] _zz_1173_; + wire [31:0] _zz_1174_; + wire [0:0] _zz_1175_; + wire [6:0] _zz_1176_; + wire _zz_1177_; + wire [0:0] _zz_1178_; + wire [4:0] _zz_1179_; + wire [0:0] _zz_1180_; + wire [4:0] _zz_1181_; + wire [3:0] _zz_1182_; + wire [3:0] _zz_1183_; + wire _zz_1184_; + wire [0:0] _zz_1185_; + wire [38:0] _zz_1186_; + wire [31:0] _zz_1187_; + wire [31:0] _zz_1188_; + wire [0:0] _zz_1189_; + wire [0:0] _zz_1190_; + wire [31:0] _zz_1191_; + wire [31:0] _zz_1192_; + wire _zz_1193_; + wire [0:0] _zz_1194_; + wire [4:0] _zz_1195_; + wire [31:0] _zz_1196_; + wire [31:0] _zz_1197_; + wire [31:0] _zz_1198_; + wire _zz_1199_; + wire [0:0] _zz_1200_; + wire [2:0] _zz_1201_; + wire _zz_1202_; + wire [0:0] _zz_1203_; + wire [2:0] _zz_1204_; + wire _zz_1205_; + wire [0:0] _zz_1206_; + wire [1:0] _zz_1207_; + wire [0:0] _zz_1208_; + wire [4:0] _zz_1209_; + wire [10:0] _zz_1210_; + wire [10:0] _zz_1211_; + wire _zz_1212_; + wire [0:0] _zz_1213_; + wire [36:0] _zz_1214_; + wire [31:0] _zz_1215_; + wire _zz_1216_; + wire [31:0] _zz_1217_; + wire [31:0] _zz_1218_; + wire [31:0] _zz_1219_; + wire [0:0] _zz_1220_; + wire [3:0] _zz_1221_; + wire [31:0] _zz_1222_; + wire [31:0] _zz_1223_; + wire [31:0] _zz_1224_; + wire _zz_1225_; + wire [0:0] _zz_1226_; + wire [1:0] _zz_1227_; + wire [31:0] _zz_1228_; + wire [31:0] _zz_1229_; + wire [0:0] _zz_1230_; + wire [1:0] _zz_1231_; + wire [31:0] _zz_1232_; + wire [31:0] _zz_1233_; + wire _zz_1234_; + wire [0:0] _zz_1235_; + wire [0:0] _zz_1236_; + wire [0:0] _zz_1237_; + wire [3:0] _zz_1238_; + wire [0:0] _zz_1239_; + wire [9:0] _zz_1240_; + wire [0:0] _zz_1241_; + wire [0:0] _zz_1242_; + wire _zz_1243_; + wire [0:0] _zz_1244_; + wire [35:0] _zz_1245_; + wire [31:0] _zz_1246_; + wire _zz_1247_; + wire [0:0] _zz_1248_; + wire [1:0] _zz_1249_; + wire [31:0] _zz_1250_; + wire [31:0] _zz_1251_; + wire [31:0] _zz_1252_; + wire _zz_1253_; + wire _zz_1254_; + wire [31:0] _zz_1255_; + wire [31:0] _zz_1256_; + wire _zz_1257_; + wire [31:0] _zz_1258_; + wire [31:0] _zz_1259_; + wire [31:0] _zz_1260_; + wire [0:0] _zz_1261_; + wire [1:0] _zz_1262_; + wire [0:0] _zz_1263_; + wire [7:0] _zz_1264_; + wire _zz_1265_; + wire [0:0] _zz_1266_; + wire [0:0] _zz_1267_; + wire _zz_1268_; + wire [0:0] _zz_1269_; + wire [33:0] _zz_1270_; + wire [31:0] _zz_1271_; + wire [31:0] _zz_1272_; + wire [31:0] _zz_1273_; + wire [31:0] _zz_1274_; + wire [31:0] _zz_1275_; + wire [31:0] _zz_1276_; + wire _zz_1277_; + wire _zz_1278_; + wire [31:0] _zz_1279_; + wire [31:0] _zz_1280_; + wire _zz_1281_; + wire [0:0] _zz_1282_; + wire [5:0] _zz_1283_; + wire [31:0] _zz_1284_; + wire [0:0] _zz_1285_; + wire [0:0] _zz_1286_; + wire [1:0] _zz_1287_; + wire [1:0] _zz_1288_; + wire _zz_1289_; + wire [0:0] _zz_1290_; + wire [31:0] _zz_1291_; + wire [31:0] _zz_1292_; + wire [31:0] _zz_1293_; + wire [31:0] _zz_1294_; + wire _zz_1295_; + wire [0:0] _zz_1296_; + wire [3:0] _zz_1297_; + wire [31:0] _zz_1298_; + wire [31:0] _zz_1299_; + wire _zz_1300_; + wire _zz_1301_; + wire [0:0] _zz_1302_; + wire [0:0] _zz_1303_; + wire [2:0] _zz_1304_; + wire [2:0] _zz_1305_; + wire _zz_1306_; + wire [0:0] _zz_1307_; + wire [29:0] _zz_1308_; + wire [31:0] _zz_1309_; + wire [31:0] _zz_1310_; + wire [31:0] _zz_1311_; + wire _zz_1312_; + wire [0:0] _zz_1313_; + wire [1:0] _zz_1314_; + wire [31:0] _zz_1315_; + wire [31:0] _zz_1316_; + wire [31:0] _zz_1317_; + wire [31:0] _zz_1318_; + wire _zz_1319_; + wire [0:0] _zz_1320_; + wire [0:0] _zz_1321_; + wire [0:0] _zz_1322_; + wire [0:0] _zz_1323_; + wire [2:0] _zz_1324_; + wire [2:0] _zz_1325_; + wire _zz_1326_; + wire [0:0] _zz_1327_; + wire [27:0] _zz_1328_; + wire [31:0] _zz_1329_; + wire [31:0] _zz_1330_; + wire [31:0] _zz_1331_; + wire _zz_1332_; + wire _zz_1333_; + wire [31:0] _zz_1334_; + wire [31:0] _zz_1335_; + wire [31:0] _zz_1336_; + wire [31:0] _zz_1337_; + wire [31:0] _zz_1338_; + wire [31:0] _zz_1339_; + wire [31:0] _zz_1340_; + wire [31:0] _zz_1341_; + wire [31:0] _zz_1342_; + wire _zz_1343_; + wire [0:0] _zz_1344_; + wire [0:0] _zz_1345_; + wire [0:0] _zz_1346_; + wire [1:0] _zz_1347_; + wire [2:0] _zz_1348_; + wire [2:0] _zz_1349_; + wire _zz_1350_; + wire [0:0] _zz_1351_; + wire [25:0] _zz_1352_; + wire [31:0] _zz_1353_; + wire [31:0] _zz_1354_; + wire [31:0] _zz_1355_; + wire [31:0] _zz_1356_; + wire [31:0] _zz_1357_; + wire [31:0] _zz_1358_; + wire [31:0] _zz_1359_; + wire [31:0] _zz_1360_; + wire [31:0] _zz_1361_; + wire _zz_1362_; + wire _zz_1363_; + wire _zz_1364_; + wire [0:0] _zz_1365_; + wire [0:0] _zz_1366_; + wire [0:0] _zz_1367_; + wire [1:0] _zz_1368_; + wire _zz_1369_; + wire [0:0] _zz_1370_; + wire [23:0] _zz_1371_; + wire [31:0] _zz_1372_; + wire [31:0] _zz_1373_; + wire [31:0] _zz_1374_; + wire [31:0] _zz_1375_; + wire [31:0] _zz_1376_; + wire [31:0] _zz_1377_; + wire [31:0] _zz_1378_; + wire _zz_1379_; + wire _zz_1380_; + wire [0:0] _zz_1381_; + wire [0:0] _zz_1382_; + wire _zz_1383_; + wire [0:0] _zz_1384_; + wire [21:0] _zz_1385_; + wire [31:0] _zz_1386_; + wire _zz_1387_; + wire _zz_1388_; + wire _zz_1389_; + wire [1:0] _zz_1390_; + wire [1:0] _zz_1391_; + wire _zz_1392_; + wire [0:0] _zz_1393_; + wire [18:0] _zz_1394_; + wire [31:0] _zz_1395_; + wire _zz_1396_; + wire _zz_1397_; + wire [0:0] _zz_1398_; + wire [1:0] _zz_1399_; + wire [5:0] _zz_1400_; + wire [5:0] _zz_1401_; + wire _zz_1402_; + wire [0:0] _zz_1403_; + wire [14:0] _zz_1404_; + wire [31:0] _zz_1405_; + wire [31:0] _zz_1406_; + wire [31:0] _zz_1407_; + wire [31:0] _zz_1408_; + wire [31:0] _zz_1409_; + wire [0:0] _zz_1410_; + wire [2:0] _zz_1411_; + wire [0:0] _zz_1412_; + wire [1:0] _zz_1413_; + wire [0:0] _zz_1414_; + wire [29:0] _zz_1415_; + wire [1:0] _zz_1416_; + wire [1:0] _zz_1417_; + wire _zz_1418_; + wire [0:0] _zz_1419_; + wire [11:0] _zz_1420_; + wire [31:0] _zz_1421_; + wire [31:0] _zz_1422_; + wire [0:0] _zz_1423_; + wire [0:0] _zz_1424_; + wire [31:0] _zz_1425_; + wire [31:0] _zz_1426_; + wire _zz_1427_; + wire [31:0] _zz_1428_; + wire [31:0] _zz_1429_; + wire _zz_1430_; + wire [0:0] _zz_1431_; + wire [27:0] _zz_1432_; + wire _zz_1433_; + wire [0:0] _zz_1434_; + wire [3:0] _zz_1435_; + wire [3:0] _zz_1436_; + wire [3:0] _zz_1437_; + wire _zz_1438_; + wire [0:0] _zz_1439_; + wire [9:0] _zz_1440_; + wire [31:0] _zz_1441_; + wire [31:0] _zz_1442_; + wire [31:0] _zz_1443_; + wire [31:0] _zz_1444_; + wire [0:0] _zz_1445_; + wire [25:0] _zz_1446_; + wire [31:0] _zz_1447_; + wire [31:0] _zz_1448_; + wire [31:0] _zz_1449_; + wire _zz_1450_; + wire [0:0] _zz_1451_; + wire [1:0] _zz_1452_; + wire _zz_1453_; + wire [0:0] _zz_1454_; + wire [1:0] _zz_1455_; + wire [0:0] _zz_1456_; + wire [0:0] _zz_1457_; + wire [3:0] _zz_1458_; + wire [3:0] _zz_1459_; + wire _zz_1460_; + wire [0:0] _zz_1461_; + wire [7:0] _zz_1462_; + wire [31:0] _zz_1463_; + wire [31:0] _zz_1464_; + wire [0:0] _zz_1465_; + wire [23:0] _zz_1466_; + wire [31:0] _zz_1467_; + wire [31:0] _zz_1468_; + wire [31:0] _zz_1469_; + wire _zz_1470_; + wire _zz_1471_; + wire [31:0] _zz_1472_; + wire _zz_1473_; + wire _zz_1474_; + wire [31:0] _zz_1475_; + wire [31:0] _zz_1476_; + wire _zz_1477_; + wire [0:0] _zz_1478_; + wire [1:0] _zz_1479_; + wire [0:0] _zz_1480_; + wire [1:0] _zz_1481_; + wire [9:0] _zz_1482_; + wire [9:0] _zz_1483_; + wire _zz_1484_; + wire [0:0] _zz_1485_; + wire [5:0] _zz_1486_; + wire [0:0] _zz_1487_; + wire [21:0] _zz_1488_; + wire [31:0] _zz_1489_; + wire [31:0] _zz_1490_; + wire [31:0] _zz_1491_; + wire [31:0] _zz_1492_; + wire [31:0] _zz_1493_; + wire [31:0] _zz_1494_; + wire [31:0] _zz_1495_; + wire _zz_1496_; + wire _zz_1497_; + wire [0:0] _zz_1498_; + wire [7:0] _zz_1499_; + wire _zz_1500_; + wire [1:0] _zz_1501_; + wire [1:0] _zz_1502_; + wire _zz_1503_; + wire [0:0] _zz_1504_; + wire [3:0] _zz_1505_; + wire [0:0] _zz_1506_; + wire [19:0] _zz_1507_; + wire [31:0] _zz_1508_; + wire [31:0] _zz_1509_; + wire [31:0] _zz_1510_; + wire [31:0] _zz_1511_; + wire _zz_1512_; + wire [0:0] _zz_1513_; + wire [5:0] _zz_1514_; + wire [31:0] _zz_1515_; + wire [1:0] _zz_1516_; + wire [1:0] _zz_1517_; + wire _zz_1518_; + wire [0:0] _zz_1519_; + wire [1:0] _zz_1520_; + wire [0:0] _zz_1521_; + wire [17:0] _zz_1522_; + wire [31:0] _zz_1523_; + wire [31:0] _zz_1524_; + wire [31:0] _zz_1525_; + wire _zz_1526_; + wire [0:0] _zz_1527_; + wire [3:0] _zz_1528_; + wire _zz_1529_; + wire _zz_1530_; + wire [0:0] _zz_1531_; + wire [4:0] _zz_1532_; + wire [0:0] _zz_1533_; + wire [0:0] _zz_1534_; + wire _zz_1535_; + wire _zz_1536_; + wire [0:0] _zz_1537_; + wire [15:0] _zz_1538_; + wire [31:0] _zz_1539_; + wire [31:0] _zz_1540_; + wire [31:0] _zz_1541_; + wire _zz_1542_; + wire [0:0] _zz_1543_; + wire [1:0] _zz_1544_; + wire [31:0] _zz_1545_; + wire [31:0] _zz_1546_; + wire _zz_1547_; + wire [0:0] _zz_1548_; + wire [2:0] _zz_1549_; + wire [31:0] _zz_1550_; + wire [31:0] _zz_1551_; + wire _zz_1552_; + wire [0:0] _zz_1553_; + wire [1:0] _zz_1554_; + wire _zz_1555_; + wire [0:0] _zz_1556_; + wire [13:0] _zz_1557_; + wire [31:0] _zz_1558_; + wire [31:0] _zz_1559_; + wire [31:0] _zz_1560_; + wire _zz_1561_; + wire [31:0] _zz_1562_; + wire [31:0] _zz_1563_; + wire [31:0] _zz_1564_; + wire [0:0] _zz_1565_; + wire [0:0] _zz_1566_; + wire [31:0] _zz_1567_; + wire [31:0] _zz_1568_; + wire [31:0] _zz_1569_; + wire _zz_1570_; + wire [31:0] _zz_1571_; + wire [0:0] _zz_1572_; + wire [8:0] _zz_1573_; + wire [31:0] _zz_1574_; + wire [31:0] _zz_1575_; + wire [31:0] _zz_1576_; + wire _zz_1577_; + wire [0:0] _zz_1578_; + wire [0:0] _zz_1579_; + wire [10:0] _zz_1580_; + wire [10:0] _zz_1581_; + wire [17:0] _zz_1582_; + wire [0:0] _zz_1583_; + wire [17:0] _zz_1584_; + wire [0:0] _zz_1585_; + wire [17:0] _zz_1586_; + wire [0:0] _zz_1587_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_1_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_2_; + wire decode_DECODER_stageables_29; + wire decode_DECODER_stageables_25; + wire [31:0] execute_NEXT_PC2; + wire execute_XER_SO; + wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_4_; + wire decode_DECODER_stageables_43; + wire decode_DECODER_stageables_27; + wire [7:0] decode_CR_FIELD_RD; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire decode_DECODER_stageables_21; + wire execute_DECODER_stageables_37; + wire decode_DECODER_stageables_37; + wire `AluCtrlEnum_defaultEncoding_type decode_DECODER_stageables_8; + wire `AluCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_DECODER_stageables_23; + wire [31:0] memory_SRC_ADD; + wire decode_DECODER_stageables_46; + wire `Src3CtrlEnum_defaultEncoding_type decode_DECODER_stageables_1; + wire `Src3CtrlEnum_defaultEncoding_type _zz_10_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_11_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_12_; + wire [7:0] execute_CR_FIELD_WR; + wire `DataSizeEnum_defaultEncoding_type memory_DECODER_stageables_7; + wire `DataSizeEnum_defaultEncoding_type _zz_13_; + wire `DataSizeEnum_defaultEncoding_type _zz_14_; + wire `DataSizeEnum_defaultEncoding_type _zz_15_; + wire `DataSizeEnum_defaultEncoding_type _zz_16_; + wire `DataSizeEnum_defaultEncoding_type _zz_17_; + wire `DataSizeEnum_defaultEncoding_type decode_DECODER_stageables_7; + wire `DataSizeEnum_defaultEncoding_type _zz_18_; + wire `DataSizeEnum_defaultEncoding_type _zz_19_; + wire `DataSizeEnum_defaultEncoding_type _zz_20_; + wire `CRMoveCtrlEnum_defaultEncoding_type decode_DECODER_stageables_51; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_21_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_22_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_23_; + wire memory_DECODER_stageables_53; + wire execute_DECODER_stageables_53; + wire decode_DECODER_stageables_53; + wire [33:0] execute_MUL_HL; + wire [4:0] writeBack_REGFILE_WRITE_ADDR; + wire [4:0] memory_REGFILE_WRITE_ADDR; + wire [4:0] execute_REGFILE_WRITE_ADDR; + wire decode_DECODER_stageables_35; + wire execute_TARGET_MISSMATCH2; + wire execute_DECODER_stageables_31; + wire decode_DECODER_stageables_31; + wire [33:0] execute_MUL_LH; + wire decode_DECODER_stageables_40; + wire decode_DECODER_stageables_2; + wire [31:0] execute_RA; + wire decode_DECODER_stageables_3; + wire decode_DECODER_stageables_14; + wire [31:0] memory_SRC1; + wire `EndianEnum_defaultEncoding_type memory_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_24_; + wire `EndianEnum_defaultEncoding_type _zz_25_; + wire `EndianEnum_defaultEncoding_type _zz_26_; + wire `EndianEnum_defaultEncoding_type _zz_27_; + wire `EndianEnum_defaultEncoding_type _zz_28_; + wire `EndianEnum_defaultEncoding_type _zz_29_; + wire `EndianEnum_defaultEncoding_type _zz_30_; + wire memory_DECODER_stageables_24; + wire execute_DECODER_stageables_24; + wire decode_DECODER_stageables_24; + wire decode_DECODER_stageables_34; + wire decode_DECODER_stageables_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_DECODER_stageables_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_31_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_33_; + wire decode_DECODER_stageables_9; + wire decode_DECODER_stageables_45; + wire [4:0] decode_RT_ADDR; + wire decode_DECODER_stageables_42; + wire [51:0] memory_MUL_LOW; + wire `CRBusCmdEnum_defaultEncoding_type _zz_34_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_35_; + wire `CRBusCmdEnum_defaultEncoding_type execute_CR_WRITE_op; + wire [4:0] execute_CR_WRITE_ba; + wire [4:0] execute_CR_WRITE_bb; + wire [4:0] execute_CR_WRITE_bt; + wire [31:0] execute_CR_WRITE_imm; + wire [7:0] execute_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_36_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_37_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_38_; + wire execute_DECODER_stageables_5; + wire decode_DECODER_stageables_5; + wire execute_DECODER_stageables_15; + wire decode_DECODER_stageables_15; + wire `AluSpecCtrlEnum_defaultEncoding_type decode_DECODER_stageables_0; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_39_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_40_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_41_; + wire execute_BRANCH_LINK; + wire execute_BRANCH_DO; + wire memory_DECODER_stageables_39; + wire execute_DECODER_stageables_39; + wire decode_DECODER_stageables_39; + wire memory_DECODER_stageables_56; + wire decode_DECODER_stageables_56; + wire `AluRimiCtrlEnum_defaultEncoding_type decode_DECODER_stageables_16; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_42_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_43_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_44_; + wire decode_DECODER_stageables_11; + wire execute_XER_CA; + wire [4:0] writeBack_LOAD_UPDATE_ADDR; + wire [4:0] memory_LOAD_UPDATE_ADDR; + wire [4:0] execute_LOAD_UPDATE_ADDR; + wire [31:0] execute_MUL_LL; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire decode_DECODER_stageables_22; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DECODER_stageables_32; + wire decode_DECODER_stageables_54; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `CRLogCtrlEnum_defaultEncoding_type decode_DECODER_stageables_20; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_45_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_46_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_47_; + wire decode_DECODER_stageables_57; + wire memory_DECODER_stageables_55; + wire execute_DECODER_stageables_55; + wire decode_DECODER_stageables_55; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49_; + wire [31:0] writeBack_LOAD_UPDATE_DATA; + wire [31:0] memory_LOAD_UPDATE_DATA; + wire [31:0] execute_LOAD_UPDATE_DATA; + wire execute_XER_WRITE_validOV; + wire execute_XER_WRITE_validCA; + wire [1:0] execute_XER_WRITE_imm; + wire decode_DECODER_stageables_48; + wire `EnvCtrlEnum_defaultEncoding_type memory_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_51_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_52_; + wire `EnvCtrlEnum_defaultEncoding_type decode_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_53_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_54_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_55_; + wire execute_PREDICTION_CONTEXT_hazard; + wire execute_PREDICTION_CONTEXT_hit; + wire [19:0] execute_PREDICTION_CONTEXT_line_source; + wire [1:0] execute_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] execute_PREDICTION_CONTEXT_line_target; + wire decode_PREDICTION_CONTEXT_hazard; + wire decode_PREDICTION_CONTEXT_hit; + wire [19:0] decode_PREDICTION_CONTEXT_line_source; + wire [1:0] decode_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] decode_PREDICTION_CONTEXT_line_target; + wire memory_DECODER_stageables_36; + wire execute_DECODER_stageables_36; + wire decode_DECODER_stageables_36; + wire `AluRimiAmtEnum_defaultEncoding_type decode_DECODER_stageables_44; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_56_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_57_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_58_; + wire decode_DECODER_stageables_28; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [31:0] execute_RB; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_59_; + wire writeBack_DECODER_stageables_39; + wire execute_DECODER_stageables_40; + wire execute_DECODER_stageables_30; + reg `EnvCtrlEnum_defaultEncoding_type _zz_60_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_61_; + wire `EnvCtrlEnum_defaultEncoding_type execute_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_62_; + reg `EndianEnum_defaultEncoding_type _zz_63_; + wire [31:0] writeBack_SRC_ADD; + wire [31:0] memory_NEXT_PC2; + wire [31:0] memory_PC; + wire [31:0] memory_BRANCH_CALC; + wire memory_TARGET_MISSMATCH2; + wire memory_BRANCH_DO; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] execute_PC; + reg [7:0] _zz_64_; + wire decode_DECODER_stageables_6; + wire `BranchCtrlEnum_defaultEncoding_type decode_DECODER_stageables_13; + wire `BranchCtrlEnum_defaultEncoding_type _zz_65_; + wire [7:0] writeBack_CR_FIELD_WR; + wire execute_BRANCH_DEC; + wire execute_DECODER_stageables_32; + wire memory_BRANCH_DEC; + wire memory_BRANCH_LINK; + wire [10:0] memory_SPR_ID; + wire memory_DECODER_stageables_32; + wire memory_XER_WRITE_validOV; + wire memory_XER_WRITE_validCA; + wire [1:0] memory_XER_WRITE_imm; + wire `CRBusCmdEnum_defaultEncoding_type memory_CR_WRITE_op; + wire [4:0] memory_CR_WRITE_ba; + wire [4:0] memory_CR_WRITE_bb; + wire [4:0] memory_CR_WRITE_bt; + wire [31:0] memory_CR_WRITE_imm; + wire [7:0] memory_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_66_; + wire memory_DECODER_stageables_31; + wire `BranchCtrlEnum_defaultEncoding_type execute_DECODER_stageables_13; + wire `BranchCtrlEnum_defaultEncoding_type _zz_67_; + wire [7:0] execute_CR_FIELD_RD; + wire [7:0] memory_CR_FIELD_WR; + reg [31:0] _zz_68_; + wire execute_DECODER_stageables_45; + wire [4:0] execute_RT_ADDR; + wire execute_DECODER_stageables_25; + wire memory_DECODER_stageables_45; + wire [4:0] memory_RT_ADDR; + wire memory_DECODER_stageables_5; + wire decode_DECODER_stageables_50; + wire decode_DECODER_stageables_47; + wire decode_DECODER_stageables_10; + wire writeBack_DECODER_stageables_45; + wire [4:0] writeBack_RT_ADDR; + reg [31:0] decode_RS; + reg [31:0] decode_RB; + reg [31:0] decode_RA; + wire [4:0] decode_R2_ADDR; + wire [4:0] decode_R1_ADDR; + wire [4:0] decode_R0_ADDR; + wire execute_DECODER_stageables_29; + wire execute_DECODER_stageables_43; + wire execute_DECODER_stageables_3; + wire [1:0] memory_SRC_CR; + wire memory_XER_SO; + wire [31:0] memory_INSTRUCTION; + wire memory_DECODER_stageables_37; + reg [31:0] _zz_69_; + wire memory_DECODER_stageables_15; + wire memory_DECODER_stageables_43; + wire writeBack_DECODER_stageables_31; + wire writeBack_DECODER_stageables_24; + wire [1:0] writeBack_SRC_CR; + wire writeBack_DECODER_stageables_55; + wire writeBack_XER_SO; + wire writeBack_DECODER_stageables_36; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_DECODER_stageables_35; + wire memory_DECODER_stageables_9; + wire execute_DECODER_stageables_9; + wire writeBack_DECODER_stageables_9; + wire execute_DECODER_stageables_48; + wire [0:0] execute_SRC3; + wire `Src3CtrlEnum_defaultEncoding_type execute_DECODER_stageables_1; + wire `Src3CtrlEnum_defaultEncoding_type _zz_70_; + wire `Src2CtrlEnum_defaultEncoding_type execute_DECODER_stageables_26; + wire `Src2CtrlEnum_defaultEncoding_type _zz_71_; + wire [31:0] _zz_72_; + wire [31:0] _zz_73_; + wire `Src1CtrlEnum_defaultEncoding_type execute_DECODER_stageables_38; + wire `Src1CtrlEnum_defaultEncoding_type _zz_74_; + wire decode_DECODER_stageables_17; + reg [7:0] _zz_75_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_76_; + wire `CRLogCtrlEnum_defaultEncoding_type execute_DECODER_stageables_20; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_77_; + wire `CRMoveCtrlEnum_defaultEncoding_type execute_DECODER_stageables_51; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_78_; + wire execute_DECODER_stageables_46; + wire execute_DECODER_stageables_34; + wire execute_DECODER_stageables_28; + wire execute_DECODER_stageables_57; + wire execute_DECODER_stageables_21; + wire [1:0] execute_SRC_CR; + wire execute_DECODER_stageables_11; + wire execute_DECODER_stageables_18; + wire [1:0] execute_SRC_CAOV; + wire execute_DECODER_stageables_14; + reg [10:0] _zz_79_; + wire execute_DECODER_stageables_6; + wire [4:0] execute_R0_ADDR; + wire `TgtCtrlEnum_defaultEncoding_type execute_DECODER_stageables_12; + wire `TgtCtrlEnum_defaultEncoding_type _zz_80_; + wire `AluCtrlEnum_defaultEncoding_type execute_DECODER_stageables_8; + wire `AluCtrlEnum_defaultEncoding_type _zz_81_; + wire execute_DECODER_stageables_27; + wire execute_DECODER_stageables_2; + wire execute_DECODER_stageables_23; + wire `AluSpecCtrlEnum_defaultEncoding_type execute_DECODER_stageables_0; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_82_; + reg [5:0] _zz_83_; + reg [5:0] _zz_83__30; + reg [5:0] _zz_83__29; + reg [5:0] _zz_83__28; + reg [5:0] _zz_83__27; + reg [5:0] _zz_83__26; + reg [5:0] _zz_83__25; + reg [5:0] _zz_83__24; + reg [5:0] _zz_83__23; + reg [5:0] _zz_83__22; + reg [5:0] _zz_83__21; + reg [5:0] _zz_83__20; + reg [5:0] _zz_83__19; + reg [5:0] _zz_83__18; + reg [5:0] _zz_83__17; + reg [5:0] _zz_83__16; + reg [5:0] _zz_83__15; + reg [5:0] _zz_83__14; + reg [5:0] _zz_83__13; + reg [5:0] _zz_83__12; + reg [5:0] _zz_83__11; + reg [5:0] _zz_83__10; + reg [5:0] _zz_83__9; + reg [5:0] _zz_83__8; + reg [5:0] _zz_83__7; + reg [5:0] _zz_83__6; + reg [5:0] _zz_83__5; + reg [5:0] _zz_83__4; + reg [5:0] _zz_83__3; + reg [5:0] _zz_83__2; + reg [5:0] _zz_83__1; + reg [5:0] _zz_83__0; + reg [3:0] _zz_84_; + reg [3:0] _zz_84__6; + reg [3:0] _zz_84__5; + reg [3:0] _zz_84__4; + reg [3:0] _zz_84__3; + reg [3:0] _zz_84__2; + reg [3:0] _zz_84__1; + reg [3:0] _zz_84__0; + reg [3:0] _zz_85_; + reg [3:0] _zz_85__6; + reg [3:0] _zz_85__5; + reg [3:0] _zz_85__4; + reg [3:0] _zz_85__3; + reg [3:0] _zz_85__2; + reg [3:0] _zz_85__1; + reg [3:0] _zz_85__0; + reg [3:0] _zz_86_; + reg [3:0] _zz_86__6; + reg [3:0] _zz_86__5; + reg [3:0] _zz_86__4; + reg [3:0] _zz_86__3; + reg [3:0] _zz_86__2; + reg [3:0] _zz_86__1; + reg [3:0] _zz_86__0; + reg [3:0] _zz_87_; + reg [3:0] _zz_87__6; + reg [3:0] _zz_87__5; + reg [3:0] _zz_87__4; + reg [3:0] _zz_87__3; + reg [3:0] _zz_87__2; + reg [3:0] _zz_87__1; + reg [3:0] _zz_87__0; + reg [31:0] _zz_88_; + reg [31:0] _zz_89_; + reg [31:0] _zz_90_; + reg [31:0] _zz_91_; + reg [31:0] _zz_92_; + reg [31:0] _zz_93_; + reg [31:0] _zz_94_; + reg [31:0] _zz_95_; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire `AluRimiCtrlEnum_defaultEncoding_type execute_DECODER_stageables_16; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_98_; + wire `AluRimiAmtEnum_defaultEncoding_type execute_DECODER_stageables_44; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_99_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_DECODER_stageables_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100_; + wire execute_DECODER_stageables_54; + wire [10:0] execute_SPR_ID; + wire [31:0] writeBack_SRC1; + wire writeBack_DECODER_stageables_32; + wire [10:0] writeBack_SPR_ID; + wire writeBack_XER_WRITE_validOV; + wire writeBack_XER_WRITE_validCA; + wire [1:0] writeBack_XER_WRITE_imm; + wire writeBack_BRANCH_LINK; + wire writeBack_BRANCH_DEC; + wire `CRBusCmdEnum_defaultEncoding_type writeBack_CR_WRITE_op; + wire [4:0] writeBack_CR_WRITE_ba; + wire [4:0] writeBack_CR_WRITE_bb; + wire [4:0] writeBack_CR_WRITE_bt; + wire [31:0] writeBack_CR_WRITE_imm; + wire [7:0] writeBack_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_101_; + wire _zz_102_; + reg _zz_103_; + wire `TgtCtrlEnum_defaultEncoding_type decode_DECODER_stageables_12; + wire `TgtCtrlEnum_defaultEncoding_type _zz_104_; + wire `Src2CtrlEnum_defaultEncoding_type decode_DECODER_stageables_26; + wire `Src2CtrlEnum_defaultEncoding_type _zz_105_; + wire `Src1CtrlEnum_defaultEncoding_type decode_DECODER_stageables_38; + wire `Src1CtrlEnum_defaultEncoding_type _zz_106_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + wire decode; + wire decode_LEGAL_INSTRUCTION; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_107_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_108_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_109_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_110_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_111_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_112_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_113_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_114_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_115_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_116_; + wire `AluCtrlEnum_defaultEncoding_type _zz_117_; + wire `DataSizeEnum_defaultEncoding_type _zz_118_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_119_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_120_; + reg [31:0] _zz_121_; + wire writeBack_SIGN_EXTEND; + wire `DataSizeEnum_defaultEncoding_type writeBack_DATA_SIZE; + wire `DataSizeEnum_defaultEncoding_type _zz_122_; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire `EndianEnum_defaultEncoding_type writeBack_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_123_; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + reg [31:0] _zz_124_; + wire execute_STORE_UPDATE; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire `DataSizeEnum_defaultEncoding_type execute_DATA_SIZE; + wire `DataSizeEnum_defaultEncoding_type _zz_125_; + wire [31:0] execute_INSTRUCTION; + wire `EndianEnum_defaultEncoding_type execute_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_126_; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg _zz_127_; + reg _zz_127__3; + reg _zz_127__2; + reg _zz_127__1; + reg _zz_127__0; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_128_; + wire `EndianEnum_defaultEncoding_type decode_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_129_; + wire memory_PREDICTION_CONTEXT_hazard; + wire memory_PREDICTION_CONTEXT_hit; + wire [19:0] memory_PREDICTION_CONTEXT_line_source; + wire [1:0] memory_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] memory_PREDICTION_CONTEXT_line_target; + reg _zz_130_; + reg [31:0] _zz_131_; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + wire sprReadBU_valid; + wire [31:0] sprReadBU_payload_data; + wire sprReadSPR_valid; + wire [31:0] sprReadSPR_payload_data; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_fetchPrediction_cmd_hadBranch; + wire [31:0] IBusCachedPlugin_fetchPrediction_cmd_targetPc; + wire IBusCachedPlugin_fetchPrediction_rsp_wasRight; + wire [31:0] IBusCachedPlugin_fetchPrediction_rsp_finalPc; + wire [31:0] IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + reg [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type IBusCachedPlugin_decodeExceptionPort_payload_codePPC; + wire [6:0] IBusCachedPlugin_decodeExceptionPort_payload_imm; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_spr_valid; + wire [9:0] IBusCachedPlugin_mmuBus_spr_payload_id; + wire [31:0] IBusCachedPlugin_mmuBus_spr_payload_data; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_spr_valid; + wire [9:0] DBusCachedPlugin_mmuBus_spr_payload_id; + wire [31:0] DBusCachedPlugin_mmuBus_spr_payload_data; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + reg [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type DBusCachedPlugin_exceptionBus_payload_codePPC; + wire [6:0] DBusCachedPlugin_exceptionBus_payload_imm; + reg decodeExceptionPort_valid; + reg [3:0] decodeExceptionPort_payload_code; + reg [31:0] decodeExceptionPort_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type decodeExceptionPort_payload_codePPC; + wire [6:0] decodeExceptionPort_payload_imm; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + reg [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire `ExcpEnum_defaultEncoding_type BranchPlugin_branchExceptionPort_payload_codePPC; + wire [6:0] BranchPlugin_branchExceptionPort_payload_imm; + reg SPRPlugin_jumpInterface_valid; + reg [31:0] SPRPlugin_jumpInterface_payload; + wire SPRPlugin_exceptionPendings_0; + wire SPRPlugin_exceptionPendings_1; + wire SPRPlugin_exceptionPendings_2; + wire SPRPlugin_exceptionPendings_3; + wire contextSwitching; + wire [1:0] SPRPlugin_privilege; + wire SPRPlugin_forceMachineWire; + reg SPRPlugin_msr_ir; + wire SPRPlugin_msr_dr; + wire SPRPlugin_msr_pr; + reg SPRPlugin_selfException_valid; + reg [3:0] SPRPlugin_selfException_payload_code; + reg [31:0] SPRPlugin_selfException_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_selfException_payload_codePPC; + reg [6:0] SPRPlugin_selfException_payload_imm; + wire SPRPlugin_allowInterrupts; + wire SPRPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_132_; + wire [2:0] _zz_133_; + wire _zz_134_; + wire _zz_135_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + wire IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_predictionPcLoad_valid; + wire [31:0] IBusCachedPlugin_fetchPc_predictionPcLoad_payload; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_139_; + reg _zz_140_; + reg [31:0] _zz_141_; + wire _zz_142_; + reg _zz_143_; + reg [31:0] _zz_144_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + reg [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire IBusCachedPlugin_predictor_historyWriteDelayPatched_valid; + wire [9:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address; + wire [19:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source; + wire [1:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; + wire [31:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target; + reg IBusCachedPlugin_predictor_historyWrite_valid; + wire [9:0] IBusCachedPlugin_predictor_historyWrite_payload_address; + wire [19:0] IBusCachedPlugin_predictor_historyWrite_payload_data_source; + reg [1:0] IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish; + wire [31:0] IBusCachedPlugin_predictor_historyWrite_payload_data_target; + reg IBusCachedPlugin_predictor_writeLast_valid; + reg [9:0] IBusCachedPlugin_predictor_writeLast_payload_address; + reg [19:0] IBusCachedPlugin_predictor_writeLast_payload_data_source; + reg [1:0] IBusCachedPlugin_predictor_writeLast_payload_data_branchWish; + reg [31:0] IBusCachedPlugin_predictor_writeLast_payload_data_target; + wire [29:0] _zz_145_; + wire [19:0] IBusCachedPlugin_predictor_buffer_line_source; + wire [1:0] IBusCachedPlugin_predictor_buffer_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_buffer_line_target; + wire [53:0] _zz_146_; + reg IBusCachedPlugin_predictor_buffer_pcCorrected; + wire IBusCachedPlugin_predictor_buffer_hazard; + reg [19:0] IBusCachedPlugin_predictor_line_source; + reg [1:0] IBusCachedPlugin_predictor_line_branchWish; + reg [31:0] IBusCachedPlugin_predictor_line_target; + reg IBusCachedPlugin_predictor_buffer_hazard_regNextWhen; + wire IBusCachedPlugin_predictor_hazard; + wire IBusCachedPlugin_predictor_hit; + wire IBusCachedPlugin_predictor_fetchContext_hazard; + wire IBusCachedPlugin_predictor_fetchContext_hit; + wire [19:0] IBusCachedPlugin_predictor_fetchContext_line_source; + wire [1:0] IBusCachedPlugin_predictor_fetchContext_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_fetchContext_line_target; + reg IBusCachedPlugin_predictor_iBusRspContext_hazard; + reg IBusCachedPlugin_predictor_iBusRspContext_hit; + reg [19:0] IBusCachedPlugin_predictor_iBusRspContext_line_source; + reg [1:0] IBusCachedPlugin_predictor_iBusRspContext_line_branchWish; + reg [31:0] IBusCachedPlugin_predictor_iBusRspContext_line_target; + wire IBusCachedPlugin_predictor_iBusRspContextOutput_hazard; + wire IBusCachedPlugin_predictor_iBusRspContextOutput_hit; + wire [19:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_source; + wire [1:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_target; + wire IBusCachedPlugin_predictor_injectorContext_hazard; + wire IBusCachedPlugin_predictor_injectorContext_hit; + wire [19:0] IBusCachedPlugin_predictor_injectorContext_line_source; + wire [1:0] IBusCachedPlugin_predictor_injectorContext_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_injectorContext_line_target; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_147_; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + wire IBusCachedPlugin_s1_bigEndian; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_s2_bigEndian; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire IBusCachedPlugin_rsp_bigEndian; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire dataCache_1__io_mem_cmd_m2sPipe_valid; + wire dataCache_1__io_mem_cmd_m2sPipe_ready; + wire dataCache_1__io_mem_cmd_m2sPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_m2sPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_m2sPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_m2sPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_m2sPipe_payload_length; + wire dataCache_1__io_mem_cmd_m2sPipe_payload_last; + reg dataCache_1__io_mem_cmd_m2sPipe_rValid; + reg dataCache_1__io_mem_cmd_m2sPipe_rData_wr; + reg [31:0] dataCache_1__io_mem_cmd_m2sPipe_rData_address; + reg [31:0] dataCache_1__io_mem_cmd_m2sPipe_rData_data; + reg [3:0] dataCache_1__io_mem_cmd_m2sPipe_rData_mask; + reg [2:0] dataCache_1__io_mem_cmd_m2sPipe_rData_length; + reg dataCache_1__io_mem_cmd_m2sPipe_rData_last; + wire [31:0] _zz_148_; + reg [31:0] DBusCachedPlugin_rspCounter; + wire execute_DBusCachedPlugin_bigEndian; + reg [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_149_; + wire [15:0] _zz_150_; + wire [15:0] _zz_151_; + reg [31:0] _zz_152_; + wire writeBack_DBusCachedPlugin_bigEndian; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg [15:0] writeBack_DBusCachedPlugin_rspHW; + wire [15:0] _zz_153_; + wire [15:0] _zz_154_; + wire _zz_155_; + reg [15:0] _zz_156_; + wire [79:0] _zz_157_; + wire _zz_158_; + wire _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire _zz_163_; + wire _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire _zz_169_; + wire _zz_170_; + wire _zz_171_; + wire _zz_172_; + wire _zz_173_; + wire _zz_174_; + wire _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + wire _zz_189_; + wire _zz_190_; + wire _zz_191_; + wire _zz_192_; + wire _zz_193_; + wire _zz_194_; + wire _zz_195_; + wire _zz_196_; + wire _zz_197_; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + wire _zz_201_; + wire _zz_202_; + wire _zz_203_; + wire _zz_204_; + wire _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire _zz_208_; + wire _zz_209_; + wire _zz_210_; + wire _zz_211_; + wire _zz_212_; + wire _zz_213_; + wire _zz_214_; + wire _zz_215_; + wire _zz_216_; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + wire _zz_220_; + wire _zz_221_; + wire _zz_222_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_223_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_224_; + wire `DataSizeEnum_defaultEncoding_type _zz_225_; + wire `AluCtrlEnum_defaultEncoding_type _zz_226_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_227_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_228_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_229_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_230_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_231_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_232_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_233_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_234_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_235_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_236_; + reg _zz_237_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_raData_pre; + wire [31:0] decode_RegFilePlugin_rbData_pre; + wire [4:0] decode_RegFilePlugin_regFileReadAddress3; + wire [31:0] decode_RegFilePlugin_rsData; + reg [31:0] decode_RegFilePlugin_raData; + reg [31:0] decode_RegFilePlugin_rbData; + reg [4:0] _zz_238_; + reg [4:0] _zz_239_; + reg [4:0] _zz_240_; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + wire UpdateRegFileWrite_valid /* verilator public */ ; + wire UpdateRegFileWrite_payload_valid /* verilator public */ ; + wire [4:0] UpdateRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] UpdateRegFileWrite_payload_data /* verilator public */ ; + reg writeBack_RegFilePlugin_crBusPort_valid; + reg `CRBusCmdEnum_defaultEncoding_type writeBack_RegFilePlugin_crBusPort_payload_op; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_ba; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_bb; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_bt; + reg [31:0] writeBack_RegFilePlugin_crBusPort_payload_imm; + wire [7:0] writeBack_RegFilePlugin_crBusPort_payload_fxm; + reg writeBack_RegFilePlugin_xerBusPort_valid; + wire writeBack_RegFilePlugin_xerBusPort_payload_validOV; + wire writeBack_RegFilePlugin_xerBusPort_payload_validCA; + wire [1:0] writeBack_RegFilePlugin_xerBusPort_payload_imm; + reg writeBack_RegFilePlugin_sprWriteXERPort_valid; + wire [9:0] writeBack_RegFilePlugin_sprWriteXERPort_payload_id; + wire [31:0] writeBack_RegFilePlugin_sprWriteXERPort_payload_data; + reg writeBack_RegFilePlugin_sprWriteCLTPort_valid; + wire [9:0] writeBack_RegFilePlugin_sprWriteCLTPort_payload_id; + wire [31:0] writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + reg _zz_241_; + reg _zz_242_; + reg _zz_243_; + reg [1:0] _zz_244_; + reg _zz_245_; + reg [31:0] ALU2_XER; + reg ALU2_sprReadValid; + wire _zz_246_; + reg [23:0] _zz_247_; + wire _zz_248_; + reg [15:0] _zz_249_; + reg [31:0] ALU2_bitwise; + reg [1:0] ALU2_bitwise_enc_cr; + reg [2:0] ALU2_bitwise_cr; + reg [4:0] ALU2_amount; + wire [4:0] ALU2_maskMB; + wire [4:0] ALU2_maskME; + reg [31:0] ALU2_mask; + reg [31:0] ALU2_maskNorm; + reg [31:0] ALU2_maskInvt; + wire [31:0] ALU2_rimi; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + reg [31:0] _zz_252_; + reg ALU2_sraw_ca; + wire [31:0] ALU2_sraw_wtf; + reg [1:0] ALU2_rimi_enc_cr; + reg [2:0] ALU2_rimi_cr; + reg [5:0] cntzero_lz; + reg [31:0] _zz_253_; + reg [5:0] cntzero_msb; + reg [5:0] cntzero_tz; + reg [5:0] cntzero_lsb; + wire [3:0] popcnt_pb0; + wire [3:0] popcnt_pb1; + wire [3:0] popcnt_pb2; + wire [3:0] popcnt_pb3; + wire [7:0] _zz_254_; + wire [7:0] _zz_255_; + wire [7:0] _zz_256_; + wire [7:0] _zz_257_; + wire [5:0] popcnt_pw0; + wire [31:0] _zz_258_; + reg [31:0] popcnt_cmpb; + wire popcnt_prtyw; + reg [31:0] ALU2_spec; + reg [31:0] _zz_259_; + reg _zz_260_; + reg _zz_261_; + reg [31:0] _zz_262_; + reg [4:0] _zz_263_; + reg ALU2_xer_ca; + wire ALU2_xer_ov; + wire ALU2_xer_so; + wire ALU2_xerBus_validOV; + wire ALU2_xerBus_validCA; + wire [1:0] ALU2_xerBus_imm; + reg [2:0] ALU2_alu_cr; + reg [2:0] ALU2_cr0_val_a; + wire [3:0] ALU2_cr0_val; + wire ALU2_cr_record; + wire ALU2_cr_mcrf; + wire ALU2_cr_update_valid; + reg `CRBusCmdEnum_defaultEncoding_type ALU2_crBus_op; + reg [4:0] ALU2_crBus_ba; + reg [4:0] ALU2_crBus_bb; + reg [4:0] ALU2_crBus_bt; + reg [31:0] ALU2_crBus_imm; + reg [7:0] ALU2_crBus_fxm; + wire [4:0] SRC1_ra; + wire [4:0] SRC1_rb; + wire [4:0] SRC1_rs; + wire [4:0] SRC1_rt; + reg [31:0] _zz_264_; + wire _zz_265_; + reg [15:0] _zz_266_; + reg [31:0] _zz_267_; + reg [0:0] _zz_268_; + wire [32:0] SRC2_adder; + wire [31:0] SRC2_ra; + wire [31:0] SRC2_rb; + wire [0:0] SRC2_cin; + wire [1:0] SRC2_add_cr; + wire [1:0] SRC2_cmp_cr; + wire SRC2_ca; + wire SRC2_ov; + reg _zz_269_; + reg [4:0] _zz_270_; + reg [31:0] _zz_271_; + reg _zz_272_; + reg `CRBusCmdEnum_defaultEncoding_type _zz_273_; + reg [31:0] _zz_274_; + wire MUL1_aSigned; + wire MUL1_bSigned; + wire [31:0] MUL1_a; + wire [31:0] MUL1_b; + wire [15:0] MUL1_aULow; + wire [15:0] MUL1_bULow; + wire [16:0] MUL1_aSLow; + wire [16:0] MUL1_bSLow; + wire [16:0] MUL1_aHigh; + wire [16:0] MUL1_bHigh; + wire [65:0] MUL3_result; + wire MUL3_xer_ov; + reg MUL3_xer_so; + reg [31:0] MUL3_result32; + wire [1:0] MUL3_cr; + reg [3:0] MUL3_cr_decode; + wire MUL3_cr_record; + reg [32:0] MULDIV_rs1; + reg [31:0] MULDIV_rs2; + reg [64:0] MULDIV_accumulator; + wire MULDIV_frontendOk; + reg MULDIV1_needRevert; + reg MULDIV1_counter_willIncrement; + reg MULDIV1_counter_willClear; + reg [5:0] MULDIV1_counter_valueNext; + reg [5:0] MULDIV1_counter_value; + wire MULDIV1_counter_willOverflowIfInc; + wire MULDIV1_counter_willOverflow; + reg MULDIV1_done; + reg [31:0] MULDIV1_result; + reg MULDIV1_crBusPort_valid; + reg `CRBusCmdEnum_defaultEncoding_type MULDIV1_crBusPort_payload_op; + wire [4:0] MULDIV1_crBusPort_payload_ba; + wire [4:0] MULDIV1_crBusPort_payload_bb; + wire [4:0] MULDIV1_crBusPort_payload_bt; + reg [31:0] MULDIV1_crBusPort_payload_imm; + wire [7:0] MULDIV1_crBusPort_payload_fxm; + reg MULDIV1_xerBusPort_valid; + reg MULDIV1_xerBusPort_payload_validOV; + reg MULDIV1_xerBusPort_payload_validCA; + reg [1:0] MULDIV1_xerBusPort_payload_imm; + wire [31:0] _zz_275_; + wire [32:0] MULDIV1_stage_0_remainderShifted; + wire [32:0] MULDIV1_stage_0_remainderMinusDenominator; + wire [31:0] MULDIV1_stage_0_outRemainder; + wire [31:0] MULDIV1_stage_0_outNumerator; + wire [31:0] _zz_276_; + wire _zz_277_; + reg _zz_278_; + reg [3:0] _zz_279_; + wire _zz_280_; + wire _zz_281_; + reg [32:0] _zz_282_; + reg _zz_283_ /* verilator public */ ; + reg _zz_284_ /* verilator public */ ; + reg _zz_285_ /* verilator public */ ; + wire Hazards_writeBackWrites_valid; + wire [4:0] Hazards_writeBackWrites_payload_address; + wire [31:0] Hazards_writeBackWrites_payload_data; + reg Hazards_writeBackBuffer_valid; + reg [4:0] Hazards_writeBackBuffer_payload_address; + reg [31:0] Hazards_writeBackBuffer_payload_data; + wire Hazards_addr0Match; + wire Hazards_addr1Match; + wire Hazards_addr2Match; + wire _zz_286_; + wire _zz_287_; + wire _zz_288_; + wire _zz_289_; + wire _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire _zz_293_; + wire _zz_294_; + wire _zz_295_; + reg _zz_296_; + reg _zz_297_; + reg _zz_298_; + reg _zz_299_; + reg _zz_300_; + reg _zz_301_; + reg _zz_302_; + reg _zz_303_; + reg [3:0] _zz_304_; + reg _zz_305_; + reg _zz_306_; + reg _zz_307_; + wire _zz_308_; + reg _zz_309_; + reg _zz_310_; + wire _zz_311_; + reg _zz_312_; + reg _zz_313_; + reg _zz_314_; + reg _zz_315_; + reg _zz_316_; + reg _zz_317_; + reg _zz_318_; + reg _zz_319_; + reg [3:0] _zz_320_; + reg _zz_321_; + reg _zz_322_; + wire _zz_323_; + reg _zz_324_; + reg _zz_325_; + wire _zz_326_; + reg decode_BranchPlugin_bc; + wire [4:0] decode_BranchPlugin_bi; + wire [2:0] decode_BranchPlugin_crbiField; + wire [4:0] decode_BranchPlugin_bo; + wire decode_BranchPlugin_crbiRead; + reg [7:0] decode_BranchPlugin_crFieldRd; + reg [31:0] execute_BranchPlugin_CR; + reg [31:0] execute_BranchPlugin_CTR; + reg [31:0] execute_BranchPlugin_LR; + reg [31:0] execute_BranchPlugin_TAR; + wire execute_BranchPlugin_ctrOne; + reg [31:0] execute_BranchPlugin_sprReadData; + reg execute_BranchPlugin_sprReadValid; + reg execute_BranchPlugin_crReadValid; + reg `CRBusCmdEnum_defaultEncoding_type execute_BranchPlugin_crBusPort_op; + reg [4:0] execute_BranchPlugin_crBusPort_ba; + reg [4:0] execute_BranchPlugin_crBusPort_bb; + reg [4:0] execute_BranchPlugin_crBusPort_bt; + reg [31:0] execute_BranchPlugin_crBusPort_imm; + reg [7:0] execute_BranchPlugin_crBusPort_fxm; + wire execute_BranchPlugin_crBusPort_valid; + reg [3:0] _zz_327_; + wire [3:0] _zz_328_; + wire _zz_329_; + reg [5:0] _zz_330_; + wire [31:0] execute_BranchPlugin_li; + wire _zz_331_; + reg [15:0] _zz_332_; + wire [31:0] execute_BranchPlugin_bd; + wire _zz_333_; + reg [31:0] execute_BranchPlugin_aaMask; + reg [31:0] execute_BranchPlugin_branch_tgt0; + reg [31:0] execute_BranchPlugin_branch_tgt1; + wire execute_BranchPlugin_use_li; + wire [31:0] execute_BranchPlugin_branch_tgt2; + reg [31:0] execute_BranchPlugin_branchAdder; + wire [4:0] execute_BranchPlugin_opbi; + wire [2:0] execute_BranchPlugin_crbiField; + wire [1:0] execute_BranchPlugin_crbiBit; + reg execute_BranchPlugin_crbi; + wire execute_BranchPlugin_ctrOK; + wire [4:0] execute_BranchPlugin_bo; + reg [3:0] execute_BranchPlugin_crBypassPort_field; + wire [0:0] execute_BranchPlugin_crBypassPort_stageID; + wire execute_BranchPlugin_crBypassPort_valid; + wire execute_BranchPlugin_condOK; + wire execute_BranchPlugin_lk; + reg _zz_334_; + reg _zz_335_; + reg _zz_336_; + wire memory_BranchPlugin_predictionMissmatch; + reg MSR_VEC; + reg MSR_VSX; + reg MSR_EE; + reg MSR_PR; + reg MSR_FP; + reg MSR_ME; + reg MSR_FE0; + reg MSR_FE1; + reg MSR_IR; + reg MSR_DR; + reg MSR_PMM; + reg MSR_RI; + reg MSR_LE; + reg [31:0] SPRPlugin_srr0; + reg [31:0] SPRPlugin_srr1; + reg [31:0] SPRPlugin_dar; + reg [31:0] SPRPlugin_sprg3; + reg [31:0] SPRPlugin_dsisr; + (* ram_style = "block" *) reg [31:0] SPRPlugin_tb; + wire SPRPlugin_incTB; + (* ram_style = "block" *) reg [31:0] SPRPlugin_dec; + reg SPRPlugin_dec31Prev; + reg SPRPlugin_intDec; + reg SPRPlugin_intDecTkn; + reg [31:0] SPRPlugin_minstret; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_decode; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_execute; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_memory; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] SPRPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC; + reg [6:0] SPRPlugin_exceptionPortCtrl_exceptionContext_imm; + wire `ExcpEnum_defaultEncoding_type _zz_337_; + wire [1:0] _zz_338_; + wire _zz_339_; + wire `ExcpEnum_defaultEncoding_type _zz_340_; + reg _zz_341_; + reg _zz_342_; + reg _zz_343_; + reg _zz_344_; + reg SPRPlugin_interrupt_valid; + reg [3:0] SPRPlugin_interrupt_code /* verilator public */ ; + reg [1:0] SPRPlugin_interrupt_targetPrivilege; + reg SPRPlugin_pipelineLiberator_pcValids_0; + reg SPRPlugin_pipelineLiberator_pcValids_1; + reg SPRPlugin_pipelineLiberator_pcValids_2; + wire SPRPlugin_pipelineLiberator_active; + reg SPRPlugin_pipelineLiberator_done; + wire SPRPlugin_exception; + reg [31:0] SPRPlugin_darSave; + reg SPRPlugin_hadException; + reg SPRPlugin_interruptJump /* verilator public */ ; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_intType; + reg [31:0] SPRPlugin_intSRR0; + reg [31:0] _zz_345_; + wire execute_SPRPLUGIN_blockedBySideEffects; + reg execute_SPRPLUGIN_sprHere; + reg execute_SPRPLUGIN_illegalAccess; + wire _zz_346_; + reg [15:0] _zz_347_; + wire [31:0] execute_SPRPLUGIN_si; + wire [4:0] execute_SPRPLUGIN_tmask; + reg execute_SPRPLUGIN_trap; + wire [3:0] execute_SPRPLUGIN_opExcp_code; + wire [31:0] execute_SPRPLUGIN_opExcp_badAddr; + wire `ExcpEnum_defaultEncoding_type execute_SPRPLUGIN_opExcp_codePPC; + wire [6:0] execute_SPRPLUGIN_opExcp_imm; + reg _zz_348_; + wire [31:0] execute_SPRPLUGIN_readData; + wire [31:0] execute_SPRPLUGIN_readToWriteData; + wire execute_SPRPLUGIN_sprg3read; + wire execute_SPRPLUGIN_privViolation; + wire execute_SPRPLUGIN_readInstruction; + wire execute_SPRPLUGIN_readEnable; + wire execute_SPRPLUGIN_writeInstruction; + wire execute_SPRPLUGIN_writeEnable; + reg [10:0] execute_SPRPLUGIN_SPRAddress; + reg [31:0] decode_to_execute_RB; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg decode_to_execute_DECODER_stageables_28; + reg `AluRimiAmtEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_44; + reg [10:0] execute_to_memory_SPR_ID; + reg [10:0] memory_to_writeBack_SPR_ID; + reg decode_to_execute_DECODER_stageables_36; + reg execute_to_memory_DECODER_stageables_36; + reg memory_to_writeBack_DECODER_stageables_36; + reg decode_to_execute_PREDICTION_CONTEXT_hazard; + reg decode_to_execute_PREDICTION_CONTEXT_hit; + reg [19:0] decode_to_execute_PREDICTION_CONTEXT_line_source; + reg [1:0] decode_to_execute_PREDICTION_CONTEXT_line_branchWish; + reg [31:0] decode_to_execute_PREDICTION_CONTEXT_line_target; + reg execute_to_memory_PREDICTION_CONTEXT_hazard; + reg execute_to_memory_PREDICTION_CONTEXT_hit; + reg [19:0] execute_to_memory_PREDICTION_CONTEXT_line_source; + reg [1:0] execute_to_memory_PREDICTION_CONTEXT_line_branchWish; + reg [31:0] execute_to_memory_PREDICTION_CONTEXT_line_target; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_49; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_DECODER_stageables_49; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_DECODER_stageables_49; + reg decode_to_execute_DECODER_stageables_48; + reg execute_to_memory_XER_WRITE_validOV; + reg execute_to_memory_XER_WRITE_validCA; + reg [1:0] execute_to_memory_XER_WRITE_imm; + reg memory_to_writeBack_XER_WRITE_validOV; + reg memory_to_writeBack_XER_WRITE_validCA; + reg [1:0] memory_to_writeBack_XER_WRITE_imm; + reg [31:0] execute_to_memory_LOAD_UPDATE_DATA; + reg [31:0] memory_to_writeBack_LOAD_UPDATE_DATA; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_13; + reg decode_to_execute_DECODER_stageables_55; + reg execute_to_memory_DECODER_stageables_55; + reg memory_to_writeBack_DECODER_stageables_55; + reg decode_to_execute_DECODER_stageables_57; + reg `CRLogCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_20; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg decode_to_execute_DECODER_stageables_54; + reg decode_to_execute_DECODER_stageables_32; + reg execute_to_memory_DECODER_stageables_32; + reg memory_to_writeBack_DECODER_stageables_32; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_DECODER_stageables_22; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_MUL_LL; + reg [4:0] execute_to_memory_LOAD_UPDATE_ADDR; + reg [4:0] memory_to_writeBack_LOAD_UPDATE_ADDR; + reg decode_to_execute_DECODER_stageables_30; + reg decode_to_execute_DECODER_stageables_52; + reg execute_to_memory_DECODER_stageables_52; + reg memory_to_writeBack_DECODER_stageables_52; + reg [4:0] decode_to_execute_R0_ADDR; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg decode_to_execute_DECODER_stageables_11; + reg `AluRimiCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_16; + reg decode_to_execute_DECODER_stageables_56; + reg execute_to_memory_DECODER_stageables_56; + reg memory_to_writeBack_DECODER_stageables_56; + reg decode_to_execute_DECODER_stageables_39; + reg execute_to_memory_DECODER_stageables_39; + reg memory_to_writeBack_DECODER_stageables_39; + reg execute_to_memory_BRANCH_DO; + reg execute_to_memory_BRANCH_LINK; + reg memory_to_writeBack_BRANCH_LINK; + reg `AluSpecCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_0; + reg decode_to_execute_DECODER_stageables_15; + reg execute_to_memory_DECODER_stageables_15; + reg decode_to_execute_DECODER_stageables_5; + reg execute_to_memory_DECODER_stageables_5; + reg `CRBusCmdEnum_defaultEncoding_type execute_to_memory_CR_WRITE_op; + reg [4:0] execute_to_memory_CR_WRITE_ba; + reg [4:0] execute_to_memory_CR_WRITE_bb; + reg [4:0] execute_to_memory_CR_WRITE_bt; + reg [31:0] execute_to_memory_CR_WRITE_imm; + reg [7:0] execute_to_memory_CR_WRITE_fxm; + reg `CRBusCmdEnum_defaultEncoding_type memory_to_writeBack_CR_WRITE_op; + reg [4:0] memory_to_writeBack_CR_WRITE_ba; + reg [4:0] memory_to_writeBack_CR_WRITE_bb; + reg [4:0] memory_to_writeBack_CR_WRITE_bt; + reg [31:0] memory_to_writeBack_CR_WRITE_imm; + reg [7:0] memory_to_writeBack_CR_WRITE_fxm; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg decode_to_execute_DECODER_stageables_42; + reg [4:0] decode_to_execute_RT_ADDR; + reg [4:0] execute_to_memory_RT_ADDR; + reg [4:0] memory_to_writeBack_RT_ADDR; + reg decode_to_execute_DECODER_stageables_45; + reg execute_to_memory_DECODER_stageables_45; + reg memory_to_writeBack_DECODER_stageables_45; + reg decode_to_execute_DECODER_stageables_9; + reg execute_to_memory_DECODER_stageables_9; + reg memory_to_writeBack_DECODER_stageables_9; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_19; + reg decode_to_execute_DECODER_stageables_18; + reg decode_to_execute_DECODER_stageables_34; + reg decode_to_execute_DECODER_stageables_24; + reg execute_to_memory_DECODER_stageables_24; + reg memory_to_writeBack_DECODER_stageables_24; + reg `EndianEnum_defaultEncoding_type decode_to_execute_MSR_ENDIAN; + reg `EndianEnum_defaultEncoding_type execute_to_memory_MSR_ENDIAN; + reg `EndianEnum_defaultEncoding_type memory_to_writeBack_MSR_ENDIAN; + reg [31:0] execute_to_memory_SRC1; + reg [31:0] memory_to_writeBack_SRC1; + reg decode_to_execute_DECODER_stageables_14; + reg decode_to_execute_DECODER_stageables_3; + reg [1:0] execute_to_memory_SRC_CR; + reg [1:0] memory_to_writeBack_SRC_CR; + reg execute_to_memory_BRANCH_DEC; + reg memory_to_writeBack_BRANCH_DEC; + reg [31:0] decode_to_execute_RA; + reg decode_to_execute_DECODER_stageables_2; + reg decode_to_execute_DECODER_stageables_6; + reg decode_to_execute_DECODER_stageables_40; + reg [33:0] execute_to_memory_MUL_LH; + reg decode_to_execute_DECODER_stageables_31; + reg execute_to_memory_DECODER_stageables_31; + reg memory_to_writeBack_DECODER_stageables_31; + reg execute_to_memory_TARGET_MISSMATCH2; + reg decode_to_execute_DECODER_stageables_35; + reg [4:0] execute_to_memory_REGFILE_WRITE_ADDR; + reg [4:0] memory_to_writeBack_REGFILE_WRITE_ADDR; + reg [33:0] execute_to_memory_MUL_HL; + reg decode_to_execute_DECODER_stageables_53; + reg execute_to_memory_DECODER_stageables_53; + reg memory_to_writeBack_DECODER_stageables_53; + reg `CRMoveCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_51; + reg `DataSizeEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_7; + reg `DataSizeEnum_defaultEncoding_type execute_to_memory_DECODER_stageables_7; + reg `DataSizeEnum_defaultEncoding_type memory_to_writeBack_DECODER_stageables_7; + reg [7:0] execute_to_memory_CR_FIELD_WR; + reg [7:0] memory_to_writeBack_CR_FIELD_WR; + reg `Src3CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_1; + reg [31:0] decode_to_execute_RS; + reg decode_to_execute_DECODER_stageables_46; + reg [31:0] execute_to_memory_SRC_ADD; + reg [31:0] memory_to_writeBack_SRC_ADD; + reg decode_to_execute_DECODER_stageables_23; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_8; + reg decode_to_execute_DECODER_stageables_37; + reg execute_to_memory_DECODER_stageables_37; + reg decode_to_execute_DECODER_stageables_21; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_26; + reg [7:0] decode_to_execute_CR_FIELD_RD; + reg decode_to_execute_DECODER_stageables_27; + reg decode_to_execute_DECODER_stageables_43; + reg execute_to_memory_DECODER_stageables_43; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_38; + reg execute_to_memory_XER_SO; + reg memory_to_writeBack_XER_SO; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] execute_to_memory_NEXT_PC2; + reg decode_to_execute_DECODER_stageables_25; + reg decode_to_execute_DECODER_stageables_29; + reg `TgtCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_12; + reg [10:0] _zz_349_; + reg execute_SPRPLUGIN_SPR_1025; + reg execute_SPRPLUGIN_SPR_26; + reg execute_SPRPLUGIN_SPR_27; + reg execute_SPRPLUGIN_SPR_19; + reg execute_SPRPLUGIN_SPR_259; + reg execute_SPRPLUGIN_SPR_18; + reg execute_SPRPLUGIN_SPR_268; + reg execute_SPRPLUGIN_SPR_22; + reg [31:0] _zz_350_; + reg [31:0] _zz_351_; + reg [31:0] _zz_352_; + reg [31:0] _zz_353_; + reg [31:0] _zz_354_; + reg [31:0] _zz_355_; + reg [31:0] _zz_356_; + reg [31:0] _zz_357_; + reg [2:0] _zz_358_; + reg _zz_359_; + reg [31:0] iBusWB_DAT_MISO_regNext; + reg [2:0] _zz_360_; + wire _zz_361_; + wire _zz_362_; + wire _zz_363_; + wire _zz_364_; + wire _zz_365_; + reg _zz_366_; + reg [31:0] dBusWB_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [15:0] _zz_1__string; + reg [15:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [47:0] _zz_4__string; + reg [63:0] _zz_5__string; + reg [63:0] _zz_6__string; + reg [39:0] decode_DECODER_stageables_8_string; + reg [39:0] _zz_7__string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [31:0] decode_DECODER_stageables_1_string; + reg [31:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [15:0] memory_DECODER_stageables_7_string; + reg [15:0] _zz_13__string; + reg [15:0] _zz_14__string; + reg [15:0] _zz_15__string; + reg [15:0] _zz_16__string; + reg [15:0] _zz_17__string; + reg [15:0] decode_DECODER_stageables_7_string; + reg [15:0] _zz_18__string; + reg [15:0] _zz_19__string; + reg [15:0] _zz_20__string; + reg [47:0] decode_DECODER_stageables_51_string; + reg [47:0] _zz_21__string; + reg [47:0] _zz_22__string; + reg [47:0] _zz_23__string; + reg [15:0] memory_MSR_ENDIAN_string; + reg [15:0] _zz_24__string; + reg [15:0] _zz_25__string; + reg [15:0] _zz_26__string; + reg [15:0] _zz_27__string; + reg [15:0] _zz_28__string; + reg [15:0] _zz_29__string; + reg [15:0] _zz_30__string; + reg [47:0] decode_DECODER_stageables_19_string; + reg [47:0] _zz_31__string; + reg [47:0] _zz_32__string; + reg [47:0] _zz_33__string; + reg [47:0] _zz_34__string; + reg [47:0] _zz_35__string; + reg [47:0] execute_CR_WRITE_op_string; + reg [47:0] _zz_36__string; + reg [47:0] _zz_37__string; + reg [47:0] _zz_38__string; + reg [55:0] decode_DECODER_stageables_0_string; + reg [55:0] _zz_39__string; + reg [55:0] _zz_40__string; + reg [55:0] _zz_41__string; + reg [55:0] decode_DECODER_stageables_16_string; + reg [55:0] _zz_42__string; + reg [55:0] _zz_43__string; + reg [55:0] _zz_44__string; + reg [47:0] decode_DECODER_stageables_20_string; + reg [47:0] _zz_45__string; + reg [47:0] _zz_46__string; + reg [47:0] _zz_47__string; + reg [39:0] _zz_48__string; + reg [39:0] _zz_49__string; + reg [39:0] memory_DECODER_stageables_49_string; + reg [39:0] _zz_50__string; + reg [39:0] _zz_51__string; + reg [39:0] _zz_52__string; + reg [39:0] decode_DECODER_stageables_49_string; + reg [39:0] _zz_53__string; + reg [39:0] _zz_54__string; + reg [39:0] _zz_55__string; + reg [23:0] decode_DECODER_stageables_44_string; + reg [23:0] _zz_56__string; + reg [23:0] _zz_57__string; + reg [23:0] _zz_58__string; + reg [39:0] writeBack_DECODER_stageables_49_string; + reg [39:0] _zz_59__string; + reg [39:0] _zz_60__string; + reg [39:0] _zz_61__string; + reg [39:0] execute_DECODER_stageables_49_string; + reg [39:0] _zz_62__string; + reg [15:0] _zz_63__string; + reg [39:0] decode_DECODER_stageables_13_string; + reg [39:0] _zz_65__string; + reg [47:0] memory_CR_WRITE_op_string; + reg [47:0] _zz_66__string; + reg [39:0] execute_DECODER_stageables_13_string; + reg [39:0] _zz_67__string; + reg [31:0] execute_DECODER_stageables_1_string; + reg [31:0] _zz_70__string; + reg [63:0] execute_DECODER_stageables_26_string; + reg [63:0] _zz_71__string; + reg [47:0] execute_DECODER_stageables_38_string; + reg [47:0] _zz_74__string; + reg [47:0] _zz_76__string; + reg [47:0] execute_DECODER_stageables_20_string; + reg [47:0] _zz_77__string; + reg [47:0] execute_DECODER_stageables_51_string; + reg [47:0] _zz_78__string; + reg [15:0] execute_DECODER_stageables_12_string; + reg [15:0] _zz_80__string; + reg [39:0] execute_DECODER_stageables_8_string; + reg [39:0] _zz_81__string; + reg [55:0] execute_DECODER_stageables_0_string; + reg [55:0] _zz_82__string; + reg [55:0] execute_DECODER_stageables_16_string; + reg [55:0] _zz_98__string; + reg [23:0] execute_DECODER_stageables_44_string; + reg [23:0] _zz_99__string; + reg [47:0] execute_DECODER_stageables_19_string; + reg [47:0] _zz_100__string; + reg [47:0] writeBack_CR_WRITE_op_string; + reg [47:0] _zz_101__string; + reg [15:0] decode_DECODER_stageables_12_string; + reg [15:0] _zz_104__string; + reg [63:0] decode_DECODER_stageables_26_string; + reg [63:0] _zz_105__string; + reg [47:0] decode_DECODER_stageables_38_string; + reg [47:0] _zz_106__string; + reg [47:0] _zz_107__string; + reg [39:0] _zz_108__string; + reg [23:0] _zz_109__string; + reg [47:0] _zz_110__string; + reg [63:0] _zz_111__string; + reg [47:0] _zz_112__string; + reg [47:0] _zz_113__string; + reg [55:0] _zz_114__string; + reg [39:0] _zz_115__string; + reg [15:0] _zz_116__string; + reg [39:0] _zz_117__string; + reg [15:0] _zz_118__string; + reg [31:0] _zz_119__string; + reg [55:0] _zz_120__string; + reg [15:0] writeBack_DATA_SIZE_string; + reg [15:0] _zz_122__string; + reg [15:0] writeBack_MSR_ENDIAN_string; + reg [15:0] _zz_123__string; + reg [15:0] execute_DATA_SIZE_string; + reg [15:0] _zz_125__string; + reg [15:0] execute_MSR_ENDIAN_string; + reg [15:0] _zz_126__string; + reg [15:0] decode_MSR_ENDIAN_string; + reg [15:0] _zz_129__string; + reg [63:0] IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string; + reg [63:0] DBusCachedPlugin_exceptionBus_payload_codePPC_string; + reg [63:0] decodeExceptionPort_payload_codePPC_string; + reg [63:0] BranchPlugin_branchExceptionPort_payload_codePPC_string; + reg [63:0] SPRPlugin_selfException_payload_codePPC_string; + reg [55:0] _zz_223__string; + reg [31:0] _zz_224__string; + reg [15:0] _zz_225__string; + reg [39:0] _zz_226__string; + reg [15:0] _zz_227__string; + reg [39:0] _zz_228__string; + reg [55:0] _zz_229__string; + reg [47:0] _zz_230__string; + reg [47:0] _zz_231__string; + reg [63:0] _zz_232__string; + reg [47:0] _zz_233__string; + reg [23:0] _zz_234__string; + reg [39:0] _zz_235__string; + reg [47:0] _zz_236__string; + reg [47:0] writeBack_RegFilePlugin_crBusPort_payload_op_string; + reg [47:0] ALU2_crBus_op_string; + reg [47:0] _zz_273__string; + reg [47:0] MULDIV1_crBusPort_payload_op_string; + reg [47:0] execute_BranchPlugin_crBusPort_op_string; + reg [63:0] SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string; + reg [63:0] _zz_337__string; + reg [63:0] _zz_340__string; + reg [63:0] SPRPlugin_intType_string; + reg [63:0] execute_SPRPLUGIN_opExcp_codePPC_string; + reg [23:0] decode_to_execute_DECODER_stageables_44_string; + reg [39:0] decode_to_execute_DECODER_stageables_49_string; + reg [39:0] execute_to_memory_DECODER_stageables_49_string; + reg [39:0] memory_to_writeBack_DECODER_stageables_49_string; + reg [39:0] decode_to_execute_DECODER_stageables_13_string; + reg [47:0] decode_to_execute_DECODER_stageables_20_string; + reg [55:0] decode_to_execute_DECODER_stageables_16_string; + reg [55:0] decode_to_execute_DECODER_stageables_0_string; + reg [47:0] execute_to_memory_CR_WRITE_op_string; + reg [47:0] memory_to_writeBack_CR_WRITE_op_string; + reg [47:0] decode_to_execute_DECODER_stageables_19_string; + reg [15:0] decode_to_execute_MSR_ENDIAN_string; + reg [15:0] execute_to_memory_MSR_ENDIAN_string; + reg [15:0] memory_to_writeBack_MSR_ENDIAN_string; + reg [47:0] decode_to_execute_DECODER_stageables_51_string; + reg [15:0] decode_to_execute_DECODER_stageables_7_string; + reg [15:0] execute_to_memory_DECODER_stageables_7_string; + reg [15:0] memory_to_writeBack_DECODER_stageables_7_string; + reg [31:0] decode_to_execute_DECODER_stageables_1_string; + reg [39:0] decode_to_execute_DECODER_stageables_8_string; + reg [63:0] decode_to_execute_DECODER_stageables_26_string; + reg [47:0] decode_to_execute_DECODER_stageables_38_string; + reg [15:0] decode_to_execute_DECODER_stageables_12_string; + `endif + + reg [53:0] IBusCachedPlugin_predictor_history [0:1023]; + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + function [6:0] zz_SPRPlugin_selfException_payload_imm(input dummy); + begin + zz_SPRPlugin_selfException_payload_imm = 7'h0; + zz_SPRPlugin_selfException_payload_imm = 7'h0; + end + endfunction + wire [6:0] _zz_1588_; + + assign _zz_394_ = (execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TW); + assign _zz_395_ = (writeBack_arbitration_isValid && writeBack_DECODER_stageables_45); + assign _zz_396_ = 1'b1; + assign _zz_397_ = (memory_arbitration_isValid && memory_DECODER_stageables_45); + assign _zz_398_ = (execute_arbitration_isValid && execute_DECODER_stageables_45); + assign _zz_399_ = (memory_arbitration_isValid && memory_DECODER_stageables_43); + assign _zz_400_ = (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_31); + assign _zz_401_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_127__3)); + assign _zz_402_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_127__2)); + assign _zz_403_ = ((_zz_372_ && (! IBusCachedPlugin_cache_io_cpu_decode_mmuException)) && (! _zz_127__1)); + assign _zz_404_ = IBusCachedPlugin_cache_io_cpu_decode_exceptionType[0]; + assign _zz_405_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_127__0)); + assign _zz_406_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_407_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_408_ = (SPRPlugin_hadException || SPRPlugin_interruptJump); + assign _zz_409_ = (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_39); + assign _zz_410_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_SC)); + assign _zz_411_ = (writeBack_arbitration_isFiring && ((writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TW) || (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TWI))); + assign _zz_412_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_SCV)); + assign _zz_413_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_RFI)); + assign _zz_414_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_RFSCV)); + assign _zz_415_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_416_ = ((! dataCache_1__io_cpu_writeBack_mmuException) && dataCache_1__io_cpu_writeBack_exceptionType[0]); + assign _zz_417_ = ((! dataCache_1__io_cpu_writeBack_exceptionType[3]) && (! writeBack_MEMORY_WR)); + assign _zz_418_ = ((! dataCache_1__io_cpu_writeBack_exceptionType[2]) && writeBack_MEMORY_WR); + assign _zz_419_ = (! decode_LEGAL_INSTRUCTION); + assign _zz_420_ = (decode && SPRPlugin_msr_pr); + assign _zz_421_ = (! UpdateRegFileWrite_valid); + assign _zz_422_ = (MULDIV_frontendOk && (! MULDIV1_done)); + assign _zz_423_ = (! memory_arbitration_isStuck); + assign _zz_424_ = (memory_DECODER_stageables_37 && memory_INSTRUCTION[10]); + assign _zz_425_ = (writeBack_arbitration_isValid && writeBack_DECODER_stageables_45); + assign _zz_426_ = (1'b0 || (! _zz_286_)); + assign _zz_427_ = (memory_arbitration_isValid && memory_DECODER_stageables_45); + assign _zz_428_ = (1'b0 || (! memory_DECODER_stageables_5)); + assign _zz_429_ = (execute_arbitration_isValid && execute_DECODER_stageables_45); + assign _zz_430_ = (1'b0 || (! execute_DECODER_stageables_25)); + assign _zz_431_ = (memory_arbitration_isValid && execute_arbitration_isValid); + assign _zz_432_ = (1'b0 ? (memory_CR_FIELD_WR != 8'h0) : ((memory_CR_FIELD_WR & execute_CR_FIELD_RD) != 8'h0)); + assign _zz_433_ = (1'b1 && (! 1'b0)); + assign _zz_434_ = (writeBack_arbitration_isValid && execute_arbitration_isValid); + assign _zz_435_ = (1'b0 ? (writeBack_CR_FIELD_WR != 8'h0) : ((writeBack_CR_FIELD_WR & execute_CR_FIELD_RD) != 8'h0)); + assign _zz_436_ = (1'b1 && (! 1'b0)); + assign _zz_437_ = (! SPRPlugin_hadException); + assign _zz_438_ = (iBus_cmd_valid || (_zz_358_ != (3'b000))); + assign _zz_439_ = 1'b1; + assign _zz_440_ = (((MSR_EE && SPRPlugin_intDec) && 1'b1) && (! 1'b0)); + assign _zz_441_ = execute_INSTRUCTION[19 : 12]; + assign _zz_442_ = execute_INSTRUCTION[20 : 18]; + assign _zz_443_ = execute_INSTRUCTION[20 : 18]; + assign _zz_444_ = (2'b00); + assign _zz_445_ = (2'b00); + assign _zz_446_ = execute_BranchPlugin_crBusPort_ba[2 : 0]; + assign _zz_447_ = _zz_157_[45 : 45]; + assign _zz_448_ = _zz_157_[39 : 39]; + assign _zz_449_ = _zz_157_[61 : 61]; + assign _zz_450_ = _zz_157_[43 : 43]; + assign _zz_451_ = _zz_157_[35 : 35]; + assign _zz_452_ = _zz_157_[53 : 53]; + assign _zz_453_ = _zz_157_[37 : 37]; + assign _zz_454_ = _zz_157_[64 : 64]; + assign _zz_455_ = _zz_157_[75 : 75]; + assign _zz_456_ = _zz_157_[51 : 51]; + assign _zz_457_ = _zz_157_[47 : 47]; + assign _zz_458_ = _zz_157_[58 : 58]; + assign _zz_459_ = _zz_157_[5 : 5]; + assign _zz_460_ = _zz_157_[6 : 6]; + assign _zz_461_ = _zz_157_[21 : 21]; + assign _zz_462_ = _zz_157_[38 : 38]; + assign _zz_463_ = _zz_157_[50 : 50]; + assign _zz_464_ = _zz_157_[27 : 27]; + assign _zz_465_ = _zz_157_[14 : 14]; + assign _zz_466_ = _zz_157_[63 : 63]; + assign _zz_467_ = _zz_157_[60 : 60]; + assign _zz_468_ = ($signed(_zz_469_) + $signed(_zz_474_)); + assign _zz_469_ = ($signed(_zz_470_) + $signed(_zz_472_)); + assign _zz_470_ = 52'h0; + assign _zz_471_ = {1'b0,memory_MUL_LL}; + assign _zz_472_ = {{19{_zz_471_[32]}}, _zz_471_}; + assign _zz_473_ = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_474_ = {{2{_zz_473_[49]}}, _zz_473_}; + assign _zz_475_ = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_476_ = {{2{_zz_475_[49]}}, _zz_475_}; + assign _zz_477_ = _zz_157_[8 : 8]; + assign _zz_478_ = _zz_157_[22 : 22]; + assign _zz_479_ = _zz_157_[57 : 57]; + assign _zz_480_ = _zz_157_[78 : 78]; + assign _zz_481_ = _zz_157_[16 : 16]; + assign _zz_482_ = _zz_157_[36 : 36]; + assign _zz_483_ = _zz_157_[48 : 48]; + assign _zz_484_ = _zz_157_[76 : 76]; + assign _zz_485_ = _zz_157_[79 : 79]; + assign _zz_486_ = _zz_157_[77 : 77]; + assign _zz_487_ = _zz_157_[66 : 66]; + assign _zz_488_ = _zz_157_[52 : 52]; + assign _zz_489_ = _zz_157_[44 : 44]; + assign _zz_490_ = _zz_157_[9 : 9]; + assign _zz_491_ = _zz_157_[71 : 71]; + assign _zz_492_ = _zz_157_[65 : 65]; + assign _zz_493_ = _zz_157_[15 : 15]; + assign _zz_494_ = _zz_157_[26 : 26]; + assign _zz_495_ = _zz_157_[46 : 46]; + assign _zz_496_ = _zz_157_[74 : 74]; + assign _zz_497_ = _zz_157_[7 : 7]; + assign _zz_498_ = (_zz_132_ - (3'b001)); + assign _zz_499_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_500_ = {29'd0, _zz_499_}; + assign _zz_501_ = _zz_145_[9:0]; + assign _zz_502_ = (IBusCachedPlugin_iBusRsp_stages_1_input_payload >>> 2); + assign _zz_503_ = _zz_502_[9:0]; + assign _zz_504_ = (IBusCachedPlugin_iBusRsp_stages_1_input_payload >>> 12); + assign _zz_505_ = (memory_PREDICTION_CONTEXT_line_branchWish + _zz_507_); + assign _zz_506_ = (memory_PREDICTION_CONTEXT_line_branchWish == (2'b10)); + assign _zz_507_ = {1'd0, _zz_506_}; + assign _zz_508_ = (memory_PREDICTION_CONTEXT_line_branchWish == (2'b01)); + assign _zz_509_ = {1'd0, _zz_508_}; + assign _zz_510_ = (memory_PREDICTION_CONTEXT_line_branchWish - _zz_512_); + assign _zz_511_ = memory_PREDICTION_CONTEXT_line_branchWish[1]; + assign _zz_512_ = {1'd0, _zz_511_}; + assign _zz_513_ = (! memory_PREDICTION_CONTEXT_line_branchWish[1]); + assign _zz_514_ = {1'd0, _zz_513_}; + assign _zz_515_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); + assign _zz_516_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); + assign _zz_517_ = writeBack_SPR_ID; + assign _zz_518_ = (writeBack_PC + 32'h00000004); + assign _zz_519_ = writeBack_SPR_ID; + assign _zz_520_ = (execute_SRC1 <<< ALU2_amount); + assign _zz_521_ = (execute_SRC1 >>> ALU2_amount); + assign _zz_522_ = _zz_523_; + assign _zz_523_ = ($signed(_zz_524_) >>> ALU2_amount); + assign _zz_524_ = execute_SRC1; + assign _zz_525_ = 32'hffffffff; + assign _zz_526_ = _zz_525_; + assign _zz_527_ = (6'h20 - _zz_528_); + assign _zz_528_ = {1'd0, ALU2_amount}; + assign _zz_529_ = sprReadBU_payload_data; + assign _zz_530_ = sprReadBU_payload_data; + assign _zz_531_ = sprReadBU_payload_data; + assign _zz_532_ = sprReadBU_payload_data; + assign _zz_533_ = sprReadBU_payload_data; + assign _zz_534_ = sprReadBU_payload_data; + assign _zz_535_ = sprReadBU_payload_data; + assign _zz_536_ = sprReadBU_payload_data; + assign _zz_537_ = sprReadBU_payload_data; + assign _zz_538_ = sprReadBU_payload_data; + assign _zz_539_ = sprReadBU_payload_data; + assign _zz_540_ = sprReadBU_payload_data; + assign _zz_541_ = sprReadBU_payload_data; + assign _zz_542_ = sprReadBU_payload_data; + assign _zz_543_ = sprReadBU_payload_data; + assign _zz_544_ = sprReadBU_payload_data; + assign _zz_545_ = sprReadBU_payload_data; + assign _zz_546_ = sprReadBU_payload_data; + assign _zz_547_ = sprReadBU_payload_data; + assign _zz_548_ = sprReadBU_payload_data; + assign _zz_549_ = sprReadBU_payload_data; + assign _zz_550_ = sprReadBU_payload_data; + assign _zz_551_ = sprReadBU_payload_data; + assign _zz_552_ = sprReadBU_payload_data; + assign _zz_553_ = sprReadBU_payload_data; + assign _zz_554_ = (5'h1f - execute_INSTRUCTION[10 : 6]); + assign _zz_555_ = ((3'b111) - execute_INSTRUCTION[25 : 23]); + assign _zz_556_ = 32'h0; + assign _zz_557_ = 32'h0; + assign _zz_558_ = 32'hffffffff; + assign _zz_559_ = ({(1'b0),SRC2_ra} + {(1'b0),SRC2_rb}); + assign _zz_560_ = {32'd0, SRC2_cin}; + assign _zz_561_ = SRC2_ra; + assign _zz_562_ = SRC2_rb; + assign _zz_563_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_564_ = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_565_ = MUL3_result[63 : 32]; + assign _zz_566_ = writeBack_MUL_LOW[31 : 0]; + assign _zz_567_ = MULDIV1_counter_willIncrement; + assign _zz_568_ = {5'd0, _zz_567_}; + assign _zz_569_ = {1'd0, MULDIV_rs2}; + assign _zz_570_ = MULDIV1_stage_0_remainderMinusDenominator[31:0]; + assign _zz_571_ = MULDIV1_stage_0_remainderShifted[31:0]; + assign _zz_572_ = {_zz_275_,(! MULDIV1_stage_0_remainderMinusDenominator[32])}; + assign _zz_573_ = _zz_574_; + assign _zz_574_ = _zz_575_; + assign _zz_575_ = ({1'b0,(MULDIV1_needRevert ? (~ _zz_276_) : _zz_276_)} + _zz_577_); + assign _zz_576_ = MULDIV1_needRevert; + assign _zz_577_ = {32'd0, _zz_576_}; + assign _zz_578_ = _zz_281_; + assign _zz_579_ = {32'd0, _zz_578_}; + assign _zz_580_ = _zz_280_; + assign _zz_581_ = {31'd0, _zz_580_}; + assign _zz_582_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_583_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_584_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_585_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_586_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_587_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_588_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_589_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_590_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_591_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_592_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_593_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_594_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_595_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_596_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_597_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_598_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_599_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_600_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_601_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_602_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_603_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_604_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_605_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_606_ = execute_BranchPlugin_li; + assign _zz_607_ = execute_BranchPlugin_bd; + assign _zz_608_ = ($signed(execute_BranchPlugin_branch_tgt1) + $signed(execute_BranchPlugin_branch_tgt2)); + assign _zz_609_ = ($signed(execute_BranchPlugin_branch_tgt1) + $signed(execute_BranchPlugin_branch_tgt2)); + assign _zz_610_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_611_ = (_zz_613_ + 5'h1c); + assign _zz_612_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_613_ = {3'd0, _zz_612_}; + assign _zz_614_ = (_zz_616_ + 5'h18); + assign _zz_615_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_616_ = {3'd0, _zz_615_}; + assign _zz_617_ = (_zz_619_ + 5'h14); + assign _zz_618_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_619_ = {3'd0, _zz_618_}; + assign _zz_620_ = (_zz_622_ + 5'h10); + assign _zz_621_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_622_ = {3'd0, _zz_621_}; + assign _zz_623_ = (_zz_625_ + (4'b1100)); + assign _zz_624_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_625_ = {2'd0, _zz_624_}; + assign _zz_626_ = (_zz_628_ + (4'b1000)); + assign _zz_627_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_628_ = {2'd0, _zz_627_}; + assign _zz_629_ = (_zz_631_ + (3'b100)); + assign _zz_630_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_631_ = {1'd0, _zz_630_}; + assign _zz_632_ = (_zz_633_ + (2'b00)); + assign _zz_633_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_634_ = (_zz_338_ & (~ _zz_635_)); + assign _zz_635_ = (_zz_338_ - (2'b01)); + assign _zz_636_ = execute_SRC1; + assign _zz_637_ = execute_SRC2; + assign _zz_638_ = execute_SRC2; + assign _zz_639_ = execute_SRC1; + assign _zz_640_ = execute_SRC1; + assign _zz_641_ = execute_SPRPLUGIN_si; + assign _zz_642_ = execute_SPRPLUGIN_si; + assign _zz_643_ = execute_SRC1; + assign _zz_644_ = execute_SRC1[23 : 23]; + assign _zz_645_ = execute_SRC1[8 : 8]; + assign _zz_646_ = execute_SRC1[11 : 11]; + assign _zz_647_ = execute_SRC1[2 : 2]; + assign _zz_648_ = execute_SRC1[5 : 5]; + assign _zz_649_ = execute_SRC1[14 : 14]; + assign _zz_650_ = execute_SRC1[13 : 13]; + assign _zz_651_ = execute_SRC1[4 : 4]; + assign _zz_652_ = execute_SRC1[25 : 25]; + assign _zz_653_ = execute_SRC1[1 : 1]; + assign _zz_654_ = execute_SRC1[12 : 12]; + assign _zz_655_ = execute_SRC1[15 : 15]; + assign _zz_656_ = execute_SRC1[0 : 0]; + assign _zz_657_ = (iBus_cmd_payload_address >>> 5); + assign _zz_658_ = {IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target,{IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish,IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source}}; + assign _zz_659_ = 1'b1; + assign _zz_660_ = 1'b1; + assign _zz_661_ = 1'b1; + assign _zz_662_ = {_zz_135_,_zz_134_}; + assign _zz_663_ = ((decode_INSTRUCTION & 32'hb4000000) == 32'h20000000); + assign _zz_664_ = {((decode_INSTRUCTION & 32'hd4000000) == 32'h40000000),{_zz_216_,{_zz_183_,{((decode_INSTRUCTION & 32'hcc100000) == 32'h80100000),{_zz_178_,{_zz_177_,{_zz_189_,{_zz_665_,_zz_666_}}}}}}}}; + assign _zz_665_ = ((decode_INSTRUCTION & 32'hd4100000) == 32'h80100000); + assign _zz_666_ = {_zz_188_,{_zz_185_,{_zz_181_,{_zz_180_,{_zz_179_,{((decode_INSTRUCTION & _zz_667_) == 32'h98020000),{_zz_173_,{_zz_668_,{_zz_669_,_zz_670_}}}}}}}}}; + assign _zz_667_ = 32'hbc020000; + assign _zz_668_ = ((decode_INSTRUCTION & 32'hf8100000) == 32'h38100000); + assign _zz_669_ = _zz_172_; + assign _zz_670_ = {((decode_INSTRUCTION & 32'hbc080000) == 32'h98080000),{((decode_INSTRUCTION & 32'hbc100000) == 32'h98100000),{_zz_175_,{_zz_174_,{(_zz_671_ == _zz_672_),{_zz_673_,{_zz_674_,_zz_675_}}}}}}}; + assign _zz_671_ = (decode_INSTRUCTION & 32'hbc040000); + assign _zz_672_ = 32'h98040000; + assign _zz_673_ = ((decode_INSTRUCTION & 32'hfc200000) == 32'hd8200000); + assign _zz_674_ = _zz_222_; + assign _zz_675_ = {((decode_INSTRUCTION & 32'hfc000003) == 32'h44000001),{((decode_INSTRUCTION & 32'hd41f0000) == 32'h80000000),{((decode_INSTRUCTION & _zz_676_) == 32'h80000000),{(_zz_677_ == _zz_678_),{_zz_679_,{_zz_680_,_zz_681_}}}}}}; + assign _zz_676_ = 32'he41f0000; + assign _zz_677_ = (decode_INSTRUCTION & 32'hcc1f0000); + assign _zz_678_ = 32'h80000000; + assign _zz_679_ = ((decode_INSTRUCTION & 32'hf81f0000) == 32'h38000000); + assign _zz_680_ = ((decode_INSTRUCTION & 32'hfc3e0000) == 32'hd8000000); + assign _zz_681_ = {((decode_INSTRUCTION & 32'hfc00003e) == 32'h4c000004),{((decode_INSTRUCTION & 32'hfc02003e) == 32'h7c02001e),{((decode_INSTRUCTION & _zz_682_) == 32'h7c10001e),{(_zz_683_ == _zz_684_),{_zz_685_,{_zz_686_,_zz_687_}}}}}}; + assign _zz_682_ = 32'hfc10003e; + assign _zz_683_ = (decode_INSTRUCTION & 32'hfc08003e); + assign _zz_684_ = 32'h7c08001e; + assign _zz_685_ = ((decode_INSTRUCTION & 32'hfc04003e) == 32'h7c04001e); + assign _zz_686_ = ((decode_INSTRUCTION & 32'hfc01003e) == 32'h7c01001e); + assign _zz_687_ = {((decode_INSTRUCTION & 32'hfc00033e) == 32'h7c000316),{((decode_INSTRUCTION & 32'hfc0003ba) == 32'h7c000190),{((decode_INSTRUCTION & _zz_688_) == 32'h7c000110),{(_zz_689_ == _zz_690_),{_zz_691_,{_zz_692_,_zz_693_}}}}}}; + assign _zz_688_ = 32'hfc00037a; + assign _zz_689_ = (decode_INSTRUCTION & 32'hfc0003da); + assign _zz_690_ = 32'h7c000010; + assign _zz_691_ = ((decode_INSTRUCTION & 32'hfc00067e) == 32'h7c00006e); + assign _zz_692_ = ((decode_INSTRUCTION & 32'hfc00057e) == 32'h7c00006e); + assign _zz_693_ = {((decode_INSTRUCTION & 32'hfc0004fe) == 32'h7c00006e),{((decode_INSTRUCTION & 32'hfc00073e) == 32'h7c000338),{((decode_INSTRUCTION & _zz_694_) == 32'h7c000038),{(_zz_695_ == _zz_696_),{_zz_697_,{_zz_698_,_zz_699_}}}}}}; + assign _zz_694_ = 32'hfc0005be; + assign _zz_695_ = (decode_INSTRUCTION & 32'hfc0003fc); + assign _zz_696_ = 32'h7c000214; + assign _zz_697_ = ((decode_INSTRUCTION & 32'hfc00037e) == 32'h7c000050); + assign _zz_698_ = ((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000734); + assign _zz_699_ = {((decode_INSTRUCTION & 32'hfc04067e) == 32'h7c04002e),{((decode_INSTRUCTION & 32'hfc02067e) == 32'h7c02002e),{((decode_INSTRUCTION & _zz_700_) == 32'h7c0000f4),{(_zz_701_ == _zz_702_),{_zz_703_,{_zz_704_,_zz_705_}}}}}}; + assign _zz_700_ = 32'hfc0005fe; + assign _zz_701_ = (decode_INSTRUCTION & 32'hfc0804fe); + assign _zz_702_ = 32'h7c08002e; + assign _zz_703_ = ((decode_INSTRUCTION & 32'hfc02057e) == 32'h7c02002e); + assign _zz_704_ = ((decode_INSTRUCTION & 32'hfc04057e) == 32'h7c04002e); + assign _zz_705_ = {((decode_INSTRUCTION & 32'hfc08057e) == 32'h7c08002e),{((decode_INSTRUCTION & 32'hfc01057e) == 32'h7c01002e),{((decode_INSTRUCTION & _zz_706_) == 32'h7c10002e),{(_zz_707_ == _zz_708_),{_zz_709_,{_zz_710_,_zz_711_}}}}}}; + assign _zz_706_ = 32'hfc10067e; + assign _zz_707_ = (decode_INSTRUCTION & 32'hfc0204fe); + assign _zz_708_ = 32'h7c02002e; + assign _zz_709_ = ((decode_INSTRUCTION & 32'hfc01067e) == 32'h7c01002e); + assign _zz_710_ = ((decode_INSTRUCTION & 32'hfc0404fe) == 32'h7c04002e); + assign _zz_711_ = {((decode_INSTRUCTION & 32'hfc0006fe) == 32'h7c0002a6),{((decode_INSTRUCTION & 32'hfc1004fe) == 32'h7c10002e),{((decode_INSTRUCTION & _zz_712_) == 32'h7c01002e),{(_zz_713_ == _zz_714_),{_zz_715_,{_zz_716_,_zz_717_}}}}}}; + assign _zz_712_ = 32'hfc0104fe; + assign _zz_713_ = (decode_INSTRUCTION & 32'hfc10057e); + assign _zz_714_ = 32'h7c10002e; + assign _zz_715_ = ((decode_INSTRUCTION & 32'hfc08067e) == 32'h7c08002e); + assign _zz_716_ = ((decode_INSTRUCTION & 32'hfc00077e) == 32'h7c000078); + assign _zz_717_ = {((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000630),{((decode_INSTRUCTION & 32'hfc00077e) == 32'h7c000026),{((decode_INSTRUCTION & _zz_718_) == 32'h7c000124),{(_zz_719_ == _zz_720_),{_zz_721_,{_zz_722_,_zz_723_}}}}}}; + assign _zz_718_ = 32'hfc0007ee; + assign _zz_719_ = (decode_INSTRUCTION & 32'hfc00077e); + assign _zz_720_ = 32'h7c000016; + assign _zz_721_ = ((decode_INSTRUCTION & 32'hfc0007de) == 32'h7c000100); + assign _zz_722_ = _zz_195_; + assign _zz_723_ = {((decode_INSTRUCTION & 32'hfc0006fe) == 32'h4c000242),{((decode_INSTRUCTION & 32'hfc0007be) == 32'h4c000182),{((decode_INSTRUCTION & _zz_724_) == 32'h4c000182),{(_zz_725_ == _zz_726_),{_zz_727_,{_zz_728_,_zz_729_}}}}}}; + assign _zz_724_ = 32'hfc0005fe; + assign _zz_725_ = (decode_INSTRUCTION & 32'hfc0007be); + assign _zz_726_ = 32'h4c000202; + assign _zz_727_ = ((decode_INSTRUCTION & 32'hfc0007f6) == 32'h7c000000); + assign _zz_728_ = ((decode_INSTRUCTION & 32'hfc0007be) == 32'h4c000420); + assign _zz_729_ = {((decode_INSTRUCTION & 32'hfc00077e) == 32'h4c000102),{((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000000),{((decode_INSTRUCTION & _zz_730_) == 32'h4c000042),{(_zz_731_ == _zz_732_),{_zz_733_,{_zz_734_,_zz_735_}}}}}}; + assign _zz_730_ = 32'hfc0005fe; + assign _zz_731_ = (decode_INSTRUCTION & 32'hfc0007de); + assign _zz_732_ = 32'h4c000000; + assign _zz_733_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c0007ac); + assign _zz_734_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c0001d6); + assign _zz_735_ = {((decode_INSTRUCTION & 32'hfc1f003e) == 32'h7c00001e),{((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c000480),{((decode_INSTRUCTION & _zz_736_) == 32'h4c00012c),{(_zz_737_ == _zz_738_),{_zz_739_,{_zz_740_,_zz_741_}}}}}}; + assign _zz_736_ = 32'hfc0007fe; + assign _zz_737_ = (decode_INSTRUCTION & 32'hfc0007fe); + assign _zz_738_ = 32'h4c000064; + assign _zz_739_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h4c0000a4); + assign _zz_740_ = ((decode_INSTRUCTION & 32'hfc6007fe) == 32'h4c0004ac); + assign _zz_741_ = {((decode_INSTRUCTION & 32'hfc1f04fe) == 32'h7c00002e),{((decode_INSTRUCTION & 32'hfc1f057e) == 32'h7c00002e),((decode_INSTRUCTION & 32'hfc1f067e) == 32'h7c00002e)}}; + assign _zz_742_ = (decode_INSTRUCTION & 32'hf8000000); + assign _zz_743_ = 32'h70000000; + assign _zz_744_ = ((decode_INSTRUCTION & 32'hbc000000) == 32'h34000000); + assign _zz_745_ = _zz_187_; + assign _zz_746_ = ((decode_INSTRUCTION & _zz_754_) == 32'h70000000); + assign _zz_747_ = ((decode_INSTRUCTION & 32'h80000100) == 32'h00000100); + assign _zz_748_ = ((decode_INSTRUCTION & 32'h7800032a) == 32'h78000002); + assign _zz_749_ = {_zz_167_,{_zz_161_,{_zz_755_,_zz_756_}}}; + assign _zz_750_ = (4'b0000); + assign _zz_751_ = ({_zz_757_,{_zz_758_,_zz_759_}} != 8'h0); + assign _zz_752_ = ({_zz_760_,_zz_761_} != 20'h0); + assign _zz_753_ = {(_zz_762_ != _zz_763_),{_zz_764_,{_zz_765_,_zz_766_}}}; + assign _zz_754_ = 32'h70000538; + assign _zz_755_ = (_zz_767_ == _zz_768_); + assign _zz_756_ = _zz_166_; + assign _zz_757_ = ((decode_INSTRUCTION & _zz_769_) == 32'ha8100000); + assign _zz_758_ = (_zz_770_ == _zz_771_); + assign _zz_759_ = {_zz_772_,{_zz_773_,_zz_774_}}; + assign _zz_760_ = (_zz_775_ == _zz_776_); + assign _zz_761_ = {_zz_221_,{_zz_777_,_zz_778_}}; + assign _zz_762_ = (_zz_779_ == _zz_780_); + assign _zz_763_ = (1'b0); + assign _zz_764_ = (_zz_781_ != (1'b0)); + assign _zz_765_ = (_zz_782_ != _zz_783_); + assign _zz_766_ = {_zz_784_,{_zz_785_,_zz_786_}}; + assign _zz_767_ = (decode_INSTRUCTION & 32'h78000318); + assign _zz_768_ = 32'h78000200; + assign _zz_769_ = 32'ha8100000; + assign _zz_770_ = (decode_INSTRUCTION & 32'hfc000000); + assign _zz_771_ = 32'hac000000; + assign _zz_772_ = ((decode_INSTRUCTION & _zz_787_) == 32'ha8040000); + assign _zz_773_ = (_zz_788_ == _zz_789_); + assign _zz_774_ = {_zz_790_,{_zz_791_,_zz_792_}}; + assign _zz_775_ = (decode_INSTRUCTION & 32'hc0100000); + assign _zz_776_ = 32'h80100000; + assign _zz_777_ = _zz_170_; + assign _zz_778_ = {_zz_218_,{_zz_793_,_zz_794_}}; + assign _zz_779_ = (decode_INSTRUCTION & 32'h20000400); + assign _zz_780_ = 32'h20000000; + assign _zz_781_ = ((decode_INSTRUCTION & _zz_795_) == 32'h20000000); + assign _zz_782_ = {_zz_796_,{_zz_797_,_zz_798_}}; + assign _zz_783_ = 20'h0; + assign _zz_784_ = (_zz_213_ != (1'b0)); + assign _zz_785_ = (_zz_799_ != _zz_800_); + assign _zz_786_ = {_zz_801_,{_zz_802_,_zz_803_}}; + assign _zz_787_ = 32'hfc040000; + assign _zz_788_ = (decode_INSTRUCTION & 32'hfc080000); + assign _zz_789_ = 32'ha8080000; + assign _zz_790_ = ((decode_INSTRUCTION & _zz_804_) == 32'ha8020000); + assign _zz_791_ = (_zz_805_ == _zz_806_); + assign _zz_792_ = {_zz_807_,_zz_808_}; + assign _zz_793_ = _zz_189_; + assign _zz_794_ = {_zz_188_,{_zz_809_,_zz_810_}}; + assign _zz_795_ = 32'h20000100; + assign _zz_796_ = ((decode_INSTRUCTION & _zz_811_) == 32'h60000030); + assign _zz_797_ = (_zz_812_ == _zz_813_); + assign _zz_798_ = {_zz_814_,{_zz_815_,_zz_816_}}; + assign _zz_799_ = {_zz_817_,{_zz_818_,_zz_819_}}; + assign _zz_800_ = (4'b0000); + assign _zz_801_ = ({_zz_820_,_zz_821_} != (4'b0000)); + assign _zz_802_ = (_zz_822_ != _zz_823_); + assign _zz_803_ = {_zz_824_,{_zz_825_,_zz_826_}}; + assign _zz_804_ = 32'hfc020000; + assign _zz_805_ = (decode_INSTRUCTION & 32'hfc010000); + assign _zz_806_ = 32'ha8010000; + assign _zz_807_ = ((decode_INSTRUCTION & _zz_827_) == 32'h780002a8); + assign _zz_808_ = ((decode_INSTRUCTION & _zz_828_) == 32'ha8000000); + assign _zz_809_ = _zz_186_; + assign _zz_810_ = {_zz_185_,{_zz_829_,_zz_830_}}; + assign _zz_811_ = 32'h60000030; + assign _zz_812_ = (decode_INSTRUCTION & 32'h60000024); + assign _zz_813_ = 32'h60000020; + assign _zz_814_ = ((decode_INSTRUCTION & _zz_831_) == 32'h90100000); + assign _zz_815_ = _zz_220_; + assign _zz_816_ = {_zz_219_,{_zz_832_,_zz_833_}}; + assign _zz_817_ = ((decode_INSTRUCTION & _zz_834_) == 32'h04000000); + assign _zz_818_ = _zz_204_; + assign _zz_819_ = {_zz_835_,_zz_836_}; + assign _zz_820_ = _zz_204_; + assign _zz_821_ = {_zz_222_,{_zz_837_,_zz_838_}}; + assign _zz_822_ = {_zz_204_,{_zz_839_,_zz_840_}}; + assign _zz_823_ = (4'b0000); + assign _zz_824_ = ({_zz_841_,_zz_842_} != (2'b00)); + assign _zz_825_ = (_zz_843_ != _zz_844_); + assign _zz_826_ = {_zz_845_,{_zz_846_,_zz_847_}}; + assign _zz_827_ = 32'h780003a8; + assign _zz_828_ = 32'hfc0f0000; + assign _zz_829_ = _zz_184_; + assign _zz_830_ = {_zz_183_,{_zz_848_,_zz_849_}}; + assign _zz_831_ = 32'hd0100000; + assign _zz_832_ = _zz_215_; + assign _zz_833_ = {_zz_214_,{_zz_850_,_zz_851_}}; + assign _zz_834_ = 32'hbc000002; + assign _zz_835_ = ((decode_INSTRUCTION & _zz_852_) == 32'h440000a0); + assign _zz_836_ = ((decode_INSTRUCTION & _zz_853_) == 32'h44000060); + assign _zz_837_ = _zz_171_; + assign _zz_838_ = _zz_199_; + assign _zz_839_ = _zz_222_; + assign _zz_840_ = {_zz_200_,_zz_193_}; + assign _zz_841_ = (_zz_854_ == _zz_855_); + assign _zz_842_ = (_zz_856_ == _zz_857_); + assign _zz_843_ = {_zz_858_,{_zz_859_,_zz_860_}}; + assign _zz_844_ = 9'h0; + assign _zz_845_ = ({_zz_861_,_zz_862_} != (3'b000)); + assign _zz_846_ = (_zz_863_ != _zz_864_); + assign _zz_847_ = {_zz_865_,{_zz_866_,_zz_867_}}; + assign _zz_848_ = _zz_182_; + assign _zz_849_ = {_zz_181_,{_zz_868_,_zz_869_}}; + assign _zz_850_ = _zz_198_; + assign _zz_851_ = {_zz_870_,{_zz_871_,_zz_872_}}; + assign _zz_852_ = 32'h740004a2; + assign _zz_853_ = 32'h74000462; + assign _zz_854_ = (decode_INSTRUCTION & 32'hfc000000); + assign _zz_855_ = 32'h28000000; + assign _zz_856_ = (decode_INSTRUCTION & 32'h78000070); + assign _zz_857_ = 32'h78000040; + assign _zz_858_ = ((decode_INSTRUCTION & _zz_873_) == 32'h58000010); + assign _zz_859_ = (_zz_874_ == _zz_875_); + assign _zz_860_ = {_zz_876_,{_zz_877_,_zz_878_}}; + assign _zz_861_ = (_zz_879_ == _zz_880_); + assign _zz_862_ = {_zz_881_,_zz_882_}; + assign _zz_863_ = {_zz_883_,{_zz_884_,_zz_885_}}; + assign _zz_864_ = 25'h0; + assign _zz_865_ = ({_zz_886_,_zz_887_} != (2'b00)); + assign _zz_866_ = (_zz_888_ != _zz_889_); + assign _zz_867_ = {_zz_890_,{_zz_891_,_zz_892_}}; + assign _zz_868_ = _zz_180_; + assign _zz_869_ = {_zz_893_,_zz_894_}; + assign _zz_870_ = (_zz_895_ == _zz_896_); + assign _zz_871_ = _zz_897_; + assign _zz_872_ = {_zz_898_,_zz_899_}; + assign _zz_873_ = 32'hd8000030; + assign _zz_874_ = (decode_INSTRUCTION & _zz_900_); + assign _zz_875_ = 32'h5c000000; + assign _zz_876_ = (_zz_901_ == _zz_902_); + assign _zz_877_ = _zz_903_; + assign _zz_878_ = {_zz_904_,_zz_905_}; + assign _zz_879_ = (decode_INSTRUCTION & _zz_906_); + assign _zz_880_ = 32'h78000020; + assign _zz_881_ = (_zz_907_ == _zz_908_); + assign _zz_882_ = (_zz_909_ == _zz_910_); + assign _zz_883_ = (_zz_911_ == _zz_912_); + assign _zz_884_ = _zz_206_; + assign _zz_885_ = {_zz_913_,_zz_914_}; + assign _zz_886_ = _zz_915_; + assign _zz_887_ = _zz_916_; + assign _zz_888_ = {_zz_917_,_zz_918_}; + assign _zz_889_ = (2'b00); + assign _zz_890_ = (_zz_919_ != _zz_920_); + assign _zz_891_ = _zz_921_; + assign _zz_892_ = {_zz_922_,_zz_923_}; + assign _zz_893_ = _zz_179_; + assign _zz_894_ = {_zz_924_,_zz_925_}; + assign _zz_895_ = (decode_INSTRUCTION & _zz_926_); + assign _zz_896_ = 32'h60000128; + assign _zz_897_ = (_zz_927_ == _zz_928_); + assign _zz_898_ = _zz_929_; + assign _zz_899_ = {_zz_930_,_zz_931_}; + assign _zz_900_ = 32'hfc000000; + assign _zz_901_ = (decode_INSTRUCTION & _zz_932_); + assign _zz_902_ = 32'h50000000; + assign _zz_903_ = (_zz_933_ == _zz_934_); + assign _zz_904_ = _zz_935_; + assign _zz_905_ = {_zz_936_,_zz_937_}; + assign _zz_906_ = 32'h78000034; + assign _zz_907_ = (decode_INSTRUCTION & _zz_938_); + assign _zz_908_ = 32'h78000400; + assign _zz_909_ = (decode_INSTRUCTION & _zz_939_); + assign _zz_910_ = 32'h4c000000; + assign _zz_911_ = (decode_INSTRUCTION & _zz_940_); + assign _zz_912_ = 32'h60000010; + assign _zz_913_ = _zz_941_; + assign _zz_914_ = {_zz_942_,_zz_943_}; + assign _zz_915_ = (_zz_944_ == _zz_945_); + assign _zz_916_ = (_zz_946_ == _zz_947_); + assign _zz_917_ = _zz_948_; + assign _zz_918_ = _zz_208_; + assign _zz_919_ = {_zz_949_,_zz_950_}; + assign _zz_920_ = (3'b000); + assign _zz_921_ = (_zz_951_ != _zz_952_); + assign _zz_922_ = _zz_953_; + assign _zz_923_ = {_zz_954_,_zz_955_}; + assign _zz_924_ = _zz_178_; + assign _zz_925_ = {_zz_956_,_zz_957_}; + assign _zz_926_ = 32'h60000528; + assign _zz_927_ = (decode_INSTRUCTION & _zz_958_); + assign _zz_928_ = 32'h60000300; + assign _zz_929_ = (_zz_959_ == _zz_960_); + assign _zz_930_ = _zz_961_; + assign _zz_931_ = {_zz_962_,_zz_963_}; + assign _zz_932_ = 32'hfc000000; + assign _zz_933_ = (decode_INSTRUCTION & _zz_964_); + assign _zz_934_ = 32'h58000500; + assign _zz_935_ = (_zz_965_ == _zz_966_); + assign _zz_936_ = _zz_967_; + assign _zz_937_ = {_zz_968_,_zz_969_}; + assign _zz_938_ = 32'h78000418; + assign _zz_939_ = 32'h7c000364; + assign _zz_940_ = 32'h60000010; + assign _zz_941_ = (_zz_970_ == _zz_971_); + assign _zz_942_ = _zz_972_; + assign _zz_943_ = {_zz_973_,_zz_974_}; + assign _zz_944_ = (decode_INSTRUCTION & _zz_975_); + assign _zz_945_ = 32'h20000000; + assign _zz_946_ = (decode_INSTRUCTION & _zz_976_); + assign _zz_947_ = 32'h08000000; + assign _zz_948_ = (_zz_977_ == _zz_978_); + assign _zz_949_ = _zz_215_; + assign _zz_950_ = {_zz_979_,_zz_980_}; + assign _zz_951_ = _zz_981_; + assign _zz_952_ = (1'b0); + assign _zz_953_ = (_zz_982_ != _zz_983_); + assign _zz_954_ = _zz_984_; + assign _zz_955_ = {_zz_985_,_zz_986_}; + assign _zz_956_ = _zz_177_; + assign _zz_957_ = {_zz_987_,{_zz_988_,_zz_989_}}; + assign _zz_958_ = 32'h60000318; + assign _zz_959_ = (decode_INSTRUCTION & 32'hf4020000); + assign _zz_960_ = 32'h90020000; + assign _zz_961_ = ((decode_INSTRUCTION & _zz_990_) == 32'h90040000); + assign _zz_962_ = (_zz_991_ == _zz_992_); + assign _zz_963_ = {_zz_993_,{_zz_994_,_zz_995_}}; + assign _zz_964_ = 32'hd8000508; + assign _zz_965_ = (decode_INSTRUCTION & 32'hd8000604); + assign _zz_966_ = 32'h58000200; + assign _zz_967_ = ((decode_INSTRUCTION & _zz_996_) == 32'h58000000); + assign _zz_968_ = (_zz_997_ == _zz_998_); + assign _zz_969_ = {_zz_999_,_zz_1000_}; + assign _zz_970_ = (decode_INSTRUCTION & 32'h60000060); + assign _zz_971_ = 32'h60000060; + assign _zz_972_ = ((decode_INSTRUCTION & _zz_1001_) == 32'h60000020); + assign _zz_973_ = _zz_221_; + assign _zz_974_ = {_zz_1002_,{_zz_1003_,_zz_1004_}}; + assign _zz_975_ = 32'h20000040; + assign _zz_976_ = 32'h28000000; + assign _zz_977_ = (decode_INSTRUCTION & 32'h7800028a); + assign _zz_978_ = 32'h78000202; + assign _zz_979_ = _zz_214_; + assign _zz_980_ = (_zz_1005_ == _zz_1006_); + assign _zz_981_ = ((decode_INSTRUCTION & _zz_1007_) == 32'h78000300); + assign _zz_982_ = {_zz_213_,{_zz_1008_,_zz_1009_}}; + assign _zz_983_ = 5'h0; + assign _zz_984_ = ({_zz_1010_,_zz_1011_} != (2'b00)); + assign _zz_985_ = (_zz_1012_ != _zz_1013_); + assign _zz_986_ = {_zz_1014_,{_zz_1015_,_zz_1016_}}; + assign _zz_987_ = (_zz_1017_ == _zz_1018_); + assign _zz_988_ = _zz_1019_; + assign _zz_989_ = {_zz_1020_,_zz_1021_}; + assign _zz_990_ = 32'hdc040000; + assign _zz_991_ = (decode_INSTRUCTION & _zz_1022_); + assign _zz_992_ = 32'h90080000; + assign _zz_993_ = (_zz_1023_ == _zz_1024_); + assign _zz_994_ = _zz_1025_; + assign _zz_995_ = {_zz_1026_,_zz_1027_}; + assign _zz_996_ = 32'hd8000504; + assign _zz_997_ = (decode_INSTRUCTION & _zz_1028_); + assign _zz_998_ = 32'h58000028; + assign _zz_999_ = (_zz_1029_ == _zz_1030_); + assign _zz_1000_ = (_zz_1031_ == _zz_1032_); + assign _zz_1001_ = 32'h60000120; + assign _zz_1002_ = (_zz_1033_ == _zz_1034_); + assign _zz_1003_ = _zz_220_; + assign _zz_1004_ = {_zz_1035_,_zz_1036_}; + assign _zz_1005_ = (decode_INSTRUCTION & _zz_1037_); + assign _zz_1006_ = 32'h78000140; + assign _zz_1007_ = 32'h780003a8; + assign _zz_1008_ = _zz_205_; + assign _zz_1009_ = {_zz_1038_,_zz_1039_}; + assign _zz_1010_ = _zz_1040_; + assign _zz_1011_ = _zz_171_; + assign _zz_1012_ = {_zz_1041_,_zz_1042_}; + assign _zz_1013_ = 9'h0; + assign _zz_1014_ = (_zz_1043_ != _zz_1044_); + assign _zz_1015_ = _zz_1045_; + assign _zz_1016_ = {_zz_1046_,_zz_1047_}; + assign _zz_1017_ = (decode_INSTRUCTION & 32'h78000438); + assign _zz_1018_ = 32'h78000028; + assign _zz_1019_ = ((decode_INSTRUCTION & _zz_1048_) == 32'h80000000); + assign _zz_1020_ = _zz_202_; + assign _zz_1021_ = (_zz_1049_ == _zz_1050_); + assign _zz_1022_ = 32'hf4080000; + assign _zz_1023_ = (decode_INSTRUCTION & 32'hdc020000); + assign _zz_1024_ = 32'h90020000; + assign _zz_1025_ = ((decode_INSTRUCTION & _zz_1051_) == 32'h90040000); + assign _zz_1026_ = (_zz_1052_ == _zz_1053_); + assign _zz_1027_ = {_zz_1054_,{_zz_1055_,_zz_1056_}}; + assign _zz_1028_ = 32'hd8000468; + assign _zz_1029_ = (decode_INSTRUCTION & 32'hd80002c8); + assign _zz_1030_ = 32'h58000200; + assign _zz_1031_ = (decode_INSTRUCTION & 32'hd8000384); + assign _zz_1032_ = 32'h58000000; + assign _zz_1033_ = (decode_INSTRUCTION & 32'hd0100000); + assign _zz_1034_ = 32'h10100000; + assign _zz_1035_ = _zz_170_; + assign _zz_1036_ = {_zz_219_,{_zz_1057_,_zz_1058_}}; + assign _zz_1037_ = 32'h78000150; + assign _zz_1038_ = _zz_204_; + assign _zz_1039_ = {_zz_171_,_zz_203_}; + assign _zz_1040_ = ((decode_INSTRUCTION & _zz_1059_) == 32'h4c000120); + assign _zz_1041_ = _zz_192_; + assign _zz_1042_ = {_zz_191_,{_zz_1060_,_zz_1061_}}; + assign _zz_1043_ = {_zz_1062_,{_zz_1063_,_zz_1064_}}; + assign _zz_1044_ = 5'h0; + assign _zz_1045_ = ({_zz_1065_,_zz_1066_} != 6'h0); + assign _zz_1046_ = (_zz_1067_ != _zz_1068_); + assign _zz_1047_ = {_zz_1069_,{_zz_1070_,_zz_1071_}}; + assign _zz_1048_ = 32'he40f0000; + assign _zz_1049_ = (decode_INSTRUCTION & 32'hcc0f0000); + assign _zz_1050_ = 32'h80000000; + assign _zz_1051_ = 32'hf4040000; + assign _zz_1052_ = (decode_INSTRUCTION & 32'hf4010000); + assign _zz_1053_ = 32'h90010000; + assign _zz_1054_ = ((decode_INSTRUCTION & _zz_1072_) == 32'h90010000); + assign _zz_1055_ = (_zz_1073_ == _zz_1074_); + assign _zz_1056_ = {_zz_1075_,_zz_1076_}; + assign _zz_1057_ = _zz_218_; + assign _zz_1058_ = {_zz_217_,{_zz_1077_,_zz_1078_}}; + assign _zz_1059_ = 32'h7c000120; + assign _zz_1060_ = _zz_169_; + assign _zz_1061_ = {_zz_1079_,{_zz_1080_,_zz_1081_}}; + assign _zz_1062_ = ((decode_INSTRUCTION & _zz_1082_) == 32'h48000004); + assign _zz_1063_ = _zz_212_; + assign _zz_1064_ = {_zz_211_,{_zz_1083_,_zz_1084_}}; + assign _zz_1065_ = (_zz_1085_ == _zz_1086_); + assign _zz_1066_ = {_zz_212_,{_zz_1087_,_zz_1088_}}; + assign _zz_1067_ = _zz_208_; + assign _zz_1068_ = (1'b0); + assign _zz_1069_ = (_zz_207_ != (1'b0)); + assign _zz_1070_ = (_zz_1089_ != _zz_1090_); + assign _zz_1071_ = {_zz_1091_,{_zz_1092_,_zz_1093_}}; + assign _zz_1072_ = 32'hdc010000; + assign _zz_1073_ = (decode_INSTRUCTION & 32'hdc080000); + assign _zz_1074_ = 32'h90080000; + assign _zz_1075_ = ((decode_INSTRUCTION & _zz_1094_) == 32'h90000000); + assign _zz_1076_ = ((decode_INSTRUCTION & _zz_1095_) == 32'h90000000); + assign _zz_1077_ = (_zz_1096_ == _zz_1097_); + assign _zz_1078_ = {_zz_1098_,{_zz_1099_,_zz_1100_}}; + assign _zz_1079_ = ((decode_INSTRUCTION & _zz_1101_) == 32'h40000020); + assign _zz_1080_ = (_zz_1102_ == _zz_1103_); + assign _zz_1081_ = {_zz_1104_,{_zz_1105_,_zz_1106_}}; + assign _zz_1082_ = 32'h78000004; + assign _zz_1083_ = _zz_210_; + assign _zz_1084_ = _zz_209_; + assign _zz_1085_ = (decode_INSTRUCTION & 32'hd8000000); + assign _zz_1086_ = 32'h0; + assign _zz_1087_ = _zz_194_; + assign _zz_1088_ = {_zz_211_,{_zz_1107_,_zz_1108_}}; + assign _zz_1089_ = {_zz_201_,{_zz_1109_,_zz_1110_}}; + assign _zz_1090_ = (3'b000); + assign _zz_1091_ = ({_zz_1111_,_zz_1112_} != (3'b000)); + assign _zz_1092_ = (_zz_1113_ != _zz_1114_); + assign _zz_1093_ = {_zz_1115_,{_zz_1116_,_zz_1117_}}; + assign _zz_1094_ = 32'hdc0f0000; + assign _zz_1095_ = 32'hf40f0000; + assign _zz_1096_ = (decode_INSTRUCTION & 32'hac000000); + assign _zz_1097_ = 32'h20000000; + assign _zz_1098_ = ((decode_INSTRUCTION & _zz_1118_) == 32'h60000100); + assign _zz_1099_ = _zz_216_; + assign _zz_1100_ = {_zz_180_,{_zz_1119_,_zz_1120_}}; + assign _zz_1101_ = 32'h40000024; + assign _zz_1102_ = (decode_INSTRUCTION & 32'h40000028); + assign _zz_1103_ = 32'h40000020; + assign _zz_1104_ = ((decode_INSTRUCTION & _zz_1121_) == 32'h40000400); + assign _zz_1105_ = (_zz_1122_ == _zz_1123_); + assign _zz_1106_ = {_zz_1124_,_zz_1125_}; + assign _zz_1107_ = _zz_210_; + assign _zz_1108_ = _zz_209_; + assign _zz_1109_ = _zz_207_; + assign _zz_1110_ = (_zz_1126_ == _zz_1127_); + assign _zz_1111_ = (_zz_1128_ == _zz_1129_); + assign _zz_1112_ = {_zz_1130_,_zz_1131_}; + assign _zz_1113_ = {_zz_206_,{_zz_1132_,_zz_1133_}}; + assign _zz_1114_ = 15'h0; + assign _zz_1115_ = ({_zz_1134_,_zz_1135_} != (2'b00)); + assign _zz_1116_ = (_zz_1136_ != _zz_1137_); + assign _zz_1117_ = {_zz_1138_,{_zz_1139_,_zz_1140_}}; + assign _zz_1118_ = 32'h60000128; + assign _zz_1119_ = _zz_179_; + assign _zz_1120_ = {_zz_178_,{_zz_1141_,_zz_1142_}}; + assign _zz_1121_ = 32'h40000414; + assign _zz_1122_ = (decode_INSTRUCTION & 32'h40000038); + assign _zz_1123_ = 32'h40000008; + assign _zz_1124_ = ((decode_INSTRUCTION & _zz_1143_) == 32'h0); + assign _zz_1125_ = ((decode_INSTRUCTION & _zz_1144_) == 32'h0); + assign _zz_1126_ = (decode_INSTRUCTION & 32'h780005e8); + assign _zz_1127_ = 32'h78000080; + assign _zz_1128_ = (decode_INSTRUCTION & 32'h7c000104); + assign _zz_1129_ = 32'h4c000100; + assign _zz_1130_ = ((decode_INSTRUCTION & _zz_1145_) == 32'h4c000200); + assign _zz_1131_ = ((decode_INSTRUCTION & _zz_1146_) == 32'h4c000040); + assign _zz_1132_ = _zz_170_; + assign _zz_1133_ = {_zz_180_,{_zz_1147_,_zz_1148_}}; + assign _zz_1134_ = (_zz_1149_ == _zz_1150_); + assign _zz_1135_ = _zz_171_; + assign _zz_1136_ = {_zz_201_,_zz_196_}; + assign _zz_1137_ = (2'b00); + assign _zz_1138_ = ({_zz_1151_,_zz_1152_} != (4'b0000)); + assign _zz_1139_ = (_zz_1153_ != _zz_1154_); + assign _zz_1140_ = {_zz_1155_,{_zz_1156_,_zz_1157_}}; + assign _zz_1141_ = _zz_177_; + assign _zz_1142_ = {_zz_173_,{_zz_1158_,_zz_1159_}}; + assign _zz_1143_ = 32'hf0000000; + assign _zz_1144_ = 32'hb0000004; + assign _zz_1145_ = 32'h7c000204; + assign _zz_1146_ = 32'h7c000444; + assign _zz_1147_ = _zz_179_; + assign _zz_1148_ = {_zz_1160_,{_zz_1161_,_zz_1162_}}; + assign _zz_1149_ = (decode_INSTRUCTION & 32'h78000318); + assign _zz_1150_ = 32'h78000300; + assign _zz_1151_ = _zz_200_; + assign _zz_1152_ = {_zz_171_,{_zz_1163_,_zz_1164_}}; + assign _zz_1153_ = {_zz_163_,_zz_162_}; + assign _zz_1154_ = (2'b00); + assign _zz_1155_ = ({_zz_1165_,_zz_1166_} != 8'h0); + assign _zz_1156_ = (_zz_1167_ != _zz_1168_); + assign _zz_1157_ = {_zz_1169_,{_zz_1170_,_zz_1171_}}; + assign _zz_1158_ = _zz_172_; + assign _zz_1159_ = {_zz_175_,{_zz_1172_,_zz_1173_}}; + assign _zz_1160_ = ((decode_INSTRUCTION & _zz_1174_) == 32'h0c000000); + assign _zz_1161_ = _zz_178_; + assign _zz_1162_ = {_zz_177_,{_zz_1175_,_zz_1176_}}; + assign _zz_1163_ = _zz_199_; + assign _zz_1164_ = _zz_193_; + assign _zz_1165_ = _zz_198_; + assign _zz_1166_ = {_zz_1177_,{_zz_1178_,_zz_1179_}}; + assign _zz_1167_ = _zz_167_; + assign _zz_1168_ = (1'b0); + assign _zz_1169_ = ({_zz_1180_,_zz_1181_} != 6'h0); + assign _zz_1170_ = (_zz_1182_ != _zz_1183_); + assign _zz_1171_ = {_zz_1184_,{_zz_1185_,_zz_1186_}}; + assign _zz_1172_ = (_zz_1187_ == _zz_1188_); + assign _zz_1173_ = {_zz_174_,{_zz_1189_,_zz_1190_}}; + assign _zz_1174_ = 32'h7c000000; + assign _zz_1175_ = (_zz_1191_ == _zz_1192_); + assign _zz_1176_ = {_zz_1193_,{_zz_1194_,_zz_1195_}}; + assign _zz_1177_ = ((decode_INSTRUCTION & _zz_1196_) == 32'h50000000); + assign _zz_1178_ = (_zz_1197_ == _zz_1198_); + assign _zz_1179_ = {_zz_1199_,{_zz_1200_,_zz_1201_}}; + assign _zz_1180_ = _zz_160_; + assign _zz_1181_ = {_zz_1202_,{_zz_1203_,_zz_1204_}}; + assign _zz_1182_ = {_zz_1205_,{_zz_1206_,_zz_1207_}}; + assign _zz_1183_ = (4'b0000); + assign _zz_1184_ = ({_zz_1208_,_zz_1209_} != 6'h0); + assign _zz_1185_ = (_zz_1210_ != _zz_1211_); + assign _zz_1186_ = {_zz_1212_,{_zz_1213_,_zz_1214_}}; + assign _zz_1187_ = (decode_INSTRUCTION & _zz_1215_); + assign _zz_1188_ = 32'h4c000004; + assign _zz_1189_ = _zz_202_; + assign _zz_1190_ = _zz_1216_; + assign _zz_1191_ = (decode_INSTRUCTION & _zz_1217_); + assign _zz_1192_ = 32'h040000a0; + assign _zz_1193_ = (_zz_1218_ == _zz_1219_); + assign _zz_1194_ = _zz_205_; + assign _zz_1195_ = {_zz_1220_,_zz_1221_}; + assign _zz_1196_ = 32'hf8000000; + assign _zz_1197_ = (decode_INSTRUCTION & _zz_1222_); + assign _zz_1198_ = 32'h58000200; + assign _zz_1199_ = (_zz_1223_ == _zz_1224_); + assign _zz_1200_ = _zz_1225_; + assign _zz_1201_ = {_zz_1226_,_zz_1227_}; + assign _zz_1202_ = (_zz_1228_ == _zz_1229_); + assign _zz_1203_ = _zz_159_; + assign _zz_1204_ = {_zz_1230_,_zz_1231_}; + assign _zz_1205_ = (_zz_1232_ == _zz_1233_); + assign _zz_1206_ = _zz_1234_; + assign _zz_1207_ = {_zz_1235_,_zz_1236_}; + assign _zz_1208_ = _zz_192_; + assign _zz_1209_ = {_zz_1237_,_zz_1238_}; + assign _zz_1210_ = {_zz_1239_,_zz_1240_}; + assign _zz_1211_ = 11'h0; + assign _zz_1212_ = (_zz_1241_ != _zz_1242_); + assign _zz_1213_ = _zz_1243_; + assign _zz_1214_ = {_zz_1244_,_zz_1245_}; + assign _zz_1215_ = 32'h4c00002c; + assign _zz_1216_ = ((decode_INSTRUCTION & _zz_1246_) == 32'h38000000); + assign _zz_1217_ = 32'h340004a0; + assign _zz_1218_ = (decode_INSTRUCTION & 32'h34000460); + assign _zz_1219_ = 32'h04000060; + assign _zz_1220_ = _zz_204_; + assign _zz_1221_ = {_zz_1247_,{_zz_1248_,_zz_1249_}}; + assign _zz_1222_ = 32'hd8000282; + assign _zz_1223_ = (decode_INSTRUCTION & 32'hd8000124); + assign _zz_1224_ = 32'h58000020; + assign _zz_1225_ = ((decode_INSTRUCTION & _zz_1250_) == 32'h58000004); + assign _zz_1226_ = (_zz_1251_ == _zz_1252_); + assign _zz_1227_ = {_zz_1253_,_zz_1254_}; + assign _zz_1228_ = (decode_INSTRUCTION & 32'h0c000000); + assign _zz_1229_ = 32'h04000000; + assign _zz_1230_ = (_zz_1255_ == _zz_1256_); + assign _zz_1231_ = {_zz_1257_,_zz_168_}; + assign _zz_1232_ = (decode_INSTRUCTION & 32'h44000000); + assign _zz_1233_ = 32'h40000000; + assign _zz_1234_ = ((decode_INSTRUCTION & _zz_1258_) == 32'h0); + assign _zz_1235_ = _zz_197_; + assign _zz_1236_ = (_zz_1259_ == _zz_1260_); + assign _zz_1237_ = _zz_169_; + assign _zz_1238_ = {_zz_197_,{_zz_1261_,_zz_1262_}}; + assign _zz_1239_ = _zz_165_; + assign _zz_1240_ = {_zz_191_,{_zz_1263_,_zz_1264_}}; + assign _zz_1241_ = _zz_196_; + assign _zz_1242_ = (1'b0); + assign _zz_1243_ = (_zz_1265_ != (1'b0)); + assign _zz_1244_ = (_zz_1266_ != _zz_1267_); + assign _zz_1245_ = {_zz_1268_,{_zz_1269_,_zz_1270_}}; + assign _zz_1246_ = 32'hf80f0000; + assign _zz_1247_ = ((decode_INSTRUCTION & _zz_1271_) == 32'h78000028); + assign _zz_1248_ = _zz_171_; + assign _zz_1249_ = {_zz_203_,_zz_202_}; + assign _zz_1250_ = 32'hd8000026; + assign _zz_1251_ = (decode_INSTRUCTION & 32'hd8000244); + assign _zz_1252_ = 32'h58000200; + assign _zz_1253_ = ((decode_INSTRUCTION & _zz_1272_) == 32'h580000c0); + assign _zz_1254_ = ((decode_INSTRUCTION & _zz_1273_) == 32'h58000010); + assign _zz_1255_ = (decode_INSTRUCTION & 32'h14000000); + assign _zz_1256_ = 32'h04000000; + assign _zz_1257_ = ((decode_INSTRUCTION & _zz_1274_) == 32'h0); + assign _zz_1258_ = 32'hb0000000; + assign _zz_1259_ = (decode_INSTRUCTION & 32'h78000066); + assign _zz_1260_ = 32'h78000044; + assign _zz_1261_ = (_zz_1275_ == _zz_1276_); + assign _zz_1262_ = {_zz_1277_,_zz_1278_}; + assign _zz_1263_ = (_zz_1279_ == _zz_1280_); + assign _zz_1264_ = {_zz_1281_,{_zz_1282_,_zz_1283_}}; + assign _zz_1265_ = ((decode_INSTRUCTION & _zz_1284_) == 32'h78100020); + assign _zz_1266_ = _zz_195_; + assign _zz_1267_ = (1'b0); + assign _zz_1268_ = ({_zz_1285_,_zz_1286_} != (2'b00)); + assign _zz_1269_ = (_zz_1287_ != _zz_1288_); + assign _zz_1270_ = {_zz_1289_,{_zz_1290_,_zz_1291_}}; + assign _zz_1271_ = 32'h78000138; + assign _zz_1272_ = 32'hd80002c4; + assign _zz_1273_ = 32'hd80000b2; + assign _zz_1274_ = 32'h48000000; + assign _zz_1275_ = (decode_INSTRUCTION & 32'h7c000000); + assign _zz_1276_ = 32'h3c000000; + assign _zz_1277_ = ((decode_INSTRUCTION & _zz_1292_) == 32'h60000080); + assign _zz_1278_ = ((decode_INSTRUCTION & _zz_1293_) == 32'h60000080); + assign _zz_1279_ = (decode_INSTRUCTION & 32'h58000000); + assign _zz_1280_ = 32'h48000000; + assign _zz_1281_ = ((decode_INSTRUCTION & _zz_1294_) == 32'h20000000); + assign _zz_1282_ = _zz_164_; + assign _zz_1283_ = {_zz_1295_,{_zz_1296_,_zz_1297_}}; + assign _zz_1284_ = 32'h781001b8; + assign _zz_1285_ = _zz_187_; + assign _zz_1286_ = (_zz_1298_ == _zz_1299_); + assign _zz_1287_ = {_zz_1300_,_zz_1301_}; + assign _zz_1288_ = (2'b00); + assign _zz_1289_ = ({_zz_1302_,_zz_1303_} != (2'b00)); + assign _zz_1290_ = (_zz_1304_ != _zz_1305_); + assign _zz_1291_ = {_zz_1306_,{_zz_1307_,_zz_1308_}}; + assign _zz_1292_ = 32'h600001a4; + assign _zz_1293_ = 32'h600002c2; + assign _zz_1294_ = 32'ha8000000; + assign _zz_1295_ = ((decode_INSTRUCTION & _zz_1309_) == 32'h20000108); + assign _zz_1296_ = (_zz_1310_ == _zz_1311_); + assign _zz_1297_ = {_zz_1312_,{_zz_1313_,_zz_1314_}}; + assign _zz_1298_ = (decode_INSTRUCTION & 32'h78000538); + assign _zz_1299_ = 32'h78000000; + assign _zz_1300_ = ((decode_INSTRUCTION & _zz_1315_) == 32'h00000040); + assign _zz_1301_ = ((decode_INSTRUCTION & _zz_1316_) == 32'h0); + assign _zz_1302_ = _zz_158_; + assign _zz_1303_ = (_zz_1317_ == _zz_1318_); + assign _zz_1304_ = {_zz_1319_,{_zz_1320_,_zz_1321_}}; + assign _zz_1305_ = (3'b000); + assign _zz_1306_ = ({_zz_1322_,_zz_1323_} != (2'b00)); + assign _zz_1307_ = (_zz_1324_ != _zz_1325_); + assign _zz_1308_ = {_zz_1326_,{_zz_1327_,_zz_1328_}}; + assign _zz_1309_ = 32'ha0000108; + assign _zz_1310_ = (decode_INSTRUCTION & 32'ha0000018); + assign _zz_1311_ = 32'h20000018; + assign _zz_1312_ = ((decode_INSTRUCTION & _zz_1329_) == 32'h20000010); + assign _zz_1313_ = (_zz_1330_ == _zz_1331_); + assign _zz_1314_ = {_zz_1332_,_zz_1333_}; + assign _zz_1315_ = 32'h000000c0; + assign _zz_1316_ = 32'h00000280; + assign _zz_1317_ = (decode_INSTRUCTION & 32'h00000180); + assign _zz_1318_ = 32'h00000100; + assign _zz_1319_ = ((decode_INSTRUCTION & _zz_1334_) == 32'h00000300); + assign _zz_1320_ = (_zz_1335_ == _zz_1336_); + assign _zz_1321_ = (_zz_1337_ == _zz_1338_); + assign _zz_1322_ = (_zz_1339_ == _zz_1340_); + assign _zz_1323_ = (_zz_1341_ == _zz_1342_); + assign _zz_1324_ = {_zz_1343_,{_zz_1344_,_zz_1345_}}; + assign _zz_1325_ = (3'b000); + assign _zz_1326_ = ({_zz_1346_,_zz_1347_} != (3'b000)); + assign _zz_1327_ = (_zz_1348_ != _zz_1349_); + assign _zz_1328_ = {_zz_1350_,{_zz_1351_,_zz_1352_}}; + assign _zz_1329_ = 32'ha0000012; + assign _zz_1330_ = (decode_INSTRUCTION & 32'ha000000c); + assign _zz_1331_ = 32'h20000000; + assign _zz_1332_ = ((decode_INSTRUCTION & _zz_1353_) == 32'h20000200); + assign _zz_1333_ = ((decode_INSTRUCTION & _zz_1354_) == 32'h20000000); + assign _zz_1334_ = 32'h00000300; + assign _zz_1335_ = (decode_INSTRUCTION & 32'h00000140); + assign _zz_1336_ = 32'h00000140; + assign _zz_1337_ = (decode_INSTRUCTION & 32'h00000240); + assign _zz_1338_ = 32'h00000240; + assign _zz_1339_ = (decode_INSTRUCTION & 32'h18000008); + assign _zz_1340_ = 32'h18000000; + assign _zz_1341_ = (decode_INSTRUCTION & 32'h18000280); + assign _zz_1342_ = 32'h18000080; + assign _zz_1343_ = ((decode_INSTRUCTION & _zz_1355_) == 32'h08000000); + assign _zz_1344_ = (_zz_1356_ == _zz_1357_); + assign _zz_1345_ = (_zz_1358_ == _zz_1359_); + assign _zz_1346_ = (_zz_1360_ == _zz_1361_); + assign _zz_1347_ = {_zz_1362_,_zz_1363_}; + assign _zz_1348_ = {_zz_1364_,{_zz_1365_,_zz_1366_}}; + assign _zz_1349_ = (3'b000); + assign _zz_1350_ = ({_zz_1367_,_zz_1368_} != (3'b000)); + assign _zz_1351_ = 1'b0; + assign _zz_1352_ = {_zz_1369_,{_zz_1370_,_zz_1371_}}; + assign _zz_1353_ = 32'ha0000218; + assign _zz_1354_ = 32'ha0000198; + assign _zz_1355_ = 32'h18000000; + assign _zz_1356_ = (decode_INSTRUCTION & 32'h080000c0); + assign _zz_1357_ = 32'h08000080; + assign _zz_1358_ = (decode_INSTRUCTION & 32'h08000300); + assign _zz_1359_ = 32'h08000200; + assign _zz_1360_ = (decode_INSTRUCTION & 32'h18000000); + assign _zz_1361_ = 32'h0; + assign _zz_1362_ = ((decode_INSTRUCTION & _zz_1372_) == 32'h18000200); + assign _zz_1363_ = ((decode_INSTRUCTION & _zz_1373_) == 32'h18000100); + assign _zz_1364_ = ((decode_INSTRUCTION & _zz_1374_) == 32'h18000040); + assign _zz_1365_ = (_zz_1375_ == _zz_1376_); + assign _zz_1366_ = (_zz_1377_ == _zz_1378_); + assign _zz_1367_ = _zz_194_; + assign _zz_1368_ = {_zz_190_,_zz_1379_}; + assign _zz_1369_ = (_zz_1380_ != (1'b0)); + assign _zz_1370_ = (_zz_1381_ != _zz_1382_); + assign _zz_1371_ = {_zz_1383_,{_zz_1384_,_zz_1385_}}; + assign _zz_1372_ = 32'h18000240; + assign _zz_1373_ = 32'h18000500; + assign _zz_1374_ = 32'h18000048; + assign _zz_1375_ = (decode_INSTRUCTION & 32'h18000540); + assign _zz_1376_ = 32'h18000100; + assign _zz_1377_ = (decode_INSTRUCTION & 32'h180002c0); + assign _zz_1378_ = 32'h18000040; + assign _zz_1379_ = ((decode_INSTRUCTION & 32'h78000132) == 32'h78000010); + assign _zz_1380_ = ((decode_INSTRUCTION & 32'h20000200) == 32'h20000200); + assign _zz_1381_ = ((decode_INSTRUCTION & _zz_1386_) == 32'h20000000); + assign _zz_1382_ = (1'b0); + assign _zz_1383_ = ({_zz_1387_,_zz_1388_} != (2'b00)); + assign _zz_1384_ = (_zz_1389_ != (1'b0)); + assign _zz_1385_ = {(_zz_1390_ != _zz_1391_),{_zz_1392_,{_zz_1393_,_zz_1394_}}}; + assign _zz_1386_ = 32'h20000200; + assign _zz_1387_ = ((decode_INSTRUCTION & 32'h04000000) == 32'h0); + assign _zz_1388_ = ((decode_INSTRUCTION & 32'h20000600) == 32'h20000400); + assign _zz_1389_ = ((decode_INSTRUCTION & 32'h7800038a) == 32'h78000202); + assign _zz_1390_ = {_zz_171_,_zz_193_}; + assign _zz_1391_ = (2'b00); + assign _zz_1392_ = (((decode_INSTRUCTION & _zz_1395_) == 32'h4c000400) != (1'b0)); + assign _zz_1393_ = ({_zz_1396_,_zz_1397_} != (2'b00)); + assign _zz_1394_ = {({_zz_1398_,_zz_1399_} != (3'b000)),{(_zz_1400_ != _zz_1401_),{_zz_1402_,{_zz_1403_,_zz_1404_}}}}; + assign _zz_1395_ = 32'h7c000404; + assign _zz_1396_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h40000000); + assign _zz_1397_ = ((decode_INSTRUCTION & 32'h7c0005e0) == 32'h4c000020); + assign _zz_1398_ = ((decode_INSTRUCTION & _zz_1405_) == 32'h48000000); + assign _zz_1399_ = {(_zz_1406_ == _zz_1407_),(_zz_1408_ == _zz_1409_)}; + assign _zz_1400_ = {_zz_165_,{_zz_192_,{_zz_1410_,_zz_1411_}}}; + assign _zz_1401_ = 6'h0; + assign _zz_1402_ = ({_zz_176_,{_zz_1412_,_zz_1413_}} != (4'b0000)); + assign _zz_1403_ = ({_zz_1414_,_zz_1415_} != 31'h0); + assign _zz_1404_ = {(_zz_1416_ != _zz_1417_),{_zz_1418_,{_zz_1419_,_zz_1420_}}}; + assign _zz_1405_ = 32'hfc000000; + assign _zz_1406_ = (decode_INSTRUCTION & 32'h78000046); + assign _zz_1407_ = 32'h48000040; + assign _zz_1408_ = (decode_INSTRUCTION & 32'h780005e0); + assign _zz_1409_ = 32'h48000020; + assign _zz_1410_ = (_zz_1421_ == _zz_1422_); + assign _zz_1411_ = {_zz_191_,{_zz_1423_,_zz_1424_}}; + assign _zz_1412_ = (_zz_1425_ == _zz_1426_); + assign _zz_1413_ = {_zz_190_,_zz_1427_}; + assign _zz_1414_ = (_zz_1428_ == _zz_1429_); + assign _zz_1415_ = {_zz_1430_,{_zz_1431_,_zz_1432_}}; + assign _zz_1416_ = {_zz_170_,_zz_1433_}; + assign _zz_1417_ = (2'b00); + assign _zz_1418_ = ({_zz_1434_,_zz_1435_} != 5'h0); + assign _zz_1419_ = (_zz_1436_ != _zz_1437_); + assign _zz_1420_ = {_zz_1438_,{_zz_1439_,_zz_1440_}}; + assign _zz_1421_ = (decode_INSTRUCTION & 32'h40000120); + assign _zz_1422_ = 32'h40000120; + assign _zz_1423_ = _zz_169_; + assign _zz_1424_ = (_zz_1441_ == _zz_1442_); + assign _zz_1425_ = (decode_INSTRUCTION & 32'h7800020c); + assign _zz_1426_ = 32'h78000200; + assign _zz_1427_ = ((decode_INSTRUCTION & _zz_1443_) == 32'h78000010); + assign _zz_1428_ = (decode_INSTRUCTION & 32'hc0100000); + assign _zz_1429_ = 32'h00100000; + assign _zz_1430_ = ((decode_INSTRUCTION & _zz_1444_) == 32'h00100000); + assign _zz_1431_ = _zz_189_; + assign _zz_1432_ = {_zz_188_,{_zz_1445_,_zz_1446_}}; + assign _zz_1433_ = ((decode_INSTRUCTION & _zz_1447_) == 32'h78000060); + assign _zz_1434_ = (_zz_1448_ == _zz_1449_); + assign _zz_1435_ = {_zz_1450_,{_zz_1451_,_zz_1452_}}; + assign _zz_1436_ = {_zz_1453_,{_zz_1454_,_zz_1455_}}; + assign _zz_1437_ = (4'b0000); + assign _zz_1438_ = ({_zz_1456_,_zz_1457_} != (2'b00)); + assign _zz_1439_ = (_zz_1458_ != _zz_1459_); + assign _zz_1440_ = {_zz_1460_,{_zz_1461_,_zz_1462_}}; + assign _zz_1441_ = (decode_INSTRUCTION & 32'h40000022); + assign _zz_1442_ = 32'h40000020; + assign _zz_1443_ = 32'h78000272; + assign _zz_1444_ = 32'h44100000; + assign _zz_1445_ = (_zz_1463_ == _zz_1464_); + assign _zz_1446_ = {_zz_187_,{_zz_1465_,_zz_1466_}}; + assign _zz_1447_ = 32'h78000170; + assign _zz_1448_ = (decode_INSTRUCTION & 32'hb0000000); + assign _zz_1449_ = 32'h10000000; + assign _zz_1450_ = ((decode_INSTRUCTION & _zz_1467_) == 32'h58000200); + assign _zz_1451_ = (_zz_1468_ == _zz_1469_); + assign _zz_1452_ = {_zz_1470_,_zz_1471_}; + assign _zz_1453_ = ((decode_INSTRUCTION & _zz_1472_) == 32'h60000000); + assign _zz_1454_ = _zz_169_; + assign _zz_1455_ = {_zz_1473_,_zz_1474_}; + assign _zz_1456_ = _zz_168_; + assign _zz_1457_ = (_zz_1475_ == _zz_1476_); + assign _zz_1458_ = {_zz_1477_,{_zz_1478_,_zz_1479_}}; + assign _zz_1459_ = (4'b0000); + assign _zz_1460_ = ({_zz_1480_,_zz_1481_} != (3'b000)); + assign _zz_1461_ = (_zz_1482_ != _zz_1483_); + assign _zz_1462_ = {_zz_1484_,{_zz_1485_,_zz_1486_}}; + assign _zz_1463_ = (decode_INSTRUCTION & 32'hec000000); + assign _zz_1464_ = 32'h0c000000; + assign _zz_1465_ = _zz_186_; + assign _zz_1466_ = {_zz_185_,{_zz_1487_,_zz_1488_}}; + assign _zz_1467_ = 32'h5800020c; + assign _zz_1468_ = (decode_INSTRUCTION & 32'h58000228); + assign _zz_1469_ = 32'h58000020; + assign _zz_1470_ = ((decode_INSTRUCTION & _zz_1489_) == 32'h580002c0); + assign _zz_1471_ = ((decode_INSTRUCTION & _zz_1490_) == 32'h58000020); + assign _zz_1472_ = 32'h68000000; + assign _zz_1473_ = ((decode_INSTRUCTION & _zz_1491_) == 32'h60000008); + assign _zz_1474_ = ((decode_INSTRUCTION & _zz_1492_) == 32'h60000024); + assign _zz_1475_ = (decode_INSTRUCTION & 32'h80000280); + assign _zz_1476_ = 32'h0; + assign _zz_1477_ = ((decode_INSTRUCTION & _zz_1493_) == 32'h0); + assign _zz_1478_ = (_zz_1494_ == _zz_1495_); + assign _zz_1479_ = {_zz_1496_,_zz_1497_}; + assign _zz_1480_ = _zz_167_; + assign _zz_1481_ = {_zz_161_,_zz_166_}; + assign _zz_1482_ = {_zz_165_,{_zz_1498_,_zz_1499_}}; + assign _zz_1483_ = 10'h0; + assign _zz_1484_ = (_zz_1500_ != (1'b0)); + assign _zz_1485_ = (_zz_1501_ != _zz_1502_); + assign _zz_1486_ = {_zz_1503_,{_zz_1504_,_zz_1505_}}; + assign _zz_1487_ = _zz_184_; + assign _zz_1488_ = {_zz_183_,{_zz_1506_,_zz_1507_}}; + assign _zz_1489_ = 32'h580002c4; + assign _zz_1490_ = 32'h5800042a; + assign _zz_1491_ = 32'h6000000c; + assign _zz_1492_ = 32'h6000002c; + assign _zz_1493_ = 32'h08000000; + assign _zz_1494_ = (decode_INSTRUCTION & 32'h80000200); + assign _zz_1495_ = 32'h00000200; + assign _zz_1496_ = ((decode_INSTRUCTION & _zz_1508_) == 32'h20000000); + assign _zz_1497_ = ((decode_INSTRUCTION & _zz_1509_) == 32'h0); + assign _zz_1498_ = (_zz_1510_ == _zz_1511_); + assign _zz_1499_ = {_zz_1512_,{_zz_1513_,_zz_1514_}}; + assign _zz_1500_ = ((decode_INSTRUCTION & _zz_1515_) == 32'h78000200); + assign _zz_1501_ = {_zz_163_,_zz_162_}; + assign _zz_1502_ = (2'b00); + assign _zz_1503_ = (_zz_161_ != (1'b0)); + assign _zz_1504_ = (_zz_1516_ != _zz_1517_); + assign _zz_1505_ = {_zz_1518_,{_zz_1519_,_zz_1520_}}; + assign _zz_1506_ = _zz_182_; + assign _zz_1507_ = {_zz_181_,{_zz_1521_,_zz_1522_}}; + assign _zz_1508_ = 32'h60000000; + assign _zz_1509_ = 32'h80000080; + assign _zz_1510_ = (decode_INSTRUCTION & 32'h40000002); + assign _zz_1511_ = 32'h40000000; + assign _zz_1512_ = ((decode_INSTRUCTION & _zz_1523_) == 32'h40000000); + assign _zz_1513_ = (_zz_1524_ == _zz_1525_); + assign _zz_1514_ = {_zz_1526_,{_zz_1527_,_zz_1528_}}; + assign _zz_1515_ = 32'h78000212; + assign _zz_1516_ = {_zz_1529_,_zz_1530_}; + assign _zz_1517_ = (2'b00); + assign _zz_1518_ = ({_zz_1531_,_zz_1532_} != 6'h0); + assign _zz_1519_ = (_zz_1533_ != _zz_1534_); + assign _zz_1520_ = {_zz_1535_,_zz_1536_}; + assign _zz_1521_ = _zz_180_; + assign _zz_1522_ = {_zz_179_,{_zz_1537_,_zz_1538_}}; + assign _zz_1523_ = 32'h60000000; + assign _zz_1524_ = (decode_INSTRUCTION & 32'h18000000); + assign _zz_1525_ = 32'h10000000; + assign _zz_1526_ = ((decode_INSTRUCTION & _zz_1539_) == 32'h0); + assign _zz_1527_ = (_zz_1540_ == _zz_1541_); + assign _zz_1528_ = {_zz_1542_,{_zz_1543_,_zz_1544_}}; + assign _zz_1529_ = ((decode_INSTRUCTION & _zz_1545_) == 32'h0); + assign _zz_1530_ = ((decode_INSTRUCTION & _zz_1546_) == 32'h40000010); + assign _zz_1531_ = _zz_160_; + assign _zz_1532_ = {_zz_1547_,{_zz_1548_,_zz_1549_}}; + assign _zz_1533_ = (_zz_1550_ == _zz_1551_); + assign _zz_1534_ = (1'b0); + assign _zz_1535_ = (_zz_1552_ != (1'b0)); + assign _zz_1536_ = ({_zz_1553_,_zz_1554_} != (3'b000)); + assign _zz_1537_ = _zz_178_; + assign _zz_1538_ = {_zz_1555_,{_zz_1556_,_zz_1557_}}; + assign _zz_1539_ = 32'h90000000; + assign _zz_1540_ = (decode_INSTRUCTION & 32'h40000028); + assign _zz_1541_ = 32'h40000008; + assign _zz_1542_ = ((decode_INSTRUCTION & _zz_1558_) == 32'h40000100); + assign _zz_1543_ = (_zz_1559_ == _zz_1560_); + assign _zz_1544_ = {_zz_164_,_zz_1561_}; + assign _zz_1545_ = 32'h98000000; + assign _zz_1546_ = 32'h40000134; + assign _zz_1547_ = ((decode_INSTRUCTION & _zz_1562_) == 32'h40000020); + assign _zz_1548_ = (_zz_1563_ == _zz_1564_); + assign _zz_1549_ = {_zz_159_,{_zz_1565_,_zz_1566_}}; + assign _zz_1550_ = (decode_INSTRUCTION & 32'h00000100); + assign _zz_1551_ = 32'h00000100; + assign _zz_1552_ = ((decode_INSTRUCTION & _zz_1567_) == 32'h00000080); + assign _zz_1553_ = (_zz_1568_ == _zz_1569_); + assign _zz_1554_ = {_zz_158_,_zz_1570_}; + assign _zz_1555_ = ((decode_INSTRUCTION & 32'hf8000000) == 32'h30000000); + assign _zz_1556_ = _zz_177_; + assign _zz_1557_ = {_zz_176_,{((decode_INSTRUCTION & _zz_1571_) == 32'h78000010),{_zz_175_,{_zz_174_,{_zz_1572_,_zz_1573_}}}}}; + assign _zz_1558_ = 32'h40000110; + assign _zz_1559_ = (decode_INSTRUCTION & 32'h40000220); + assign _zz_1560_ = 32'h40000200; + assign _zz_1561_ = ((decode_INSTRUCTION & 32'h40000018) == 32'h40000000); + assign _zz_1562_ = 32'h40000020; + assign _zz_1563_ = (decode_INSTRUCTION & 32'h40000010); + assign _zz_1564_ = 32'h40000000; + assign _zz_1565_ = ((decode_INSTRUCTION & 32'h48000000) == 32'h08000000); + assign _zz_1566_ = ((decode_INSTRUCTION & 32'h40000104) == 32'h40000004); + assign _zz_1567_ = 32'h00000180; + assign _zz_1568_ = (decode_INSTRUCTION & 32'h00000400); + assign _zz_1569_ = 32'h00000400; + assign _zz_1570_ = ((decode_INSTRUCTION & 32'h00000300) == 32'h00000200); + assign _zz_1571_ = 32'h78000030; + assign _zz_1572_ = _zz_173_; + assign _zz_1573_ = {_zz_172_,{((decode_INSTRUCTION & 32'h78000188) == 32'h78000180),{_zz_171_,{((decode_INSTRUCTION & 32'h38100458) == 32'h38100008),{((decode_INSTRUCTION & _zz_1574_) == 32'h78000000),{(_zz_1575_ == _zz_1576_),{_zz_1577_,{_zz_1578_,_zz_1579_}}}}}}}}; + assign _zz_1574_ = 32'h78000524; + assign _zz_1575_ = (decode_INSTRUCTION & 32'h38010478); + assign _zz_1576_ = 32'h38010028; + assign _zz_1577_ = ((decode_INSTRUCTION & 32'h38020478) == 32'h38020028); + assign _zz_1578_ = ((decode_INSTRUCTION & 32'h38080478) == 32'h38080028); + assign _zz_1579_ = ((decode_INSTRUCTION & 32'h38040478) == 32'h38040028); + assign _zz_1580_ = 11'h008; + assign _zz_1581_ = 11'h009; + assign _zz_1582_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h0},MSR_EE},MSR_PR}; + assign _zz_1583_ = MSR_FP; + assign _zz_1584_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h0},MSR_EE},MSR_PR}; + assign _zz_1585_ = MSR_FP; + assign _zz_1586_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h02},MSR_EE},MSR_PR}; + assign _zz_1587_ = MSR_FP; + always @ (posedge clk) begin + if(_zz_130_) begin + IBusCachedPlugin_predictor_history[IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address] <= _zz_658_; + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_389_ <= IBusCachedPlugin_predictor_history[_zz_501_]; + end + end + + always @ (posedge clk) begin + if(_zz_659_) begin + _zz_390_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_660_) begin + _zz_391_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_661_) begin + _zz_392_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress3]; + end + end + + always @ (posedge clk) begin + if(_zz_103_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_367_ ), //i + .io_cpu_prefetch_isValid (_zz_368_ ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_369_ ), //i + .io_cpu_fetch_isStuck (_zz_370_ ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_externalFlush ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuBus_cmd_isValid (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid ), //o + .io_cpu_fetch_mmuBus_cmd_virtualAddress (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress[31:0] ), //o + .io_cpu_fetch_mmuBus_cmd_bypassTranslation (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation ), //o + .io_cpu_fetch_mmuBus_rsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuBus_rsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuBus_rsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuBus_rsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuBus_rsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuBus_rsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuBus_rsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuBus_spr_valid (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid ), //o + .io_cpu_fetch_mmuBus_spr_payload_id (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id[9:0] ), //o + .io_cpu_fetch_mmuBus_spr_payload_data (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data[31:0] ), //o + .io_cpu_fetch_mmuBus_end (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end ), //o + .io_cpu_fetch_mmuBus_busy (IBusCachedPlugin_mmuBus_busy ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_fetch_exceptionType (IBusCachedPlugin_cache_io_cpu_fetch_exceptionType[3:0] ), //o + .io_cpu_fetch_bypassTranslation (_zz_371_ ), //i + .io_cpu_fetch_haltIt (IBusCachedPlugin_cache_io_cpu_fetch_haltIt ), //o + .io_cpu_decode_isValid (_zz_372_ ), //i + .io_cpu_decode_isStuck (_zz_373_ ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_374_ ), //i + .io_cpu_decode_exceptionType (IBusCachedPlugin_cache_io_cpu_decode_exceptionType[3:0] ), //o + .io_cpu_fill_valid (_zz_375_ ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_spr_valid (_zz_237_ ), //i + .io_spr_payload_id (_zz_376_[9:0] ), //i + .io_spr_payload_data (writeBack_SRC1[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1_ ( + .io_cpu_execute_isValid (_zz_377_ ), //i + .io_cpu_execute_address (_zz_378_[31:0] ), //i + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_379_[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_memory_isValid (_zz_380_ ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isRemoved (memory_arbitration_removeIt ), //i + .io_cpu_memory_isWrite (dataCache_1__io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_381_[31:0] ), //i + .io_cpu_memory_mmuBus_cmd_isValid (dataCache_1__io_cpu_memory_mmuBus_cmd_isValid ), //o + .io_cpu_memory_mmuBus_cmd_virtualAddress (dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress[31:0] ), //o + .io_cpu_memory_mmuBus_cmd_bypassTranslation (dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation ), //o + .io_cpu_memory_mmuBus_rsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuBus_rsp_isIoAccess (_zz_382_ ), //i + .io_cpu_memory_mmuBus_rsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuBus_rsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuBus_rsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuBus_rsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuBus_rsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuBus_spr_valid (dataCache_1__io_cpu_memory_mmuBus_spr_valid ), //o + .io_cpu_memory_mmuBus_spr_payload_id (dataCache_1__io_cpu_memory_mmuBus_spr_payload_id[9:0] ), //o + .io_cpu_memory_mmuBus_spr_payload_data (dataCache_1__io_cpu_memory_mmuBus_spr_payload_data[31:0] ), //o + .io_cpu_memory_mmuBus_end (dataCache_1__io_cpu_memory_mmuBus_end ), //o + .io_cpu_memory_mmuBus_busy (DBusCachedPlugin_mmuBus_busy ), //i + .io_cpu_memory_bypassTranslation (_zz_383_ ), //i + .io_cpu_writeBack_isValid (_zz_384_ ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_385_ ), //i + .io_cpu_writeBack_haltIt (dataCache_1__io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1__io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1__io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_386_[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1__io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1__io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1__io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_exceptionType (dataCache_1__io_cpu_writeBack_exceptionType[3:0] ), //o + .io_cpu_redo (dataCache_1__io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_387_ ), //i + .io_cpu_flush_ready (dataCache_1__io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1__io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_388_ ), //i + .io_mem_cmd_payload_wr (dataCache_1__io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_address (dataCache_1__io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1__io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1__io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1__io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1__io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_662_) + 2'b00 : begin + _zz_393_ = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_393_ = SPRPlugin_jumpInterface_payload; + end + default : begin + _zz_393_ = BranchPlugin_jumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_1__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_1__string = "RA"; + default : _zz_1__string = "??"; + endcase + end + always @(*) begin + case(_zz_2_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_2__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_2__string = "RA"; + default : _zz_2__string = "??"; + endcase + end + always @(*) begin + case(_zz_3_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_3__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_3__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_3__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_3__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_4__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_4__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_4__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_4__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + default : _zz_4__string = "??????"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_5__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_5__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_5__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_5__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_5__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_5__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_5__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_5__string = "RA "; + default : _zz_5__string = "????????"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_6__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_6__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_6__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_6__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_6__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_6__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_6__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_6__string = "RA "; + default : _zz_6__string = "????????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : decode_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : decode_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : decode_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : decode_DECODER_stageables_8_string = "SPEC "; + default : decode_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_7__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_7__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_7__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_7__string = "SPEC "; + default : _zz_7__string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_8__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_8__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_8__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_8__string = "SPEC "; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_9__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_9__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_9__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_9__string = "SPEC "; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : decode_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : decode_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : decode_DECODER_stageables_1_string = "CA_1"; + default : decode_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_10__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_10__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_10__string = "CA_1"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_11__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_11__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_11__string = "CA_1"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_12__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_12__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_12__string = "CA_1"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(memory_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : memory_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : memory_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : memory_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : memory_DECODER_stageables_7_string = "W "; + default : memory_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(_zz_13_) + `DataSizeEnum_defaultEncoding_B : _zz_13__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_13__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_13__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_13__string = "W "; + default : _zz_13__string = "??"; + endcase + end + always @(*) begin + case(_zz_14_) + `DataSizeEnum_defaultEncoding_B : _zz_14__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_14__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_14__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_14__string = "W "; + default : _zz_14__string = "??"; + endcase + end + always @(*) begin + case(_zz_15_) + `DataSizeEnum_defaultEncoding_B : _zz_15__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_15__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_15__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_15__string = "W "; + default : _zz_15__string = "??"; + endcase + end + always @(*) begin + case(_zz_16_) + `DataSizeEnum_defaultEncoding_B : _zz_16__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_16__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_16__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_16__string = "W "; + default : _zz_16__string = "??"; + endcase + end + always @(*) begin + case(_zz_17_) + `DataSizeEnum_defaultEncoding_B : _zz_17__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_17__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_17__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_17__string = "W "; + default : _zz_17__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : decode_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : decode_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : decode_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : decode_DECODER_stageables_7_string = "W "; + default : decode_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(_zz_18_) + `DataSizeEnum_defaultEncoding_B : _zz_18__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_18__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_18__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_18__string = "W "; + default : _zz_18__string = "??"; + endcase + end + always @(*) begin + case(_zz_19_) + `DataSizeEnum_defaultEncoding_B : _zz_19__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_19__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_19__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_19__string = "W "; + default : _zz_19__string = "??"; + endcase + end + always @(*) begin + case(_zz_20_) + `DataSizeEnum_defaultEncoding_B : _zz_20__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_20__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_20__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_20__string = "W "; + default : _zz_20__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : decode_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : decode_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : decode_DECODER_stageables_51_string = "MTCRF "; + default : decode_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(_zz_21_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_21__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_21__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_21__string = "MTCRF "; + default : _zz_21__string = "??????"; + endcase + end + always @(*) begin + case(_zz_22_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_22__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_22__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_22__string = "MTCRF "; + default : _zz_22__string = "??????"; + endcase + end + always @(*) begin + case(_zz_23_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_23__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_23__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_23__string = "MTCRF "; + default : _zz_23__string = "??????"; + endcase + end + always @(*) begin + case(memory_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : memory_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : memory_MSR_ENDIAN_string = "LE"; + default : memory_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_24_) + `EndianEnum_defaultEncoding_BE : _zz_24__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_24__string = "LE"; + default : _zz_24__string = "??"; + endcase + end + always @(*) begin + case(_zz_25_) + `EndianEnum_defaultEncoding_BE : _zz_25__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_25__string = "LE"; + default : _zz_25__string = "??"; + endcase + end + always @(*) begin + case(_zz_26_) + `EndianEnum_defaultEncoding_BE : _zz_26__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_26__string = "LE"; + default : _zz_26__string = "??"; + endcase + end + always @(*) begin + case(_zz_27_) + `EndianEnum_defaultEncoding_BE : _zz_27__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_27__string = "LE"; + default : _zz_27__string = "??"; + endcase + end + always @(*) begin + case(_zz_28_) + `EndianEnum_defaultEncoding_BE : _zz_28__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_28__string = "LE"; + default : _zz_28__string = "??"; + endcase + end + always @(*) begin + case(_zz_29_) + `EndianEnum_defaultEncoding_BE : _zz_29__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_29__string = "LE"; + default : _zz_29__string = "??"; + endcase + end + always @(*) begin + case(_zz_30_) + `EndianEnum_defaultEncoding_BE : _zz_30__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_30__string = "LE"; + default : _zz_30__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : decode_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : decode_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : decode_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : decode_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : decode_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : decode_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : decode_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : decode_DECODER_stageables_19_string = "EXTSH "; + default : decode_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(_zz_31_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_31__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_31__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_31__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_31__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_31__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_31__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_31__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_31__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_31__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_31__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_31__string = "EXTSH "; + default : _zz_31__string = "??????"; + endcase + end + always @(*) begin + case(_zz_32_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_32__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_32__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_32__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_32__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_32__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_32__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_32__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_32__string = "EXTSH "; + default : _zz_32__string = "??????"; + endcase + end + always @(*) begin + case(_zz_33_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_33__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_33__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_33__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_33__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_33__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_33__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_33__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_33__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_33__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_33__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_33__string = "EXTSH "; + default : _zz_33__string = "??????"; + endcase + end + always @(*) begin + case(_zz_34_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_34__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_34__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_34__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_34__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_34__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_34__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_34__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_34__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_34__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_34__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_34__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_34__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_34__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_34__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_34__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_34__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_34__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_34__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_34__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_34__string = "DECLNK"; + default : _zz_34__string = "??????"; + endcase + end + always @(*) begin + case(_zz_35_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_35__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_35__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_35__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_35__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_35__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_35__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_35__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_35__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_35__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_35__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_35__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_35__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_35__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_35__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_35__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_35__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_35__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_35__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_35__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_35__string = "DECLNK"; + default : _zz_35__string = "??????"; + endcase + end + always @(*) begin + case(execute_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_CR_WRITE_op_string = "DECLNK"; + default : execute_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_36_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_36__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_36__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_36__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_36__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_36__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_36__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_36__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_36__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_36__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_36__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_36__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_36__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_36__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_36__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_36__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_36__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_36__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_36__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_36__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_36__string = "DECLNK"; + default : _zz_36__string = "??????"; + endcase + end + always @(*) begin + case(_zz_37_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_37__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_37__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_37__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_37__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_37__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_37__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_37__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_37__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_37__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_37__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_37__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_37__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_37__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_37__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_37__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_37__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_37__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_37__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_37__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_37__string = "DECLNK"; + default : _zz_37__string = "??????"; + endcase + end + always @(*) begin + case(_zz_38_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_38__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_38__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_38__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_38__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_38__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_38__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_38__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_38__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_38__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_38__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_38__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_38__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_38__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_38__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_38__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_38__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_38__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_38__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_38__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_38__string = "DECLNK"; + default : _zz_38__string = "??????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : decode_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : decode_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : decode_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : decode_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : decode_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : decode_DECODER_stageables_0_string = "PRTYW "; + default : decode_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(_zz_39_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_39__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_39__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_39__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_39__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_39__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_39__string = "PRTYW "; + default : _zz_39__string = "???????"; + endcase + end + always @(*) begin + case(_zz_40_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_40__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_40__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_40__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_40__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_40__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_40__string = "PRTYW "; + default : _zz_40__string = "???????"; + endcase + end + always @(*) begin + case(_zz_41_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_41__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_41__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_41__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_41__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_41__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_41__string = "PRTYW "; + default : _zz_41__string = "???????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : decode_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : decode_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : decode_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : decode_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : decode_DECODER_stageables_16_string = "SHIFTRA"; + default : decode_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(_zz_42_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_42__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_42__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_42__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_42__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_42__string = "SHIFTRA"; + default : _zz_42__string = "???????"; + endcase + end + always @(*) begin + case(_zz_43_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_43__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_43__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_43__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_43__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_43__string = "SHIFTRA"; + default : _zz_43__string = "???????"; + endcase + end + always @(*) begin + case(_zz_44_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_44__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_44__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_44__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_44__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_44__string = "SHIFTRA"; + default : _zz_44__string = "???????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : decode_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : decode_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : decode_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : decode_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : decode_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : decode_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : decode_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : decode_DECODER_stageables_20_string = "ORC "; + default : decode_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(_zz_45_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_45__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_45__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_45__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_45__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_45__string = "ORC "; + default : _zz_45__string = "??????"; + endcase + end + always @(*) begin + case(_zz_46_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_46__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_46__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_46__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_46__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_46__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_46__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_46__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_46__string = "ORC "; + default : _zz_46__string = "??????"; + endcase + end + always @(*) begin + case(_zz_47_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_47__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_47__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_47__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_47__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_47__string = "ORC "; + default : _zz_47__string = "??????"; + endcase + end + always @(*) begin + case(_zz_48_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_48__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_48__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_48__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_48__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_48__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_48__string = "BCTAR"; + default : _zz_48__string = "?????"; + endcase + end + always @(*) begin + case(_zz_49_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_49__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_49__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_49__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_49__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_49__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_49__string = "BCTAR"; + default : _zz_49__string = "?????"; + endcase + end + always @(*) begin + case(memory_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : memory_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : memory_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : memory_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : memory_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : memory_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : memory_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : memory_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : memory_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : memory_DECODER_stageables_49_string = "TWI "; + default : memory_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_50__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_50__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_50__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_50__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_50__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_50__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_50__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_50__string = "TWI "; + default : _zz_50__string = "?????"; + endcase + end + always @(*) begin + case(_zz_51_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_51__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_51__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_51__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_51__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_51__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_51__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_51__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_51__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_51__string = "TWI "; + default : _zz_51__string = "?????"; + endcase + end + always @(*) begin + case(_zz_52_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_52__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_52__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_52__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_52__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_52__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_52__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_52__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_52__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_52__string = "TWI "; + default : _zz_52__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : decode_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : decode_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : decode_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : decode_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : decode_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : decode_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : decode_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : decode_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : decode_DECODER_stageables_49_string = "TWI "; + default : decode_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_53_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_53__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_53__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_53__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_53__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_53__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_53__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_53__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_53__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_53__string = "TWI "; + default : _zz_53__string = "?????"; + endcase + end + always @(*) begin + case(_zz_54_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_54__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_54__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_54__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_54__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_54__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_54__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_54__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_54__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_54__string = "TWI "; + default : _zz_54__string = "?????"; + endcase + end + always @(*) begin + case(_zz_55_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_55__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_55__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_55__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_55__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_55__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_55__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_55__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_55__string = "TWI "; + default : _zz_55__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : decode_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : decode_DECODER_stageables_44_string = "RB "; + default : decode_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_56__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_56__string = "RB "; + default : _zz_56__string = "???"; + endcase + end + always @(*) begin + case(_zz_57_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_57__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_57__string = "RB "; + default : _zz_57__string = "???"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_58__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_58__string = "RB "; + default : _zz_58__string = "???"; + endcase + end + always @(*) begin + case(writeBack_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : writeBack_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : writeBack_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : writeBack_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : writeBack_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : writeBack_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : writeBack_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : writeBack_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : writeBack_DECODER_stageables_49_string = "TWI "; + default : writeBack_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_59_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_59__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_59__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_59__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_59__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_59__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_59__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_59__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_59__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_59__string = "TWI "; + default : _zz_59__string = "?????"; + endcase + end + always @(*) begin + case(_zz_60_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_60__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_60__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_60__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_60__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_60__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_60__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_60__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_60__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_60__string = "TWI "; + default : _zz_60__string = "?????"; + endcase + end + always @(*) begin + case(_zz_61_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_61__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_61__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_61__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_61__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_61__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_61__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_61__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_61__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_61__string = "TWI "; + default : _zz_61__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : execute_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : execute_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : execute_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : execute_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : execute_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : execute_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : execute_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : execute_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : execute_DECODER_stageables_49_string = "TWI "; + default : execute_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_62_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_62__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_62__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_62__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_62__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_62__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_62__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_62__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_62__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_62__string = "TWI "; + default : _zz_62__string = "?????"; + endcase + end + always @(*) begin + case(_zz_63_) + `EndianEnum_defaultEncoding_BE : _zz_63__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_63__string = "LE"; + default : _zz_63__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : decode_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : decode_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : decode_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : decode_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : decode_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : decode_DECODER_stageables_13_string = "BCTAR"; + default : decode_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(_zz_65_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_65__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_65__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_65__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_65__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_65__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_65__string = "BCTAR"; + default : _zz_65__string = "?????"; + endcase + end + always @(*) begin + case(memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : memory_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : memory_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : memory_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : memory_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : memory_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : memory_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : memory_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : memory_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : memory_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : memory_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : memory_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : memory_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : memory_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : memory_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : memory_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : memory_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : memory_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : memory_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : memory_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : memory_CR_WRITE_op_string = "DECLNK"; + default : memory_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_66_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_66__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_66__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_66__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_66__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_66__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_66__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_66__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_66__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_66__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_66__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_66__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_66__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_66__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_66__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_66__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_66__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_66__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_66__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_66__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_66__string = "DECLNK"; + default : _zz_66__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : execute_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : execute_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : execute_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : execute_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : execute_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : execute_DECODER_stageables_13_string = "BCTAR"; + default : execute_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(_zz_67_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_67__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_67__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_67__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_67__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_67__string = "BCTAR"; + default : _zz_67__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : execute_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : execute_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : execute_DECODER_stageables_1_string = "CA_1"; + default : execute_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_70_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_70__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_70__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_70__string = "CA_1"; + default : _zz_70__string = "????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : execute_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : execute_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : execute_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : execute_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : execute_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : execute_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : execute_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_26_string = "RA "; + default : execute_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(_zz_71_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_71__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_71__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_71__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_71__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_71__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_71__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_71__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_71__string = "RA "; + default : _zz_71__string = "????????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : execute_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : execute_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : execute_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : execute_DECODER_stageables_38_string = "RS "; + default : execute_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(_zz_74_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_74__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_74__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_74__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_74__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_74__string = "RS "; + default : _zz_74__string = "??????"; + endcase + end + always @(*) begin + case(_zz_76_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_76__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_76__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_76__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_76__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_76__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_76__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_76__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_76__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_76__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_76__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_76__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_76__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_76__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_76__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_76__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_76__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_76__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_76__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_76__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_76__string = "DECLNK"; + default : _zz_76__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : execute_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : execute_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : execute_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : execute_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : execute_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : execute_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : execute_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : execute_DECODER_stageables_20_string = "ORC "; + default : execute_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(_zz_77_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_77__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_77__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_77__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_77__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_77__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_77__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_77__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_77__string = "ORC "; + default : _zz_77__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : execute_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : execute_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : execute_DECODER_stageables_51_string = "MTCRF "; + default : execute_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(_zz_78_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_78__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_78__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_78__string = "MTCRF "; + default : _zz_78__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : execute_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_12_string = "RA"; + default : execute_DECODER_stageables_12_string = "??"; + endcase + end + always @(*) begin + case(_zz_80_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_80__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_80__string = "RA"; + default : _zz_80__string = "??"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : execute_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : execute_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : execute_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : execute_DECODER_stageables_8_string = "SPEC "; + default : execute_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_81__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_81__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_81__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_81__string = "SPEC "; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : execute_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : execute_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : execute_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : execute_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : execute_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : execute_DECODER_stageables_0_string = "PRTYW "; + default : execute_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(_zz_82_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_82__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_82__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_82__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_82__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_82__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_82__string = "PRTYW "; + default : _zz_82__string = "???????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : execute_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : execute_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : execute_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : execute_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : execute_DECODER_stageables_16_string = "SHIFTRA"; + default : execute_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(_zz_98_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_98__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_98__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_98__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_98__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_98__string = "SHIFTRA"; + default : _zz_98__string = "???????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : execute_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : execute_DECODER_stageables_44_string = "RB "; + default : execute_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(_zz_99_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_99__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_99__string = "RB "; + default : _zz_99__string = "???"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : execute_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : execute_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : execute_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : execute_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : execute_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : execute_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : execute_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : execute_DECODER_stageables_19_string = "EXTSH "; + default : execute_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(_zz_100_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_100__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_100__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_100__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_100__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_100__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_100__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_100__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_100__string = "EXTSH "; + default : _zz_100__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : writeBack_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : writeBack_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : writeBack_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : writeBack_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : writeBack_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : writeBack_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : writeBack_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : writeBack_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : writeBack_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : writeBack_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : writeBack_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : writeBack_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : writeBack_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : writeBack_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : writeBack_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : writeBack_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : writeBack_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : writeBack_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : writeBack_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : writeBack_CR_WRITE_op_string = "DECLNK"; + default : writeBack_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_101_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_101__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_101__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_101__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_101__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_101__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_101__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_101__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_101__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_101__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_101__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_101__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_101__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_101__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_101__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_101__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_101__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_101__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_101__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_101__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_101__string = "DECLNK"; + default : _zz_101__string = "??????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : decode_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_12_string = "RA"; + default : decode_DECODER_stageables_12_string = "??"; + endcase + end + always @(*) begin + case(_zz_104_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_104__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_104__string = "RA"; + default : _zz_104__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : decode_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : decode_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : decode_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : decode_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : decode_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : decode_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : decode_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_26_string = "RA "; + default : decode_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(_zz_105_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_105__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_105__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_105__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_105__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_105__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_105__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_105__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_105__string = "RA "; + default : _zz_105__string = "????????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : decode_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : decode_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : decode_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : decode_DECODER_stageables_38_string = "RS "; + default : decode_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(_zz_106_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_106__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_106__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_106__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_106__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_106__string = "RS "; + default : _zz_106__string = "??????"; + endcase + end + always @(*) begin + case(_zz_107_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_107__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_107__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_107__string = "MTCRF "; + default : _zz_107__string = "??????"; + endcase + end + always @(*) begin + case(_zz_108_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_108__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_108__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_108__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_108__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_108__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_108__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_108__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_108__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_108__string = "TWI "; + default : _zz_108__string = "?????"; + endcase + end + always @(*) begin + case(_zz_109_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_109__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_109__string = "RB "; + default : _zz_109__string = "???"; + endcase + end + always @(*) begin + case(_zz_110_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_110__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_110__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_110__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_110__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_110__string = "RS "; + default : _zz_110__string = "??????"; + endcase + end + always @(*) begin + case(_zz_111_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_111__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_111__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_111__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_111__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_111__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_111__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_111__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_111__string = "RA "; + default : _zz_111__string = "????????"; + endcase + end + always @(*) begin + case(_zz_112_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_112__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_112__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_112__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_112__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_112__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_112__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_112__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_112__string = "ORC "; + default : _zz_112__string = "??????"; + endcase + end + always @(*) begin + case(_zz_113_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_113__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_113__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_113__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_113__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_113__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_113__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_113__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_113__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_113__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_113__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_113__string = "EXTSH "; + default : _zz_113__string = "??????"; + endcase + end + always @(*) begin + case(_zz_114_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_114__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_114__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_114__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_114__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_114__string = "SHIFTRA"; + default : _zz_114__string = "???????"; + endcase + end + always @(*) begin + case(_zz_115_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_115__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_115__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_115__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_115__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_115__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_115__string = "BCTAR"; + default : _zz_115__string = "?????"; + endcase + end + always @(*) begin + case(_zz_116_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_116__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_116__string = "RA"; + default : _zz_116__string = "??"; + endcase + end + always @(*) begin + case(_zz_117_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_117__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_117__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_117__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_117__string = "SPEC "; + default : _zz_117__string = "?????"; + endcase + end + always @(*) begin + case(_zz_118_) + `DataSizeEnum_defaultEncoding_B : _zz_118__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_118__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_118__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_118__string = "W "; + default : _zz_118__string = "??"; + endcase + end + always @(*) begin + case(_zz_119_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_119__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_119__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_119__string = "CA_1"; + default : _zz_119__string = "????"; + endcase + end + always @(*) begin + case(_zz_120_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_120__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_120__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_120__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_120__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_120__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_120__string = "PRTYW "; + default : _zz_120__string = "???????"; + endcase + end + always @(*) begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : writeBack_DATA_SIZE_string = "B "; + `DataSizeEnum_defaultEncoding_H : writeBack_DATA_SIZE_string = "H "; + `DataSizeEnum_defaultEncoding_HA : writeBack_DATA_SIZE_string = "HA"; + `DataSizeEnum_defaultEncoding_W : writeBack_DATA_SIZE_string = "W "; + default : writeBack_DATA_SIZE_string = "??"; + endcase + end + always @(*) begin + case(_zz_122_) + `DataSizeEnum_defaultEncoding_B : _zz_122__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_122__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_122__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_122__string = "W "; + default : _zz_122__string = "??"; + endcase + end + always @(*) begin + case(writeBack_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : writeBack_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : writeBack_MSR_ENDIAN_string = "LE"; + default : writeBack_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_123_) + `EndianEnum_defaultEncoding_BE : _zz_123__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_123__string = "LE"; + default : _zz_123__string = "??"; + endcase + end + always @(*) begin + case(execute_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : execute_DATA_SIZE_string = "B "; + `DataSizeEnum_defaultEncoding_H : execute_DATA_SIZE_string = "H "; + `DataSizeEnum_defaultEncoding_HA : execute_DATA_SIZE_string = "HA"; + `DataSizeEnum_defaultEncoding_W : execute_DATA_SIZE_string = "W "; + default : execute_DATA_SIZE_string = "??"; + endcase + end + always @(*) begin + case(_zz_125_) + `DataSizeEnum_defaultEncoding_B : _zz_125__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_125__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_125__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_125__string = "W "; + default : _zz_125__string = "??"; + endcase + end + always @(*) begin + case(execute_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : execute_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : execute_MSR_ENDIAN_string = "LE"; + default : execute_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_126_) + `EndianEnum_defaultEncoding_BE : _zz_126__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_126__string = "LE"; + default : _zz_126__string = "??"; + endcase + end + always @(*) begin + case(decode_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : decode_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : decode_MSR_ENDIAN_string = "LE"; + default : decode_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_129_) + `EndianEnum_defaultEncoding_BE : _zz_129__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_129__string = "LE"; + default : _zz_129__string = "??"; + endcase + end + always @(*) begin + case(IBusCachedPlugin_decodeExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PM "; + default : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(DBusCachedPlugin_exceptionBus_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PM "; + default : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(decodeExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : decodeExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : decodeExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : decodeExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : decodeExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : decodeExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : decodeExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : decodeExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : decodeExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : decodeExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : decodeExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : decodeExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : decodeExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : decodeExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : decodeExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : decodeExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : decodeExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : decodeExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : decodeExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : decodeExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : decodeExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : decodeExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : decodeExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : decodeExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : decodeExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : decodeExceptionPort_payload_codePPC_string = "PM "; + default : decodeExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(BranchPlugin_branchExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : BranchPlugin_branchExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : BranchPlugin_branchExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : BranchPlugin_branchExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : BranchPlugin_branchExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : BranchPlugin_branchExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PM "; + default : BranchPlugin_branchExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(SPRPlugin_selfException_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_selfException_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_selfException_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_selfException_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_selfException_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_selfException_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_selfException_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_selfException_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_selfException_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_selfException_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_selfException_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_selfException_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_selfException_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_selfException_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_selfException_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_selfException_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_selfException_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_selfException_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_selfException_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_selfException_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_selfException_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_selfException_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_selfException_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_selfException_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_selfException_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_selfException_payload_codePPC_string = "PM "; + default : SPRPlugin_selfException_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(_zz_223_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_223__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_223__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_223__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_223__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_223__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_223__string = "PRTYW "; + default : _zz_223__string = "???????"; + endcase + end + always @(*) begin + case(_zz_224_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_224__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_224__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_224__string = "CA_1"; + default : _zz_224__string = "????"; + endcase + end + always @(*) begin + case(_zz_225_) + `DataSizeEnum_defaultEncoding_B : _zz_225__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_225__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_225__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_225__string = "W "; + default : _zz_225__string = "??"; + endcase + end + always @(*) begin + case(_zz_226_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_226__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_226__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_226__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_226__string = "SPEC "; + default : _zz_226__string = "?????"; + endcase + end + always @(*) begin + case(_zz_227_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_227__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_227__string = "RA"; + default : _zz_227__string = "??"; + endcase + end + always @(*) begin + case(_zz_228_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_228__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_228__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_228__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_228__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_228__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_228__string = "BCTAR"; + default : _zz_228__string = "?????"; + endcase + end + always @(*) begin + case(_zz_229_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_229__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_229__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_229__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_229__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_229__string = "SHIFTRA"; + default : _zz_229__string = "???????"; + endcase + end + always @(*) begin + case(_zz_230_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_230__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_230__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_230__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_230__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_230__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_230__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_230__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_230__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_230__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_230__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_230__string = "EXTSH "; + default : _zz_230__string = "??????"; + endcase + end + always @(*) begin + case(_zz_231_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_231__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_231__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_231__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_231__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_231__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_231__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_231__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_231__string = "ORC "; + default : _zz_231__string = "??????"; + endcase + end + always @(*) begin + case(_zz_232_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_232__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_232__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_232__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_232__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_232__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_232__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_232__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_232__string = "RA "; + default : _zz_232__string = "????????"; + endcase + end + always @(*) begin + case(_zz_233_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_233__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_233__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_233__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_233__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_233__string = "RS "; + default : _zz_233__string = "??????"; + endcase + end + always @(*) begin + case(_zz_234_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_234__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_234__string = "RB "; + default : _zz_234__string = "???"; + endcase + end + always @(*) begin + case(_zz_235_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_235__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_235__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_235__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_235__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_235__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_235__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_235__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_235__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_235__string = "TWI "; + default : _zz_235__string = "?????"; + endcase + end + always @(*) begin + case(_zz_236_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_236__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_236__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_236__string = "MTCRF "; + default : _zz_236__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_RegFilePlugin_crBusPort_payload_op) + `CRBusCmdEnum_defaultEncoding_NOP : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : writeBack_RegFilePlugin_crBusPort_payload_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : writeBack_RegFilePlugin_crBusPort_payload_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : writeBack_RegFilePlugin_crBusPort_payload_op_string = "DECLNK"; + default : writeBack_RegFilePlugin_crBusPort_payload_op_string = "??????"; + endcase + end + always @(*) begin + case(ALU2_crBus_op) + `CRBusCmdEnum_defaultEncoding_NOP : ALU2_crBus_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : ALU2_crBus_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : ALU2_crBus_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : ALU2_crBus_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : ALU2_crBus_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : ALU2_crBus_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : ALU2_crBus_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : ALU2_crBus_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : ALU2_crBus_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : ALU2_crBus_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : ALU2_crBus_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : ALU2_crBus_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : ALU2_crBus_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : ALU2_crBus_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : ALU2_crBus_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : ALU2_crBus_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : ALU2_crBus_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : ALU2_crBus_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : ALU2_crBus_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : ALU2_crBus_op_string = "DECLNK"; + default : ALU2_crBus_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_273_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_273__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_273__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_273__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_273__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_273__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_273__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_273__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_273__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_273__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_273__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_273__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_273__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_273__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_273__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_273__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_273__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_273__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_273__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_273__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_273__string = "DECLNK"; + default : _zz_273__string = "??????"; + endcase + end + always @(*) begin + case(MULDIV1_crBusPort_payload_op) + `CRBusCmdEnum_defaultEncoding_NOP : MULDIV1_crBusPort_payload_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : MULDIV1_crBusPort_payload_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : MULDIV1_crBusPort_payload_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : MULDIV1_crBusPort_payload_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : MULDIV1_crBusPort_payload_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : MULDIV1_crBusPort_payload_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : MULDIV1_crBusPort_payload_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : MULDIV1_crBusPort_payload_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : MULDIV1_crBusPort_payload_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : MULDIV1_crBusPort_payload_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : MULDIV1_crBusPort_payload_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : MULDIV1_crBusPort_payload_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : MULDIV1_crBusPort_payload_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : MULDIV1_crBusPort_payload_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : MULDIV1_crBusPort_payload_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : MULDIV1_crBusPort_payload_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : MULDIV1_crBusPort_payload_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : MULDIV1_crBusPort_payload_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : MULDIV1_crBusPort_payload_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : MULDIV1_crBusPort_payload_op_string = "DECLNK"; + default : MULDIV1_crBusPort_payload_op_string = "??????"; + endcase + end + always @(*) begin + case(execute_BranchPlugin_crBusPort_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_BranchPlugin_crBusPort_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_BranchPlugin_crBusPort_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_BranchPlugin_crBusPort_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_BranchPlugin_crBusPort_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_BranchPlugin_crBusPort_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_BranchPlugin_crBusPort_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_BranchPlugin_crBusPort_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_BranchPlugin_crBusPort_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_BranchPlugin_crBusPort_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_BranchPlugin_crBusPort_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_BranchPlugin_crBusPort_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_BranchPlugin_crBusPort_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_BranchPlugin_crBusPort_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_BranchPlugin_crBusPort_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_BranchPlugin_crBusPort_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_BranchPlugin_crBusPort_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_BranchPlugin_crBusPort_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_BranchPlugin_crBusPort_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_BranchPlugin_crBusPort_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_BranchPlugin_crBusPort_op_string = "DECLNK"; + default : execute_BranchPlugin_crBusPort_op_string = "??????"; + endcase + end + always @(*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PM "; + default : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(_zz_337_) + `ExcpEnum_defaultEncoding_NONE : _zz_337__string = "NONE "; + `ExcpEnum_defaultEncoding_SC : _zz_337__string = "SC "; + `ExcpEnum_defaultEncoding_SCV : _zz_337__string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : _zz_337__string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : _zz_337__string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : _zz_337__string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : _zz_337__string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : _zz_337__string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : _zz_337__string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : _zz_337__string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : _zz_337__string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : _zz_337__string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : _zz_337__string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : _zz_337__string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : _zz_337__string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : _zz_337__string = "FP "; + `ExcpEnum_defaultEncoding_VEC : _zz_337__string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : _zz_337__string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : _zz_337__string = "FAC "; + `ExcpEnum_defaultEncoding_SR : _zz_337__string = "SR "; + `ExcpEnum_defaultEncoding_MC : _zz_337__string = "MC "; + `ExcpEnum_defaultEncoding_EXT : _zz_337__string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : _zz_337__string = "DEC "; + `ExcpEnum_defaultEncoding_TR : _zz_337__string = "TR "; + `ExcpEnum_defaultEncoding_PM : _zz_337__string = "PM "; + default : _zz_337__string = "????????"; + endcase + end + always @(*) begin + case(_zz_340_) + `ExcpEnum_defaultEncoding_NONE : _zz_340__string = "NONE "; + `ExcpEnum_defaultEncoding_SC : _zz_340__string = "SC "; + `ExcpEnum_defaultEncoding_SCV : _zz_340__string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : _zz_340__string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : _zz_340__string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : _zz_340__string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : _zz_340__string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : _zz_340__string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : _zz_340__string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : _zz_340__string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : _zz_340__string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : _zz_340__string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : _zz_340__string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : _zz_340__string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : _zz_340__string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : _zz_340__string = "FP "; + `ExcpEnum_defaultEncoding_VEC : _zz_340__string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : _zz_340__string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : _zz_340__string = "FAC "; + `ExcpEnum_defaultEncoding_SR : _zz_340__string = "SR "; + `ExcpEnum_defaultEncoding_MC : _zz_340__string = "MC "; + `ExcpEnum_defaultEncoding_EXT : _zz_340__string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : _zz_340__string = "DEC "; + `ExcpEnum_defaultEncoding_TR : _zz_340__string = "TR "; + `ExcpEnum_defaultEncoding_PM : _zz_340__string = "PM "; + default : _zz_340__string = "????????"; + endcase + end + always @(*) begin + case(SPRPlugin_intType) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_intType_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_intType_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_intType_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_intType_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_intType_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_intType_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_intType_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_intType_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_intType_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_intType_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_intType_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_intType_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_intType_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_intType_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_intType_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_intType_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_intType_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_intType_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_intType_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_intType_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_intType_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_intType_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_intType_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_intType_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_intType_string = "PM "; + default : SPRPlugin_intType_string = "????????"; + endcase + end + always @(*) begin + case(execute_SPRPLUGIN_opExcp_codePPC) + `ExcpEnum_defaultEncoding_NONE : execute_SPRPLUGIN_opExcp_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : execute_SPRPLUGIN_opExcp_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : execute_SPRPLUGIN_opExcp_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : execute_SPRPLUGIN_opExcp_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : execute_SPRPLUGIN_opExcp_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : execute_SPRPLUGIN_opExcp_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : execute_SPRPLUGIN_opExcp_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : execute_SPRPLUGIN_opExcp_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : execute_SPRPLUGIN_opExcp_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : execute_SPRPLUGIN_opExcp_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : execute_SPRPLUGIN_opExcp_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : execute_SPRPLUGIN_opExcp_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : execute_SPRPLUGIN_opExcp_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : execute_SPRPLUGIN_opExcp_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : execute_SPRPLUGIN_opExcp_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : execute_SPRPLUGIN_opExcp_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : execute_SPRPLUGIN_opExcp_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : execute_SPRPLUGIN_opExcp_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : execute_SPRPLUGIN_opExcp_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : execute_SPRPLUGIN_opExcp_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : execute_SPRPLUGIN_opExcp_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : execute_SPRPLUGIN_opExcp_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : execute_SPRPLUGIN_opExcp_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : execute_SPRPLUGIN_opExcp_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : execute_SPRPLUGIN_opExcp_codePPC_string = "PM "; + default : execute_SPRPLUGIN_opExcp_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : decode_to_execute_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : decode_to_execute_DECODER_stageables_44_string = "RB "; + default : decode_to_execute_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : decode_to_execute_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : decode_to_execute_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : decode_to_execute_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : decode_to_execute_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : decode_to_execute_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : decode_to_execute_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : decode_to_execute_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : decode_to_execute_DECODER_stageables_49_string = "TWI "; + default : decode_to_execute_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : execute_to_memory_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : execute_to_memory_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : execute_to_memory_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : execute_to_memory_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : execute_to_memory_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : execute_to_memory_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : execute_to_memory_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : execute_to_memory_DECODER_stageables_49_string = "TWI "; + default : execute_to_memory_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : memory_to_writeBack_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : memory_to_writeBack_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : memory_to_writeBack_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : memory_to_writeBack_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : memory_to_writeBack_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : memory_to_writeBack_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : memory_to_writeBack_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : memory_to_writeBack_DECODER_stageables_49_string = "TWI "; + default : memory_to_writeBack_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : decode_to_execute_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : decode_to_execute_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : decode_to_execute_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : decode_to_execute_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : decode_to_execute_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : decode_to_execute_DECODER_stageables_13_string = "BCTAR"; + default : decode_to_execute_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : decode_to_execute_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : decode_to_execute_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : decode_to_execute_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : decode_to_execute_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : decode_to_execute_DECODER_stageables_20_string = "ORC "; + default : decode_to_execute_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : decode_to_execute_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : decode_to_execute_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : decode_to_execute_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : decode_to_execute_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : decode_to_execute_DECODER_stageables_16_string = "SHIFTRA"; + default : decode_to_execute_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : decode_to_execute_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : decode_to_execute_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : decode_to_execute_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : decode_to_execute_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : decode_to_execute_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : decode_to_execute_DECODER_stageables_0_string = "PRTYW "; + default : decode_to_execute_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(execute_to_memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_to_memory_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_to_memory_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_to_memory_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_to_memory_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_to_memory_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_to_memory_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_to_memory_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_to_memory_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_to_memory_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_to_memory_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_to_memory_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_to_memory_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_to_memory_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_to_memory_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_to_memory_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_to_memory_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_to_memory_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_to_memory_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_to_memory_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_to_memory_CR_WRITE_op_string = "DECLNK"; + default : execute_to_memory_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : memory_to_writeBack_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : memory_to_writeBack_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : memory_to_writeBack_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : memory_to_writeBack_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : memory_to_writeBack_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : memory_to_writeBack_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : memory_to_writeBack_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : memory_to_writeBack_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : memory_to_writeBack_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : memory_to_writeBack_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : memory_to_writeBack_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : memory_to_writeBack_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : memory_to_writeBack_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : memory_to_writeBack_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : memory_to_writeBack_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : memory_to_writeBack_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : memory_to_writeBack_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : memory_to_writeBack_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : memory_to_writeBack_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : memory_to_writeBack_CR_WRITE_op_string = "DECLNK"; + default : memory_to_writeBack_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : decode_to_execute_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : decode_to_execute_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : decode_to_execute_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : decode_to_execute_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : decode_to_execute_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : decode_to_execute_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : decode_to_execute_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : decode_to_execute_DECODER_stageables_19_string = "EXTSH "; + default : decode_to_execute_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : decode_to_execute_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : decode_to_execute_MSR_ENDIAN_string = "LE"; + default : decode_to_execute_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(execute_to_memory_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : execute_to_memory_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : execute_to_memory_MSR_ENDIAN_string = "LE"; + default : execute_to_memory_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(memory_to_writeBack_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : memory_to_writeBack_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : memory_to_writeBack_MSR_ENDIAN_string = "LE"; + default : memory_to_writeBack_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : decode_to_execute_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : decode_to_execute_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : decode_to_execute_DECODER_stageables_51_string = "MTCRF "; + default : decode_to_execute_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : decode_to_execute_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : decode_to_execute_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : decode_to_execute_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : decode_to_execute_DECODER_stageables_7_string = "W "; + default : decode_to_execute_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(execute_to_memory_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : execute_to_memory_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : execute_to_memory_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : execute_to_memory_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : execute_to_memory_DECODER_stageables_7_string = "W "; + default : execute_to_memory_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(memory_to_writeBack_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : memory_to_writeBack_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : memory_to_writeBack_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : memory_to_writeBack_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : memory_to_writeBack_DECODER_stageables_7_string = "W "; + default : memory_to_writeBack_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : decode_to_execute_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : decode_to_execute_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : decode_to_execute_DECODER_stageables_1_string = "CA_1"; + default : decode_to_execute_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : decode_to_execute_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : decode_to_execute_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : decode_to_execute_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : decode_to_execute_DECODER_stageables_8_string = "SPEC "; + default : decode_to_execute_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : decode_to_execute_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : decode_to_execute_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : decode_to_execute_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : decode_to_execute_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : decode_to_execute_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : decode_to_execute_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : decode_to_execute_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_26_string = "RA "; + default : decode_to_execute_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : decode_to_execute_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : decode_to_execute_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : decode_to_execute_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_DECODER_stageables_38_string = "RS "; + default : decode_to_execute_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : decode_to_execute_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_12_string = "RA"; + default : decode_to_execute_DECODER_stageables_12_string = "??"; + endcase + end + `endif + + assign _zz_1_ = _zz_2_; + assign decode_DECODER_stageables_29 = _zz_447_[0]; + assign decode_DECODER_stageables_25 = _zz_448_[0]; + assign execute_NEXT_PC2 = (execute_PC + 32'h00000004); + assign execute_XER_SO = ALU2_XER[31]; + assign _zz_3_ = _zz_4_; + assign decode_DECODER_stageables_43 = _zz_449_[0]; + assign decode_DECODER_stageables_27 = _zz_450_[0]; + assign decode_CR_FIELD_RD = _zz_64_; + assign _zz_5_ = _zz_6_; + assign decode_DECODER_stageables_21 = _zz_451_[0]; + assign execute_DECODER_stageables_37 = decode_to_execute_DECODER_stageables_37; + assign decode_DECODER_stageables_37 = _zz_452_[0]; + assign decode_DECODER_stageables_8 = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_DECODER_stageables_23 = _zz_453_[0]; + assign memory_SRC_ADD = execute_to_memory_SRC_ADD; + assign decode_DECODER_stageables_46 = _zz_454_[0]; + assign decode_DECODER_stageables_1 = _zz_10_; + assign _zz_11_ = _zz_12_; + assign execute_CR_FIELD_WR = _zz_75_; + assign memory_DECODER_stageables_7 = _zz_13_; + assign _zz_14_ = _zz_15_; + assign _zz_16_ = _zz_17_; + assign decode_DECODER_stageables_7 = _zz_18_; + assign _zz_19_ = _zz_20_; + assign decode_DECODER_stageables_51 = _zz_21_; + assign _zz_22_ = _zz_23_; + assign memory_DECODER_stageables_53 = execute_to_memory_DECODER_stageables_53; + assign execute_DECODER_stageables_53 = decode_to_execute_DECODER_stageables_53; + assign decode_DECODER_stageables_53 = _zz_455_[0]; + assign execute_MUL_HL = ($signed(MUL1_aHigh) * $signed(MUL1_bSLow)); + assign writeBack_REGFILE_WRITE_ADDR = memory_to_writeBack_REGFILE_WRITE_ADDR; + assign memory_REGFILE_WRITE_ADDR = execute_to_memory_REGFILE_WRITE_ADDR; + assign execute_REGFILE_WRITE_ADDR = _zz_263_; + assign decode_DECODER_stageables_35 = _zz_456_[0]; + assign execute_TARGET_MISSMATCH2 = (decode_PC != execute_BRANCH_CALC); + assign execute_DECODER_stageables_31 = decode_to_execute_DECODER_stageables_31; + assign decode_DECODER_stageables_31 = _zz_457_[0]; + assign execute_MUL_LH = ($signed(MUL1_aSLow) * $signed(MUL1_bHigh)); + assign decode_DECODER_stageables_40 = _zz_458_[0]; + assign decode_DECODER_stageables_2 = _zz_459_[0]; + assign execute_RA = decode_to_execute_RA; + assign decode_DECODER_stageables_3 = _zz_460_[0]; + assign decode_DECODER_stageables_14 = _zz_461_[0]; + assign memory_SRC1 = execute_to_memory_SRC1; + assign memory_MSR_ENDIAN = _zz_24_; + assign _zz_25_ = _zz_26_; + assign _zz_27_ = _zz_28_; + assign _zz_29_ = _zz_30_; + assign memory_DECODER_stageables_24 = execute_to_memory_DECODER_stageables_24; + assign execute_DECODER_stageables_24 = decode_to_execute_DECODER_stageables_24; + assign decode_DECODER_stageables_24 = _zz_462_[0]; + assign decode_DECODER_stageables_34 = _zz_463_[0]; + assign decode_DECODER_stageables_18 = _zz_464_[0]; + assign decode_DECODER_stageables_19 = _zz_31_; + assign _zz_32_ = _zz_33_; + assign decode_DECODER_stageables_9 = _zz_465_[0]; + assign decode_DECODER_stageables_45 = _zz_466_[0]; + assign decode_RT_ADDR = _zz_240_; + assign decode_DECODER_stageables_42 = _zz_467_[0]; + assign memory_MUL_LOW = ($signed(_zz_468_) + $signed(_zz_476_)); + assign _zz_34_ = _zz_35_; + assign execute_CR_WRITE_op = _zz_36_; + assign execute_CR_WRITE_ba = ALU2_crBus_ba; + assign execute_CR_WRITE_bb = ALU2_crBus_bb; + assign execute_CR_WRITE_bt = ALU2_crBus_bt; + assign execute_CR_WRITE_imm = ALU2_crBus_imm; + assign execute_CR_WRITE_fxm = ALU2_crBus_fxm; + assign _zz_37_ = _zz_38_; + assign execute_DECODER_stageables_5 = decode_to_execute_DECODER_stageables_5; + assign decode_DECODER_stageables_5 = _zz_477_[0]; + assign execute_DECODER_stageables_15 = decode_to_execute_DECODER_stageables_15; + assign decode_DECODER_stageables_15 = _zz_478_[0]; + assign decode_DECODER_stageables_0 = _zz_39_; + assign _zz_40_ = _zz_41_; + assign execute_BRANCH_LINK = _zz_336_; + assign execute_BRANCH_DO = _zz_334_; + assign memory_DECODER_stageables_39 = execute_to_memory_DECODER_stageables_39; + assign execute_DECODER_stageables_39 = decode_to_execute_DECODER_stageables_39; + assign decode_DECODER_stageables_39 = _zz_479_[0]; + assign memory_DECODER_stageables_56 = execute_to_memory_DECODER_stageables_56; + assign decode_DECODER_stageables_56 = _zz_480_[0]; + assign decode_DECODER_stageables_16 = _zz_42_; + assign _zz_43_ = _zz_44_; + assign decode_DECODER_stageables_11 = _zz_481_[0]; + assign execute_XER_CA = (ALU2_XER[29] ? 1'b1 : 1'b0); + assign writeBack_LOAD_UPDATE_ADDR = memory_to_writeBack_LOAD_UPDATE_ADDR; + assign memory_LOAD_UPDATE_ADDR = execute_to_memory_LOAD_UPDATE_ADDR; + assign execute_LOAD_UPDATE_ADDR = execute_R0_ADDR; + assign execute_MUL_LL = (MUL1_aULow * MUL1_bULow); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign decode_DECODER_stageables_22 = _zz_482_[0]; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_378_[1 : 0]; + assign decode_DECODER_stageables_32 = _zz_483_[0]; + assign decode_DECODER_stageables_54 = _zz_484_[0]; + assign execute_REGFILE_WRITE_DATA = _zz_124_; + assign decode_DECODER_stageables_20 = _zz_45_; + assign _zz_46_ = _zz_47_; + assign decode_DECODER_stageables_57 = _zz_485_[0]; + assign memory_DECODER_stageables_55 = execute_to_memory_DECODER_stageables_55; + assign execute_DECODER_stageables_55 = decode_to_execute_DECODER_stageables_55; + assign decode_DECODER_stageables_55 = _zz_486_[0]; + assign _zz_48_ = _zz_49_; + assign writeBack_LOAD_UPDATE_DATA = memory_to_writeBack_LOAD_UPDATE_DATA; + assign memory_LOAD_UPDATE_DATA = execute_to_memory_LOAD_UPDATE_DATA; + assign execute_LOAD_UPDATE_DATA = execute_SRC_ADD; + assign execute_XER_WRITE_validOV = ALU2_xerBus_validOV; + assign execute_XER_WRITE_validCA = ALU2_xerBus_validCA; + assign execute_XER_WRITE_imm = ALU2_xerBus_imm; + assign decode_DECODER_stageables_48 = _zz_487_[0]; + assign memory_DECODER_stageables_49 = _zz_50_; + assign _zz_51_ = _zz_52_; + assign decode_DECODER_stageables_49 = _zz_53_; + assign _zz_54_ = _zz_55_; + assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard; + assign execute_PREDICTION_CONTEXT_hit = decode_to_execute_PREDICTION_CONTEXT_hit; + assign execute_PREDICTION_CONTEXT_line_source = decode_to_execute_PREDICTION_CONTEXT_line_source; + assign execute_PREDICTION_CONTEXT_line_branchWish = decode_to_execute_PREDICTION_CONTEXT_line_branchWish; + assign execute_PREDICTION_CONTEXT_line_target = decode_to_execute_PREDICTION_CONTEXT_line_target; + assign decode_PREDICTION_CONTEXT_hazard = IBusCachedPlugin_predictor_injectorContext_hazard; + assign decode_PREDICTION_CONTEXT_hit = IBusCachedPlugin_predictor_injectorContext_hit; + assign decode_PREDICTION_CONTEXT_line_source = IBusCachedPlugin_predictor_injectorContext_line_source; + assign decode_PREDICTION_CONTEXT_line_branchWish = IBusCachedPlugin_predictor_injectorContext_line_branchWish; + assign decode_PREDICTION_CONTEXT_line_target = IBusCachedPlugin_predictor_injectorContext_line_target; + assign memory_DECODER_stageables_36 = execute_to_memory_DECODER_stageables_36; + assign execute_DECODER_stageables_36 = decode_to_execute_DECODER_stageables_36; + assign decode_DECODER_stageables_36 = _zz_488_[0]; + assign decode_DECODER_stageables_44 = _zz_56_; + assign _zz_57_ = _zz_58_; + assign decode_DECODER_stageables_28 = _zz_489_[0]; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(MUL1_aHigh) * $signed(MUL1_bHigh)); + assign execute_RB = decode_to_execute_RB; + assign writeBack_DECODER_stageables_49 = _zz_59_; + assign writeBack_DECODER_stageables_39 = memory_to_writeBack_DECODER_stageables_39; + assign execute_DECODER_stageables_40 = decode_to_execute_DECODER_stageables_40; + assign execute_DECODER_stageables_30 = decode_to_execute_DECODER_stageables_30; + always @ (*) begin + _zz_60_ = _zz_61_; + if(execute_arbitration_isValid)begin + if(_zz_394_)begin + if((! execute_SPRPLUGIN_trap))begin + _zz_60_ = `EnvCtrlEnum_defaultEncoding_NONE; + end + end + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TWI))begin + if((! _zz_348_))begin + _zz_60_ = `EnvCtrlEnum_defaultEncoding_NONE; + end + end + end + end + + assign execute_DECODER_stageables_49 = _zz_62_; + assign writeBack_SRC_ADD = memory_to_writeBack_SRC_ADD; + assign memory_NEXT_PC2 = execute_to_memory_NEXT_PC2; + assign memory_PC = execute_to_memory_PC; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_TARGET_MISSMATCH2 = execute_to_memory_TARGET_MISSMATCH2; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_BRANCH_CALC = execute_BranchPlugin_branchAdder; + assign execute_PC = decode_to_execute_PC; + assign decode_DECODER_stageables_6 = _zz_490_[0]; + assign decode_DECODER_stageables_13 = _zz_65_; + assign writeBack_CR_FIELD_WR = memory_to_writeBack_CR_FIELD_WR; + assign execute_BRANCH_DEC = _zz_335_; + assign execute_DECODER_stageables_32 = decode_to_execute_DECODER_stageables_32; + assign memory_BRANCH_DEC = execute_to_memory_BRANCH_DEC; + assign memory_BRANCH_LINK = execute_to_memory_BRANCH_LINK; + assign memory_SPR_ID = execute_to_memory_SPR_ID; + assign memory_DECODER_stageables_32 = execute_to_memory_DECODER_stageables_32; + assign memory_XER_WRITE_validOV = execute_to_memory_XER_WRITE_validOV; + assign memory_XER_WRITE_validCA = execute_to_memory_XER_WRITE_validCA; + assign memory_XER_WRITE_imm = execute_to_memory_XER_WRITE_imm; + assign memory_CR_WRITE_op = _zz_66_; + assign memory_CR_WRITE_ba = execute_to_memory_CR_WRITE_ba; + assign memory_CR_WRITE_bb = execute_to_memory_CR_WRITE_bb; + assign memory_CR_WRITE_bt = execute_to_memory_CR_WRITE_bt; + assign memory_CR_WRITE_imm = execute_to_memory_CR_WRITE_imm; + assign memory_CR_WRITE_fxm = execute_to_memory_CR_WRITE_fxm; + assign memory_DECODER_stageables_31 = execute_to_memory_DECODER_stageables_31; + assign execute_DECODER_stageables_13 = _zz_67_; + assign execute_CR_FIELD_RD = decode_to_execute_CR_FIELD_RD; + assign memory_CR_FIELD_WR = execute_to_memory_CR_FIELD_WR; + always @ (*) begin + _zz_68_ = execute_REGFILE_WRITE_DATA; + if(execute_SPRPLUGIN_readInstruction)begin + _zz_68_ = execute_SPRPLUGIN_readData; + end + end + + assign execute_DECODER_stageables_45 = decode_to_execute_DECODER_stageables_45; + assign execute_RT_ADDR = decode_to_execute_RT_ADDR; + assign execute_DECODER_stageables_25 = decode_to_execute_DECODER_stageables_25; + assign memory_DECODER_stageables_45 = execute_to_memory_DECODER_stageables_45; + assign memory_RT_ADDR = execute_to_memory_RT_ADDR; + assign memory_DECODER_stageables_5 = execute_to_memory_DECODER_stageables_5; + assign decode_DECODER_stageables_50 = _zz_491_[0]; + assign decode_DECODER_stageables_47 = _zz_492_[0]; + assign decode_DECODER_stageables_10 = _zz_493_[0]; + assign writeBack_DECODER_stageables_45 = memory_to_writeBack_DECODER_stageables_45; + assign writeBack_RT_ADDR = memory_to_writeBack_RT_ADDR; + always @ (*) begin + decode_RS = decode_RegFilePlugin_rsData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr2Match)begin + decode_RS = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if((_zz_289_ && 1'b1))begin + decode_RS = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if((_zz_292_ && 1'b1))begin + decode_RS = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if((_zz_295_ && 1'b1))begin + decode_RS = _zz_68_; + end + end + end + end + + always @ (*) begin + decode_RB = decode_RegFilePlugin_rbData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr1Match)begin + decode_RB = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if(_zz_288_)begin + decode_RB = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if(_zz_291_)begin + decode_RB = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if(_zz_294_)begin + decode_RB = _zz_68_; + end + end + end + end + + always @ (*) begin + decode_RA = decode_RegFilePlugin_raData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr0Match)begin + decode_RA = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if(_zz_287_)begin + decode_RA = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if(_zz_290_)begin + decode_RA = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if(_zz_293_)begin + decode_RA = _zz_68_; + end + end + end + end + + assign decode_R2_ADDR = decode_INSTRUCTION[25 : 21]; + assign decode_R1_ADDR = _zz_239_; + assign decode_R0_ADDR = _zz_238_; + assign execute_DECODER_stageables_29 = decode_to_execute_DECODER_stageables_29; + assign execute_DECODER_stageables_43 = decode_to_execute_DECODER_stageables_43; + assign execute_DECODER_stageables_3 = decode_to_execute_DECODER_stageables_3; + assign memory_SRC_CR = execute_to_memory_SRC_CR; + assign memory_XER_SO = execute_to_memory_XER_SO; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_DECODER_stageables_37 = execute_to_memory_DECODER_stageables_37; + always @ (*) begin + _zz_69_ = memory_REGFILE_WRITE_DATA; + if(_zz_399_)begin + _zz_69_ = MULDIV1_result; + end + end + + assign memory_DECODER_stageables_15 = execute_to_memory_DECODER_stageables_15; + assign memory_DECODER_stageables_43 = execute_to_memory_DECODER_stageables_43; + assign writeBack_DECODER_stageables_31 = memory_to_writeBack_DECODER_stageables_31; + assign writeBack_DECODER_stageables_24 = memory_to_writeBack_DECODER_stageables_24; + assign writeBack_SRC_CR = memory_to_writeBack_SRC_CR; + assign writeBack_DECODER_stageables_55 = memory_to_writeBack_DECODER_stageables_55; + assign writeBack_XER_SO = memory_to_writeBack_XER_SO; + assign writeBack_DECODER_stageables_36 = memory_to_writeBack_DECODER_stageables_36; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_DECODER_stageables_35 = decode_to_execute_DECODER_stageables_35; + assign memory_DECODER_stageables_9 = execute_to_memory_DECODER_stageables_9; + assign execute_DECODER_stageables_9 = decode_to_execute_DECODER_stageables_9; + assign writeBack_DECODER_stageables_9 = memory_to_writeBack_DECODER_stageables_9; + assign execute_DECODER_stageables_48 = decode_to_execute_DECODER_stageables_48; + assign execute_SRC3 = _zz_268_; + assign execute_DECODER_stageables_1 = _zz_70_; + assign execute_DECODER_stageables_26 = _zz_71_; + assign _zz_72_ = execute_PC; + assign _zz_73_ = execute_RA; + assign execute_DECODER_stageables_38 = _zz_74_; + assign decode_DECODER_stageables_17 = _zz_494_[0]; + assign execute_DECODER_stageables_20 = _zz_77_; + assign execute_DECODER_stageables_51 = _zz_78_; + assign execute_DECODER_stageables_46 = decode_to_execute_DECODER_stageables_46; + assign execute_DECODER_stageables_34 = decode_to_execute_DECODER_stageables_34; + assign execute_DECODER_stageables_28 = decode_to_execute_DECODER_stageables_28; + assign execute_DECODER_stageables_57 = decode_to_execute_DECODER_stageables_57; + assign execute_DECODER_stageables_21 = decode_to_execute_DECODER_stageables_21; + assign execute_SRC_CR = (execute_DECODER_stageables_21 ? SRC2_cmp_cr : SRC2_add_cr); + assign execute_DECODER_stageables_11 = decode_to_execute_DECODER_stageables_11; + assign execute_DECODER_stageables_18 = decode_to_execute_DECODER_stageables_18; + assign execute_SRC_CAOV = {SRC2_ca,SRC2_ov}; + assign execute_DECODER_stageables_14 = decode_to_execute_DECODER_stageables_14; + assign execute_DECODER_stageables_6 = decode_to_execute_DECODER_stageables_6; + assign execute_R0_ADDR = decode_to_execute_R0_ADDR; + assign execute_DECODER_stageables_12 = _zz_80_; + assign execute_DECODER_stageables_8 = _zz_81_; + assign execute_DECODER_stageables_27 = decode_to_execute_DECODER_stageables_27; + assign execute_DECODER_stageables_2 = decode_to_execute_DECODER_stageables_2; + assign execute_DECODER_stageables_23 = decode_to_execute_DECODER_stageables_23; + assign execute_DECODER_stageables_0 = _zz_82_; + always @ (*) begin + _zz_83_ = _zz_83__30; + if(_zz_258_[31])begin + _zz_83_ = (_zz_83__30 + 6'h01); + end + end + + always @ (*) begin + _zz_83__30 = _zz_83__29; + if(_zz_258_[30])begin + _zz_83__30 = (_zz_83__29 + 6'h01); + end + end + + always @ (*) begin + _zz_83__29 = _zz_83__28; + if(_zz_258_[29])begin + _zz_83__29 = (_zz_83__28 + 6'h01); + end + end + + always @ (*) begin + _zz_83__28 = _zz_83__27; + if(_zz_258_[28])begin + _zz_83__28 = (_zz_83__27 + 6'h01); + end + end + + always @ (*) begin + _zz_83__27 = _zz_83__26; + if(_zz_258_[27])begin + _zz_83__27 = (_zz_83__26 + 6'h01); + end + end + + always @ (*) begin + _zz_83__26 = _zz_83__25; + if(_zz_258_[26])begin + _zz_83__26 = (_zz_83__25 + 6'h01); + end + end + + always @ (*) begin + _zz_83__25 = _zz_83__24; + if(_zz_258_[25])begin + _zz_83__25 = (_zz_83__24 + 6'h01); + end + end + + always @ (*) begin + _zz_83__24 = _zz_83__23; + if(_zz_258_[24])begin + _zz_83__24 = (_zz_83__23 + 6'h01); + end + end + + always @ (*) begin + _zz_83__23 = _zz_83__22; + if(_zz_258_[23])begin + _zz_83__23 = (_zz_83__22 + 6'h01); + end + end + + always @ (*) begin + _zz_83__22 = _zz_83__21; + if(_zz_258_[22])begin + _zz_83__22 = (_zz_83__21 + 6'h01); + end + end + + always @ (*) begin + _zz_83__21 = _zz_83__20; + if(_zz_258_[21])begin + _zz_83__21 = (_zz_83__20 + 6'h01); + end + end + + always @ (*) begin + _zz_83__20 = _zz_83__19; + if(_zz_258_[20])begin + _zz_83__20 = (_zz_83__19 + 6'h01); + end + end + + always @ (*) begin + _zz_83__19 = _zz_83__18; + if(_zz_258_[19])begin + _zz_83__19 = (_zz_83__18 + 6'h01); + end + end + + always @ (*) begin + _zz_83__18 = _zz_83__17; + if(_zz_258_[18])begin + _zz_83__18 = (_zz_83__17 + 6'h01); + end + end + + always @ (*) begin + _zz_83__17 = _zz_83__16; + if(_zz_258_[17])begin + _zz_83__17 = (_zz_83__16 + 6'h01); + end + end + + always @ (*) begin + _zz_83__16 = _zz_83__15; + if(_zz_258_[16])begin + _zz_83__16 = (_zz_83__15 + 6'h01); + end + end + + always @ (*) begin + _zz_83__15 = _zz_83__14; + if(_zz_258_[15])begin + _zz_83__15 = (_zz_83__14 + 6'h01); + end + end + + always @ (*) begin + _zz_83__14 = _zz_83__13; + if(_zz_258_[14])begin + _zz_83__14 = (_zz_83__13 + 6'h01); + end + end + + always @ (*) begin + _zz_83__13 = _zz_83__12; + if(_zz_258_[13])begin + _zz_83__13 = (_zz_83__12 + 6'h01); + end + end + + always @ (*) begin + _zz_83__12 = _zz_83__11; + if(_zz_258_[12])begin + _zz_83__12 = (_zz_83__11 + 6'h01); + end + end + + always @ (*) begin + _zz_83__11 = _zz_83__10; + if(_zz_258_[11])begin + _zz_83__11 = (_zz_83__10 + 6'h01); + end + end + + always @ (*) begin + _zz_83__10 = _zz_83__9; + if(_zz_258_[10])begin + _zz_83__10 = (_zz_83__9 + 6'h01); + end + end + + always @ (*) begin + _zz_83__9 = _zz_83__8; + if(_zz_258_[9])begin + _zz_83__9 = (_zz_83__8 + 6'h01); + end + end + + always @ (*) begin + _zz_83__8 = _zz_83__7; + if(_zz_258_[8])begin + _zz_83__8 = (_zz_83__7 + 6'h01); + end + end + + always @ (*) begin + _zz_83__7 = _zz_83__6; + if(_zz_258_[7])begin + _zz_83__7 = (_zz_83__6 + 6'h01); + end + end + + always @ (*) begin + _zz_83__6 = _zz_83__5; + if(_zz_258_[6])begin + _zz_83__6 = (_zz_83__5 + 6'h01); + end + end + + always @ (*) begin + _zz_83__5 = _zz_83__4; + if(_zz_258_[5])begin + _zz_83__5 = (_zz_83__4 + 6'h01); + end + end + + always @ (*) begin + _zz_83__4 = _zz_83__3; + if(_zz_258_[4])begin + _zz_83__4 = (_zz_83__3 + 6'h01); + end + end + + always @ (*) begin + _zz_83__3 = _zz_83__2; + if(_zz_258_[3])begin + _zz_83__3 = (_zz_83__2 + 6'h01); + end + end + + always @ (*) begin + _zz_83__2 = _zz_83__1; + if(_zz_258_[2])begin + _zz_83__2 = (_zz_83__1 + 6'h01); + end + end + + always @ (*) begin + _zz_83__1 = _zz_83__0; + if(_zz_258_[1])begin + _zz_83__1 = (_zz_83__0 + 6'h01); + end + end + + always @ (*) begin + _zz_83__0 = 6'h0; + if(_zz_258_[0])begin + _zz_83__0 = (6'h0 + 6'h01); + end + end + + always @ (*) begin + _zz_84_ = _zz_84__6; + if(_zz_257_[7])begin + _zz_84_ = (_zz_84__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__6 = _zz_84__5; + if(_zz_257_[6])begin + _zz_84__6 = (_zz_84__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__5 = _zz_84__4; + if(_zz_257_[5])begin + _zz_84__5 = (_zz_84__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__4 = _zz_84__3; + if(_zz_257_[4])begin + _zz_84__4 = (_zz_84__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__3 = _zz_84__2; + if(_zz_257_[3])begin + _zz_84__3 = (_zz_84__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__2 = _zz_84__1; + if(_zz_257_[2])begin + _zz_84__2 = (_zz_84__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__1 = _zz_84__0; + if(_zz_257_[1])begin + _zz_84__1 = (_zz_84__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__0 = (4'b0000); + if(_zz_257_[0])begin + _zz_84__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_85_ = _zz_85__6; + if(_zz_256_[7])begin + _zz_85_ = (_zz_85__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__6 = _zz_85__5; + if(_zz_256_[6])begin + _zz_85__6 = (_zz_85__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__5 = _zz_85__4; + if(_zz_256_[5])begin + _zz_85__5 = (_zz_85__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__4 = _zz_85__3; + if(_zz_256_[4])begin + _zz_85__4 = (_zz_85__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__3 = _zz_85__2; + if(_zz_256_[3])begin + _zz_85__3 = (_zz_85__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__2 = _zz_85__1; + if(_zz_256_[2])begin + _zz_85__2 = (_zz_85__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__1 = _zz_85__0; + if(_zz_256_[1])begin + _zz_85__1 = (_zz_85__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__0 = (4'b0000); + if(_zz_256_[0])begin + _zz_85__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_86_ = _zz_86__6; + if(_zz_255_[7])begin + _zz_86_ = (_zz_86__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__6 = _zz_86__5; + if(_zz_255_[6])begin + _zz_86__6 = (_zz_86__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__5 = _zz_86__4; + if(_zz_255_[5])begin + _zz_86__5 = (_zz_86__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__4 = _zz_86__3; + if(_zz_255_[4])begin + _zz_86__4 = (_zz_86__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__3 = _zz_86__2; + if(_zz_255_[3])begin + _zz_86__3 = (_zz_86__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__2 = _zz_86__1; + if(_zz_255_[2])begin + _zz_86__2 = (_zz_86__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__1 = _zz_86__0; + if(_zz_255_[1])begin + _zz_86__1 = (_zz_86__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__0 = (4'b0000); + if(_zz_255_[0])begin + _zz_86__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_87_ = _zz_87__6; + if(_zz_254_[7])begin + _zz_87_ = (_zz_87__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__6 = _zz_87__5; + if(_zz_254_[6])begin + _zz_87__6 = (_zz_87__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__5 = _zz_87__4; + if(_zz_254_[5])begin + _zz_87__5 = (_zz_87__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__4 = _zz_87__3; + if(_zz_254_[4])begin + _zz_87__4 = (_zz_87__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__3 = _zz_87__2; + if(_zz_254_[3])begin + _zz_87__3 = (_zz_87__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__2 = _zz_87__1; + if(_zz_254_[2])begin + _zz_87__2 = (_zz_87__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__1 = _zz_87__0; + if(_zz_254_[1])begin + _zz_87__1 = (_zz_87__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__0 = (4'b0000); + if(_zz_254_[0])begin + _zz_87__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_88_ = _zz_89_; + _zz_88_ = (ALU2_amount[4] ? {_zz_89_[15 : 0],_zz_89_[31 : 16]} : _zz_89_); + end + + always @ (*) begin + _zz_89_ = _zz_90_; + _zz_89_ = (ALU2_amount[3] ? {_zz_90_[23 : 0],_zz_90_[31 : 24]} : _zz_90_); + end + + always @ (*) begin + _zz_90_ = _zz_91_; + _zz_90_ = (ALU2_amount[2] ? {_zz_91_[27 : 0],_zz_91_[31 : 28]} : _zz_91_); + end + + always @ (*) begin + _zz_91_ = _zz_92_; + _zz_91_ = (ALU2_amount[1] ? {_zz_92_[29 : 0],_zz_92_[31 : 30]} : _zz_92_); + end + + always @ (*) begin + _zz_92_ = _zz_251_; + _zz_92_ = (ALU2_amount[0] ? {_zz_251_[30 : 0],_zz_251_[31 : 31]} : _zz_251_); + end + + always @ (*) begin + _zz_93_ = _zz_94_; + _zz_93_ = (ALU2_amount[4] ? {_zz_94_[15 : 0],_zz_94_[31 : 16]} : _zz_94_); + end + + always @ (*) begin + _zz_94_ = _zz_95_; + _zz_94_ = (ALU2_amount[3] ? {_zz_95_[23 : 0],_zz_95_[31 : 24]} : _zz_95_); + end + + always @ (*) begin + _zz_95_ = _zz_96_; + _zz_95_ = (ALU2_amount[2] ? {_zz_96_[27 : 0],_zz_96_[31 : 28]} : _zz_96_); + end + + always @ (*) begin + _zz_96_ = _zz_97_; + _zz_96_ = (ALU2_amount[1] ? {_zz_97_[29 : 0],_zz_97_[31 : 30]} : _zz_97_); + end + + always @ (*) begin + _zz_97_ = _zz_250_; + _zz_97_ = (ALU2_amount[0] ? {_zz_250_[30 : 0],_zz_250_[31 : 31]} : _zz_250_); + end + + assign execute_DECODER_stageables_16 = _zz_98_; + assign execute_DECODER_stageables_44 = _zz_99_; + assign execute_SRC2 = _zz_267_; + assign execute_SRC1 = _zz_264_; + assign execute_DECODER_stageables_19 = _zz_100_; + assign execute_DECODER_stageables_54 = decode_to_execute_DECODER_stageables_54; + assign execute_SPR_ID = _zz_79_; + assign writeBack_SRC1 = memory_to_writeBack_SRC1; + assign writeBack_DECODER_stageables_32 = memory_to_writeBack_DECODER_stageables_32; + assign writeBack_SPR_ID = memory_to_writeBack_SPR_ID; + assign writeBack_XER_WRITE_validOV = memory_to_writeBack_XER_WRITE_validOV; + assign writeBack_XER_WRITE_validCA = memory_to_writeBack_XER_WRITE_validCA; + assign writeBack_XER_WRITE_imm = memory_to_writeBack_XER_WRITE_imm; + assign writeBack_BRANCH_LINK = memory_to_writeBack_BRANCH_LINK; + assign writeBack_BRANCH_DEC = memory_to_writeBack_BRANCH_DEC; + assign writeBack_CR_WRITE_op = _zz_101_; + assign writeBack_CR_WRITE_ba = memory_to_writeBack_CR_WRITE_ba; + assign writeBack_CR_WRITE_bb = memory_to_writeBack_CR_WRITE_bb; + assign writeBack_CR_WRITE_bt = memory_to_writeBack_CR_WRITE_bt; + assign writeBack_CR_WRITE_imm = memory_to_writeBack_CR_WRITE_imm; + assign writeBack_CR_WRITE_fxm = memory_to_writeBack_CR_WRITE_fxm; + assign _zz_102_ = writeBack_DECODER_stageables_45; + always @ (*) begin + _zz_103_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_103_ = 1'b1; + end + end + + assign decode_DECODER_stageables_12 = _zz_104_; + assign decode_DECODER_stageables_26 = _zz_105_; + assign decode_DECODER_stageables_38 = _zz_106_; + assign decode_INSTRUCTION_ANTICIPATED = _zz_128_; + assign decode = _zz_495_[0]; + assign decode_LEGAL_INSTRUCTION = ({_zz_221_,{((decode_INSTRUCTION & 32'h6c000000) == 32'h0c000000),{_zz_220_,{((decode_INSTRUCTION & 32'hb8000000) == 32'h28000000),{_zz_170_,{_zz_219_,{_zz_217_,{_zz_663_,_zz_664_}}}}}}}} != 101'h0); + always @ (*) begin + _zz_121_ = writeBack_REGFILE_WRITE_DATA; + if(((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_WR)))begin + _zz_121_ = writeBack_DBusCachedPlugin_rspFormated; + end + if(_zz_400_)begin + _zz_121_ = MUL3_result32; + end + end + + assign writeBack_SIGN_EXTEND = memory_to_writeBack_DECODER_stageables_53; + assign writeBack_DATA_SIZE = _zz_122_; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_DECODER_stageables_56; + assign writeBack_MSR_ENDIAN = _zz_123_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_DECODER_stageables_52; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_DECODER_stageables_52; + assign execute_STORE_UPDATE = decode_to_execute_DECODER_stageables_42; + assign execute_MEMORY_MANAGMENT = decode_to_execute_DECODER_stageables_22; + assign execute_RS = decode_to_execute_RS; + assign execute_MEMORY_WR = decode_to_execute_DECODER_stageables_56; + assign execute_SRC_ADD = SRC2_adder[31 : 0]; + assign execute_MEMORY_ENABLE = decode_to_execute_DECODER_stageables_52; + assign execute_DATA_SIZE = _zz_125_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MSR_ENDIAN = _zz_126_; + assign decode_MEMORY_ENABLE = _zz_496_[0]; + assign decode_FLUSH_ALL = _zz_497_[0]; + always @ (*) begin + _zz_127_ = _zz_127__3; + if(_zz_401_)begin + _zz_127_ = 1'b1; + end + end + + always @ (*) begin + _zz_127__3 = _zz_127__2; + if(_zz_402_)begin + _zz_127__3 = 1'b1; + end + end + + always @ (*) begin + _zz_127__2 = _zz_127__1; + if(_zz_403_)begin + if(_zz_404_)begin + _zz_127__2 = 1'b1; + end + end + end + + always @ (*) begin + _zz_127__1 = _zz_127__0; + if(_zz_405_)begin + _zz_127__1 = 1'b1; + end + end + + always @ (*) begin + _zz_127__0 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_406_)begin + _zz_127__0 = 1'b1; + end + end + + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign decode_MSR_ENDIAN = _zz_129_; + assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard; + assign memory_PREDICTION_CONTEXT_hit = execute_to_memory_PREDICTION_CONTEXT_hit; + assign memory_PREDICTION_CONTEXT_line_source = execute_to_memory_PREDICTION_CONTEXT_line_source; + assign memory_PREDICTION_CONTEXT_line_branchWish = execute_to_memory_PREDICTION_CONTEXT_line_branchWish; + assign memory_PREDICTION_CONTEXT_line_target = execute_to_memory_PREDICTION_CONTEXT_line_target; + always @ (*) begin + _zz_130_ = 1'b0; + if(IBusCachedPlugin_predictor_historyWriteDelayPatched_valid)begin + _zz_130_ = 1'b1; + end + end + + always @ (*) begin + _zz_131_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_131_ = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(((((execute_arbitration_isValid && execute_DECODER_stageables_9) || (memory_arbitration_isValid && memory_DECODER_stageables_9)) || (writeBack_arbitration_isValid && writeBack_DECODER_stageables_9)) || _zz_269_))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && ((_zz_283_ || _zz_284_) || _zz_285_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(SPRPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_407_)begin + decode_arbitration_removeIt = _zz_341_; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if((_zz_387_ && (! dataCache_1__io_cpu_flush_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_SPRPLUGIN_readInstruction || execute_SPRPLUGIN_writeInstruction))begin + if(execute_SPRPLUGIN_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((_zz_296_ || _zz_312_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_298_ || _zz_314_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_299_ || _zz_315_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_297_ || _zz_313_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_300_ || _zz_316_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_301_ || _zz_317_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_302_ || _zz_318_))begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(SPRPlugin_selfException_valid)begin + execute_arbitration_removeIt = _zz_342_; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + assign execute_arbitration_flushNext = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_399_)begin + if(((! MULDIV_frontendOk) || (! MULDIV1_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = _zz_343_; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1__io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = _zz_344_; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_408_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_409_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_410_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_411_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_412_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_413_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_414_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack,{SPRPlugin_exceptionPortCtrl_exceptionValids_memory,{SPRPlugin_exceptionPortCtrl_exceptionValids_execute,SPRPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_408_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_409_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_410_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_411_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_412_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_413_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_414_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = (5'bxxxxx); + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_ISI; + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_ISI_PROT; + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_MC; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_imm = 7'h0; + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_badAddr = 32'h0; + IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],(2'b00)}; + end + + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_codePPC = (5'bxxxxx); + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_MC; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI_PROT; + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI_PROT; + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_ALG; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_imm = 7'h0; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_badAddr = 32'h0; + DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_PC; + end + + always @ (*) begin + decodeExceptionPort_payload_codePPC = (5'bxxxxx); + decodeExceptionPort_payload_codePPC = (5'bxxxxx); + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_ILL; + end + if(_zz_420_)begin + decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_PRV; + end + end + end + + assign decodeExceptionPort_payload_imm = 7'h0; + always @ (*) begin + decodeExceptionPort_payload_badAddr = 32'h0; + decodeExceptionPort_payload_badAddr = 32'h0; + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_badAddr = decode_PC; + end + if(_zz_420_)begin + decodeExceptionPort_payload_badAddr = decode_PC; + end + end + end + + assign BranchPlugin_branchExceptionPort_payload_codePPC = (5'bxxxxx); + assign BranchPlugin_branchExceptionPort_payload_imm = 7'h0; + always @ (*) begin + BranchPlugin_branchExceptionPort_payload_badAddr = 32'h0; + BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + end + + always @ (*) begin + SPRPlugin_jumpInterface_valid = 1'b0; + if(_zz_408_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_409_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_410_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_411_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_412_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_413_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_414_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + SPRPlugin_jumpInterface_payload = 32'h0; + if(_zz_408_)begin + SPRPlugin_jumpInterface_payload = _zz_345_; + end + if(_zz_409_)begin + SPRPlugin_jumpInterface_payload = (writeBack_PC + 32'h00000004); + end + if(_zz_410_)begin + SPRPlugin_jumpInterface_payload = 32'h00000c00; + end + if(_zz_411_)begin + SPRPlugin_jumpInterface_payload = 32'h00000c00; + end + if(_zz_413_)begin + SPRPlugin_jumpInterface_payload = SPRPlugin_srr0; + end + end + + assign SPRPlugin_forceMachineWire = 1'b0; + always @ (*) begin + SPRPlugin_selfException_payload_codePPC = (5'bxxxxx); + SPRPlugin_selfException_payload_codePPC = `ExcpEnum_defaultEncoding_NONE; + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_PRV; + end + end + + assign _zz_1588_ = zz_SPRPlugin_selfException_payload_imm(1'b0); + always @ (*) SPRPlugin_selfException_payload_imm = _zz_1588_; + always @ (*) begin + SPRPlugin_selfException_payload_badAddr = 32'h0; + SPRPlugin_selfException_payload_badAddr = execute_PC; + end + + assign SPRPlugin_allowInterrupts = 1'b1; + assign SPRPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)); + assign IBusCachedPlugin_jump_pcLoad_valid = ({SPRPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_132_ = {BranchPlugin_jumpInterface_valid,{SPRPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_133_ = (_zz_132_ & (~ _zz_498_)); + assign _zz_134_ = _zz_133_[1]; + assign _zz_135_ = _zz_133_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_393_; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_predictionPcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + assign IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_500_); + if(IBusCachedPlugin_fetchPc_predictionPcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_predictionPcLoad_payload; + end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_136_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_136_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_136_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_137_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_137_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_137_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((_zz_127_ || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_138_ = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_138_); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_138_); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_139_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_139_ = _zz_140_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_139_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = _zz_141_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_142_)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_142_ = _zz_143_; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_142_; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_144_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_valid = IBusCachedPlugin_predictor_historyWrite_valid; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address = (IBusCachedPlugin_predictor_historyWrite_payload_address - 10'h001); + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source = IBusCachedPlugin_predictor_historyWrite_payload_data_source; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish = IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target = IBusCachedPlugin_predictor_historyWrite_payload_data_target; + assign _zz_145_ = (IBusCachedPlugin_iBusRsp_stages_0_input_payload >>> 2); + assign _zz_146_ = _zz_389_; + assign IBusCachedPlugin_predictor_buffer_line_source = _zz_146_[19 : 0]; + assign IBusCachedPlugin_predictor_buffer_line_branchWish = _zz_146_[21 : 20]; + assign IBusCachedPlugin_predictor_buffer_line_target = _zz_146_[53 : 22]; + assign IBusCachedPlugin_predictor_buffer_hazard = (IBusCachedPlugin_predictor_writeLast_valid && (IBusCachedPlugin_predictor_writeLast_payload_address == _zz_503_)); + assign IBusCachedPlugin_predictor_hazard = (IBusCachedPlugin_predictor_buffer_hazard_regNextWhen || IBusCachedPlugin_predictor_buffer_pcCorrected); + assign IBusCachedPlugin_predictor_hit = (IBusCachedPlugin_predictor_line_source == _zz_504_); + assign IBusCachedPlugin_fetchPc_predictionPcLoad_valid = (((IBusCachedPlugin_predictor_line_branchWish[1] && IBusCachedPlugin_predictor_hit) && (! IBusCachedPlugin_predictor_hazard)) && IBusCachedPlugin_iBusRsp_stages_1_input_valid); + assign IBusCachedPlugin_fetchPc_predictionPcLoad_payload = IBusCachedPlugin_predictor_line_target; + assign IBusCachedPlugin_predictor_fetchContext_hazard = IBusCachedPlugin_predictor_hazard; + assign IBusCachedPlugin_predictor_fetchContext_hit = IBusCachedPlugin_predictor_hit; + assign IBusCachedPlugin_predictor_fetchContext_line_source = IBusCachedPlugin_predictor_line_source; + assign IBusCachedPlugin_predictor_fetchContext_line_branchWish = IBusCachedPlugin_predictor_line_branchWish; + assign IBusCachedPlugin_predictor_fetchContext_line_target = IBusCachedPlugin_predictor_line_target; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_hazard = IBusCachedPlugin_predictor_iBusRspContext_hazard; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_hit = IBusCachedPlugin_predictor_iBusRspContext_hit; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_source = IBusCachedPlugin_predictor_iBusRspContext_line_source; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish = IBusCachedPlugin_predictor_iBusRspContext_line_branchWish; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_target = IBusCachedPlugin_predictor_iBusRspContext_line_target; + assign IBusCachedPlugin_predictor_injectorContext_hazard = IBusCachedPlugin_predictor_iBusRspContextOutput_hazard; + assign IBusCachedPlugin_predictor_injectorContext_hit = IBusCachedPlugin_predictor_iBusRspContextOutput_hit; + assign IBusCachedPlugin_predictor_injectorContext_line_source = IBusCachedPlugin_predictor_iBusRspContextOutput_line_source; + assign IBusCachedPlugin_predictor_injectorContext_line_branchWish = IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish; + assign IBusCachedPlugin_predictor_injectorContext_line_target = IBusCachedPlugin_predictor_iBusRspContextOutput_line_target; + assign IBusCachedPlugin_fetchPrediction_cmd_hadBranch = ((memory_PREDICTION_CONTEXT_hit && (! memory_PREDICTION_CONTEXT_hazard)) && memory_PREDICTION_CONTEXT_line_branchWish[1]); + assign IBusCachedPlugin_fetchPrediction_cmd_targetPc = memory_PREDICTION_CONTEXT_line_target; + always @ (*) begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b0; + if(IBusCachedPlugin_fetchPrediction_rsp_wasRight)begin + IBusCachedPlugin_predictor_historyWrite_valid = memory_PREDICTION_CONTEXT_hit; + end else begin + if(memory_PREDICTION_CONTEXT_hit)begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b1; + end else begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b1; + end + end + if((memory_PREDICTION_CONTEXT_hazard || (! memory_arbitration_isFiring)))begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b0; + end + end + + assign IBusCachedPlugin_predictor_historyWrite_payload_address = IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord[11 : 2]; + assign IBusCachedPlugin_predictor_historyWrite_payload_data_source = (IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord >>> 12); + assign IBusCachedPlugin_predictor_historyWrite_payload_data_target = IBusCachedPlugin_fetchPrediction_rsp_finalPc; + always @ (*) begin + if(IBusCachedPlugin_fetchPrediction_rsp_wasRight)begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (_zz_505_ - _zz_509_); + end else begin + if(memory_PREDICTION_CONTEXT_hit)begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (_zz_510_ + _zz_514_); + end else begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (2'b10); + end + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_368_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_s1_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + assign _zz_369_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_370_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_371_ = (! SPRPlugin_msr_ir); + assign IBusCachedPlugin_s2_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + assign _zz_372_ = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_373_ = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_374_ = (SPRPlugin_privilege == (2'b00)); + always @ (*) begin + if(IBusCachedPlugin_s2_bigEndian)begin + _zz_128_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + end else begin + _zz_128_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : {{{IBusCachedPlugin_cache_io_cpu_fetch_data[7 : 0],IBusCachedPlugin_cache_io_cpu_fetch_data[15 : 8]},IBusCachedPlugin_cache_io_cpu_fetch_data[23 : 16]},IBusCachedPlugin_cache_io_cpu_fetch_data[31 : 24]}); + end + end + + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_406_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_401_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_rsp_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + _zz_375_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_401_)begin + _zz_375_ = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1011); + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + always @ (*) begin + if(IBusCachedPlugin_rsp_bigEndian)begin + IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + end else begin + IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = {{{IBusCachedPlugin_cache_io_cpu_decode_data[7 : 0],IBusCachedPlugin_cache_io_cpu_decode_data[15 : 8]},IBusCachedPlugin_cache_io_cpu_decode_data[23 : 16]},IBusCachedPlugin_cache_io_cpu_decode_data[31 : 24]}; + end + end + + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_spr_valid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid; + assign IBusCachedPlugin_mmuBus_spr_payload_id = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id; + assign IBusCachedPlugin_mmuBus_spr_payload_data = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_367_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_388_ = ((1'b1 && (! dataCache_1__io_mem_cmd_m2sPipe_valid)) || dataCache_1__io_mem_cmd_m2sPipe_ready); + assign dataCache_1__io_mem_cmd_m2sPipe_valid = dataCache_1__io_mem_cmd_m2sPipe_rValid; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_wr = dataCache_1__io_mem_cmd_m2sPipe_rData_wr; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_address = dataCache_1__io_mem_cmd_m2sPipe_rData_address; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_data = dataCache_1__io_mem_cmd_m2sPipe_rData_data; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_mask = dataCache_1__io_mem_cmd_m2sPipe_rData_mask; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_length = dataCache_1__io_mem_cmd_m2sPipe_rData_length; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_last = dataCache_1__io_mem_cmd_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1__io_mem_cmd_m2sPipe_valid; + assign dataCache_1__io_mem_cmd_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_m2sPipe_payload_wr; + assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_bigEndian = (execute_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + case(execute_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + execute_DBusCachedPlugin_size = (2'b00); + end + `DataSizeEnum_defaultEncoding_H : begin + execute_DBusCachedPlugin_size = (2'b01); + end + `DataSizeEnum_defaultEncoding_W : begin + execute_DBusCachedPlugin_size = (2'b10); + end + default : begin + execute_DBusCachedPlugin_size = (2'b00); + end + endcase + end + + assign _zz_377_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_378_ = execute_SRC_ADD[31 : 0]; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_149_ = {{{execute_RS[7 : 0],execute_RS[7 : 0]},execute_RS[7 : 0]},execute_RS[7 : 0]}; + end + 2'b01 : begin + _zz_149_ = {execute_RS[15 : 0],execute_RS[15 : 0]}; + end + default : begin + _zz_149_ = execute_RS; + end + endcase + end + + always @ (*) begin + if(execute_DBusCachedPlugin_bigEndian)begin + _zz_379_ = _zz_149_; + end else begin + _zz_379_ = _zz_152_; + end + end + + assign _zz_150_ = execute_RS[15 : 0]; + assign _zz_151_ = execute_RS[15 : 0]; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_152_ = {{{execute_RS[7 : 0],execute_RS[7 : 0]},execute_RS[7 : 0]},execute_RS[7 : 0]}; + end + 2'b01 : begin + _zz_152_ = {{_zz_150_[7 : 0],_zz_150_[15 : 8]},{_zz_151_[7 : 0],_zz_151_[15 : 8]}}; + end + default : begin + _zz_152_ = {{{execute_RS[7 : 0],execute_RS[15 : 8]},execute_RS[23 : 16]},execute_RS[31 : 24]}; + end + endcase + end + + assign _zz_387_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + always @ (*) begin + if(execute_STORE_UPDATE)begin + _zz_124_ = execute_SRC_ADD; + end + if(execute_DECODER_stageables_54)begin + if(ALU2_sprReadValid)begin + _zz_124_ = ALU2_XER; + end else begin + if(execute_DECODER_stageables_23)begin + _zz_124_ = _zz_259_; + end else begin + if(execute_DECODER_stageables_2)begin + if(_zz_260_)begin + _zz_124_ = 32'hffffffff; + end else begin + if(_zz_261_)begin + _zz_124_ = 32'h00000001; + end else begin + _zz_124_ = 32'h0; + end + end + end else begin + if(execute_DECODER_stageables_27)begin + _zz_124_ = (_zz_553_[_zz_554_] ? execute_SRC1 : execute_SRC2); + end else begin + _zz_124_ = sprReadBU_payload_data; + end + end + end + end + end else begin + _zz_124_ = _zz_262_; + end + end + + assign _zz_380_ = ((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! DBusCachedPlugin_exceptionBus_valid)) && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign _zz_381_ = memory_REGFILE_WRITE_DATA; + assign _zz_383_ = (! SPRPlugin_msr_dr); + assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + always @ (*) begin + _zz_382_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin + _zz_382_ = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_spr_valid = dataCache_1__io_cpu_memory_mmuBus_spr_valid; + assign DBusCachedPlugin_mmuBus_spr_payload_id = dataCache_1__io_cpu_memory_mmuBus_spr_payload_id; + assign DBusCachedPlugin_mmuBus_spr_payload_data = dataCache_1__io_cpu_memory_mmuBus_spr_payload_data; + assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; + assign _zz_384_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_385_ = (SPRPlugin_privilege == (2'b00)); + assign _zz_386_ = writeBack_REGFILE_WRITE_DATA; + assign writeBack_DBusCachedPlugin_bigEndian = (writeBack_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_415_)begin + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_515_}; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_payload_code = (4'b0000); + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_payload_code = (4'b0000); + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_516_}; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + if(writeBack_DBusCachedPlugin_bigEndian)begin + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b00 : begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + `DataSizeEnum_defaultEncoding_H : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + default : begin + end + endcase + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[23 : 16]; + end + 2'b10 : begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + default : begin + end + endcase + end + default : begin + end + endcase + end else begin + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspHW = 16'h0; + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + end + `DataSizeEnum_defaultEncoding_H : begin + if((writeBack_MEMORY_ADDRESS_LOW == (2'b00)))begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspHW = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end else begin + writeBack_DBusCachedPlugin_rspHW = {_zz_153_[7 : 0],_zz_153_[15 : 8]}; + end + end else begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspHW = writeBack_DBusCachedPlugin_rspShifted[31 : 16]; + end else begin + writeBack_DBusCachedPlugin_rspHW = {_zz_154_[7 : 0],_zz_154_[15 : 8]}; + end + end + end + default : begin + end + endcase + end + + always @ (*) begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspFormated = {24'h0,writeBack_DBusCachedPlugin_rspShifted[7 : 0]}; + end + `DataSizeEnum_defaultEncoding_H : begin + if(writeBack_SIGN_EXTEND)begin + writeBack_DBusCachedPlugin_rspFormated = {_zz_156_,writeBack_DBusCachedPlugin_rspHW}; + end else begin + writeBack_DBusCachedPlugin_rspFormated = {16'h0,writeBack_DBusCachedPlugin_rspHW}; + end + end + default : begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end else begin + writeBack_DBusCachedPlugin_rspFormated = {{{writeBack_DBusCachedPlugin_rspShifted[7 : 0],writeBack_DBusCachedPlugin_rspShifted[15 : 8]},writeBack_DBusCachedPlugin_rspShifted[23 : 16]},writeBack_DBusCachedPlugin_rspShifted[31 : 24]}; + end + end + endcase + end + + assign _zz_153_ = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + assign _zz_154_ = writeBack_DBusCachedPlugin_rspShifted[31 : 16]; + assign _zz_155_ = writeBack_DBusCachedPlugin_rspHW[15]; + always @ (*) begin + _zz_156_[15] = _zz_155_; + _zz_156_[14] = _zz_155_; + _zz_156_[13] = _zz_155_; + _zz_156_[12] = _zz_155_; + _zz_156_[11] = _zz_155_; + _zz_156_[10] = _zz_155_; + _zz_156_[9] = _zz_155_; + _zz_156_[8] = _zz_155_; + _zz_156_[7] = _zz_155_; + _zz_156_[6] = _zz_155_; + _zz_156_[5] = _zz_155_; + _zz_156_[4] = _zz_155_; + _zz_156_[3] = _zz_155_; + _zz_156_[2] = _zz_155_; + _zz_156_[1] = _zz_155_; + _zz_156_[0] = _zz_155_; + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_158_ = ((decode_INSTRUCTION & 32'h00000300) == 32'h00000100); + assign _zz_159_ = ((decode_INSTRUCTION & 32'h50000000) == 32'h10000000); + assign _zz_160_ = ((decode_INSTRUCTION & 32'h80000000) == 32'h80000000); + assign _zz_161_ = ((decode_INSTRUCTION & 32'h78000138) == 32'h78000100); + assign _zz_162_ = ((decode_INSTRUCTION & 32'h00000500) == 32'h00000400); + assign _zz_163_ = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); + assign _zz_164_ = ((decode_INSTRUCTION & 32'he0000000) == 32'h20000000); + assign _zz_165_ = ((decode_INSTRUCTION & 32'h90000000) == 32'h90000000); + assign _zz_166_ = ((decode_INSTRUCTION & 32'h780001b8) == 32'h78000020); + assign _zz_167_ = ((decode_INSTRUCTION & 32'h78000038) == 32'h78000018); + assign _zz_168_ = ((decode_INSTRUCTION & 32'h28000000) == 32'h0); + assign _zz_169_ = ((decode_INSTRUCTION & 32'h70000000) == 32'h60000000); + assign _zz_170_ = ((decode_INSTRUCTION & 32'hd4000000) == 32'h84000000); + assign _zz_171_ = ((decode_INSTRUCTION & 32'h78000416) == 32'h78000004); + assign _zz_172_ = ((decode_INSTRUCTION & 32'hf8040000) == 32'h38040000); + assign _zz_173_ = ((decode_INSTRUCTION & 32'hf8080000) == 32'h38080000); + assign _zz_174_ = ((decode_INSTRUCTION & 32'hf8010000) == 32'h38010000); + assign _zz_175_ = ((decode_INSTRUCTION & 32'hf8020000) == 32'h38020000); + assign _zz_176_ = ((decode_INSTRUCTION & 32'hec000000) == 32'h20000000); + assign _zz_177_ = ((decode_INSTRUCTION & 32'hd4020000) == 32'h80020000); + assign _zz_178_ = ((decode_INSTRUCTION & 32'hd4080000) == 32'h80080000); + assign _zz_179_ = ((decode_INSTRUCTION & 32'hd4040000) == 32'h80040000); + assign _zz_180_ = ((decode_INSTRUCTION & 32'hd4010000) == 32'h80010000); + assign _zz_181_ = ((decode_INSTRUCTION & 32'hcc080000) == 32'h80080000); + assign _zz_182_ = ((decode_INSTRUCTION & 32'he4020000) == 32'h80020000); + assign _zz_183_ = ((decode_INSTRUCTION & 32'hcc020000) == 32'h80020000); + assign _zz_184_ = ((decode_INSTRUCTION & 32'he4040000) == 32'h80040000); + assign _zz_185_ = ((decode_INSTRUCTION & 32'hcc010000) == 32'h80010000); + assign _zz_186_ = ((decode_INSTRUCTION & 32'he4080000) == 32'h80080000); + assign _zz_187_ = ((decode_INSTRUCTION & 32'hf8000000) == 32'h28000000); + assign _zz_188_ = ((decode_INSTRUCTION & 32'hcc040000) == 32'h80040000); + assign _zz_189_ = ((decode_INSTRUCTION & 32'he4010000) == 32'h80010000); + assign _zz_190_ = ((decode_INSTRUCTION & 32'h78000382) == 32'h78000180); + assign _zz_191_ = ((decode_INSTRUCTION & 32'h70000000) == 32'h50000000); + assign _zz_192_ = ((decode_INSTRUCTION & 32'h48000000) == 32'h40000000); + assign _zz_193_ = ((decode_INSTRUCTION & 32'h78000698) == 32'h78000080); + assign _zz_194_ = ((decode_INSTRUCTION & 32'h78000034) == 32'h78000010); + assign _zz_195_ = ((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f); + assign _zz_196_ = ((decode_INSTRUCTION & 32'h7800022a) == 32'h78000002); + assign _zz_197_ = ((decode_INSTRUCTION & 32'h9c000000) == 32'h08000000); + assign _zz_198_ = ((decode_INSTRUCTION & 32'hf4000000) == 32'h54000000); + assign _zz_199_ = ((decode_INSTRUCTION & 32'h7c0004a0) == 32'h4c0000a0); + assign _zz_200_ = ((decode_INSTRUCTION & 32'h7c000460) == 32'h4c000060); + assign _zz_201_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h1c000000); + assign _zz_202_ = ((decode_INSTRUCTION & 32'hd40f0000) == 32'h80000000); + assign _zz_203_ = ((decode_INSTRUCTION & 32'h78000498) == 32'h78000080); + assign _zz_204_ = ((decode_INSTRUCTION & 32'h7800002c) == 32'h78000008); + assign _zz_205_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h44000000); + assign _zz_206_ = ((decode_INSTRUCTION & 32'h90100000) == 32'h80100000); + assign _zz_207_ = ((decode_INSTRUCTION & 32'h7800030a) == 32'h78000102); + assign _zz_208_ = ((decode_INSTRUCTION & 32'h78000328) == 32'h78000300); + assign _zz_209_ = ((decode_INSTRUCTION & 32'h381f0038) == 32'h38000028); + assign _zz_210_ = ((decode_INSTRUCTION & 32'h381f0038) == 32'h38000018); + assign _zz_211_ = ((decode_INSTRUCTION & 32'h781f0000) == 32'h38000000); + assign _zz_212_ = ((decode_INSTRUCTION & 32'h801f0000) == 32'h80000000); + assign _zz_213_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h0c000000); + assign _zz_214_ = ((decode_INSTRUCTION & 32'hdc000000) == 32'h94000000); + assign _zz_215_ = ((decode_INSTRUCTION & 32'hf4000000) == 32'h94000000); + assign _zz_216_ = ((decode_INSTRUCTION & 32'hbc000000) == 32'h1c000000); + assign _zz_217_ = ((decode_INSTRUCTION & 32'hb8000000) == 32'h30000000); + assign _zz_218_ = ((decode_INSTRUCTION & 32'he4000000) == 32'h84000000); + assign _zz_219_ = ((decode_INSTRUCTION & 32'hd8000000) == 32'h50000000); + assign _zz_220_ = ((decode_INSTRUCTION & 32'hf0000000) == 32'h60000000); + assign _zz_221_ = ((decode_INSTRUCTION & 32'hcc000000) == 32'h84000000); + assign _zz_222_ = ((decode_INSTRUCTION & 32'hfc000002) == 32'h44000002); + assign _zz_157_ = {({(_zz_742_ == _zz_743_),{_zz_744_,{_zz_745_,_zz_746_}}} != (4'b0000)),{({_zz_159_,_zz_747_} != (2'b00)),{(_zz_748_ != (1'b0)),{(_zz_749_ != _zz_750_),{_zz_751_,{_zz_752_,_zz_753_}}}}}}; + assign _zz_223_ = _zz_157_[2 : 0]; + assign _zz_120_ = _zz_223_; + assign _zz_224_ = _zz_157_[4 : 3]; + assign _zz_119_ = _zz_224_; + assign _zz_225_ = _zz_157_[11 : 10]; + assign _zz_118_ = _zz_225_; + assign _zz_226_ = _zz_157_[13 : 12]; + assign _zz_117_ = _zz_226_; + assign _zz_227_ = _zz_157_[17 : 17]; + assign _zz_116_ = _zz_227_; + assign _zz_228_ = _zz_157_[20 : 18]; + assign _zz_115_ = _zz_228_; + assign _zz_229_ = _zz_157_[25 : 23]; + assign _zz_114_ = _zz_229_; + assign _zz_230_ = _zz_157_[31 : 28]; + assign _zz_113_ = _zz_230_; + assign _zz_231_ = _zz_157_[34 : 32]; + assign _zz_112_ = _zz_231_; + assign _zz_232_ = _zz_157_[42 : 40]; + assign _zz_111_ = _zz_232_; + assign _zz_233_ = _zz_157_[56 : 54]; + assign _zz_110_ = _zz_233_; + assign _zz_234_ = _zz_157_[62 : 62]; + assign _zz_109_ = _zz_234_; + assign _zz_235_ = _zz_157_[70 : 67]; + assign _zz_108_ = _zz_235_; + assign _zz_236_ = _zz_157_[73 : 72]; + assign _zz_107_ = _zz_236_; + always @ (*) begin + decodeExceptionPort_valid = 1'b0; + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_valid = 1'b1; + end + if(_zz_420_)begin + decodeExceptionPort_valid = 1'b1; + end + end + end + + always @ (*) begin + decodeExceptionPort_payload_code = (4'bxxxx); + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_code = (4'b0010); + end + if(_zz_420_)begin + decodeExceptionPort_payload_code = (4'b0010); + end + end + end + + assign _zz_376_ = _zz_517_[9 : 0]; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[20 : 16]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[15 : 11]; + assign decode_RegFilePlugin_raData_pre = _zz_390_; + assign decode_RegFilePlugin_rbData_pre = _zz_391_; + assign decode_RegFilePlugin_regFileReadAddress3 = decode_INSTRUCTION_ANTICIPATED[25 : 21]; + assign decode_RegFilePlugin_rsData = _zz_392_; + always @ (*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RS : begin + decode_RegFilePlugin_raData = decode_RegFilePlugin_rsData; + end + default : begin + decode_RegFilePlugin_raData = decode_RegFilePlugin_raData_pre; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RA : begin + decode_RegFilePlugin_rbData = decode_RegFilePlugin_raData; + end + default : begin + decode_RegFilePlugin_rbData = decode_RegFilePlugin_rbData_pre; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_238_ = decode_INSTRUCTION[25 : 21]; + end + default : begin + _zz_238_ = decode_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RA : begin + _zz_239_ = decode_INSTRUCTION[20 : 16]; + end + default : begin + _zz_239_ = decode_INSTRUCTION[15 : 11]; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : begin + _zz_240_ = decode_INSTRUCTION[25 : 21]; + end + default : begin + _zz_240_ = decode_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_valid = (_zz_102_ && writeBack_arbitration_isFiring); + end else begin + lastStageRegFileWrite_valid = 1'b1; + end + if(_zz_241_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_payload_address = writeBack_REGFILE_WRITE_ADDR; + end else begin + lastStageRegFileWrite_payload_address = UpdateRegFileWrite_payload_address; + end + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_payload_data = _zz_121_; + end else begin + lastStageRegFileWrite_payload_data = UpdateRegFileWrite_payload_data; + end + end + + always @ (*) begin + if(writeBack_arbitration_isFiring)begin + writeBack_RegFilePlugin_crBusPort_valid = ((1'b1 || writeBack_BRANCH_DEC) || writeBack_BRANCH_LINK); + end else begin + writeBack_RegFilePlugin_crBusPort_valid = 1'b0; + end + end + + always @ (*) begin + if((writeBack_BRANCH_DEC && writeBack_BRANCH_LINK))begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_DECLNK; + end else begin + if(writeBack_BRANCH_DEC)begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_DEC; + end else begin + if(writeBack_BRANCH_LINK)begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_LNK; + end else begin + writeBack_RegFilePlugin_crBusPort_payload_op = writeBack_CR_WRITE_op; + end + end + end + end + + assign writeBack_RegFilePlugin_crBusPort_payload_ba = writeBack_CR_WRITE_ba; + assign writeBack_RegFilePlugin_crBusPort_payload_bb = writeBack_CR_WRITE_bb; + assign writeBack_RegFilePlugin_crBusPort_payload_bt = writeBack_CR_WRITE_bt; + always @ (*) begin + if(writeBack_BRANCH_LINK)begin + writeBack_RegFilePlugin_crBusPort_payload_imm = _zz_518_; + end else begin + writeBack_RegFilePlugin_crBusPort_payload_imm = writeBack_CR_WRITE_imm; + end + end + + assign writeBack_RegFilePlugin_crBusPort_payload_fxm = writeBack_CR_WRITE_fxm; + always @ (*) begin + if(writeBack_arbitration_isFiring)begin + writeBack_RegFilePlugin_xerBusPort_valid = (writeBack_XER_WRITE_validOV || writeBack_XER_WRITE_validCA); + end else begin + writeBack_RegFilePlugin_xerBusPort_valid = 1'b0; + end + end + + assign writeBack_RegFilePlugin_xerBusPort_payload_validOV = writeBack_XER_WRITE_validOV; + assign writeBack_RegFilePlugin_xerBusPort_payload_validCA = writeBack_XER_WRITE_validCA; + assign writeBack_RegFilePlugin_xerBusPort_payload_imm = writeBack_XER_WRITE_imm; + always @ (*) begin + case(writeBack_SPR_ID) + 11'b00000000001 : begin + writeBack_RegFilePlugin_sprWriteXERPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + default : begin + writeBack_RegFilePlugin_sprWriteXERPort_valid = 1'b0; + end + endcase + end + + assign writeBack_RegFilePlugin_sprWriteXERPort_payload_id = 10'h0; + assign writeBack_RegFilePlugin_sprWriteXERPort_payload_data = writeBack_SRC1; + always @ (*) begin + case(writeBack_SPR_ID) + 11'b00000001001 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + 11'b00000001000 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + 11'b01100101111 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + default : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = 1'b0; + end + endcase + end + + assign writeBack_RegFilePlugin_sprWriteCLTPort_payload_id = _zz_519_[9 : 0]; + assign writeBack_RegFilePlugin_sprWriteCLTPort_payload_data = writeBack_SRC1; + always @ (*) begin + _zz_237_ = 1'b0; + if((writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring))begin + case(writeBack_SPR_ID) + 11'b01111101000 : begin + _zz_237_ = 1'b1; + end + 11'b01111101001 : begin + _zz_237_ = 1'b1; + end + 11'b01111101010 : begin + _zz_237_ = 1'b1; + end + default : begin + end + endcase + end + end + + always @ (*) begin + _zz_243_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_243_ = writeBack_RegFilePlugin_xerBusPort_payload_validCA; + end + end + + always @ (*) begin + _zz_242_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_242_ = writeBack_RegFilePlugin_xerBusPort_payload_validOV; + end + end + + always @ (*) begin + _zz_244_ = (2'bxx); + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_244_ = writeBack_RegFilePlugin_xerBusPort_payload_imm; + end + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b00000000001 : begin + ALU2_sprReadValid = execute_DECODER_stageables_54; + end + default : begin + ALU2_sprReadValid = 1'b0; + end + endcase + end + + always @ (*) begin + _zz_245_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_245_ = 1'b1; + end + end + + assign _zz_246_ = execute_SRC1[7]; + always @ (*) begin + _zz_247_[23] = _zz_246_; + _zz_247_[22] = _zz_246_; + _zz_247_[21] = _zz_246_; + _zz_247_[20] = _zz_246_; + _zz_247_[19] = _zz_246_; + _zz_247_[18] = _zz_246_; + _zz_247_[17] = _zz_246_; + _zz_247_[16] = _zz_246_; + _zz_247_[15] = _zz_246_; + _zz_247_[14] = _zz_246_; + _zz_247_[13] = _zz_246_; + _zz_247_[12] = _zz_246_; + _zz_247_[11] = _zz_246_; + _zz_247_[10] = _zz_246_; + _zz_247_[9] = _zz_246_; + _zz_247_[8] = _zz_246_; + _zz_247_[7] = _zz_246_; + _zz_247_[6] = _zz_246_; + _zz_247_[5] = _zz_246_; + _zz_247_[4] = _zz_246_; + _zz_247_[3] = _zz_246_; + _zz_247_[2] = _zz_246_; + _zz_247_[1] = _zz_246_; + _zz_247_[0] = _zz_246_; + end + + assign _zz_248_ = execute_SRC1[15]; + always @ (*) begin + _zz_249_[15] = _zz_248_; + _zz_249_[14] = _zz_248_; + _zz_249_[13] = _zz_248_; + _zz_249_[12] = _zz_248_; + _zz_249_[11] = _zz_248_; + _zz_249_[10] = _zz_248_; + _zz_249_[9] = _zz_248_; + _zz_249_[8] = _zz_248_; + _zz_249_[7] = _zz_248_; + _zz_249_[6] = _zz_248_; + _zz_249_[5] = _zz_248_; + _zz_249_[4] = _zz_248_; + _zz_249_[3] = _zz_248_; + _zz_249_[2] = _zz_248_; + _zz_249_[1] = _zz_248_; + _zz_249_[0] = _zz_248_; + end + + always @ (*) begin + case(execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + ALU2_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : begin + ALU2_bitwise = (execute_SRC1 & (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + ALU2_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_ORC : begin + ALU2_bitwise = (execute_SRC1 | (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + ALU2_bitwise = (execute_SRC1 ^ execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XORC : begin + ALU2_bitwise = (execute_SRC1 ^ (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : begin + ALU2_bitwise = (~ (execute_SRC1 & execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : begin + ALU2_bitwise = (~ (execute_SRC1 | execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_EQV : begin + ALU2_bitwise = (~ (execute_SRC1 ^ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : begin + ALU2_bitwise = {_zz_247_,execute_SRC1[7 : 0]}; + end + default : begin + ALU2_bitwise = {_zz_249_,execute_SRC1[15 : 0]}; + end + endcase + end + + always @ (*) begin + ALU2_bitwise_enc_cr[1] = ALU2_bitwise[31]; + ALU2_bitwise_enc_cr[0] = (ALU2_bitwise == 32'h0); + end + + always @ (*) begin + case(ALU2_bitwise_enc_cr) + 2'b00 : begin + ALU2_bitwise_cr = (3'b010); + end + 2'b01 : begin + ALU2_bitwise_cr = (3'b001); + end + default : begin + ALU2_bitwise_cr = (3'b100); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : begin + ALU2_amount = execute_INSTRUCTION[15 : 11]; + end + default : begin + ALU2_amount = execute_SRC2[4 : 0]; + end + endcase + end + + assign ALU2_maskMB = execute_INSTRUCTION[10 : 6]; + assign ALU2_maskME = execute_INSTRUCTION[5 : 1]; + always @ (*) begin + ALU2_maskNorm[0] = 1'b0; + if(((ALU2_maskMB <= 5'h1f) && (5'h1f <= ALU2_maskME)))begin + ALU2_maskNorm[0] = 1'b1; + end + ALU2_maskNorm[1] = 1'b0; + if(((ALU2_maskMB <= 5'h1e) && (5'h1e <= ALU2_maskME)))begin + ALU2_maskNorm[1] = 1'b1; + end + ALU2_maskNorm[2] = 1'b0; + if(((ALU2_maskMB <= 5'h1d) && (5'h1d <= ALU2_maskME)))begin + ALU2_maskNorm[2] = 1'b1; + end + ALU2_maskNorm[3] = 1'b0; + if(((ALU2_maskMB <= 5'h1c) && (5'h1c <= ALU2_maskME)))begin + ALU2_maskNorm[3] = 1'b1; + end + ALU2_maskNorm[4] = 1'b0; + if(((ALU2_maskMB <= 5'h1b) && (5'h1b <= ALU2_maskME)))begin + ALU2_maskNorm[4] = 1'b1; + end + ALU2_maskNorm[5] = 1'b0; + if(((ALU2_maskMB <= 5'h1a) && (5'h1a <= ALU2_maskME)))begin + ALU2_maskNorm[5] = 1'b1; + end + ALU2_maskNorm[6] = 1'b0; + if(((ALU2_maskMB <= 5'h19) && (5'h19 <= ALU2_maskME)))begin + ALU2_maskNorm[6] = 1'b1; + end + ALU2_maskNorm[7] = 1'b0; + if(((ALU2_maskMB <= 5'h18) && (5'h18 <= ALU2_maskME)))begin + ALU2_maskNorm[7] = 1'b1; + end + ALU2_maskNorm[8] = 1'b0; + if(((ALU2_maskMB <= 5'h17) && (5'h17 <= ALU2_maskME)))begin + ALU2_maskNorm[8] = 1'b1; + end + ALU2_maskNorm[9] = 1'b0; + if(((ALU2_maskMB <= 5'h16) && (5'h16 <= ALU2_maskME)))begin + ALU2_maskNorm[9] = 1'b1; + end + ALU2_maskNorm[10] = 1'b0; + if(((ALU2_maskMB <= 5'h15) && (5'h15 <= ALU2_maskME)))begin + ALU2_maskNorm[10] = 1'b1; + end + ALU2_maskNorm[11] = 1'b0; + if(((ALU2_maskMB <= 5'h14) && (5'h14 <= ALU2_maskME)))begin + ALU2_maskNorm[11] = 1'b1; + end + ALU2_maskNorm[12] = 1'b0; + if(((ALU2_maskMB <= 5'h13) && (5'h13 <= ALU2_maskME)))begin + ALU2_maskNorm[12] = 1'b1; + end + ALU2_maskNorm[13] = 1'b0; + if(((ALU2_maskMB <= 5'h12) && (5'h12 <= ALU2_maskME)))begin + ALU2_maskNorm[13] = 1'b1; + end + ALU2_maskNorm[14] = 1'b0; + if(((ALU2_maskMB <= 5'h11) && (5'h11 <= ALU2_maskME)))begin + ALU2_maskNorm[14] = 1'b1; + end + ALU2_maskNorm[15] = 1'b0; + if(((ALU2_maskMB <= 5'h10) && (5'h10 <= ALU2_maskME)))begin + ALU2_maskNorm[15] = 1'b1; + end + ALU2_maskNorm[16] = 1'b0; + if(((ALU2_maskMB <= 5'h0f) && (5'h0f <= ALU2_maskME)))begin + ALU2_maskNorm[16] = 1'b1; + end + ALU2_maskNorm[17] = 1'b0; + if(((ALU2_maskMB <= 5'h0e) && (5'h0e <= ALU2_maskME)))begin + ALU2_maskNorm[17] = 1'b1; + end + ALU2_maskNorm[18] = 1'b0; + if(((ALU2_maskMB <= 5'h0d) && (5'h0d <= ALU2_maskME)))begin + ALU2_maskNorm[18] = 1'b1; + end + ALU2_maskNorm[19] = 1'b0; + if(((ALU2_maskMB <= 5'h0c) && (5'h0c <= ALU2_maskME)))begin + ALU2_maskNorm[19] = 1'b1; + end + ALU2_maskNorm[20] = 1'b0; + if(((ALU2_maskMB <= 5'h0b) && (5'h0b <= ALU2_maskME)))begin + ALU2_maskNorm[20] = 1'b1; + end + ALU2_maskNorm[21] = 1'b0; + if(((ALU2_maskMB <= 5'h0a) && (5'h0a <= ALU2_maskME)))begin + ALU2_maskNorm[21] = 1'b1; + end + ALU2_maskNorm[22] = 1'b0; + if(((ALU2_maskMB <= 5'h09) && (5'h09 <= ALU2_maskME)))begin + ALU2_maskNorm[22] = 1'b1; + end + ALU2_maskNorm[23] = 1'b0; + if(((ALU2_maskMB <= 5'h08) && (5'h08 <= ALU2_maskME)))begin + ALU2_maskNorm[23] = 1'b1; + end + ALU2_maskNorm[24] = 1'b0; + if(((ALU2_maskMB <= 5'h07) && (5'h07 <= ALU2_maskME)))begin + ALU2_maskNorm[24] = 1'b1; + end + ALU2_maskNorm[25] = 1'b0; + if(((ALU2_maskMB <= 5'h06) && (5'h06 <= ALU2_maskME)))begin + ALU2_maskNorm[25] = 1'b1; + end + ALU2_maskNorm[26] = 1'b0; + if(((ALU2_maskMB <= 5'h05) && (5'h05 <= ALU2_maskME)))begin + ALU2_maskNorm[26] = 1'b1; + end + ALU2_maskNorm[27] = 1'b0; + if(((ALU2_maskMB <= 5'h04) && (5'h04 <= ALU2_maskME)))begin + ALU2_maskNorm[27] = 1'b1; + end + ALU2_maskNorm[28] = 1'b0; + if(((ALU2_maskMB <= 5'h03) && (5'h03 <= ALU2_maskME)))begin + ALU2_maskNorm[28] = 1'b1; + end + ALU2_maskNorm[29] = 1'b0; + if(((ALU2_maskMB <= 5'h02) && (5'h02 <= ALU2_maskME)))begin + ALU2_maskNorm[29] = 1'b1; + end + ALU2_maskNorm[30] = 1'b0; + if(((ALU2_maskMB <= 5'h01) && (5'h01 <= ALU2_maskME)))begin + ALU2_maskNorm[30] = 1'b1; + end + ALU2_maskNorm[31] = 1'b0; + if(((ALU2_maskMB <= 5'h0) && (5'h0 <= ALU2_maskME)))begin + ALU2_maskNorm[31] = 1'b1; + end + end + + always @ (*) begin + ALU2_maskInvt[0] = 1'b0; + if(((5'h1f <= ALU2_maskME) || (ALU2_maskMB <= 5'h1f)))begin + ALU2_maskInvt[0] = 1'b1; + end + ALU2_maskInvt[1] = 1'b0; + if(((5'h1e <= ALU2_maskME) || (ALU2_maskMB <= 5'h1e)))begin + ALU2_maskInvt[1] = 1'b1; + end + ALU2_maskInvt[2] = 1'b0; + if(((5'h1d <= ALU2_maskME) || (ALU2_maskMB <= 5'h1d)))begin + ALU2_maskInvt[2] = 1'b1; + end + ALU2_maskInvt[3] = 1'b0; + if(((5'h1c <= ALU2_maskME) || (ALU2_maskMB <= 5'h1c)))begin + ALU2_maskInvt[3] = 1'b1; + end + ALU2_maskInvt[4] = 1'b0; + if(((5'h1b <= ALU2_maskME) || (ALU2_maskMB <= 5'h1b)))begin + ALU2_maskInvt[4] = 1'b1; + end + ALU2_maskInvt[5] = 1'b0; + if(((5'h1a <= ALU2_maskME) || (ALU2_maskMB <= 5'h1a)))begin + ALU2_maskInvt[5] = 1'b1; + end + ALU2_maskInvt[6] = 1'b0; + if(((5'h19 <= ALU2_maskME) || (ALU2_maskMB <= 5'h19)))begin + ALU2_maskInvt[6] = 1'b1; + end + ALU2_maskInvt[7] = 1'b0; + if(((5'h18 <= ALU2_maskME) || (ALU2_maskMB <= 5'h18)))begin + ALU2_maskInvt[7] = 1'b1; + end + ALU2_maskInvt[8] = 1'b0; + if(((5'h17 <= ALU2_maskME) || (ALU2_maskMB <= 5'h17)))begin + ALU2_maskInvt[8] = 1'b1; + end + ALU2_maskInvt[9] = 1'b0; + if(((5'h16 <= ALU2_maskME) || (ALU2_maskMB <= 5'h16)))begin + ALU2_maskInvt[9] = 1'b1; + end + ALU2_maskInvt[10] = 1'b0; + if(((5'h15 <= ALU2_maskME) || (ALU2_maskMB <= 5'h15)))begin + ALU2_maskInvt[10] = 1'b1; + end + ALU2_maskInvt[11] = 1'b0; + if(((5'h14 <= ALU2_maskME) || (ALU2_maskMB <= 5'h14)))begin + ALU2_maskInvt[11] = 1'b1; + end + ALU2_maskInvt[12] = 1'b0; + if(((5'h13 <= ALU2_maskME) || (ALU2_maskMB <= 5'h13)))begin + ALU2_maskInvt[12] = 1'b1; + end + ALU2_maskInvt[13] = 1'b0; + if(((5'h12 <= ALU2_maskME) || (ALU2_maskMB <= 5'h12)))begin + ALU2_maskInvt[13] = 1'b1; + end + ALU2_maskInvt[14] = 1'b0; + if(((5'h11 <= ALU2_maskME) || (ALU2_maskMB <= 5'h11)))begin + ALU2_maskInvt[14] = 1'b1; + end + ALU2_maskInvt[15] = 1'b0; + if(((5'h10 <= ALU2_maskME) || (ALU2_maskMB <= 5'h10)))begin + ALU2_maskInvt[15] = 1'b1; + end + ALU2_maskInvt[16] = 1'b0; + if(((5'h0f <= ALU2_maskME) || (ALU2_maskMB <= 5'h0f)))begin + ALU2_maskInvt[16] = 1'b1; + end + ALU2_maskInvt[17] = 1'b0; + if(((5'h0e <= ALU2_maskME) || (ALU2_maskMB <= 5'h0e)))begin + ALU2_maskInvt[17] = 1'b1; + end + ALU2_maskInvt[18] = 1'b0; + if(((5'h0d <= ALU2_maskME) || (ALU2_maskMB <= 5'h0d)))begin + ALU2_maskInvt[18] = 1'b1; + end + ALU2_maskInvt[19] = 1'b0; + if(((5'h0c <= ALU2_maskME) || (ALU2_maskMB <= 5'h0c)))begin + ALU2_maskInvt[19] = 1'b1; + end + ALU2_maskInvt[20] = 1'b0; + if(((5'h0b <= ALU2_maskME) || (ALU2_maskMB <= 5'h0b)))begin + ALU2_maskInvt[20] = 1'b1; + end + ALU2_maskInvt[21] = 1'b0; + if(((5'h0a <= ALU2_maskME) || (ALU2_maskMB <= 5'h0a)))begin + ALU2_maskInvt[21] = 1'b1; + end + ALU2_maskInvt[22] = 1'b0; + if(((5'h09 <= ALU2_maskME) || (ALU2_maskMB <= 5'h09)))begin + ALU2_maskInvt[22] = 1'b1; + end + ALU2_maskInvt[23] = 1'b0; + if(((5'h08 <= ALU2_maskME) || (ALU2_maskMB <= 5'h08)))begin + ALU2_maskInvt[23] = 1'b1; + end + ALU2_maskInvt[24] = 1'b0; + if(((5'h07 <= ALU2_maskME) || (ALU2_maskMB <= 5'h07)))begin + ALU2_maskInvt[24] = 1'b1; + end + ALU2_maskInvt[25] = 1'b0; + if(((5'h06 <= ALU2_maskME) || (ALU2_maskMB <= 5'h06)))begin + ALU2_maskInvt[25] = 1'b1; + end + ALU2_maskInvt[26] = 1'b0; + if(((5'h05 <= ALU2_maskME) || (ALU2_maskMB <= 5'h05)))begin + ALU2_maskInvt[26] = 1'b1; + end + ALU2_maskInvt[27] = 1'b0; + if(((5'h04 <= ALU2_maskME) || (ALU2_maskMB <= 5'h04)))begin + ALU2_maskInvt[27] = 1'b1; + end + ALU2_maskInvt[28] = 1'b0; + if(((5'h03 <= ALU2_maskME) || (ALU2_maskMB <= 5'h03)))begin + ALU2_maskInvt[28] = 1'b1; + end + ALU2_maskInvt[29] = 1'b0; + if(((5'h02 <= ALU2_maskME) || (ALU2_maskMB <= 5'h02)))begin + ALU2_maskInvt[29] = 1'b1; + end + ALU2_maskInvt[30] = 1'b0; + if(((5'h01 <= ALU2_maskME) || (ALU2_maskMB <= 5'h01)))begin + ALU2_maskInvt[30] = 1'b1; + end + ALU2_maskInvt[31] = 1'b0; + if(((5'h0 <= ALU2_maskME) || (ALU2_maskMB <= 5'h0)))begin + ALU2_maskInvt[31] = 1'b1; + end + end + + always @ (*) begin + if((ALU2_maskMB <= ALU2_maskME))begin + ALU2_mask = ALU2_maskNorm; + end else begin + ALU2_mask = ALU2_maskInvt; + end + end + + assign _zz_250_ = execute_SRC1; + assign _zz_251_ = execute_SRC1; + always @ (*) begin + case(execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : begin + _zz_252_ = (_zz_93_ & ALU2_mask); + end + `AluRimiCtrlEnum_defaultEncoding_INS : begin + _zz_252_ = ((_zz_88_ & ALU2_mask) | (execute_SRC2 & (~ ALU2_mask))); + end + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : begin + _zz_252_ = _zz_520_[31 : 0]; + end + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : begin + _zz_252_ = _zz_521_[31 : 0]; + end + default : begin + _zz_252_ = _zz_522_[31 : 0]; + end + endcase + end + + assign ALU2_rimi = _zz_252_; + always @ (*) begin + ALU2_sraw_ca = 1'b0; + if((ALU2_amount != 5'h0))begin + ALU2_sraw_ca = (execute_SRC1[31] && ((ALU2_sraw_wtf & execute_SRC1) != 32'h0)); + end + end + + assign ALU2_sraw_wtf = (_zz_526_ >>> _zz_527_); + always @ (*) begin + ALU2_rimi_enc_cr[1] = ALU2_rimi[31]; + ALU2_rimi_enc_cr[0] = (ALU2_rimi == 32'h0); + end + + always @ (*) begin + case(ALU2_rimi_enc_cr) + 2'b00 : begin + ALU2_rimi_cr = (3'b010); + end + 2'b01 : begin + ALU2_rimi_cr = (3'b001); + end + default : begin + ALU2_rimi_cr = (3'b100); + end + endcase + end + + always @ (*) begin + _zz_253_[0] = execute_SRC1[31]; + _zz_253_[1] = execute_SRC1[30]; + _zz_253_[2] = execute_SRC1[29]; + _zz_253_[3] = execute_SRC1[28]; + _zz_253_[4] = execute_SRC1[27]; + _zz_253_[5] = execute_SRC1[26]; + _zz_253_[6] = execute_SRC1[25]; + _zz_253_[7] = execute_SRC1[24]; + _zz_253_[8] = execute_SRC1[23]; + _zz_253_[9] = execute_SRC1[22]; + _zz_253_[10] = execute_SRC1[21]; + _zz_253_[11] = execute_SRC1[20]; + _zz_253_[12] = execute_SRC1[19]; + _zz_253_[13] = execute_SRC1[18]; + _zz_253_[14] = execute_SRC1[17]; + _zz_253_[15] = execute_SRC1[16]; + _zz_253_[16] = execute_SRC1[15]; + _zz_253_[17] = execute_SRC1[14]; + _zz_253_[18] = execute_SRC1[13]; + _zz_253_[19] = execute_SRC1[12]; + _zz_253_[20] = execute_SRC1[11]; + _zz_253_[21] = execute_SRC1[10]; + _zz_253_[22] = execute_SRC1[9]; + _zz_253_[23] = execute_SRC1[8]; + _zz_253_[24] = execute_SRC1[7]; + _zz_253_[25] = execute_SRC1[6]; + _zz_253_[26] = execute_SRC1[5]; + _zz_253_[27] = execute_SRC1[4]; + _zz_253_[28] = execute_SRC1[3]; + _zz_253_[29] = execute_SRC1[2]; + _zz_253_[30] = execute_SRC1[1]; + _zz_253_[31] = execute_SRC1[0]; + end + + always @ (*) begin + cntzero_msb = 6'h0; + if(_zz_253_[31])begin + cntzero_msb = 6'h1f; + end + if(_zz_253_[30])begin + cntzero_msb = 6'h1e; + end + if(_zz_253_[29])begin + cntzero_msb = 6'h1d; + end + if(_zz_253_[28])begin + cntzero_msb = 6'h1c; + end + if(_zz_253_[27])begin + cntzero_msb = 6'h1b; + end + if(_zz_253_[26])begin + cntzero_msb = 6'h1a; + end + if(_zz_253_[25])begin + cntzero_msb = 6'h19; + end + if(_zz_253_[24])begin + cntzero_msb = 6'h18; + end + if(_zz_253_[23])begin + cntzero_msb = 6'h17; + end + if(_zz_253_[22])begin + cntzero_msb = 6'h16; + end + if(_zz_253_[21])begin + cntzero_msb = 6'h15; + end + if(_zz_253_[20])begin + cntzero_msb = 6'h14; + end + if(_zz_253_[19])begin + cntzero_msb = 6'h13; + end + if(_zz_253_[18])begin + cntzero_msb = 6'h12; + end + if(_zz_253_[17])begin + cntzero_msb = 6'h11; + end + if(_zz_253_[16])begin + cntzero_msb = 6'h10; + end + if(_zz_253_[15])begin + cntzero_msb = 6'h0f; + end + if(_zz_253_[14])begin + cntzero_msb = 6'h0e; + end + if(_zz_253_[13])begin + cntzero_msb = 6'h0d; + end + if(_zz_253_[12])begin + cntzero_msb = 6'h0c; + end + if(_zz_253_[11])begin + cntzero_msb = 6'h0b; + end + if(_zz_253_[10])begin + cntzero_msb = 6'h0a; + end + if(_zz_253_[9])begin + cntzero_msb = 6'h09; + end + if(_zz_253_[8])begin + cntzero_msb = 6'h08; + end + if(_zz_253_[7])begin + cntzero_msb = 6'h07; + end + if(_zz_253_[6])begin + cntzero_msb = 6'h06; + end + if(_zz_253_[5])begin + cntzero_msb = 6'h05; + end + if(_zz_253_[4])begin + cntzero_msb = 6'h04; + end + if(_zz_253_[3])begin + cntzero_msb = 6'h03; + end + if(_zz_253_[2])begin + cntzero_msb = 6'h02; + end + if(_zz_253_[1])begin + cntzero_msb = 6'h01; + end + if(_zz_253_[0])begin + cntzero_msb = 6'h0; + end + end + + always @ (*) begin + if((cntzero_msb == 6'h0))begin + if(execute_SRC1[31])begin + cntzero_lz = 6'h0; + end else begin + cntzero_lz = 6'h20; + end + end else begin + cntzero_lz = cntzero_msb; + end + end + + always @ (*) begin + cntzero_lsb = 6'h0; + if(execute_SRC1[31])begin + cntzero_lsb = 6'h1f; + end + if(execute_SRC1[30])begin + cntzero_lsb = 6'h1e; + end + if(execute_SRC1[29])begin + cntzero_lsb = 6'h1d; + end + if(execute_SRC1[28])begin + cntzero_lsb = 6'h1c; + end + if(execute_SRC1[27])begin + cntzero_lsb = 6'h1b; + end + if(execute_SRC1[26])begin + cntzero_lsb = 6'h1a; + end + if(execute_SRC1[25])begin + cntzero_lsb = 6'h19; + end + if(execute_SRC1[24])begin + cntzero_lsb = 6'h18; + end + if(execute_SRC1[23])begin + cntzero_lsb = 6'h17; + end + if(execute_SRC1[22])begin + cntzero_lsb = 6'h16; + end + if(execute_SRC1[21])begin + cntzero_lsb = 6'h15; + end + if(execute_SRC1[20])begin + cntzero_lsb = 6'h14; + end + if(execute_SRC1[19])begin + cntzero_lsb = 6'h13; + end + if(execute_SRC1[18])begin + cntzero_lsb = 6'h12; + end + if(execute_SRC1[17])begin + cntzero_lsb = 6'h11; + end + if(execute_SRC1[16])begin + cntzero_lsb = 6'h10; + end + if(execute_SRC1[15])begin + cntzero_lsb = 6'h0f; + end + if(execute_SRC1[14])begin + cntzero_lsb = 6'h0e; + end + if(execute_SRC1[13])begin + cntzero_lsb = 6'h0d; + end + if(execute_SRC1[12])begin + cntzero_lsb = 6'h0c; + end + if(execute_SRC1[11])begin + cntzero_lsb = 6'h0b; + end + if(execute_SRC1[10])begin + cntzero_lsb = 6'h0a; + end + if(execute_SRC1[9])begin + cntzero_lsb = 6'h09; + end + if(execute_SRC1[8])begin + cntzero_lsb = 6'h08; + end + if(execute_SRC1[7])begin + cntzero_lsb = 6'h07; + end + if(execute_SRC1[6])begin + cntzero_lsb = 6'h06; + end + if(execute_SRC1[5])begin + cntzero_lsb = 6'h05; + end + if(execute_SRC1[4])begin + cntzero_lsb = 6'h04; + end + if(execute_SRC1[3])begin + cntzero_lsb = 6'h03; + end + if(execute_SRC1[2])begin + cntzero_lsb = 6'h02; + end + if(execute_SRC1[1])begin + cntzero_lsb = 6'h01; + end + if(execute_SRC1[0])begin + cntzero_lsb = 6'h0; + end + end + + always @ (*) begin + if((cntzero_lsb == 6'h0))begin + if(execute_SRC1[0])begin + cntzero_tz = 6'h0; + end else begin + cntzero_tz = 6'h20; + end + end else begin + cntzero_tz = cntzero_lsb; + end + end + + assign _zz_254_ = execute_SRC1[31 : 24]; + assign popcnt_pb3 = _zz_87_; + assign _zz_255_ = execute_SRC1[23 : 16]; + assign popcnt_pb2 = _zz_86_; + assign _zz_256_ = execute_SRC1[15 : 8]; + assign popcnt_pb1 = _zz_85_; + assign _zz_257_ = execute_SRC1[7 : 0]; + assign popcnt_pb0 = _zz_84_; + assign _zz_258_ = execute_SRC1[31 : 0]; + assign popcnt_pw0 = _zz_83_; + always @ (*) begin + if((execute_SRC1[31 : 24] == execute_SRC2[31 : 24]))begin + popcnt_cmpb[31 : 24] = 8'hff; + end else begin + popcnt_cmpb[31 : 24] = 8'h0; + end + if((execute_SRC1[23 : 16] == execute_SRC2[23 : 16]))begin + popcnt_cmpb[23 : 16] = 8'hff; + end else begin + popcnt_cmpb[23 : 16] = 8'h0; + end + if((execute_SRC1[15 : 8] == execute_SRC2[15 : 8]))begin + popcnt_cmpb[15 : 8] = 8'hff; + end else begin + popcnt_cmpb[15 : 8] = 8'h0; + end + if((execute_SRC1[7 : 0] == execute_SRC2[7 : 0]))begin + popcnt_cmpb[7 : 0] = 8'hff; + end else begin + popcnt_cmpb[7 : 0] = 8'h0; + end + end + + assign popcnt_prtyw = (((execute_SRC1[24] ^ execute_SRC1[16]) ^ execute_SRC1[8]) ^ execute_SRC1[0]); + always @ (*) begin + case(execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : begin + ALU2_spec = {26'h0,cntzero_lz}; + end + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : begin + ALU2_spec = {26'h0,cntzero_tz}; + end + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : begin + ALU2_spec = {{{{{{{(4'b0000),popcnt_pb3},(4'b0000)},popcnt_pb2},(4'b0000)},popcnt_pb1},(4'b0000)},popcnt_pb0}; + end + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : begin + ALU2_spec = {26'h0,popcnt_pw0}; + end + `AluSpecCtrlEnum_defaultEncoding_CMPB : begin + ALU2_spec = popcnt_cmpb; + end + default : begin + ALU2_spec = {31'h0,popcnt_prtyw}; + end + endcase + end + + always @ (*) begin + case(_zz_441_) + 8'b10000000 : begin + _zz_259_ = {_zz_529_[31 : 28],28'h0}; + end + 8'b01000000 : begin + _zz_259_ = {{(4'b0000),_zz_530_[27 : 24]},24'h0}; + end + 8'b00100000 : begin + _zz_259_ = {{8'h0,_zz_531_[23 : 20]},20'h0}; + end + 8'b00010000 : begin + _zz_259_ = {{12'h0,_zz_532_[19 : 16]},16'h0}; + end + 8'b00001000 : begin + _zz_259_ = {{16'h0,_zz_533_[15 : 12]},12'h0}; + end + 8'b00000100 : begin + _zz_259_ = {{20'h0,_zz_534_[11 : 8]},8'h0}; + end + 8'b00000010 : begin + _zz_259_ = {{24'h0,_zz_535_[7 : 4]},(4'b0000)}; + end + default : begin + _zz_259_ = {28'h0,_zz_536_[3 : 0]}; + end + endcase + end + + always @ (*) begin + case(_zz_442_) + 3'b000 : begin + _zz_260_ = _zz_537_[31]; + end + 3'b001 : begin + _zz_260_ = _zz_538_[27]; + end + 3'b010 : begin + _zz_260_ = _zz_539_[23]; + end + 3'b011 : begin + _zz_260_ = _zz_540_[19]; + end + 3'b100 : begin + _zz_260_ = _zz_541_[15]; + end + 3'b101 : begin + _zz_260_ = _zz_542_[11]; + end + 3'b110 : begin + _zz_260_ = _zz_543_[7]; + end + default : begin + _zz_260_ = _zz_544_[3]; + end + endcase + end + + always @ (*) begin + case(_zz_443_) + 3'b000 : begin + _zz_261_ = _zz_545_[30]; + end + 3'b001 : begin + _zz_261_ = _zz_546_[26]; + end + 3'b010 : begin + _zz_261_ = _zz_547_[22]; + end + 3'b011 : begin + _zz_261_ = _zz_548_[18]; + end + 3'b100 : begin + _zz_261_ = _zz_549_[14]; + end + 3'b101 : begin + _zz_261_ = _zz_550_[10]; + end + 3'b110 : begin + _zz_261_ = _zz_551_[6]; + end + default : begin + _zz_261_ = _zz_552_[2]; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_BIT_1 : begin + _zz_262_ = ALU2_bitwise; + end + `AluCtrlEnum_defaultEncoding_ADD : begin + _zz_262_ = execute_SRC_ADD; + end + `AluCtrlEnum_defaultEncoding_RIMI : begin + _zz_262_ = ALU2_rimi; + end + default : begin + _zz_262_ = ALU2_spec; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : begin + _zz_263_ = execute_INSTRUCTION[25 : 21]; + end + default : begin + _zz_263_ = execute_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + if(execute_DECODER_stageables_6)begin + _zz_79_ = 11'h402; + end else begin + if(execute_DECODER_stageables_14)begin + _zz_79_ = 11'h401; + end else begin + _zz_79_ = {{(1'b0),execute_INSTRUCTION[15 : 11]},execute_INSTRUCTION[20 : 16]}; + end + end + end + + always @ (*) begin + ALU2_xer_ca = 1'b0; + if((execute_DECODER_stageables_16 == `AluRimiCtrlEnum_defaultEncoding_SHIFTRA))begin + ALU2_xer_ca = ALU2_sraw_ca; + end else begin + ALU2_xer_ca = execute_SRC_CAOV[1]; + end + end + + assign ALU2_xer_ov = execute_SRC_CAOV[0]; + assign ALU2_xer_so = (ALU2_XER[31] || ALU2_xer_ov); + assign ALU2_xerBus_validOV = (execute_DECODER_stageables_18 && execute_INSTRUCTION[10]); + assign ALU2_xerBus_validCA = execute_DECODER_stageables_11; + assign ALU2_xerBus_imm = {ALU2_xer_ov,ALU2_xer_ca}; + always @ (*) begin + case(execute_SRC_CR) + 2'b00 : begin + ALU2_alu_cr = (3'b010); + end + 2'b01 : begin + ALU2_alu_cr = (3'b001); + end + default : begin + ALU2_alu_cr = (3'b100); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_BIT_1 : begin + ALU2_cr0_val_a = ALU2_bitwise_cr; + end + `AluCtrlEnum_defaultEncoding_ADD : begin + ALU2_cr0_val_a = ALU2_alu_cr; + end + `AluCtrlEnum_defaultEncoding_RIMI : begin + ALU2_cr0_val_a = ALU2_rimi_cr; + end + default : begin + ALU2_cr0_val_a = (3'b000); + end + endcase + end + + assign ALU2_cr0_val = {ALU2_cr0_val_a,ALU2_xer_so}; + assign ALU2_cr_record = ((! execute_DECODER_stageables_21) && (execute_DECODER_stageables_57 || (execute_DECODER_stageables_28 && (execute_INSTRUCTION[0] == 1'b1)))); + assign ALU2_cr_mcrf = (execute_DECODER_stageables_51 == `CRMoveCtrlEnum_defaultEncoding_MCRF); + assign ALU2_cr_update_valid = (((ALU2_cr_record || execute_DECODER_stageables_34) || execute_DECODER_stageables_46) || execute_DECODER_stageables_21); + always @ (*) begin + if(ALU2_cr_record)begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + if(execute_DECODER_stageables_21)begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_CMP; + end else begin + if(execute_DECODER_stageables_34)begin + case(execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_AND_1; + end + `CRLogCtrlEnum_defaultEncoding_OR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_OR_1; + end + `CRLogCtrlEnum_defaultEncoding_XOR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_XOR_1; + end + `CRLogCtrlEnum_defaultEncoding_NAND_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NAND_1; + end + `CRLogCtrlEnum_defaultEncoding_NOR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NOR_1; + end + `CRLogCtrlEnum_defaultEncoding_EQV : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_EQV; + end + `CRLogCtrlEnum_defaultEncoding_ANDC : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_ANDC; + end + default : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_ORC; + end + endcase + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MCRF; + end + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MTCRF; + end + default : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MTCRF; + end + endcase + end else begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_ba = execute_INSTRUCTION[20 : 16]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_ba = {(2'b00),execute_INSTRUCTION[20 : 18]}; + end else begin + ALU2_crBus_ba = 5'h0; + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_bb = execute_INSTRUCTION[15 : 11]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_bb = 5'h0; + end else begin + ALU2_crBus_bb = 5'h0; + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_bt = execute_INSTRUCTION[25 : 21]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_bt = {(2'b00),execute_INSTRUCTION[25 : 23]}; + end else begin + ALU2_crBus_bt = 5'h0; + end + end + end + + always @ (*) begin + if(ALU2_cr_record)begin + ALU2_crBus_imm = {28'h0,ALU2_cr0_val}; + end else begin + if(execute_DECODER_stageables_21)begin + ALU2_crBus_imm = {28'h0,ALU2_cr0_val}; + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_imm = {{{{28'h0,ALU2_XER[30]},ALU2_XER[19]},ALU2_XER[29]},ALU2_XER[18]}; + end + default : begin + ALU2_crBus_imm = execute_SRC1; + end + endcase + end else begin + ALU2_crBus_imm = 32'h0; + end + end + end + end + + always @ (*) begin + ALU2_crBus_fxm = 8'h0; + if(execute_DECODER_stageables_21)begin + ALU2_crBus_fxm[_zz_555_] = 1'b1; + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_fxm = execute_INSTRUCTION[19 : 12]; + end + default : begin + ALU2_crBus_fxm = execute_INSTRUCTION[19 : 12]; + end + endcase + end + end + end + + assign _zz_76_ = ALU2_crBus_op; + always @ (*) begin + if(ALU2_cr_update_valid)begin + case(ALU2_crBus_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_75_ = 8'h80; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_75_ = 8'h40; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_75_ = 8'h02; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_75_ = ALU2_crBus_fxm; + end + default : begin + _zz_75_ = 8'hff; + end + endcase + end else begin + _zz_75_ = 8'h0; + end + end + + assign SRC1_ra = execute_INSTRUCTION[20 : 16]; + assign SRC1_rb = execute_INSTRUCTION[15 : 11]; + assign SRC1_rs = execute_INSTRUCTION[25 : 21]; + assign SRC1_rt = execute_INSTRUCTION[25 : 21]; + always @ (*) begin + case(execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : begin + _zz_264_ = _zz_73_; + end + `Src1CtrlEnum_defaultEncoding_RA_N : begin + _zz_264_ = (~ _zz_73_); + end + `Src1CtrlEnum_defaultEncoding_RA_0 : begin + _zz_264_ = _zz_556_; + end + `Src1CtrlEnum_defaultEncoding_RA_NIA : begin + _zz_264_ = _zz_72_; + end + default : begin + _zz_264_ = execute_RS; + end + endcase + end + + assign _zz_265_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_266_[15] = _zz_265_; + _zz_266_[14] = _zz_265_; + _zz_266_[13] = _zz_265_; + _zz_266_[12] = _zz_265_; + _zz_266_[11] = _zz_265_; + _zz_266_[10] = _zz_265_; + _zz_266_[9] = _zz_265_; + _zz_266_[8] = _zz_265_; + _zz_266_[7] = _zz_265_; + _zz_266_[6] = _zz_265_; + _zz_266_[5] = _zz_265_; + _zz_266_[4] = _zz_265_; + _zz_266_[3] = _zz_265_; + _zz_266_[2] = _zz_265_; + _zz_266_[1] = _zz_265_; + _zz_266_[0] = _zz_265_; + end + + always @ (*) begin + case(execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : begin + _zz_267_ = execute_RB; + end + `Src2CtrlEnum_defaultEncoding_RB_0 : begin + _zz_267_ = _zz_557_; + end + `Src2CtrlEnum_defaultEncoding_RB_M1 : begin + _zz_267_ = _zz_558_; + end + `Src2CtrlEnum_defaultEncoding_RB_UI : begin + _zz_267_ = {16'h0,execute_INSTRUCTION[15 : 0]}; + end + `Src2CtrlEnum_defaultEncoding_RB_SI : begin + _zz_267_ = {_zz_266_,execute_INSTRUCTION[15 : 0]}; + end + `Src2CtrlEnum_defaultEncoding_RB_SH : begin + _zz_267_ = {execute_INSTRUCTION[15 : 0],16'h0}; + end + `Src2CtrlEnum_defaultEncoding_RB_PCISD : begin + _zz_267_ = {{{execute_INSTRUCTION[15 : 6],execute_INSTRUCTION[20 : 16]},execute_INSTRUCTION[0]},16'h0004}; + end + default : begin + _zz_267_ = _zz_73_; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : begin + _zz_268_ = execute_XER_CA; + end + `Src3CtrlEnum_defaultEncoding_CA_0 : begin + _zz_268_ = (1'b0); + end + default : begin + _zz_268_ = (1'b1); + end + endcase + end + + assign SRC2_ra = execute_SRC1; + assign SRC2_rb = execute_SRC2; + assign SRC2_cin = execute_SRC3; + assign SRC2_adder = (_zz_559_ + _zz_560_); + assign SRC2_add_cr = {SRC2_adder[31],(SRC2_adder[31 : 0] == 32'h0)}; + assign SRC2_cmp_cr = (execute_DECODER_stageables_48 ? {(SRC2_ra < SRC2_rb),(SRC2_ra == SRC2_rb)} : {($signed(_zz_561_) < $signed(_zz_562_)),(SRC2_ra == SRC2_rb)}); + assign SRC2_ca = SRC2_adder[32]; + assign SRC2_ov = ((SRC2_adder[32] ^ SRC2_adder[31]) && (! (SRC2_ra[31] ^ SRC2_rb[31]))); + assign UpdateRegFileWrite_valid = _zz_269_; + assign UpdateRegFileWrite_payload_address = _zz_270_; + assign UpdateRegFileWrite_payload_data = _zz_271_; + assign MUL1_a = execute_SRC1; + assign MUL1_b = execute_SRC2; + assign MUL1_aSigned = execute_DECODER_stageables_35; + assign MUL1_bSigned = execute_DECODER_stageables_35; + assign MUL1_aULow = MUL1_a[15 : 0]; + assign MUL1_bULow = MUL1_b[15 : 0]; + assign MUL1_aSLow = {1'b0,MUL1_a[15 : 0]}; + assign MUL1_bSLow = {1'b0,MUL1_b[15 : 0]}; + assign MUL1_aHigh = {(MUL1_aSigned && MUL1_a[31]),MUL1_a[31 : 16]}; + assign MUL1_bHigh = {(MUL1_bSigned && MUL1_b[31]),MUL1_b[31 : 16]}; + assign MUL3_result = ($signed(_zz_563_) + $signed(_zz_564_)); + assign MUL3_xer_ov = MUL3_result[32]; + always @ (*) begin + MUL3_xer_so = 1'b0; + if((writeBack_DECODER_stageables_36 && writeBack_INSTRUCTION[10]))begin + MUL3_xer_so = (writeBack_XER_SO || MUL3_xer_ov); + end else begin + MUL3_xer_so = writeBack_XER_SO; + end + end + + always @ (*) begin + if(writeBack_DECODER_stageables_55)begin + MUL3_result32 = _zz_565_; + end else begin + MUL3_result32 = _zz_566_; + end + end + + assign MUL3_cr = {MUL3_result32[31],(MUL3_result32[31 : 0] == 32'h0)}; + always @ (*) begin + case(writeBack_SRC_CR) + 2'b00 : begin + MUL3_cr_decode = {(3'b010),MUL3_xer_so}; + end + 2'b01 : begin + MUL3_cr_decode = {(3'b001),MUL3_xer_so}; + end + default : begin + MUL3_cr_decode = {(3'b100),MUL3_xer_so}; + end + endcase + end + + always @ (*) begin + _zz_272_ = 1'b0; + if(_zz_400_)begin + _zz_272_ = 1'b1; + end + end + + always @ (*) begin + _zz_273_ = (5'bxxxxx); + if(MUL3_cr_record)begin + _zz_273_ = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + _zz_273_ = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + + always @ (*) begin + _zz_274_ = 32'h0; + _zz_274_ = {28'h0,MUL3_cr_decode}; + end + + assign MUL3_cr_record = (writeBack_DECODER_stageables_24 && writeBack_INSTRUCTION[0]); + assign MULDIV_frontendOk = 1'b1; + always @ (*) begin + MULDIV1_counter_willIncrement = 1'b0; + if(_zz_399_)begin + if(_zz_422_)begin + MULDIV1_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + MULDIV1_counter_willClear = 1'b0; + if(_zz_423_)begin + MULDIV1_counter_willClear = 1'b1; + end + end + + assign MULDIV1_counter_willOverflowIfInc = (MULDIV1_counter_value == 6'h21); + assign MULDIV1_counter_willOverflow = (MULDIV1_counter_willOverflowIfInc && MULDIV1_counter_willIncrement); + always @ (*) begin + if(MULDIV1_counter_willOverflow)begin + MULDIV1_counter_valueNext = 6'h0; + end else begin + MULDIV1_counter_valueNext = (MULDIV1_counter_value + _zz_568_); + end + if(MULDIV1_counter_willClear)begin + MULDIV1_counter_valueNext = 6'h0; + end + end + + always @ (*) begin + MULDIV1_crBusPort_valid = 1'b0; + if(_zz_399_)begin + MULDIV1_crBusPort_valid = 1'b1; + end + end + + always @ (*) begin + MULDIV1_crBusPort_payload_op = (5'bxxxxx); + if(_zz_399_)begin + if(memory_INSTRUCTION[0])begin + MULDIV1_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + MULDIV1_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + end + + assign MULDIV1_crBusPort_payload_ba = 5'h0; + assign MULDIV1_crBusPort_payload_bb = 5'h0; + assign MULDIV1_crBusPort_payload_bt = 5'h0; + always @ (*) begin + MULDIV1_crBusPort_payload_imm = 32'h0; + if(_zz_399_)begin + MULDIV1_crBusPort_payload_imm = {28'h0,_zz_279_}; + end + end + + assign MULDIV1_crBusPort_payload_fxm = 8'h0; + always @ (*) begin + MULDIV1_xerBusPort_valid = 1'b0; + if(_zz_399_)begin + MULDIV1_xerBusPort_valid = 1'b1; + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_validOV = 1'bx; + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_validOV = 1'b0; + if(_zz_424_)begin + MULDIV1_xerBusPort_payload_validOV = 1'b1; + end + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_validCA = 1'bx; + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_validCA = 1'b0; + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_imm = (2'bxx); + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_imm = {_zz_277_,(1'b0)}; + end + end + + assign _zz_275_ = MULDIV_rs1[31 : 0]; + assign MULDIV1_stage_0_remainderShifted = {MULDIV_accumulator[31 : 0],_zz_275_[31]}; + assign MULDIV1_stage_0_remainderMinusDenominator = (MULDIV1_stage_0_remainderShifted - _zz_569_); + assign MULDIV1_stage_0_outRemainder = ((! MULDIV1_stage_0_remainderMinusDenominator[32]) ? _zz_570_ : _zz_571_); + assign MULDIV1_stage_0_outNumerator = _zz_572_[31:0]; + assign _zz_276_ = (memory_DECODER_stageables_15 ? MULDIV_accumulator[31 : 0] : MULDIV_rs1[31 : 0]); + assign _zz_277_ = (MULDIV_rs2 == 32'h0); + always @ (*) begin + _zz_278_ = 1'b0; + if(_zz_424_)begin + _zz_278_ = (memory_XER_SO || _zz_277_); + end else begin + _zz_278_ = memory_XER_SO; + end + end + + always @ (*) begin + case(memory_SRC_CR) + 2'b00 : begin + _zz_279_ = {(3'b010),_zz_278_}; + end + 2'b01 : begin + _zz_279_ = {(3'b001),_zz_278_}; + end + default : begin + _zz_279_ = {(3'b100),_zz_278_}; + end + endcase + end + + assign _zz_280_ = (execute_SRC2[31] && execute_DECODER_stageables_3); + assign _zz_281_ = (1'b0 || ((execute_DECODER_stageables_43 && execute_SRC1[31]) && execute_DECODER_stageables_29)); + always @ (*) begin + _zz_282_[32] = (execute_DECODER_stageables_29 && execute_SRC1[31]); + _zz_282_[31 : 0] = execute_SRC1; + end + + always @ (*) begin + _zz_283_ = 1'b0; + if(_zz_425_)begin + if(_zz_426_)begin + if(_zz_287_)begin + _zz_283_ = 1'b1; + end + end + end + if(_zz_427_)begin + if(_zz_428_)begin + if(_zz_290_)begin + _zz_283_ = 1'b1; + end + end + end + if(_zz_429_)begin + if(_zz_430_)begin + if(_zz_293_)begin + _zz_283_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_10))begin + _zz_283_ = 1'b0; + end + end + + always @ (*) begin + _zz_284_ = 1'b0; + if(_zz_425_)begin + if(_zz_426_)begin + if(_zz_288_)begin + _zz_284_ = 1'b1; + end + end + end + if(_zz_427_)begin + if(_zz_428_)begin + if(_zz_291_)begin + _zz_284_ = 1'b1; + end + end + end + if(_zz_429_)begin + if(_zz_430_)begin + if(_zz_294_)begin + _zz_284_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_47))begin + _zz_284_ = 1'b0; + end + end + + always @ (*) begin + _zz_285_ = 1'b0; + if((writeBack_arbitration_isValid && writeBack_DECODER_stageables_45))begin + if(((1'b0 || (! _zz_286_)) || (! 1'b1)))begin + if(_zz_289_)begin + _zz_285_ = 1'b1; + end + end + end + if((memory_arbitration_isValid && memory_DECODER_stageables_45))begin + if(((1'b0 || (! memory_DECODER_stageables_5)) || (! 1'b1)))begin + if(_zz_292_)begin + _zz_285_ = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_DECODER_stageables_45))begin + if(((1'b0 || (! execute_DECODER_stageables_25)) || (! 1'b1)))begin + if(_zz_295_)begin + _zz_285_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_50))begin + _zz_285_ = 1'b0; + end + end + + assign Hazards_writeBackWrites_valid = (_zz_102_ && writeBack_arbitration_isFiring); + assign Hazards_writeBackWrites_payload_address = writeBack_RT_ADDR; + assign Hazards_writeBackWrites_payload_data = _zz_121_; + assign Hazards_addr0Match = (Hazards_writeBackBuffer_payload_address == decode_R0_ADDR); + assign Hazards_addr1Match = (Hazards_writeBackBuffer_payload_address == decode_R1_ADDR); + assign Hazards_addr2Match = (Hazards_writeBackBuffer_payload_address == decode_R2_ADDR); + assign _zz_286_ = 1'b1; + assign _zz_287_ = (writeBack_RT_ADDR == decode_R0_ADDR); + assign _zz_288_ = (writeBack_RT_ADDR == decode_R1_ADDR); + assign _zz_289_ = (writeBack_RT_ADDR == decode_R2_ADDR); + assign _zz_290_ = (memory_RT_ADDR == decode_R0_ADDR); + assign _zz_291_ = (memory_RT_ADDR == decode_R1_ADDR); + assign _zz_292_ = (memory_RT_ADDR == decode_R2_ADDR); + assign _zz_293_ = (execute_RT_ADDR == decode_R0_ADDR); + assign _zz_294_ = (execute_RT_ADDR == decode_R1_ADDR); + assign _zz_295_ = (execute_RT_ADDR == decode_R2_ADDR); + always @ (*) begin + _zz_296_ = 1'b0; + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + if(! _zz_303_) begin + _zz_296_ = 1'b1; + end + end else begin + _zz_296_ = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_297_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_297_ = (_zz_309_ && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_298_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_298_ = (((execute_DECODER_stageables_54 && (execute_SPR_ID == 11'h001)) || _zz_308_) && (memory_XER_WRITE_validCA || memory_XER_WRITE_validOV)); + end + end + + always @ (*) begin + _zz_299_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_299_ = ((memory_DECODER_stageables_32 && (memory_SPR_ID == 11'h001)) && _zz_308_); + end + end + + always @ (*) begin + _zz_300_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_300_ = ((((((memory_SPR_ID == _zz_1580_) && memory_DECODER_stageables_32) && _zz_311_) || (((memory_SPR_ID == _zz_1581_) && memory_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCCTR))) || (((memory_SPR_ID == 11'h32f) && memory_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCTAR))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_301_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_301_ = (((memory_BRANCH_LINK && ((execute_SPR_ID == 11'h008) && (! execute_DECODER_stageables_32))) || (memory_BRANCH_DEC && ((execute_SPR_ID == 11'h009) && (! execute_DECODER_stageables_32)))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_302_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_302_ = (((memory_BRANCH_LINK && _zz_311_) || (memory_BRANCH_DEC && execute_BRANCH_DEC)) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_303_ = 1'b0; + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + _zz_303_ = (_zz_305_ && _zz_306_); + end + end + end + end + + always @ (*) begin + _zz_304_ = (4'b0000); + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + if(_zz_303_)begin + _zz_304_ = memory_CR_WRITE_imm[3 : 0]; + end + end + end + end + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + _zz_305_ = 1'b1; + end + default : begin + _zz_305_ = 1'b0; + end + endcase + end + + always @ (*) begin + _zz_306_ = 1'b0; + if((! (memory_DECODER_stageables_31 || memory_DECODER_stageables_43)))begin + _zz_306_ = _zz_307_; + end + end + + always @ (*) begin + case(memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_307_ = 1'b1; + end + default : begin + _zz_307_ = 1'b0; + end + endcase + end + + assign _zz_308_ = (execute_DECODER_stageables_1 == `Src3CtrlEnum_defaultEncoding_CA); + always @ (*) begin + _zz_309_ = 1'b0; + if(memory_DECODER_stageables_32)begin + _zz_309_ = _zz_310_; + end + end + + always @ (*) begin + case(_zz_444_) + 2'b10 : begin + _zz_310_ = 1'b1; + end + 2'b01 : begin + _zz_310_ = execute_DECODER_stageables_54; + end + default : begin + _zz_310_ = (execute_DECODER_stageables_54 && (execute_SPR_ID == memory_SPR_ID)); + end + endcase + end + + assign _zz_311_ = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCLR); + always @ (*) begin + _zz_312_ = 1'b0; + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + if(! _zz_319_) begin + _zz_312_ = 1'b1; + end + end else begin + _zz_312_ = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_313_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_313_ = (_zz_324_ && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_314_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_314_ = (((execute_DECODER_stageables_54 && (execute_SPR_ID == 11'h001)) || _zz_323_) && (writeBack_XER_WRITE_validCA || writeBack_XER_WRITE_validOV)); + end + end + + always @ (*) begin + _zz_315_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_315_ = ((writeBack_DECODER_stageables_32 && (writeBack_SPR_ID == 11'h001)) && _zz_323_); + end + end + + always @ (*) begin + _zz_316_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_316_ = ((((((writeBack_SPR_ID == 11'h008) && writeBack_DECODER_stageables_32) && _zz_326_) || (((writeBack_SPR_ID == 11'h009) && writeBack_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCCTR))) || (((writeBack_SPR_ID == 11'h32f) && writeBack_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCTAR))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_317_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_317_ = (((writeBack_BRANCH_LINK && ((execute_SPR_ID == 11'h008) && (! execute_DECODER_stageables_32))) || (writeBack_BRANCH_DEC && ((execute_SPR_ID == 11'h009) && (! execute_DECODER_stageables_32)))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_318_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_318_ = (((writeBack_BRANCH_LINK && _zz_326_) || (writeBack_BRANCH_DEC && execute_BRANCH_DEC)) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_319_ = 1'b0; + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + _zz_319_ = (_zz_321_ && _zz_322_); + end + end + end + end + + always @ (*) begin + _zz_320_ = (4'b0000); + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + if(_zz_319_)begin + _zz_320_ = writeBack_CR_WRITE_imm[3 : 0]; + end + end + end + end + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + _zz_321_ = 1'b1; + end + default : begin + _zz_321_ = 1'b0; + end + endcase + end + + always @ (*) begin + case(writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_322_ = 1'b1; + end + default : begin + _zz_322_ = 1'b0; + end + endcase + end + + assign _zz_323_ = (execute_DECODER_stageables_1 == `Src3CtrlEnum_defaultEncoding_CA); + always @ (*) begin + _zz_324_ = 1'b0; + if(writeBack_DECODER_stageables_32)begin + _zz_324_ = _zz_325_; + end + end + + always @ (*) begin + case(_zz_445_) + 2'b10 : begin + _zz_325_ = 1'b1; + end + 2'b01 : begin + _zz_325_ = execute_DECODER_stageables_54; + end + default : begin + _zz_325_ = (execute_DECODER_stageables_54 && (execute_SPR_ID == writeBack_SPR_ID)); + end + endcase + end + + assign _zz_326_ = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCLR); + always @ (*) begin + case(decode_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + decode_BranchPlugin_bc = 1'b1; + end + default : begin + decode_BranchPlugin_bc = 1'b0; + end + endcase + end + + assign decode_BranchPlugin_bi = decode_INSTRUCTION[20 : 16]; + assign decode_BranchPlugin_crbiField = decode_BranchPlugin_bi[4 : 2]; + assign decode_BranchPlugin_bo = decode_INSTRUCTION[25 : 21]; + assign decode_BranchPlugin_crbiRead = ((decode_BranchPlugin_bc && (! decode_BranchPlugin_bo[4])) && ((decode_DECODER_stageables_13 != `BranchCtrlEnum_defaultEncoding_BU) && (decode_DECODER_stageables_13 != `BranchCtrlEnum_defaultEncoding_NONE))); + always @ (*) begin + case(decode_BranchPlugin_crbiField) + 3'b000 : begin + decode_BranchPlugin_crFieldRd = {decode_BranchPlugin_crbiRead,7'h0}; + end + 3'b001 : begin + decode_BranchPlugin_crFieldRd = {{(1'b0),decode_BranchPlugin_crbiRead},6'h0}; + end + 3'b010 : begin + decode_BranchPlugin_crFieldRd = {{(2'b00),decode_BranchPlugin_crbiRead},5'h0}; + end + 3'b011 : begin + decode_BranchPlugin_crFieldRd = {{(3'b000),decode_BranchPlugin_crbiRead},(4'b0000)}; + end + 3'b100 : begin + decode_BranchPlugin_crFieldRd = {{(4'b0000),decode_BranchPlugin_crbiRead},(3'b000)}; + end + 3'b101 : begin + decode_BranchPlugin_crFieldRd = {{5'h0,decode_BranchPlugin_crbiRead},(2'b00)}; + end + 3'b110 : begin + decode_BranchPlugin_crFieldRd = {{6'h0,decode_BranchPlugin_crbiRead},(1'b0)}; + end + default : begin + decode_BranchPlugin_crFieldRd = {7'h0,decode_BranchPlugin_crbiRead}; + end + endcase + end + + always @ (*) begin + if(decode_BranchPlugin_crbiRead)begin + _zz_64_ = decode_BranchPlugin_crFieldRd; + end else begin + if(decode_DECODER_stageables_6)begin + _zz_64_ = 8'hff; + end else begin + _zz_64_ = 8'h0; + end + end + end + + assign execute_BranchPlugin_ctrOne = (execute_BranchPlugin_CTR == 32'h00000001); + always @ (*) begin + case(execute_SPR_ID) + 11'b00000001001 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_CTR; + end + 11'b00000001000 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_LR; + end + 11'b01100101111 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_TAR; + end + default : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_CR; + end + endcase + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000010 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b00000001001 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b00000001000 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b01100101111 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + default : begin + execute_BranchPlugin_sprReadValid = 1'b0; + end + endcase + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000010 : begin + execute_BranchPlugin_crReadValid = execute_DECODER_stageables_54; + end + default : begin + execute_BranchPlugin_crReadValid = 1'b0; + end + endcase + end + + assign sprReadBU_valid = execute_BranchPlugin_sprReadValid; + assign sprReadBU_payload_data = execute_BranchPlugin_sprReadData; + assign execute_BranchPlugin_crBusPort_valid = ((writeBack_RegFilePlugin_crBusPort_valid || _zz_272_) || MULDIV1_crBusPort_valid); + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_op = writeBack_RegFilePlugin_crBusPort_payload_op; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_op = _zz_273_; + end else begin + execute_BranchPlugin_crBusPort_op = MULDIV1_crBusPort_payload_op; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_ba = writeBack_RegFilePlugin_crBusPort_payload_ba; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_ba = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_ba = MULDIV1_crBusPort_payload_ba; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_bb = writeBack_RegFilePlugin_crBusPort_payload_bb; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_bb = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_bb = MULDIV1_crBusPort_payload_bb; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_bt = writeBack_RegFilePlugin_crBusPort_payload_bt; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_bt = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_bt = MULDIV1_crBusPort_payload_bt; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_imm = writeBack_RegFilePlugin_crBusPort_payload_imm; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_imm = _zz_274_; + end else begin + execute_BranchPlugin_crBusPort_imm = MULDIV1_crBusPort_payload_imm; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_fxm = writeBack_RegFilePlugin_crBusPort_payload_fxm; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_fxm = 8'h0; + end else begin + execute_BranchPlugin_crBusPort_fxm = MULDIV1_crBusPort_payload_fxm; + end + end + end + + always @ (*) begin + case(_zz_446_) + 3'b000 : begin + _zz_327_ = execute_BranchPlugin_CR[31 : 28]; + end + 3'b001 : begin + _zz_327_ = execute_BranchPlugin_CR[27 : 24]; + end + 3'b010 : begin + _zz_327_ = execute_BranchPlugin_CR[23 : 20]; + end + 3'b011 : begin + _zz_327_ = execute_BranchPlugin_CR[19 : 16]; + end + 3'b100 : begin + _zz_327_ = execute_BranchPlugin_CR[15 : 12]; + end + 3'b101 : begin + _zz_327_ = execute_BranchPlugin_CR[11 : 8]; + end + 3'b110 : begin + _zz_327_ = execute_BranchPlugin_CR[7 : 4]; + end + default : begin + _zz_327_ = execute_BranchPlugin_CR[3 : 0]; + end + endcase + end + + assign _zz_328_ = execute_BranchPlugin_crBusPort_imm[3 : 0]; + assign _zz_329_ = execute_INSTRUCTION[25]; + always @ (*) begin + _zz_330_[5] = _zz_329_; + _zz_330_[4] = _zz_329_; + _zz_330_[3] = _zz_329_; + _zz_330_[2] = _zz_329_; + _zz_330_[1] = _zz_329_; + _zz_330_[0] = _zz_329_; + end + + assign execute_BranchPlugin_li = {{_zz_330_,execute_INSTRUCTION[25 : 2]},(2'b00)}; + assign _zz_331_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_332_[15] = _zz_331_; + _zz_332_[14] = _zz_331_; + _zz_332_[13] = _zz_331_; + _zz_332_[12] = _zz_331_; + _zz_332_[11] = _zz_331_; + _zz_332_[10] = _zz_331_; + _zz_332_[9] = _zz_331_; + _zz_332_[8] = _zz_331_; + _zz_332_[7] = _zz_331_; + _zz_332_[6] = _zz_331_; + _zz_332_[5] = _zz_331_; + _zz_332_[4] = _zz_331_; + _zz_332_[3] = _zz_331_; + _zz_332_[2] = _zz_331_; + _zz_332_[1] = _zz_331_; + _zz_332_[0] = _zz_331_; + end + + assign execute_BranchPlugin_bd = {{_zz_332_,execute_INSTRUCTION[15 : 2]},(2'b00)}; + assign _zz_333_ = (! execute_INSTRUCTION[1]); + always @ (*) begin + execute_BranchPlugin_aaMask[31] = _zz_333_; + execute_BranchPlugin_aaMask[30] = _zz_333_; + execute_BranchPlugin_aaMask[29] = _zz_333_; + execute_BranchPlugin_aaMask[28] = _zz_333_; + execute_BranchPlugin_aaMask[27] = _zz_333_; + execute_BranchPlugin_aaMask[26] = _zz_333_; + execute_BranchPlugin_aaMask[25] = _zz_333_; + execute_BranchPlugin_aaMask[24] = _zz_333_; + execute_BranchPlugin_aaMask[23] = _zz_333_; + execute_BranchPlugin_aaMask[22] = _zz_333_; + execute_BranchPlugin_aaMask[21] = _zz_333_; + execute_BranchPlugin_aaMask[20] = _zz_333_; + execute_BranchPlugin_aaMask[19] = _zz_333_; + execute_BranchPlugin_aaMask[18] = _zz_333_; + execute_BranchPlugin_aaMask[17] = _zz_333_; + execute_BranchPlugin_aaMask[16] = _zz_333_; + execute_BranchPlugin_aaMask[15] = _zz_333_; + execute_BranchPlugin_aaMask[14] = _zz_333_; + execute_BranchPlugin_aaMask[13] = _zz_333_; + execute_BranchPlugin_aaMask[12] = _zz_333_; + execute_BranchPlugin_aaMask[11] = _zz_333_; + execute_BranchPlugin_aaMask[10] = _zz_333_; + execute_BranchPlugin_aaMask[9] = _zz_333_; + execute_BranchPlugin_aaMask[8] = _zz_333_; + execute_BranchPlugin_aaMask[7] = _zz_333_; + execute_BranchPlugin_aaMask[6] = _zz_333_; + execute_BranchPlugin_aaMask[5] = _zz_333_; + execute_BranchPlugin_aaMask[4] = _zz_333_; + execute_BranchPlugin_aaMask[3] = _zz_333_; + execute_BranchPlugin_aaMask[2] = _zz_333_; + execute_BranchPlugin_aaMask[1] = _zz_333_; + execute_BranchPlugin_aaMask[0] = _zz_333_; + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BCLR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_LR; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_CTR; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_TAR; + end + default : begin + execute_BranchPlugin_branch_tgt0 = 32'h0; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BU : begin + execute_BranchPlugin_branch_tgt1 = (execute_PC & execute_BranchPlugin_aaMask); + end + `BranchCtrlEnum_defaultEncoding_BC : begin + execute_BranchPlugin_branch_tgt1 = (execute_PC & execute_BranchPlugin_aaMask); + end + default : begin + execute_BranchPlugin_branch_tgt1 = 32'h0; + end + endcase + end + + assign execute_BranchPlugin_use_li = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BU); + assign execute_BranchPlugin_branch_tgt2 = (execute_BranchPlugin_use_li ? _zz_606_ : _zz_607_); + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BU : begin + execute_BranchPlugin_branchAdder = _zz_608_; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + execute_BranchPlugin_branchAdder = _zz_609_; + end + default : begin + execute_BranchPlugin_branchAdder = execute_BranchPlugin_branch_tgt0; + end + endcase + end + + assign execute_BranchPlugin_opbi = execute_INSTRUCTION[20 : 16]; + assign execute_BranchPlugin_crbiField = execute_BranchPlugin_opbi[4 : 2]; + assign execute_BranchPlugin_crbiBit = execute_BranchPlugin_opbi[1 : 0]; + assign execute_BranchPlugin_bo = execute_INSTRUCTION[25 : 21]; + assign execute_BranchPlugin_crBypassPort_valid = (_zz_303_ || _zz_319_); + always @ (*) begin + if(_zz_303_)begin + execute_BranchPlugin_crBypassPort_field = _zz_304_; + end else begin + execute_BranchPlugin_crBypassPort_field = _zz_320_; + end + end + + always @ (*) begin + if(execute_BranchPlugin_crBypassPort_valid)begin + execute_BranchPlugin_crbi = execute_BranchPlugin_crBypassPort_field[_zz_610_]; + end else begin + case(execute_BranchPlugin_crbiField) + 3'b000 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_611_]; + end + 3'b001 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_614_]; + end + 3'b010 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_617_]; + end + 3'b011 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_620_]; + end + 3'b100 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_623_]; + end + 3'b101 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_626_]; + end + 3'b110 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_629_]; + end + default : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_632_]; + end + endcase + end + end + + assign execute_BranchPlugin_ctrOK = (execute_BranchPlugin_bo[2] || ((! execute_BranchPlugin_ctrOne) ^ execute_BranchPlugin_bo[1])); + assign execute_BranchPlugin_condOK = (execute_BranchPlugin_bo[4] || (! (execute_BranchPlugin_crbi ^ execute_BranchPlugin_bo[3]))); + assign execute_BranchPlugin_lk = execute_INSTRUCTION[0]; + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_334_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_334_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_334_ = execute_BranchPlugin_condOK; + end + default : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_335_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_335_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_335_ = 1'b0; + end + default : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_336_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_336_ = execute_BranchPlugin_lk; + end + default : begin + _zz_336_ = execute_BranchPlugin_lk; + end + endcase + end + + assign memory_BranchPlugin_predictionMissmatch = ((IBusCachedPlugin_fetchPrediction_cmd_hadBranch != memory_BRANCH_DO) || (memory_BRANCH_DO && memory_TARGET_MISSMATCH2)); + assign IBusCachedPlugin_fetchPrediction_rsp_wasRight = (! memory_BranchPlugin_predictionMissmatch); + assign IBusCachedPlugin_fetchPrediction_rsp_finalPc = memory_BRANCH_CALC; + assign IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord = memory_PC; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BranchPlugin_predictionMissmatch) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = (memory_BRANCH_DO ? memory_BRANCH_CALC : memory_NEXT_PC2); + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && memory_BRANCH_CALC[1]); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + always @ (*) begin + SPRPlugin_msr_ir = MSR_IR; + if(_zz_410_)begin + SPRPlugin_msr_ir = 1'b0; + end + if(_zz_411_)begin + SPRPlugin_msr_ir = 1'b0; + end + if(_zz_413_)begin + SPRPlugin_msr_ir = SPRPlugin_srr1[5]; + end + end + + assign SPRPlugin_msr_dr = MSR_DR; + assign SPRPlugin_msr_pr = MSR_PR; + assign SPRPlugin_incTB = 1'b1; + always @ (*) begin + SPRPlugin_intDecTkn = 1'b0; + if(_zz_408_)begin + SPRPlugin_intDecTkn = (SPRPlugin_intType == `ExcpEnum_defaultEncoding_DEC); + end + end + + assign _zz_338_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_339_ = _zz_634_[0]; + assign _zz_340_ = (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_codePPC : decodeExceptionPort_payload_codePPC); + assign _zz_337_ = _zz_340_; + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_407_)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(SPRPlugin_selfException_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_341_ = 1'b0; + end + default : begin + _zz_341_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_342_ = 1'b0; + end + default : begin + _zz_342_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_343_ = 1'b0; + end + default : begin + _zz_343_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_344_ = 1'b0; + end + default : begin + _zz_344_ = 1'b1; + end + endcase + end + + assign SPRPlugin_exceptionPendings_0 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign SPRPlugin_exceptionPendings_1 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign SPRPlugin_exceptionPendings_2 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign SPRPlugin_exceptionPendings_3 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign SPRPlugin_pipelineLiberator_active = ((SPRPlugin_interrupt_valid && SPRPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + SPRPlugin_pipelineLiberator_done = SPRPlugin_pipelineLiberator_pcValids_2; + if(({SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + SPRPlugin_pipelineLiberator_done = 1'b0; + end + if(SPRPlugin_hadException)begin + SPRPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign SPRPlugin_exception = (SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack && SPRPlugin_allowException); + always @ (*) begin + SPRPlugin_interruptJump = 1'b0; + if(_zz_437_)begin + SPRPlugin_interruptJump = ((SPRPlugin_interrupt_valid && SPRPlugin_pipelineLiberator_done) && SPRPlugin_allowInterrupts); + end + end + + always @ (*) begin + SPRPlugin_intType = `ExcpEnum_defaultEncoding_NONE; + if(_zz_408_)begin + if(SPRPlugin_interruptJump)begin + case(SPRPlugin_interrupt_code) + 4'b1001 : begin + SPRPlugin_intType = `ExcpEnum_defaultEncoding_DEC; + end + default : begin + end + endcase + end else begin + SPRPlugin_intType = SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC; + end + end + end + + always @ (*) begin + SPRPlugin_intSRR0 = 32'h0; + if(_zz_408_)begin + if(SPRPlugin_interruptJump)begin + SPRPlugin_intSRR0 = writeBack_PC; + end else begin + SPRPlugin_intSRR0 = SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + end + + always @ (*) begin + case(SPRPlugin_intType) + `ExcpEnum_defaultEncoding_SR : begin + _zz_345_ = 32'h00000100; + end + `ExcpEnum_defaultEncoding_MC : begin + _zz_345_ = 32'h00000200; + end + `ExcpEnum_defaultEncoding_EXT : begin + _zz_345_ = 32'h00000500; + end + `ExcpEnum_defaultEncoding_DEC : begin + _zz_345_ = 32'h00000900; + end + `ExcpEnum_defaultEncoding_PM : begin + _zz_345_ = 32'h00000f00; + end + `ExcpEnum_defaultEncoding_DSI : begin + _zz_345_ = 32'h00000300; + end + `ExcpEnum_defaultEncoding_DSI_PROT : begin + _zz_345_ = 32'h00000300; + end + `ExcpEnum_defaultEncoding_ISI : begin + _zz_345_ = 32'h00000400; + end + `ExcpEnum_defaultEncoding_ISI_PROT : begin + _zz_345_ = 32'h00000400; + end + `ExcpEnum_defaultEncoding_ALG : begin + _zz_345_ = 32'h00000600; + end + `ExcpEnum_defaultEncoding_PGM_ILL : begin + _zz_345_ = 32'h00000700; + end + `ExcpEnum_defaultEncoding_PGM_PRV : begin + _zz_345_ = 32'h00000700; + end + `ExcpEnum_defaultEncoding_FP : begin + _zz_345_ = 32'h00000800; + end + `ExcpEnum_defaultEncoding_TR : begin + _zz_345_ = 32'h00000d00; + end + `ExcpEnum_defaultEncoding_VEC : begin + _zz_345_ = 32'h00000f20; + end + `ExcpEnum_defaultEncoding_VSX : begin + _zz_345_ = 32'h00000f40; + end + `ExcpEnum_defaultEncoding_FAC : begin + _zz_345_ = 32'h00000f60; + end + default : begin + _zz_345_ = 32'h0; + end + endcase + end + + always @ (*) begin + if(MSR_LE)begin + _zz_63_ = `EndianEnum_defaultEncoding_LE; + end else begin + _zz_63_ = `EndianEnum_defaultEncoding_BE; + end + end + + assign execute_SPRPLUGIN_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000001 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000011010 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000011011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010010 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00100001100 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010110 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00100000011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + default : begin + execute_SPRPLUGIN_sprHere = 1'b0; + end + endcase + end + + always @ (*) begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + if((! execute_SPRPLUGIN_sprHere))begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_arbitration_isValid)begin + if((execute_DECODER_stageables_30 && SPRPlugin_msr_pr))begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + end + end + if(execute_SPRPLUGIN_SPR_1025)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_26)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_27)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_19)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_259)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_18)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_268)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_22)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_privViolation)begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_DECODER_stageables_40)))begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_selfException_valid = 1'b0; + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + SPRPlugin_selfException_payload_code = (4'bxxxx); + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_payload_code = (4'b0010); + end + end + + assign _zz_346_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_347_[15] = _zz_346_; + _zz_347_[14] = _zz_346_; + _zz_347_[13] = _zz_346_; + _zz_347_[12] = _zz_346_; + _zz_347_[11] = _zz_346_; + _zz_347_[10] = _zz_346_; + _zz_347_[9] = _zz_346_; + _zz_347_[8] = _zz_346_; + _zz_347_[7] = _zz_346_; + _zz_347_[6] = _zz_346_; + _zz_347_[5] = _zz_346_; + _zz_347_[4] = _zz_346_; + _zz_347_[3] = _zz_346_; + _zz_347_[2] = _zz_346_; + _zz_347_[1] = _zz_346_; + _zz_347_[0] = _zz_346_; + end + + assign execute_SPRPLUGIN_si = {_zz_347_,execute_INSTRUCTION[15 : 0]}; + assign execute_SPRPLUGIN_tmask = execute_INSTRUCTION[25 : 21]; + always @ (*) begin + execute_SPRPLUGIN_trap = 1'b0; + if(execute_arbitration_isValid)begin + if(_zz_394_)begin + if(($signed(_zz_636_) < $signed(_zz_637_)))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[4]; + end else begin + if(($signed(_zz_638_) < $signed(_zz_639_)))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[3]; + end else begin + if((execute_SRC1 == execute_SRC2))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[2]; + end else begin + if((execute_SRC1 < execute_SRC2))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[1]; + end else begin + if((execute_SRC2 < execute_SRC1))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[0]; + end + end + end + end + end + end + end + end + + assign execute_SPRPLUGIN_opExcp_codePPC = `ExcpEnum_defaultEncoding_NONE; + assign execute_SPRPLUGIN_opExcp_imm = 7'h0; + assign execute_SPRPLUGIN_opExcp_badAddr = execute_PC; + always @ (*) begin + _zz_348_ = 1'b0; + if(($signed(_zz_640_) < $signed(_zz_641_)))begin + _zz_348_ = execute_SPRPLUGIN_tmask[4]; + end else begin + if(($signed(_zz_642_) < $signed(_zz_643_)))begin + _zz_348_ = execute_SPRPLUGIN_tmask[3]; + end else begin + if((execute_SRC1 == execute_SPRPLUGIN_si))begin + _zz_348_ = execute_SPRPLUGIN_tmask[2]; + end else begin + if((execute_SRC1 < execute_SPRPLUGIN_si))begin + _zz_348_ = execute_SPRPLUGIN_tmask[1]; + end else begin + if((execute_SPRPLUGIN_si < execute_SRC1))begin + _zz_348_ = execute_SPRPLUGIN_tmask[0]; + end + end + end + end + end + end + + assign execute_SPRPLUGIN_readToWriteData = execute_SPRPLUGIN_readData; + assign execute_SPRPLUGIN_sprg3read = 1'b0; + assign execute_SPRPLUGIN_privViolation = ((execute_SPRPLUGIN_sprHere && MSR_PR) && (! execute_SPRPLUGIN_sprg3read)); + assign execute_SPRPLUGIN_readInstruction = ((((execute_arbitration_isValid && execute_SPRPLUGIN_sprHere) && execute_DECODER_stageables_54) && execute_DECODER_stageables_40) && (! execute_SPRPLUGIN_privViolation)); + assign execute_SPRPLUGIN_readEnable = ((execute_SPRPLUGIN_readInstruction && (! execute_SPRPLUGIN_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_SPRPLUGIN_writeInstruction = ((((execute_arbitration_isValid && execute_SPRPLUGIN_sprHere) && execute_DECODER_stageables_32) && execute_DECODER_stageables_40) && (! execute_SPRPLUGIN_privViolation)); + assign execute_SPRPLUGIN_writeEnable = ((execute_SPRPLUGIN_writeInstruction && (! execute_SPRPLUGIN_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_SPRPLUGIN_SPRAddress = {(1'b0),execute_SPR_ID[9 : 0]}; + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MFMSR))begin + execute_SPRPLUGIN_SPRAddress = 11'h401; + end else begin + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MTMSR))begin + execute_SPRPLUGIN_SPRAddress = 11'h401; + end + end + end + + assign contextSwitching = SPRPlugin_jumpInterface_valid; + assign _zz_58_ = decode_DECODER_stageables_44; + assign _zz_56_ = _zz_109_; + assign _zz_99_ = decode_to_execute_DECODER_stageables_44; + assign _zz_55_ = decode_DECODER_stageables_49; + assign _zz_61_ = execute_DECODER_stageables_49; + assign _zz_52_ = memory_DECODER_stageables_49; + assign _zz_53_ = _zz_108_; + assign _zz_62_ = decode_to_execute_DECODER_stageables_49; + assign _zz_50_ = execute_to_memory_DECODER_stageables_49; + assign _zz_59_ = memory_to_writeBack_DECODER_stageables_49; + assign _zz_49_ = decode_DECODER_stageables_13; + assign _zz_65_ = _zz_115_; + assign _zz_67_ = decode_to_execute_DECODER_stageables_13; + assign _zz_47_ = decode_DECODER_stageables_20; + assign _zz_45_ = _zz_112_; + assign _zz_77_ = decode_to_execute_DECODER_stageables_20; + assign _zz_44_ = decode_DECODER_stageables_16; + assign _zz_42_ = _zz_114_; + assign _zz_98_ = decode_to_execute_DECODER_stageables_16; + assign _zz_41_ = decode_DECODER_stageables_0; + assign _zz_39_ = _zz_120_; + assign _zz_82_ = decode_to_execute_DECODER_stageables_0; + assign _zz_38_ = execute_CR_WRITE_op; + assign _zz_35_ = memory_CR_WRITE_op; + assign _zz_36_ = _zz_76_; + assign _zz_66_ = execute_to_memory_CR_WRITE_op; + assign _zz_101_ = memory_to_writeBack_CR_WRITE_op; + assign _zz_33_ = decode_DECODER_stageables_19; + assign _zz_31_ = _zz_113_; + assign _zz_100_ = decode_to_execute_DECODER_stageables_19; + assign _zz_30_ = decode_MSR_ENDIAN; + assign _zz_28_ = execute_MSR_ENDIAN; + assign _zz_26_ = memory_MSR_ENDIAN; + assign _zz_129_ = _zz_63_; + assign _zz_126_ = decode_to_execute_MSR_ENDIAN; + assign _zz_24_ = execute_to_memory_MSR_ENDIAN; + assign _zz_123_ = memory_to_writeBack_MSR_ENDIAN; + assign _zz_23_ = decode_DECODER_stageables_51; + assign _zz_21_ = _zz_107_; + assign _zz_78_ = decode_to_execute_DECODER_stageables_51; + assign _zz_20_ = decode_DECODER_stageables_7; + assign _zz_17_ = execute_DATA_SIZE; + assign _zz_15_ = memory_DECODER_stageables_7; + assign _zz_18_ = _zz_118_; + assign _zz_125_ = decode_to_execute_DECODER_stageables_7; + assign _zz_13_ = execute_to_memory_DECODER_stageables_7; + assign _zz_122_ = memory_to_writeBack_DECODER_stageables_7; + assign _zz_12_ = decode_DECODER_stageables_1; + assign _zz_10_ = _zz_119_; + assign _zz_70_ = decode_to_execute_DECODER_stageables_1; + assign _zz_9_ = decode_DECODER_stageables_8; + assign _zz_7_ = _zz_117_; + assign _zz_81_ = decode_to_execute_DECODER_stageables_8; + assign _zz_6_ = decode_DECODER_stageables_26; + assign _zz_105_ = _zz_111_; + assign _zz_71_ = decode_to_execute_DECODER_stageables_26; + assign _zz_4_ = decode_DECODER_stageables_38; + assign _zz_106_ = _zz_110_; + assign _zz_74_ = decode_to_execute_DECODER_stageables_38; + assign _zz_2_ = decode_DECODER_stageables_12; + assign _zz_104_ = _zz_116_; + assign _zz_80_ = decode_to_execute_DECODER_stageables_12; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_349_ = {{(1'b0),decode_INSTRUCTION[15 : 11]},decode_INSTRUCTION[20 : 16]}; + if((decode_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MFMSR))begin + _zz_349_ = 11'h401; + end else begin + if((decode_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MTMSR))begin + _zz_349_ = 11'h401; + end + end + end + + always @ (*) begin + _zz_350_ = 32'h0; + if(execute_SPRPLUGIN_SPR_1025)begin + _zz_350_[23 : 23] = MSR_VSX; + _zz_350_[8 : 8] = MSR_FE1; + _zz_350_[11 : 11] = MSR_FE0; + _zz_350_[2 : 2] = MSR_PMM; + _zz_350_[5 : 5] = MSR_IR; + _zz_350_[14 : 14] = MSR_PR; + _zz_350_[13 : 13] = MSR_FP; + _zz_350_[4 : 4] = MSR_DR; + _zz_350_[25 : 25] = MSR_VEC; + _zz_350_[1 : 1] = MSR_RI; + _zz_350_[12 : 12] = MSR_ME; + _zz_350_[15 : 15] = MSR_EE; + _zz_350_[0 : 0] = MSR_LE; + end + end + + always @ (*) begin + _zz_351_ = 32'h0; + if(execute_SPRPLUGIN_SPR_26)begin + _zz_351_[31 : 0] = SPRPlugin_srr0; + end + end + + always @ (*) begin + _zz_352_ = 32'h0; + if(execute_SPRPLUGIN_SPR_27)begin + _zz_352_[31 : 0] = SPRPlugin_srr1; + end + end + + always @ (*) begin + _zz_353_ = 32'h0; + if(execute_SPRPLUGIN_SPR_19)begin + _zz_353_[31 : 0] = SPRPlugin_dar; + end + end + + always @ (*) begin + _zz_354_ = 32'h0; + if(execute_SPRPLUGIN_SPR_259)begin + _zz_354_[31 : 0] = SPRPlugin_sprg3; + end + end + + always @ (*) begin + _zz_355_ = 32'h0; + if(execute_SPRPLUGIN_SPR_18)begin + _zz_355_[31 : 0] = SPRPlugin_dsisr; + end + end + + always @ (*) begin + _zz_356_ = 32'h0; + if(execute_SPRPLUGIN_SPR_268)begin + _zz_356_[31 : 0] = SPRPlugin_tb; + end + end + + always @ (*) begin + _zz_357_ = 32'h0; + if(execute_SPRPLUGIN_SPR_22)begin + _zz_357_[31 : 0] = SPRPlugin_dec; + end + end + + assign execute_SPRPLUGIN_readData = (((_zz_350_ | _zz_351_) | (_zz_352_ | _zz_353_)) | ((_zz_354_ | _zz_355_) | (_zz_356_ | _zz_357_))); + assign iBusWB_ADR = {_zz_657_,_zz_358_}; + assign iBusWB_CTI = ((_zz_358_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWB_BTE = (2'b00); + assign iBusWB_SEL = (4'b1111); + assign iBusWB_WE = 1'b0; + assign iBusWB_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWB_CYC = 1'b0; + if(_zz_438_)begin + iBusWB_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWB_STB = 1'b0; + if(_zz_438_)begin + iBusWB_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWB_ACK); + assign iBus_rsp_valid = _zz_359_; + assign iBus_rsp_payload_data = iBusWB_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_365_ = (dBus_cmd_payload_length != (3'b000)); + assign _zz_361_ = dBus_cmd_valid; + assign _zz_363_ = dBus_cmd_payload_wr; + assign _zz_364_ = (_zz_360_ == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_362_ && (_zz_363_ || _zz_364_)); + assign dBusWB_ADR = ((_zz_365_ ? {{dBus_cmd_payload_address[31 : 5],_zz_360_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); + assign dBusWB_CTI = (_zz_365_ ? (_zz_364_ ? (3'b111) : (3'b010)) : (3'b000)); + assign dBusWB_BTE = (2'b00); + assign dBusWB_SEL = (_zz_363_ ? dBus_cmd_payload_mask : (4'b1111)); + assign dBusWB_WE = _zz_363_; + assign dBusWB_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_362_ = (_zz_361_ && dBusWB_ACK); + assign dBusWB_CYC = _zz_361_; + assign dBusWB_STB = _zz_361_; + assign dBus_rsp_valid = _zz_366_; + assign dBus_rsp_payload_data = dBusWB_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_140_ <= 1'b0; + _zz_143_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_147_; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1__io_mem_cmd_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_148_; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_241_ <= 1'b1; + ALU2_XER <= 32'h0; + MULDIV1_counter_value <= 6'h0; + Hazards_writeBackBuffer_valid <= 1'b0; + execute_BranchPlugin_CR <= 32'h0; + execute_BranchPlugin_CTR <= 32'h0; + execute_BranchPlugin_LR <= 32'h0; + execute_BranchPlugin_TAR <= 32'h0; + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + MSR_LE <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + SPRPlugin_interrupt_valid <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + SPRPlugin_hadException <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + _zz_358_ <= (3'b000); + _zz_359_ <= 1'b0; + _zz_360_ <= (3'b000); + _zz_366_ <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_140_ <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_140_ <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_143_ <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_143_ <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(_zz_388_)begin + dataCache_1__io_mem_cmd_m2sPipe_rValid <= dataCache_1__io_mem_cmd_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_241_ <= 1'b0; + ALU2_XER[31 : 29] <= ALU2_XER[31 : 29]; + if(_zz_245_)begin + if(_zz_242_)begin + ALU2_XER[30] <= _zz_244_[1]; + ALU2_XER[31] <= (ALU2_XER[31] || _zz_244_[1]); + end + if(_zz_243_)begin + ALU2_XER[29] <= _zz_244_[0]; + end + end + if(writeBack_RegFilePlugin_sprWriteXERPort_valid)begin + ALU2_XER <= writeBack_RegFilePlugin_sprWriteXERPort_payload_data; + end + MULDIV1_counter_value <= MULDIV1_counter_valueNext; + Hazards_writeBackBuffer_valid <= Hazards_writeBackWrites_valid; + if(writeBack_RegFilePlugin_sprWriteCLTPort_valid)begin + case(writeBack_RegFilePlugin_sprWriteCLTPort_payload_id) + 10'b0000001001 : begin + execute_BranchPlugin_CTR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + 10'b0000001000 : begin + execute_BranchPlugin_LR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + 10'b1100101111 : begin + execute_BranchPlugin_TAR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + default : begin + end + endcase + end + if(execute_BranchPlugin_crBusPort_valid)begin + case(execute_BranchPlugin_crBusPort_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_AND_1 : begin + execute_BranchPlugin_CR[_zz_582_] <= (execute_BranchPlugin_CR[_zz_583_] && execute_BranchPlugin_CR[_zz_584_]); + end + `CRBusCmdEnum_defaultEncoding_OR_1 : begin + execute_BranchPlugin_CR[_zz_585_] <= (execute_BranchPlugin_CR[_zz_586_] || execute_BranchPlugin_CR[_zz_587_]); + end + `CRBusCmdEnum_defaultEncoding_XOR_1 : begin + execute_BranchPlugin_CR[_zz_588_] <= (execute_BranchPlugin_CR[_zz_589_] ^ execute_BranchPlugin_CR[_zz_590_]); + end + `CRBusCmdEnum_defaultEncoding_NAND_1 : begin + execute_BranchPlugin_CR[_zz_591_] <= (! (execute_BranchPlugin_CR[_zz_592_] && execute_BranchPlugin_CR[_zz_593_])); + end + `CRBusCmdEnum_defaultEncoding_NOR_1 : begin + execute_BranchPlugin_CR[_zz_594_] <= (! (execute_BranchPlugin_CR[_zz_595_] || execute_BranchPlugin_CR[_zz_596_])); + end + `CRBusCmdEnum_defaultEncoding_EQV : begin + execute_BranchPlugin_CR[_zz_597_] <= (! (execute_BranchPlugin_CR[_zz_598_] ^ execute_BranchPlugin_CR[_zz_599_])); + end + `CRBusCmdEnum_defaultEncoding_ANDC : begin + execute_BranchPlugin_CR[_zz_600_] <= (execute_BranchPlugin_CR[_zz_601_] && (! execute_BranchPlugin_CR[_zz_602_])); + end + `CRBusCmdEnum_defaultEncoding_ORC : begin + execute_BranchPlugin_CR[_zz_603_] <= (execute_BranchPlugin_CR[_zz_604_] || (! execute_BranchPlugin_CR[_zz_605_])); + end + `CRBusCmdEnum_defaultEncoding_MCRF : begin + case(execute_BranchPlugin_crBusPort_bt) + 5'b00000 : begin + execute_BranchPlugin_CR[31 : 28] <= _zz_327_; + end + 5'b00001 : begin + execute_BranchPlugin_CR[27 : 24] <= _zz_327_; + end + 5'b00010 : begin + execute_BranchPlugin_CR[23 : 20] <= _zz_327_; + end + 5'b00011 : begin + execute_BranchPlugin_CR[19 : 16] <= _zz_327_; + end + 5'b00100 : begin + execute_BranchPlugin_CR[15 : 12] <= _zz_327_; + end + 5'b00101 : begin + execute_BranchPlugin_CR[11 : 8] <= _zz_327_; + end + 5'b00110 : begin + execute_BranchPlugin_CR[7 : 4] <= _zz_327_; + end + 5'b00111 : begin + execute_BranchPlugin_CR[3 : 0] <= _zz_327_; + end + default : begin + end + endcase + end + `CRBusCmdEnum_defaultEncoding_MCRXRX : begin + case(execute_BranchPlugin_crBusPort_bt) + 5'b00000 : begin + execute_BranchPlugin_CR[31 : 28] <= _zz_328_; + end + 5'b00001 : begin + execute_BranchPlugin_CR[27 : 24] <= _zz_328_; + end + 5'b00010 : begin + execute_BranchPlugin_CR[23 : 20] <= _zz_328_; + end + 5'b00011 : begin + execute_BranchPlugin_CR[19 : 16] <= _zz_328_; + end + 5'b00100 : begin + execute_BranchPlugin_CR[15 : 12] <= _zz_328_; + end + 5'b00101 : begin + execute_BranchPlugin_CR[11 : 8] <= _zz_328_; + end + 5'b00110 : begin + execute_BranchPlugin_CR[7 : 4] <= _zz_328_; + end + 5'b00111 : begin + execute_BranchPlugin_CR[3 : 0] <= _zz_328_; + end + default : begin + end + endcase + end + `CRBusCmdEnum_defaultEncoding_MTCRF : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[31 : 28]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[27 : 24]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[23 : 20]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[19 : 16]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[15 : 12]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[11 : 8]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[7 : 4]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_MTOCRF : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[31 : 28]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[27 : 24]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[23 : 20]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[19 : 16]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[15 : 12]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[11 : 8]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[7 : 4]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_DEC : begin + execute_BranchPlugin_CTR <= (execute_BranchPlugin_CTR - 32'h00000001); + end + `CRBusCmdEnum_defaultEncoding_LNK : begin + execute_BranchPlugin_LR <= execute_BranchPlugin_crBusPort_imm; + end + `CRBusCmdEnum_defaultEncoding_DECLNK : begin + execute_BranchPlugin_CTR <= (execute_BranchPlugin_CTR - 32'h00000001); + execute_BranchPlugin_LR <= execute_BranchPlugin_crBusPort_imm; + end + default : begin + end + endcase + end + if((! decode_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= SPRPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (SPRPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= SPRPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (SPRPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= SPRPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (SPRPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + SPRPlugin_interrupt_valid <= 1'b0; + if(_zz_439_)begin + if(_zz_440_)begin + SPRPlugin_interrupt_valid <= 1'b1; + end + end + if(SPRPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_1 <= SPRPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_2 <= SPRPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! SPRPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + SPRPlugin_hadException <= SPRPlugin_exception; + if(_zz_437_)begin + if(SPRPlugin_interruptJump)begin + SPRPlugin_interrupt_valid <= 1'b0; + end + end + if(_zz_408_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_410_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_411_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_413_)begin + MSR_VEC <= SPRPlugin_srr1[25]; + MSR_VSX <= SPRPlugin_srr1[23]; + MSR_EE <= SPRPlugin_srr1[15]; + MSR_PR <= SPRPlugin_srr1[14]; + MSR_FP <= SPRPlugin_srr1[13]; + MSR_ME <= SPRPlugin_srr1[12]; + MSR_FE0 <= SPRPlugin_srr1[11]; + MSR_FE1 <= SPRPlugin_srr1[8]; + MSR_IR <= SPRPlugin_srr1[5]; + MSR_DR <= SPRPlugin_srr1[4]; + MSR_PMM <= SPRPlugin_srr1[2]; + MSR_RI <= SPRPlugin_srr1[1]; + MSR_LE <= SPRPlugin_srr1[0]; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_69_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_SPRPLUGIN_SPR_1025)begin + if(execute_SPRPLUGIN_writeEnable)begin + MSR_VSX <= _zz_644_[0]; + MSR_FE1 <= _zz_645_[0]; + MSR_FE0 <= _zz_646_[0]; + MSR_PMM <= _zz_647_[0]; + MSR_IR <= _zz_648_[0]; + MSR_PR <= _zz_649_[0]; + MSR_FP <= _zz_650_[0]; + MSR_DR <= _zz_651_[0]; + MSR_VEC <= _zz_652_[0]; + MSR_RI <= _zz_653_[0]; + MSR_ME <= _zz_654_[0]; + MSR_EE <= _zz_655_[0]; + MSR_LE <= _zz_656_[0]; + end + end + if(_zz_438_)begin + if(iBusWB_ACK)begin + _zz_358_ <= (_zz_358_ + (3'b001)); + end + end + _zz_359_ <= (iBusWB_CYC && iBusWB_ACK); + if((_zz_361_ && _zz_362_))begin + _zz_360_ <= (_zz_360_ + (3'b001)); + if(_zz_364_)begin + _zz_360_ <= (3'b000); + end + end + _zz_366_ <= ((_zz_361_ && (! dBusWB_WE)) && dBusWB_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_141_ <= IBusCachedPlugin_iBusRsp_stages_0_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_144_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_writeLast_valid <= IBusCachedPlugin_predictor_historyWriteDelayPatched_valid; + IBusCachedPlugin_predictor_writeLast_payload_address <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address; + IBusCachedPlugin_predictor_writeLast_payload_data_source <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source; + IBusCachedPlugin_predictor_writeLast_payload_data_branchWish <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; + IBusCachedPlugin_predictor_writeLast_payload_data_target <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target; + end + if(IBusCachedPlugin_iBusRsp_stages_0_input_ready)begin + IBusCachedPlugin_predictor_buffer_pcCorrected <= IBusCachedPlugin_fetchPc_corrected; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_line_source <= IBusCachedPlugin_predictor_buffer_line_source; + IBusCachedPlugin_predictor_line_branchWish <= IBusCachedPlugin_predictor_buffer_line_branchWish; + IBusCachedPlugin_predictor_line_target <= IBusCachedPlugin_predictor_buffer_line_target; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_buffer_hazard_regNextWhen <= IBusCachedPlugin_predictor_buffer_hazard; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + IBusCachedPlugin_predictor_iBusRspContext_hazard <= IBusCachedPlugin_predictor_fetchContext_hazard; + IBusCachedPlugin_predictor_iBusRspContext_hit <= IBusCachedPlugin_predictor_fetchContext_hit; + IBusCachedPlugin_predictor_iBusRspContext_line_source <= IBusCachedPlugin_predictor_fetchContext_line_source; + IBusCachedPlugin_predictor_iBusRspContext_line_branchWish <= IBusCachedPlugin_predictor_fetchContext_line_branchWish; + IBusCachedPlugin_predictor_iBusRspContext_line_target <= IBusCachedPlugin_predictor_fetchContext_line_target; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_388_)begin + dataCache_1__io_mem_cmd_m2sPipe_rData_wr <= dataCache_1__io_mem_cmd_payload_wr; + dataCache_1__io_mem_cmd_m2sPipe_rData_address <= dataCache_1__io_mem_cmd_payload_address; + dataCache_1__io_mem_cmd_m2sPipe_rData_data <= dataCache_1__io_mem_cmd_payload_data; + dataCache_1__io_mem_cmd_m2sPipe_rData_mask <= dataCache_1__io_mem_cmd_payload_mask; + dataCache_1__io_mem_cmd_m2sPipe_rData_length <= dataCache_1__io_mem_cmd_payload_length; + dataCache_1__io_mem_cmd_m2sPipe_rData_last <= dataCache_1__io_mem_cmd_payload_last; + end + _zz_269_ <= (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_9); + _zz_270_ <= writeBack_LOAD_UPDATE_ADDR; + _zz_271_ <= writeBack_LOAD_UPDATE_DATA; + if((MULDIV1_counter_value == 6'h20))begin + MULDIV1_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + MULDIV1_done <= 1'b0; + end + if(_zz_399_)begin + if(_zz_422_)begin + MULDIV_rs1[31 : 0] <= MULDIV1_stage_0_outNumerator; + MULDIV_accumulator[31 : 0] <= MULDIV1_stage_0_outRemainder; + if((MULDIV1_counter_value == 6'h20))begin + MULDIV1_result <= _zz_573_[31:0]; + end + end + end + if(_zz_423_)begin + MULDIV_accumulator <= 65'h0; + MULDIV_rs1 <= ((_zz_281_ ? (~ _zz_282_) : _zz_282_) + _zz_579_); + MULDIV_rs2 <= ((_zz_280_ ? (~ execute_SRC2) : execute_SRC2) + _zz_581_); + MULDIV1_needRevert <= ((_zz_281_ ^ _zz_280_) && (! ((execute_SRC2 == 32'h0) && execute_DECODER_stageables_3))); + end + Hazards_writeBackBuffer_payload_address <= Hazards_writeBackWrites_payload_address; + Hazards_writeBackBuffer_payload_data <= Hazards_writeBackWrites_payload_data; + SPRPlugin_dec31Prev <= SPRPlugin_dec[31]; + if((SPRPlugin_dec31Prev && (! SPRPlugin_dec[31])))begin + SPRPlugin_intDec <= 1'b0; + end else begin + if(((! SPRPlugin_dec31Prev) && SPRPlugin_dec[31]))begin + SPRPlugin_intDec <= 1'b1; + end else begin + if(SPRPlugin_intDecTkn)begin + SPRPlugin_intDec <= 1'b0; + end + end + end + if(writeBack_arbitration_isFiring)begin + SPRPlugin_minstret <= (SPRPlugin_minstret + 32'h00000001); + end + if(_zz_407_)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= _zz_337_; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_imm : decodeExceptionPort_payload_imm); + end + if(SPRPlugin_selfException_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= SPRPlugin_selfException_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= SPRPlugin_selfException_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= SPRPlugin_selfException_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= SPRPlugin_selfException_payload_imm; + end + if(BranchPlugin_branchExceptionPort_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= BranchPlugin_branchExceptionPort_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= BranchPlugin_branchExceptionPort_payload_imm; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= DBusCachedPlugin_exceptionBus_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= DBusCachedPlugin_exceptionBus_payload_imm; + end + if(_zz_439_)begin + if(_zz_440_)begin + SPRPlugin_interrupt_code <= (4'b1001); + SPRPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + SPRPlugin_darSave <= writeBack_SRC_ADD; + if(_zz_408_)begin + SPRPlugin_srr0 <= SPRPlugin_intSRR0; + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1582_,_zz_1583_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_PGM_ILL))begin + SPRPlugin_srr1[19] <= 1'b1; + end + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_PGM_PRV))begin + SPRPlugin_srr1[18] <= 1'b1; + end + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ISI))begin + SPRPlugin_srr1[30] <= 1'b1; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ISI_PROT))begin + SPRPlugin_srr1[29] <= 1'b1; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_DSI))begin + SPRPlugin_dsisr <= 32'h0; + SPRPlugin_dsisr[30] <= 1'b1; + SPRPlugin_dar <= SPRPlugin_darSave; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_DSI_PROT))begin + SPRPlugin_dsisr <= 32'h0; + SPRPlugin_dsisr[27] <= 1'b1; + SPRPlugin_dar <= SPRPlugin_darSave; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ALG))begin + SPRPlugin_dar <= SPRPlugin_darSave; + end + end + end + end + end + end + if(! (execute_SPRPLUGIN_writeEnable && (execute_SPR_ID == 11'h10c))) begin + if(SPRPlugin_incTB)begin + SPRPlugin_tb <= (SPRPlugin_tb + 32'h00000001); + end + end + if(! (execute_SPRPLUGIN_writeEnable && (execute_SPR_ID == 11'h016))) begin + SPRPlugin_dec <= (SPRPlugin_dec - 32'h00000001); + end + if(_zz_410_)begin + SPRPlugin_srr0 <= (writeBack_PC + 32'h00000004); + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1584_,_zz_1585_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + end + if(_zz_411_)begin + SPRPlugin_srr0 <= (writeBack_PC + 32'h00000004); + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1586_,_zz_1587_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RB <= decode_RB; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_28 <= decode_DECODER_stageables_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_44 <= _zz_57_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SPR_ID <= execute_SPR_ID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SPR_ID <= memory_SPR_ID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_36 <= decode_DECODER_stageables_36; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_36 <= execute_DECODER_stageables_36; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_36 <= memory_DECODER_stageables_36; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard; + decode_to_execute_PREDICTION_CONTEXT_hit <= decode_PREDICTION_CONTEXT_hit; + decode_to_execute_PREDICTION_CONTEXT_line_source <= decode_PREDICTION_CONTEXT_line_source; + decode_to_execute_PREDICTION_CONTEXT_line_branchWish <= decode_PREDICTION_CONTEXT_line_branchWish; + decode_to_execute_PREDICTION_CONTEXT_line_target <= decode_PREDICTION_CONTEXT_line_target; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard; + execute_to_memory_PREDICTION_CONTEXT_hit <= execute_PREDICTION_CONTEXT_hit; + execute_to_memory_PREDICTION_CONTEXT_line_source <= execute_PREDICTION_CONTEXT_line_source; + execute_to_memory_PREDICTION_CONTEXT_line_branchWish <= execute_PREDICTION_CONTEXT_line_branchWish; + execute_to_memory_PREDICTION_CONTEXT_line_target <= execute_PREDICTION_CONTEXT_line_target; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_49 <= _zz_54_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_49 <= _zz_60_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_49 <= _zz_51_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_48 <= decode_DECODER_stageables_48; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_XER_WRITE_validOV <= execute_XER_WRITE_validOV; + execute_to_memory_XER_WRITE_validCA <= execute_XER_WRITE_validCA; + execute_to_memory_XER_WRITE_imm <= execute_XER_WRITE_imm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_XER_WRITE_validOV <= memory_XER_WRITE_validOV; + memory_to_writeBack_XER_WRITE_validCA <= memory_XER_WRITE_validCA; + memory_to_writeBack_XER_WRITE_imm <= memory_XER_WRITE_imm; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_LOAD_UPDATE_DATA <= execute_LOAD_UPDATE_DATA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_LOAD_UPDATE_DATA <= memory_LOAD_UPDATE_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_13 <= _zz_48_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_55 <= decode_DECODER_stageables_55; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_55 <= execute_DECODER_stageables_55; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_55 <= memory_DECODER_stageables_55; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_57 <= decode_DECODER_stageables_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_20 <= _zz_46_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_68_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_54 <= decode_DECODER_stageables_54; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_32 <= decode_DECODER_stageables_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_32 <= execute_DECODER_stageables_32; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_32 <= memory_DECODER_stageables_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_22 <= decode_DECODER_stageables_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_131_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_LOAD_UPDATE_ADDR <= execute_LOAD_UPDATE_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_LOAD_UPDATE_ADDR <= memory_LOAD_UPDATE_ADDR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_30 <= decode; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_52 <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_52 <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_52 <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_R0_ADDR <= decode_R0_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_11 <= decode_DECODER_stageables_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_16 <= _zz_43_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_56 <= decode_DECODER_stageables_56; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_56 <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_56 <= memory_DECODER_stageables_56; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_39 <= decode_DECODER_stageables_39; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_39 <= execute_DECODER_stageables_39; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_39 <= memory_DECODER_stageables_39; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_LINK <= execute_BRANCH_LINK; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_BRANCH_LINK <= memory_BRANCH_LINK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_0 <= _zz_40_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_15 <= decode_DECODER_stageables_15; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_15 <= execute_DECODER_stageables_15; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_5 <= decode_DECODER_stageables_5; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_5 <= execute_DECODER_stageables_5; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CR_WRITE_op <= _zz_37_; + execute_to_memory_CR_WRITE_ba <= execute_CR_WRITE_ba; + execute_to_memory_CR_WRITE_bb <= execute_CR_WRITE_bb; + execute_to_memory_CR_WRITE_bt <= execute_CR_WRITE_bt; + execute_to_memory_CR_WRITE_imm <= execute_CR_WRITE_imm; + execute_to_memory_CR_WRITE_fxm <= execute_CR_WRITE_fxm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CR_WRITE_op <= _zz_34_; + memory_to_writeBack_CR_WRITE_ba <= memory_CR_WRITE_ba; + memory_to_writeBack_CR_WRITE_bb <= memory_CR_WRITE_bb; + memory_to_writeBack_CR_WRITE_bt <= memory_CR_WRITE_bt; + memory_to_writeBack_CR_WRITE_imm <= memory_CR_WRITE_imm; + memory_to_writeBack_CR_WRITE_fxm <= memory_CR_WRITE_fxm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_42 <= decode_DECODER_stageables_42; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RT_ADDR <= decode_RT_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_RT_ADDR <= execute_RT_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_RT_ADDR <= memory_RT_ADDR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_45 <= decode_DECODER_stageables_45; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_45 <= execute_DECODER_stageables_45; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_45 <= memory_DECODER_stageables_45; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_9 <= decode_DECODER_stageables_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_9 <= execute_DECODER_stageables_9; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_9 <= memory_DECODER_stageables_9; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_19 <= _zz_32_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_18 <= decode_DECODER_stageables_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_34 <= decode_DECODER_stageables_34; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_24 <= decode_DECODER_stageables_24; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_24 <= execute_DECODER_stageables_24; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_24 <= memory_DECODER_stageables_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MSR_ENDIAN <= _zz_29_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MSR_ENDIAN <= _zz_27_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MSR_ENDIAN <= _zz_25_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC1 <= execute_SRC1; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC1 <= memory_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_14 <= decode_DECODER_stageables_14; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_3 <= decode_DECODER_stageables_3; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC_CR <= execute_SRC_CR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC_CR <= memory_SRC_CR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DEC <= execute_BRANCH_DEC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_BRANCH_DEC <= memory_BRANCH_DEC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RA <= decode_RA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_2 <= decode_DECODER_stageables_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_6 <= decode_DECODER_stageables_6; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_40 <= decode_DECODER_stageables_40; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_31 <= decode_DECODER_stageables_31; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_31 <= execute_DECODER_stageables_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_31 <= memory_DECODER_stageables_31; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_TARGET_MISSMATCH2 <= execute_TARGET_MISSMATCH2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_35 <= decode_DECODER_stageables_35; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_ADDR <= execute_REGFILE_WRITE_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_ADDR <= memory_REGFILE_WRITE_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_53 <= decode_DECODER_stageables_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_53 <= execute_DECODER_stageables_53; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_53 <= memory_DECODER_stageables_53; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_51 <= _zz_22_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_7 <= _zz_19_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_7 <= _zz_16_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_7 <= _zz_14_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CR_FIELD_WR <= execute_CR_FIELD_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CR_FIELD_WR <= memory_CR_FIELD_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_1 <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS <= decode_RS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_46 <= decode_DECODER_stageables_46; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC_ADD <= execute_SRC_ADD; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC_ADD <= memory_SRC_ADD; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_23 <= decode_DECODER_stageables_23; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_8 <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_37 <= decode_DECODER_stageables_37; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_37 <= execute_DECODER_stageables_37; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_21 <= decode_DECODER_stageables_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_26 <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CR_FIELD_RD <= decode_CR_FIELD_RD; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_27 <= decode_DECODER_stageables_27; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_43 <= decode_DECODER_stageables_43; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_43 <= execute_DECODER_stageables_43; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_38 <= _zz_3_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_XER_SO <= execute_XER_SO; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_XER_SO <= memory_XER_SO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_72_; + end + if(((! writeBack_arbitration_isStuck) && (! SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_NEXT_PC2 <= execute_NEXT_PC2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_25 <= decode_DECODER_stageables_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_29 <= decode_DECODER_stageables_29; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_12 <= _zz_1_; + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_1025 <= (_zz_349_ == 11'h401); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_26 <= (_zz_349_ == 11'h01a); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_27 <= (_zz_349_ == 11'h01b); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_19 <= (_zz_349_ == 11'h013); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_259 <= (_zz_349_ == 11'h103); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_18 <= (_zz_349_ == 11'h012); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_268 <= (_zz_349_ == 11'h10c); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_22 <= (_zz_349_ == 11'h016); + end + if(execute_SPRPLUGIN_SPR_26)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_srr0 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_27)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_srr1 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_19)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dar <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_259)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_sprg3 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_18)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dsisr <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_268)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_tb <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_22)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dec <= execute_SRC1[31 : 0]; + end + end + iBusWB_DAT_MISO_regNext <= iBusWB_DAT_MISO; + dBusWB_DAT_MISO_regNext <= dBusWB_DAT_MISO; + end + + +endmodule diff --git a/build/litex/bin2init b/build/litex/bin2init new file mode 100755 index 0000000..b89e435 --- /dev/null +++ b/build/litex/bin2init @@ -0,0 +1,27 @@ +#!/usr/bin/python3 + +# read .bin (objcopy -O binary x.elf x.bin) and create ascii block file + +import sys +from binascii import hexlify, unhexlify + +def x2d(i): + return int(i, 16) + +inFile = sys.argv[1] +#size = sys.argv[2] + +outFile = inFile + '.hex' + +lines = [] +with open(inFile, 'rb') as binFile: + word = binFile.read(4) + while word: + hex = hexlify(word) + lines.append(hex.decode('utf-8').upper() + '\n') + word = binFile.read(4) + +# need to pad to full size? +with open(outFile, 'w') as txtFile: + txtFile.writelines(lines) + diff --git a/sim/soc/A2P_WB.v b/sim/soc/A2P_WB.v new file mode 100644 index 0000000..751355c --- /dev/null +++ b/sim/soc/A2P_WB.v @@ -0,0 +1,14250 @@ +// Generator : SpinalHDL v1.4.0 git head : ecb5a80b713566f417ea3ea061f9969e73770a7f +// Date : 27/08/2022, 10:55:10 +// Component : A2P_4K1W + + +`define TgtCtrlEnum_defaultEncoding_type [0:0] +`define TgtCtrlEnum_defaultEncoding_RT 1'b0 +`define TgtCtrlEnum_defaultEncoding_RA 1'b1 + +`define Src1CtrlEnum_defaultEncoding_type [2:0] +`define Src1CtrlEnum_defaultEncoding_RA 3'b000 +`define Src1CtrlEnum_defaultEncoding_RA_N 3'b001 +`define Src1CtrlEnum_defaultEncoding_RA_NIA 3'b010 +`define Src1CtrlEnum_defaultEncoding_RA_0 3'b011 +`define Src1CtrlEnum_defaultEncoding_RS 3'b100 + +`define Src2CtrlEnum_defaultEncoding_type [2:0] +`define Src2CtrlEnum_defaultEncoding_RB 3'b000 +`define Src2CtrlEnum_defaultEncoding_RB_0 3'b001 +`define Src2CtrlEnum_defaultEncoding_RB_M1 3'b010 +`define Src2CtrlEnum_defaultEncoding_RB_UI 3'b011 +`define Src2CtrlEnum_defaultEncoding_RB_SI 3'b100 +`define Src2CtrlEnum_defaultEncoding_RB_SH 3'b101 +`define Src2CtrlEnum_defaultEncoding_RB_PCISD 3'b110 +`define Src2CtrlEnum_defaultEncoding_RA 3'b111 + +`define AluCtrlEnum_defaultEncoding_type [1:0] +`define AluCtrlEnum_defaultEncoding_ADD 2'b00 +`define AluCtrlEnum_defaultEncoding_BIT_1 2'b01 +`define AluCtrlEnum_defaultEncoding_RIMI 2'b10 +`define AluCtrlEnum_defaultEncoding_SPEC 2'b11 + +`define Src3CtrlEnum_defaultEncoding_type [1:0] +`define Src3CtrlEnum_defaultEncoding_CA 2'b00 +`define Src3CtrlEnum_defaultEncoding_CA_0 2'b01 +`define Src3CtrlEnum_defaultEncoding_CA_1 2'b10 + +`define DataSizeEnum_defaultEncoding_type [1:0] +`define DataSizeEnum_defaultEncoding_B 2'b00 +`define DataSizeEnum_defaultEncoding_H 2'b01 +`define DataSizeEnum_defaultEncoding_HA 2'b10 +`define DataSizeEnum_defaultEncoding_W 2'b11 + +`define CRMoveCtrlEnum_defaultEncoding_type [1:0] +`define CRMoveCtrlEnum_defaultEncoding_MCRF 2'b00 +`define CRMoveCtrlEnum_defaultEncoding_MCRXRX 2'b01 +`define CRMoveCtrlEnum_defaultEncoding_MTCRF 2'b10 + +`define EndianEnum_defaultEncoding_type [0:0] +`define EndianEnum_defaultEncoding_BE 1'b0 +`define EndianEnum_defaultEncoding_LE 1'b1 + +`define AluBitwiseCtrlEnum_defaultEncoding_type [3:0] +`define AluBitwiseCtrlEnum_defaultEncoding_AND_1 4'b0000 +`define AluBitwiseCtrlEnum_defaultEncoding_ANDC 4'b0001 +`define AluBitwiseCtrlEnum_defaultEncoding_OR_1 4'b0010 +`define AluBitwiseCtrlEnum_defaultEncoding_ORC 4'b0011 +`define AluBitwiseCtrlEnum_defaultEncoding_XOR_1 4'b0100 +`define AluBitwiseCtrlEnum_defaultEncoding_XORC 4'b0101 +`define AluBitwiseCtrlEnum_defaultEncoding_EQV 4'b0110 +`define AluBitwiseCtrlEnum_defaultEncoding_NAND_1 4'b0111 +`define AluBitwiseCtrlEnum_defaultEncoding_NOR_1 4'b1000 +`define AluBitwiseCtrlEnum_defaultEncoding_EXTSB 4'b1001 +`define AluBitwiseCtrlEnum_defaultEncoding_EXTSH 4'b1010 + +`define CRBusCmdEnum_defaultEncoding_type [4:0] +`define CRBusCmdEnum_defaultEncoding_NOP 5'b00000 +`define CRBusCmdEnum_defaultEncoding_CR0 5'b00001 +`define CRBusCmdEnum_defaultEncoding_CR1 5'b00010 +`define CRBusCmdEnum_defaultEncoding_CR6 5'b00011 +`define CRBusCmdEnum_defaultEncoding_CMP 5'b00100 +`define CRBusCmdEnum_defaultEncoding_AND_1 5'b00101 +`define CRBusCmdEnum_defaultEncoding_OR_1 5'b00110 +`define CRBusCmdEnum_defaultEncoding_XOR_1 5'b00111 +`define CRBusCmdEnum_defaultEncoding_NAND_1 5'b01000 +`define CRBusCmdEnum_defaultEncoding_NOR_1 5'b01001 +`define CRBusCmdEnum_defaultEncoding_EQV 5'b01010 +`define CRBusCmdEnum_defaultEncoding_ANDC 5'b01011 +`define CRBusCmdEnum_defaultEncoding_ORC 5'b01100 +`define CRBusCmdEnum_defaultEncoding_MCRF 5'b01101 +`define CRBusCmdEnum_defaultEncoding_MCRXRX 5'b01110 +`define CRBusCmdEnum_defaultEncoding_MTOCRF 5'b01111 +`define CRBusCmdEnum_defaultEncoding_MTCRF 5'b10000 +`define CRBusCmdEnum_defaultEncoding_DEC 5'b10001 +`define CRBusCmdEnum_defaultEncoding_LNK 5'b10010 +`define CRBusCmdEnum_defaultEncoding_DECLNK 5'b10011 + +`define AluSpecCtrlEnum_defaultEncoding_type [2:0] +`define AluSpecCtrlEnum_defaultEncoding_CNTLZW 3'b000 +`define AluSpecCtrlEnum_defaultEncoding_CNTTZW 3'b001 +`define AluSpecCtrlEnum_defaultEncoding_POPCNTB 3'b010 +`define AluSpecCtrlEnum_defaultEncoding_POPCNTW 3'b011 +`define AluSpecCtrlEnum_defaultEncoding_CMPB 3'b100 +`define AluSpecCtrlEnum_defaultEncoding_PRTYW 3'b101 + +`define AluRimiCtrlEnum_defaultEncoding_type [2:0] +`define AluRimiCtrlEnum_defaultEncoding_ROT 3'b000 +`define AluRimiCtrlEnum_defaultEncoding_INS 3'b001 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTL 3'b010 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTR 3'b011 +`define AluRimiCtrlEnum_defaultEncoding_SHIFTRA 3'b100 + +`define CRLogCtrlEnum_defaultEncoding_type [2:0] +`define CRLogCtrlEnum_defaultEncoding_AND_1 3'b000 +`define CRLogCtrlEnum_defaultEncoding_OR_1 3'b001 +`define CRLogCtrlEnum_defaultEncoding_XOR_1 3'b010 +`define CRLogCtrlEnum_defaultEncoding_NAND_1 3'b011 +`define CRLogCtrlEnum_defaultEncoding_NOR_1 3'b100 +`define CRLogCtrlEnum_defaultEncoding_EQV 3'b101 +`define CRLogCtrlEnum_defaultEncoding_ANDC 3'b110 +`define CRLogCtrlEnum_defaultEncoding_ORC 3'b111 + +`define BranchCtrlEnum_defaultEncoding_type [2:0] +`define BranchCtrlEnum_defaultEncoding_NONE 3'b000 +`define BranchCtrlEnum_defaultEncoding_BU 3'b001 +`define BranchCtrlEnum_defaultEncoding_BC 3'b010 +`define BranchCtrlEnum_defaultEncoding_BCLR 3'b011 +`define BranchCtrlEnum_defaultEncoding_BCCTR 3'b100 +`define BranchCtrlEnum_defaultEncoding_BCTAR 3'b101 + +`define EnvCtrlEnum_defaultEncoding_type [3:0] +`define EnvCtrlEnum_defaultEncoding_NONE 4'b0000 +`define EnvCtrlEnum_defaultEncoding_MFMSR 4'b0001 +`define EnvCtrlEnum_defaultEncoding_MTMSR 4'b0010 +`define EnvCtrlEnum_defaultEncoding_SC 4'b0011 +`define EnvCtrlEnum_defaultEncoding_SCV 4'b0100 +`define EnvCtrlEnum_defaultEncoding_RFI 4'b0101 +`define EnvCtrlEnum_defaultEncoding_RFSCV 4'b0110 +`define EnvCtrlEnum_defaultEncoding_TW 4'b0111 +`define EnvCtrlEnum_defaultEncoding_TWI 4'b1000 + +`define AluRimiAmtEnum_defaultEncoding_type [0:0] +`define AluRimiAmtEnum_defaultEncoding_IMM 1'b0 +`define AluRimiAmtEnum_defaultEncoding_RB 1'b1 + +`define ExcpEnum_defaultEncoding_type [4:0] +`define ExcpEnum_defaultEncoding_NONE 5'b00000 +`define ExcpEnum_defaultEncoding_SC 5'b00001 +`define ExcpEnum_defaultEncoding_SCV 5'b00010 +`define ExcpEnum_defaultEncoding_TRAP 5'b00011 +`define ExcpEnum_defaultEncoding_RFI 5'b00100 +`define ExcpEnum_defaultEncoding_RFSCV 5'b00101 +`define ExcpEnum_defaultEncoding_DSI 5'b00110 +`define ExcpEnum_defaultEncoding_DSI_PROT 5'b00111 +`define ExcpEnum_defaultEncoding_DSS 5'b01000 +`define ExcpEnum_defaultEncoding_ISI 5'b01001 +`define ExcpEnum_defaultEncoding_ISI_PROT 5'b01010 +`define ExcpEnum_defaultEncoding_ISS 5'b01011 +`define ExcpEnum_defaultEncoding_ALG 5'b01100 +`define ExcpEnum_defaultEncoding_PGM_ILL 5'b01101 +`define ExcpEnum_defaultEncoding_PGM_PRV 5'b01110 +`define ExcpEnum_defaultEncoding_FP 5'b01111 +`define ExcpEnum_defaultEncoding_VEC 5'b10000 +`define ExcpEnum_defaultEncoding_VSX 5'b10001 +`define ExcpEnum_defaultEncoding_FAC 5'b10010 +`define ExcpEnum_defaultEncoding_SR 5'b10011 +`define ExcpEnum_defaultEncoding_MC 5'b10100 +`define ExcpEnum_defaultEncoding_EXT 5'b10101 +`define ExcpEnum_defaultEncoding_DEC 5'b10110 +`define ExcpEnum_defaultEncoding_TR 5'b10111 +`define ExcpEnum_defaultEncoding_PM 5'b11000 + + +module InstructionCache ( + input io_flush, + input io_cpu_prefetch_isValid, + output reg io_cpu_prefetch_haltIt, + input [31:0] io_cpu_prefetch_pc, + input io_cpu_fetch_isValid, + input io_cpu_fetch_isStuck, + input io_cpu_fetch_isRemoved, + input [31:0] io_cpu_fetch_pc, + output [31:0] io_cpu_fetch_data, + output io_cpu_fetch_mmuBus_cmd_isValid, + output [31:0] io_cpu_fetch_mmuBus_cmd_virtualAddress, + output io_cpu_fetch_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_fetch_mmuBus_rsp_physicalAddress, + input io_cpu_fetch_mmuBus_rsp_isIoAccess, + input io_cpu_fetch_mmuBus_rsp_allowRead, + input io_cpu_fetch_mmuBus_rsp_allowWrite, + input io_cpu_fetch_mmuBus_rsp_allowExecute, + input io_cpu_fetch_mmuBus_rsp_exception, + input io_cpu_fetch_mmuBus_rsp_refilling, + output io_cpu_fetch_mmuBus_spr_valid, + output [9:0] io_cpu_fetch_mmuBus_spr_payload_id, + output [31:0] io_cpu_fetch_mmuBus_spr_payload_data, + output io_cpu_fetch_mmuBus_end, + input io_cpu_fetch_mmuBus_busy, + output [31:0] io_cpu_fetch_physicalAddress, + output [3:0] io_cpu_fetch_exceptionType, + input io_cpu_fetch_bypassTranslation, + output io_cpu_fetch_haltIt, + input io_cpu_decode_isValid, + input io_cpu_decode_isStuck, + input [31:0] io_cpu_decode_pc, + output [31:0] io_cpu_decode_physicalAddress, + output [31:0] io_cpu_decode_data, + output io_cpu_decode_cacheMiss, + output io_cpu_decode_error, + output io_cpu_decode_mmuRefilling, + output io_cpu_decode_mmuException, + input io_cpu_decode_isUser, + output [3:0] io_cpu_decode_exceptionType, + input io_cpu_fill_valid, + input [31:0] io_cpu_fill_payload, + output io_mem_cmd_valid, + input io_mem_cmd_ready, + output [31:0] io_mem_cmd_payload_address, + output [2:0] io_mem_cmd_payload_size, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input io_spr_valid, + input [9:0] io_spr_payload_id, + input [31:0] io_spr_payload_data, + input clk, + input reset +); + reg [21:0] _zz_11_; + reg [31:0] _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire [0:0] _zz_15_; + wire [0:0] _zz_16_; + wire [21:0] _zz_17_; + reg _zz_1_; + reg _zz_2_; + reg lineLoader_fire; + reg lineLoader_valid; + (* syn_keep , keep *) reg [31:0] lineLoader_address /* synthesis syn_keep = 1 */ ; + reg lineLoader_hadError; + reg lineLoader_flushPending; + reg [7:0] lineLoader_flushCounter; + reg _zz_3_; + reg lineLoader_cmdSent; + reg lineLoader_wayToAllocate_willIncrement; + wire lineLoader_wayToAllocate_willClear; + wire lineLoader_wayToAllocate_willOverflowIfInc; + wire lineLoader_wayToAllocate_willOverflow; + (* syn_keep , keep *) reg [2:0] lineLoader_wordIndex /* synthesis syn_keep = 1 */ ; + wire lineLoader_write_tag_0_valid; + wire [6:0] lineLoader_write_tag_0_payload_address; + wire lineLoader_write_tag_0_payload_data_valid; + wire lineLoader_write_tag_0_payload_data_error; + wire [19:0] lineLoader_write_tag_0_payload_data_address; + wire lineLoader_write_data_0_valid; + wire [9:0] lineLoader_write_data_0_payload_address; + wire [31:0] lineLoader_write_data_0_payload_data; + wire _zz_4_; + wire [6:0] _zz_5_; + wire _zz_6_; + wire fetchStage_read_waysValues_0_tag_valid; + wire fetchStage_read_waysValues_0_tag_error; + wire [19:0] fetchStage_read_waysValues_0_tag_address; + wire [21:0] _zz_7_; + wire [9:0] _zz_8_; + wire _zz_9_; + wire [31:0] fetchStage_read_waysValues_0_data; + reg [31:0] decodeStage_mmuRsp_physicalAddress; + reg decodeStage_mmuRsp_isIoAccess; + reg decodeStage_mmuRsp_allowRead; + reg decodeStage_mmuRsp_allowWrite; + reg decodeStage_mmuRsp_allowExecute; + reg decodeStage_mmuRsp_exception; + reg decodeStage_mmuRsp_refilling; + reg decodeStage_hit_tags_0_valid; + reg decodeStage_hit_tags_0_error; + reg [19:0] decodeStage_hit_tags_0_address; + wire decodeStage_hit_hits_0; + wire decodeStage_hit_valid; + reg [31:0] _zz_10_; + wire [31:0] decodeStage_hit_data; + wire decodeStage_protError; + reg [21:0] ways_0_tags [0:127]; + reg [31:0] ways_0_datas [0:1023]; + + assign _zz_13_ = (! lineLoader_flushCounter[7]); + assign _zz_14_ = (lineLoader_flushPending && (! (lineLoader_valid || io_cpu_fetch_isValid))); + assign _zz_15_ = _zz_7_[0 : 0]; + assign _zz_16_ = _zz_7_[1 : 1]; + assign _zz_17_ = {lineLoader_write_tag_0_payload_data_address,{lineLoader_write_tag_0_payload_data_error,lineLoader_write_tag_0_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_2_) begin + ways_0_tags[lineLoader_write_tag_0_payload_address] <= _zz_17_; + end + end + + always @ (posedge clk) begin + if(_zz_6_) begin + _zz_11_ <= ways_0_tags[_zz_5_]; + end + end + + always @ (posedge clk) begin + if(_zz_1_) begin + ways_0_datas[lineLoader_write_data_0_payload_address] <= lineLoader_write_data_0_payload_data; + end + end + + always @ (posedge clk) begin + if(_zz_9_) begin + _zz_12_ <= ways_0_datas[_zz_8_]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if(lineLoader_write_data_0_valid)begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if(lineLoader_write_tag_0_valid)begin + _zz_2_ = 1'b1; + end + end + + assign io_cpu_fetch_haltIt = io_cpu_fetch_mmuBus_busy; + always @ (*) begin + lineLoader_fire = 1'b0; + if(io_mem_rsp_valid)begin + if((lineLoader_wordIndex == (3'b111)))begin + lineLoader_fire = 1'b1; + end + end + end + + always @ (*) begin + io_cpu_prefetch_haltIt = (lineLoader_valid || lineLoader_flushPending); + if(_zz_13_)begin + io_cpu_prefetch_haltIt = 1'b1; + end + if((! _zz_3_))begin + io_cpu_prefetch_haltIt = 1'b1; + end + if(io_flush)begin + io_cpu_prefetch_haltIt = 1'b1; + end + end + + assign io_mem_cmd_valid = (lineLoader_valid && (! lineLoader_cmdSent)); + assign io_mem_cmd_payload_address = {lineLoader_address[31 : 5],5'h0}; + assign io_mem_cmd_payload_size = (3'b101); + always @ (*) begin + lineLoader_wayToAllocate_willIncrement = 1'b0; + if((! lineLoader_valid))begin + lineLoader_wayToAllocate_willIncrement = 1'b1; + end + end + + assign lineLoader_wayToAllocate_willClear = 1'b0; + assign lineLoader_wayToAllocate_willOverflowIfInc = 1'b1; + assign lineLoader_wayToAllocate_willOverflow = (lineLoader_wayToAllocate_willOverflowIfInc && lineLoader_wayToAllocate_willIncrement); + assign _zz_4_ = 1'b1; + assign lineLoader_write_tag_0_valid = ((_zz_4_ && lineLoader_fire) || (! lineLoader_flushCounter[7])); + assign lineLoader_write_tag_0_payload_address = (lineLoader_flushCounter[7] ? lineLoader_address[11 : 5] : lineLoader_flushCounter[6 : 0]); + assign lineLoader_write_tag_0_payload_data_valid = lineLoader_flushCounter[7]; + assign lineLoader_write_tag_0_payload_data_error = (lineLoader_hadError || io_mem_rsp_payload_error); + assign lineLoader_write_tag_0_payload_data_address = lineLoader_address[31 : 12]; + assign lineLoader_write_data_0_valid = (io_mem_rsp_valid && _zz_4_); + assign lineLoader_write_data_0_payload_address = {lineLoader_address[11 : 5],lineLoader_wordIndex}; + assign lineLoader_write_data_0_payload_data = io_mem_rsp_payload_data; + assign _zz_5_ = io_cpu_prefetch_pc[11 : 5]; + assign _zz_6_ = (! io_cpu_fetch_isStuck); + assign _zz_7_ = _zz_11_; + assign fetchStage_read_waysValues_0_tag_valid = _zz_15_[0]; + assign fetchStage_read_waysValues_0_tag_error = _zz_16_[0]; + assign fetchStage_read_waysValues_0_tag_address = _zz_7_[21 : 2]; + assign _zz_8_ = io_cpu_prefetch_pc[11 : 2]; + assign _zz_9_ = (! io_cpu_fetch_isStuck); + assign fetchStage_read_waysValues_0_data = _zz_12_; + assign io_cpu_fetch_data = fetchStage_read_waysValues_0_data; + assign io_cpu_fetch_mmuBus_cmd_isValid = io_cpu_fetch_isValid; + assign io_cpu_fetch_mmuBus_cmd_virtualAddress = io_cpu_fetch_pc; + assign io_cpu_fetch_mmuBus_cmd_bypassTranslation = io_cpu_fetch_bypassTranslation; + assign io_cpu_fetch_mmuBus_end = ((! io_cpu_fetch_isStuck) || io_cpu_fetch_isRemoved); + assign io_cpu_fetch_physicalAddress = io_cpu_fetch_mmuBus_rsp_physicalAddress; + assign io_cpu_fetch_mmuBus_spr_valid = io_spr_valid; + assign io_cpu_fetch_mmuBus_spr_payload_id = io_spr_payload_id; + assign io_cpu_fetch_mmuBus_spr_payload_data = io_spr_payload_data; + assign decodeStage_hit_hits_0 = (decodeStage_hit_tags_0_valid && (decodeStage_hit_tags_0_address == decodeStage_mmuRsp_physicalAddress[31 : 12])); + assign decodeStage_hit_valid = (decodeStage_hit_hits_0 != (1'b0)); + assign decodeStage_hit_data = _zz_10_; + assign io_cpu_decode_data = decodeStage_hit_data; + assign io_cpu_decode_cacheMiss = (! decodeStage_hit_valid); + assign io_cpu_decode_error = decodeStage_hit_tags_0_error; + assign io_cpu_decode_mmuRefilling = decodeStage_mmuRsp_refilling; + assign io_cpu_decode_mmuException = ((! decodeStage_mmuRsp_refilling) && decodeStage_mmuRsp_exception); + assign decodeStage_protError = (io_cpu_decode_isValid && ((! decodeStage_mmuRsp_refilling) && ((! decodeStage_mmuRsp_allowRead) || (! decodeStage_mmuRsp_allowExecute)))); + assign io_cpu_decode_exceptionType = {{{decodeStage_mmuRsp_allowRead,decodeStage_mmuRsp_allowWrite},decodeStage_mmuRsp_allowExecute},decodeStage_protError}; + assign io_cpu_decode_physicalAddress = decodeStage_mmuRsp_physicalAddress; + always @ (posedge clk or posedge reset) begin + if (reset) begin + lineLoader_valid <= 1'b0; + lineLoader_hadError <= 1'b0; + lineLoader_flushPending <= 1'b1; + lineLoader_cmdSent <= 1'b0; + lineLoader_wordIndex <= (3'b000); + end else begin + if(lineLoader_fire)begin + lineLoader_valid <= 1'b0; + end + if(lineLoader_fire)begin + lineLoader_hadError <= 1'b0; + end + if(io_cpu_fill_valid)begin + lineLoader_valid <= 1'b1; + end + if(io_flush)begin + lineLoader_flushPending <= 1'b1; + end + if(_zz_14_)begin + lineLoader_flushPending <= 1'b0; + end + if((io_mem_cmd_valid && io_mem_cmd_ready))begin + lineLoader_cmdSent <= 1'b1; + end + if(lineLoader_fire)begin + lineLoader_cmdSent <= 1'b0; + end + if(io_mem_rsp_valid)begin + lineLoader_wordIndex <= (lineLoader_wordIndex + (3'b001)); + if(io_mem_rsp_payload_error)begin + lineLoader_hadError <= 1'b1; + end + end + end + end + + always @ (posedge clk) begin + if(io_cpu_fill_valid)begin + lineLoader_address <= io_cpu_fill_payload; + end + if(_zz_13_)begin + lineLoader_flushCounter <= (lineLoader_flushCounter + 8'h01); + end + _zz_3_ <= lineLoader_flushCounter[7]; + if(_zz_14_)begin + lineLoader_flushCounter <= 8'h0; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_mmuRsp_physicalAddress <= io_cpu_fetch_mmuBus_rsp_physicalAddress; + decodeStage_mmuRsp_isIoAccess <= io_cpu_fetch_mmuBus_rsp_isIoAccess; + decodeStage_mmuRsp_allowRead <= io_cpu_fetch_mmuBus_rsp_allowRead; + decodeStage_mmuRsp_allowWrite <= io_cpu_fetch_mmuBus_rsp_allowWrite; + decodeStage_mmuRsp_allowExecute <= io_cpu_fetch_mmuBus_rsp_allowExecute; + decodeStage_mmuRsp_exception <= io_cpu_fetch_mmuBus_rsp_exception; + decodeStage_mmuRsp_refilling <= io_cpu_fetch_mmuBus_rsp_refilling; + end + if((! io_cpu_decode_isStuck))begin + decodeStage_hit_tags_0_valid <= fetchStage_read_waysValues_0_tag_valid; + decodeStage_hit_tags_0_error <= fetchStage_read_waysValues_0_tag_error; + decodeStage_hit_tags_0_address <= fetchStage_read_waysValues_0_tag_address; + end + if((! io_cpu_decode_isStuck))begin + _zz_10_ <= fetchStage_read_waysValues_0_data; + end + end + + +endmodule + +module DataCache ( + input io_cpu_execute_isValid, + input [31:0] io_cpu_execute_address, + input io_cpu_execute_args_wr, + input [31:0] io_cpu_execute_args_data, + input [1:0] io_cpu_execute_args_size, + input io_cpu_memory_isValid, + input io_cpu_memory_isStuck, + input io_cpu_memory_isRemoved, + output io_cpu_memory_isWrite, + input [31:0] io_cpu_memory_address, + output io_cpu_memory_mmuBus_cmd_isValid, + output [31:0] io_cpu_memory_mmuBus_cmd_virtualAddress, + output io_cpu_memory_mmuBus_cmd_bypassTranslation, + input [31:0] io_cpu_memory_mmuBus_rsp_physicalAddress, + input io_cpu_memory_mmuBus_rsp_isIoAccess, + input io_cpu_memory_mmuBus_rsp_allowRead, + input io_cpu_memory_mmuBus_rsp_allowWrite, + input io_cpu_memory_mmuBus_rsp_allowExecute, + input io_cpu_memory_mmuBus_rsp_exception, + input io_cpu_memory_mmuBus_rsp_refilling, + output io_cpu_memory_mmuBus_spr_valid, + output [9:0] io_cpu_memory_mmuBus_spr_payload_id, + output [31:0] io_cpu_memory_mmuBus_spr_payload_data, + output io_cpu_memory_mmuBus_end, + input io_cpu_memory_mmuBus_busy, + input io_cpu_memory_bypassTranslation, + input io_cpu_writeBack_isValid, + input io_cpu_writeBack_isStuck, + input io_cpu_writeBack_isUser, + output reg io_cpu_writeBack_haltIt, + output io_cpu_writeBack_isWrite, + output reg [31:0] io_cpu_writeBack_data, + input [31:0] io_cpu_writeBack_address, + output io_cpu_writeBack_mmuException, + output io_cpu_writeBack_unalignedAccess, + output reg io_cpu_writeBack_accessError, + output [3:0] io_cpu_writeBack_exceptionType, + output reg io_cpu_redo, + input io_cpu_flush_valid, + output reg io_cpu_flush_ready, + output reg io_mem_cmd_valid, + input io_mem_cmd_ready, + output reg io_mem_cmd_payload_wr, + output reg [31:0] io_mem_cmd_payload_address, + output [31:0] io_mem_cmd_payload_data, + output [3:0] io_mem_cmd_payload_mask, + output reg [2:0] io_mem_cmd_payload_length, + output reg io_mem_cmd_payload_last, + input io_mem_rsp_valid, + input [31:0] io_mem_rsp_payload_data, + input io_mem_rsp_payload_error, + input clk, + input reset +); + reg [21:0] _zz_10_; + reg [31:0] _zz_11_; + wire _zz_12_; + wire _zz_13_; + wire _zz_14_; + wire _zz_15_; + wire _zz_16_; + wire [0:0] _zz_17_; + wire [0:0] _zz_18_; + wire [0:0] _zz_19_; + wire [2:0] _zz_20_; + wire [1:0] _zz_21_; + wire [21:0] _zz_22_; + reg _zz_1_; + reg _zz_2_; + wire haltCpu; + reg tagsReadCmd_valid; + reg [6:0] tagsReadCmd_payload; + reg tagsWriteCmd_valid; + reg [0:0] tagsWriteCmd_payload_way; + reg [6:0] tagsWriteCmd_payload_address; + reg tagsWriteCmd_payload_data_valid; + reg tagsWriteCmd_payload_data_error; + reg [19:0] tagsWriteCmd_payload_data_address; + reg tagsWriteLastCmd_valid; + reg [0:0] tagsWriteLastCmd_payload_way; + reg [6:0] tagsWriteLastCmd_payload_address; + reg tagsWriteLastCmd_payload_data_valid; + reg tagsWriteLastCmd_payload_data_error; + reg [19:0] tagsWriteLastCmd_payload_data_address; + reg dataReadCmd_valid; + reg [9:0] dataReadCmd_payload; + reg dataWriteCmd_valid; + reg [0:0] dataWriteCmd_payload_way; + reg [9:0] dataWriteCmd_payload_address; + reg [31:0] dataWriteCmd_payload_data; + reg [3:0] dataWriteCmd_payload_mask; + wire _zz_3_; + wire DC_DIR_tagsReadRsp_valid; + wire DC_DIR_tagsReadRsp_error; + wire [19:0] DC_DIR_tagsReadRsp_address; + wire [21:0] _zz_4_; + wire _zz_5_; + wire [31:0] DC_DIR_dataReadRsp; + reg [3:0] _zz_6_; + wire [3:0] stage0_mask; + wire [0:0] stage0_colisions; + reg stageA_request_wr; + reg [31:0] stageA_request_data; + reg [1:0] stageA_request_size; + reg [3:0] stageA_mask; + wire stageA_wayHits_0; + reg [0:0] stage0_colisions_regNextWhen; + wire [0:0] _zz_7_; + wire [0:0] stageA_colisions; + reg stageB_request_wr; + reg [31:0] stageB_request_data; + reg [1:0] stageB_request_size; + reg stageB_mmuRspFreeze; + reg [31:0] stageB_mmuRsp_physicalAddress; + reg stageB_mmuRsp_isIoAccess; + reg stageB_mmuRsp_allowRead; + reg stageB_mmuRsp_allowWrite; + reg stageB_mmuRsp_allowExecute; + reg stageB_mmuRsp_exception; + reg stageB_mmuRsp_refilling; + reg stageB_tagsReadRsp_0_valid; + reg stageB_tagsReadRsp_0_error; + reg [19:0] stageB_tagsReadRsp_0_address; + reg [31:0] stageB_dataReadRsp_0; + wire [0:0] _zz_8_; + reg [0:0] stageB_waysHits; + wire stageB_waysHit; + wire [31:0] stageB_dataMux; + reg [3:0] stageB_mask; + reg [0:0] stageB_colisions; + reg stageB_loaderValid; + reg stageB_flusher_valid; + reg stageB_flusher_start; + wire [31:0] stageB_requestDataBypass; + wire stageB_isAmo; + reg stageB_memCmdSent; + wire stageB_protError; + wire [0:0] _zz_9_; + reg loader_valid; + reg loader_counter_willIncrement; + wire loader_counter_willClear; + reg [2:0] loader_counter_valueNext; + reg [2:0] loader_counter_value; + wire loader_counter_willOverflowIfInc; + wire loader_counter_willOverflow; + reg [0:0] loader_waysAllocator; + reg loader_error; + reg [21:0] DC_DIR_tags [0:127]; + reg [7:0] DC_DIR_data_symbol0 [0:1023]; + reg [7:0] DC_DIR_data_symbol1 [0:1023]; + reg [7:0] DC_DIR_data_symbol2 [0:1023]; + reg [7:0] DC_DIR_data_symbol3 [0:1023]; + reg [7:0] _zz_23_; + reg [7:0] _zz_24_; + reg [7:0] _zz_25_; + reg [7:0] _zz_26_; + + assign _zz_12_ = (io_cpu_execute_isValid && (! io_cpu_memory_isStuck)); + assign _zz_13_ = ((((stageB_mmuRsp_refilling || io_cpu_writeBack_accessError) || io_cpu_writeBack_mmuException) || io_cpu_writeBack_unalignedAccess) || stageB_protError); + assign _zz_14_ = (stageB_waysHit || (stageB_request_wr && (! stageB_isAmo))); + assign _zz_15_ = (loader_valid && io_mem_rsp_valid); + assign _zz_16_ = (stageB_mmuRsp_physicalAddress[11 : 5] != 7'h7f); + assign _zz_17_ = _zz_4_[0 : 0]; + assign _zz_18_ = _zz_4_[1 : 1]; + assign _zz_19_ = loader_counter_willIncrement; + assign _zz_20_ = {2'd0, _zz_19_}; + assign _zz_21_ = {loader_waysAllocator,loader_waysAllocator[0]}; + assign _zz_22_ = {tagsWriteCmd_payload_data_address,{tagsWriteCmd_payload_data_error,tagsWriteCmd_payload_data_valid}}; + always @ (posedge clk) begin + if(_zz_3_) begin + _zz_10_ <= DC_DIR_tags[tagsReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(_zz_2_) begin + DC_DIR_tags[tagsWriteCmd_payload_address] <= _zz_22_; + end + end + + always @ (*) begin + _zz_11_ = {_zz_26_, _zz_25_, _zz_24_, _zz_23_}; + end + always @ (posedge clk) begin + if(_zz_5_) begin + _zz_23_ <= DC_DIR_data_symbol0[dataReadCmd_payload]; + _zz_24_ <= DC_DIR_data_symbol1[dataReadCmd_payload]; + _zz_25_ <= DC_DIR_data_symbol2[dataReadCmd_payload]; + _zz_26_ <= DC_DIR_data_symbol3[dataReadCmd_payload]; + end + end + + always @ (posedge clk) begin + if(dataWriteCmd_payload_mask[0] && _zz_1_) begin + DC_DIR_data_symbol0[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[7 : 0]; + end + if(dataWriteCmd_payload_mask[1] && _zz_1_) begin + DC_DIR_data_symbol1[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[15 : 8]; + end + if(dataWriteCmd_payload_mask[2] && _zz_1_) begin + DC_DIR_data_symbol2[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[23 : 16]; + end + if(dataWriteCmd_payload_mask[3] && _zz_1_) begin + DC_DIR_data_symbol3[dataWriteCmd_payload_address] <= dataWriteCmd_payload_data[31 : 24]; + end + end + + always @ (*) begin + _zz_1_ = 1'b0; + if((dataWriteCmd_valid && dataWriteCmd_payload_way[0]))begin + _zz_1_ = 1'b1; + end + end + + always @ (*) begin + _zz_2_ = 1'b0; + if((tagsWriteCmd_valid && tagsWriteCmd_payload_way[0]))begin + _zz_2_ = 1'b1; + end + end + + assign haltCpu = 1'b0; + assign _zz_3_ = (tagsReadCmd_valid && (! io_cpu_memory_isStuck)); + assign _zz_4_ = _zz_10_; + assign DC_DIR_tagsReadRsp_valid = _zz_17_[0]; + assign DC_DIR_tagsReadRsp_error = _zz_18_[0]; + assign DC_DIR_tagsReadRsp_address = _zz_4_[21 : 2]; + assign _zz_5_ = (dataReadCmd_valid && (! io_cpu_memory_isStuck)); + assign DC_DIR_dataReadRsp = _zz_11_; + always @ (*) begin + tagsReadCmd_valid = 1'b0; + if(_zz_12_)begin + tagsReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsReadCmd_payload = 7'h0; + if(_zz_12_)begin + tagsReadCmd_payload = io_cpu_execute_address[11 : 5]; + end + end + + always @ (*) begin + dataReadCmd_valid = 1'b0; + if(_zz_12_)begin + dataReadCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataReadCmd_payload = 10'h0; + if(_zz_12_)begin + dataReadCmd_payload = io_cpu_execute_address[11 : 2]; + end + end + + always @ (*) begin + tagsWriteCmd_valid = 1'b0; + if(stageB_flusher_valid)begin + tagsWriteCmd_valid = stageB_flusher_valid; + end + if(_zz_13_)begin + tagsWriteCmd_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_way = (1'bx); + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_way = (1'b1); + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + tagsWriteCmd_payload_address = 7'h0; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 5]; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_valid = 1'bx; + if(stageB_flusher_valid)begin + tagsWriteCmd_payload_data_valid = 1'b0; + end + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_valid = 1'b1; + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_error = 1'bx; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_error = (loader_error || io_mem_rsp_payload_error); + end + end + + always @ (*) begin + tagsWriteCmd_payload_data_address = 20'h0; + if(loader_counter_willOverflow)begin + tagsWriteCmd_payload_data_address = stageB_mmuRsp_physicalAddress[31 : 12]; + end + end + + always @ (*) begin + dataWriteCmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((stageB_request_wr && stageB_waysHit))begin + dataWriteCmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + dataWriteCmd_valid = 1'b0; + end + if(_zz_15_)begin + dataWriteCmd_valid = 1'b1; + end + end + + always @ (*) begin + dataWriteCmd_payload_way = (1'bx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_way = stageB_waysHits; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_way = loader_waysAllocator; + end + end + + always @ (*) begin + dataWriteCmd_payload_address = 10'h0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_address = stageB_mmuRsp_physicalAddress[11 : 2]; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_address = {stageB_mmuRsp_physicalAddress[11 : 5],loader_counter_value}; + end + end + + always @ (*) begin + dataWriteCmd_payload_data = 32'h0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_data = stageB_requestDataBypass; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_data = io_mem_rsp_payload_data; + end + end + + always @ (*) begin + dataWriteCmd_payload_mask = (4'bxxxx); + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + dataWriteCmd_payload_mask = stageB_mask; + end + end + end + if(_zz_15_)begin + dataWriteCmd_payload_mask = (4'b1111); + end + end + + always @ (*) begin + case(io_cpu_execute_args_size) + 2'b00 : begin + _zz_6_ = (4'b1000); + end + 2'b01 : begin + _zz_6_ = (4'b1100); + end + default : begin + _zz_6_ = (4'b1111); + end + endcase + end + + assign stage0_mask = (_zz_6_ >>> io_cpu_execute_address[1 : 0]); + assign stage0_colisions[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_execute_address[11 : 2])) && ((stage0_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign io_cpu_memory_mmuBus_cmd_isValid = io_cpu_memory_isValid; + assign io_cpu_memory_mmuBus_cmd_virtualAddress = io_cpu_memory_address; + assign io_cpu_memory_mmuBus_cmd_bypassTranslation = io_cpu_memory_bypassTranslation; + assign io_cpu_memory_mmuBus_end = ((! io_cpu_memory_isStuck) || io_cpu_memory_isRemoved); + assign io_cpu_memory_mmuBus_spr_valid = 1'b0; + assign io_cpu_memory_mmuBus_spr_payload_id = 10'h0; + assign io_cpu_memory_mmuBus_spr_payload_data = 32'h0; + assign io_cpu_memory_isWrite = stageA_request_wr; + assign stageA_wayHits_0 = ((io_cpu_memory_mmuBus_rsp_physicalAddress[31 : 12] == DC_DIR_tagsReadRsp_address) && DC_DIR_tagsReadRsp_valid); + assign _zz_7_[0] = (((dataWriteCmd_valid && dataWriteCmd_payload_way[0]) && (dataWriteCmd_payload_address == io_cpu_memory_address[11 : 2])) && ((stageA_mask & dataWriteCmd_payload_mask) != (4'b0000))); + assign stageA_colisions = (stage0_colisions_regNextWhen | _zz_7_); + always @ (*) begin + stageB_mmuRspFreeze = 1'b0; + if((stageB_loaderValid || loader_valid))begin + stageB_mmuRspFreeze = 1'b1; + end + end + + assign _zz_8_[0] = stageA_wayHits_0; + assign stageB_waysHit = (stageB_waysHits != (1'b0)); + assign stageB_dataMux = stageB_dataReadRsp_0; + always @ (*) begin + stageB_loaderValid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + if(io_mem_cmd_ready)begin + stageB_loaderValid = 1'b1; + end + end + end + end + if(_zz_13_)begin + stageB_loaderValid = 1'b0; + end + end + + always @ (*) begin + io_cpu_writeBack_haltIt = io_cpu_writeBack_isValid; + if(stageB_flusher_valid)begin + io_cpu_writeBack_haltIt = 1'b1; + end + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + if((stageB_request_wr ? io_mem_cmd_ready : io_mem_rsp_valid))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end else begin + if(_zz_14_)begin + if(((! stageB_request_wr) || io_mem_cmd_ready))begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + end + end + if(_zz_13_)begin + io_cpu_writeBack_haltIt = 1'b0; + end + end + + always @ (*) begin + io_cpu_flush_ready = 1'b0; + if(stageB_flusher_start)begin + io_cpu_flush_ready = 1'b1; + end + end + + assign stageB_requestDataBypass = stageB_request_data; + assign stageB_isAmo = 1'b0; + always @ (*) begin + io_cpu_redo = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(_zz_14_)begin + if((((! stageB_request_wr) || stageB_isAmo) && ((stageB_colisions & stageB_waysHits) != (1'b0))))begin + io_cpu_redo = 1'b1; + end + end + end + end + if((io_cpu_writeBack_isValid && stageB_mmuRsp_refilling))begin + io_cpu_redo = 1'b1; + end + if(loader_valid)begin + io_cpu_redo = 1'b1; + end + end + + always @ (*) begin + io_cpu_writeBack_accessError = 1'b0; + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_accessError = (io_mem_rsp_valid && io_mem_rsp_payload_error); + end else begin + io_cpu_writeBack_accessError = ((stageB_waysHits & _zz_9_) != (1'b0)); + end + end + + assign io_cpu_writeBack_mmuException = (io_cpu_writeBack_isValid && stageB_mmuRsp_exception); + assign io_cpu_writeBack_unalignedAccess = (io_cpu_writeBack_isValid && (((stageB_request_size == (2'b10)) && (stageB_mmuRsp_physicalAddress[1 : 0] != (2'b00))) || ((stageB_request_size == (2'b01)) && (stageB_mmuRsp_physicalAddress[0 : 0] != (1'b0))))); + assign io_cpu_writeBack_isWrite = stageB_request_wr; + assign stageB_protError = (io_cpu_writeBack_isValid && ((! stageB_mmuRsp_refilling) && (((! stageB_mmuRsp_allowRead) && (! stageB_request_wr)) || ((! stageB_mmuRsp_allowWrite) && stageB_request_wr)))); + assign io_cpu_writeBack_exceptionType = {{{stageB_mmuRsp_allowRead,stageB_mmuRsp_allowWrite},stageB_mmuRsp_allowExecute},stageB_protError}; + always @ (*) begin + io_mem_cmd_valid = 1'b0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_valid = (! stageB_memCmdSent); + end else begin + if(_zz_14_)begin + if(stageB_request_wr)begin + io_mem_cmd_valid = 1'b1; + end + end else begin + if((! stageB_memCmdSent))begin + io_mem_cmd_valid = 1'b1; + end + end + end + end + if(_zz_13_)begin + io_mem_cmd_valid = 1'b0; + end + end + + always @ (*) begin + io_mem_cmd_payload_address = 32'h0; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 2],(2'b00)}; + end else begin + io_mem_cmd_payload_address = {stageB_mmuRsp_physicalAddress[31 : 5],5'h0}; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_length = (3'bxxx); + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_length = (3'b000); + end else begin + io_mem_cmd_payload_length = (3'b111); + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_last = 1'bx; + if(io_cpu_writeBack_isValid)begin + if(stageB_mmuRsp_isIoAccess)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + if(_zz_14_)begin + io_mem_cmd_payload_last = 1'b1; + end else begin + io_mem_cmd_payload_last = 1'b1; + end + end + end + end + + always @ (*) begin + io_mem_cmd_payload_wr = stageB_request_wr; + if(io_cpu_writeBack_isValid)begin + if(! stageB_mmuRsp_isIoAccess) begin + if(! _zz_14_) begin + io_mem_cmd_payload_wr = 1'b0; + end + end + end + end + + assign io_mem_cmd_payload_mask = stageB_mask; + assign io_mem_cmd_payload_data = stageB_requestDataBypass; + always @ (*) begin + if(stageB_mmuRsp_isIoAccess)begin + io_cpu_writeBack_data = io_mem_rsp_payload_data; + end else begin + io_cpu_writeBack_data = stageB_dataMux; + end + end + + assign _zz_9_[0] = stageB_tagsReadRsp_0_error; + always @ (*) begin + loader_counter_willIncrement = 1'b0; + if(_zz_15_)begin + loader_counter_willIncrement = 1'b1; + end + end + + assign loader_counter_willClear = 1'b0; + assign loader_counter_willOverflowIfInc = (loader_counter_value == (3'b111)); + assign loader_counter_willOverflow = (loader_counter_willOverflowIfInc && loader_counter_willIncrement); + always @ (*) begin + loader_counter_valueNext = (loader_counter_value + _zz_20_); + if(loader_counter_willClear)begin + loader_counter_valueNext = (3'b000); + end + end + + always @ (posedge clk) begin + tagsWriteLastCmd_valid <= tagsWriteCmd_valid; + tagsWriteLastCmd_payload_way <= tagsWriteCmd_payload_way; + tagsWriteLastCmd_payload_address <= tagsWriteCmd_payload_address; + tagsWriteLastCmd_payload_data_valid <= tagsWriteCmd_payload_data_valid; + tagsWriteLastCmd_payload_data_error <= tagsWriteCmd_payload_data_error; + tagsWriteLastCmd_payload_data_address <= tagsWriteCmd_payload_data_address; + if((! io_cpu_memory_isStuck))begin + stageA_request_wr <= io_cpu_execute_args_wr; + stageA_request_data <= io_cpu_execute_args_data; + stageA_request_size <= io_cpu_execute_args_size; + end + if((! io_cpu_memory_isStuck))begin + stageA_mask <= stage0_mask; + end + if((! io_cpu_memory_isStuck))begin + stage0_colisions_regNextWhen <= stage0_colisions; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_request_wr <= stageA_request_wr; + stageB_request_data <= stageA_request_data; + stageB_request_size <= stageA_request_size; + end + if(((! io_cpu_writeBack_isStuck) && (! stageB_mmuRspFreeze)))begin + stageB_mmuRsp_physicalAddress <= io_cpu_memory_mmuBus_rsp_physicalAddress; + stageB_mmuRsp_isIoAccess <= io_cpu_memory_mmuBus_rsp_isIoAccess; + stageB_mmuRsp_allowRead <= io_cpu_memory_mmuBus_rsp_allowRead; + stageB_mmuRsp_allowWrite <= io_cpu_memory_mmuBus_rsp_allowWrite; + stageB_mmuRsp_allowExecute <= io_cpu_memory_mmuBus_rsp_allowExecute; + stageB_mmuRsp_exception <= io_cpu_memory_mmuBus_rsp_exception; + stageB_mmuRsp_refilling <= io_cpu_memory_mmuBus_rsp_refilling; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_tagsReadRsp_0_valid <= DC_DIR_tagsReadRsp_valid; + stageB_tagsReadRsp_0_error <= DC_DIR_tagsReadRsp_error; + stageB_tagsReadRsp_0_address <= DC_DIR_tagsReadRsp_address; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_dataReadRsp_0 <= DC_DIR_dataReadRsp; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_waysHits <= _zz_8_; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_mask <= stageA_mask; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_colisions <= stageA_colisions; + end + if(stageB_flusher_valid)begin + if(_zz_16_)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= (stageB_mmuRsp_physicalAddress[11 : 5] + 7'h01); + end + end + if(stageB_flusher_start)begin + stageB_mmuRsp_physicalAddress[11 : 5] <= 7'h0; + end + end + + always @ (posedge clk or posedge reset) begin + if (reset) begin + stageB_flusher_valid <= 1'b0; + stageB_flusher_start <= 1'b1; + stageB_memCmdSent <= 1'b0; + loader_valid <= 1'b0; + loader_counter_value <= (3'b000); + loader_waysAllocator <= (1'b1); + loader_error <= 1'b0; + end else begin + if(stageB_flusher_valid)begin + if(! _zz_16_) begin + stageB_flusher_valid <= 1'b0; + end + end + stageB_flusher_start <= ((((((! stageB_flusher_start) && io_cpu_flush_valid) && (! io_cpu_execute_isValid)) && (! io_cpu_memory_isValid)) && (! io_cpu_writeBack_isValid)) && (! io_cpu_redo)); + if(stageB_flusher_start)begin + stageB_flusher_valid <= 1'b1; + end + if(io_mem_cmd_ready)begin + stageB_memCmdSent <= 1'b1; + end + if((! io_cpu_writeBack_isStuck))begin + stageB_memCmdSent <= 1'b0; + end + if(stageB_loaderValid)begin + loader_valid <= 1'b1; + end + loader_counter_value <= loader_counter_valueNext; + if(_zz_15_)begin + loader_error <= (loader_error || io_mem_rsp_payload_error); + end + if(loader_counter_willOverflow)begin + loader_valid <= 1'b0; + loader_error <= 1'b0; + end + if((! loader_valid))begin + loader_waysAllocator <= _zz_21_[0:0]; + end + end + end + + +endmodule + +module A2P_WB ( + input [31:0] externalResetVector, + input timerInterrupt, + input externalInterrupt, + input softwareInterrupt, + input externalInterruptS, + output reg iBusWB_CYC /* verilator public */ , + output reg iBusWB_STB /* verilator public */ , + input iBusWB_ACK /* verilator public */ , + output iBusWB_WE /* verilator public */ , + output [29:0] iBusWB_ADR /* verilator public */ , + input [31:0] iBusWB_DAT_MISO /* verilator public */ , + output [31:0] iBusWB_DAT_MOSI /* verilator public */ , + output [3:0] iBusWB_SEL /* verilator public */ , + input iBusWB_ERR /* verilator public */ , + output [1:0] iBusWB_BTE /* verilator public */ , + output [2:0] iBusWB_CTI /* verilator public */ , + output dBusWB_CYC /* verilator public */ , + output dBusWB_STB /* verilator public */ , + input dBusWB_ACK /* verilator public */ , + output dBusWB_WE /* verilator public */ , + output [29:0] dBusWB_ADR /* verilator public */ , + input [31:0] dBusWB_DAT_MISO /* verilator public */ , + output [31:0] dBusWB_DAT_MOSI /* verilator public */ , + output [3:0] dBusWB_SEL /* verilator public */ , + input dBusWB_ERR /* verilator public */ , + output [1:0] dBusWB_BTE /* verilator public */ , + output [2:0] dBusWB_CTI /* verilator public */ , + input clk, + input reset +); + wire _zz_367_; + wire _zz_368_; + wire _zz_369_; + wire _zz_370_; + wire _zz_371_; + wire _zz_372_; + wire _zz_373_; + wire _zz_374_; + reg _zz_375_; + wire [9:0] _zz_376_; + wire _zz_377_; + wire [31:0] _zz_378_; + reg [31:0] _zz_379_; + wire _zz_380_; + wire [31:0] _zz_381_; + reg _zz_382_; + wire _zz_383_; + wire _zz_384_; + wire _zz_385_; + wire [31:0] _zz_386_; + wire _zz_387_; + wire _zz_388_; + reg [53:0] _zz_389_; + reg [31:0] _zz_390_; + reg [31:0] _zz_391_; + reg [31:0] _zz_392_; + reg [31:0] _zz_393_; + wire IBusCachedPlugin_cache_io_cpu_prefetch_haltIt; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_data; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_haltIt; + wire [3:0] IBusCachedPlugin_cache_io_cpu_fetch_exceptionType; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + wire IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid; + wire [9:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id; + wire [31:0] IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data; + wire IBusCachedPlugin_cache_io_cpu_decode_error; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling; + wire IBusCachedPlugin_cache_io_cpu_decode_mmuException; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_data; + wire IBusCachedPlugin_cache_io_cpu_decode_cacheMiss; + wire [31:0] IBusCachedPlugin_cache_io_cpu_decode_physicalAddress; + wire [3:0] IBusCachedPlugin_cache_io_cpu_decode_exceptionType; + wire IBusCachedPlugin_cache_io_mem_cmd_valid; + wire [31:0] IBusCachedPlugin_cache_io_mem_cmd_payload_address; + wire [2:0] IBusCachedPlugin_cache_io_mem_cmd_payload_size; + wire dataCache_1__io_cpu_memory_isWrite; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + wire dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + wire dataCache_1__io_cpu_memory_mmuBus_end; + wire dataCache_1__io_cpu_memory_mmuBus_spr_valid; + wire [9:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_id; + wire [31:0] dataCache_1__io_cpu_memory_mmuBus_spr_payload_data; + wire dataCache_1__io_cpu_writeBack_haltIt; + wire [31:0] dataCache_1__io_cpu_writeBack_data; + wire dataCache_1__io_cpu_writeBack_mmuException; + wire dataCache_1__io_cpu_writeBack_unalignedAccess; + wire dataCache_1__io_cpu_writeBack_accessError; + wire dataCache_1__io_cpu_writeBack_isWrite; + wire [3:0] dataCache_1__io_cpu_writeBack_exceptionType; + wire dataCache_1__io_cpu_flush_ready; + wire dataCache_1__io_cpu_redo; + wire dataCache_1__io_mem_cmd_valid; + wire dataCache_1__io_mem_cmd_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_payload_length; + wire dataCache_1__io_mem_cmd_payload_last; + wire _zz_394_; + wire _zz_395_; + wire _zz_396_; + wire _zz_397_; + wire _zz_398_; + wire _zz_399_; + wire _zz_400_; + wire _zz_401_; + wire _zz_402_; + wire _zz_403_; + wire _zz_404_; + wire _zz_405_; + wire _zz_406_; + wire _zz_407_; + wire _zz_408_; + wire _zz_409_; + wire _zz_410_; + wire _zz_411_; + wire _zz_412_; + wire _zz_413_; + wire _zz_414_; + wire _zz_415_; + wire _zz_416_; + wire _zz_417_; + wire _zz_418_; + wire _zz_419_; + wire _zz_420_; + wire _zz_421_; + wire _zz_422_; + wire _zz_423_; + wire _zz_424_; + wire _zz_425_; + wire _zz_426_; + wire _zz_427_; + wire _zz_428_; + wire _zz_429_; + wire _zz_430_; + wire _zz_431_; + wire _zz_432_; + wire _zz_433_; + wire _zz_434_; + wire _zz_435_; + wire _zz_436_; + wire _zz_437_; + wire _zz_438_; + wire _zz_439_; + wire _zz_440_; + wire [7:0] _zz_441_; + wire [2:0] _zz_442_; + wire [2:0] _zz_443_; + wire [1:0] _zz_444_; + wire [1:0] _zz_445_; + wire [2:0] _zz_446_; + wire [0:0] _zz_447_; + wire [0:0] _zz_448_; + wire [0:0] _zz_449_; + wire [0:0] _zz_450_; + wire [0:0] _zz_451_; + wire [0:0] _zz_452_; + wire [0:0] _zz_453_; + wire [0:0] _zz_454_; + wire [0:0] _zz_455_; + wire [0:0] _zz_456_; + wire [0:0] _zz_457_; + wire [0:0] _zz_458_; + wire [0:0] _zz_459_; + wire [0:0] _zz_460_; + wire [0:0] _zz_461_; + wire [0:0] _zz_462_; + wire [0:0] _zz_463_; + wire [0:0] _zz_464_; + wire [0:0] _zz_465_; + wire [0:0] _zz_466_; + wire [0:0] _zz_467_; + wire [51:0] _zz_468_; + wire [51:0] _zz_469_; + wire [51:0] _zz_470_; + wire [32:0] _zz_471_; + wire [51:0] _zz_472_; + wire [49:0] _zz_473_; + wire [51:0] _zz_474_; + wire [49:0] _zz_475_; + wire [51:0] _zz_476_; + wire [0:0] _zz_477_; + wire [0:0] _zz_478_; + wire [0:0] _zz_479_; + wire [0:0] _zz_480_; + wire [0:0] _zz_481_; + wire [0:0] _zz_482_; + wire [0:0] _zz_483_; + wire [0:0] _zz_484_; + wire [0:0] _zz_485_; + wire [0:0] _zz_486_; + wire [0:0] _zz_487_; + wire [0:0] _zz_488_; + wire [0:0] _zz_489_; + wire [0:0] _zz_490_; + wire [0:0] _zz_491_; + wire [0:0] _zz_492_; + wire [0:0] _zz_493_; + wire [0:0] _zz_494_; + wire [0:0] _zz_495_; + wire [0:0] _zz_496_; + wire [0:0] _zz_497_; + wire [2:0] _zz_498_; + wire [2:0] _zz_499_; + wire [31:0] _zz_500_; + wire [9:0] _zz_501_; + wire [29:0] _zz_502_; + wire [9:0] _zz_503_; + wire [19:0] _zz_504_; + wire [1:0] _zz_505_; + wire [0:0] _zz_506_; + wire [1:0] _zz_507_; + wire [0:0] _zz_508_; + wire [1:0] _zz_509_; + wire [1:0] _zz_510_; + wire [0:0] _zz_511_; + wire [1:0] _zz_512_; + wire [0:0] _zz_513_; + wire [1:0] _zz_514_; + wire [2:0] _zz_515_; + wire [2:0] _zz_516_; + wire [10:0] _zz_517_; + wire [31:0] _zz_518_; + wire [10:0] _zz_519_; + wire [31:0] _zz_520_; + wire [31:0] _zz_521_; + wire [31:0] _zz_522_; + wire [31:0] _zz_523_; + wire [31:0] _zz_524_; + wire [31:0] _zz_525_; + wire [31:0] _zz_526_; + wire [5:0] _zz_527_; + wire [5:0] _zz_528_; + wire [31:0] _zz_529_; + wire [31:0] _zz_530_; + wire [31:0] _zz_531_; + wire [31:0] _zz_532_; + wire [31:0] _zz_533_; + wire [31:0] _zz_534_; + wire [31:0] _zz_535_; + wire [31:0] _zz_536_; + wire [31:0] _zz_537_; + wire [31:0] _zz_538_; + wire [31:0] _zz_539_; + wire [31:0] _zz_540_; + wire [31:0] _zz_541_; + wire [31:0] _zz_542_; + wire [31:0] _zz_543_; + wire [31:0] _zz_544_; + wire [31:0] _zz_545_; + wire [31:0] _zz_546_; + wire [31:0] _zz_547_; + wire [31:0] _zz_548_; + wire [31:0] _zz_549_; + wire [31:0] _zz_550_; + wire [31:0] _zz_551_; + wire [31:0] _zz_552_; + wire [31:0] _zz_553_; + wire [4:0] _zz_554_; + wire [2:0] _zz_555_; + wire [31:0] _zz_556_; + wire [31:0] _zz_557_; + wire [31:0] _zz_558_; + wire [32:0] _zz_559_; + wire [32:0] _zz_560_; + wire [31:0] _zz_561_; + wire [31:0] _zz_562_; + wire [65:0] _zz_563_; + wire [65:0] _zz_564_; + wire [31:0] _zz_565_; + wire [31:0] _zz_566_; + wire [0:0] _zz_567_; + wire [5:0] _zz_568_; + wire [32:0] _zz_569_; + wire [31:0] _zz_570_; + wire [31:0] _zz_571_; + wire [32:0] _zz_572_; + wire [32:0] _zz_573_; + wire [32:0] _zz_574_; + wire [32:0] _zz_575_; + wire [0:0] _zz_576_; + wire [32:0] _zz_577_; + wire [0:0] _zz_578_; + wire [32:0] _zz_579_; + wire [0:0] _zz_580_; + wire [31:0] _zz_581_; + wire [4:0] _zz_582_; + wire [4:0] _zz_583_; + wire [4:0] _zz_584_; + wire [4:0] _zz_585_; + wire [4:0] _zz_586_; + wire [4:0] _zz_587_; + wire [4:0] _zz_588_; + wire [4:0] _zz_589_; + wire [4:0] _zz_590_; + wire [4:0] _zz_591_; + wire [4:0] _zz_592_; + wire [4:0] _zz_593_; + wire [4:0] _zz_594_; + wire [4:0] _zz_595_; + wire [4:0] _zz_596_; + wire [4:0] _zz_597_; + wire [4:0] _zz_598_; + wire [4:0] _zz_599_; + wire [4:0] _zz_600_; + wire [4:0] _zz_601_; + wire [4:0] _zz_602_; + wire [4:0] _zz_603_; + wire [4:0] _zz_604_; + wire [4:0] _zz_605_; + wire [31:0] _zz_606_; + wire [31:0] _zz_607_; + wire [31:0] _zz_608_; + wire [31:0] _zz_609_; + wire [1:0] _zz_610_; + wire [4:0] _zz_611_; + wire [1:0] _zz_612_; + wire [4:0] _zz_613_; + wire [4:0] _zz_614_; + wire [1:0] _zz_615_; + wire [4:0] _zz_616_; + wire [4:0] _zz_617_; + wire [1:0] _zz_618_; + wire [4:0] _zz_619_; + wire [4:0] _zz_620_; + wire [1:0] _zz_621_; + wire [4:0] _zz_622_; + wire [3:0] _zz_623_; + wire [1:0] _zz_624_; + wire [3:0] _zz_625_; + wire [3:0] _zz_626_; + wire [1:0] _zz_627_; + wire [3:0] _zz_628_; + wire [2:0] _zz_629_; + wire [1:0] _zz_630_; + wire [2:0] _zz_631_; + wire [1:0] _zz_632_; + wire [1:0] _zz_633_; + wire [1:0] _zz_634_; + wire [1:0] _zz_635_; + wire [31:0] _zz_636_; + wire [31:0] _zz_637_; + wire [31:0] _zz_638_; + wire [31:0] _zz_639_; + wire [31:0] _zz_640_; + wire [31:0] _zz_641_; + wire [31:0] _zz_642_; + wire [31:0] _zz_643_; + wire [0:0] _zz_644_; + wire [0:0] _zz_645_; + wire [0:0] _zz_646_; + wire [0:0] _zz_647_; + wire [0:0] _zz_648_; + wire [0:0] _zz_649_; + wire [0:0] _zz_650_; + wire [0:0] _zz_651_; + wire [0:0] _zz_652_; + wire [0:0] _zz_653_; + wire [0:0] _zz_654_; + wire [0:0] _zz_655_; + wire [0:0] _zz_656_; + wire [26:0] _zz_657_; + wire [53:0] _zz_658_; + wire _zz_659_; + wire _zz_660_; + wire _zz_661_; + wire [1:0] _zz_662_; + wire [0:0] _zz_663_; + wire [92:0] _zz_664_; + wire [0:0] _zz_665_; + wire [84:0] _zz_666_; + wire [31:0] _zz_667_; + wire _zz_668_; + wire [0:0] _zz_669_; + wire [75:0] _zz_670_; + wire [31:0] _zz_671_; + wire [31:0] _zz_672_; + wire _zz_673_; + wire [0:0] _zz_674_; + wire [68:0] _zz_675_; + wire [31:0] _zz_676_; + wire [31:0] _zz_677_; + wire [31:0] _zz_678_; + wire _zz_679_; + wire [0:0] _zz_680_; + wire [62:0] _zz_681_; + wire [31:0] _zz_682_; + wire [31:0] _zz_683_; + wire [31:0] _zz_684_; + wire _zz_685_; + wire [0:0] _zz_686_; + wire [56:0] _zz_687_; + wire [31:0] _zz_688_; + wire [31:0] _zz_689_; + wire [31:0] _zz_690_; + wire _zz_691_; + wire [0:0] _zz_692_; + wire [50:0] _zz_693_; + wire [31:0] _zz_694_; + wire [31:0] _zz_695_; + wire [31:0] _zz_696_; + wire _zz_697_; + wire [0:0] _zz_698_; + wire [44:0] _zz_699_; + wire [31:0] _zz_700_; + wire [31:0] _zz_701_; + wire [31:0] _zz_702_; + wire _zz_703_; + wire [0:0] _zz_704_; + wire [38:0] _zz_705_; + wire [31:0] _zz_706_; + wire [31:0] _zz_707_; + wire [31:0] _zz_708_; + wire _zz_709_; + wire [0:0] _zz_710_; + wire [32:0] _zz_711_; + wire [31:0] _zz_712_; + wire [31:0] _zz_713_; + wire [31:0] _zz_714_; + wire _zz_715_; + wire [0:0] _zz_716_; + wire [26:0] _zz_717_; + wire [31:0] _zz_718_; + wire [31:0] _zz_719_; + wire [31:0] _zz_720_; + wire _zz_721_; + wire [0:0] _zz_722_; + wire [20:0] _zz_723_; + wire [31:0] _zz_724_; + wire [31:0] _zz_725_; + wire [31:0] _zz_726_; + wire _zz_727_; + wire [0:0] _zz_728_; + wire [14:0] _zz_729_; + wire [31:0] _zz_730_; + wire [31:0] _zz_731_; + wire [31:0] _zz_732_; + wire _zz_733_; + wire [0:0] _zz_734_; + wire [8:0] _zz_735_; + wire [31:0] _zz_736_; + wire [31:0] _zz_737_; + wire [31:0] _zz_738_; + wire _zz_739_; + wire [0:0] _zz_740_; + wire [2:0] _zz_741_; + wire [31:0] _zz_742_; + wire [31:0] _zz_743_; + wire _zz_744_; + wire [0:0] _zz_745_; + wire [0:0] _zz_746_; + wire _zz_747_; + wire _zz_748_; + wire [3:0] _zz_749_; + wire [3:0] _zz_750_; + wire _zz_751_; + wire [0:0] _zz_752_; + wire [73:0] _zz_753_; + wire [31:0] _zz_754_; + wire [0:0] _zz_755_; + wire [0:0] _zz_756_; + wire _zz_757_; + wire [0:0] _zz_758_; + wire [5:0] _zz_759_; + wire [0:0] _zz_760_; + wire [18:0] _zz_761_; + wire [0:0] _zz_762_; + wire [0:0] _zz_763_; + wire _zz_764_; + wire [0:0] _zz_765_; + wire [70:0] _zz_766_; + wire [31:0] _zz_767_; + wire [31:0] _zz_768_; + wire [31:0] _zz_769_; + wire [31:0] _zz_770_; + wire [31:0] _zz_771_; + wire _zz_772_; + wire [0:0] _zz_773_; + wire [3:0] _zz_774_; + wire [31:0] _zz_775_; + wire [31:0] _zz_776_; + wire [0:0] _zz_777_; + wire [16:0] _zz_778_; + wire [31:0] _zz_779_; + wire [31:0] _zz_780_; + wire _zz_781_; + wire [19:0] _zz_782_; + wire [19:0] _zz_783_; + wire _zz_784_; + wire [0:0] _zz_785_; + wire [68:0] _zz_786_; + wire [31:0] _zz_787_; + wire [31:0] _zz_788_; + wire [31:0] _zz_789_; + wire _zz_790_; + wire [0:0] _zz_791_; + wire [1:0] _zz_792_; + wire [0:0] _zz_793_; + wire [14:0] _zz_794_; + wire [31:0] _zz_795_; + wire _zz_796_; + wire [0:0] _zz_797_; + wire [17:0] _zz_798_; + wire [3:0] _zz_799_; + wire [3:0] _zz_800_; + wire _zz_801_; + wire [0:0] _zz_802_; + wire [66:0] _zz_803_; + wire [31:0] _zz_804_; + wire [31:0] _zz_805_; + wire [31:0] _zz_806_; + wire _zz_807_; + wire _zz_808_; + wire [0:0] _zz_809_; + wire [12:0] _zz_810_; + wire [31:0] _zz_811_; + wire [31:0] _zz_812_; + wire [31:0] _zz_813_; + wire _zz_814_; + wire [0:0] _zz_815_; + wire [15:0] _zz_816_; + wire _zz_817_; + wire [0:0] _zz_818_; + wire [1:0] _zz_819_; + wire [0:0] _zz_820_; + wire [2:0] _zz_821_; + wire [3:0] _zz_822_; + wire [3:0] _zz_823_; + wire _zz_824_; + wire [0:0] _zz_825_; + wire [64:0] _zz_826_; + wire [31:0] _zz_827_; + wire [31:0] _zz_828_; + wire [0:0] _zz_829_; + wire [10:0] _zz_830_; + wire [31:0] _zz_831_; + wire [0:0] _zz_832_; + wire [13:0] _zz_833_; + wire [31:0] _zz_834_; + wire _zz_835_; + wire _zz_836_; + wire [0:0] _zz_837_; + wire [0:0] _zz_838_; + wire [0:0] _zz_839_; + wire [1:0] _zz_840_; + wire [0:0] _zz_841_; + wire [0:0] _zz_842_; + wire [8:0] _zz_843_; + wire [8:0] _zz_844_; + wire _zz_845_; + wire [0:0] _zz_846_; + wire [62:0] _zz_847_; + wire [0:0] _zz_848_; + wire [8:0] _zz_849_; + wire [0:0] _zz_850_; + wire [11:0] _zz_851_; + wire [31:0] _zz_852_; + wire [31:0] _zz_853_; + wire [31:0] _zz_854_; + wire [31:0] _zz_855_; + wire [31:0] _zz_856_; + wire [31:0] _zz_857_; + wire _zz_858_; + wire [0:0] _zz_859_; + wire [6:0] _zz_860_; + wire [0:0] _zz_861_; + wire [1:0] _zz_862_; + wire [24:0] _zz_863_; + wire [24:0] _zz_864_; + wire _zz_865_; + wire [0:0] _zz_866_; + wire [60:0] _zz_867_; + wire [0:0] _zz_868_; + wire [6:0] _zz_869_; + wire _zz_870_; + wire [0:0] _zz_871_; + wire [9:0] _zz_872_; + wire [31:0] _zz_873_; + wire [31:0] _zz_874_; + wire [31:0] _zz_875_; + wire _zz_876_; + wire [0:0] _zz_877_; + wire [4:0] _zz_878_; + wire [31:0] _zz_879_; + wire [31:0] _zz_880_; + wire _zz_881_; + wire _zz_882_; + wire _zz_883_; + wire [0:0] _zz_884_; + wire [22:0] _zz_885_; + wire [0:0] _zz_886_; + wire [0:0] _zz_887_; + wire [1:0] _zz_888_; + wire [1:0] _zz_889_; + wire _zz_890_; + wire [0:0] _zz_891_; + wire [58:0] _zz_892_; + wire [0:0] _zz_893_; + wire [5:0] _zz_894_; + wire [31:0] _zz_895_; + wire [31:0] _zz_896_; + wire _zz_897_; + wire [0:0] _zz_898_; + wire [8:0] _zz_899_; + wire [31:0] _zz_900_; + wire [31:0] _zz_901_; + wire [31:0] _zz_902_; + wire _zz_903_; + wire [0:0] _zz_904_; + wire [3:0] _zz_905_; + wire [31:0] _zz_906_; + wire [31:0] _zz_907_; + wire [31:0] _zz_908_; + wire [31:0] _zz_909_; + wire [31:0] _zz_910_; + wire [31:0] _zz_911_; + wire [31:0] _zz_912_; + wire [0:0] _zz_913_; + wire [21:0] _zz_914_; + wire _zz_915_; + wire _zz_916_; + wire [0:0] _zz_917_; + wire [0:0] _zz_918_; + wire [2:0] _zz_919_; + wire [2:0] _zz_920_; + wire _zz_921_; + wire [0:0] _zz_922_; + wire [57:0] _zz_923_; + wire [0:0] _zz_924_; + wire [4:0] _zz_925_; + wire [31:0] _zz_926_; + wire [31:0] _zz_927_; + wire [31:0] _zz_928_; + wire _zz_929_; + wire [0:0] _zz_930_; + wire [7:0] _zz_931_; + wire [31:0] _zz_932_; + wire [31:0] _zz_933_; + wire [31:0] _zz_934_; + wire _zz_935_; + wire [0:0] _zz_936_; + wire [2:0] _zz_937_; + wire [31:0] _zz_938_; + wire [31:0] _zz_939_; + wire [31:0] _zz_940_; + wire _zz_941_; + wire [0:0] _zz_942_; + wire [20:0] _zz_943_; + wire [31:0] _zz_944_; + wire [31:0] _zz_945_; + wire [31:0] _zz_946_; + wire [31:0] _zz_947_; + wire _zz_948_; + wire [0:0] _zz_949_; + wire [1:0] _zz_950_; + wire [0:0] _zz_951_; + wire [0:0] _zz_952_; + wire _zz_953_; + wire [0:0] _zz_954_; + wire [56:0] _zz_955_; + wire [0:0] _zz_956_; + wire [3:0] _zz_957_; + wire [31:0] _zz_958_; + wire [31:0] _zz_959_; + wire [31:0] _zz_960_; + wire _zz_961_; + wire [0:0] _zz_962_; + wire [6:0] _zz_963_; + wire [31:0] _zz_964_; + wire [31:0] _zz_965_; + wire [31:0] _zz_966_; + wire _zz_967_; + wire [0:0] _zz_968_; + wire [1:0] _zz_969_; + wire [31:0] _zz_970_; + wire [31:0] _zz_971_; + wire _zz_972_; + wire [0:0] _zz_973_; + wire [19:0] _zz_974_; + wire [31:0] _zz_975_; + wire [31:0] _zz_976_; + wire [31:0] _zz_977_; + wire [31:0] _zz_978_; + wire [0:0] _zz_979_; + wire [0:0] _zz_980_; + wire _zz_981_; + wire [4:0] _zz_982_; + wire [4:0] _zz_983_; + wire _zz_984_; + wire [0:0] _zz_985_; + wire [55:0] _zz_986_; + wire _zz_987_; + wire [0:0] _zz_988_; + wire [1:0] _zz_989_; + wire [31:0] _zz_990_; + wire [31:0] _zz_991_; + wire [31:0] _zz_992_; + wire _zz_993_; + wire [0:0] _zz_994_; + wire [4:0] _zz_995_; + wire [31:0] _zz_996_; + wire [31:0] _zz_997_; + wire [31:0] _zz_998_; + wire _zz_999_; + wire _zz_1000_; + wire [31:0] _zz_1001_; + wire _zz_1002_; + wire [0:0] _zz_1003_; + wire [17:0] _zz_1004_; + wire [31:0] _zz_1005_; + wire [31:0] _zz_1006_; + wire [31:0] _zz_1007_; + wire [0:0] _zz_1008_; + wire [2:0] _zz_1009_; + wire [0:0] _zz_1010_; + wire [0:0] _zz_1011_; + wire [8:0] _zz_1012_; + wire [8:0] _zz_1013_; + wire _zz_1014_; + wire [0:0] _zz_1015_; + wire [53:0] _zz_1016_; + wire [31:0] _zz_1017_; + wire [31:0] _zz_1018_; + wire _zz_1019_; + wire [0:0] _zz_1020_; + wire [0:0] _zz_1021_; + wire [31:0] _zz_1022_; + wire [31:0] _zz_1023_; + wire [31:0] _zz_1024_; + wire _zz_1025_; + wire [0:0] _zz_1026_; + wire [3:0] _zz_1027_; + wire [31:0] _zz_1028_; + wire [31:0] _zz_1029_; + wire [31:0] _zz_1030_; + wire [31:0] _zz_1031_; + wire [31:0] _zz_1032_; + wire [31:0] _zz_1033_; + wire [31:0] _zz_1034_; + wire [0:0] _zz_1035_; + wire [16:0] _zz_1036_; + wire [31:0] _zz_1037_; + wire [0:0] _zz_1038_; + wire [1:0] _zz_1039_; + wire _zz_1040_; + wire [0:0] _zz_1041_; + wire [7:0] _zz_1042_; + wire [4:0] _zz_1043_; + wire [4:0] _zz_1044_; + wire _zz_1045_; + wire [0:0] _zz_1046_; + wire [52:0] _zz_1047_; + wire [31:0] _zz_1048_; + wire [31:0] _zz_1049_; + wire [31:0] _zz_1050_; + wire [31:0] _zz_1051_; + wire [31:0] _zz_1052_; + wire [31:0] _zz_1053_; + wire _zz_1054_; + wire [0:0] _zz_1055_; + wire [1:0] _zz_1056_; + wire [0:0] _zz_1057_; + wire [14:0] _zz_1058_; + wire [31:0] _zz_1059_; + wire [0:0] _zz_1060_; + wire [5:0] _zz_1061_; + wire _zz_1062_; + wire [0:0] _zz_1063_; + wire [2:0] _zz_1064_; + wire [0:0] _zz_1065_; + wire [4:0] _zz_1066_; + wire [0:0] _zz_1067_; + wire [0:0] _zz_1068_; + wire _zz_1069_; + wire [0:0] _zz_1070_; + wire [50:0] _zz_1071_; + wire [31:0] _zz_1072_; + wire [31:0] _zz_1073_; + wire [31:0] _zz_1074_; + wire _zz_1075_; + wire _zz_1076_; + wire [0:0] _zz_1077_; + wire [12:0] _zz_1078_; + wire _zz_1079_; + wire [0:0] _zz_1080_; + wire [3:0] _zz_1081_; + wire [31:0] _zz_1082_; + wire [0:0] _zz_1083_; + wire [0:0] _zz_1084_; + wire [31:0] _zz_1085_; + wire [31:0] _zz_1086_; + wire [0:0] _zz_1087_; + wire [2:0] _zz_1088_; + wire [2:0] _zz_1089_; + wire [2:0] _zz_1090_; + wire _zz_1091_; + wire [0:0] _zz_1092_; + wire [48:0] _zz_1093_; + wire [31:0] _zz_1094_; + wire [31:0] _zz_1095_; + wire [31:0] _zz_1096_; + wire [31:0] _zz_1097_; + wire _zz_1098_; + wire [0:0] _zz_1099_; + wire [10:0] _zz_1100_; + wire [31:0] _zz_1101_; + wire [31:0] _zz_1102_; + wire [31:0] _zz_1103_; + wire _zz_1104_; + wire [0:0] _zz_1105_; + wire [1:0] _zz_1106_; + wire [0:0] _zz_1107_; + wire [0:0] _zz_1108_; + wire [0:0] _zz_1109_; + wire [0:0] _zz_1110_; + wire [0:0] _zz_1111_; + wire [1:0] _zz_1112_; + wire [14:0] _zz_1113_; + wire [14:0] _zz_1114_; + wire _zz_1115_; + wire [0:0] _zz_1116_; + wire [46:0] _zz_1117_; + wire [31:0] _zz_1118_; + wire [0:0] _zz_1119_; + wire [8:0] _zz_1120_; + wire [31:0] _zz_1121_; + wire [31:0] _zz_1122_; + wire [31:0] _zz_1123_; + wire _zz_1124_; + wire _zz_1125_; + wire [31:0] _zz_1126_; + wire [31:0] _zz_1127_; + wire [31:0] _zz_1128_; + wire [31:0] _zz_1129_; + wire _zz_1130_; + wire _zz_1131_; + wire [0:0] _zz_1132_; + wire [12:0] _zz_1133_; + wire [0:0] _zz_1134_; + wire [0:0] _zz_1135_; + wire [1:0] _zz_1136_; + wire [1:0] _zz_1137_; + wire _zz_1138_; + wire [0:0] _zz_1139_; + wire [44:0] _zz_1140_; + wire [0:0] _zz_1141_; + wire [6:0] _zz_1142_; + wire [31:0] _zz_1143_; + wire [31:0] _zz_1144_; + wire [31:0] _zz_1145_; + wire [31:0] _zz_1146_; + wire [0:0] _zz_1147_; + wire [10:0] _zz_1148_; + wire [31:0] _zz_1149_; + wire [31:0] _zz_1150_; + wire [0:0] _zz_1151_; + wire [2:0] _zz_1152_; + wire [1:0] _zz_1153_; + wire [1:0] _zz_1154_; + wire _zz_1155_; + wire [0:0] _zz_1156_; + wire [42:0] _zz_1157_; + wire [0:0] _zz_1158_; + wire [4:0] _zz_1159_; + wire _zz_1160_; + wire [0:0] _zz_1161_; + wire [8:0] _zz_1162_; + wire [0:0] _zz_1163_; + wire [0:0] _zz_1164_; + wire [0:0] _zz_1165_; + wire [6:0] _zz_1166_; + wire [0:0] _zz_1167_; + wire [0:0] _zz_1168_; + wire _zz_1169_; + wire [0:0] _zz_1170_; + wire [40:0] _zz_1171_; + wire [0:0] _zz_1172_; + wire [2:0] _zz_1173_; + wire [31:0] _zz_1174_; + wire [0:0] _zz_1175_; + wire [6:0] _zz_1176_; + wire _zz_1177_; + wire [0:0] _zz_1178_; + wire [4:0] _zz_1179_; + wire [0:0] _zz_1180_; + wire [4:0] _zz_1181_; + wire [3:0] _zz_1182_; + wire [3:0] _zz_1183_; + wire _zz_1184_; + wire [0:0] _zz_1185_; + wire [38:0] _zz_1186_; + wire [31:0] _zz_1187_; + wire [31:0] _zz_1188_; + wire [0:0] _zz_1189_; + wire [0:0] _zz_1190_; + wire [31:0] _zz_1191_; + wire [31:0] _zz_1192_; + wire _zz_1193_; + wire [0:0] _zz_1194_; + wire [4:0] _zz_1195_; + wire [31:0] _zz_1196_; + wire [31:0] _zz_1197_; + wire [31:0] _zz_1198_; + wire _zz_1199_; + wire [0:0] _zz_1200_; + wire [2:0] _zz_1201_; + wire _zz_1202_; + wire [0:0] _zz_1203_; + wire [2:0] _zz_1204_; + wire _zz_1205_; + wire [0:0] _zz_1206_; + wire [1:0] _zz_1207_; + wire [0:0] _zz_1208_; + wire [4:0] _zz_1209_; + wire [10:0] _zz_1210_; + wire [10:0] _zz_1211_; + wire _zz_1212_; + wire [0:0] _zz_1213_; + wire [36:0] _zz_1214_; + wire [31:0] _zz_1215_; + wire _zz_1216_; + wire [31:0] _zz_1217_; + wire [31:0] _zz_1218_; + wire [31:0] _zz_1219_; + wire [0:0] _zz_1220_; + wire [3:0] _zz_1221_; + wire [31:0] _zz_1222_; + wire [31:0] _zz_1223_; + wire [31:0] _zz_1224_; + wire _zz_1225_; + wire [0:0] _zz_1226_; + wire [1:0] _zz_1227_; + wire [31:0] _zz_1228_; + wire [31:0] _zz_1229_; + wire [0:0] _zz_1230_; + wire [1:0] _zz_1231_; + wire [31:0] _zz_1232_; + wire [31:0] _zz_1233_; + wire _zz_1234_; + wire [0:0] _zz_1235_; + wire [0:0] _zz_1236_; + wire [0:0] _zz_1237_; + wire [3:0] _zz_1238_; + wire [0:0] _zz_1239_; + wire [9:0] _zz_1240_; + wire [0:0] _zz_1241_; + wire [0:0] _zz_1242_; + wire _zz_1243_; + wire [0:0] _zz_1244_; + wire [35:0] _zz_1245_; + wire [31:0] _zz_1246_; + wire _zz_1247_; + wire [0:0] _zz_1248_; + wire [1:0] _zz_1249_; + wire [31:0] _zz_1250_; + wire [31:0] _zz_1251_; + wire [31:0] _zz_1252_; + wire _zz_1253_; + wire _zz_1254_; + wire [31:0] _zz_1255_; + wire [31:0] _zz_1256_; + wire _zz_1257_; + wire [31:0] _zz_1258_; + wire [31:0] _zz_1259_; + wire [31:0] _zz_1260_; + wire [0:0] _zz_1261_; + wire [1:0] _zz_1262_; + wire [0:0] _zz_1263_; + wire [7:0] _zz_1264_; + wire _zz_1265_; + wire [0:0] _zz_1266_; + wire [0:0] _zz_1267_; + wire _zz_1268_; + wire [0:0] _zz_1269_; + wire [33:0] _zz_1270_; + wire [31:0] _zz_1271_; + wire [31:0] _zz_1272_; + wire [31:0] _zz_1273_; + wire [31:0] _zz_1274_; + wire [31:0] _zz_1275_; + wire [31:0] _zz_1276_; + wire _zz_1277_; + wire _zz_1278_; + wire [31:0] _zz_1279_; + wire [31:0] _zz_1280_; + wire _zz_1281_; + wire [0:0] _zz_1282_; + wire [5:0] _zz_1283_; + wire [31:0] _zz_1284_; + wire [0:0] _zz_1285_; + wire [0:0] _zz_1286_; + wire [1:0] _zz_1287_; + wire [1:0] _zz_1288_; + wire _zz_1289_; + wire [0:0] _zz_1290_; + wire [31:0] _zz_1291_; + wire [31:0] _zz_1292_; + wire [31:0] _zz_1293_; + wire [31:0] _zz_1294_; + wire _zz_1295_; + wire [0:0] _zz_1296_; + wire [3:0] _zz_1297_; + wire [31:0] _zz_1298_; + wire [31:0] _zz_1299_; + wire _zz_1300_; + wire _zz_1301_; + wire [0:0] _zz_1302_; + wire [0:0] _zz_1303_; + wire [2:0] _zz_1304_; + wire [2:0] _zz_1305_; + wire _zz_1306_; + wire [0:0] _zz_1307_; + wire [29:0] _zz_1308_; + wire [31:0] _zz_1309_; + wire [31:0] _zz_1310_; + wire [31:0] _zz_1311_; + wire _zz_1312_; + wire [0:0] _zz_1313_; + wire [1:0] _zz_1314_; + wire [31:0] _zz_1315_; + wire [31:0] _zz_1316_; + wire [31:0] _zz_1317_; + wire [31:0] _zz_1318_; + wire _zz_1319_; + wire [0:0] _zz_1320_; + wire [0:0] _zz_1321_; + wire [0:0] _zz_1322_; + wire [0:0] _zz_1323_; + wire [2:0] _zz_1324_; + wire [2:0] _zz_1325_; + wire _zz_1326_; + wire [0:0] _zz_1327_; + wire [27:0] _zz_1328_; + wire [31:0] _zz_1329_; + wire [31:0] _zz_1330_; + wire [31:0] _zz_1331_; + wire _zz_1332_; + wire _zz_1333_; + wire [31:0] _zz_1334_; + wire [31:0] _zz_1335_; + wire [31:0] _zz_1336_; + wire [31:0] _zz_1337_; + wire [31:0] _zz_1338_; + wire [31:0] _zz_1339_; + wire [31:0] _zz_1340_; + wire [31:0] _zz_1341_; + wire [31:0] _zz_1342_; + wire _zz_1343_; + wire [0:0] _zz_1344_; + wire [0:0] _zz_1345_; + wire [0:0] _zz_1346_; + wire [1:0] _zz_1347_; + wire [2:0] _zz_1348_; + wire [2:0] _zz_1349_; + wire _zz_1350_; + wire [0:0] _zz_1351_; + wire [25:0] _zz_1352_; + wire [31:0] _zz_1353_; + wire [31:0] _zz_1354_; + wire [31:0] _zz_1355_; + wire [31:0] _zz_1356_; + wire [31:0] _zz_1357_; + wire [31:0] _zz_1358_; + wire [31:0] _zz_1359_; + wire [31:0] _zz_1360_; + wire [31:0] _zz_1361_; + wire _zz_1362_; + wire _zz_1363_; + wire _zz_1364_; + wire [0:0] _zz_1365_; + wire [0:0] _zz_1366_; + wire [0:0] _zz_1367_; + wire [1:0] _zz_1368_; + wire _zz_1369_; + wire [0:0] _zz_1370_; + wire [23:0] _zz_1371_; + wire [31:0] _zz_1372_; + wire [31:0] _zz_1373_; + wire [31:0] _zz_1374_; + wire [31:0] _zz_1375_; + wire [31:0] _zz_1376_; + wire [31:0] _zz_1377_; + wire [31:0] _zz_1378_; + wire _zz_1379_; + wire _zz_1380_; + wire [0:0] _zz_1381_; + wire [0:0] _zz_1382_; + wire _zz_1383_; + wire [0:0] _zz_1384_; + wire [21:0] _zz_1385_; + wire [31:0] _zz_1386_; + wire _zz_1387_; + wire _zz_1388_; + wire _zz_1389_; + wire [1:0] _zz_1390_; + wire [1:0] _zz_1391_; + wire _zz_1392_; + wire [0:0] _zz_1393_; + wire [18:0] _zz_1394_; + wire [31:0] _zz_1395_; + wire _zz_1396_; + wire _zz_1397_; + wire [0:0] _zz_1398_; + wire [1:0] _zz_1399_; + wire [5:0] _zz_1400_; + wire [5:0] _zz_1401_; + wire _zz_1402_; + wire [0:0] _zz_1403_; + wire [14:0] _zz_1404_; + wire [31:0] _zz_1405_; + wire [31:0] _zz_1406_; + wire [31:0] _zz_1407_; + wire [31:0] _zz_1408_; + wire [31:0] _zz_1409_; + wire [0:0] _zz_1410_; + wire [2:0] _zz_1411_; + wire [0:0] _zz_1412_; + wire [1:0] _zz_1413_; + wire [0:0] _zz_1414_; + wire [29:0] _zz_1415_; + wire [1:0] _zz_1416_; + wire [1:0] _zz_1417_; + wire _zz_1418_; + wire [0:0] _zz_1419_; + wire [11:0] _zz_1420_; + wire [31:0] _zz_1421_; + wire [31:0] _zz_1422_; + wire [0:0] _zz_1423_; + wire [0:0] _zz_1424_; + wire [31:0] _zz_1425_; + wire [31:0] _zz_1426_; + wire _zz_1427_; + wire [31:0] _zz_1428_; + wire [31:0] _zz_1429_; + wire _zz_1430_; + wire [0:0] _zz_1431_; + wire [27:0] _zz_1432_; + wire _zz_1433_; + wire [0:0] _zz_1434_; + wire [3:0] _zz_1435_; + wire [3:0] _zz_1436_; + wire [3:0] _zz_1437_; + wire _zz_1438_; + wire [0:0] _zz_1439_; + wire [9:0] _zz_1440_; + wire [31:0] _zz_1441_; + wire [31:0] _zz_1442_; + wire [31:0] _zz_1443_; + wire [31:0] _zz_1444_; + wire [0:0] _zz_1445_; + wire [25:0] _zz_1446_; + wire [31:0] _zz_1447_; + wire [31:0] _zz_1448_; + wire [31:0] _zz_1449_; + wire _zz_1450_; + wire [0:0] _zz_1451_; + wire [1:0] _zz_1452_; + wire _zz_1453_; + wire [0:0] _zz_1454_; + wire [1:0] _zz_1455_; + wire [0:0] _zz_1456_; + wire [0:0] _zz_1457_; + wire [3:0] _zz_1458_; + wire [3:0] _zz_1459_; + wire _zz_1460_; + wire [0:0] _zz_1461_; + wire [7:0] _zz_1462_; + wire [31:0] _zz_1463_; + wire [31:0] _zz_1464_; + wire [0:0] _zz_1465_; + wire [23:0] _zz_1466_; + wire [31:0] _zz_1467_; + wire [31:0] _zz_1468_; + wire [31:0] _zz_1469_; + wire _zz_1470_; + wire _zz_1471_; + wire [31:0] _zz_1472_; + wire _zz_1473_; + wire _zz_1474_; + wire [31:0] _zz_1475_; + wire [31:0] _zz_1476_; + wire _zz_1477_; + wire [0:0] _zz_1478_; + wire [1:0] _zz_1479_; + wire [0:0] _zz_1480_; + wire [1:0] _zz_1481_; + wire [9:0] _zz_1482_; + wire [9:0] _zz_1483_; + wire _zz_1484_; + wire [0:0] _zz_1485_; + wire [5:0] _zz_1486_; + wire [0:0] _zz_1487_; + wire [21:0] _zz_1488_; + wire [31:0] _zz_1489_; + wire [31:0] _zz_1490_; + wire [31:0] _zz_1491_; + wire [31:0] _zz_1492_; + wire [31:0] _zz_1493_; + wire [31:0] _zz_1494_; + wire [31:0] _zz_1495_; + wire _zz_1496_; + wire _zz_1497_; + wire [0:0] _zz_1498_; + wire [7:0] _zz_1499_; + wire _zz_1500_; + wire [1:0] _zz_1501_; + wire [1:0] _zz_1502_; + wire _zz_1503_; + wire [0:0] _zz_1504_; + wire [3:0] _zz_1505_; + wire [0:0] _zz_1506_; + wire [19:0] _zz_1507_; + wire [31:0] _zz_1508_; + wire [31:0] _zz_1509_; + wire [31:0] _zz_1510_; + wire [31:0] _zz_1511_; + wire _zz_1512_; + wire [0:0] _zz_1513_; + wire [5:0] _zz_1514_; + wire [31:0] _zz_1515_; + wire [1:0] _zz_1516_; + wire [1:0] _zz_1517_; + wire _zz_1518_; + wire [0:0] _zz_1519_; + wire [1:0] _zz_1520_; + wire [0:0] _zz_1521_; + wire [17:0] _zz_1522_; + wire [31:0] _zz_1523_; + wire [31:0] _zz_1524_; + wire [31:0] _zz_1525_; + wire _zz_1526_; + wire [0:0] _zz_1527_; + wire [3:0] _zz_1528_; + wire _zz_1529_; + wire _zz_1530_; + wire [0:0] _zz_1531_; + wire [4:0] _zz_1532_; + wire [0:0] _zz_1533_; + wire [0:0] _zz_1534_; + wire _zz_1535_; + wire _zz_1536_; + wire [0:0] _zz_1537_; + wire [15:0] _zz_1538_; + wire [31:0] _zz_1539_; + wire [31:0] _zz_1540_; + wire [31:0] _zz_1541_; + wire _zz_1542_; + wire [0:0] _zz_1543_; + wire [1:0] _zz_1544_; + wire [31:0] _zz_1545_; + wire [31:0] _zz_1546_; + wire _zz_1547_; + wire [0:0] _zz_1548_; + wire [2:0] _zz_1549_; + wire [31:0] _zz_1550_; + wire [31:0] _zz_1551_; + wire _zz_1552_; + wire [0:0] _zz_1553_; + wire [1:0] _zz_1554_; + wire _zz_1555_; + wire [0:0] _zz_1556_; + wire [13:0] _zz_1557_; + wire [31:0] _zz_1558_; + wire [31:0] _zz_1559_; + wire [31:0] _zz_1560_; + wire _zz_1561_; + wire [31:0] _zz_1562_; + wire [31:0] _zz_1563_; + wire [31:0] _zz_1564_; + wire [0:0] _zz_1565_; + wire [0:0] _zz_1566_; + wire [31:0] _zz_1567_; + wire [31:0] _zz_1568_; + wire [31:0] _zz_1569_; + wire _zz_1570_; + wire [31:0] _zz_1571_; + wire [0:0] _zz_1572_; + wire [8:0] _zz_1573_; + wire [31:0] _zz_1574_; + wire [31:0] _zz_1575_; + wire [31:0] _zz_1576_; + wire _zz_1577_; + wire [0:0] _zz_1578_; + wire [0:0] _zz_1579_; + wire [10:0] _zz_1580_; + wire [10:0] _zz_1581_; + wire [17:0] _zz_1582_; + wire [0:0] _zz_1583_; + wire [17:0] _zz_1584_; + wire [0:0] _zz_1585_; + wire [17:0] _zz_1586_; + wire [0:0] _zz_1587_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_1_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_2_; + wire decode_DECODER_stageables_29; + wire decode_DECODER_stageables_25; + wire [31:0] execute_NEXT_PC2; + wire execute_XER_SO; + wire `Src1CtrlEnum_defaultEncoding_type _zz_3_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_4_; + wire decode_DECODER_stageables_43; + wire decode_DECODER_stageables_27; + wire [7:0] decode_CR_FIELD_RD; + wire `Src2CtrlEnum_defaultEncoding_type _zz_5_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_6_; + wire decode_DECODER_stageables_21; + wire execute_DECODER_stageables_37; + wire decode_DECODER_stageables_37; + wire `AluCtrlEnum_defaultEncoding_type decode_DECODER_stageables_8; + wire `AluCtrlEnum_defaultEncoding_type _zz_7_; + wire `AluCtrlEnum_defaultEncoding_type _zz_8_; + wire `AluCtrlEnum_defaultEncoding_type _zz_9_; + wire decode_DECODER_stageables_23; + wire [31:0] memory_SRC_ADD; + wire decode_DECODER_stageables_46; + wire `Src3CtrlEnum_defaultEncoding_type decode_DECODER_stageables_1; + wire `Src3CtrlEnum_defaultEncoding_type _zz_10_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_11_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_12_; + wire [7:0] execute_CR_FIELD_WR; + wire `DataSizeEnum_defaultEncoding_type memory_DECODER_stageables_7; + wire `DataSizeEnum_defaultEncoding_type _zz_13_; + wire `DataSizeEnum_defaultEncoding_type _zz_14_; + wire `DataSizeEnum_defaultEncoding_type _zz_15_; + wire `DataSizeEnum_defaultEncoding_type _zz_16_; + wire `DataSizeEnum_defaultEncoding_type _zz_17_; + wire `DataSizeEnum_defaultEncoding_type decode_DECODER_stageables_7; + wire `DataSizeEnum_defaultEncoding_type _zz_18_; + wire `DataSizeEnum_defaultEncoding_type _zz_19_; + wire `DataSizeEnum_defaultEncoding_type _zz_20_; + wire `CRMoveCtrlEnum_defaultEncoding_type decode_DECODER_stageables_51; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_21_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_22_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_23_; + wire memory_DECODER_stageables_53; + wire execute_DECODER_stageables_53; + wire decode_DECODER_stageables_53; + wire [33:0] execute_MUL_HL; + wire [4:0] writeBack_REGFILE_WRITE_ADDR; + wire [4:0] memory_REGFILE_WRITE_ADDR; + wire [4:0] execute_REGFILE_WRITE_ADDR; + wire decode_DECODER_stageables_35; + wire execute_TARGET_MISSMATCH2; + wire execute_DECODER_stageables_31; + wire decode_DECODER_stageables_31; + wire [33:0] execute_MUL_LH; + wire decode_DECODER_stageables_40; + wire decode_DECODER_stageables_2; + wire [31:0] execute_RA; + wire decode_DECODER_stageables_3; + wire decode_DECODER_stageables_14; + wire [31:0] memory_SRC1; + wire `EndianEnum_defaultEncoding_type memory_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_24_; + wire `EndianEnum_defaultEncoding_type _zz_25_; + wire `EndianEnum_defaultEncoding_type _zz_26_; + wire `EndianEnum_defaultEncoding_type _zz_27_; + wire `EndianEnum_defaultEncoding_type _zz_28_; + wire `EndianEnum_defaultEncoding_type _zz_29_; + wire `EndianEnum_defaultEncoding_type _zz_30_; + wire memory_DECODER_stageables_24; + wire execute_DECODER_stageables_24; + wire decode_DECODER_stageables_24; + wire decode_DECODER_stageables_34; + wire decode_DECODER_stageables_18; + wire `AluBitwiseCtrlEnum_defaultEncoding_type decode_DECODER_stageables_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_31_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_32_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_33_; + wire decode_DECODER_stageables_9; + wire decode_DECODER_stageables_45; + wire [4:0] decode_RT_ADDR; + wire decode_DECODER_stageables_42; + wire [51:0] memory_MUL_LOW; + wire `CRBusCmdEnum_defaultEncoding_type _zz_34_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_35_; + wire `CRBusCmdEnum_defaultEncoding_type execute_CR_WRITE_op; + wire [4:0] execute_CR_WRITE_ba; + wire [4:0] execute_CR_WRITE_bb; + wire [4:0] execute_CR_WRITE_bt; + wire [31:0] execute_CR_WRITE_imm; + wire [7:0] execute_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_36_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_37_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_38_; + wire execute_DECODER_stageables_5; + wire decode_DECODER_stageables_5; + wire execute_DECODER_stageables_15; + wire decode_DECODER_stageables_15; + wire `AluSpecCtrlEnum_defaultEncoding_type decode_DECODER_stageables_0; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_39_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_40_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_41_; + wire execute_BRANCH_LINK; + wire execute_BRANCH_DO; + wire memory_DECODER_stageables_39; + wire execute_DECODER_stageables_39; + wire decode_DECODER_stageables_39; + wire memory_DECODER_stageables_56; + wire decode_DECODER_stageables_56; + wire `AluRimiCtrlEnum_defaultEncoding_type decode_DECODER_stageables_16; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_42_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_43_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_44_; + wire decode_DECODER_stageables_11; + wire execute_XER_CA; + wire [4:0] writeBack_LOAD_UPDATE_ADDR; + wire [4:0] memory_LOAD_UPDATE_ADDR; + wire [4:0] execute_LOAD_UPDATE_ADDR; + wire [31:0] execute_MUL_LL; + wire [31:0] writeBack_FORMAL_PC_NEXT; + wire [31:0] memory_FORMAL_PC_NEXT; + wire [31:0] execute_FORMAL_PC_NEXT; + wire [31:0] decode_FORMAL_PC_NEXT; + wire decode_DECODER_stageables_22; + wire [1:0] memory_MEMORY_ADDRESS_LOW; + wire [1:0] execute_MEMORY_ADDRESS_LOW; + wire decode_DECODER_stageables_32; + wire decode_DECODER_stageables_54; + wire [31:0] execute_REGFILE_WRITE_DATA; + wire `CRLogCtrlEnum_defaultEncoding_type decode_DECODER_stageables_20; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_45_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_46_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_47_; + wire decode_DECODER_stageables_57; + wire memory_DECODER_stageables_55; + wire execute_DECODER_stageables_55; + wire decode_DECODER_stageables_55; + wire `BranchCtrlEnum_defaultEncoding_type _zz_48_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_49_; + wire [31:0] writeBack_LOAD_UPDATE_DATA; + wire [31:0] memory_LOAD_UPDATE_DATA; + wire [31:0] execute_LOAD_UPDATE_DATA; + wire execute_XER_WRITE_validOV; + wire execute_XER_WRITE_validCA; + wire [1:0] execute_XER_WRITE_imm; + wire decode_DECODER_stageables_48; + wire `EnvCtrlEnum_defaultEncoding_type memory_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_50_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_51_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_52_; + wire `EnvCtrlEnum_defaultEncoding_type decode_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_53_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_54_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_55_; + wire execute_PREDICTION_CONTEXT_hazard; + wire execute_PREDICTION_CONTEXT_hit; + wire [19:0] execute_PREDICTION_CONTEXT_line_source; + wire [1:0] execute_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] execute_PREDICTION_CONTEXT_line_target; + wire decode_PREDICTION_CONTEXT_hazard; + wire decode_PREDICTION_CONTEXT_hit; + wire [19:0] decode_PREDICTION_CONTEXT_line_source; + wire [1:0] decode_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] decode_PREDICTION_CONTEXT_line_target; + wire memory_DECODER_stageables_36; + wire execute_DECODER_stageables_36; + wire decode_DECODER_stageables_36; + wire `AluRimiAmtEnum_defaultEncoding_type decode_DECODER_stageables_44; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_56_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_57_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_58_; + wire decode_DECODER_stageables_28; + wire [33:0] memory_MUL_HH; + wire [33:0] execute_MUL_HH; + wire [31:0] execute_RB; + wire `EnvCtrlEnum_defaultEncoding_type writeBack_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_59_; + wire writeBack_DECODER_stageables_39; + wire execute_DECODER_stageables_40; + wire execute_DECODER_stageables_30; + reg `EnvCtrlEnum_defaultEncoding_type _zz_60_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_61_; + wire `EnvCtrlEnum_defaultEncoding_type execute_DECODER_stageables_49; + wire `EnvCtrlEnum_defaultEncoding_type _zz_62_; + reg `EndianEnum_defaultEncoding_type _zz_63_; + wire [31:0] writeBack_SRC_ADD; + wire [31:0] memory_NEXT_PC2; + wire [31:0] memory_PC; + wire [31:0] memory_BRANCH_CALC; + wire memory_TARGET_MISSMATCH2; + wire memory_BRANCH_DO; + wire [31:0] execute_BRANCH_CALC; + wire [31:0] execute_PC; + reg [7:0] _zz_64_; + wire decode_DECODER_stageables_6; + wire `BranchCtrlEnum_defaultEncoding_type decode_DECODER_stageables_13; + wire `BranchCtrlEnum_defaultEncoding_type _zz_65_; + wire [7:0] writeBack_CR_FIELD_WR; + wire execute_BRANCH_DEC; + wire execute_DECODER_stageables_32; + wire memory_BRANCH_DEC; + wire memory_BRANCH_LINK; + wire [10:0] memory_SPR_ID; + wire memory_DECODER_stageables_32; + wire memory_XER_WRITE_validOV; + wire memory_XER_WRITE_validCA; + wire [1:0] memory_XER_WRITE_imm; + wire `CRBusCmdEnum_defaultEncoding_type memory_CR_WRITE_op; + wire [4:0] memory_CR_WRITE_ba; + wire [4:0] memory_CR_WRITE_bb; + wire [4:0] memory_CR_WRITE_bt; + wire [31:0] memory_CR_WRITE_imm; + wire [7:0] memory_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_66_; + wire memory_DECODER_stageables_31; + wire `BranchCtrlEnum_defaultEncoding_type execute_DECODER_stageables_13; + wire `BranchCtrlEnum_defaultEncoding_type _zz_67_; + wire [7:0] execute_CR_FIELD_RD; + wire [7:0] memory_CR_FIELD_WR; + reg [31:0] _zz_68_; + wire execute_DECODER_stageables_45; + wire [4:0] execute_RT_ADDR; + wire execute_DECODER_stageables_25; + wire memory_DECODER_stageables_45; + wire [4:0] memory_RT_ADDR; + wire memory_DECODER_stageables_5; + wire decode_DECODER_stageables_50; + wire decode_DECODER_stageables_47; + wire decode_DECODER_stageables_10; + wire writeBack_DECODER_stageables_45; + wire [4:0] writeBack_RT_ADDR; + reg [31:0] decode_RS; + reg [31:0] decode_RB; + reg [31:0] decode_RA; + wire [4:0] decode_R2_ADDR; + wire [4:0] decode_R1_ADDR; + wire [4:0] decode_R0_ADDR; + wire execute_DECODER_stageables_29; + wire execute_DECODER_stageables_43; + wire execute_DECODER_stageables_3; + wire [1:0] memory_SRC_CR; + wire memory_XER_SO; + wire [31:0] memory_INSTRUCTION; + wire memory_DECODER_stageables_37; + reg [31:0] _zz_69_; + wire memory_DECODER_stageables_15; + wire memory_DECODER_stageables_43; + wire writeBack_DECODER_stageables_31; + wire writeBack_DECODER_stageables_24; + wire [1:0] writeBack_SRC_CR; + wire writeBack_DECODER_stageables_55; + wire writeBack_XER_SO; + wire writeBack_DECODER_stageables_36; + wire [33:0] writeBack_MUL_HH; + wire [51:0] writeBack_MUL_LOW; + wire [33:0] memory_MUL_HL; + wire [33:0] memory_MUL_LH; + wire [31:0] memory_MUL_LL; + wire execute_DECODER_stageables_35; + wire memory_DECODER_stageables_9; + wire execute_DECODER_stageables_9; + wire writeBack_DECODER_stageables_9; + wire execute_DECODER_stageables_48; + wire [0:0] execute_SRC3; + wire `Src3CtrlEnum_defaultEncoding_type execute_DECODER_stageables_1; + wire `Src3CtrlEnum_defaultEncoding_type _zz_70_; + wire `Src2CtrlEnum_defaultEncoding_type execute_DECODER_stageables_26; + wire `Src2CtrlEnum_defaultEncoding_type _zz_71_; + wire [31:0] _zz_72_; + wire [31:0] _zz_73_; + wire `Src1CtrlEnum_defaultEncoding_type execute_DECODER_stageables_38; + wire `Src1CtrlEnum_defaultEncoding_type _zz_74_; + wire decode_DECODER_stageables_17; + reg [7:0] _zz_75_; + wire `CRBusCmdEnum_defaultEncoding_type _zz_76_; + wire `CRLogCtrlEnum_defaultEncoding_type execute_DECODER_stageables_20; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_77_; + wire `CRMoveCtrlEnum_defaultEncoding_type execute_DECODER_stageables_51; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_78_; + wire execute_DECODER_stageables_46; + wire execute_DECODER_stageables_34; + wire execute_DECODER_stageables_28; + wire execute_DECODER_stageables_57; + wire execute_DECODER_stageables_21; + wire [1:0] execute_SRC_CR; + wire execute_DECODER_stageables_11; + wire execute_DECODER_stageables_18; + wire [1:0] execute_SRC_CAOV; + wire execute_DECODER_stageables_14; + reg [10:0] _zz_79_; + wire execute_DECODER_stageables_6; + wire [4:0] execute_R0_ADDR; + wire `TgtCtrlEnum_defaultEncoding_type execute_DECODER_stageables_12; + wire `TgtCtrlEnum_defaultEncoding_type _zz_80_; + wire `AluCtrlEnum_defaultEncoding_type execute_DECODER_stageables_8; + wire `AluCtrlEnum_defaultEncoding_type _zz_81_; + wire execute_DECODER_stageables_27; + wire execute_DECODER_stageables_2; + wire execute_DECODER_stageables_23; + wire `AluSpecCtrlEnum_defaultEncoding_type execute_DECODER_stageables_0; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_82_; + reg [5:0] _zz_83_; + reg [5:0] _zz_83__30; + reg [5:0] _zz_83__29; + reg [5:0] _zz_83__28; + reg [5:0] _zz_83__27; + reg [5:0] _zz_83__26; + reg [5:0] _zz_83__25; + reg [5:0] _zz_83__24; + reg [5:0] _zz_83__23; + reg [5:0] _zz_83__22; + reg [5:0] _zz_83__21; + reg [5:0] _zz_83__20; + reg [5:0] _zz_83__19; + reg [5:0] _zz_83__18; + reg [5:0] _zz_83__17; + reg [5:0] _zz_83__16; + reg [5:0] _zz_83__15; + reg [5:0] _zz_83__14; + reg [5:0] _zz_83__13; + reg [5:0] _zz_83__12; + reg [5:0] _zz_83__11; + reg [5:0] _zz_83__10; + reg [5:0] _zz_83__9; + reg [5:0] _zz_83__8; + reg [5:0] _zz_83__7; + reg [5:0] _zz_83__6; + reg [5:0] _zz_83__5; + reg [5:0] _zz_83__4; + reg [5:0] _zz_83__3; + reg [5:0] _zz_83__2; + reg [5:0] _zz_83__1; + reg [5:0] _zz_83__0; + reg [3:0] _zz_84_; + reg [3:0] _zz_84__6; + reg [3:0] _zz_84__5; + reg [3:0] _zz_84__4; + reg [3:0] _zz_84__3; + reg [3:0] _zz_84__2; + reg [3:0] _zz_84__1; + reg [3:0] _zz_84__0; + reg [3:0] _zz_85_; + reg [3:0] _zz_85__6; + reg [3:0] _zz_85__5; + reg [3:0] _zz_85__4; + reg [3:0] _zz_85__3; + reg [3:0] _zz_85__2; + reg [3:0] _zz_85__1; + reg [3:0] _zz_85__0; + reg [3:0] _zz_86_; + reg [3:0] _zz_86__6; + reg [3:0] _zz_86__5; + reg [3:0] _zz_86__4; + reg [3:0] _zz_86__3; + reg [3:0] _zz_86__2; + reg [3:0] _zz_86__1; + reg [3:0] _zz_86__0; + reg [3:0] _zz_87_; + reg [3:0] _zz_87__6; + reg [3:0] _zz_87__5; + reg [3:0] _zz_87__4; + reg [3:0] _zz_87__3; + reg [3:0] _zz_87__2; + reg [3:0] _zz_87__1; + reg [3:0] _zz_87__0; + reg [31:0] _zz_88_; + reg [31:0] _zz_89_; + reg [31:0] _zz_90_; + reg [31:0] _zz_91_; + reg [31:0] _zz_92_; + reg [31:0] _zz_93_; + reg [31:0] _zz_94_; + reg [31:0] _zz_95_; + reg [31:0] _zz_96_; + reg [31:0] _zz_97_; + wire `AluRimiCtrlEnum_defaultEncoding_type execute_DECODER_stageables_16; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_98_; + wire `AluRimiAmtEnum_defaultEncoding_type execute_DECODER_stageables_44; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_99_; + wire [31:0] execute_SRC2; + wire [31:0] execute_SRC1; + wire `AluBitwiseCtrlEnum_defaultEncoding_type execute_DECODER_stageables_19; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_100_; + wire execute_DECODER_stageables_54; + wire [10:0] execute_SPR_ID; + wire [31:0] writeBack_SRC1; + wire writeBack_DECODER_stageables_32; + wire [10:0] writeBack_SPR_ID; + wire writeBack_XER_WRITE_validOV; + wire writeBack_XER_WRITE_validCA; + wire [1:0] writeBack_XER_WRITE_imm; + wire writeBack_BRANCH_LINK; + wire writeBack_BRANCH_DEC; + wire `CRBusCmdEnum_defaultEncoding_type writeBack_CR_WRITE_op; + wire [4:0] writeBack_CR_WRITE_ba; + wire [4:0] writeBack_CR_WRITE_bb; + wire [4:0] writeBack_CR_WRITE_bt; + wire [31:0] writeBack_CR_WRITE_imm; + wire [7:0] writeBack_CR_WRITE_fxm; + wire `CRBusCmdEnum_defaultEncoding_type _zz_101_; + wire _zz_102_; + reg _zz_103_; + wire `TgtCtrlEnum_defaultEncoding_type decode_DECODER_stageables_12; + wire `TgtCtrlEnum_defaultEncoding_type _zz_104_; + wire `Src2CtrlEnum_defaultEncoding_type decode_DECODER_stageables_26; + wire `Src2CtrlEnum_defaultEncoding_type _zz_105_; + wire `Src1CtrlEnum_defaultEncoding_type decode_DECODER_stageables_38; + wire `Src1CtrlEnum_defaultEncoding_type _zz_106_; + wire [31:0] decode_INSTRUCTION_ANTICIPATED; + wire decode; + wire decode_LEGAL_INSTRUCTION; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_107_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_108_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_109_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_110_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_111_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_112_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_113_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_114_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_115_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_116_; + wire `AluCtrlEnum_defaultEncoding_type _zz_117_; + wire `DataSizeEnum_defaultEncoding_type _zz_118_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_119_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_120_; + reg [31:0] _zz_121_; + wire writeBack_SIGN_EXTEND; + wire `DataSizeEnum_defaultEncoding_type writeBack_DATA_SIZE; + wire `DataSizeEnum_defaultEncoding_type _zz_122_; + wire [1:0] writeBack_MEMORY_ADDRESS_LOW; + wire writeBack_MEMORY_WR; + wire `EndianEnum_defaultEncoding_type writeBack_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_123_; + wire [31:0] writeBack_REGFILE_WRITE_DATA; + wire writeBack_MEMORY_ENABLE; + wire [31:0] memory_REGFILE_WRITE_DATA; + wire memory_MEMORY_ENABLE; + reg [31:0] _zz_124_; + wire execute_STORE_UPDATE; + wire execute_MEMORY_MANAGMENT; + wire [31:0] execute_RS; + wire execute_MEMORY_WR; + wire [31:0] execute_SRC_ADD; + wire execute_MEMORY_ENABLE; + wire `DataSizeEnum_defaultEncoding_type execute_DATA_SIZE; + wire `DataSizeEnum_defaultEncoding_type _zz_125_; + wire [31:0] execute_INSTRUCTION; + wire `EndianEnum_defaultEncoding_type execute_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_126_; + wire decode_MEMORY_ENABLE; + wire decode_FLUSH_ALL; + reg _zz_127_; + reg _zz_127__3; + reg _zz_127__2; + reg _zz_127__1; + reg _zz_127__0; + wire [31:0] decode_INSTRUCTION; + reg [31:0] _zz_128_; + wire `EndianEnum_defaultEncoding_type decode_MSR_ENDIAN; + wire `EndianEnum_defaultEncoding_type _zz_129_; + wire memory_PREDICTION_CONTEXT_hazard; + wire memory_PREDICTION_CONTEXT_hit; + wire [19:0] memory_PREDICTION_CONTEXT_line_source; + wire [1:0] memory_PREDICTION_CONTEXT_line_branchWish; + wire [31:0] memory_PREDICTION_CONTEXT_line_target; + reg _zz_130_; + reg [31:0] _zz_131_; + wire [31:0] decode_PC; + wire [31:0] writeBack_PC; + wire [31:0] writeBack_INSTRUCTION; + wire sprReadBU_valid; + wire [31:0] sprReadBU_payload_data; + wire sprReadSPR_valid; + wire [31:0] sprReadSPR_payload_data; + reg decode_arbitration_haltItself; + reg decode_arbitration_haltByOther; + reg decode_arbitration_removeIt; + wire decode_arbitration_flushIt; + wire decode_arbitration_flushNext; + wire decode_arbitration_isValid; + wire decode_arbitration_isStuck; + wire decode_arbitration_isStuckByOthers; + wire decode_arbitration_isFlushed; + wire decode_arbitration_isMoving; + wire decode_arbitration_isFiring; + reg execute_arbitration_haltItself; + reg execute_arbitration_haltByOther; + reg execute_arbitration_removeIt; + wire execute_arbitration_flushIt; + wire execute_arbitration_flushNext; + reg execute_arbitration_isValid; + wire execute_arbitration_isStuck; + wire execute_arbitration_isStuckByOthers; + wire execute_arbitration_isFlushed; + wire execute_arbitration_isMoving; + wire execute_arbitration_isFiring; + reg memory_arbitration_haltItself; + wire memory_arbitration_haltByOther; + reg memory_arbitration_removeIt; + wire memory_arbitration_flushIt; + reg memory_arbitration_flushNext; + reg memory_arbitration_isValid; + wire memory_arbitration_isStuck; + wire memory_arbitration_isStuckByOthers; + wire memory_arbitration_isFlushed; + wire memory_arbitration_isMoving; + wire memory_arbitration_isFiring; + reg writeBack_arbitration_haltItself; + wire writeBack_arbitration_haltByOther; + reg writeBack_arbitration_removeIt; + reg writeBack_arbitration_flushIt; + reg writeBack_arbitration_flushNext; + reg writeBack_arbitration_isValid; + wire writeBack_arbitration_isStuck; + wire writeBack_arbitration_isStuckByOthers; + wire writeBack_arbitration_isFlushed; + wire writeBack_arbitration_isMoving; + wire writeBack_arbitration_isFiring; + wire [31:0] lastStageInstruction /* verilator public */ ; + wire [31:0] lastStagePc /* verilator public */ ; + wire lastStageIsValid /* verilator public */ ; + wire lastStageIsFiring /* verilator public */ ; + reg IBusCachedPlugin_fetcherHalt; + reg IBusCachedPlugin_incomingInstruction; + wire IBusCachedPlugin_fetchPrediction_cmd_hadBranch; + wire [31:0] IBusCachedPlugin_fetchPrediction_cmd_targetPc; + wire IBusCachedPlugin_fetchPrediction_rsp_wasRight; + wire [31:0] IBusCachedPlugin_fetchPrediction_rsp_finalPc; + wire [31:0] IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord; + wire IBusCachedPlugin_pcValids_0; + wire IBusCachedPlugin_pcValids_1; + wire IBusCachedPlugin_pcValids_2; + wire IBusCachedPlugin_pcValids_3; + reg IBusCachedPlugin_decodeExceptionPort_valid; + reg [3:0] IBusCachedPlugin_decodeExceptionPort_payload_code; + reg [31:0] IBusCachedPlugin_decodeExceptionPort_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type IBusCachedPlugin_decodeExceptionPort_payload_codePPC; + wire [6:0] IBusCachedPlugin_decodeExceptionPort_payload_imm; + wire IBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] IBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire IBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] IBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire IBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire IBusCachedPlugin_mmuBus_rsp_allowRead; + wire IBusCachedPlugin_mmuBus_rsp_allowWrite; + wire IBusCachedPlugin_mmuBus_rsp_allowExecute; + wire IBusCachedPlugin_mmuBus_rsp_exception; + wire IBusCachedPlugin_mmuBus_rsp_refilling; + wire IBusCachedPlugin_mmuBus_spr_valid; + wire [9:0] IBusCachedPlugin_mmuBus_spr_payload_id; + wire [31:0] IBusCachedPlugin_mmuBus_spr_payload_data; + wire IBusCachedPlugin_mmuBus_end; + wire IBusCachedPlugin_mmuBus_busy; + wire DBusCachedPlugin_mmuBus_cmd_isValid; + wire [31:0] DBusCachedPlugin_mmuBus_cmd_virtualAddress; + wire DBusCachedPlugin_mmuBus_cmd_bypassTranslation; + wire [31:0] DBusCachedPlugin_mmuBus_rsp_physicalAddress; + wire DBusCachedPlugin_mmuBus_rsp_isIoAccess; + wire DBusCachedPlugin_mmuBus_rsp_allowRead; + wire DBusCachedPlugin_mmuBus_rsp_allowWrite; + wire DBusCachedPlugin_mmuBus_rsp_allowExecute; + wire DBusCachedPlugin_mmuBus_rsp_exception; + wire DBusCachedPlugin_mmuBus_rsp_refilling; + wire DBusCachedPlugin_mmuBus_spr_valid; + wire [9:0] DBusCachedPlugin_mmuBus_spr_payload_id; + wire [31:0] DBusCachedPlugin_mmuBus_spr_payload_data; + wire DBusCachedPlugin_mmuBus_end; + wire DBusCachedPlugin_mmuBus_busy; + reg DBusCachedPlugin_redoBranch_valid; + wire [31:0] DBusCachedPlugin_redoBranch_payload; + reg DBusCachedPlugin_exceptionBus_valid; + reg [3:0] DBusCachedPlugin_exceptionBus_payload_code; + reg [31:0] DBusCachedPlugin_exceptionBus_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type DBusCachedPlugin_exceptionBus_payload_codePPC; + wire [6:0] DBusCachedPlugin_exceptionBus_payload_imm; + reg decodeExceptionPort_valid; + reg [3:0] decodeExceptionPort_payload_code; + reg [31:0] decodeExceptionPort_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type decodeExceptionPort_payload_codePPC; + wire [6:0] decodeExceptionPort_payload_imm; + wire BranchPlugin_jumpInterface_valid; + wire [31:0] BranchPlugin_jumpInterface_payload; + wire BranchPlugin_branchExceptionPort_valid; + wire [3:0] BranchPlugin_branchExceptionPort_payload_code; + reg [31:0] BranchPlugin_branchExceptionPort_payload_badAddr; + wire `ExcpEnum_defaultEncoding_type BranchPlugin_branchExceptionPort_payload_codePPC; + wire [6:0] BranchPlugin_branchExceptionPort_payload_imm; + reg SPRPlugin_jumpInterface_valid; + reg [31:0] SPRPlugin_jumpInterface_payload; + wire SPRPlugin_exceptionPendings_0; + wire SPRPlugin_exceptionPendings_1; + wire SPRPlugin_exceptionPendings_2; + wire SPRPlugin_exceptionPendings_3; + wire contextSwitching; + wire [1:0] SPRPlugin_privilege; + wire SPRPlugin_forceMachineWire; + reg SPRPlugin_msr_ir; + wire SPRPlugin_msr_dr; + wire SPRPlugin_msr_pr; + reg SPRPlugin_selfException_valid; + reg [3:0] SPRPlugin_selfException_payload_code; + reg [31:0] SPRPlugin_selfException_payload_badAddr; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_selfException_payload_codePPC; + reg [6:0] SPRPlugin_selfException_payload_imm; + wire SPRPlugin_allowInterrupts; + wire SPRPlugin_allowException; + wire IBusCachedPlugin_externalFlush; + wire IBusCachedPlugin_jump_pcLoad_valid; + wire [31:0] IBusCachedPlugin_jump_pcLoad_payload; + wire [2:0] _zz_132_; + wire [2:0] _zz_133_; + wire _zz_134_; + wire _zz_135_; + wire IBusCachedPlugin_fetchPc_output_valid; + wire IBusCachedPlugin_fetchPc_output_ready; + wire [31:0] IBusCachedPlugin_fetchPc_output_payload; + reg [31:0] IBusCachedPlugin_fetchPc_pcReg /* verilator public */ ; + reg IBusCachedPlugin_fetchPc_correction; + reg IBusCachedPlugin_fetchPc_correctionReg; + wire IBusCachedPlugin_fetchPc_corrected; + wire IBusCachedPlugin_fetchPc_pcRegPropagate; + reg IBusCachedPlugin_fetchPc_booted; + reg IBusCachedPlugin_fetchPc_inc; + reg [31:0] IBusCachedPlugin_fetchPc_pc; + wire IBusCachedPlugin_fetchPc_predictionPcLoad_valid; + wire [31:0] IBusCachedPlugin_fetchPc_predictionPcLoad_payload; + wire IBusCachedPlugin_fetchPc_redo_valid; + wire [31:0] IBusCachedPlugin_fetchPc_redo_payload; + reg IBusCachedPlugin_fetchPc_flushed; + reg IBusCachedPlugin_iBusRsp_redoFetch; + wire IBusCachedPlugin_iBusRsp_stages_0_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_0_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_0_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_0_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_0_halt; + wire IBusCachedPlugin_iBusRsp_stages_1_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_1_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_1_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_1_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_1_halt; + wire IBusCachedPlugin_iBusRsp_stages_2_input_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_input_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_input_payload; + wire IBusCachedPlugin_iBusRsp_stages_2_output_valid; + wire IBusCachedPlugin_iBusRsp_stages_2_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_stages_2_output_payload; + reg IBusCachedPlugin_iBusRsp_stages_2_halt; + wire _zz_136_; + wire _zz_137_; + wire _zz_138_; + wire IBusCachedPlugin_iBusRsp_flush; + wire _zz_139_; + reg _zz_140_; + reg [31:0] _zz_141_; + wire _zz_142_; + reg _zz_143_; + reg [31:0] _zz_144_; + reg IBusCachedPlugin_iBusRsp_readyForError; + wire IBusCachedPlugin_iBusRsp_output_valid; + wire IBusCachedPlugin_iBusRsp_output_ready; + wire [31:0] IBusCachedPlugin_iBusRsp_output_payload_pc; + wire IBusCachedPlugin_iBusRsp_output_payload_rsp_error; + reg [31:0] IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + wire IBusCachedPlugin_iBusRsp_output_payload_isRvc; + reg IBusCachedPlugin_injector_nextPcCalc_valids_0; + reg IBusCachedPlugin_injector_nextPcCalc_valids_1; + reg IBusCachedPlugin_injector_nextPcCalc_valids_2; + reg IBusCachedPlugin_injector_nextPcCalc_valids_3; + reg IBusCachedPlugin_injector_nextPcCalc_valids_4; + wire IBusCachedPlugin_predictor_historyWriteDelayPatched_valid; + wire [9:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address; + wire [19:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source; + wire [1:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; + wire [31:0] IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target; + reg IBusCachedPlugin_predictor_historyWrite_valid; + wire [9:0] IBusCachedPlugin_predictor_historyWrite_payload_address; + wire [19:0] IBusCachedPlugin_predictor_historyWrite_payload_data_source; + reg [1:0] IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish; + wire [31:0] IBusCachedPlugin_predictor_historyWrite_payload_data_target; + reg IBusCachedPlugin_predictor_writeLast_valid; + reg [9:0] IBusCachedPlugin_predictor_writeLast_payload_address; + reg [19:0] IBusCachedPlugin_predictor_writeLast_payload_data_source; + reg [1:0] IBusCachedPlugin_predictor_writeLast_payload_data_branchWish; + reg [31:0] IBusCachedPlugin_predictor_writeLast_payload_data_target; + wire [29:0] _zz_145_; + wire [19:0] IBusCachedPlugin_predictor_buffer_line_source; + wire [1:0] IBusCachedPlugin_predictor_buffer_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_buffer_line_target; + wire [53:0] _zz_146_; + reg IBusCachedPlugin_predictor_buffer_pcCorrected; + wire IBusCachedPlugin_predictor_buffer_hazard; + reg [19:0] IBusCachedPlugin_predictor_line_source; + reg [1:0] IBusCachedPlugin_predictor_line_branchWish; + reg [31:0] IBusCachedPlugin_predictor_line_target; + reg IBusCachedPlugin_predictor_buffer_hazard_regNextWhen; + wire IBusCachedPlugin_predictor_hazard; + wire IBusCachedPlugin_predictor_hit; + wire IBusCachedPlugin_predictor_fetchContext_hazard; + wire IBusCachedPlugin_predictor_fetchContext_hit; + wire [19:0] IBusCachedPlugin_predictor_fetchContext_line_source; + wire [1:0] IBusCachedPlugin_predictor_fetchContext_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_fetchContext_line_target; + reg IBusCachedPlugin_predictor_iBusRspContext_hazard; + reg IBusCachedPlugin_predictor_iBusRspContext_hit; + reg [19:0] IBusCachedPlugin_predictor_iBusRspContext_line_source; + reg [1:0] IBusCachedPlugin_predictor_iBusRspContext_line_branchWish; + reg [31:0] IBusCachedPlugin_predictor_iBusRspContext_line_target; + wire IBusCachedPlugin_predictor_iBusRspContextOutput_hazard; + wire IBusCachedPlugin_predictor_iBusRspContextOutput_hit; + wire [19:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_source; + wire [1:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_iBusRspContextOutput_line_target; + wire IBusCachedPlugin_predictor_injectorContext_hazard; + wire IBusCachedPlugin_predictor_injectorContext_hit; + wire [19:0] IBusCachedPlugin_predictor_injectorContext_line_source; + wire [1:0] IBusCachedPlugin_predictor_injectorContext_line_branchWish; + wire [31:0] IBusCachedPlugin_predictor_injectorContext_line_target; + wire iBus_cmd_valid; + wire iBus_cmd_ready; + reg [31:0] iBus_cmd_payload_address; + wire [2:0] iBus_cmd_payload_size; + wire iBus_rsp_valid; + wire [31:0] iBus_rsp_payload_data; + wire iBus_rsp_payload_error; + wire [31:0] _zz_147_; + reg [31:0] IBusCachedPlugin_rspCounter; + wire IBusCachedPlugin_s0_tightlyCoupledHit; + wire IBusCachedPlugin_s1_bigEndian; + reg IBusCachedPlugin_s1_tightlyCoupledHit; + wire IBusCachedPlugin_s2_bigEndian; + reg IBusCachedPlugin_s2_tightlyCoupledHit; + wire IBusCachedPlugin_rsp_iBusRspOutputHalt; + wire IBusCachedPlugin_rsp_issueDetected; + reg IBusCachedPlugin_rsp_redoFetch; + wire IBusCachedPlugin_rsp_bigEndian; + wire dBus_cmd_valid; + wire dBus_cmd_ready; + wire dBus_cmd_payload_wr; + wire [31:0] dBus_cmd_payload_address; + wire [31:0] dBus_cmd_payload_data; + wire [3:0] dBus_cmd_payload_mask; + wire [2:0] dBus_cmd_payload_length; + wire dBus_cmd_payload_last; + wire dBus_rsp_valid; + wire [31:0] dBus_rsp_payload_data; + wire dBus_rsp_payload_error; + wire dataCache_1__io_mem_cmd_m2sPipe_valid; + wire dataCache_1__io_mem_cmd_m2sPipe_ready; + wire dataCache_1__io_mem_cmd_m2sPipe_payload_wr; + wire [31:0] dataCache_1__io_mem_cmd_m2sPipe_payload_address; + wire [31:0] dataCache_1__io_mem_cmd_m2sPipe_payload_data; + wire [3:0] dataCache_1__io_mem_cmd_m2sPipe_payload_mask; + wire [2:0] dataCache_1__io_mem_cmd_m2sPipe_payload_length; + wire dataCache_1__io_mem_cmd_m2sPipe_payload_last; + reg dataCache_1__io_mem_cmd_m2sPipe_rValid; + reg dataCache_1__io_mem_cmd_m2sPipe_rData_wr; + reg [31:0] dataCache_1__io_mem_cmd_m2sPipe_rData_address; + reg [31:0] dataCache_1__io_mem_cmd_m2sPipe_rData_data; + reg [3:0] dataCache_1__io_mem_cmd_m2sPipe_rData_mask; + reg [2:0] dataCache_1__io_mem_cmd_m2sPipe_rData_length; + reg dataCache_1__io_mem_cmd_m2sPipe_rData_last; + wire [31:0] _zz_148_; + reg [31:0] DBusCachedPlugin_rspCounter; + wire execute_DBusCachedPlugin_bigEndian; + reg [1:0] execute_DBusCachedPlugin_size; + reg [31:0] _zz_149_; + wire [15:0] _zz_150_; + wire [15:0] _zz_151_; + reg [31:0] _zz_152_; + wire writeBack_DBusCachedPlugin_bigEndian; + reg [31:0] writeBack_DBusCachedPlugin_rspShifted; + reg [31:0] writeBack_DBusCachedPlugin_rspFormated; + reg [15:0] writeBack_DBusCachedPlugin_rspHW; + wire [15:0] _zz_153_; + wire [15:0] _zz_154_; + wire _zz_155_; + reg [15:0] _zz_156_; + wire [79:0] _zz_157_; + wire _zz_158_; + wire _zz_159_; + wire _zz_160_; + wire _zz_161_; + wire _zz_162_; + wire _zz_163_; + wire _zz_164_; + wire _zz_165_; + wire _zz_166_; + wire _zz_167_; + wire _zz_168_; + wire _zz_169_; + wire _zz_170_; + wire _zz_171_; + wire _zz_172_; + wire _zz_173_; + wire _zz_174_; + wire _zz_175_; + wire _zz_176_; + wire _zz_177_; + wire _zz_178_; + wire _zz_179_; + wire _zz_180_; + wire _zz_181_; + wire _zz_182_; + wire _zz_183_; + wire _zz_184_; + wire _zz_185_; + wire _zz_186_; + wire _zz_187_; + wire _zz_188_; + wire _zz_189_; + wire _zz_190_; + wire _zz_191_; + wire _zz_192_; + wire _zz_193_; + wire _zz_194_; + wire _zz_195_; + wire _zz_196_; + wire _zz_197_; + wire _zz_198_; + wire _zz_199_; + wire _zz_200_; + wire _zz_201_; + wire _zz_202_; + wire _zz_203_; + wire _zz_204_; + wire _zz_205_; + wire _zz_206_; + wire _zz_207_; + wire _zz_208_; + wire _zz_209_; + wire _zz_210_; + wire _zz_211_; + wire _zz_212_; + wire _zz_213_; + wire _zz_214_; + wire _zz_215_; + wire _zz_216_; + wire _zz_217_; + wire _zz_218_; + wire _zz_219_; + wire _zz_220_; + wire _zz_221_; + wire _zz_222_; + wire `AluSpecCtrlEnum_defaultEncoding_type _zz_223_; + wire `Src3CtrlEnum_defaultEncoding_type _zz_224_; + wire `DataSizeEnum_defaultEncoding_type _zz_225_; + wire `AluCtrlEnum_defaultEncoding_type _zz_226_; + wire `TgtCtrlEnum_defaultEncoding_type _zz_227_; + wire `BranchCtrlEnum_defaultEncoding_type _zz_228_; + wire `AluRimiCtrlEnum_defaultEncoding_type _zz_229_; + wire `AluBitwiseCtrlEnum_defaultEncoding_type _zz_230_; + wire `CRLogCtrlEnum_defaultEncoding_type _zz_231_; + wire `Src2CtrlEnum_defaultEncoding_type _zz_232_; + wire `Src1CtrlEnum_defaultEncoding_type _zz_233_; + wire `AluRimiAmtEnum_defaultEncoding_type _zz_234_; + wire `EnvCtrlEnum_defaultEncoding_type _zz_235_; + wire `CRMoveCtrlEnum_defaultEncoding_type _zz_236_; + reg _zz_237_; + wire [4:0] decode_RegFilePlugin_regFileReadAddress1; + wire [4:0] decode_RegFilePlugin_regFileReadAddress2; + wire [31:0] decode_RegFilePlugin_raData_pre; + wire [31:0] decode_RegFilePlugin_rbData_pre; + wire [4:0] decode_RegFilePlugin_regFileReadAddress3; + wire [31:0] decode_RegFilePlugin_rsData; + reg [31:0] decode_RegFilePlugin_raData; + reg [31:0] decode_RegFilePlugin_rbData; + reg [4:0] _zz_238_; + reg [4:0] _zz_239_; + reg [4:0] _zz_240_; + reg lastStageRegFileWrite_valid /* verilator public */ ; + reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + wire UpdateRegFileWrite_valid /* verilator public */ ; + wire UpdateRegFileWrite_payload_valid /* verilator public */ ; + wire [4:0] UpdateRegFileWrite_payload_address /* verilator public */ ; + wire [31:0] UpdateRegFileWrite_payload_data /* verilator public */ ; + reg writeBack_RegFilePlugin_crBusPort_valid; + reg `CRBusCmdEnum_defaultEncoding_type writeBack_RegFilePlugin_crBusPort_payload_op; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_ba; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_bb; + wire [4:0] writeBack_RegFilePlugin_crBusPort_payload_bt; + reg [31:0] writeBack_RegFilePlugin_crBusPort_payload_imm; + wire [7:0] writeBack_RegFilePlugin_crBusPort_payload_fxm; + reg writeBack_RegFilePlugin_xerBusPort_valid; + wire writeBack_RegFilePlugin_xerBusPort_payload_validOV; + wire writeBack_RegFilePlugin_xerBusPort_payload_validCA; + wire [1:0] writeBack_RegFilePlugin_xerBusPort_payload_imm; + reg writeBack_RegFilePlugin_sprWriteXERPort_valid; + wire [9:0] writeBack_RegFilePlugin_sprWriteXERPort_payload_id; + wire [31:0] writeBack_RegFilePlugin_sprWriteXERPort_payload_data; + reg writeBack_RegFilePlugin_sprWriteCLTPort_valid; + wire [9:0] writeBack_RegFilePlugin_sprWriteCLTPort_payload_id; + wire [31:0] writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + reg _zz_241_; + reg _zz_242_; + reg _zz_243_; + reg [1:0] _zz_244_; + reg _zz_245_; + reg [31:0] ALU2_XER; + reg ALU2_sprReadValid; + wire _zz_246_; + reg [23:0] _zz_247_; + wire _zz_248_; + reg [15:0] _zz_249_; + reg [31:0] ALU2_bitwise; + reg [1:0] ALU2_bitwise_enc_cr; + reg [2:0] ALU2_bitwise_cr; + reg [4:0] ALU2_amount; + wire [4:0] ALU2_maskMB; + wire [4:0] ALU2_maskME; + reg [31:0] ALU2_mask; + reg [31:0] ALU2_maskNorm; + reg [31:0] ALU2_maskInvt; + wire [31:0] ALU2_rimi; + wire [31:0] _zz_250_; + wire [31:0] _zz_251_; + reg [31:0] _zz_252_; + reg ALU2_sraw_ca; + wire [31:0] ALU2_sraw_wtf; + reg [1:0] ALU2_rimi_enc_cr; + reg [2:0] ALU2_rimi_cr; + reg [5:0] cntzero_lz; + reg [31:0] _zz_253_; + reg [5:0] cntzero_msb; + reg [5:0] cntzero_tz; + reg [5:0] cntzero_lsb; + wire [3:0] popcnt_pb0; + wire [3:0] popcnt_pb1; + wire [3:0] popcnt_pb2; + wire [3:0] popcnt_pb3; + wire [7:0] _zz_254_; + wire [7:0] _zz_255_; + wire [7:0] _zz_256_; + wire [7:0] _zz_257_; + wire [5:0] popcnt_pw0; + wire [31:0] _zz_258_; + reg [31:0] popcnt_cmpb; + wire popcnt_prtyw; + reg [31:0] ALU2_spec; + reg [31:0] _zz_259_; + reg _zz_260_; + reg _zz_261_; + reg [31:0] _zz_262_; + reg [4:0] _zz_263_; + reg ALU2_xer_ca; + wire ALU2_xer_ov; + wire ALU2_xer_so; + wire ALU2_xerBus_validOV; + wire ALU2_xerBus_validCA; + wire [1:0] ALU2_xerBus_imm; + reg [2:0] ALU2_alu_cr; + reg [2:0] ALU2_cr0_val_a; + wire [3:0] ALU2_cr0_val; + wire ALU2_cr_record; + wire ALU2_cr_mcrf; + wire ALU2_cr_update_valid; + reg `CRBusCmdEnum_defaultEncoding_type ALU2_crBus_op; + reg [4:0] ALU2_crBus_ba; + reg [4:0] ALU2_crBus_bb; + reg [4:0] ALU2_crBus_bt; + reg [31:0] ALU2_crBus_imm; + reg [7:0] ALU2_crBus_fxm; + wire [4:0] SRC1_ra; + wire [4:0] SRC1_rb; + wire [4:0] SRC1_rs; + wire [4:0] SRC1_rt; + reg [31:0] _zz_264_; + wire _zz_265_; + reg [15:0] _zz_266_; + reg [31:0] _zz_267_; + reg [0:0] _zz_268_; + wire [32:0] SRC2_adder; + wire [31:0] SRC2_ra; + wire [31:0] SRC2_rb; + wire [0:0] SRC2_cin; + wire [1:0] SRC2_add_cr; + wire [1:0] SRC2_cmp_cr; + wire SRC2_ca; + wire SRC2_ov; + reg _zz_269_; + reg [4:0] _zz_270_; + reg [31:0] _zz_271_; + reg _zz_272_; + reg `CRBusCmdEnum_defaultEncoding_type _zz_273_; + reg [31:0] _zz_274_; + wire MUL1_aSigned; + wire MUL1_bSigned; + wire [31:0] MUL1_a; + wire [31:0] MUL1_b; + wire [15:0] MUL1_aULow; + wire [15:0] MUL1_bULow; + wire [16:0] MUL1_aSLow; + wire [16:0] MUL1_bSLow; + wire [16:0] MUL1_aHigh; + wire [16:0] MUL1_bHigh; + wire [65:0] MUL3_result; + wire MUL3_xer_ov; + reg MUL3_xer_so; + reg [31:0] MUL3_result32; + wire [1:0] MUL3_cr; + reg [3:0] MUL3_cr_decode; + wire MUL3_cr_record; + reg [32:0] MULDIV_rs1; + reg [31:0] MULDIV_rs2; + reg [64:0] MULDIV_accumulator; + wire MULDIV_frontendOk; + reg MULDIV1_needRevert; + reg MULDIV1_counter_willIncrement; + reg MULDIV1_counter_willClear; + reg [5:0] MULDIV1_counter_valueNext; + reg [5:0] MULDIV1_counter_value; + wire MULDIV1_counter_willOverflowIfInc; + wire MULDIV1_counter_willOverflow; + reg MULDIV1_done; + reg [31:0] MULDIV1_result; + reg MULDIV1_crBusPort_valid; + reg `CRBusCmdEnum_defaultEncoding_type MULDIV1_crBusPort_payload_op; + wire [4:0] MULDIV1_crBusPort_payload_ba; + wire [4:0] MULDIV1_crBusPort_payload_bb; + wire [4:0] MULDIV1_crBusPort_payload_bt; + reg [31:0] MULDIV1_crBusPort_payload_imm; + wire [7:0] MULDIV1_crBusPort_payload_fxm; + reg MULDIV1_xerBusPort_valid; + reg MULDIV1_xerBusPort_payload_validOV; + reg MULDIV1_xerBusPort_payload_validCA; + reg [1:0] MULDIV1_xerBusPort_payload_imm; + wire [31:0] _zz_275_; + wire [32:0] MULDIV1_stage_0_remainderShifted; + wire [32:0] MULDIV1_stage_0_remainderMinusDenominator; + wire [31:0] MULDIV1_stage_0_outRemainder; + wire [31:0] MULDIV1_stage_0_outNumerator; + wire [31:0] _zz_276_; + wire _zz_277_; + reg _zz_278_; + reg [3:0] _zz_279_; + wire _zz_280_; + wire _zz_281_; + reg [32:0] _zz_282_; + reg _zz_283_ /* verilator public */ ; + reg _zz_284_ /* verilator public */ ; + reg _zz_285_ /* verilator public */ ; + wire Hazards_writeBackWrites_valid; + wire [4:0] Hazards_writeBackWrites_payload_address; + wire [31:0] Hazards_writeBackWrites_payload_data; + reg Hazards_writeBackBuffer_valid; + reg [4:0] Hazards_writeBackBuffer_payload_address; + reg [31:0] Hazards_writeBackBuffer_payload_data; + wire Hazards_addr0Match; + wire Hazards_addr1Match; + wire Hazards_addr2Match; + wire _zz_286_; + wire _zz_287_; + wire _zz_288_; + wire _zz_289_; + wire _zz_290_; + wire _zz_291_; + wire _zz_292_; + wire _zz_293_; + wire _zz_294_; + wire _zz_295_; + reg _zz_296_; + reg _zz_297_; + reg _zz_298_; + reg _zz_299_; + reg _zz_300_; + reg _zz_301_; + reg _zz_302_; + reg _zz_303_; + reg [3:0] _zz_304_; + reg _zz_305_; + reg _zz_306_; + reg _zz_307_; + wire _zz_308_; + reg _zz_309_; + reg _zz_310_; + wire _zz_311_; + reg _zz_312_; + reg _zz_313_; + reg _zz_314_; + reg _zz_315_; + reg _zz_316_; + reg _zz_317_; + reg _zz_318_; + reg _zz_319_; + reg [3:0] _zz_320_; + reg _zz_321_; + reg _zz_322_; + wire _zz_323_; + reg _zz_324_; + reg _zz_325_; + wire _zz_326_; + reg decode_BranchPlugin_bc; + wire [4:0] decode_BranchPlugin_bi; + wire [2:0] decode_BranchPlugin_crbiField; + wire [4:0] decode_BranchPlugin_bo; + wire decode_BranchPlugin_crbiRead; + reg [7:0] decode_BranchPlugin_crFieldRd; + reg [31:0] execute_BranchPlugin_CR; + reg [31:0] execute_BranchPlugin_CTR; + reg [31:0] execute_BranchPlugin_LR; + reg [31:0] execute_BranchPlugin_TAR; + wire execute_BranchPlugin_ctrOne; + reg [31:0] execute_BranchPlugin_sprReadData; + reg execute_BranchPlugin_sprReadValid; + reg execute_BranchPlugin_crReadValid; + reg `CRBusCmdEnum_defaultEncoding_type execute_BranchPlugin_crBusPort_op; + reg [4:0] execute_BranchPlugin_crBusPort_ba; + reg [4:0] execute_BranchPlugin_crBusPort_bb; + reg [4:0] execute_BranchPlugin_crBusPort_bt; + reg [31:0] execute_BranchPlugin_crBusPort_imm; + reg [7:0] execute_BranchPlugin_crBusPort_fxm; + wire execute_BranchPlugin_crBusPort_valid; + reg [3:0] _zz_327_; + wire [3:0] _zz_328_; + wire _zz_329_; + reg [5:0] _zz_330_; + wire [31:0] execute_BranchPlugin_li; + wire _zz_331_; + reg [15:0] _zz_332_; + wire [31:0] execute_BranchPlugin_bd; + wire _zz_333_; + reg [31:0] execute_BranchPlugin_aaMask; + reg [31:0] execute_BranchPlugin_branch_tgt0; + reg [31:0] execute_BranchPlugin_branch_tgt1; + wire execute_BranchPlugin_use_li; + wire [31:0] execute_BranchPlugin_branch_tgt2; + reg [31:0] execute_BranchPlugin_branchAdder; + wire [4:0] execute_BranchPlugin_opbi; + wire [2:0] execute_BranchPlugin_crbiField; + wire [1:0] execute_BranchPlugin_crbiBit; + reg execute_BranchPlugin_crbi; + wire execute_BranchPlugin_ctrOK; + wire [4:0] execute_BranchPlugin_bo; + reg [3:0] execute_BranchPlugin_crBypassPort_field; + wire [0:0] execute_BranchPlugin_crBypassPort_stageID; + wire execute_BranchPlugin_crBypassPort_valid; + wire execute_BranchPlugin_condOK; + wire execute_BranchPlugin_lk; + reg _zz_334_; + reg _zz_335_; + reg _zz_336_; + wire memory_BranchPlugin_predictionMissmatch; + reg MSR_VEC; + reg MSR_VSX; + reg MSR_EE; + reg MSR_PR; + reg MSR_FP; + reg MSR_ME; + reg MSR_FE0; + reg MSR_FE1; + reg MSR_IR; + reg MSR_DR; + reg MSR_PMM; + reg MSR_RI; + reg MSR_LE; + reg [31:0] SPRPlugin_srr0; + reg [31:0] SPRPlugin_srr1; + reg [31:0] SPRPlugin_dar; + reg [31:0] SPRPlugin_sprg3; + reg [31:0] SPRPlugin_dsisr; + (* ram_style = "block" *) reg [31:0] SPRPlugin_tb; + wire SPRPlugin_incTB; + (* ram_style = "block" *) reg [31:0] SPRPlugin_dec; + reg SPRPlugin_dec31Prev; + reg SPRPlugin_intDec; + reg SPRPlugin_intDecTkn; + reg [31:0] SPRPlugin_minstret; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_decode; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_execute; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_memory; + reg SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + reg SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + reg [3:0] SPRPlugin_exceptionPortCtrl_exceptionContext_code; + reg [31:0] SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC; + reg [6:0] SPRPlugin_exceptionPortCtrl_exceptionContext_imm; + wire `ExcpEnum_defaultEncoding_type _zz_337_; + wire [1:0] _zz_338_; + wire _zz_339_; + wire `ExcpEnum_defaultEncoding_type _zz_340_; + reg _zz_341_; + reg _zz_342_; + reg _zz_343_; + reg _zz_344_; + reg SPRPlugin_interrupt_valid; + reg [3:0] SPRPlugin_interrupt_code /* verilator public */ ; + reg [1:0] SPRPlugin_interrupt_targetPrivilege; + reg SPRPlugin_pipelineLiberator_pcValids_0; + reg SPRPlugin_pipelineLiberator_pcValids_1; + reg SPRPlugin_pipelineLiberator_pcValids_2; + wire SPRPlugin_pipelineLiberator_active; + reg SPRPlugin_pipelineLiberator_done; + wire SPRPlugin_exception; + reg [31:0] SPRPlugin_darSave; + reg SPRPlugin_hadException; + reg SPRPlugin_interruptJump /* verilator public */ ; + reg `ExcpEnum_defaultEncoding_type SPRPlugin_intType; + reg [31:0] SPRPlugin_intSRR0; + reg [31:0] _zz_345_; + wire execute_SPRPLUGIN_blockedBySideEffects; + reg execute_SPRPLUGIN_sprHere; + reg execute_SPRPLUGIN_illegalAccess; + wire _zz_346_; + reg [15:0] _zz_347_; + wire [31:0] execute_SPRPLUGIN_si; + wire [4:0] execute_SPRPLUGIN_tmask; + reg execute_SPRPLUGIN_trap; + wire [3:0] execute_SPRPLUGIN_opExcp_code; + wire [31:0] execute_SPRPLUGIN_opExcp_badAddr; + wire `ExcpEnum_defaultEncoding_type execute_SPRPLUGIN_opExcp_codePPC; + wire [6:0] execute_SPRPLUGIN_opExcp_imm; + reg _zz_348_; + wire [31:0] execute_SPRPLUGIN_readData; + wire [31:0] execute_SPRPLUGIN_readToWriteData; + wire execute_SPRPLUGIN_sprg3read; + wire execute_SPRPLUGIN_privViolation; + wire execute_SPRPLUGIN_readInstruction; + wire execute_SPRPLUGIN_readEnable; + wire execute_SPRPLUGIN_writeInstruction; + wire execute_SPRPLUGIN_writeEnable; + reg [10:0] execute_SPRPLUGIN_SPRAddress; + reg [31:0] decode_to_execute_RB; + reg [33:0] execute_to_memory_MUL_HH; + reg [33:0] memory_to_writeBack_MUL_HH; + reg decode_to_execute_DECODER_stageables_28; + reg `AluRimiAmtEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_44; + reg [10:0] execute_to_memory_SPR_ID; + reg [10:0] memory_to_writeBack_SPR_ID; + reg decode_to_execute_DECODER_stageables_36; + reg execute_to_memory_DECODER_stageables_36; + reg memory_to_writeBack_DECODER_stageables_36; + reg decode_to_execute_PREDICTION_CONTEXT_hazard; + reg decode_to_execute_PREDICTION_CONTEXT_hit; + reg [19:0] decode_to_execute_PREDICTION_CONTEXT_line_source; + reg [1:0] decode_to_execute_PREDICTION_CONTEXT_line_branchWish; + reg [31:0] decode_to_execute_PREDICTION_CONTEXT_line_target; + reg execute_to_memory_PREDICTION_CONTEXT_hazard; + reg execute_to_memory_PREDICTION_CONTEXT_hit; + reg [19:0] execute_to_memory_PREDICTION_CONTEXT_line_source; + reg [1:0] execute_to_memory_PREDICTION_CONTEXT_line_branchWish; + reg [31:0] execute_to_memory_PREDICTION_CONTEXT_line_target; + reg `EnvCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_49; + reg `EnvCtrlEnum_defaultEncoding_type execute_to_memory_DECODER_stageables_49; + reg `EnvCtrlEnum_defaultEncoding_type memory_to_writeBack_DECODER_stageables_49; + reg decode_to_execute_DECODER_stageables_48; + reg execute_to_memory_XER_WRITE_validOV; + reg execute_to_memory_XER_WRITE_validCA; + reg [1:0] execute_to_memory_XER_WRITE_imm; + reg memory_to_writeBack_XER_WRITE_validOV; + reg memory_to_writeBack_XER_WRITE_validCA; + reg [1:0] memory_to_writeBack_XER_WRITE_imm; + reg [31:0] execute_to_memory_LOAD_UPDATE_DATA; + reg [31:0] memory_to_writeBack_LOAD_UPDATE_DATA; + reg `BranchCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_13; + reg decode_to_execute_DECODER_stageables_55; + reg execute_to_memory_DECODER_stageables_55; + reg memory_to_writeBack_DECODER_stageables_55; + reg decode_to_execute_DECODER_stageables_57; + reg `CRLogCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_20; + reg [31:0] execute_to_memory_REGFILE_WRITE_DATA; + reg [31:0] memory_to_writeBack_REGFILE_WRITE_DATA; + reg decode_to_execute_DECODER_stageables_54; + reg decode_to_execute_DECODER_stageables_32; + reg execute_to_memory_DECODER_stageables_32; + reg memory_to_writeBack_DECODER_stageables_32; + reg [1:0] execute_to_memory_MEMORY_ADDRESS_LOW; + reg [1:0] memory_to_writeBack_MEMORY_ADDRESS_LOW; + reg decode_to_execute_DECODER_stageables_22; + reg [31:0] decode_to_execute_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_FORMAL_PC_NEXT; + reg [31:0] memory_to_writeBack_FORMAL_PC_NEXT; + reg [31:0] execute_to_memory_MUL_LL; + reg [4:0] execute_to_memory_LOAD_UPDATE_ADDR; + reg [4:0] memory_to_writeBack_LOAD_UPDATE_ADDR; + reg decode_to_execute_DECODER_stageables_30; + reg decode_to_execute_DECODER_stageables_52; + reg execute_to_memory_DECODER_stageables_52; + reg memory_to_writeBack_DECODER_stageables_52; + reg [4:0] decode_to_execute_R0_ADDR; + reg [31:0] execute_to_memory_BRANCH_CALC; + reg decode_to_execute_DECODER_stageables_11; + reg `AluRimiCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_16; + reg decode_to_execute_DECODER_stageables_56; + reg execute_to_memory_DECODER_stageables_56; + reg memory_to_writeBack_DECODER_stageables_56; + reg decode_to_execute_DECODER_stageables_39; + reg execute_to_memory_DECODER_stageables_39; + reg memory_to_writeBack_DECODER_stageables_39; + reg execute_to_memory_BRANCH_DO; + reg execute_to_memory_BRANCH_LINK; + reg memory_to_writeBack_BRANCH_LINK; + reg `AluSpecCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_0; + reg decode_to_execute_DECODER_stageables_15; + reg execute_to_memory_DECODER_stageables_15; + reg decode_to_execute_DECODER_stageables_5; + reg execute_to_memory_DECODER_stageables_5; + reg `CRBusCmdEnum_defaultEncoding_type execute_to_memory_CR_WRITE_op; + reg [4:0] execute_to_memory_CR_WRITE_ba; + reg [4:0] execute_to_memory_CR_WRITE_bb; + reg [4:0] execute_to_memory_CR_WRITE_bt; + reg [31:0] execute_to_memory_CR_WRITE_imm; + reg [7:0] execute_to_memory_CR_WRITE_fxm; + reg `CRBusCmdEnum_defaultEncoding_type memory_to_writeBack_CR_WRITE_op; + reg [4:0] memory_to_writeBack_CR_WRITE_ba; + reg [4:0] memory_to_writeBack_CR_WRITE_bb; + reg [4:0] memory_to_writeBack_CR_WRITE_bt; + reg [31:0] memory_to_writeBack_CR_WRITE_imm; + reg [7:0] memory_to_writeBack_CR_WRITE_fxm; + reg [51:0] memory_to_writeBack_MUL_LOW; + reg decode_to_execute_DECODER_stageables_42; + reg [4:0] decode_to_execute_RT_ADDR; + reg [4:0] execute_to_memory_RT_ADDR; + reg [4:0] memory_to_writeBack_RT_ADDR; + reg decode_to_execute_DECODER_stageables_45; + reg execute_to_memory_DECODER_stageables_45; + reg memory_to_writeBack_DECODER_stageables_45; + reg decode_to_execute_DECODER_stageables_9; + reg execute_to_memory_DECODER_stageables_9; + reg memory_to_writeBack_DECODER_stageables_9; + reg [31:0] decode_to_execute_INSTRUCTION; + reg [31:0] execute_to_memory_INSTRUCTION; + reg [31:0] memory_to_writeBack_INSTRUCTION; + reg `AluBitwiseCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_19; + reg decode_to_execute_DECODER_stageables_18; + reg decode_to_execute_DECODER_stageables_34; + reg decode_to_execute_DECODER_stageables_24; + reg execute_to_memory_DECODER_stageables_24; + reg memory_to_writeBack_DECODER_stageables_24; + reg `EndianEnum_defaultEncoding_type decode_to_execute_MSR_ENDIAN; + reg `EndianEnum_defaultEncoding_type execute_to_memory_MSR_ENDIAN; + reg `EndianEnum_defaultEncoding_type memory_to_writeBack_MSR_ENDIAN; + reg [31:0] execute_to_memory_SRC1; + reg [31:0] memory_to_writeBack_SRC1; + reg decode_to_execute_DECODER_stageables_14; + reg decode_to_execute_DECODER_stageables_3; + reg [1:0] execute_to_memory_SRC_CR; + reg [1:0] memory_to_writeBack_SRC_CR; + reg execute_to_memory_BRANCH_DEC; + reg memory_to_writeBack_BRANCH_DEC; + reg [31:0] decode_to_execute_RA; + reg decode_to_execute_DECODER_stageables_2; + reg decode_to_execute_DECODER_stageables_6; + reg decode_to_execute_DECODER_stageables_40; + reg [33:0] execute_to_memory_MUL_LH; + reg decode_to_execute_DECODER_stageables_31; + reg execute_to_memory_DECODER_stageables_31; + reg memory_to_writeBack_DECODER_stageables_31; + reg execute_to_memory_TARGET_MISSMATCH2; + reg decode_to_execute_DECODER_stageables_35; + reg [4:0] execute_to_memory_REGFILE_WRITE_ADDR; + reg [4:0] memory_to_writeBack_REGFILE_WRITE_ADDR; + reg [33:0] execute_to_memory_MUL_HL; + reg decode_to_execute_DECODER_stageables_53; + reg execute_to_memory_DECODER_stageables_53; + reg memory_to_writeBack_DECODER_stageables_53; + reg `CRMoveCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_51; + reg `DataSizeEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_7; + reg `DataSizeEnum_defaultEncoding_type execute_to_memory_DECODER_stageables_7; + reg `DataSizeEnum_defaultEncoding_type memory_to_writeBack_DECODER_stageables_7; + reg [7:0] execute_to_memory_CR_FIELD_WR; + reg [7:0] memory_to_writeBack_CR_FIELD_WR; + reg `Src3CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_1; + reg [31:0] decode_to_execute_RS; + reg decode_to_execute_DECODER_stageables_46; + reg [31:0] execute_to_memory_SRC_ADD; + reg [31:0] memory_to_writeBack_SRC_ADD; + reg decode_to_execute_DECODER_stageables_23; + reg `AluCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_8; + reg decode_to_execute_DECODER_stageables_37; + reg execute_to_memory_DECODER_stageables_37; + reg decode_to_execute_DECODER_stageables_21; + reg `Src2CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_26; + reg [7:0] decode_to_execute_CR_FIELD_RD; + reg decode_to_execute_DECODER_stageables_27; + reg decode_to_execute_DECODER_stageables_43; + reg execute_to_memory_DECODER_stageables_43; + reg `Src1CtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_38; + reg execute_to_memory_XER_SO; + reg memory_to_writeBack_XER_SO; + reg [31:0] decode_to_execute_PC; + reg [31:0] execute_to_memory_PC; + reg [31:0] memory_to_writeBack_PC; + reg [31:0] execute_to_memory_NEXT_PC2; + reg decode_to_execute_DECODER_stageables_25; + reg decode_to_execute_DECODER_stageables_29; + reg `TgtCtrlEnum_defaultEncoding_type decode_to_execute_DECODER_stageables_12; + reg [10:0] _zz_349_; + reg execute_SPRPLUGIN_SPR_1025; + reg execute_SPRPLUGIN_SPR_26; + reg execute_SPRPLUGIN_SPR_27; + reg execute_SPRPLUGIN_SPR_19; + reg execute_SPRPLUGIN_SPR_259; + reg execute_SPRPLUGIN_SPR_18; + reg execute_SPRPLUGIN_SPR_268; + reg execute_SPRPLUGIN_SPR_22; + reg [31:0] _zz_350_; + reg [31:0] _zz_351_; + reg [31:0] _zz_352_; + reg [31:0] _zz_353_; + reg [31:0] _zz_354_; + reg [31:0] _zz_355_; + reg [31:0] _zz_356_; + reg [31:0] _zz_357_; + reg [2:0] _zz_358_; + reg _zz_359_; + reg [31:0] iBusWB_DAT_MISO_regNext; + reg [2:0] _zz_360_; + wire _zz_361_; + wire _zz_362_; + wire _zz_363_; + wire _zz_364_; + wire _zz_365_; + reg _zz_366_; + reg [31:0] dBusWB_DAT_MISO_regNext; + `ifndef SYNTHESIS + reg [15:0] _zz_1__string; + reg [15:0] _zz_2__string; + reg [47:0] _zz_3__string; + reg [47:0] _zz_4__string; + reg [63:0] _zz_5__string; + reg [63:0] _zz_6__string; + reg [39:0] decode_DECODER_stageables_8_string; + reg [39:0] _zz_7__string; + reg [39:0] _zz_8__string; + reg [39:0] _zz_9__string; + reg [31:0] decode_DECODER_stageables_1_string; + reg [31:0] _zz_10__string; + reg [31:0] _zz_11__string; + reg [31:0] _zz_12__string; + reg [15:0] memory_DECODER_stageables_7_string; + reg [15:0] _zz_13__string; + reg [15:0] _zz_14__string; + reg [15:0] _zz_15__string; + reg [15:0] _zz_16__string; + reg [15:0] _zz_17__string; + reg [15:0] decode_DECODER_stageables_7_string; + reg [15:0] _zz_18__string; + reg [15:0] _zz_19__string; + reg [15:0] _zz_20__string; + reg [47:0] decode_DECODER_stageables_51_string; + reg [47:0] _zz_21__string; + reg [47:0] _zz_22__string; + reg [47:0] _zz_23__string; + reg [15:0] memory_MSR_ENDIAN_string; + reg [15:0] _zz_24__string; + reg [15:0] _zz_25__string; + reg [15:0] _zz_26__string; + reg [15:0] _zz_27__string; + reg [15:0] _zz_28__string; + reg [15:0] _zz_29__string; + reg [15:0] _zz_30__string; + reg [47:0] decode_DECODER_stageables_19_string; + reg [47:0] _zz_31__string; + reg [47:0] _zz_32__string; + reg [47:0] _zz_33__string; + reg [47:0] _zz_34__string; + reg [47:0] _zz_35__string; + reg [47:0] execute_CR_WRITE_op_string; + reg [47:0] _zz_36__string; + reg [47:0] _zz_37__string; + reg [47:0] _zz_38__string; + reg [55:0] decode_DECODER_stageables_0_string; + reg [55:0] _zz_39__string; + reg [55:0] _zz_40__string; + reg [55:0] _zz_41__string; + reg [55:0] decode_DECODER_stageables_16_string; + reg [55:0] _zz_42__string; + reg [55:0] _zz_43__string; + reg [55:0] _zz_44__string; + reg [47:0] decode_DECODER_stageables_20_string; + reg [47:0] _zz_45__string; + reg [47:0] _zz_46__string; + reg [47:0] _zz_47__string; + reg [39:0] _zz_48__string; + reg [39:0] _zz_49__string; + reg [39:0] memory_DECODER_stageables_49_string; + reg [39:0] _zz_50__string; + reg [39:0] _zz_51__string; + reg [39:0] _zz_52__string; + reg [39:0] decode_DECODER_stageables_49_string; + reg [39:0] _zz_53__string; + reg [39:0] _zz_54__string; + reg [39:0] _zz_55__string; + reg [23:0] decode_DECODER_stageables_44_string; + reg [23:0] _zz_56__string; + reg [23:0] _zz_57__string; + reg [23:0] _zz_58__string; + reg [39:0] writeBack_DECODER_stageables_49_string; + reg [39:0] _zz_59__string; + reg [39:0] _zz_60__string; + reg [39:0] _zz_61__string; + reg [39:0] execute_DECODER_stageables_49_string; + reg [39:0] _zz_62__string; + reg [15:0] _zz_63__string; + reg [39:0] decode_DECODER_stageables_13_string; + reg [39:0] _zz_65__string; + reg [47:0] memory_CR_WRITE_op_string; + reg [47:0] _zz_66__string; + reg [39:0] execute_DECODER_stageables_13_string; + reg [39:0] _zz_67__string; + reg [31:0] execute_DECODER_stageables_1_string; + reg [31:0] _zz_70__string; + reg [63:0] execute_DECODER_stageables_26_string; + reg [63:0] _zz_71__string; + reg [47:0] execute_DECODER_stageables_38_string; + reg [47:0] _zz_74__string; + reg [47:0] _zz_76__string; + reg [47:0] execute_DECODER_stageables_20_string; + reg [47:0] _zz_77__string; + reg [47:0] execute_DECODER_stageables_51_string; + reg [47:0] _zz_78__string; + reg [15:0] execute_DECODER_stageables_12_string; + reg [15:0] _zz_80__string; + reg [39:0] execute_DECODER_stageables_8_string; + reg [39:0] _zz_81__string; + reg [55:0] execute_DECODER_stageables_0_string; + reg [55:0] _zz_82__string; + reg [55:0] execute_DECODER_stageables_16_string; + reg [55:0] _zz_98__string; + reg [23:0] execute_DECODER_stageables_44_string; + reg [23:0] _zz_99__string; + reg [47:0] execute_DECODER_stageables_19_string; + reg [47:0] _zz_100__string; + reg [47:0] writeBack_CR_WRITE_op_string; + reg [47:0] _zz_101__string; + reg [15:0] decode_DECODER_stageables_12_string; + reg [15:0] _zz_104__string; + reg [63:0] decode_DECODER_stageables_26_string; + reg [63:0] _zz_105__string; + reg [47:0] decode_DECODER_stageables_38_string; + reg [47:0] _zz_106__string; + reg [47:0] _zz_107__string; + reg [39:0] _zz_108__string; + reg [23:0] _zz_109__string; + reg [47:0] _zz_110__string; + reg [63:0] _zz_111__string; + reg [47:0] _zz_112__string; + reg [47:0] _zz_113__string; + reg [55:0] _zz_114__string; + reg [39:0] _zz_115__string; + reg [15:0] _zz_116__string; + reg [39:0] _zz_117__string; + reg [15:0] _zz_118__string; + reg [31:0] _zz_119__string; + reg [55:0] _zz_120__string; + reg [15:0] writeBack_DATA_SIZE_string; + reg [15:0] _zz_122__string; + reg [15:0] writeBack_MSR_ENDIAN_string; + reg [15:0] _zz_123__string; + reg [15:0] execute_DATA_SIZE_string; + reg [15:0] _zz_125__string; + reg [15:0] execute_MSR_ENDIAN_string; + reg [15:0] _zz_126__string; + reg [15:0] decode_MSR_ENDIAN_string; + reg [15:0] _zz_129__string; + reg [63:0] IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string; + reg [63:0] DBusCachedPlugin_exceptionBus_payload_codePPC_string; + reg [63:0] decodeExceptionPort_payload_codePPC_string; + reg [63:0] BranchPlugin_branchExceptionPort_payload_codePPC_string; + reg [63:0] SPRPlugin_selfException_payload_codePPC_string; + reg [55:0] _zz_223__string; + reg [31:0] _zz_224__string; + reg [15:0] _zz_225__string; + reg [39:0] _zz_226__string; + reg [15:0] _zz_227__string; + reg [39:0] _zz_228__string; + reg [55:0] _zz_229__string; + reg [47:0] _zz_230__string; + reg [47:0] _zz_231__string; + reg [63:0] _zz_232__string; + reg [47:0] _zz_233__string; + reg [23:0] _zz_234__string; + reg [39:0] _zz_235__string; + reg [47:0] _zz_236__string; + reg [47:0] writeBack_RegFilePlugin_crBusPort_payload_op_string; + reg [47:0] ALU2_crBus_op_string; + reg [47:0] _zz_273__string; + reg [47:0] MULDIV1_crBusPort_payload_op_string; + reg [47:0] execute_BranchPlugin_crBusPort_op_string; + reg [63:0] SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string; + reg [63:0] _zz_337__string; + reg [63:0] _zz_340__string; + reg [63:0] SPRPlugin_intType_string; + reg [63:0] execute_SPRPLUGIN_opExcp_codePPC_string; + reg [23:0] decode_to_execute_DECODER_stageables_44_string; + reg [39:0] decode_to_execute_DECODER_stageables_49_string; + reg [39:0] execute_to_memory_DECODER_stageables_49_string; + reg [39:0] memory_to_writeBack_DECODER_stageables_49_string; + reg [39:0] decode_to_execute_DECODER_stageables_13_string; + reg [47:0] decode_to_execute_DECODER_stageables_20_string; + reg [55:0] decode_to_execute_DECODER_stageables_16_string; + reg [55:0] decode_to_execute_DECODER_stageables_0_string; + reg [47:0] execute_to_memory_CR_WRITE_op_string; + reg [47:0] memory_to_writeBack_CR_WRITE_op_string; + reg [47:0] decode_to_execute_DECODER_stageables_19_string; + reg [15:0] decode_to_execute_MSR_ENDIAN_string; + reg [15:0] execute_to_memory_MSR_ENDIAN_string; + reg [15:0] memory_to_writeBack_MSR_ENDIAN_string; + reg [47:0] decode_to_execute_DECODER_stageables_51_string; + reg [15:0] decode_to_execute_DECODER_stageables_7_string; + reg [15:0] execute_to_memory_DECODER_stageables_7_string; + reg [15:0] memory_to_writeBack_DECODER_stageables_7_string; + reg [31:0] decode_to_execute_DECODER_stageables_1_string; + reg [39:0] decode_to_execute_DECODER_stageables_8_string; + reg [63:0] decode_to_execute_DECODER_stageables_26_string; + reg [47:0] decode_to_execute_DECODER_stageables_38_string; + reg [15:0] decode_to_execute_DECODER_stageables_12_string; + `endif + + reg [53:0] IBusCachedPlugin_predictor_history [0:1023]; + reg [31:0] RegFilePlugin_regFile [0:31] /* verilator public */ ; + function [6:0] zz_SPRPlugin_selfException_payload_imm(input dummy); + begin + zz_SPRPlugin_selfException_payload_imm = 7'h0; + zz_SPRPlugin_selfException_payload_imm = 7'h0; + end + endfunction + wire [6:0] _zz_1588_; + + assign _zz_394_ = (execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TW); + assign _zz_395_ = (writeBack_arbitration_isValid && writeBack_DECODER_stageables_45); + assign _zz_396_ = 1'b1; + assign _zz_397_ = (memory_arbitration_isValid && memory_DECODER_stageables_45); + assign _zz_398_ = (execute_arbitration_isValid && execute_DECODER_stageables_45); + assign _zz_399_ = (memory_arbitration_isValid && memory_DECODER_stageables_43); + assign _zz_400_ = (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_31); + assign _zz_401_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_cacheMiss) && (! _zz_127__3)); + assign _zz_402_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_error) && (! _zz_127__2)); + assign _zz_403_ = ((_zz_372_ && (! IBusCachedPlugin_cache_io_cpu_decode_mmuException)) && (! _zz_127__1)); + assign _zz_404_ = IBusCachedPlugin_cache_io_cpu_decode_exceptionType[0]; + assign _zz_405_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_mmuException) && (! _zz_127__0)); + assign _zz_406_ = ((_zz_372_ && IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling) && (! IBusCachedPlugin_rsp_issueDetected)); + assign _zz_407_ = ({decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid} != (2'b00)); + assign _zz_408_ = (SPRPlugin_hadException || SPRPlugin_interruptJump); + assign _zz_409_ = (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_39); + assign _zz_410_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_SC)); + assign _zz_411_ = (writeBack_arbitration_isFiring && ((writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TW) || (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TWI))); + assign _zz_412_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_SCV)); + assign _zz_413_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_RFI)); + assign _zz_414_ = (writeBack_arbitration_isFiring && (writeBack_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_RFSCV)); + assign _zz_415_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_416_ = ((! dataCache_1__io_cpu_writeBack_mmuException) && dataCache_1__io_cpu_writeBack_exceptionType[0]); + assign _zz_417_ = ((! dataCache_1__io_cpu_writeBack_exceptionType[3]) && (! writeBack_MEMORY_WR)); + assign _zz_418_ = ((! dataCache_1__io_cpu_writeBack_exceptionType[2]) && writeBack_MEMORY_WR); + assign _zz_419_ = (! decode_LEGAL_INSTRUCTION); + assign _zz_420_ = (decode && SPRPlugin_msr_pr); + assign _zz_421_ = (! UpdateRegFileWrite_valid); + assign _zz_422_ = (MULDIV_frontendOk && (! MULDIV1_done)); + assign _zz_423_ = (! memory_arbitration_isStuck); + assign _zz_424_ = (memory_DECODER_stageables_37 && memory_INSTRUCTION[10]); + assign _zz_425_ = (writeBack_arbitration_isValid && writeBack_DECODER_stageables_45); + assign _zz_426_ = (1'b0 || (! _zz_286_)); + assign _zz_427_ = (memory_arbitration_isValid && memory_DECODER_stageables_45); + assign _zz_428_ = (1'b0 || (! memory_DECODER_stageables_5)); + assign _zz_429_ = (execute_arbitration_isValid && execute_DECODER_stageables_45); + assign _zz_430_ = (1'b0 || (! execute_DECODER_stageables_25)); + assign _zz_431_ = (memory_arbitration_isValid && execute_arbitration_isValid); + assign _zz_432_ = (1'b0 ? (memory_CR_FIELD_WR != 8'h0) : ((memory_CR_FIELD_WR & execute_CR_FIELD_RD) != 8'h0)); + assign _zz_433_ = (1'b1 && (! 1'b0)); + assign _zz_434_ = (writeBack_arbitration_isValid && execute_arbitration_isValid); + assign _zz_435_ = (1'b0 ? (writeBack_CR_FIELD_WR != 8'h0) : ((writeBack_CR_FIELD_WR & execute_CR_FIELD_RD) != 8'h0)); + assign _zz_436_ = (1'b1 && (! 1'b0)); + assign _zz_437_ = (! SPRPlugin_hadException); + assign _zz_438_ = (iBus_cmd_valid || (_zz_358_ != (3'b000))); + assign _zz_439_ = 1'b1; + assign _zz_440_ = (((MSR_EE && SPRPlugin_intDec) && 1'b1) && (! 1'b0)); + assign _zz_441_ = execute_INSTRUCTION[19 : 12]; + assign _zz_442_ = execute_INSTRUCTION[20 : 18]; + assign _zz_443_ = execute_INSTRUCTION[20 : 18]; + assign _zz_444_ = (2'b00); + assign _zz_445_ = (2'b00); + assign _zz_446_ = execute_BranchPlugin_crBusPort_ba[2 : 0]; + assign _zz_447_ = _zz_157_[45 : 45]; + assign _zz_448_ = _zz_157_[39 : 39]; + assign _zz_449_ = _zz_157_[61 : 61]; + assign _zz_450_ = _zz_157_[43 : 43]; + assign _zz_451_ = _zz_157_[35 : 35]; + assign _zz_452_ = _zz_157_[53 : 53]; + assign _zz_453_ = _zz_157_[37 : 37]; + assign _zz_454_ = _zz_157_[64 : 64]; + assign _zz_455_ = _zz_157_[75 : 75]; + assign _zz_456_ = _zz_157_[51 : 51]; + assign _zz_457_ = _zz_157_[47 : 47]; + assign _zz_458_ = _zz_157_[58 : 58]; + assign _zz_459_ = _zz_157_[5 : 5]; + assign _zz_460_ = _zz_157_[6 : 6]; + assign _zz_461_ = _zz_157_[21 : 21]; + assign _zz_462_ = _zz_157_[38 : 38]; + assign _zz_463_ = _zz_157_[50 : 50]; + assign _zz_464_ = _zz_157_[27 : 27]; + assign _zz_465_ = _zz_157_[14 : 14]; + assign _zz_466_ = _zz_157_[63 : 63]; + assign _zz_467_ = _zz_157_[60 : 60]; + assign _zz_468_ = ($signed(_zz_469_) + $signed(_zz_474_)); + assign _zz_469_ = ($signed(_zz_470_) + $signed(_zz_472_)); + assign _zz_470_ = 52'h0; + assign _zz_471_ = {1'b0,memory_MUL_LL}; + assign _zz_472_ = {{19{_zz_471_[32]}}, _zz_471_}; + assign _zz_473_ = ({16'd0,memory_MUL_LH} <<< 16); + assign _zz_474_ = {{2{_zz_473_[49]}}, _zz_473_}; + assign _zz_475_ = ({16'd0,memory_MUL_HL} <<< 16); + assign _zz_476_ = {{2{_zz_475_[49]}}, _zz_475_}; + assign _zz_477_ = _zz_157_[8 : 8]; + assign _zz_478_ = _zz_157_[22 : 22]; + assign _zz_479_ = _zz_157_[57 : 57]; + assign _zz_480_ = _zz_157_[78 : 78]; + assign _zz_481_ = _zz_157_[16 : 16]; + assign _zz_482_ = _zz_157_[36 : 36]; + assign _zz_483_ = _zz_157_[48 : 48]; + assign _zz_484_ = _zz_157_[76 : 76]; + assign _zz_485_ = _zz_157_[79 : 79]; + assign _zz_486_ = _zz_157_[77 : 77]; + assign _zz_487_ = _zz_157_[66 : 66]; + assign _zz_488_ = _zz_157_[52 : 52]; + assign _zz_489_ = _zz_157_[44 : 44]; + assign _zz_490_ = _zz_157_[9 : 9]; + assign _zz_491_ = _zz_157_[71 : 71]; + assign _zz_492_ = _zz_157_[65 : 65]; + assign _zz_493_ = _zz_157_[15 : 15]; + assign _zz_494_ = _zz_157_[26 : 26]; + assign _zz_495_ = _zz_157_[46 : 46]; + assign _zz_496_ = _zz_157_[74 : 74]; + assign _zz_497_ = _zz_157_[7 : 7]; + assign _zz_498_ = (_zz_132_ - (3'b001)); + assign _zz_499_ = {IBusCachedPlugin_fetchPc_inc,(2'b00)}; + assign _zz_500_ = {29'd0, _zz_499_}; + assign _zz_501_ = _zz_145_[9:0]; + assign _zz_502_ = (IBusCachedPlugin_iBusRsp_stages_1_input_payload >>> 2); + assign _zz_503_ = _zz_502_[9:0]; + assign _zz_504_ = (IBusCachedPlugin_iBusRsp_stages_1_input_payload >>> 12); + assign _zz_505_ = (memory_PREDICTION_CONTEXT_line_branchWish + _zz_507_); + assign _zz_506_ = (memory_PREDICTION_CONTEXT_line_branchWish == (2'b10)); + assign _zz_507_ = {1'd0, _zz_506_}; + assign _zz_508_ = (memory_PREDICTION_CONTEXT_line_branchWish == (2'b01)); + assign _zz_509_ = {1'd0, _zz_508_}; + assign _zz_510_ = (memory_PREDICTION_CONTEXT_line_branchWish - _zz_512_); + assign _zz_511_ = memory_PREDICTION_CONTEXT_line_branchWish[1]; + assign _zz_512_ = {1'd0, _zz_511_}; + assign _zz_513_ = (! memory_PREDICTION_CONTEXT_line_branchWish[1]); + assign _zz_514_ = {1'd0, _zz_513_}; + assign _zz_515_ = (writeBack_MEMORY_WR ? (3'b111) : (3'b101)); + assign _zz_516_ = (writeBack_MEMORY_WR ? (3'b110) : (3'b100)); + assign _zz_517_ = writeBack_SPR_ID; + assign _zz_518_ = (writeBack_PC + 32'h00000004); + assign _zz_519_ = writeBack_SPR_ID; + assign _zz_520_ = (execute_SRC1 <<< ALU2_amount); + assign _zz_521_ = (execute_SRC1 >>> ALU2_amount); + assign _zz_522_ = _zz_523_; + assign _zz_523_ = ($signed(_zz_524_) >>> ALU2_amount); + assign _zz_524_ = execute_SRC1; + assign _zz_525_ = 32'hffffffff; + assign _zz_526_ = _zz_525_; + assign _zz_527_ = (6'h20 - _zz_528_); + assign _zz_528_ = {1'd0, ALU2_amount}; + assign _zz_529_ = sprReadBU_payload_data; + assign _zz_530_ = sprReadBU_payload_data; + assign _zz_531_ = sprReadBU_payload_data; + assign _zz_532_ = sprReadBU_payload_data; + assign _zz_533_ = sprReadBU_payload_data; + assign _zz_534_ = sprReadBU_payload_data; + assign _zz_535_ = sprReadBU_payload_data; + assign _zz_536_ = sprReadBU_payload_data; + assign _zz_537_ = sprReadBU_payload_data; + assign _zz_538_ = sprReadBU_payload_data; + assign _zz_539_ = sprReadBU_payload_data; + assign _zz_540_ = sprReadBU_payload_data; + assign _zz_541_ = sprReadBU_payload_data; + assign _zz_542_ = sprReadBU_payload_data; + assign _zz_543_ = sprReadBU_payload_data; + assign _zz_544_ = sprReadBU_payload_data; + assign _zz_545_ = sprReadBU_payload_data; + assign _zz_546_ = sprReadBU_payload_data; + assign _zz_547_ = sprReadBU_payload_data; + assign _zz_548_ = sprReadBU_payload_data; + assign _zz_549_ = sprReadBU_payload_data; + assign _zz_550_ = sprReadBU_payload_data; + assign _zz_551_ = sprReadBU_payload_data; + assign _zz_552_ = sprReadBU_payload_data; + assign _zz_553_ = sprReadBU_payload_data; + assign _zz_554_ = (5'h1f - execute_INSTRUCTION[10 : 6]); + assign _zz_555_ = ((3'b111) - execute_INSTRUCTION[25 : 23]); + assign _zz_556_ = 32'h0; + assign _zz_557_ = 32'h0; + assign _zz_558_ = 32'hffffffff; + assign _zz_559_ = ({(1'b0),SRC2_ra} + {(1'b0),SRC2_rb}); + assign _zz_560_ = {32'd0, SRC2_cin}; + assign _zz_561_ = SRC2_ra; + assign _zz_562_ = SRC2_rb; + assign _zz_563_ = {{14{writeBack_MUL_LOW[51]}}, writeBack_MUL_LOW}; + assign _zz_564_ = ({32'd0,writeBack_MUL_HH} <<< 32); + assign _zz_565_ = MUL3_result[63 : 32]; + assign _zz_566_ = writeBack_MUL_LOW[31 : 0]; + assign _zz_567_ = MULDIV1_counter_willIncrement; + assign _zz_568_ = {5'd0, _zz_567_}; + assign _zz_569_ = {1'd0, MULDIV_rs2}; + assign _zz_570_ = MULDIV1_stage_0_remainderMinusDenominator[31:0]; + assign _zz_571_ = MULDIV1_stage_0_remainderShifted[31:0]; + assign _zz_572_ = {_zz_275_,(! MULDIV1_stage_0_remainderMinusDenominator[32])}; + assign _zz_573_ = _zz_574_; + assign _zz_574_ = _zz_575_; + assign _zz_575_ = ({1'b0,(MULDIV1_needRevert ? (~ _zz_276_) : _zz_276_)} + _zz_577_); + assign _zz_576_ = MULDIV1_needRevert; + assign _zz_577_ = {32'd0, _zz_576_}; + assign _zz_578_ = _zz_281_; + assign _zz_579_ = {32'd0, _zz_578_}; + assign _zz_580_ = _zz_280_; + assign _zz_581_ = {31'd0, _zz_580_}; + assign _zz_582_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_583_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_584_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_585_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_586_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_587_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_588_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_589_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_590_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_591_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_592_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_593_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_594_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_595_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_596_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_597_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_598_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_599_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_600_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_601_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_602_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_603_ = (5'h1f - execute_BranchPlugin_crBusPort_bt); + assign _zz_604_ = (5'h1f - execute_BranchPlugin_crBusPort_ba); + assign _zz_605_ = (5'h1f - execute_BranchPlugin_crBusPort_bb); + assign _zz_606_ = execute_BranchPlugin_li; + assign _zz_607_ = execute_BranchPlugin_bd; + assign _zz_608_ = ($signed(execute_BranchPlugin_branch_tgt1) + $signed(execute_BranchPlugin_branch_tgt2)); + assign _zz_609_ = ($signed(execute_BranchPlugin_branch_tgt1) + $signed(execute_BranchPlugin_branch_tgt2)); + assign _zz_610_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_611_ = (_zz_613_ + 5'h1c); + assign _zz_612_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_613_ = {3'd0, _zz_612_}; + assign _zz_614_ = (_zz_616_ + 5'h18); + assign _zz_615_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_616_ = {3'd0, _zz_615_}; + assign _zz_617_ = (_zz_619_ + 5'h14); + assign _zz_618_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_619_ = {3'd0, _zz_618_}; + assign _zz_620_ = (_zz_622_ + 5'h10); + assign _zz_621_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_622_ = {3'd0, _zz_621_}; + assign _zz_623_ = (_zz_625_ + (4'b1100)); + assign _zz_624_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_625_ = {2'd0, _zz_624_}; + assign _zz_626_ = (_zz_628_ + (4'b1000)); + assign _zz_627_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_628_ = {2'd0, _zz_627_}; + assign _zz_629_ = (_zz_631_ + (3'b100)); + assign _zz_630_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_631_ = {1'd0, _zz_630_}; + assign _zz_632_ = (_zz_633_ + (2'b00)); + assign _zz_633_ = ((2'b11) - execute_BranchPlugin_crbiBit); + assign _zz_634_ = (_zz_338_ & (~ _zz_635_)); + assign _zz_635_ = (_zz_338_ - (2'b01)); + assign _zz_636_ = execute_SRC1; + assign _zz_637_ = execute_SRC2; + assign _zz_638_ = execute_SRC2; + assign _zz_639_ = execute_SRC1; + assign _zz_640_ = execute_SRC1; + assign _zz_641_ = execute_SPRPLUGIN_si; + assign _zz_642_ = execute_SPRPLUGIN_si; + assign _zz_643_ = execute_SRC1; + assign _zz_644_ = execute_SRC1[23 : 23]; + assign _zz_645_ = execute_SRC1[8 : 8]; + assign _zz_646_ = execute_SRC1[11 : 11]; + assign _zz_647_ = execute_SRC1[2 : 2]; + assign _zz_648_ = execute_SRC1[5 : 5]; + assign _zz_649_ = execute_SRC1[14 : 14]; + assign _zz_650_ = execute_SRC1[13 : 13]; + assign _zz_651_ = execute_SRC1[4 : 4]; + assign _zz_652_ = execute_SRC1[25 : 25]; + assign _zz_653_ = execute_SRC1[1 : 1]; + assign _zz_654_ = execute_SRC1[12 : 12]; + assign _zz_655_ = execute_SRC1[15 : 15]; + assign _zz_656_ = execute_SRC1[0 : 0]; + assign _zz_657_ = (iBus_cmd_payload_address >>> 5); + assign _zz_658_ = {IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target,{IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish,IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source}}; + assign _zz_659_ = 1'b1; + assign _zz_660_ = 1'b1; + assign _zz_661_ = 1'b1; + assign _zz_662_ = {_zz_135_,_zz_134_}; + assign _zz_663_ = ((decode_INSTRUCTION & 32'hb4000000) == 32'h20000000); + assign _zz_664_ = {((decode_INSTRUCTION & 32'hd4000000) == 32'h40000000),{_zz_216_,{_zz_183_,{((decode_INSTRUCTION & 32'hcc100000) == 32'h80100000),{_zz_178_,{_zz_177_,{_zz_189_,{_zz_665_,_zz_666_}}}}}}}}; + assign _zz_665_ = ((decode_INSTRUCTION & 32'hd4100000) == 32'h80100000); + assign _zz_666_ = {_zz_188_,{_zz_185_,{_zz_181_,{_zz_180_,{_zz_179_,{((decode_INSTRUCTION & _zz_667_) == 32'h98020000),{_zz_173_,{_zz_668_,{_zz_669_,_zz_670_}}}}}}}}}; + assign _zz_667_ = 32'hbc020000; + assign _zz_668_ = ((decode_INSTRUCTION & 32'hf8100000) == 32'h38100000); + assign _zz_669_ = _zz_172_; + assign _zz_670_ = {((decode_INSTRUCTION & 32'hbc080000) == 32'h98080000),{((decode_INSTRUCTION & 32'hbc100000) == 32'h98100000),{_zz_175_,{_zz_174_,{(_zz_671_ == _zz_672_),{_zz_673_,{_zz_674_,_zz_675_}}}}}}}; + assign _zz_671_ = (decode_INSTRUCTION & 32'hbc040000); + assign _zz_672_ = 32'h98040000; + assign _zz_673_ = ((decode_INSTRUCTION & 32'hfc200000) == 32'hd8200000); + assign _zz_674_ = _zz_222_; + assign _zz_675_ = {((decode_INSTRUCTION & 32'hfc000003) == 32'h44000001),{((decode_INSTRUCTION & 32'hd41f0000) == 32'h80000000),{((decode_INSTRUCTION & _zz_676_) == 32'h80000000),{(_zz_677_ == _zz_678_),{_zz_679_,{_zz_680_,_zz_681_}}}}}}; + assign _zz_676_ = 32'he41f0000; + assign _zz_677_ = (decode_INSTRUCTION & 32'hcc1f0000); + assign _zz_678_ = 32'h80000000; + assign _zz_679_ = ((decode_INSTRUCTION & 32'hf81f0000) == 32'h38000000); + assign _zz_680_ = ((decode_INSTRUCTION & 32'hfc3e0000) == 32'hd8000000); + assign _zz_681_ = {((decode_INSTRUCTION & 32'hfc00003e) == 32'h4c000004),{((decode_INSTRUCTION & 32'hfc02003e) == 32'h7c02001e),{((decode_INSTRUCTION & _zz_682_) == 32'h7c10001e),{(_zz_683_ == _zz_684_),{_zz_685_,{_zz_686_,_zz_687_}}}}}}; + assign _zz_682_ = 32'hfc10003e; + assign _zz_683_ = (decode_INSTRUCTION & 32'hfc08003e); + assign _zz_684_ = 32'h7c08001e; + assign _zz_685_ = ((decode_INSTRUCTION & 32'hfc04003e) == 32'h7c04001e); + assign _zz_686_ = ((decode_INSTRUCTION & 32'hfc01003e) == 32'h7c01001e); + assign _zz_687_ = {((decode_INSTRUCTION & 32'hfc00033e) == 32'h7c000316),{((decode_INSTRUCTION & 32'hfc0003ba) == 32'h7c000190),{((decode_INSTRUCTION & _zz_688_) == 32'h7c000110),{(_zz_689_ == _zz_690_),{_zz_691_,{_zz_692_,_zz_693_}}}}}}; + assign _zz_688_ = 32'hfc00037a; + assign _zz_689_ = (decode_INSTRUCTION & 32'hfc0003da); + assign _zz_690_ = 32'h7c000010; + assign _zz_691_ = ((decode_INSTRUCTION & 32'hfc00067e) == 32'h7c00006e); + assign _zz_692_ = ((decode_INSTRUCTION & 32'hfc00057e) == 32'h7c00006e); + assign _zz_693_ = {((decode_INSTRUCTION & 32'hfc0004fe) == 32'h7c00006e),{((decode_INSTRUCTION & 32'hfc00073e) == 32'h7c000338),{((decode_INSTRUCTION & _zz_694_) == 32'h7c000038),{(_zz_695_ == _zz_696_),{_zz_697_,{_zz_698_,_zz_699_}}}}}}; + assign _zz_694_ = 32'hfc0005be; + assign _zz_695_ = (decode_INSTRUCTION & 32'hfc0003fc); + assign _zz_696_ = 32'h7c000214; + assign _zz_697_ = ((decode_INSTRUCTION & 32'hfc00037e) == 32'h7c000050); + assign _zz_698_ = ((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000734); + assign _zz_699_ = {((decode_INSTRUCTION & 32'hfc04067e) == 32'h7c04002e),{((decode_INSTRUCTION & 32'hfc02067e) == 32'h7c02002e),{((decode_INSTRUCTION & _zz_700_) == 32'h7c0000f4),{(_zz_701_ == _zz_702_),{_zz_703_,{_zz_704_,_zz_705_}}}}}}; + assign _zz_700_ = 32'hfc0005fe; + assign _zz_701_ = (decode_INSTRUCTION & 32'hfc0804fe); + assign _zz_702_ = 32'h7c08002e; + assign _zz_703_ = ((decode_INSTRUCTION & 32'hfc02057e) == 32'h7c02002e); + assign _zz_704_ = ((decode_INSTRUCTION & 32'hfc04057e) == 32'h7c04002e); + assign _zz_705_ = {((decode_INSTRUCTION & 32'hfc08057e) == 32'h7c08002e),{((decode_INSTRUCTION & 32'hfc01057e) == 32'h7c01002e),{((decode_INSTRUCTION & _zz_706_) == 32'h7c10002e),{(_zz_707_ == _zz_708_),{_zz_709_,{_zz_710_,_zz_711_}}}}}}; + assign _zz_706_ = 32'hfc10067e; + assign _zz_707_ = (decode_INSTRUCTION & 32'hfc0204fe); + assign _zz_708_ = 32'h7c02002e; + assign _zz_709_ = ((decode_INSTRUCTION & 32'hfc01067e) == 32'h7c01002e); + assign _zz_710_ = ((decode_INSTRUCTION & 32'hfc0404fe) == 32'h7c04002e); + assign _zz_711_ = {((decode_INSTRUCTION & 32'hfc0006fe) == 32'h7c0002a6),{((decode_INSTRUCTION & 32'hfc1004fe) == 32'h7c10002e),{((decode_INSTRUCTION & _zz_712_) == 32'h7c01002e),{(_zz_713_ == _zz_714_),{_zz_715_,{_zz_716_,_zz_717_}}}}}}; + assign _zz_712_ = 32'hfc0104fe; + assign _zz_713_ = (decode_INSTRUCTION & 32'hfc10057e); + assign _zz_714_ = 32'h7c10002e; + assign _zz_715_ = ((decode_INSTRUCTION & 32'hfc08067e) == 32'h7c08002e); + assign _zz_716_ = ((decode_INSTRUCTION & 32'hfc00077e) == 32'h7c000078); + assign _zz_717_ = {((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000630),{((decode_INSTRUCTION & 32'hfc00077e) == 32'h7c000026),{((decode_INSTRUCTION & _zz_718_) == 32'h7c000124),{(_zz_719_ == _zz_720_),{_zz_721_,{_zz_722_,_zz_723_}}}}}}; + assign _zz_718_ = 32'hfc0007ee; + assign _zz_719_ = (decode_INSTRUCTION & 32'hfc00077e); + assign _zz_720_ = 32'h7c000016; + assign _zz_721_ = ((decode_INSTRUCTION & 32'hfc0007de) == 32'h7c000100); + assign _zz_722_ = _zz_195_; + assign _zz_723_ = {((decode_INSTRUCTION & 32'hfc0006fe) == 32'h4c000242),{((decode_INSTRUCTION & 32'hfc0007be) == 32'h4c000182),{((decode_INSTRUCTION & _zz_724_) == 32'h4c000182),{(_zz_725_ == _zz_726_),{_zz_727_,{_zz_728_,_zz_729_}}}}}}; + assign _zz_724_ = 32'hfc0005fe; + assign _zz_725_ = (decode_INSTRUCTION & 32'hfc0007be); + assign _zz_726_ = 32'h4c000202; + assign _zz_727_ = ((decode_INSTRUCTION & 32'hfc0007f6) == 32'h7c000000); + assign _zz_728_ = ((decode_INSTRUCTION & 32'hfc0007be) == 32'h4c000420); + assign _zz_729_ = {((decode_INSTRUCTION & 32'hfc00077e) == 32'h4c000102),{((decode_INSTRUCTION & 32'hfc0007be) == 32'h7c000000),{((decode_INSTRUCTION & _zz_730_) == 32'h4c000042),{(_zz_731_ == _zz_732_),{_zz_733_,{_zz_734_,_zz_735_}}}}}}; + assign _zz_730_ = 32'hfc0005fe; + assign _zz_731_ = (decode_INSTRUCTION & 32'hfc0007de); + assign _zz_732_ = 32'h4c000000; + assign _zz_733_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c0007ac); + assign _zz_734_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c0001d6); + assign _zz_735_ = {((decode_INSTRUCTION & 32'hfc1f003e) == 32'h7c00001e),{((decode_INSTRUCTION & 32'hfc0007fe) == 32'h7c000480),{((decode_INSTRUCTION & _zz_736_) == 32'h4c00012c),{(_zz_737_ == _zz_738_),{_zz_739_,{_zz_740_,_zz_741_}}}}}}; + assign _zz_736_ = 32'hfc0007fe; + assign _zz_737_ = (decode_INSTRUCTION & 32'hfc0007fe); + assign _zz_738_ = 32'h4c000064; + assign _zz_739_ = ((decode_INSTRUCTION & 32'hfc0007fe) == 32'h4c0000a4); + assign _zz_740_ = ((decode_INSTRUCTION & 32'hfc6007fe) == 32'h4c0004ac); + assign _zz_741_ = {((decode_INSTRUCTION & 32'hfc1f04fe) == 32'h7c00002e),{((decode_INSTRUCTION & 32'hfc1f057e) == 32'h7c00002e),((decode_INSTRUCTION & 32'hfc1f067e) == 32'h7c00002e)}}; + assign _zz_742_ = (decode_INSTRUCTION & 32'hf8000000); + assign _zz_743_ = 32'h70000000; + assign _zz_744_ = ((decode_INSTRUCTION & 32'hbc000000) == 32'h34000000); + assign _zz_745_ = _zz_187_; + assign _zz_746_ = ((decode_INSTRUCTION & _zz_754_) == 32'h70000000); + assign _zz_747_ = ((decode_INSTRUCTION & 32'h80000100) == 32'h00000100); + assign _zz_748_ = ((decode_INSTRUCTION & 32'h7800032a) == 32'h78000002); + assign _zz_749_ = {_zz_167_,{_zz_161_,{_zz_755_,_zz_756_}}}; + assign _zz_750_ = (4'b0000); + assign _zz_751_ = ({_zz_757_,{_zz_758_,_zz_759_}} != 8'h0); + assign _zz_752_ = ({_zz_760_,_zz_761_} != 20'h0); + assign _zz_753_ = {(_zz_762_ != _zz_763_),{_zz_764_,{_zz_765_,_zz_766_}}}; + assign _zz_754_ = 32'h70000538; + assign _zz_755_ = (_zz_767_ == _zz_768_); + assign _zz_756_ = _zz_166_; + assign _zz_757_ = ((decode_INSTRUCTION & _zz_769_) == 32'ha8100000); + assign _zz_758_ = (_zz_770_ == _zz_771_); + assign _zz_759_ = {_zz_772_,{_zz_773_,_zz_774_}}; + assign _zz_760_ = (_zz_775_ == _zz_776_); + assign _zz_761_ = {_zz_221_,{_zz_777_,_zz_778_}}; + assign _zz_762_ = (_zz_779_ == _zz_780_); + assign _zz_763_ = (1'b0); + assign _zz_764_ = (_zz_781_ != (1'b0)); + assign _zz_765_ = (_zz_782_ != _zz_783_); + assign _zz_766_ = {_zz_784_,{_zz_785_,_zz_786_}}; + assign _zz_767_ = (decode_INSTRUCTION & 32'h78000318); + assign _zz_768_ = 32'h78000200; + assign _zz_769_ = 32'ha8100000; + assign _zz_770_ = (decode_INSTRUCTION & 32'hfc000000); + assign _zz_771_ = 32'hac000000; + assign _zz_772_ = ((decode_INSTRUCTION & _zz_787_) == 32'ha8040000); + assign _zz_773_ = (_zz_788_ == _zz_789_); + assign _zz_774_ = {_zz_790_,{_zz_791_,_zz_792_}}; + assign _zz_775_ = (decode_INSTRUCTION & 32'hc0100000); + assign _zz_776_ = 32'h80100000; + assign _zz_777_ = _zz_170_; + assign _zz_778_ = {_zz_218_,{_zz_793_,_zz_794_}}; + assign _zz_779_ = (decode_INSTRUCTION & 32'h20000400); + assign _zz_780_ = 32'h20000000; + assign _zz_781_ = ((decode_INSTRUCTION & _zz_795_) == 32'h20000000); + assign _zz_782_ = {_zz_796_,{_zz_797_,_zz_798_}}; + assign _zz_783_ = 20'h0; + assign _zz_784_ = (_zz_213_ != (1'b0)); + assign _zz_785_ = (_zz_799_ != _zz_800_); + assign _zz_786_ = {_zz_801_,{_zz_802_,_zz_803_}}; + assign _zz_787_ = 32'hfc040000; + assign _zz_788_ = (decode_INSTRUCTION & 32'hfc080000); + assign _zz_789_ = 32'ha8080000; + assign _zz_790_ = ((decode_INSTRUCTION & _zz_804_) == 32'ha8020000); + assign _zz_791_ = (_zz_805_ == _zz_806_); + assign _zz_792_ = {_zz_807_,_zz_808_}; + assign _zz_793_ = _zz_189_; + assign _zz_794_ = {_zz_188_,{_zz_809_,_zz_810_}}; + assign _zz_795_ = 32'h20000100; + assign _zz_796_ = ((decode_INSTRUCTION & _zz_811_) == 32'h60000030); + assign _zz_797_ = (_zz_812_ == _zz_813_); + assign _zz_798_ = {_zz_814_,{_zz_815_,_zz_816_}}; + assign _zz_799_ = {_zz_817_,{_zz_818_,_zz_819_}}; + assign _zz_800_ = (4'b0000); + assign _zz_801_ = ({_zz_820_,_zz_821_} != (4'b0000)); + assign _zz_802_ = (_zz_822_ != _zz_823_); + assign _zz_803_ = {_zz_824_,{_zz_825_,_zz_826_}}; + assign _zz_804_ = 32'hfc020000; + assign _zz_805_ = (decode_INSTRUCTION & 32'hfc010000); + assign _zz_806_ = 32'ha8010000; + assign _zz_807_ = ((decode_INSTRUCTION & _zz_827_) == 32'h780002a8); + assign _zz_808_ = ((decode_INSTRUCTION & _zz_828_) == 32'ha8000000); + assign _zz_809_ = _zz_186_; + assign _zz_810_ = {_zz_185_,{_zz_829_,_zz_830_}}; + assign _zz_811_ = 32'h60000030; + assign _zz_812_ = (decode_INSTRUCTION & 32'h60000024); + assign _zz_813_ = 32'h60000020; + assign _zz_814_ = ((decode_INSTRUCTION & _zz_831_) == 32'h90100000); + assign _zz_815_ = _zz_220_; + assign _zz_816_ = {_zz_219_,{_zz_832_,_zz_833_}}; + assign _zz_817_ = ((decode_INSTRUCTION & _zz_834_) == 32'h04000000); + assign _zz_818_ = _zz_204_; + assign _zz_819_ = {_zz_835_,_zz_836_}; + assign _zz_820_ = _zz_204_; + assign _zz_821_ = {_zz_222_,{_zz_837_,_zz_838_}}; + assign _zz_822_ = {_zz_204_,{_zz_839_,_zz_840_}}; + assign _zz_823_ = (4'b0000); + assign _zz_824_ = ({_zz_841_,_zz_842_} != (2'b00)); + assign _zz_825_ = (_zz_843_ != _zz_844_); + assign _zz_826_ = {_zz_845_,{_zz_846_,_zz_847_}}; + assign _zz_827_ = 32'h780003a8; + assign _zz_828_ = 32'hfc0f0000; + assign _zz_829_ = _zz_184_; + assign _zz_830_ = {_zz_183_,{_zz_848_,_zz_849_}}; + assign _zz_831_ = 32'hd0100000; + assign _zz_832_ = _zz_215_; + assign _zz_833_ = {_zz_214_,{_zz_850_,_zz_851_}}; + assign _zz_834_ = 32'hbc000002; + assign _zz_835_ = ((decode_INSTRUCTION & _zz_852_) == 32'h440000a0); + assign _zz_836_ = ((decode_INSTRUCTION & _zz_853_) == 32'h44000060); + assign _zz_837_ = _zz_171_; + assign _zz_838_ = _zz_199_; + assign _zz_839_ = _zz_222_; + assign _zz_840_ = {_zz_200_,_zz_193_}; + assign _zz_841_ = (_zz_854_ == _zz_855_); + assign _zz_842_ = (_zz_856_ == _zz_857_); + assign _zz_843_ = {_zz_858_,{_zz_859_,_zz_860_}}; + assign _zz_844_ = 9'h0; + assign _zz_845_ = ({_zz_861_,_zz_862_} != (3'b000)); + assign _zz_846_ = (_zz_863_ != _zz_864_); + assign _zz_847_ = {_zz_865_,{_zz_866_,_zz_867_}}; + assign _zz_848_ = _zz_182_; + assign _zz_849_ = {_zz_181_,{_zz_868_,_zz_869_}}; + assign _zz_850_ = _zz_198_; + assign _zz_851_ = {_zz_870_,{_zz_871_,_zz_872_}}; + assign _zz_852_ = 32'h740004a2; + assign _zz_853_ = 32'h74000462; + assign _zz_854_ = (decode_INSTRUCTION & 32'hfc000000); + assign _zz_855_ = 32'h28000000; + assign _zz_856_ = (decode_INSTRUCTION & 32'h78000070); + assign _zz_857_ = 32'h78000040; + assign _zz_858_ = ((decode_INSTRUCTION & _zz_873_) == 32'h58000010); + assign _zz_859_ = (_zz_874_ == _zz_875_); + assign _zz_860_ = {_zz_876_,{_zz_877_,_zz_878_}}; + assign _zz_861_ = (_zz_879_ == _zz_880_); + assign _zz_862_ = {_zz_881_,_zz_882_}; + assign _zz_863_ = {_zz_883_,{_zz_884_,_zz_885_}}; + assign _zz_864_ = 25'h0; + assign _zz_865_ = ({_zz_886_,_zz_887_} != (2'b00)); + assign _zz_866_ = (_zz_888_ != _zz_889_); + assign _zz_867_ = {_zz_890_,{_zz_891_,_zz_892_}}; + assign _zz_868_ = _zz_180_; + assign _zz_869_ = {_zz_893_,_zz_894_}; + assign _zz_870_ = (_zz_895_ == _zz_896_); + assign _zz_871_ = _zz_897_; + assign _zz_872_ = {_zz_898_,_zz_899_}; + assign _zz_873_ = 32'hd8000030; + assign _zz_874_ = (decode_INSTRUCTION & _zz_900_); + assign _zz_875_ = 32'h5c000000; + assign _zz_876_ = (_zz_901_ == _zz_902_); + assign _zz_877_ = _zz_903_; + assign _zz_878_ = {_zz_904_,_zz_905_}; + assign _zz_879_ = (decode_INSTRUCTION & _zz_906_); + assign _zz_880_ = 32'h78000020; + assign _zz_881_ = (_zz_907_ == _zz_908_); + assign _zz_882_ = (_zz_909_ == _zz_910_); + assign _zz_883_ = (_zz_911_ == _zz_912_); + assign _zz_884_ = _zz_206_; + assign _zz_885_ = {_zz_913_,_zz_914_}; + assign _zz_886_ = _zz_915_; + assign _zz_887_ = _zz_916_; + assign _zz_888_ = {_zz_917_,_zz_918_}; + assign _zz_889_ = (2'b00); + assign _zz_890_ = (_zz_919_ != _zz_920_); + assign _zz_891_ = _zz_921_; + assign _zz_892_ = {_zz_922_,_zz_923_}; + assign _zz_893_ = _zz_179_; + assign _zz_894_ = {_zz_924_,_zz_925_}; + assign _zz_895_ = (decode_INSTRUCTION & _zz_926_); + assign _zz_896_ = 32'h60000128; + assign _zz_897_ = (_zz_927_ == _zz_928_); + assign _zz_898_ = _zz_929_; + assign _zz_899_ = {_zz_930_,_zz_931_}; + assign _zz_900_ = 32'hfc000000; + assign _zz_901_ = (decode_INSTRUCTION & _zz_932_); + assign _zz_902_ = 32'h50000000; + assign _zz_903_ = (_zz_933_ == _zz_934_); + assign _zz_904_ = _zz_935_; + assign _zz_905_ = {_zz_936_,_zz_937_}; + assign _zz_906_ = 32'h78000034; + assign _zz_907_ = (decode_INSTRUCTION & _zz_938_); + assign _zz_908_ = 32'h78000400; + assign _zz_909_ = (decode_INSTRUCTION & _zz_939_); + assign _zz_910_ = 32'h4c000000; + assign _zz_911_ = (decode_INSTRUCTION & _zz_940_); + assign _zz_912_ = 32'h60000010; + assign _zz_913_ = _zz_941_; + assign _zz_914_ = {_zz_942_,_zz_943_}; + assign _zz_915_ = (_zz_944_ == _zz_945_); + assign _zz_916_ = (_zz_946_ == _zz_947_); + assign _zz_917_ = _zz_948_; + assign _zz_918_ = _zz_208_; + assign _zz_919_ = {_zz_949_,_zz_950_}; + assign _zz_920_ = (3'b000); + assign _zz_921_ = (_zz_951_ != _zz_952_); + assign _zz_922_ = _zz_953_; + assign _zz_923_ = {_zz_954_,_zz_955_}; + assign _zz_924_ = _zz_178_; + assign _zz_925_ = {_zz_956_,_zz_957_}; + assign _zz_926_ = 32'h60000528; + assign _zz_927_ = (decode_INSTRUCTION & _zz_958_); + assign _zz_928_ = 32'h60000300; + assign _zz_929_ = (_zz_959_ == _zz_960_); + assign _zz_930_ = _zz_961_; + assign _zz_931_ = {_zz_962_,_zz_963_}; + assign _zz_932_ = 32'hfc000000; + assign _zz_933_ = (decode_INSTRUCTION & _zz_964_); + assign _zz_934_ = 32'h58000500; + assign _zz_935_ = (_zz_965_ == _zz_966_); + assign _zz_936_ = _zz_967_; + assign _zz_937_ = {_zz_968_,_zz_969_}; + assign _zz_938_ = 32'h78000418; + assign _zz_939_ = 32'h7c000364; + assign _zz_940_ = 32'h60000010; + assign _zz_941_ = (_zz_970_ == _zz_971_); + assign _zz_942_ = _zz_972_; + assign _zz_943_ = {_zz_973_,_zz_974_}; + assign _zz_944_ = (decode_INSTRUCTION & _zz_975_); + assign _zz_945_ = 32'h20000000; + assign _zz_946_ = (decode_INSTRUCTION & _zz_976_); + assign _zz_947_ = 32'h08000000; + assign _zz_948_ = (_zz_977_ == _zz_978_); + assign _zz_949_ = _zz_215_; + assign _zz_950_ = {_zz_979_,_zz_980_}; + assign _zz_951_ = _zz_981_; + assign _zz_952_ = (1'b0); + assign _zz_953_ = (_zz_982_ != _zz_983_); + assign _zz_954_ = _zz_984_; + assign _zz_955_ = {_zz_985_,_zz_986_}; + assign _zz_956_ = _zz_177_; + assign _zz_957_ = {_zz_987_,{_zz_988_,_zz_989_}}; + assign _zz_958_ = 32'h60000318; + assign _zz_959_ = (decode_INSTRUCTION & 32'hf4020000); + assign _zz_960_ = 32'h90020000; + assign _zz_961_ = ((decode_INSTRUCTION & _zz_990_) == 32'h90040000); + assign _zz_962_ = (_zz_991_ == _zz_992_); + assign _zz_963_ = {_zz_993_,{_zz_994_,_zz_995_}}; + assign _zz_964_ = 32'hd8000508; + assign _zz_965_ = (decode_INSTRUCTION & 32'hd8000604); + assign _zz_966_ = 32'h58000200; + assign _zz_967_ = ((decode_INSTRUCTION & _zz_996_) == 32'h58000000); + assign _zz_968_ = (_zz_997_ == _zz_998_); + assign _zz_969_ = {_zz_999_,_zz_1000_}; + assign _zz_970_ = (decode_INSTRUCTION & 32'h60000060); + assign _zz_971_ = 32'h60000060; + assign _zz_972_ = ((decode_INSTRUCTION & _zz_1001_) == 32'h60000020); + assign _zz_973_ = _zz_221_; + assign _zz_974_ = {_zz_1002_,{_zz_1003_,_zz_1004_}}; + assign _zz_975_ = 32'h20000040; + assign _zz_976_ = 32'h28000000; + assign _zz_977_ = (decode_INSTRUCTION & 32'h7800028a); + assign _zz_978_ = 32'h78000202; + assign _zz_979_ = _zz_214_; + assign _zz_980_ = (_zz_1005_ == _zz_1006_); + assign _zz_981_ = ((decode_INSTRUCTION & _zz_1007_) == 32'h78000300); + assign _zz_982_ = {_zz_213_,{_zz_1008_,_zz_1009_}}; + assign _zz_983_ = 5'h0; + assign _zz_984_ = ({_zz_1010_,_zz_1011_} != (2'b00)); + assign _zz_985_ = (_zz_1012_ != _zz_1013_); + assign _zz_986_ = {_zz_1014_,{_zz_1015_,_zz_1016_}}; + assign _zz_987_ = (_zz_1017_ == _zz_1018_); + assign _zz_988_ = _zz_1019_; + assign _zz_989_ = {_zz_1020_,_zz_1021_}; + assign _zz_990_ = 32'hdc040000; + assign _zz_991_ = (decode_INSTRUCTION & _zz_1022_); + assign _zz_992_ = 32'h90080000; + assign _zz_993_ = (_zz_1023_ == _zz_1024_); + assign _zz_994_ = _zz_1025_; + assign _zz_995_ = {_zz_1026_,_zz_1027_}; + assign _zz_996_ = 32'hd8000504; + assign _zz_997_ = (decode_INSTRUCTION & _zz_1028_); + assign _zz_998_ = 32'h58000028; + assign _zz_999_ = (_zz_1029_ == _zz_1030_); + assign _zz_1000_ = (_zz_1031_ == _zz_1032_); + assign _zz_1001_ = 32'h60000120; + assign _zz_1002_ = (_zz_1033_ == _zz_1034_); + assign _zz_1003_ = _zz_220_; + assign _zz_1004_ = {_zz_1035_,_zz_1036_}; + assign _zz_1005_ = (decode_INSTRUCTION & _zz_1037_); + assign _zz_1006_ = 32'h78000140; + assign _zz_1007_ = 32'h780003a8; + assign _zz_1008_ = _zz_205_; + assign _zz_1009_ = {_zz_1038_,_zz_1039_}; + assign _zz_1010_ = _zz_1040_; + assign _zz_1011_ = _zz_171_; + assign _zz_1012_ = {_zz_1041_,_zz_1042_}; + assign _zz_1013_ = 9'h0; + assign _zz_1014_ = (_zz_1043_ != _zz_1044_); + assign _zz_1015_ = _zz_1045_; + assign _zz_1016_ = {_zz_1046_,_zz_1047_}; + assign _zz_1017_ = (decode_INSTRUCTION & 32'h78000438); + assign _zz_1018_ = 32'h78000028; + assign _zz_1019_ = ((decode_INSTRUCTION & _zz_1048_) == 32'h80000000); + assign _zz_1020_ = _zz_202_; + assign _zz_1021_ = (_zz_1049_ == _zz_1050_); + assign _zz_1022_ = 32'hf4080000; + assign _zz_1023_ = (decode_INSTRUCTION & 32'hdc020000); + assign _zz_1024_ = 32'h90020000; + assign _zz_1025_ = ((decode_INSTRUCTION & _zz_1051_) == 32'h90040000); + assign _zz_1026_ = (_zz_1052_ == _zz_1053_); + assign _zz_1027_ = {_zz_1054_,{_zz_1055_,_zz_1056_}}; + assign _zz_1028_ = 32'hd8000468; + assign _zz_1029_ = (decode_INSTRUCTION & 32'hd80002c8); + assign _zz_1030_ = 32'h58000200; + assign _zz_1031_ = (decode_INSTRUCTION & 32'hd8000384); + assign _zz_1032_ = 32'h58000000; + assign _zz_1033_ = (decode_INSTRUCTION & 32'hd0100000); + assign _zz_1034_ = 32'h10100000; + assign _zz_1035_ = _zz_170_; + assign _zz_1036_ = {_zz_219_,{_zz_1057_,_zz_1058_}}; + assign _zz_1037_ = 32'h78000150; + assign _zz_1038_ = _zz_204_; + assign _zz_1039_ = {_zz_171_,_zz_203_}; + assign _zz_1040_ = ((decode_INSTRUCTION & _zz_1059_) == 32'h4c000120); + assign _zz_1041_ = _zz_192_; + assign _zz_1042_ = {_zz_191_,{_zz_1060_,_zz_1061_}}; + assign _zz_1043_ = {_zz_1062_,{_zz_1063_,_zz_1064_}}; + assign _zz_1044_ = 5'h0; + assign _zz_1045_ = ({_zz_1065_,_zz_1066_} != 6'h0); + assign _zz_1046_ = (_zz_1067_ != _zz_1068_); + assign _zz_1047_ = {_zz_1069_,{_zz_1070_,_zz_1071_}}; + assign _zz_1048_ = 32'he40f0000; + assign _zz_1049_ = (decode_INSTRUCTION & 32'hcc0f0000); + assign _zz_1050_ = 32'h80000000; + assign _zz_1051_ = 32'hf4040000; + assign _zz_1052_ = (decode_INSTRUCTION & 32'hf4010000); + assign _zz_1053_ = 32'h90010000; + assign _zz_1054_ = ((decode_INSTRUCTION & _zz_1072_) == 32'h90010000); + assign _zz_1055_ = (_zz_1073_ == _zz_1074_); + assign _zz_1056_ = {_zz_1075_,_zz_1076_}; + assign _zz_1057_ = _zz_218_; + assign _zz_1058_ = {_zz_217_,{_zz_1077_,_zz_1078_}}; + assign _zz_1059_ = 32'h7c000120; + assign _zz_1060_ = _zz_169_; + assign _zz_1061_ = {_zz_1079_,{_zz_1080_,_zz_1081_}}; + assign _zz_1062_ = ((decode_INSTRUCTION & _zz_1082_) == 32'h48000004); + assign _zz_1063_ = _zz_212_; + assign _zz_1064_ = {_zz_211_,{_zz_1083_,_zz_1084_}}; + assign _zz_1065_ = (_zz_1085_ == _zz_1086_); + assign _zz_1066_ = {_zz_212_,{_zz_1087_,_zz_1088_}}; + assign _zz_1067_ = _zz_208_; + assign _zz_1068_ = (1'b0); + assign _zz_1069_ = (_zz_207_ != (1'b0)); + assign _zz_1070_ = (_zz_1089_ != _zz_1090_); + assign _zz_1071_ = {_zz_1091_,{_zz_1092_,_zz_1093_}}; + assign _zz_1072_ = 32'hdc010000; + assign _zz_1073_ = (decode_INSTRUCTION & 32'hdc080000); + assign _zz_1074_ = 32'h90080000; + assign _zz_1075_ = ((decode_INSTRUCTION & _zz_1094_) == 32'h90000000); + assign _zz_1076_ = ((decode_INSTRUCTION & _zz_1095_) == 32'h90000000); + assign _zz_1077_ = (_zz_1096_ == _zz_1097_); + assign _zz_1078_ = {_zz_1098_,{_zz_1099_,_zz_1100_}}; + assign _zz_1079_ = ((decode_INSTRUCTION & _zz_1101_) == 32'h40000020); + assign _zz_1080_ = (_zz_1102_ == _zz_1103_); + assign _zz_1081_ = {_zz_1104_,{_zz_1105_,_zz_1106_}}; + assign _zz_1082_ = 32'h78000004; + assign _zz_1083_ = _zz_210_; + assign _zz_1084_ = _zz_209_; + assign _zz_1085_ = (decode_INSTRUCTION & 32'hd8000000); + assign _zz_1086_ = 32'h0; + assign _zz_1087_ = _zz_194_; + assign _zz_1088_ = {_zz_211_,{_zz_1107_,_zz_1108_}}; + assign _zz_1089_ = {_zz_201_,{_zz_1109_,_zz_1110_}}; + assign _zz_1090_ = (3'b000); + assign _zz_1091_ = ({_zz_1111_,_zz_1112_} != (3'b000)); + assign _zz_1092_ = (_zz_1113_ != _zz_1114_); + assign _zz_1093_ = {_zz_1115_,{_zz_1116_,_zz_1117_}}; + assign _zz_1094_ = 32'hdc0f0000; + assign _zz_1095_ = 32'hf40f0000; + assign _zz_1096_ = (decode_INSTRUCTION & 32'hac000000); + assign _zz_1097_ = 32'h20000000; + assign _zz_1098_ = ((decode_INSTRUCTION & _zz_1118_) == 32'h60000100); + assign _zz_1099_ = _zz_216_; + assign _zz_1100_ = {_zz_180_,{_zz_1119_,_zz_1120_}}; + assign _zz_1101_ = 32'h40000024; + assign _zz_1102_ = (decode_INSTRUCTION & 32'h40000028); + assign _zz_1103_ = 32'h40000020; + assign _zz_1104_ = ((decode_INSTRUCTION & _zz_1121_) == 32'h40000400); + assign _zz_1105_ = (_zz_1122_ == _zz_1123_); + assign _zz_1106_ = {_zz_1124_,_zz_1125_}; + assign _zz_1107_ = _zz_210_; + assign _zz_1108_ = _zz_209_; + assign _zz_1109_ = _zz_207_; + assign _zz_1110_ = (_zz_1126_ == _zz_1127_); + assign _zz_1111_ = (_zz_1128_ == _zz_1129_); + assign _zz_1112_ = {_zz_1130_,_zz_1131_}; + assign _zz_1113_ = {_zz_206_,{_zz_1132_,_zz_1133_}}; + assign _zz_1114_ = 15'h0; + assign _zz_1115_ = ({_zz_1134_,_zz_1135_} != (2'b00)); + assign _zz_1116_ = (_zz_1136_ != _zz_1137_); + assign _zz_1117_ = {_zz_1138_,{_zz_1139_,_zz_1140_}}; + assign _zz_1118_ = 32'h60000128; + assign _zz_1119_ = _zz_179_; + assign _zz_1120_ = {_zz_178_,{_zz_1141_,_zz_1142_}}; + assign _zz_1121_ = 32'h40000414; + assign _zz_1122_ = (decode_INSTRUCTION & 32'h40000038); + assign _zz_1123_ = 32'h40000008; + assign _zz_1124_ = ((decode_INSTRUCTION & _zz_1143_) == 32'h0); + assign _zz_1125_ = ((decode_INSTRUCTION & _zz_1144_) == 32'h0); + assign _zz_1126_ = (decode_INSTRUCTION & 32'h780005e8); + assign _zz_1127_ = 32'h78000080; + assign _zz_1128_ = (decode_INSTRUCTION & 32'h7c000104); + assign _zz_1129_ = 32'h4c000100; + assign _zz_1130_ = ((decode_INSTRUCTION & _zz_1145_) == 32'h4c000200); + assign _zz_1131_ = ((decode_INSTRUCTION & _zz_1146_) == 32'h4c000040); + assign _zz_1132_ = _zz_170_; + assign _zz_1133_ = {_zz_180_,{_zz_1147_,_zz_1148_}}; + assign _zz_1134_ = (_zz_1149_ == _zz_1150_); + assign _zz_1135_ = _zz_171_; + assign _zz_1136_ = {_zz_201_,_zz_196_}; + assign _zz_1137_ = (2'b00); + assign _zz_1138_ = ({_zz_1151_,_zz_1152_} != (4'b0000)); + assign _zz_1139_ = (_zz_1153_ != _zz_1154_); + assign _zz_1140_ = {_zz_1155_,{_zz_1156_,_zz_1157_}}; + assign _zz_1141_ = _zz_177_; + assign _zz_1142_ = {_zz_173_,{_zz_1158_,_zz_1159_}}; + assign _zz_1143_ = 32'hf0000000; + assign _zz_1144_ = 32'hb0000004; + assign _zz_1145_ = 32'h7c000204; + assign _zz_1146_ = 32'h7c000444; + assign _zz_1147_ = _zz_179_; + assign _zz_1148_ = {_zz_1160_,{_zz_1161_,_zz_1162_}}; + assign _zz_1149_ = (decode_INSTRUCTION & 32'h78000318); + assign _zz_1150_ = 32'h78000300; + assign _zz_1151_ = _zz_200_; + assign _zz_1152_ = {_zz_171_,{_zz_1163_,_zz_1164_}}; + assign _zz_1153_ = {_zz_163_,_zz_162_}; + assign _zz_1154_ = (2'b00); + assign _zz_1155_ = ({_zz_1165_,_zz_1166_} != 8'h0); + assign _zz_1156_ = (_zz_1167_ != _zz_1168_); + assign _zz_1157_ = {_zz_1169_,{_zz_1170_,_zz_1171_}}; + assign _zz_1158_ = _zz_172_; + assign _zz_1159_ = {_zz_175_,{_zz_1172_,_zz_1173_}}; + assign _zz_1160_ = ((decode_INSTRUCTION & _zz_1174_) == 32'h0c000000); + assign _zz_1161_ = _zz_178_; + assign _zz_1162_ = {_zz_177_,{_zz_1175_,_zz_1176_}}; + assign _zz_1163_ = _zz_199_; + assign _zz_1164_ = _zz_193_; + assign _zz_1165_ = _zz_198_; + assign _zz_1166_ = {_zz_1177_,{_zz_1178_,_zz_1179_}}; + assign _zz_1167_ = _zz_167_; + assign _zz_1168_ = (1'b0); + assign _zz_1169_ = ({_zz_1180_,_zz_1181_} != 6'h0); + assign _zz_1170_ = (_zz_1182_ != _zz_1183_); + assign _zz_1171_ = {_zz_1184_,{_zz_1185_,_zz_1186_}}; + assign _zz_1172_ = (_zz_1187_ == _zz_1188_); + assign _zz_1173_ = {_zz_174_,{_zz_1189_,_zz_1190_}}; + assign _zz_1174_ = 32'h7c000000; + assign _zz_1175_ = (_zz_1191_ == _zz_1192_); + assign _zz_1176_ = {_zz_1193_,{_zz_1194_,_zz_1195_}}; + assign _zz_1177_ = ((decode_INSTRUCTION & _zz_1196_) == 32'h50000000); + assign _zz_1178_ = (_zz_1197_ == _zz_1198_); + assign _zz_1179_ = {_zz_1199_,{_zz_1200_,_zz_1201_}}; + assign _zz_1180_ = _zz_160_; + assign _zz_1181_ = {_zz_1202_,{_zz_1203_,_zz_1204_}}; + assign _zz_1182_ = {_zz_1205_,{_zz_1206_,_zz_1207_}}; + assign _zz_1183_ = (4'b0000); + assign _zz_1184_ = ({_zz_1208_,_zz_1209_} != 6'h0); + assign _zz_1185_ = (_zz_1210_ != _zz_1211_); + assign _zz_1186_ = {_zz_1212_,{_zz_1213_,_zz_1214_}}; + assign _zz_1187_ = (decode_INSTRUCTION & _zz_1215_); + assign _zz_1188_ = 32'h4c000004; + assign _zz_1189_ = _zz_202_; + assign _zz_1190_ = _zz_1216_; + assign _zz_1191_ = (decode_INSTRUCTION & _zz_1217_); + assign _zz_1192_ = 32'h040000a0; + assign _zz_1193_ = (_zz_1218_ == _zz_1219_); + assign _zz_1194_ = _zz_205_; + assign _zz_1195_ = {_zz_1220_,_zz_1221_}; + assign _zz_1196_ = 32'hf8000000; + assign _zz_1197_ = (decode_INSTRUCTION & _zz_1222_); + assign _zz_1198_ = 32'h58000200; + assign _zz_1199_ = (_zz_1223_ == _zz_1224_); + assign _zz_1200_ = _zz_1225_; + assign _zz_1201_ = {_zz_1226_,_zz_1227_}; + assign _zz_1202_ = (_zz_1228_ == _zz_1229_); + assign _zz_1203_ = _zz_159_; + assign _zz_1204_ = {_zz_1230_,_zz_1231_}; + assign _zz_1205_ = (_zz_1232_ == _zz_1233_); + assign _zz_1206_ = _zz_1234_; + assign _zz_1207_ = {_zz_1235_,_zz_1236_}; + assign _zz_1208_ = _zz_192_; + assign _zz_1209_ = {_zz_1237_,_zz_1238_}; + assign _zz_1210_ = {_zz_1239_,_zz_1240_}; + assign _zz_1211_ = 11'h0; + assign _zz_1212_ = (_zz_1241_ != _zz_1242_); + assign _zz_1213_ = _zz_1243_; + assign _zz_1214_ = {_zz_1244_,_zz_1245_}; + assign _zz_1215_ = 32'h4c00002c; + assign _zz_1216_ = ((decode_INSTRUCTION & _zz_1246_) == 32'h38000000); + assign _zz_1217_ = 32'h340004a0; + assign _zz_1218_ = (decode_INSTRUCTION & 32'h34000460); + assign _zz_1219_ = 32'h04000060; + assign _zz_1220_ = _zz_204_; + assign _zz_1221_ = {_zz_1247_,{_zz_1248_,_zz_1249_}}; + assign _zz_1222_ = 32'hd8000282; + assign _zz_1223_ = (decode_INSTRUCTION & 32'hd8000124); + assign _zz_1224_ = 32'h58000020; + assign _zz_1225_ = ((decode_INSTRUCTION & _zz_1250_) == 32'h58000004); + assign _zz_1226_ = (_zz_1251_ == _zz_1252_); + assign _zz_1227_ = {_zz_1253_,_zz_1254_}; + assign _zz_1228_ = (decode_INSTRUCTION & 32'h0c000000); + assign _zz_1229_ = 32'h04000000; + assign _zz_1230_ = (_zz_1255_ == _zz_1256_); + assign _zz_1231_ = {_zz_1257_,_zz_168_}; + assign _zz_1232_ = (decode_INSTRUCTION & 32'h44000000); + assign _zz_1233_ = 32'h40000000; + assign _zz_1234_ = ((decode_INSTRUCTION & _zz_1258_) == 32'h0); + assign _zz_1235_ = _zz_197_; + assign _zz_1236_ = (_zz_1259_ == _zz_1260_); + assign _zz_1237_ = _zz_169_; + assign _zz_1238_ = {_zz_197_,{_zz_1261_,_zz_1262_}}; + assign _zz_1239_ = _zz_165_; + assign _zz_1240_ = {_zz_191_,{_zz_1263_,_zz_1264_}}; + assign _zz_1241_ = _zz_196_; + assign _zz_1242_ = (1'b0); + assign _zz_1243_ = (_zz_1265_ != (1'b0)); + assign _zz_1244_ = (_zz_1266_ != _zz_1267_); + assign _zz_1245_ = {_zz_1268_,{_zz_1269_,_zz_1270_}}; + assign _zz_1246_ = 32'hf80f0000; + assign _zz_1247_ = ((decode_INSTRUCTION & _zz_1271_) == 32'h78000028); + assign _zz_1248_ = _zz_171_; + assign _zz_1249_ = {_zz_203_,_zz_202_}; + assign _zz_1250_ = 32'hd8000026; + assign _zz_1251_ = (decode_INSTRUCTION & 32'hd8000244); + assign _zz_1252_ = 32'h58000200; + assign _zz_1253_ = ((decode_INSTRUCTION & _zz_1272_) == 32'h580000c0); + assign _zz_1254_ = ((decode_INSTRUCTION & _zz_1273_) == 32'h58000010); + assign _zz_1255_ = (decode_INSTRUCTION & 32'h14000000); + assign _zz_1256_ = 32'h04000000; + assign _zz_1257_ = ((decode_INSTRUCTION & _zz_1274_) == 32'h0); + assign _zz_1258_ = 32'hb0000000; + assign _zz_1259_ = (decode_INSTRUCTION & 32'h78000066); + assign _zz_1260_ = 32'h78000044; + assign _zz_1261_ = (_zz_1275_ == _zz_1276_); + assign _zz_1262_ = {_zz_1277_,_zz_1278_}; + assign _zz_1263_ = (_zz_1279_ == _zz_1280_); + assign _zz_1264_ = {_zz_1281_,{_zz_1282_,_zz_1283_}}; + assign _zz_1265_ = ((decode_INSTRUCTION & _zz_1284_) == 32'h78100020); + assign _zz_1266_ = _zz_195_; + assign _zz_1267_ = (1'b0); + assign _zz_1268_ = ({_zz_1285_,_zz_1286_} != (2'b00)); + assign _zz_1269_ = (_zz_1287_ != _zz_1288_); + assign _zz_1270_ = {_zz_1289_,{_zz_1290_,_zz_1291_}}; + assign _zz_1271_ = 32'h78000138; + assign _zz_1272_ = 32'hd80002c4; + assign _zz_1273_ = 32'hd80000b2; + assign _zz_1274_ = 32'h48000000; + assign _zz_1275_ = (decode_INSTRUCTION & 32'h7c000000); + assign _zz_1276_ = 32'h3c000000; + assign _zz_1277_ = ((decode_INSTRUCTION & _zz_1292_) == 32'h60000080); + assign _zz_1278_ = ((decode_INSTRUCTION & _zz_1293_) == 32'h60000080); + assign _zz_1279_ = (decode_INSTRUCTION & 32'h58000000); + assign _zz_1280_ = 32'h48000000; + assign _zz_1281_ = ((decode_INSTRUCTION & _zz_1294_) == 32'h20000000); + assign _zz_1282_ = _zz_164_; + assign _zz_1283_ = {_zz_1295_,{_zz_1296_,_zz_1297_}}; + assign _zz_1284_ = 32'h781001b8; + assign _zz_1285_ = _zz_187_; + assign _zz_1286_ = (_zz_1298_ == _zz_1299_); + assign _zz_1287_ = {_zz_1300_,_zz_1301_}; + assign _zz_1288_ = (2'b00); + assign _zz_1289_ = ({_zz_1302_,_zz_1303_} != (2'b00)); + assign _zz_1290_ = (_zz_1304_ != _zz_1305_); + assign _zz_1291_ = {_zz_1306_,{_zz_1307_,_zz_1308_}}; + assign _zz_1292_ = 32'h600001a4; + assign _zz_1293_ = 32'h600002c2; + assign _zz_1294_ = 32'ha8000000; + assign _zz_1295_ = ((decode_INSTRUCTION & _zz_1309_) == 32'h20000108); + assign _zz_1296_ = (_zz_1310_ == _zz_1311_); + assign _zz_1297_ = {_zz_1312_,{_zz_1313_,_zz_1314_}}; + assign _zz_1298_ = (decode_INSTRUCTION & 32'h78000538); + assign _zz_1299_ = 32'h78000000; + assign _zz_1300_ = ((decode_INSTRUCTION & _zz_1315_) == 32'h00000040); + assign _zz_1301_ = ((decode_INSTRUCTION & _zz_1316_) == 32'h0); + assign _zz_1302_ = _zz_158_; + assign _zz_1303_ = (_zz_1317_ == _zz_1318_); + assign _zz_1304_ = {_zz_1319_,{_zz_1320_,_zz_1321_}}; + assign _zz_1305_ = (3'b000); + assign _zz_1306_ = ({_zz_1322_,_zz_1323_} != (2'b00)); + assign _zz_1307_ = (_zz_1324_ != _zz_1325_); + assign _zz_1308_ = {_zz_1326_,{_zz_1327_,_zz_1328_}}; + assign _zz_1309_ = 32'ha0000108; + assign _zz_1310_ = (decode_INSTRUCTION & 32'ha0000018); + assign _zz_1311_ = 32'h20000018; + assign _zz_1312_ = ((decode_INSTRUCTION & _zz_1329_) == 32'h20000010); + assign _zz_1313_ = (_zz_1330_ == _zz_1331_); + assign _zz_1314_ = {_zz_1332_,_zz_1333_}; + assign _zz_1315_ = 32'h000000c0; + assign _zz_1316_ = 32'h00000280; + assign _zz_1317_ = (decode_INSTRUCTION & 32'h00000180); + assign _zz_1318_ = 32'h00000100; + assign _zz_1319_ = ((decode_INSTRUCTION & _zz_1334_) == 32'h00000300); + assign _zz_1320_ = (_zz_1335_ == _zz_1336_); + assign _zz_1321_ = (_zz_1337_ == _zz_1338_); + assign _zz_1322_ = (_zz_1339_ == _zz_1340_); + assign _zz_1323_ = (_zz_1341_ == _zz_1342_); + assign _zz_1324_ = {_zz_1343_,{_zz_1344_,_zz_1345_}}; + assign _zz_1325_ = (3'b000); + assign _zz_1326_ = ({_zz_1346_,_zz_1347_} != (3'b000)); + assign _zz_1327_ = (_zz_1348_ != _zz_1349_); + assign _zz_1328_ = {_zz_1350_,{_zz_1351_,_zz_1352_}}; + assign _zz_1329_ = 32'ha0000012; + assign _zz_1330_ = (decode_INSTRUCTION & 32'ha000000c); + assign _zz_1331_ = 32'h20000000; + assign _zz_1332_ = ((decode_INSTRUCTION & _zz_1353_) == 32'h20000200); + assign _zz_1333_ = ((decode_INSTRUCTION & _zz_1354_) == 32'h20000000); + assign _zz_1334_ = 32'h00000300; + assign _zz_1335_ = (decode_INSTRUCTION & 32'h00000140); + assign _zz_1336_ = 32'h00000140; + assign _zz_1337_ = (decode_INSTRUCTION & 32'h00000240); + assign _zz_1338_ = 32'h00000240; + assign _zz_1339_ = (decode_INSTRUCTION & 32'h18000008); + assign _zz_1340_ = 32'h18000000; + assign _zz_1341_ = (decode_INSTRUCTION & 32'h18000280); + assign _zz_1342_ = 32'h18000080; + assign _zz_1343_ = ((decode_INSTRUCTION & _zz_1355_) == 32'h08000000); + assign _zz_1344_ = (_zz_1356_ == _zz_1357_); + assign _zz_1345_ = (_zz_1358_ == _zz_1359_); + assign _zz_1346_ = (_zz_1360_ == _zz_1361_); + assign _zz_1347_ = {_zz_1362_,_zz_1363_}; + assign _zz_1348_ = {_zz_1364_,{_zz_1365_,_zz_1366_}}; + assign _zz_1349_ = (3'b000); + assign _zz_1350_ = ({_zz_1367_,_zz_1368_} != (3'b000)); + assign _zz_1351_ = 1'b0; + assign _zz_1352_ = {_zz_1369_,{_zz_1370_,_zz_1371_}}; + assign _zz_1353_ = 32'ha0000218; + assign _zz_1354_ = 32'ha0000198; + assign _zz_1355_ = 32'h18000000; + assign _zz_1356_ = (decode_INSTRUCTION & 32'h080000c0); + assign _zz_1357_ = 32'h08000080; + assign _zz_1358_ = (decode_INSTRUCTION & 32'h08000300); + assign _zz_1359_ = 32'h08000200; + assign _zz_1360_ = (decode_INSTRUCTION & 32'h18000000); + assign _zz_1361_ = 32'h0; + assign _zz_1362_ = ((decode_INSTRUCTION & _zz_1372_) == 32'h18000200); + assign _zz_1363_ = ((decode_INSTRUCTION & _zz_1373_) == 32'h18000100); + assign _zz_1364_ = ((decode_INSTRUCTION & _zz_1374_) == 32'h18000040); + assign _zz_1365_ = (_zz_1375_ == _zz_1376_); + assign _zz_1366_ = (_zz_1377_ == _zz_1378_); + assign _zz_1367_ = _zz_194_; + assign _zz_1368_ = {_zz_190_,_zz_1379_}; + assign _zz_1369_ = (_zz_1380_ != (1'b0)); + assign _zz_1370_ = (_zz_1381_ != _zz_1382_); + assign _zz_1371_ = {_zz_1383_,{_zz_1384_,_zz_1385_}}; + assign _zz_1372_ = 32'h18000240; + assign _zz_1373_ = 32'h18000500; + assign _zz_1374_ = 32'h18000048; + assign _zz_1375_ = (decode_INSTRUCTION & 32'h18000540); + assign _zz_1376_ = 32'h18000100; + assign _zz_1377_ = (decode_INSTRUCTION & 32'h180002c0); + assign _zz_1378_ = 32'h18000040; + assign _zz_1379_ = ((decode_INSTRUCTION & 32'h78000132) == 32'h78000010); + assign _zz_1380_ = ((decode_INSTRUCTION & 32'h20000200) == 32'h20000200); + assign _zz_1381_ = ((decode_INSTRUCTION & _zz_1386_) == 32'h20000000); + assign _zz_1382_ = (1'b0); + assign _zz_1383_ = ({_zz_1387_,_zz_1388_} != (2'b00)); + assign _zz_1384_ = (_zz_1389_ != (1'b0)); + assign _zz_1385_ = {(_zz_1390_ != _zz_1391_),{_zz_1392_,{_zz_1393_,_zz_1394_}}}; + assign _zz_1386_ = 32'h20000200; + assign _zz_1387_ = ((decode_INSTRUCTION & 32'h04000000) == 32'h0); + assign _zz_1388_ = ((decode_INSTRUCTION & 32'h20000600) == 32'h20000400); + assign _zz_1389_ = ((decode_INSTRUCTION & 32'h7800038a) == 32'h78000202); + assign _zz_1390_ = {_zz_171_,_zz_193_}; + assign _zz_1391_ = (2'b00); + assign _zz_1392_ = (((decode_INSTRUCTION & _zz_1395_) == 32'h4c000400) != (1'b0)); + assign _zz_1393_ = ({_zz_1396_,_zz_1397_} != (2'b00)); + assign _zz_1394_ = {({_zz_1398_,_zz_1399_} != (3'b000)),{(_zz_1400_ != _zz_1401_),{_zz_1402_,{_zz_1403_,_zz_1404_}}}}; + assign _zz_1395_ = 32'h7c000404; + assign _zz_1396_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h40000000); + assign _zz_1397_ = ((decode_INSTRUCTION & 32'h7c0005e0) == 32'h4c000020); + assign _zz_1398_ = ((decode_INSTRUCTION & _zz_1405_) == 32'h48000000); + assign _zz_1399_ = {(_zz_1406_ == _zz_1407_),(_zz_1408_ == _zz_1409_)}; + assign _zz_1400_ = {_zz_165_,{_zz_192_,{_zz_1410_,_zz_1411_}}}; + assign _zz_1401_ = 6'h0; + assign _zz_1402_ = ({_zz_176_,{_zz_1412_,_zz_1413_}} != (4'b0000)); + assign _zz_1403_ = ({_zz_1414_,_zz_1415_} != 31'h0); + assign _zz_1404_ = {(_zz_1416_ != _zz_1417_),{_zz_1418_,{_zz_1419_,_zz_1420_}}}; + assign _zz_1405_ = 32'hfc000000; + assign _zz_1406_ = (decode_INSTRUCTION & 32'h78000046); + assign _zz_1407_ = 32'h48000040; + assign _zz_1408_ = (decode_INSTRUCTION & 32'h780005e0); + assign _zz_1409_ = 32'h48000020; + assign _zz_1410_ = (_zz_1421_ == _zz_1422_); + assign _zz_1411_ = {_zz_191_,{_zz_1423_,_zz_1424_}}; + assign _zz_1412_ = (_zz_1425_ == _zz_1426_); + assign _zz_1413_ = {_zz_190_,_zz_1427_}; + assign _zz_1414_ = (_zz_1428_ == _zz_1429_); + assign _zz_1415_ = {_zz_1430_,{_zz_1431_,_zz_1432_}}; + assign _zz_1416_ = {_zz_170_,_zz_1433_}; + assign _zz_1417_ = (2'b00); + assign _zz_1418_ = ({_zz_1434_,_zz_1435_} != 5'h0); + assign _zz_1419_ = (_zz_1436_ != _zz_1437_); + assign _zz_1420_ = {_zz_1438_,{_zz_1439_,_zz_1440_}}; + assign _zz_1421_ = (decode_INSTRUCTION & 32'h40000120); + assign _zz_1422_ = 32'h40000120; + assign _zz_1423_ = _zz_169_; + assign _zz_1424_ = (_zz_1441_ == _zz_1442_); + assign _zz_1425_ = (decode_INSTRUCTION & 32'h7800020c); + assign _zz_1426_ = 32'h78000200; + assign _zz_1427_ = ((decode_INSTRUCTION & _zz_1443_) == 32'h78000010); + assign _zz_1428_ = (decode_INSTRUCTION & 32'hc0100000); + assign _zz_1429_ = 32'h00100000; + assign _zz_1430_ = ((decode_INSTRUCTION & _zz_1444_) == 32'h00100000); + assign _zz_1431_ = _zz_189_; + assign _zz_1432_ = {_zz_188_,{_zz_1445_,_zz_1446_}}; + assign _zz_1433_ = ((decode_INSTRUCTION & _zz_1447_) == 32'h78000060); + assign _zz_1434_ = (_zz_1448_ == _zz_1449_); + assign _zz_1435_ = {_zz_1450_,{_zz_1451_,_zz_1452_}}; + assign _zz_1436_ = {_zz_1453_,{_zz_1454_,_zz_1455_}}; + assign _zz_1437_ = (4'b0000); + assign _zz_1438_ = ({_zz_1456_,_zz_1457_} != (2'b00)); + assign _zz_1439_ = (_zz_1458_ != _zz_1459_); + assign _zz_1440_ = {_zz_1460_,{_zz_1461_,_zz_1462_}}; + assign _zz_1441_ = (decode_INSTRUCTION & 32'h40000022); + assign _zz_1442_ = 32'h40000020; + assign _zz_1443_ = 32'h78000272; + assign _zz_1444_ = 32'h44100000; + assign _zz_1445_ = (_zz_1463_ == _zz_1464_); + assign _zz_1446_ = {_zz_187_,{_zz_1465_,_zz_1466_}}; + assign _zz_1447_ = 32'h78000170; + assign _zz_1448_ = (decode_INSTRUCTION & 32'hb0000000); + assign _zz_1449_ = 32'h10000000; + assign _zz_1450_ = ((decode_INSTRUCTION & _zz_1467_) == 32'h58000200); + assign _zz_1451_ = (_zz_1468_ == _zz_1469_); + assign _zz_1452_ = {_zz_1470_,_zz_1471_}; + assign _zz_1453_ = ((decode_INSTRUCTION & _zz_1472_) == 32'h60000000); + assign _zz_1454_ = _zz_169_; + assign _zz_1455_ = {_zz_1473_,_zz_1474_}; + assign _zz_1456_ = _zz_168_; + assign _zz_1457_ = (_zz_1475_ == _zz_1476_); + assign _zz_1458_ = {_zz_1477_,{_zz_1478_,_zz_1479_}}; + assign _zz_1459_ = (4'b0000); + assign _zz_1460_ = ({_zz_1480_,_zz_1481_} != (3'b000)); + assign _zz_1461_ = (_zz_1482_ != _zz_1483_); + assign _zz_1462_ = {_zz_1484_,{_zz_1485_,_zz_1486_}}; + assign _zz_1463_ = (decode_INSTRUCTION & 32'hec000000); + assign _zz_1464_ = 32'h0c000000; + assign _zz_1465_ = _zz_186_; + assign _zz_1466_ = {_zz_185_,{_zz_1487_,_zz_1488_}}; + assign _zz_1467_ = 32'h5800020c; + assign _zz_1468_ = (decode_INSTRUCTION & 32'h58000228); + assign _zz_1469_ = 32'h58000020; + assign _zz_1470_ = ((decode_INSTRUCTION & _zz_1489_) == 32'h580002c0); + assign _zz_1471_ = ((decode_INSTRUCTION & _zz_1490_) == 32'h58000020); + assign _zz_1472_ = 32'h68000000; + assign _zz_1473_ = ((decode_INSTRUCTION & _zz_1491_) == 32'h60000008); + assign _zz_1474_ = ((decode_INSTRUCTION & _zz_1492_) == 32'h60000024); + assign _zz_1475_ = (decode_INSTRUCTION & 32'h80000280); + assign _zz_1476_ = 32'h0; + assign _zz_1477_ = ((decode_INSTRUCTION & _zz_1493_) == 32'h0); + assign _zz_1478_ = (_zz_1494_ == _zz_1495_); + assign _zz_1479_ = {_zz_1496_,_zz_1497_}; + assign _zz_1480_ = _zz_167_; + assign _zz_1481_ = {_zz_161_,_zz_166_}; + assign _zz_1482_ = {_zz_165_,{_zz_1498_,_zz_1499_}}; + assign _zz_1483_ = 10'h0; + assign _zz_1484_ = (_zz_1500_ != (1'b0)); + assign _zz_1485_ = (_zz_1501_ != _zz_1502_); + assign _zz_1486_ = {_zz_1503_,{_zz_1504_,_zz_1505_}}; + assign _zz_1487_ = _zz_184_; + assign _zz_1488_ = {_zz_183_,{_zz_1506_,_zz_1507_}}; + assign _zz_1489_ = 32'h580002c4; + assign _zz_1490_ = 32'h5800042a; + assign _zz_1491_ = 32'h6000000c; + assign _zz_1492_ = 32'h6000002c; + assign _zz_1493_ = 32'h08000000; + assign _zz_1494_ = (decode_INSTRUCTION & 32'h80000200); + assign _zz_1495_ = 32'h00000200; + assign _zz_1496_ = ((decode_INSTRUCTION & _zz_1508_) == 32'h20000000); + assign _zz_1497_ = ((decode_INSTRUCTION & _zz_1509_) == 32'h0); + assign _zz_1498_ = (_zz_1510_ == _zz_1511_); + assign _zz_1499_ = {_zz_1512_,{_zz_1513_,_zz_1514_}}; + assign _zz_1500_ = ((decode_INSTRUCTION & _zz_1515_) == 32'h78000200); + assign _zz_1501_ = {_zz_163_,_zz_162_}; + assign _zz_1502_ = (2'b00); + assign _zz_1503_ = (_zz_161_ != (1'b0)); + assign _zz_1504_ = (_zz_1516_ != _zz_1517_); + assign _zz_1505_ = {_zz_1518_,{_zz_1519_,_zz_1520_}}; + assign _zz_1506_ = _zz_182_; + assign _zz_1507_ = {_zz_181_,{_zz_1521_,_zz_1522_}}; + assign _zz_1508_ = 32'h60000000; + assign _zz_1509_ = 32'h80000080; + assign _zz_1510_ = (decode_INSTRUCTION & 32'h40000002); + assign _zz_1511_ = 32'h40000000; + assign _zz_1512_ = ((decode_INSTRUCTION & _zz_1523_) == 32'h40000000); + assign _zz_1513_ = (_zz_1524_ == _zz_1525_); + assign _zz_1514_ = {_zz_1526_,{_zz_1527_,_zz_1528_}}; + assign _zz_1515_ = 32'h78000212; + assign _zz_1516_ = {_zz_1529_,_zz_1530_}; + assign _zz_1517_ = (2'b00); + assign _zz_1518_ = ({_zz_1531_,_zz_1532_} != 6'h0); + assign _zz_1519_ = (_zz_1533_ != _zz_1534_); + assign _zz_1520_ = {_zz_1535_,_zz_1536_}; + assign _zz_1521_ = _zz_180_; + assign _zz_1522_ = {_zz_179_,{_zz_1537_,_zz_1538_}}; + assign _zz_1523_ = 32'h60000000; + assign _zz_1524_ = (decode_INSTRUCTION & 32'h18000000); + assign _zz_1525_ = 32'h10000000; + assign _zz_1526_ = ((decode_INSTRUCTION & _zz_1539_) == 32'h0); + assign _zz_1527_ = (_zz_1540_ == _zz_1541_); + assign _zz_1528_ = {_zz_1542_,{_zz_1543_,_zz_1544_}}; + assign _zz_1529_ = ((decode_INSTRUCTION & _zz_1545_) == 32'h0); + assign _zz_1530_ = ((decode_INSTRUCTION & _zz_1546_) == 32'h40000010); + assign _zz_1531_ = _zz_160_; + assign _zz_1532_ = {_zz_1547_,{_zz_1548_,_zz_1549_}}; + assign _zz_1533_ = (_zz_1550_ == _zz_1551_); + assign _zz_1534_ = (1'b0); + assign _zz_1535_ = (_zz_1552_ != (1'b0)); + assign _zz_1536_ = ({_zz_1553_,_zz_1554_} != (3'b000)); + assign _zz_1537_ = _zz_178_; + assign _zz_1538_ = {_zz_1555_,{_zz_1556_,_zz_1557_}}; + assign _zz_1539_ = 32'h90000000; + assign _zz_1540_ = (decode_INSTRUCTION & 32'h40000028); + assign _zz_1541_ = 32'h40000008; + assign _zz_1542_ = ((decode_INSTRUCTION & _zz_1558_) == 32'h40000100); + assign _zz_1543_ = (_zz_1559_ == _zz_1560_); + assign _zz_1544_ = {_zz_164_,_zz_1561_}; + assign _zz_1545_ = 32'h98000000; + assign _zz_1546_ = 32'h40000134; + assign _zz_1547_ = ((decode_INSTRUCTION & _zz_1562_) == 32'h40000020); + assign _zz_1548_ = (_zz_1563_ == _zz_1564_); + assign _zz_1549_ = {_zz_159_,{_zz_1565_,_zz_1566_}}; + assign _zz_1550_ = (decode_INSTRUCTION & 32'h00000100); + assign _zz_1551_ = 32'h00000100; + assign _zz_1552_ = ((decode_INSTRUCTION & _zz_1567_) == 32'h00000080); + assign _zz_1553_ = (_zz_1568_ == _zz_1569_); + assign _zz_1554_ = {_zz_158_,_zz_1570_}; + assign _zz_1555_ = ((decode_INSTRUCTION & 32'hf8000000) == 32'h30000000); + assign _zz_1556_ = _zz_177_; + assign _zz_1557_ = {_zz_176_,{((decode_INSTRUCTION & _zz_1571_) == 32'h78000010),{_zz_175_,{_zz_174_,{_zz_1572_,_zz_1573_}}}}}; + assign _zz_1558_ = 32'h40000110; + assign _zz_1559_ = (decode_INSTRUCTION & 32'h40000220); + assign _zz_1560_ = 32'h40000200; + assign _zz_1561_ = ((decode_INSTRUCTION & 32'h40000018) == 32'h40000000); + assign _zz_1562_ = 32'h40000020; + assign _zz_1563_ = (decode_INSTRUCTION & 32'h40000010); + assign _zz_1564_ = 32'h40000000; + assign _zz_1565_ = ((decode_INSTRUCTION & 32'h48000000) == 32'h08000000); + assign _zz_1566_ = ((decode_INSTRUCTION & 32'h40000104) == 32'h40000004); + assign _zz_1567_ = 32'h00000180; + assign _zz_1568_ = (decode_INSTRUCTION & 32'h00000400); + assign _zz_1569_ = 32'h00000400; + assign _zz_1570_ = ((decode_INSTRUCTION & 32'h00000300) == 32'h00000200); + assign _zz_1571_ = 32'h78000030; + assign _zz_1572_ = _zz_173_; + assign _zz_1573_ = {_zz_172_,{((decode_INSTRUCTION & 32'h78000188) == 32'h78000180),{_zz_171_,{((decode_INSTRUCTION & 32'h38100458) == 32'h38100008),{((decode_INSTRUCTION & _zz_1574_) == 32'h78000000),{(_zz_1575_ == _zz_1576_),{_zz_1577_,{_zz_1578_,_zz_1579_}}}}}}}}; + assign _zz_1574_ = 32'h78000524; + assign _zz_1575_ = (decode_INSTRUCTION & 32'h38010478); + assign _zz_1576_ = 32'h38010028; + assign _zz_1577_ = ((decode_INSTRUCTION & 32'h38020478) == 32'h38020028); + assign _zz_1578_ = ((decode_INSTRUCTION & 32'h38080478) == 32'h38080028); + assign _zz_1579_ = ((decode_INSTRUCTION & 32'h38040478) == 32'h38040028); + assign _zz_1580_ = 11'h008; + assign _zz_1581_ = 11'h009; + assign _zz_1582_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h0},MSR_EE},MSR_PR}; + assign _zz_1583_ = MSR_FP; + assign _zz_1584_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h0},MSR_EE},MSR_PR}; + assign _zz_1585_ = MSR_FP; + assign _zz_1586_ = {{{{{{6'h0,MSR_VEC},(1'b0)},MSR_VSX},7'h02},MSR_EE},MSR_PR}; + assign _zz_1587_ = MSR_FP; + always @ (posedge clk) begin + if(_zz_130_) begin + IBusCachedPlugin_predictor_history[IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address] <= _zz_658_; + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready) begin + _zz_389_ <= IBusCachedPlugin_predictor_history[_zz_501_]; + end + end + + always @ (posedge clk) begin + if(_zz_659_) begin + _zz_390_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress1]; + end + end + + always @ (posedge clk) begin + if(_zz_660_) begin + _zz_391_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress2]; + end + end + + always @ (posedge clk) begin + if(_zz_661_) begin + _zz_392_ <= RegFilePlugin_regFile[decode_RegFilePlugin_regFileReadAddress3]; + end + end + + always @ (posedge clk) begin + if(_zz_103_) begin + RegFilePlugin_regFile[lastStageRegFileWrite_payload_address] <= lastStageRegFileWrite_payload_data; + end + end + + InstructionCache IBusCachedPlugin_cache ( + .io_flush (_zz_367_ ), //i + .io_cpu_prefetch_isValid (_zz_368_ ), //i + .io_cpu_prefetch_haltIt (IBusCachedPlugin_cache_io_cpu_prefetch_haltIt ), //o + .io_cpu_prefetch_pc (IBusCachedPlugin_iBusRsp_stages_0_input_payload[31:0] ), //i + .io_cpu_fetch_isValid (_zz_369_ ), //i + .io_cpu_fetch_isStuck (_zz_370_ ), //i + .io_cpu_fetch_isRemoved (IBusCachedPlugin_externalFlush ), //i + .io_cpu_fetch_pc (IBusCachedPlugin_iBusRsp_stages_1_input_payload[31:0] ), //i + .io_cpu_fetch_data (IBusCachedPlugin_cache_io_cpu_fetch_data[31:0] ), //o + .io_cpu_fetch_mmuBus_cmd_isValid (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid ), //o + .io_cpu_fetch_mmuBus_cmd_virtualAddress (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress[31:0] ), //o + .io_cpu_fetch_mmuBus_cmd_bypassTranslation (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation ), //o + .io_cpu_fetch_mmuBus_rsp_physicalAddress (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_fetch_mmuBus_rsp_isIoAccess (IBusCachedPlugin_mmuBus_rsp_isIoAccess ), //i + .io_cpu_fetch_mmuBus_rsp_allowRead (IBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_fetch_mmuBus_rsp_allowWrite (IBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_fetch_mmuBus_rsp_allowExecute (IBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_fetch_mmuBus_rsp_exception (IBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_fetch_mmuBus_rsp_refilling (IBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_fetch_mmuBus_spr_valid (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid ), //o + .io_cpu_fetch_mmuBus_spr_payload_id (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id[9:0] ), //o + .io_cpu_fetch_mmuBus_spr_payload_data (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data[31:0] ), //o + .io_cpu_fetch_mmuBus_end (IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end ), //o + .io_cpu_fetch_mmuBus_busy (IBusCachedPlugin_mmuBus_busy ), //i + .io_cpu_fetch_physicalAddress (IBusCachedPlugin_cache_io_cpu_fetch_physicalAddress[31:0] ), //o + .io_cpu_fetch_exceptionType (IBusCachedPlugin_cache_io_cpu_fetch_exceptionType[3:0] ), //o + .io_cpu_fetch_bypassTranslation (_zz_371_ ), //i + .io_cpu_fetch_haltIt (IBusCachedPlugin_cache_io_cpu_fetch_haltIt ), //o + .io_cpu_decode_isValid (_zz_372_ ), //i + .io_cpu_decode_isStuck (_zz_373_ ), //i + .io_cpu_decode_pc (IBusCachedPlugin_iBusRsp_stages_2_input_payload[31:0] ), //i + .io_cpu_decode_physicalAddress (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //o + .io_cpu_decode_data (IBusCachedPlugin_cache_io_cpu_decode_data[31:0] ), //o + .io_cpu_decode_cacheMiss (IBusCachedPlugin_cache_io_cpu_decode_cacheMiss ), //o + .io_cpu_decode_error (IBusCachedPlugin_cache_io_cpu_decode_error ), //o + .io_cpu_decode_mmuRefilling (IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling ), //o + .io_cpu_decode_mmuException (IBusCachedPlugin_cache_io_cpu_decode_mmuException ), //o + .io_cpu_decode_isUser (_zz_374_ ), //i + .io_cpu_decode_exceptionType (IBusCachedPlugin_cache_io_cpu_decode_exceptionType[3:0] ), //o + .io_cpu_fill_valid (_zz_375_ ), //i + .io_cpu_fill_payload (IBusCachedPlugin_cache_io_cpu_decode_physicalAddress[31:0] ), //i + .io_mem_cmd_valid (IBusCachedPlugin_cache_io_mem_cmd_valid ), //o + .io_mem_cmd_ready (iBus_cmd_ready ), //i + .io_mem_cmd_payload_address (IBusCachedPlugin_cache_io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_size (IBusCachedPlugin_cache_io_mem_cmd_payload_size[2:0] ), //o + .io_mem_rsp_valid (iBus_rsp_valid ), //i + .io_mem_rsp_payload_data (iBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (iBus_rsp_payload_error ), //i + .io_spr_valid (_zz_237_ ), //i + .io_spr_payload_id (_zz_376_[9:0] ), //i + .io_spr_payload_data (writeBack_SRC1[31:0] ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + DataCache dataCache_1_ ( + .io_cpu_execute_isValid (_zz_377_ ), //i + .io_cpu_execute_address (_zz_378_[31:0] ), //i + .io_cpu_execute_args_wr (execute_MEMORY_WR ), //i + .io_cpu_execute_args_data (_zz_379_[31:0] ), //i + .io_cpu_execute_args_size (execute_DBusCachedPlugin_size[1:0] ), //i + .io_cpu_memory_isValid (_zz_380_ ), //i + .io_cpu_memory_isStuck (memory_arbitration_isStuck ), //i + .io_cpu_memory_isRemoved (memory_arbitration_removeIt ), //i + .io_cpu_memory_isWrite (dataCache_1__io_cpu_memory_isWrite ), //o + .io_cpu_memory_address (_zz_381_[31:0] ), //i + .io_cpu_memory_mmuBus_cmd_isValid (dataCache_1__io_cpu_memory_mmuBus_cmd_isValid ), //o + .io_cpu_memory_mmuBus_cmd_virtualAddress (dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress[31:0] ), //o + .io_cpu_memory_mmuBus_cmd_bypassTranslation (dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation ), //o + .io_cpu_memory_mmuBus_rsp_physicalAddress (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31:0] ), //i + .io_cpu_memory_mmuBus_rsp_isIoAccess (_zz_382_ ), //i + .io_cpu_memory_mmuBus_rsp_allowRead (DBusCachedPlugin_mmuBus_rsp_allowRead ), //i + .io_cpu_memory_mmuBus_rsp_allowWrite (DBusCachedPlugin_mmuBus_rsp_allowWrite ), //i + .io_cpu_memory_mmuBus_rsp_allowExecute (DBusCachedPlugin_mmuBus_rsp_allowExecute ), //i + .io_cpu_memory_mmuBus_rsp_exception (DBusCachedPlugin_mmuBus_rsp_exception ), //i + .io_cpu_memory_mmuBus_rsp_refilling (DBusCachedPlugin_mmuBus_rsp_refilling ), //i + .io_cpu_memory_mmuBus_spr_valid (dataCache_1__io_cpu_memory_mmuBus_spr_valid ), //o + .io_cpu_memory_mmuBus_spr_payload_id (dataCache_1__io_cpu_memory_mmuBus_spr_payload_id[9:0] ), //o + .io_cpu_memory_mmuBus_spr_payload_data (dataCache_1__io_cpu_memory_mmuBus_spr_payload_data[31:0] ), //o + .io_cpu_memory_mmuBus_end (dataCache_1__io_cpu_memory_mmuBus_end ), //o + .io_cpu_memory_mmuBus_busy (DBusCachedPlugin_mmuBus_busy ), //i + .io_cpu_memory_bypassTranslation (_zz_383_ ), //i + .io_cpu_writeBack_isValid (_zz_384_ ), //i + .io_cpu_writeBack_isStuck (writeBack_arbitration_isStuck ), //i + .io_cpu_writeBack_isUser (_zz_385_ ), //i + .io_cpu_writeBack_haltIt (dataCache_1__io_cpu_writeBack_haltIt ), //o + .io_cpu_writeBack_isWrite (dataCache_1__io_cpu_writeBack_isWrite ), //o + .io_cpu_writeBack_data (dataCache_1__io_cpu_writeBack_data[31:0] ), //o + .io_cpu_writeBack_address (_zz_386_[31:0] ), //i + .io_cpu_writeBack_mmuException (dataCache_1__io_cpu_writeBack_mmuException ), //o + .io_cpu_writeBack_unalignedAccess (dataCache_1__io_cpu_writeBack_unalignedAccess ), //o + .io_cpu_writeBack_accessError (dataCache_1__io_cpu_writeBack_accessError ), //o + .io_cpu_writeBack_exceptionType (dataCache_1__io_cpu_writeBack_exceptionType[3:0] ), //o + .io_cpu_redo (dataCache_1__io_cpu_redo ), //o + .io_cpu_flush_valid (_zz_387_ ), //i + .io_cpu_flush_ready (dataCache_1__io_cpu_flush_ready ), //o + .io_mem_cmd_valid (dataCache_1__io_mem_cmd_valid ), //o + .io_mem_cmd_ready (_zz_388_ ), //i + .io_mem_cmd_payload_wr (dataCache_1__io_mem_cmd_payload_wr ), //o + .io_mem_cmd_payload_address (dataCache_1__io_mem_cmd_payload_address[31:0] ), //o + .io_mem_cmd_payload_data (dataCache_1__io_mem_cmd_payload_data[31:0] ), //o + .io_mem_cmd_payload_mask (dataCache_1__io_mem_cmd_payload_mask[3:0] ), //o + .io_mem_cmd_payload_length (dataCache_1__io_mem_cmd_payload_length[2:0] ), //o + .io_mem_cmd_payload_last (dataCache_1__io_mem_cmd_payload_last ), //o + .io_mem_rsp_valid (dBus_rsp_valid ), //i + .io_mem_rsp_payload_data (dBus_rsp_payload_data[31:0] ), //i + .io_mem_rsp_payload_error (dBus_rsp_payload_error ), //i + .clk (clk ), //i + .reset (reset ) //i + ); + always @(*) begin + case(_zz_662_) + 2'b00 : begin + _zz_393_ = DBusCachedPlugin_redoBranch_payload; + end + 2'b01 : begin + _zz_393_ = SPRPlugin_jumpInterface_payload; + end + default : begin + _zz_393_ = BranchPlugin_jumpInterface_payload; + end + endcase + end + + `ifndef SYNTHESIS + always @(*) begin + case(_zz_1_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_1__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_1__string = "RA"; + default : _zz_1__string = "??"; + endcase + end + always @(*) begin + case(_zz_2_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_2__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_2__string = "RA"; + default : _zz_2__string = "??"; + endcase + end + always @(*) begin + case(_zz_3_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_3__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_3__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_3__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_3__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_3__string = "RS "; + default : _zz_3__string = "??????"; + endcase + end + always @(*) begin + case(_zz_4_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_4__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_4__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_4__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_4__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_4__string = "RS "; + default : _zz_4__string = "??????"; + endcase + end + always @(*) begin + case(_zz_5_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_5__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_5__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_5__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_5__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_5__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_5__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_5__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_5__string = "RA "; + default : _zz_5__string = "????????"; + endcase + end + always @(*) begin + case(_zz_6_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_6__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_6__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_6__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_6__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_6__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_6__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_6__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_6__string = "RA "; + default : _zz_6__string = "????????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : decode_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : decode_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : decode_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : decode_DECODER_stageables_8_string = "SPEC "; + default : decode_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_7_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_7__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_7__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_7__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_7__string = "SPEC "; + default : _zz_7__string = "?????"; + endcase + end + always @(*) begin + case(_zz_8_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_8__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_8__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_8__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_8__string = "SPEC "; + default : _zz_8__string = "?????"; + endcase + end + always @(*) begin + case(_zz_9_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_9__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_9__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_9__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_9__string = "SPEC "; + default : _zz_9__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : decode_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : decode_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : decode_DECODER_stageables_1_string = "CA_1"; + default : decode_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_10_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_10__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_10__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_10__string = "CA_1"; + default : _zz_10__string = "????"; + endcase + end + always @(*) begin + case(_zz_11_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_11__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_11__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_11__string = "CA_1"; + default : _zz_11__string = "????"; + endcase + end + always @(*) begin + case(_zz_12_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_12__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_12__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_12__string = "CA_1"; + default : _zz_12__string = "????"; + endcase + end + always @(*) begin + case(memory_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : memory_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : memory_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : memory_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : memory_DECODER_stageables_7_string = "W "; + default : memory_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(_zz_13_) + `DataSizeEnum_defaultEncoding_B : _zz_13__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_13__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_13__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_13__string = "W "; + default : _zz_13__string = "??"; + endcase + end + always @(*) begin + case(_zz_14_) + `DataSizeEnum_defaultEncoding_B : _zz_14__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_14__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_14__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_14__string = "W "; + default : _zz_14__string = "??"; + endcase + end + always @(*) begin + case(_zz_15_) + `DataSizeEnum_defaultEncoding_B : _zz_15__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_15__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_15__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_15__string = "W "; + default : _zz_15__string = "??"; + endcase + end + always @(*) begin + case(_zz_16_) + `DataSizeEnum_defaultEncoding_B : _zz_16__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_16__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_16__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_16__string = "W "; + default : _zz_16__string = "??"; + endcase + end + always @(*) begin + case(_zz_17_) + `DataSizeEnum_defaultEncoding_B : _zz_17__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_17__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_17__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_17__string = "W "; + default : _zz_17__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : decode_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : decode_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : decode_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : decode_DECODER_stageables_7_string = "W "; + default : decode_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(_zz_18_) + `DataSizeEnum_defaultEncoding_B : _zz_18__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_18__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_18__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_18__string = "W "; + default : _zz_18__string = "??"; + endcase + end + always @(*) begin + case(_zz_19_) + `DataSizeEnum_defaultEncoding_B : _zz_19__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_19__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_19__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_19__string = "W "; + default : _zz_19__string = "??"; + endcase + end + always @(*) begin + case(_zz_20_) + `DataSizeEnum_defaultEncoding_B : _zz_20__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_20__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_20__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_20__string = "W "; + default : _zz_20__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : decode_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : decode_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : decode_DECODER_stageables_51_string = "MTCRF "; + default : decode_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(_zz_21_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_21__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_21__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_21__string = "MTCRF "; + default : _zz_21__string = "??????"; + endcase + end + always @(*) begin + case(_zz_22_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_22__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_22__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_22__string = "MTCRF "; + default : _zz_22__string = "??????"; + endcase + end + always @(*) begin + case(_zz_23_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_23__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_23__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_23__string = "MTCRF "; + default : _zz_23__string = "??????"; + endcase + end + always @(*) begin + case(memory_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : memory_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : memory_MSR_ENDIAN_string = "LE"; + default : memory_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_24_) + `EndianEnum_defaultEncoding_BE : _zz_24__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_24__string = "LE"; + default : _zz_24__string = "??"; + endcase + end + always @(*) begin + case(_zz_25_) + `EndianEnum_defaultEncoding_BE : _zz_25__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_25__string = "LE"; + default : _zz_25__string = "??"; + endcase + end + always @(*) begin + case(_zz_26_) + `EndianEnum_defaultEncoding_BE : _zz_26__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_26__string = "LE"; + default : _zz_26__string = "??"; + endcase + end + always @(*) begin + case(_zz_27_) + `EndianEnum_defaultEncoding_BE : _zz_27__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_27__string = "LE"; + default : _zz_27__string = "??"; + endcase + end + always @(*) begin + case(_zz_28_) + `EndianEnum_defaultEncoding_BE : _zz_28__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_28__string = "LE"; + default : _zz_28__string = "??"; + endcase + end + always @(*) begin + case(_zz_29_) + `EndianEnum_defaultEncoding_BE : _zz_29__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_29__string = "LE"; + default : _zz_29__string = "??"; + endcase + end + always @(*) begin + case(_zz_30_) + `EndianEnum_defaultEncoding_BE : _zz_30__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_30__string = "LE"; + default : _zz_30__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : decode_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : decode_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : decode_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : decode_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : decode_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : decode_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : decode_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : decode_DECODER_stageables_19_string = "EXTSH "; + default : decode_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(_zz_31_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_31__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_31__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_31__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_31__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_31__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_31__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_31__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_31__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_31__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_31__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_31__string = "EXTSH "; + default : _zz_31__string = "??????"; + endcase + end + always @(*) begin + case(_zz_32_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_32__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_32__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_32__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_32__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_32__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_32__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_32__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_32__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_32__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_32__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_32__string = "EXTSH "; + default : _zz_32__string = "??????"; + endcase + end + always @(*) begin + case(_zz_33_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_33__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_33__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_33__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_33__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_33__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_33__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_33__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_33__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_33__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_33__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_33__string = "EXTSH "; + default : _zz_33__string = "??????"; + endcase + end + always @(*) begin + case(_zz_34_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_34__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_34__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_34__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_34__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_34__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_34__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_34__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_34__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_34__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_34__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_34__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_34__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_34__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_34__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_34__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_34__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_34__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_34__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_34__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_34__string = "DECLNK"; + default : _zz_34__string = "??????"; + endcase + end + always @(*) begin + case(_zz_35_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_35__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_35__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_35__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_35__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_35__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_35__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_35__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_35__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_35__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_35__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_35__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_35__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_35__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_35__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_35__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_35__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_35__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_35__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_35__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_35__string = "DECLNK"; + default : _zz_35__string = "??????"; + endcase + end + always @(*) begin + case(execute_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_CR_WRITE_op_string = "DECLNK"; + default : execute_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_36_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_36__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_36__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_36__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_36__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_36__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_36__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_36__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_36__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_36__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_36__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_36__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_36__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_36__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_36__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_36__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_36__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_36__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_36__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_36__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_36__string = "DECLNK"; + default : _zz_36__string = "??????"; + endcase + end + always @(*) begin + case(_zz_37_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_37__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_37__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_37__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_37__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_37__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_37__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_37__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_37__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_37__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_37__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_37__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_37__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_37__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_37__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_37__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_37__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_37__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_37__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_37__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_37__string = "DECLNK"; + default : _zz_37__string = "??????"; + endcase + end + always @(*) begin + case(_zz_38_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_38__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_38__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_38__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_38__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_38__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_38__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_38__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_38__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_38__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_38__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_38__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_38__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_38__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_38__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_38__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_38__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_38__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_38__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_38__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_38__string = "DECLNK"; + default : _zz_38__string = "??????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : decode_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : decode_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : decode_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : decode_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : decode_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : decode_DECODER_stageables_0_string = "PRTYW "; + default : decode_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(_zz_39_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_39__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_39__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_39__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_39__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_39__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_39__string = "PRTYW "; + default : _zz_39__string = "???????"; + endcase + end + always @(*) begin + case(_zz_40_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_40__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_40__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_40__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_40__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_40__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_40__string = "PRTYW "; + default : _zz_40__string = "???????"; + endcase + end + always @(*) begin + case(_zz_41_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_41__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_41__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_41__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_41__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_41__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_41__string = "PRTYW "; + default : _zz_41__string = "???????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : decode_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : decode_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : decode_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : decode_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : decode_DECODER_stageables_16_string = "SHIFTRA"; + default : decode_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(_zz_42_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_42__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_42__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_42__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_42__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_42__string = "SHIFTRA"; + default : _zz_42__string = "???????"; + endcase + end + always @(*) begin + case(_zz_43_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_43__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_43__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_43__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_43__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_43__string = "SHIFTRA"; + default : _zz_43__string = "???????"; + endcase + end + always @(*) begin + case(_zz_44_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_44__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_44__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_44__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_44__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_44__string = "SHIFTRA"; + default : _zz_44__string = "???????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : decode_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : decode_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : decode_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : decode_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : decode_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : decode_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : decode_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : decode_DECODER_stageables_20_string = "ORC "; + default : decode_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(_zz_45_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_45__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_45__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_45__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_45__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_45__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_45__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_45__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_45__string = "ORC "; + default : _zz_45__string = "??????"; + endcase + end + always @(*) begin + case(_zz_46_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_46__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_46__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_46__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_46__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_46__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_46__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_46__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_46__string = "ORC "; + default : _zz_46__string = "??????"; + endcase + end + always @(*) begin + case(_zz_47_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_47__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_47__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_47__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_47__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_47__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_47__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_47__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_47__string = "ORC "; + default : _zz_47__string = "??????"; + endcase + end + always @(*) begin + case(_zz_48_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_48__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_48__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_48__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_48__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_48__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_48__string = "BCTAR"; + default : _zz_48__string = "?????"; + endcase + end + always @(*) begin + case(_zz_49_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_49__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_49__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_49__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_49__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_49__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_49__string = "BCTAR"; + default : _zz_49__string = "?????"; + endcase + end + always @(*) begin + case(memory_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : memory_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : memory_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : memory_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : memory_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : memory_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : memory_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : memory_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : memory_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : memory_DECODER_stageables_49_string = "TWI "; + default : memory_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_50_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_50__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_50__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_50__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_50__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_50__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_50__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_50__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_50__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_50__string = "TWI "; + default : _zz_50__string = "?????"; + endcase + end + always @(*) begin + case(_zz_51_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_51__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_51__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_51__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_51__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_51__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_51__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_51__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_51__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_51__string = "TWI "; + default : _zz_51__string = "?????"; + endcase + end + always @(*) begin + case(_zz_52_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_52__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_52__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_52__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_52__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_52__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_52__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_52__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_52__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_52__string = "TWI "; + default : _zz_52__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : decode_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : decode_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : decode_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : decode_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : decode_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : decode_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : decode_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : decode_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : decode_DECODER_stageables_49_string = "TWI "; + default : decode_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_53_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_53__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_53__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_53__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_53__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_53__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_53__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_53__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_53__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_53__string = "TWI "; + default : _zz_53__string = "?????"; + endcase + end + always @(*) begin + case(_zz_54_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_54__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_54__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_54__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_54__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_54__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_54__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_54__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_54__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_54__string = "TWI "; + default : _zz_54__string = "?????"; + endcase + end + always @(*) begin + case(_zz_55_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_55__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_55__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_55__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_55__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_55__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_55__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_55__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_55__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_55__string = "TWI "; + default : _zz_55__string = "?????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : decode_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : decode_DECODER_stageables_44_string = "RB "; + default : decode_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(_zz_56_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_56__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_56__string = "RB "; + default : _zz_56__string = "???"; + endcase + end + always @(*) begin + case(_zz_57_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_57__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_57__string = "RB "; + default : _zz_57__string = "???"; + endcase + end + always @(*) begin + case(_zz_58_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_58__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_58__string = "RB "; + default : _zz_58__string = "???"; + endcase + end + always @(*) begin + case(writeBack_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : writeBack_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : writeBack_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : writeBack_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : writeBack_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : writeBack_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : writeBack_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : writeBack_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : writeBack_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : writeBack_DECODER_stageables_49_string = "TWI "; + default : writeBack_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_59_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_59__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_59__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_59__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_59__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_59__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_59__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_59__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_59__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_59__string = "TWI "; + default : _zz_59__string = "?????"; + endcase + end + always @(*) begin + case(_zz_60_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_60__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_60__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_60__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_60__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_60__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_60__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_60__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_60__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_60__string = "TWI "; + default : _zz_60__string = "?????"; + endcase + end + always @(*) begin + case(_zz_61_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_61__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_61__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_61__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_61__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_61__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_61__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_61__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_61__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_61__string = "TWI "; + default : _zz_61__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : execute_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : execute_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : execute_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : execute_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : execute_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : execute_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : execute_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : execute_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : execute_DECODER_stageables_49_string = "TWI "; + default : execute_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(_zz_62_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_62__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_62__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_62__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_62__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_62__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_62__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_62__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_62__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_62__string = "TWI "; + default : _zz_62__string = "?????"; + endcase + end + always @(*) begin + case(_zz_63_) + `EndianEnum_defaultEncoding_BE : _zz_63__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_63__string = "LE"; + default : _zz_63__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : decode_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : decode_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : decode_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : decode_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : decode_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : decode_DECODER_stageables_13_string = "BCTAR"; + default : decode_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(_zz_65_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_65__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_65__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_65__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_65__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_65__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_65__string = "BCTAR"; + default : _zz_65__string = "?????"; + endcase + end + always @(*) begin + case(memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : memory_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : memory_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : memory_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : memory_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : memory_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : memory_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : memory_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : memory_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : memory_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : memory_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : memory_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : memory_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : memory_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : memory_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : memory_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : memory_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : memory_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : memory_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : memory_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : memory_CR_WRITE_op_string = "DECLNK"; + default : memory_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_66_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_66__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_66__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_66__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_66__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_66__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_66__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_66__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_66__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_66__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_66__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_66__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_66__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_66__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_66__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_66__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_66__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_66__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_66__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_66__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_66__string = "DECLNK"; + default : _zz_66__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : execute_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : execute_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : execute_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : execute_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : execute_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : execute_DECODER_stageables_13_string = "BCTAR"; + default : execute_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(_zz_67_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_67__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_67__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_67__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_67__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_67__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_67__string = "BCTAR"; + default : _zz_67__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : execute_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : execute_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : execute_DECODER_stageables_1_string = "CA_1"; + default : execute_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(_zz_70_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_70__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_70__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_70__string = "CA_1"; + default : _zz_70__string = "????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : execute_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : execute_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : execute_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : execute_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : execute_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : execute_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : execute_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_26_string = "RA "; + default : execute_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(_zz_71_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_71__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_71__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_71__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_71__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_71__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_71__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_71__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_71__string = "RA "; + default : _zz_71__string = "????????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : execute_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : execute_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : execute_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : execute_DECODER_stageables_38_string = "RS "; + default : execute_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(_zz_74_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_74__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_74__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_74__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_74__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_74__string = "RS "; + default : _zz_74__string = "??????"; + endcase + end + always @(*) begin + case(_zz_76_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_76__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_76__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_76__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_76__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_76__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_76__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_76__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_76__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_76__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_76__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_76__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_76__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_76__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_76__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_76__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_76__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_76__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_76__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_76__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_76__string = "DECLNK"; + default : _zz_76__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : execute_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : execute_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : execute_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : execute_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : execute_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : execute_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : execute_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : execute_DECODER_stageables_20_string = "ORC "; + default : execute_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(_zz_77_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_77__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_77__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_77__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_77__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_77__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_77__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_77__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_77__string = "ORC "; + default : _zz_77__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : execute_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : execute_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : execute_DECODER_stageables_51_string = "MTCRF "; + default : execute_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(_zz_78_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_78__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_78__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_78__string = "MTCRF "; + default : _zz_78__string = "??????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : execute_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : execute_DECODER_stageables_12_string = "RA"; + default : execute_DECODER_stageables_12_string = "??"; + endcase + end + always @(*) begin + case(_zz_80_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_80__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_80__string = "RA"; + default : _zz_80__string = "??"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : execute_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : execute_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : execute_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : execute_DECODER_stageables_8_string = "SPEC "; + default : execute_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(_zz_81_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_81__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_81__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_81__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_81__string = "SPEC "; + default : _zz_81__string = "?????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : execute_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : execute_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : execute_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : execute_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : execute_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : execute_DECODER_stageables_0_string = "PRTYW "; + default : execute_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(_zz_82_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_82__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_82__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_82__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_82__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_82__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_82__string = "PRTYW "; + default : _zz_82__string = "???????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : execute_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : execute_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : execute_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : execute_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : execute_DECODER_stageables_16_string = "SHIFTRA"; + default : execute_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(_zz_98_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_98__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_98__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_98__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_98__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_98__string = "SHIFTRA"; + default : _zz_98__string = "???????"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : execute_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : execute_DECODER_stageables_44_string = "RB "; + default : execute_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(_zz_99_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_99__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_99__string = "RB "; + default : _zz_99__string = "???"; + endcase + end + always @(*) begin + case(execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : execute_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : execute_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : execute_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : execute_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : execute_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : execute_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : execute_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : execute_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : execute_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : execute_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : execute_DECODER_stageables_19_string = "EXTSH "; + default : execute_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(_zz_100_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_100__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_100__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_100__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_100__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_100__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_100__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_100__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_100__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_100__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_100__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_100__string = "EXTSH "; + default : _zz_100__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : writeBack_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : writeBack_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : writeBack_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : writeBack_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : writeBack_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : writeBack_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : writeBack_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : writeBack_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : writeBack_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : writeBack_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : writeBack_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : writeBack_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : writeBack_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : writeBack_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : writeBack_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : writeBack_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : writeBack_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : writeBack_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : writeBack_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : writeBack_CR_WRITE_op_string = "DECLNK"; + default : writeBack_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_101_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_101__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_101__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_101__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_101__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_101__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_101__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_101__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_101__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_101__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_101__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_101__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_101__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_101__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_101__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_101__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_101__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_101__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_101__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_101__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_101__string = "DECLNK"; + default : _zz_101__string = "??????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : decode_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_12_string = "RA"; + default : decode_DECODER_stageables_12_string = "??"; + endcase + end + always @(*) begin + case(_zz_104_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_104__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_104__string = "RA"; + default : _zz_104__string = "??"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : decode_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : decode_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : decode_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : decode_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : decode_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : decode_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : decode_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_26_string = "RA "; + default : decode_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(_zz_105_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_105__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_105__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_105__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_105__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_105__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_105__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_105__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_105__string = "RA "; + default : _zz_105__string = "????????"; + endcase + end + always @(*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : decode_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : decode_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : decode_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : decode_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : decode_DECODER_stageables_38_string = "RS "; + default : decode_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(_zz_106_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_106__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_106__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_106__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_106__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_106__string = "RS "; + default : _zz_106__string = "??????"; + endcase + end + always @(*) begin + case(_zz_107_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_107__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_107__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_107__string = "MTCRF "; + default : _zz_107__string = "??????"; + endcase + end + always @(*) begin + case(_zz_108_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_108__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_108__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_108__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_108__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_108__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_108__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_108__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_108__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_108__string = "TWI "; + default : _zz_108__string = "?????"; + endcase + end + always @(*) begin + case(_zz_109_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_109__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_109__string = "RB "; + default : _zz_109__string = "???"; + endcase + end + always @(*) begin + case(_zz_110_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_110__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_110__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_110__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_110__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_110__string = "RS "; + default : _zz_110__string = "??????"; + endcase + end + always @(*) begin + case(_zz_111_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_111__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_111__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_111__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_111__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_111__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_111__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_111__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_111__string = "RA "; + default : _zz_111__string = "????????"; + endcase + end + always @(*) begin + case(_zz_112_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_112__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_112__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_112__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_112__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_112__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_112__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_112__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_112__string = "ORC "; + default : _zz_112__string = "??????"; + endcase + end + always @(*) begin + case(_zz_113_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_113__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_113__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_113__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_113__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_113__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_113__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_113__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_113__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_113__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_113__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_113__string = "EXTSH "; + default : _zz_113__string = "??????"; + endcase + end + always @(*) begin + case(_zz_114_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_114__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_114__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_114__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_114__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_114__string = "SHIFTRA"; + default : _zz_114__string = "???????"; + endcase + end + always @(*) begin + case(_zz_115_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_115__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_115__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_115__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_115__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_115__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_115__string = "BCTAR"; + default : _zz_115__string = "?????"; + endcase + end + always @(*) begin + case(_zz_116_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_116__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_116__string = "RA"; + default : _zz_116__string = "??"; + endcase + end + always @(*) begin + case(_zz_117_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_117__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_117__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_117__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_117__string = "SPEC "; + default : _zz_117__string = "?????"; + endcase + end + always @(*) begin + case(_zz_118_) + `DataSizeEnum_defaultEncoding_B : _zz_118__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_118__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_118__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_118__string = "W "; + default : _zz_118__string = "??"; + endcase + end + always @(*) begin + case(_zz_119_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_119__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_119__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_119__string = "CA_1"; + default : _zz_119__string = "????"; + endcase + end + always @(*) begin + case(_zz_120_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_120__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_120__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_120__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_120__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_120__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_120__string = "PRTYW "; + default : _zz_120__string = "???????"; + endcase + end + always @(*) begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : writeBack_DATA_SIZE_string = "B "; + `DataSizeEnum_defaultEncoding_H : writeBack_DATA_SIZE_string = "H "; + `DataSizeEnum_defaultEncoding_HA : writeBack_DATA_SIZE_string = "HA"; + `DataSizeEnum_defaultEncoding_W : writeBack_DATA_SIZE_string = "W "; + default : writeBack_DATA_SIZE_string = "??"; + endcase + end + always @(*) begin + case(_zz_122_) + `DataSizeEnum_defaultEncoding_B : _zz_122__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_122__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_122__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_122__string = "W "; + default : _zz_122__string = "??"; + endcase + end + always @(*) begin + case(writeBack_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : writeBack_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : writeBack_MSR_ENDIAN_string = "LE"; + default : writeBack_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_123_) + `EndianEnum_defaultEncoding_BE : _zz_123__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_123__string = "LE"; + default : _zz_123__string = "??"; + endcase + end + always @(*) begin + case(execute_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : execute_DATA_SIZE_string = "B "; + `DataSizeEnum_defaultEncoding_H : execute_DATA_SIZE_string = "H "; + `DataSizeEnum_defaultEncoding_HA : execute_DATA_SIZE_string = "HA"; + `DataSizeEnum_defaultEncoding_W : execute_DATA_SIZE_string = "W "; + default : execute_DATA_SIZE_string = "??"; + endcase + end + always @(*) begin + case(_zz_125_) + `DataSizeEnum_defaultEncoding_B : _zz_125__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_125__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_125__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_125__string = "W "; + default : _zz_125__string = "??"; + endcase + end + always @(*) begin + case(execute_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : execute_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : execute_MSR_ENDIAN_string = "LE"; + default : execute_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_126_) + `EndianEnum_defaultEncoding_BE : _zz_126__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_126__string = "LE"; + default : _zz_126__string = "??"; + endcase + end + always @(*) begin + case(decode_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : decode_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : decode_MSR_ENDIAN_string = "LE"; + default : decode_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(_zz_129_) + `EndianEnum_defaultEncoding_BE : _zz_129__string = "BE"; + `EndianEnum_defaultEncoding_LE : _zz_129__string = "LE"; + default : _zz_129__string = "??"; + endcase + end + always @(*) begin + case(IBusCachedPlugin_decodeExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "PM "; + default : IBusCachedPlugin_decodeExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(DBusCachedPlugin_exceptionBus_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "PM "; + default : DBusCachedPlugin_exceptionBus_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(decodeExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : decodeExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : decodeExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : decodeExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : decodeExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : decodeExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : decodeExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : decodeExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : decodeExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : decodeExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : decodeExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : decodeExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : decodeExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : decodeExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : decodeExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : decodeExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : decodeExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : decodeExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : decodeExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : decodeExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : decodeExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : decodeExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : decodeExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : decodeExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : decodeExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : decodeExceptionPort_payload_codePPC_string = "PM "; + default : decodeExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(BranchPlugin_branchExceptionPort_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : BranchPlugin_branchExceptionPort_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : BranchPlugin_branchExceptionPort_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : BranchPlugin_branchExceptionPort_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : BranchPlugin_branchExceptionPort_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : BranchPlugin_branchExceptionPort_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : BranchPlugin_branchExceptionPort_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : BranchPlugin_branchExceptionPort_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : BranchPlugin_branchExceptionPort_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : BranchPlugin_branchExceptionPort_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : BranchPlugin_branchExceptionPort_payload_codePPC_string = "PM "; + default : BranchPlugin_branchExceptionPort_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(SPRPlugin_selfException_payload_codePPC) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_selfException_payload_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_selfException_payload_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_selfException_payload_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_selfException_payload_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_selfException_payload_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_selfException_payload_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_selfException_payload_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_selfException_payload_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_selfException_payload_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_selfException_payload_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_selfException_payload_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_selfException_payload_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_selfException_payload_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_selfException_payload_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_selfException_payload_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_selfException_payload_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_selfException_payload_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_selfException_payload_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_selfException_payload_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_selfException_payload_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_selfException_payload_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_selfException_payload_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_selfException_payload_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_selfException_payload_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_selfException_payload_codePPC_string = "PM "; + default : SPRPlugin_selfException_payload_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(_zz_223_) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : _zz_223__string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : _zz_223__string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : _zz_223__string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : _zz_223__string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : _zz_223__string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : _zz_223__string = "PRTYW "; + default : _zz_223__string = "???????"; + endcase + end + always @(*) begin + case(_zz_224_) + `Src3CtrlEnum_defaultEncoding_CA : _zz_224__string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : _zz_224__string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : _zz_224__string = "CA_1"; + default : _zz_224__string = "????"; + endcase + end + always @(*) begin + case(_zz_225_) + `DataSizeEnum_defaultEncoding_B : _zz_225__string = "B "; + `DataSizeEnum_defaultEncoding_H : _zz_225__string = "H "; + `DataSizeEnum_defaultEncoding_HA : _zz_225__string = "HA"; + `DataSizeEnum_defaultEncoding_W : _zz_225__string = "W "; + default : _zz_225__string = "??"; + endcase + end + always @(*) begin + case(_zz_226_) + `AluCtrlEnum_defaultEncoding_ADD : _zz_226__string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : _zz_226__string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : _zz_226__string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : _zz_226__string = "SPEC "; + default : _zz_226__string = "?????"; + endcase + end + always @(*) begin + case(_zz_227_) + `TgtCtrlEnum_defaultEncoding_RT : _zz_227__string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : _zz_227__string = "RA"; + default : _zz_227__string = "??"; + endcase + end + always @(*) begin + case(_zz_228_) + `BranchCtrlEnum_defaultEncoding_NONE : _zz_228__string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : _zz_228__string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : _zz_228__string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : _zz_228__string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : _zz_228__string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : _zz_228__string = "BCTAR"; + default : _zz_228__string = "?????"; + endcase + end + always @(*) begin + case(_zz_229_) + `AluRimiCtrlEnum_defaultEncoding_ROT : _zz_229__string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : _zz_229__string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : _zz_229__string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : _zz_229__string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : _zz_229__string = "SHIFTRA"; + default : _zz_229__string = "???????"; + endcase + end + always @(*) begin + case(_zz_230_) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : _zz_230__string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : _zz_230__string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : _zz_230__string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : _zz_230__string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : _zz_230__string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : _zz_230__string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : _zz_230__string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : _zz_230__string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : _zz_230__string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : _zz_230__string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : _zz_230__string = "EXTSH "; + default : _zz_230__string = "??????"; + endcase + end + always @(*) begin + case(_zz_231_) + `CRLogCtrlEnum_defaultEncoding_AND_1 : _zz_231__string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : _zz_231__string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : _zz_231__string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : _zz_231__string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : _zz_231__string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : _zz_231__string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : _zz_231__string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : _zz_231__string = "ORC "; + default : _zz_231__string = "??????"; + endcase + end + always @(*) begin + case(_zz_232_) + `Src2CtrlEnum_defaultEncoding_RB : _zz_232__string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : _zz_232__string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : _zz_232__string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : _zz_232__string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : _zz_232__string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : _zz_232__string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : _zz_232__string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : _zz_232__string = "RA "; + default : _zz_232__string = "????????"; + endcase + end + always @(*) begin + case(_zz_233_) + `Src1CtrlEnum_defaultEncoding_RA : _zz_233__string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : _zz_233__string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : _zz_233__string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : _zz_233__string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : _zz_233__string = "RS "; + default : _zz_233__string = "??????"; + endcase + end + always @(*) begin + case(_zz_234_) + `AluRimiAmtEnum_defaultEncoding_IMM : _zz_234__string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : _zz_234__string = "RB "; + default : _zz_234__string = "???"; + endcase + end + always @(*) begin + case(_zz_235_) + `EnvCtrlEnum_defaultEncoding_NONE : _zz_235__string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : _zz_235__string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : _zz_235__string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : _zz_235__string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : _zz_235__string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : _zz_235__string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : _zz_235__string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : _zz_235__string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : _zz_235__string = "TWI "; + default : _zz_235__string = "?????"; + endcase + end + always @(*) begin + case(_zz_236_) + `CRMoveCtrlEnum_defaultEncoding_MCRF : _zz_236__string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : _zz_236__string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : _zz_236__string = "MTCRF "; + default : _zz_236__string = "??????"; + endcase + end + always @(*) begin + case(writeBack_RegFilePlugin_crBusPort_payload_op) + `CRBusCmdEnum_defaultEncoding_NOP : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : writeBack_RegFilePlugin_crBusPort_payload_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : writeBack_RegFilePlugin_crBusPort_payload_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : writeBack_RegFilePlugin_crBusPort_payload_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : writeBack_RegFilePlugin_crBusPort_payload_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : writeBack_RegFilePlugin_crBusPort_payload_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : writeBack_RegFilePlugin_crBusPort_payload_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : writeBack_RegFilePlugin_crBusPort_payload_op_string = "DECLNK"; + default : writeBack_RegFilePlugin_crBusPort_payload_op_string = "??????"; + endcase + end + always @(*) begin + case(ALU2_crBus_op) + `CRBusCmdEnum_defaultEncoding_NOP : ALU2_crBus_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : ALU2_crBus_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : ALU2_crBus_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : ALU2_crBus_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : ALU2_crBus_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : ALU2_crBus_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : ALU2_crBus_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : ALU2_crBus_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : ALU2_crBus_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : ALU2_crBus_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : ALU2_crBus_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : ALU2_crBus_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : ALU2_crBus_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : ALU2_crBus_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : ALU2_crBus_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : ALU2_crBus_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : ALU2_crBus_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : ALU2_crBus_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : ALU2_crBus_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : ALU2_crBus_op_string = "DECLNK"; + default : ALU2_crBus_op_string = "??????"; + endcase + end + always @(*) begin + case(_zz_273_) + `CRBusCmdEnum_defaultEncoding_NOP : _zz_273__string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : _zz_273__string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : _zz_273__string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : _zz_273__string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : _zz_273__string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : _zz_273__string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : _zz_273__string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : _zz_273__string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : _zz_273__string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : _zz_273__string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : _zz_273__string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : _zz_273__string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : _zz_273__string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : _zz_273__string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : _zz_273__string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : _zz_273__string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : _zz_273__string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : _zz_273__string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : _zz_273__string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : _zz_273__string = "DECLNK"; + default : _zz_273__string = "??????"; + endcase + end + always @(*) begin + case(MULDIV1_crBusPort_payload_op) + `CRBusCmdEnum_defaultEncoding_NOP : MULDIV1_crBusPort_payload_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : MULDIV1_crBusPort_payload_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : MULDIV1_crBusPort_payload_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : MULDIV1_crBusPort_payload_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : MULDIV1_crBusPort_payload_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : MULDIV1_crBusPort_payload_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : MULDIV1_crBusPort_payload_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : MULDIV1_crBusPort_payload_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : MULDIV1_crBusPort_payload_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : MULDIV1_crBusPort_payload_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : MULDIV1_crBusPort_payload_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : MULDIV1_crBusPort_payload_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : MULDIV1_crBusPort_payload_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : MULDIV1_crBusPort_payload_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : MULDIV1_crBusPort_payload_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : MULDIV1_crBusPort_payload_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : MULDIV1_crBusPort_payload_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : MULDIV1_crBusPort_payload_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : MULDIV1_crBusPort_payload_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : MULDIV1_crBusPort_payload_op_string = "DECLNK"; + default : MULDIV1_crBusPort_payload_op_string = "??????"; + endcase + end + always @(*) begin + case(execute_BranchPlugin_crBusPort_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_BranchPlugin_crBusPort_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_BranchPlugin_crBusPort_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_BranchPlugin_crBusPort_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_BranchPlugin_crBusPort_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_BranchPlugin_crBusPort_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_BranchPlugin_crBusPort_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_BranchPlugin_crBusPort_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_BranchPlugin_crBusPort_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_BranchPlugin_crBusPort_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_BranchPlugin_crBusPort_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_BranchPlugin_crBusPort_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_BranchPlugin_crBusPort_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_BranchPlugin_crBusPort_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_BranchPlugin_crBusPort_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_BranchPlugin_crBusPort_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_BranchPlugin_crBusPort_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_BranchPlugin_crBusPort_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_BranchPlugin_crBusPort_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_BranchPlugin_crBusPort_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_BranchPlugin_crBusPort_op_string = "DECLNK"; + default : execute_BranchPlugin_crBusPort_op_string = "??????"; + endcase + end + always @(*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "PM "; + default : SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(_zz_337_) + `ExcpEnum_defaultEncoding_NONE : _zz_337__string = "NONE "; + `ExcpEnum_defaultEncoding_SC : _zz_337__string = "SC "; + `ExcpEnum_defaultEncoding_SCV : _zz_337__string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : _zz_337__string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : _zz_337__string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : _zz_337__string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : _zz_337__string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : _zz_337__string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : _zz_337__string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : _zz_337__string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : _zz_337__string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : _zz_337__string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : _zz_337__string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : _zz_337__string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : _zz_337__string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : _zz_337__string = "FP "; + `ExcpEnum_defaultEncoding_VEC : _zz_337__string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : _zz_337__string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : _zz_337__string = "FAC "; + `ExcpEnum_defaultEncoding_SR : _zz_337__string = "SR "; + `ExcpEnum_defaultEncoding_MC : _zz_337__string = "MC "; + `ExcpEnum_defaultEncoding_EXT : _zz_337__string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : _zz_337__string = "DEC "; + `ExcpEnum_defaultEncoding_TR : _zz_337__string = "TR "; + `ExcpEnum_defaultEncoding_PM : _zz_337__string = "PM "; + default : _zz_337__string = "????????"; + endcase + end + always @(*) begin + case(_zz_340_) + `ExcpEnum_defaultEncoding_NONE : _zz_340__string = "NONE "; + `ExcpEnum_defaultEncoding_SC : _zz_340__string = "SC "; + `ExcpEnum_defaultEncoding_SCV : _zz_340__string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : _zz_340__string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : _zz_340__string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : _zz_340__string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : _zz_340__string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : _zz_340__string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : _zz_340__string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : _zz_340__string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : _zz_340__string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : _zz_340__string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : _zz_340__string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : _zz_340__string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : _zz_340__string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : _zz_340__string = "FP "; + `ExcpEnum_defaultEncoding_VEC : _zz_340__string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : _zz_340__string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : _zz_340__string = "FAC "; + `ExcpEnum_defaultEncoding_SR : _zz_340__string = "SR "; + `ExcpEnum_defaultEncoding_MC : _zz_340__string = "MC "; + `ExcpEnum_defaultEncoding_EXT : _zz_340__string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : _zz_340__string = "DEC "; + `ExcpEnum_defaultEncoding_TR : _zz_340__string = "TR "; + `ExcpEnum_defaultEncoding_PM : _zz_340__string = "PM "; + default : _zz_340__string = "????????"; + endcase + end + always @(*) begin + case(SPRPlugin_intType) + `ExcpEnum_defaultEncoding_NONE : SPRPlugin_intType_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : SPRPlugin_intType_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : SPRPlugin_intType_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : SPRPlugin_intType_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : SPRPlugin_intType_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : SPRPlugin_intType_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : SPRPlugin_intType_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : SPRPlugin_intType_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : SPRPlugin_intType_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : SPRPlugin_intType_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : SPRPlugin_intType_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : SPRPlugin_intType_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : SPRPlugin_intType_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : SPRPlugin_intType_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : SPRPlugin_intType_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : SPRPlugin_intType_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : SPRPlugin_intType_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : SPRPlugin_intType_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : SPRPlugin_intType_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : SPRPlugin_intType_string = "SR "; + `ExcpEnum_defaultEncoding_MC : SPRPlugin_intType_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : SPRPlugin_intType_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : SPRPlugin_intType_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : SPRPlugin_intType_string = "TR "; + `ExcpEnum_defaultEncoding_PM : SPRPlugin_intType_string = "PM "; + default : SPRPlugin_intType_string = "????????"; + endcase + end + always @(*) begin + case(execute_SPRPLUGIN_opExcp_codePPC) + `ExcpEnum_defaultEncoding_NONE : execute_SPRPLUGIN_opExcp_codePPC_string = "NONE "; + `ExcpEnum_defaultEncoding_SC : execute_SPRPLUGIN_opExcp_codePPC_string = "SC "; + `ExcpEnum_defaultEncoding_SCV : execute_SPRPLUGIN_opExcp_codePPC_string = "SCV "; + `ExcpEnum_defaultEncoding_TRAP : execute_SPRPLUGIN_opExcp_codePPC_string = "TRAP "; + `ExcpEnum_defaultEncoding_RFI : execute_SPRPLUGIN_opExcp_codePPC_string = "RFI "; + `ExcpEnum_defaultEncoding_RFSCV : execute_SPRPLUGIN_opExcp_codePPC_string = "RFSCV "; + `ExcpEnum_defaultEncoding_DSI : execute_SPRPLUGIN_opExcp_codePPC_string = "DSI "; + `ExcpEnum_defaultEncoding_DSI_PROT : execute_SPRPLUGIN_opExcp_codePPC_string = "DSI_PROT"; + `ExcpEnum_defaultEncoding_DSS : execute_SPRPLUGIN_opExcp_codePPC_string = "DSS "; + `ExcpEnum_defaultEncoding_ISI : execute_SPRPLUGIN_opExcp_codePPC_string = "ISI "; + `ExcpEnum_defaultEncoding_ISI_PROT : execute_SPRPLUGIN_opExcp_codePPC_string = "ISI_PROT"; + `ExcpEnum_defaultEncoding_ISS : execute_SPRPLUGIN_opExcp_codePPC_string = "ISS "; + `ExcpEnum_defaultEncoding_ALG : execute_SPRPLUGIN_opExcp_codePPC_string = "ALG "; + `ExcpEnum_defaultEncoding_PGM_ILL : execute_SPRPLUGIN_opExcp_codePPC_string = "PGM_ILL "; + `ExcpEnum_defaultEncoding_PGM_PRV : execute_SPRPLUGIN_opExcp_codePPC_string = "PGM_PRV "; + `ExcpEnum_defaultEncoding_FP : execute_SPRPLUGIN_opExcp_codePPC_string = "FP "; + `ExcpEnum_defaultEncoding_VEC : execute_SPRPLUGIN_opExcp_codePPC_string = "VEC "; + `ExcpEnum_defaultEncoding_VSX : execute_SPRPLUGIN_opExcp_codePPC_string = "VSX "; + `ExcpEnum_defaultEncoding_FAC : execute_SPRPLUGIN_opExcp_codePPC_string = "FAC "; + `ExcpEnum_defaultEncoding_SR : execute_SPRPLUGIN_opExcp_codePPC_string = "SR "; + `ExcpEnum_defaultEncoding_MC : execute_SPRPLUGIN_opExcp_codePPC_string = "MC "; + `ExcpEnum_defaultEncoding_EXT : execute_SPRPLUGIN_opExcp_codePPC_string = "EXT "; + `ExcpEnum_defaultEncoding_DEC : execute_SPRPLUGIN_opExcp_codePPC_string = "DEC "; + `ExcpEnum_defaultEncoding_TR : execute_SPRPLUGIN_opExcp_codePPC_string = "TR "; + `ExcpEnum_defaultEncoding_PM : execute_SPRPLUGIN_opExcp_codePPC_string = "PM "; + default : execute_SPRPLUGIN_opExcp_codePPC_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : decode_to_execute_DECODER_stageables_44_string = "IMM"; + `AluRimiAmtEnum_defaultEncoding_RB : decode_to_execute_DECODER_stageables_44_string = "RB "; + default : decode_to_execute_DECODER_stageables_44_string = "???"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : decode_to_execute_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : decode_to_execute_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : decode_to_execute_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : decode_to_execute_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : decode_to_execute_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : decode_to_execute_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : decode_to_execute_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : decode_to_execute_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : decode_to_execute_DECODER_stageables_49_string = "TWI "; + default : decode_to_execute_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(execute_to_memory_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : execute_to_memory_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : execute_to_memory_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : execute_to_memory_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : execute_to_memory_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : execute_to_memory_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : execute_to_memory_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : execute_to_memory_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : execute_to_memory_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : execute_to_memory_DECODER_stageables_49_string = "TWI "; + default : execute_to_memory_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_DECODER_stageables_49) + `EnvCtrlEnum_defaultEncoding_NONE : memory_to_writeBack_DECODER_stageables_49_string = "NONE "; + `EnvCtrlEnum_defaultEncoding_MFMSR : memory_to_writeBack_DECODER_stageables_49_string = "MFMSR"; + `EnvCtrlEnum_defaultEncoding_MTMSR : memory_to_writeBack_DECODER_stageables_49_string = "MTMSR"; + `EnvCtrlEnum_defaultEncoding_SC : memory_to_writeBack_DECODER_stageables_49_string = "SC "; + `EnvCtrlEnum_defaultEncoding_SCV : memory_to_writeBack_DECODER_stageables_49_string = "SCV "; + `EnvCtrlEnum_defaultEncoding_RFI : memory_to_writeBack_DECODER_stageables_49_string = "RFI "; + `EnvCtrlEnum_defaultEncoding_RFSCV : memory_to_writeBack_DECODER_stageables_49_string = "RFSCV"; + `EnvCtrlEnum_defaultEncoding_TW : memory_to_writeBack_DECODER_stageables_49_string = "TW "; + `EnvCtrlEnum_defaultEncoding_TWI : memory_to_writeBack_DECODER_stageables_49_string = "TWI "; + default : memory_to_writeBack_DECODER_stageables_49_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : decode_to_execute_DECODER_stageables_13_string = "NONE "; + `BranchCtrlEnum_defaultEncoding_BU : decode_to_execute_DECODER_stageables_13_string = "BU "; + `BranchCtrlEnum_defaultEncoding_BC : decode_to_execute_DECODER_stageables_13_string = "BC "; + `BranchCtrlEnum_defaultEncoding_BCLR : decode_to_execute_DECODER_stageables_13_string = "BCLR "; + `BranchCtrlEnum_defaultEncoding_BCCTR : decode_to_execute_DECODER_stageables_13_string = "BCCTR"; + `BranchCtrlEnum_defaultEncoding_BCTAR : decode_to_execute_DECODER_stageables_13_string = "BCTAR"; + default : decode_to_execute_DECODER_stageables_13_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_DECODER_stageables_20_string = "AND_1 "; + `CRLogCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_DECODER_stageables_20_string = "OR_1 "; + `CRLogCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_DECODER_stageables_20_string = "XOR_1 "; + `CRLogCtrlEnum_defaultEncoding_NAND_1 : decode_to_execute_DECODER_stageables_20_string = "NAND_1"; + `CRLogCtrlEnum_defaultEncoding_NOR_1 : decode_to_execute_DECODER_stageables_20_string = "NOR_1 "; + `CRLogCtrlEnum_defaultEncoding_EQV : decode_to_execute_DECODER_stageables_20_string = "EQV "; + `CRLogCtrlEnum_defaultEncoding_ANDC : decode_to_execute_DECODER_stageables_20_string = "ANDC "; + `CRLogCtrlEnum_defaultEncoding_ORC : decode_to_execute_DECODER_stageables_20_string = "ORC "; + default : decode_to_execute_DECODER_stageables_20_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : decode_to_execute_DECODER_stageables_16_string = "ROT "; + `AluRimiCtrlEnum_defaultEncoding_INS : decode_to_execute_DECODER_stageables_16_string = "INS "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : decode_to_execute_DECODER_stageables_16_string = "SHIFTL "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : decode_to_execute_DECODER_stageables_16_string = "SHIFTR "; + `AluRimiCtrlEnum_defaultEncoding_SHIFTRA : decode_to_execute_DECODER_stageables_16_string = "SHIFTRA"; + default : decode_to_execute_DECODER_stageables_16_string = "???????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : decode_to_execute_DECODER_stageables_0_string = "CNTLZW "; + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : decode_to_execute_DECODER_stageables_0_string = "CNTTZW "; + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : decode_to_execute_DECODER_stageables_0_string = "POPCNTB"; + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : decode_to_execute_DECODER_stageables_0_string = "POPCNTW"; + `AluSpecCtrlEnum_defaultEncoding_CMPB : decode_to_execute_DECODER_stageables_0_string = "CMPB "; + `AluSpecCtrlEnum_defaultEncoding_PRTYW : decode_to_execute_DECODER_stageables_0_string = "PRTYW "; + default : decode_to_execute_DECODER_stageables_0_string = "???????"; + endcase + end + always @(*) begin + case(execute_to_memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : execute_to_memory_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : execute_to_memory_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : execute_to_memory_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : execute_to_memory_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : execute_to_memory_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : execute_to_memory_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : execute_to_memory_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : execute_to_memory_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : execute_to_memory_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : execute_to_memory_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : execute_to_memory_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : execute_to_memory_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : execute_to_memory_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : execute_to_memory_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : execute_to_memory_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : execute_to_memory_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : execute_to_memory_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : execute_to_memory_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : execute_to_memory_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : execute_to_memory_CR_WRITE_op_string = "DECLNK"; + default : execute_to_memory_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(memory_to_writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_NOP : memory_to_writeBack_CR_WRITE_op_string = "NOP "; + `CRBusCmdEnum_defaultEncoding_CR0 : memory_to_writeBack_CR_WRITE_op_string = "CR0 "; + `CRBusCmdEnum_defaultEncoding_CR1 : memory_to_writeBack_CR_WRITE_op_string = "CR1 "; + `CRBusCmdEnum_defaultEncoding_CR6 : memory_to_writeBack_CR_WRITE_op_string = "CR6 "; + `CRBusCmdEnum_defaultEncoding_CMP : memory_to_writeBack_CR_WRITE_op_string = "CMP "; + `CRBusCmdEnum_defaultEncoding_AND_1 : memory_to_writeBack_CR_WRITE_op_string = "AND_1 "; + `CRBusCmdEnum_defaultEncoding_OR_1 : memory_to_writeBack_CR_WRITE_op_string = "OR_1 "; + `CRBusCmdEnum_defaultEncoding_XOR_1 : memory_to_writeBack_CR_WRITE_op_string = "XOR_1 "; + `CRBusCmdEnum_defaultEncoding_NAND_1 : memory_to_writeBack_CR_WRITE_op_string = "NAND_1"; + `CRBusCmdEnum_defaultEncoding_NOR_1 : memory_to_writeBack_CR_WRITE_op_string = "NOR_1 "; + `CRBusCmdEnum_defaultEncoding_EQV : memory_to_writeBack_CR_WRITE_op_string = "EQV "; + `CRBusCmdEnum_defaultEncoding_ANDC : memory_to_writeBack_CR_WRITE_op_string = "ANDC "; + `CRBusCmdEnum_defaultEncoding_ORC : memory_to_writeBack_CR_WRITE_op_string = "ORC "; + `CRBusCmdEnum_defaultEncoding_MCRF : memory_to_writeBack_CR_WRITE_op_string = "MCRF "; + `CRBusCmdEnum_defaultEncoding_MCRXRX : memory_to_writeBack_CR_WRITE_op_string = "MCRXRX"; + `CRBusCmdEnum_defaultEncoding_MTOCRF : memory_to_writeBack_CR_WRITE_op_string = "MTOCRF"; + `CRBusCmdEnum_defaultEncoding_MTCRF : memory_to_writeBack_CR_WRITE_op_string = "MTCRF "; + `CRBusCmdEnum_defaultEncoding_DEC : memory_to_writeBack_CR_WRITE_op_string = "DEC "; + `CRBusCmdEnum_defaultEncoding_LNK : memory_to_writeBack_CR_WRITE_op_string = "LNK "; + `CRBusCmdEnum_defaultEncoding_DECLNK : memory_to_writeBack_CR_WRITE_op_string = "DECLNK"; + default : memory_to_writeBack_CR_WRITE_op_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : decode_to_execute_DECODER_stageables_19_string = "AND_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : decode_to_execute_DECODER_stageables_19_string = "ANDC "; + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : decode_to_execute_DECODER_stageables_19_string = "OR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_ORC : decode_to_execute_DECODER_stageables_19_string = "ORC "; + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : decode_to_execute_DECODER_stageables_19_string = "XOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_XORC : decode_to_execute_DECODER_stageables_19_string = "XORC "; + `AluBitwiseCtrlEnum_defaultEncoding_EQV : decode_to_execute_DECODER_stageables_19_string = "EQV "; + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : decode_to_execute_DECODER_stageables_19_string = "NAND_1"; + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : decode_to_execute_DECODER_stageables_19_string = "NOR_1 "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : decode_to_execute_DECODER_stageables_19_string = "EXTSB "; + `AluBitwiseCtrlEnum_defaultEncoding_EXTSH : decode_to_execute_DECODER_stageables_19_string = "EXTSH "; + default : decode_to_execute_DECODER_stageables_19_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : decode_to_execute_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : decode_to_execute_MSR_ENDIAN_string = "LE"; + default : decode_to_execute_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(execute_to_memory_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : execute_to_memory_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : execute_to_memory_MSR_ENDIAN_string = "LE"; + default : execute_to_memory_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(memory_to_writeBack_MSR_ENDIAN) + `EndianEnum_defaultEncoding_BE : memory_to_writeBack_MSR_ENDIAN_string = "BE"; + `EndianEnum_defaultEncoding_LE : memory_to_writeBack_MSR_ENDIAN_string = "LE"; + default : memory_to_writeBack_MSR_ENDIAN_string = "??"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : decode_to_execute_DECODER_stageables_51_string = "MCRF "; + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : decode_to_execute_DECODER_stageables_51_string = "MCRXRX"; + `CRMoveCtrlEnum_defaultEncoding_MTCRF : decode_to_execute_DECODER_stageables_51_string = "MTCRF "; + default : decode_to_execute_DECODER_stageables_51_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : decode_to_execute_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : decode_to_execute_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : decode_to_execute_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : decode_to_execute_DECODER_stageables_7_string = "W "; + default : decode_to_execute_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(execute_to_memory_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : execute_to_memory_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : execute_to_memory_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : execute_to_memory_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : execute_to_memory_DECODER_stageables_7_string = "W "; + default : execute_to_memory_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(memory_to_writeBack_DECODER_stageables_7) + `DataSizeEnum_defaultEncoding_B : memory_to_writeBack_DECODER_stageables_7_string = "B "; + `DataSizeEnum_defaultEncoding_H : memory_to_writeBack_DECODER_stageables_7_string = "H "; + `DataSizeEnum_defaultEncoding_HA : memory_to_writeBack_DECODER_stageables_7_string = "HA"; + `DataSizeEnum_defaultEncoding_W : memory_to_writeBack_DECODER_stageables_7_string = "W "; + default : memory_to_writeBack_DECODER_stageables_7_string = "??"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : decode_to_execute_DECODER_stageables_1_string = "CA "; + `Src3CtrlEnum_defaultEncoding_CA_0 : decode_to_execute_DECODER_stageables_1_string = "CA_0"; + `Src3CtrlEnum_defaultEncoding_CA_1 : decode_to_execute_DECODER_stageables_1_string = "CA_1"; + default : decode_to_execute_DECODER_stageables_1_string = "????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_ADD : decode_to_execute_DECODER_stageables_8_string = "ADD "; + `AluCtrlEnum_defaultEncoding_BIT_1 : decode_to_execute_DECODER_stageables_8_string = "BIT_1"; + `AluCtrlEnum_defaultEncoding_RIMI : decode_to_execute_DECODER_stageables_8_string = "RIMI "; + `AluCtrlEnum_defaultEncoding_SPEC : decode_to_execute_DECODER_stageables_8_string = "SPEC "; + default : decode_to_execute_DECODER_stageables_8_string = "?????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : decode_to_execute_DECODER_stageables_26_string = "RB "; + `Src2CtrlEnum_defaultEncoding_RB_0 : decode_to_execute_DECODER_stageables_26_string = "RB_0 "; + `Src2CtrlEnum_defaultEncoding_RB_M1 : decode_to_execute_DECODER_stageables_26_string = "RB_M1 "; + `Src2CtrlEnum_defaultEncoding_RB_UI : decode_to_execute_DECODER_stageables_26_string = "RB_UI "; + `Src2CtrlEnum_defaultEncoding_RB_SI : decode_to_execute_DECODER_stageables_26_string = "RB_SI "; + `Src2CtrlEnum_defaultEncoding_RB_SH : decode_to_execute_DECODER_stageables_26_string = "RB_SH "; + `Src2CtrlEnum_defaultEncoding_RB_PCISD : decode_to_execute_DECODER_stageables_26_string = "RB_PCISD"; + `Src2CtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_26_string = "RA "; + default : decode_to_execute_DECODER_stageables_26_string = "????????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_38_string = "RA "; + `Src1CtrlEnum_defaultEncoding_RA_N : decode_to_execute_DECODER_stageables_38_string = "RA_N "; + `Src1CtrlEnum_defaultEncoding_RA_NIA : decode_to_execute_DECODER_stageables_38_string = "RA_NIA"; + `Src1CtrlEnum_defaultEncoding_RA_0 : decode_to_execute_DECODER_stageables_38_string = "RA_0 "; + `Src1CtrlEnum_defaultEncoding_RS : decode_to_execute_DECODER_stageables_38_string = "RS "; + default : decode_to_execute_DECODER_stageables_38_string = "??????"; + endcase + end + always @(*) begin + case(decode_to_execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : decode_to_execute_DECODER_stageables_12_string = "RT"; + `TgtCtrlEnum_defaultEncoding_RA : decode_to_execute_DECODER_stageables_12_string = "RA"; + default : decode_to_execute_DECODER_stageables_12_string = "??"; + endcase + end + `endif + + assign _zz_1_ = _zz_2_; + assign decode_DECODER_stageables_29 = _zz_447_[0]; + assign decode_DECODER_stageables_25 = _zz_448_[0]; + assign execute_NEXT_PC2 = (execute_PC + 32'h00000004); + assign execute_XER_SO = ALU2_XER[31]; + assign _zz_3_ = _zz_4_; + assign decode_DECODER_stageables_43 = _zz_449_[0]; + assign decode_DECODER_stageables_27 = _zz_450_[0]; + assign decode_CR_FIELD_RD = _zz_64_; + assign _zz_5_ = _zz_6_; + assign decode_DECODER_stageables_21 = _zz_451_[0]; + assign execute_DECODER_stageables_37 = decode_to_execute_DECODER_stageables_37; + assign decode_DECODER_stageables_37 = _zz_452_[0]; + assign decode_DECODER_stageables_8 = _zz_7_; + assign _zz_8_ = _zz_9_; + assign decode_DECODER_stageables_23 = _zz_453_[0]; + assign memory_SRC_ADD = execute_to_memory_SRC_ADD; + assign decode_DECODER_stageables_46 = _zz_454_[0]; + assign decode_DECODER_stageables_1 = _zz_10_; + assign _zz_11_ = _zz_12_; + assign execute_CR_FIELD_WR = _zz_75_; + assign memory_DECODER_stageables_7 = _zz_13_; + assign _zz_14_ = _zz_15_; + assign _zz_16_ = _zz_17_; + assign decode_DECODER_stageables_7 = _zz_18_; + assign _zz_19_ = _zz_20_; + assign decode_DECODER_stageables_51 = _zz_21_; + assign _zz_22_ = _zz_23_; + assign memory_DECODER_stageables_53 = execute_to_memory_DECODER_stageables_53; + assign execute_DECODER_stageables_53 = decode_to_execute_DECODER_stageables_53; + assign decode_DECODER_stageables_53 = _zz_455_[0]; + assign execute_MUL_HL = ($signed(MUL1_aHigh) * $signed(MUL1_bSLow)); + assign writeBack_REGFILE_WRITE_ADDR = memory_to_writeBack_REGFILE_WRITE_ADDR; + assign memory_REGFILE_WRITE_ADDR = execute_to_memory_REGFILE_WRITE_ADDR; + assign execute_REGFILE_WRITE_ADDR = _zz_263_; + assign decode_DECODER_stageables_35 = _zz_456_[0]; + assign execute_TARGET_MISSMATCH2 = (decode_PC != execute_BRANCH_CALC); + assign execute_DECODER_stageables_31 = decode_to_execute_DECODER_stageables_31; + assign decode_DECODER_stageables_31 = _zz_457_[0]; + assign execute_MUL_LH = ($signed(MUL1_aSLow) * $signed(MUL1_bHigh)); + assign decode_DECODER_stageables_40 = _zz_458_[0]; + assign decode_DECODER_stageables_2 = _zz_459_[0]; + assign execute_RA = decode_to_execute_RA; + assign decode_DECODER_stageables_3 = _zz_460_[0]; + assign decode_DECODER_stageables_14 = _zz_461_[0]; + assign memory_SRC1 = execute_to_memory_SRC1; + assign memory_MSR_ENDIAN = _zz_24_; + assign _zz_25_ = _zz_26_; + assign _zz_27_ = _zz_28_; + assign _zz_29_ = _zz_30_; + assign memory_DECODER_stageables_24 = execute_to_memory_DECODER_stageables_24; + assign execute_DECODER_stageables_24 = decode_to_execute_DECODER_stageables_24; + assign decode_DECODER_stageables_24 = _zz_462_[0]; + assign decode_DECODER_stageables_34 = _zz_463_[0]; + assign decode_DECODER_stageables_18 = _zz_464_[0]; + assign decode_DECODER_stageables_19 = _zz_31_; + assign _zz_32_ = _zz_33_; + assign decode_DECODER_stageables_9 = _zz_465_[0]; + assign decode_DECODER_stageables_45 = _zz_466_[0]; + assign decode_RT_ADDR = _zz_240_; + assign decode_DECODER_stageables_42 = _zz_467_[0]; + assign memory_MUL_LOW = ($signed(_zz_468_) + $signed(_zz_476_)); + assign _zz_34_ = _zz_35_; + assign execute_CR_WRITE_op = _zz_36_; + assign execute_CR_WRITE_ba = ALU2_crBus_ba; + assign execute_CR_WRITE_bb = ALU2_crBus_bb; + assign execute_CR_WRITE_bt = ALU2_crBus_bt; + assign execute_CR_WRITE_imm = ALU2_crBus_imm; + assign execute_CR_WRITE_fxm = ALU2_crBus_fxm; + assign _zz_37_ = _zz_38_; + assign execute_DECODER_stageables_5 = decode_to_execute_DECODER_stageables_5; + assign decode_DECODER_stageables_5 = _zz_477_[0]; + assign execute_DECODER_stageables_15 = decode_to_execute_DECODER_stageables_15; + assign decode_DECODER_stageables_15 = _zz_478_[0]; + assign decode_DECODER_stageables_0 = _zz_39_; + assign _zz_40_ = _zz_41_; + assign execute_BRANCH_LINK = _zz_336_; + assign execute_BRANCH_DO = _zz_334_; + assign memory_DECODER_stageables_39 = execute_to_memory_DECODER_stageables_39; + assign execute_DECODER_stageables_39 = decode_to_execute_DECODER_stageables_39; + assign decode_DECODER_stageables_39 = _zz_479_[0]; + assign memory_DECODER_stageables_56 = execute_to_memory_DECODER_stageables_56; + assign decode_DECODER_stageables_56 = _zz_480_[0]; + assign decode_DECODER_stageables_16 = _zz_42_; + assign _zz_43_ = _zz_44_; + assign decode_DECODER_stageables_11 = _zz_481_[0]; + assign execute_XER_CA = (ALU2_XER[29] ? 1'b1 : 1'b0); + assign writeBack_LOAD_UPDATE_ADDR = memory_to_writeBack_LOAD_UPDATE_ADDR; + assign memory_LOAD_UPDATE_ADDR = execute_to_memory_LOAD_UPDATE_ADDR; + assign execute_LOAD_UPDATE_ADDR = execute_R0_ADDR; + assign execute_MUL_LL = (MUL1_aULow * MUL1_bULow); + assign writeBack_FORMAL_PC_NEXT = memory_to_writeBack_FORMAL_PC_NEXT; + assign memory_FORMAL_PC_NEXT = execute_to_memory_FORMAL_PC_NEXT; + assign execute_FORMAL_PC_NEXT = decode_to_execute_FORMAL_PC_NEXT; + assign decode_FORMAL_PC_NEXT = (decode_PC + 32'h00000004); + assign decode_DECODER_stageables_22 = _zz_482_[0]; + assign memory_MEMORY_ADDRESS_LOW = execute_to_memory_MEMORY_ADDRESS_LOW; + assign execute_MEMORY_ADDRESS_LOW = _zz_378_[1 : 0]; + assign decode_DECODER_stageables_32 = _zz_483_[0]; + assign decode_DECODER_stageables_54 = _zz_484_[0]; + assign execute_REGFILE_WRITE_DATA = _zz_124_; + assign decode_DECODER_stageables_20 = _zz_45_; + assign _zz_46_ = _zz_47_; + assign decode_DECODER_stageables_57 = _zz_485_[0]; + assign memory_DECODER_stageables_55 = execute_to_memory_DECODER_stageables_55; + assign execute_DECODER_stageables_55 = decode_to_execute_DECODER_stageables_55; + assign decode_DECODER_stageables_55 = _zz_486_[0]; + assign _zz_48_ = _zz_49_; + assign writeBack_LOAD_UPDATE_DATA = memory_to_writeBack_LOAD_UPDATE_DATA; + assign memory_LOAD_UPDATE_DATA = execute_to_memory_LOAD_UPDATE_DATA; + assign execute_LOAD_UPDATE_DATA = execute_SRC_ADD; + assign execute_XER_WRITE_validOV = ALU2_xerBus_validOV; + assign execute_XER_WRITE_validCA = ALU2_xerBus_validCA; + assign execute_XER_WRITE_imm = ALU2_xerBus_imm; + assign decode_DECODER_stageables_48 = _zz_487_[0]; + assign memory_DECODER_stageables_49 = _zz_50_; + assign _zz_51_ = _zz_52_; + assign decode_DECODER_stageables_49 = _zz_53_; + assign _zz_54_ = _zz_55_; + assign execute_PREDICTION_CONTEXT_hazard = decode_to_execute_PREDICTION_CONTEXT_hazard; + assign execute_PREDICTION_CONTEXT_hit = decode_to_execute_PREDICTION_CONTEXT_hit; + assign execute_PREDICTION_CONTEXT_line_source = decode_to_execute_PREDICTION_CONTEXT_line_source; + assign execute_PREDICTION_CONTEXT_line_branchWish = decode_to_execute_PREDICTION_CONTEXT_line_branchWish; + assign execute_PREDICTION_CONTEXT_line_target = decode_to_execute_PREDICTION_CONTEXT_line_target; + assign decode_PREDICTION_CONTEXT_hazard = IBusCachedPlugin_predictor_injectorContext_hazard; + assign decode_PREDICTION_CONTEXT_hit = IBusCachedPlugin_predictor_injectorContext_hit; + assign decode_PREDICTION_CONTEXT_line_source = IBusCachedPlugin_predictor_injectorContext_line_source; + assign decode_PREDICTION_CONTEXT_line_branchWish = IBusCachedPlugin_predictor_injectorContext_line_branchWish; + assign decode_PREDICTION_CONTEXT_line_target = IBusCachedPlugin_predictor_injectorContext_line_target; + assign memory_DECODER_stageables_36 = execute_to_memory_DECODER_stageables_36; + assign execute_DECODER_stageables_36 = decode_to_execute_DECODER_stageables_36; + assign decode_DECODER_stageables_36 = _zz_488_[0]; + assign decode_DECODER_stageables_44 = _zz_56_; + assign _zz_57_ = _zz_58_; + assign decode_DECODER_stageables_28 = _zz_489_[0]; + assign memory_MUL_HH = execute_to_memory_MUL_HH; + assign execute_MUL_HH = ($signed(MUL1_aHigh) * $signed(MUL1_bHigh)); + assign execute_RB = decode_to_execute_RB; + assign writeBack_DECODER_stageables_49 = _zz_59_; + assign writeBack_DECODER_stageables_39 = memory_to_writeBack_DECODER_stageables_39; + assign execute_DECODER_stageables_40 = decode_to_execute_DECODER_stageables_40; + assign execute_DECODER_stageables_30 = decode_to_execute_DECODER_stageables_30; + always @ (*) begin + _zz_60_ = _zz_61_; + if(execute_arbitration_isValid)begin + if(_zz_394_)begin + if((! execute_SPRPLUGIN_trap))begin + _zz_60_ = `EnvCtrlEnum_defaultEncoding_NONE; + end + end + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_TWI))begin + if((! _zz_348_))begin + _zz_60_ = `EnvCtrlEnum_defaultEncoding_NONE; + end + end + end + end + + assign execute_DECODER_stageables_49 = _zz_62_; + assign writeBack_SRC_ADD = memory_to_writeBack_SRC_ADD; + assign memory_NEXT_PC2 = execute_to_memory_NEXT_PC2; + assign memory_PC = execute_to_memory_PC; + assign memory_BRANCH_CALC = execute_to_memory_BRANCH_CALC; + assign memory_TARGET_MISSMATCH2 = execute_to_memory_TARGET_MISSMATCH2; + assign memory_BRANCH_DO = execute_to_memory_BRANCH_DO; + assign execute_BRANCH_CALC = execute_BranchPlugin_branchAdder; + assign execute_PC = decode_to_execute_PC; + assign decode_DECODER_stageables_6 = _zz_490_[0]; + assign decode_DECODER_stageables_13 = _zz_65_; + assign writeBack_CR_FIELD_WR = memory_to_writeBack_CR_FIELD_WR; + assign execute_BRANCH_DEC = _zz_335_; + assign execute_DECODER_stageables_32 = decode_to_execute_DECODER_stageables_32; + assign memory_BRANCH_DEC = execute_to_memory_BRANCH_DEC; + assign memory_BRANCH_LINK = execute_to_memory_BRANCH_LINK; + assign memory_SPR_ID = execute_to_memory_SPR_ID; + assign memory_DECODER_stageables_32 = execute_to_memory_DECODER_stageables_32; + assign memory_XER_WRITE_validOV = execute_to_memory_XER_WRITE_validOV; + assign memory_XER_WRITE_validCA = execute_to_memory_XER_WRITE_validCA; + assign memory_XER_WRITE_imm = execute_to_memory_XER_WRITE_imm; + assign memory_CR_WRITE_op = _zz_66_; + assign memory_CR_WRITE_ba = execute_to_memory_CR_WRITE_ba; + assign memory_CR_WRITE_bb = execute_to_memory_CR_WRITE_bb; + assign memory_CR_WRITE_bt = execute_to_memory_CR_WRITE_bt; + assign memory_CR_WRITE_imm = execute_to_memory_CR_WRITE_imm; + assign memory_CR_WRITE_fxm = execute_to_memory_CR_WRITE_fxm; + assign memory_DECODER_stageables_31 = execute_to_memory_DECODER_stageables_31; + assign execute_DECODER_stageables_13 = _zz_67_; + assign execute_CR_FIELD_RD = decode_to_execute_CR_FIELD_RD; + assign memory_CR_FIELD_WR = execute_to_memory_CR_FIELD_WR; + always @ (*) begin + _zz_68_ = execute_REGFILE_WRITE_DATA; + if(execute_SPRPLUGIN_readInstruction)begin + _zz_68_ = execute_SPRPLUGIN_readData; + end + end + + assign execute_DECODER_stageables_45 = decode_to_execute_DECODER_stageables_45; + assign execute_RT_ADDR = decode_to_execute_RT_ADDR; + assign execute_DECODER_stageables_25 = decode_to_execute_DECODER_stageables_25; + assign memory_DECODER_stageables_45 = execute_to_memory_DECODER_stageables_45; + assign memory_RT_ADDR = execute_to_memory_RT_ADDR; + assign memory_DECODER_stageables_5 = execute_to_memory_DECODER_stageables_5; + assign decode_DECODER_stageables_50 = _zz_491_[0]; + assign decode_DECODER_stageables_47 = _zz_492_[0]; + assign decode_DECODER_stageables_10 = _zz_493_[0]; + assign writeBack_DECODER_stageables_45 = memory_to_writeBack_DECODER_stageables_45; + assign writeBack_RT_ADDR = memory_to_writeBack_RT_ADDR; + always @ (*) begin + decode_RS = decode_RegFilePlugin_rsData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr2Match)begin + decode_RS = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if((_zz_289_ && 1'b1))begin + decode_RS = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if((_zz_292_ && 1'b1))begin + decode_RS = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if((_zz_295_ && 1'b1))begin + decode_RS = _zz_68_; + end + end + end + end + + always @ (*) begin + decode_RB = decode_RegFilePlugin_rbData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr1Match)begin + decode_RB = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if(_zz_288_)begin + decode_RB = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if(_zz_291_)begin + decode_RB = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if(_zz_294_)begin + decode_RB = _zz_68_; + end + end + end + end + + always @ (*) begin + decode_RA = decode_RegFilePlugin_raData; + if(Hazards_writeBackBuffer_valid)begin + if(Hazards_addr0Match)begin + decode_RA = Hazards_writeBackBuffer_payload_data; + end + end + if(_zz_395_)begin + if(_zz_396_)begin + if(_zz_287_)begin + decode_RA = _zz_121_; + end + end + end + if(_zz_397_)begin + if(memory_DECODER_stageables_5)begin + if(_zz_290_)begin + decode_RA = _zz_69_; + end + end + end + if(_zz_398_)begin + if(execute_DECODER_stageables_25)begin + if(_zz_293_)begin + decode_RA = _zz_68_; + end + end + end + end + + assign decode_R2_ADDR = decode_INSTRUCTION[25 : 21]; + assign decode_R1_ADDR = _zz_239_; + assign decode_R0_ADDR = _zz_238_; + assign execute_DECODER_stageables_29 = decode_to_execute_DECODER_stageables_29; + assign execute_DECODER_stageables_43 = decode_to_execute_DECODER_stageables_43; + assign execute_DECODER_stageables_3 = decode_to_execute_DECODER_stageables_3; + assign memory_SRC_CR = execute_to_memory_SRC_CR; + assign memory_XER_SO = execute_to_memory_XER_SO; + assign memory_INSTRUCTION = execute_to_memory_INSTRUCTION; + assign memory_DECODER_stageables_37 = execute_to_memory_DECODER_stageables_37; + always @ (*) begin + _zz_69_ = memory_REGFILE_WRITE_DATA; + if(_zz_399_)begin + _zz_69_ = MULDIV1_result; + end + end + + assign memory_DECODER_stageables_15 = execute_to_memory_DECODER_stageables_15; + assign memory_DECODER_stageables_43 = execute_to_memory_DECODER_stageables_43; + assign writeBack_DECODER_stageables_31 = memory_to_writeBack_DECODER_stageables_31; + assign writeBack_DECODER_stageables_24 = memory_to_writeBack_DECODER_stageables_24; + assign writeBack_SRC_CR = memory_to_writeBack_SRC_CR; + assign writeBack_DECODER_stageables_55 = memory_to_writeBack_DECODER_stageables_55; + assign writeBack_XER_SO = memory_to_writeBack_XER_SO; + assign writeBack_DECODER_stageables_36 = memory_to_writeBack_DECODER_stageables_36; + assign writeBack_MUL_HH = memory_to_writeBack_MUL_HH; + assign writeBack_MUL_LOW = memory_to_writeBack_MUL_LOW; + assign memory_MUL_HL = execute_to_memory_MUL_HL; + assign memory_MUL_LH = execute_to_memory_MUL_LH; + assign memory_MUL_LL = execute_to_memory_MUL_LL; + assign execute_DECODER_stageables_35 = decode_to_execute_DECODER_stageables_35; + assign memory_DECODER_stageables_9 = execute_to_memory_DECODER_stageables_9; + assign execute_DECODER_stageables_9 = decode_to_execute_DECODER_stageables_9; + assign writeBack_DECODER_stageables_9 = memory_to_writeBack_DECODER_stageables_9; + assign execute_DECODER_stageables_48 = decode_to_execute_DECODER_stageables_48; + assign execute_SRC3 = _zz_268_; + assign execute_DECODER_stageables_1 = _zz_70_; + assign execute_DECODER_stageables_26 = _zz_71_; + assign _zz_72_ = execute_PC; + assign _zz_73_ = execute_RA; + assign execute_DECODER_stageables_38 = _zz_74_; + assign decode_DECODER_stageables_17 = _zz_494_[0]; + assign execute_DECODER_stageables_20 = _zz_77_; + assign execute_DECODER_stageables_51 = _zz_78_; + assign execute_DECODER_stageables_46 = decode_to_execute_DECODER_stageables_46; + assign execute_DECODER_stageables_34 = decode_to_execute_DECODER_stageables_34; + assign execute_DECODER_stageables_28 = decode_to_execute_DECODER_stageables_28; + assign execute_DECODER_stageables_57 = decode_to_execute_DECODER_stageables_57; + assign execute_DECODER_stageables_21 = decode_to_execute_DECODER_stageables_21; + assign execute_SRC_CR = (execute_DECODER_stageables_21 ? SRC2_cmp_cr : SRC2_add_cr); + assign execute_DECODER_stageables_11 = decode_to_execute_DECODER_stageables_11; + assign execute_DECODER_stageables_18 = decode_to_execute_DECODER_stageables_18; + assign execute_SRC_CAOV = {SRC2_ca,SRC2_ov}; + assign execute_DECODER_stageables_14 = decode_to_execute_DECODER_stageables_14; + assign execute_DECODER_stageables_6 = decode_to_execute_DECODER_stageables_6; + assign execute_R0_ADDR = decode_to_execute_R0_ADDR; + assign execute_DECODER_stageables_12 = _zz_80_; + assign execute_DECODER_stageables_8 = _zz_81_; + assign execute_DECODER_stageables_27 = decode_to_execute_DECODER_stageables_27; + assign execute_DECODER_stageables_2 = decode_to_execute_DECODER_stageables_2; + assign execute_DECODER_stageables_23 = decode_to_execute_DECODER_stageables_23; + assign execute_DECODER_stageables_0 = _zz_82_; + always @ (*) begin + _zz_83_ = _zz_83__30; + if(_zz_258_[31])begin + _zz_83_ = (_zz_83__30 + 6'h01); + end + end + + always @ (*) begin + _zz_83__30 = _zz_83__29; + if(_zz_258_[30])begin + _zz_83__30 = (_zz_83__29 + 6'h01); + end + end + + always @ (*) begin + _zz_83__29 = _zz_83__28; + if(_zz_258_[29])begin + _zz_83__29 = (_zz_83__28 + 6'h01); + end + end + + always @ (*) begin + _zz_83__28 = _zz_83__27; + if(_zz_258_[28])begin + _zz_83__28 = (_zz_83__27 + 6'h01); + end + end + + always @ (*) begin + _zz_83__27 = _zz_83__26; + if(_zz_258_[27])begin + _zz_83__27 = (_zz_83__26 + 6'h01); + end + end + + always @ (*) begin + _zz_83__26 = _zz_83__25; + if(_zz_258_[26])begin + _zz_83__26 = (_zz_83__25 + 6'h01); + end + end + + always @ (*) begin + _zz_83__25 = _zz_83__24; + if(_zz_258_[25])begin + _zz_83__25 = (_zz_83__24 + 6'h01); + end + end + + always @ (*) begin + _zz_83__24 = _zz_83__23; + if(_zz_258_[24])begin + _zz_83__24 = (_zz_83__23 + 6'h01); + end + end + + always @ (*) begin + _zz_83__23 = _zz_83__22; + if(_zz_258_[23])begin + _zz_83__23 = (_zz_83__22 + 6'h01); + end + end + + always @ (*) begin + _zz_83__22 = _zz_83__21; + if(_zz_258_[22])begin + _zz_83__22 = (_zz_83__21 + 6'h01); + end + end + + always @ (*) begin + _zz_83__21 = _zz_83__20; + if(_zz_258_[21])begin + _zz_83__21 = (_zz_83__20 + 6'h01); + end + end + + always @ (*) begin + _zz_83__20 = _zz_83__19; + if(_zz_258_[20])begin + _zz_83__20 = (_zz_83__19 + 6'h01); + end + end + + always @ (*) begin + _zz_83__19 = _zz_83__18; + if(_zz_258_[19])begin + _zz_83__19 = (_zz_83__18 + 6'h01); + end + end + + always @ (*) begin + _zz_83__18 = _zz_83__17; + if(_zz_258_[18])begin + _zz_83__18 = (_zz_83__17 + 6'h01); + end + end + + always @ (*) begin + _zz_83__17 = _zz_83__16; + if(_zz_258_[17])begin + _zz_83__17 = (_zz_83__16 + 6'h01); + end + end + + always @ (*) begin + _zz_83__16 = _zz_83__15; + if(_zz_258_[16])begin + _zz_83__16 = (_zz_83__15 + 6'h01); + end + end + + always @ (*) begin + _zz_83__15 = _zz_83__14; + if(_zz_258_[15])begin + _zz_83__15 = (_zz_83__14 + 6'h01); + end + end + + always @ (*) begin + _zz_83__14 = _zz_83__13; + if(_zz_258_[14])begin + _zz_83__14 = (_zz_83__13 + 6'h01); + end + end + + always @ (*) begin + _zz_83__13 = _zz_83__12; + if(_zz_258_[13])begin + _zz_83__13 = (_zz_83__12 + 6'h01); + end + end + + always @ (*) begin + _zz_83__12 = _zz_83__11; + if(_zz_258_[12])begin + _zz_83__12 = (_zz_83__11 + 6'h01); + end + end + + always @ (*) begin + _zz_83__11 = _zz_83__10; + if(_zz_258_[11])begin + _zz_83__11 = (_zz_83__10 + 6'h01); + end + end + + always @ (*) begin + _zz_83__10 = _zz_83__9; + if(_zz_258_[10])begin + _zz_83__10 = (_zz_83__9 + 6'h01); + end + end + + always @ (*) begin + _zz_83__9 = _zz_83__8; + if(_zz_258_[9])begin + _zz_83__9 = (_zz_83__8 + 6'h01); + end + end + + always @ (*) begin + _zz_83__8 = _zz_83__7; + if(_zz_258_[8])begin + _zz_83__8 = (_zz_83__7 + 6'h01); + end + end + + always @ (*) begin + _zz_83__7 = _zz_83__6; + if(_zz_258_[7])begin + _zz_83__7 = (_zz_83__6 + 6'h01); + end + end + + always @ (*) begin + _zz_83__6 = _zz_83__5; + if(_zz_258_[6])begin + _zz_83__6 = (_zz_83__5 + 6'h01); + end + end + + always @ (*) begin + _zz_83__5 = _zz_83__4; + if(_zz_258_[5])begin + _zz_83__5 = (_zz_83__4 + 6'h01); + end + end + + always @ (*) begin + _zz_83__4 = _zz_83__3; + if(_zz_258_[4])begin + _zz_83__4 = (_zz_83__3 + 6'h01); + end + end + + always @ (*) begin + _zz_83__3 = _zz_83__2; + if(_zz_258_[3])begin + _zz_83__3 = (_zz_83__2 + 6'h01); + end + end + + always @ (*) begin + _zz_83__2 = _zz_83__1; + if(_zz_258_[2])begin + _zz_83__2 = (_zz_83__1 + 6'h01); + end + end + + always @ (*) begin + _zz_83__1 = _zz_83__0; + if(_zz_258_[1])begin + _zz_83__1 = (_zz_83__0 + 6'h01); + end + end + + always @ (*) begin + _zz_83__0 = 6'h0; + if(_zz_258_[0])begin + _zz_83__0 = (6'h0 + 6'h01); + end + end + + always @ (*) begin + _zz_84_ = _zz_84__6; + if(_zz_257_[7])begin + _zz_84_ = (_zz_84__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__6 = _zz_84__5; + if(_zz_257_[6])begin + _zz_84__6 = (_zz_84__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__5 = _zz_84__4; + if(_zz_257_[5])begin + _zz_84__5 = (_zz_84__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__4 = _zz_84__3; + if(_zz_257_[4])begin + _zz_84__4 = (_zz_84__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__3 = _zz_84__2; + if(_zz_257_[3])begin + _zz_84__3 = (_zz_84__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__2 = _zz_84__1; + if(_zz_257_[2])begin + _zz_84__2 = (_zz_84__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__1 = _zz_84__0; + if(_zz_257_[1])begin + _zz_84__1 = (_zz_84__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_84__0 = (4'b0000); + if(_zz_257_[0])begin + _zz_84__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_85_ = _zz_85__6; + if(_zz_256_[7])begin + _zz_85_ = (_zz_85__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__6 = _zz_85__5; + if(_zz_256_[6])begin + _zz_85__6 = (_zz_85__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__5 = _zz_85__4; + if(_zz_256_[5])begin + _zz_85__5 = (_zz_85__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__4 = _zz_85__3; + if(_zz_256_[4])begin + _zz_85__4 = (_zz_85__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__3 = _zz_85__2; + if(_zz_256_[3])begin + _zz_85__3 = (_zz_85__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__2 = _zz_85__1; + if(_zz_256_[2])begin + _zz_85__2 = (_zz_85__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__1 = _zz_85__0; + if(_zz_256_[1])begin + _zz_85__1 = (_zz_85__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_85__0 = (4'b0000); + if(_zz_256_[0])begin + _zz_85__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_86_ = _zz_86__6; + if(_zz_255_[7])begin + _zz_86_ = (_zz_86__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__6 = _zz_86__5; + if(_zz_255_[6])begin + _zz_86__6 = (_zz_86__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__5 = _zz_86__4; + if(_zz_255_[5])begin + _zz_86__5 = (_zz_86__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__4 = _zz_86__3; + if(_zz_255_[4])begin + _zz_86__4 = (_zz_86__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__3 = _zz_86__2; + if(_zz_255_[3])begin + _zz_86__3 = (_zz_86__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__2 = _zz_86__1; + if(_zz_255_[2])begin + _zz_86__2 = (_zz_86__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__1 = _zz_86__0; + if(_zz_255_[1])begin + _zz_86__1 = (_zz_86__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_86__0 = (4'b0000); + if(_zz_255_[0])begin + _zz_86__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_87_ = _zz_87__6; + if(_zz_254_[7])begin + _zz_87_ = (_zz_87__6 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__6 = _zz_87__5; + if(_zz_254_[6])begin + _zz_87__6 = (_zz_87__5 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__5 = _zz_87__4; + if(_zz_254_[5])begin + _zz_87__5 = (_zz_87__4 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__4 = _zz_87__3; + if(_zz_254_[4])begin + _zz_87__4 = (_zz_87__3 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__3 = _zz_87__2; + if(_zz_254_[3])begin + _zz_87__3 = (_zz_87__2 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__2 = _zz_87__1; + if(_zz_254_[2])begin + _zz_87__2 = (_zz_87__1 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__1 = _zz_87__0; + if(_zz_254_[1])begin + _zz_87__1 = (_zz_87__0 + (4'b0001)); + end + end + + always @ (*) begin + _zz_87__0 = (4'b0000); + if(_zz_254_[0])begin + _zz_87__0 = ((4'b0000) + (4'b0001)); + end + end + + always @ (*) begin + _zz_88_ = _zz_89_; + _zz_88_ = (ALU2_amount[4] ? {_zz_89_[15 : 0],_zz_89_[31 : 16]} : _zz_89_); + end + + always @ (*) begin + _zz_89_ = _zz_90_; + _zz_89_ = (ALU2_amount[3] ? {_zz_90_[23 : 0],_zz_90_[31 : 24]} : _zz_90_); + end + + always @ (*) begin + _zz_90_ = _zz_91_; + _zz_90_ = (ALU2_amount[2] ? {_zz_91_[27 : 0],_zz_91_[31 : 28]} : _zz_91_); + end + + always @ (*) begin + _zz_91_ = _zz_92_; + _zz_91_ = (ALU2_amount[1] ? {_zz_92_[29 : 0],_zz_92_[31 : 30]} : _zz_92_); + end + + always @ (*) begin + _zz_92_ = _zz_251_; + _zz_92_ = (ALU2_amount[0] ? {_zz_251_[30 : 0],_zz_251_[31 : 31]} : _zz_251_); + end + + always @ (*) begin + _zz_93_ = _zz_94_; + _zz_93_ = (ALU2_amount[4] ? {_zz_94_[15 : 0],_zz_94_[31 : 16]} : _zz_94_); + end + + always @ (*) begin + _zz_94_ = _zz_95_; + _zz_94_ = (ALU2_amount[3] ? {_zz_95_[23 : 0],_zz_95_[31 : 24]} : _zz_95_); + end + + always @ (*) begin + _zz_95_ = _zz_96_; + _zz_95_ = (ALU2_amount[2] ? {_zz_96_[27 : 0],_zz_96_[31 : 28]} : _zz_96_); + end + + always @ (*) begin + _zz_96_ = _zz_97_; + _zz_96_ = (ALU2_amount[1] ? {_zz_97_[29 : 0],_zz_97_[31 : 30]} : _zz_97_); + end + + always @ (*) begin + _zz_97_ = _zz_250_; + _zz_97_ = (ALU2_amount[0] ? {_zz_250_[30 : 0],_zz_250_[31 : 31]} : _zz_250_); + end + + assign execute_DECODER_stageables_16 = _zz_98_; + assign execute_DECODER_stageables_44 = _zz_99_; + assign execute_SRC2 = _zz_267_; + assign execute_SRC1 = _zz_264_; + assign execute_DECODER_stageables_19 = _zz_100_; + assign execute_DECODER_stageables_54 = decode_to_execute_DECODER_stageables_54; + assign execute_SPR_ID = _zz_79_; + assign writeBack_SRC1 = memory_to_writeBack_SRC1; + assign writeBack_DECODER_stageables_32 = memory_to_writeBack_DECODER_stageables_32; + assign writeBack_SPR_ID = memory_to_writeBack_SPR_ID; + assign writeBack_XER_WRITE_validOV = memory_to_writeBack_XER_WRITE_validOV; + assign writeBack_XER_WRITE_validCA = memory_to_writeBack_XER_WRITE_validCA; + assign writeBack_XER_WRITE_imm = memory_to_writeBack_XER_WRITE_imm; + assign writeBack_BRANCH_LINK = memory_to_writeBack_BRANCH_LINK; + assign writeBack_BRANCH_DEC = memory_to_writeBack_BRANCH_DEC; + assign writeBack_CR_WRITE_op = _zz_101_; + assign writeBack_CR_WRITE_ba = memory_to_writeBack_CR_WRITE_ba; + assign writeBack_CR_WRITE_bb = memory_to_writeBack_CR_WRITE_bb; + assign writeBack_CR_WRITE_bt = memory_to_writeBack_CR_WRITE_bt; + assign writeBack_CR_WRITE_imm = memory_to_writeBack_CR_WRITE_imm; + assign writeBack_CR_WRITE_fxm = memory_to_writeBack_CR_WRITE_fxm; + assign _zz_102_ = writeBack_DECODER_stageables_45; + always @ (*) begin + _zz_103_ = 1'b0; + if(lastStageRegFileWrite_valid)begin + _zz_103_ = 1'b1; + end + end + + assign decode_DECODER_stageables_12 = _zz_104_; + assign decode_DECODER_stageables_26 = _zz_105_; + assign decode_DECODER_stageables_38 = _zz_106_; + assign decode_INSTRUCTION_ANTICIPATED = _zz_128_; + assign decode = _zz_495_[0]; + assign decode_LEGAL_INSTRUCTION = ({_zz_221_,{((decode_INSTRUCTION & 32'h6c000000) == 32'h0c000000),{_zz_220_,{((decode_INSTRUCTION & 32'hb8000000) == 32'h28000000),{_zz_170_,{_zz_219_,{_zz_217_,{_zz_663_,_zz_664_}}}}}}}} != 101'h0); + always @ (*) begin + _zz_121_ = writeBack_REGFILE_WRITE_DATA; + if(((writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE) && (! writeBack_MEMORY_WR)))begin + _zz_121_ = writeBack_DBusCachedPlugin_rspFormated; + end + if(_zz_400_)begin + _zz_121_ = MUL3_result32; + end + end + + assign writeBack_SIGN_EXTEND = memory_to_writeBack_DECODER_stageables_53; + assign writeBack_DATA_SIZE = _zz_122_; + assign writeBack_MEMORY_ADDRESS_LOW = memory_to_writeBack_MEMORY_ADDRESS_LOW; + assign writeBack_MEMORY_WR = memory_to_writeBack_DECODER_stageables_56; + assign writeBack_MSR_ENDIAN = _zz_123_; + assign writeBack_REGFILE_WRITE_DATA = memory_to_writeBack_REGFILE_WRITE_DATA; + assign writeBack_MEMORY_ENABLE = memory_to_writeBack_DECODER_stageables_52; + assign memory_REGFILE_WRITE_DATA = execute_to_memory_REGFILE_WRITE_DATA; + assign memory_MEMORY_ENABLE = execute_to_memory_DECODER_stageables_52; + assign execute_STORE_UPDATE = decode_to_execute_DECODER_stageables_42; + assign execute_MEMORY_MANAGMENT = decode_to_execute_DECODER_stageables_22; + assign execute_RS = decode_to_execute_RS; + assign execute_MEMORY_WR = decode_to_execute_DECODER_stageables_56; + assign execute_SRC_ADD = SRC2_adder[31 : 0]; + assign execute_MEMORY_ENABLE = decode_to_execute_DECODER_stageables_52; + assign execute_DATA_SIZE = _zz_125_; + assign execute_INSTRUCTION = decode_to_execute_INSTRUCTION; + assign execute_MSR_ENDIAN = _zz_126_; + assign decode_MEMORY_ENABLE = _zz_496_[0]; + assign decode_FLUSH_ALL = _zz_497_[0]; + always @ (*) begin + _zz_127_ = _zz_127__3; + if(_zz_401_)begin + _zz_127_ = 1'b1; + end + end + + always @ (*) begin + _zz_127__3 = _zz_127__2; + if(_zz_402_)begin + _zz_127__3 = 1'b1; + end + end + + always @ (*) begin + _zz_127__2 = _zz_127__1; + if(_zz_403_)begin + if(_zz_404_)begin + _zz_127__2 = 1'b1; + end + end + end + + always @ (*) begin + _zz_127__1 = _zz_127__0; + if(_zz_405_)begin + _zz_127__1 = 1'b1; + end + end + + always @ (*) begin + _zz_127__0 = IBusCachedPlugin_rsp_issueDetected; + if(_zz_406_)begin + _zz_127__0 = 1'b1; + end + end + + assign decode_INSTRUCTION = IBusCachedPlugin_iBusRsp_output_payload_rsp_inst; + assign decode_MSR_ENDIAN = _zz_129_; + assign memory_PREDICTION_CONTEXT_hazard = execute_to_memory_PREDICTION_CONTEXT_hazard; + assign memory_PREDICTION_CONTEXT_hit = execute_to_memory_PREDICTION_CONTEXT_hit; + assign memory_PREDICTION_CONTEXT_line_source = execute_to_memory_PREDICTION_CONTEXT_line_source; + assign memory_PREDICTION_CONTEXT_line_branchWish = execute_to_memory_PREDICTION_CONTEXT_line_branchWish; + assign memory_PREDICTION_CONTEXT_line_target = execute_to_memory_PREDICTION_CONTEXT_line_target; + always @ (*) begin + _zz_130_ = 1'b0; + if(IBusCachedPlugin_predictor_historyWriteDelayPatched_valid)begin + _zz_130_ = 1'b1; + end + end + + always @ (*) begin + _zz_131_ = memory_FORMAL_PC_NEXT; + if(BranchPlugin_jumpInterface_valid)begin + _zz_131_ = BranchPlugin_jumpInterface_payload; + end + end + + assign decode_PC = IBusCachedPlugin_iBusRsp_output_payload_pc; + assign writeBack_PC = memory_to_writeBack_PC; + assign writeBack_INSTRUCTION = memory_to_writeBack_INSTRUCTION; + always @ (*) begin + decode_arbitration_haltItself = 1'b0; + if(((DBusCachedPlugin_mmuBus_busy && decode_arbitration_isValid) && decode_MEMORY_ENABLE))begin + decode_arbitration_haltItself = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_haltByOther = 1'b0; + if(((((execute_arbitration_isValid && execute_DECODER_stageables_9) || (memory_arbitration_isValid && memory_DECODER_stageables_9)) || (writeBack_arbitration_isValid && writeBack_DECODER_stageables_9)) || _zz_269_))begin + decode_arbitration_haltByOther = 1'b1; + end + if((decode_arbitration_isValid && ((_zz_283_ || _zz_284_) || _zz_285_)))begin + decode_arbitration_haltByOther = 1'b1; + end + if(SPRPlugin_pipelineLiberator_active)begin + decode_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + decode_arbitration_removeIt = 1'b0; + if(_zz_407_)begin + decode_arbitration_removeIt = _zz_341_; + end + if(decode_arbitration_isFlushed)begin + decode_arbitration_removeIt = 1'b1; + end + end + + assign decode_arbitration_flushIt = 1'b0; + assign decode_arbitration_flushNext = 1'b0; + always @ (*) begin + execute_arbitration_haltItself = 1'b0; + if((_zz_387_ && (! dataCache_1__io_cpu_flush_ready)))begin + execute_arbitration_haltItself = 1'b1; + end + if(((dataCache_1__io_cpu_redo && execute_arbitration_isValid) && execute_MEMORY_ENABLE))begin + execute_arbitration_haltItself = 1'b1; + end + if((execute_SPRPLUGIN_readInstruction || execute_SPRPLUGIN_writeInstruction))begin + if(execute_SPRPLUGIN_blockedBySideEffects)begin + execute_arbitration_haltItself = 1'b1; + end + end + end + + always @ (*) begin + execute_arbitration_haltByOther = 1'b0; + if((_zz_296_ || _zz_312_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_298_ || _zz_314_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_299_ || _zz_315_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_297_ || _zz_313_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_300_ || _zz_316_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_301_ || _zz_317_))begin + execute_arbitration_haltByOther = 1'b1; + end + if((_zz_302_ || _zz_318_))begin + execute_arbitration_haltByOther = 1'b1; + end + end + + always @ (*) begin + execute_arbitration_removeIt = 1'b0; + if(SPRPlugin_selfException_valid)begin + execute_arbitration_removeIt = _zz_342_; + end + if(execute_arbitration_isFlushed)begin + execute_arbitration_removeIt = 1'b1; + end + end + + assign execute_arbitration_flushIt = 1'b0; + assign execute_arbitration_flushNext = 1'b0; + always @ (*) begin + memory_arbitration_haltItself = 1'b0; + if(_zz_399_)begin + if(((! MULDIV_frontendOk) || (! MULDIV1_done)))begin + memory_arbitration_haltItself = 1'b1; + end + end + end + + assign memory_arbitration_haltByOther = 1'b0; + always @ (*) begin + memory_arbitration_removeIt = 1'b0; + if(BranchPlugin_branchExceptionPort_valid)begin + memory_arbitration_removeIt = _zz_343_; + end + if(memory_arbitration_isFlushed)begin + memory_arbitration_removeIt = 1'b1; + end + end + + assign memory_arbitration_flushIt = 1'b0; + always @ (*) begin + memory_arbitration_flushNext = 1'b0; + if(BranchPlugin_jumpInterface_valid)begin + memory_arbitration_flushNext = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_haltItself = 1'b0; + if(dataCache_1__io_cpu_writeBack_haltIt)begin + writeBack_arbitration_haltItself = 1'b1; + end + end + + assign writeBack_arbitration_haltByOther = 1'b0; + always @ (*) begin + writeBack_arbitration_removeIt = 1'b0; + if(DBusCachedPlugin_exceptionBus_valid)begin + writeBack_arbitration_removeIt = _zz_344_; + end + if(writeBack_arbitration_isFlushed)begin + writeBack_arbitration_removeIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushIt = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushIt = 1'b1; + end + end + + always @ (*) begin + writeBack_arbitration_flushNext = 1'b0; + if(DBusCachedPlugin_redoBranch_valid)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_408_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_409_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_410_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_411_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_412_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_413_)begin + writeBack_arbitration_flushNext = 1'b1; + end + if(_zz_414_)begin + writeBack_arbitration_flushNext = 1'b1; + end + end + + assign lastStageInstruction = writeBack_INSTRUCTION; + assign lastStagePc = writeBack_PC; + assign lastStageIsValid = writeBack_arbitration_isValid; + assign lastStageIsFiring = writeBack_arbitration_isFiring; + always @ (*) begin + IBusCachedPlugin_fetcherHalt = 1'b0; + if(({SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack,{SPRPlugin_exceptionPortCtrl_exceptionValids_memory,{SPRPlugin_exceptionPortCtrl_exceptionValids_execute,SPRPlugin_exceptionPortCtrl_exceptionValids_decode}}} != (4'b0000)))begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_408_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_409_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_410_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_411_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_412_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_413_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + if(_zz_414_)begin + IBusCachedPlugin_fetcherHalt = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_incomingInstruction = 1'b0; + if((IBusCachedPlugin_iBusRsp_stages_1_input_valid || IBusCachedPlugin_iBusRsp_stages_2_input_valid))begin + IBusCachedPlugin_incomingInstruction = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = (5'bxxxxx); + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_ISI; + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_ISI_PROT; + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_MC; + end + end + + assign IBusCachedPlugin_decodeExceptionPort_payload_imm = 7'h0; + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_badAddr = 32'h0; + IBusCachedPlugin_decodeExceptionPort_payload_badAddr = {IBusCachedPlugin_iBusRsp_stages_2_input_payload[31 : 2],(2'b00)}; + end + + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_codePPC = (5'bxxxxx); + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_MC; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI_PROT; + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI_PROT; + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_ALG; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_codePPC = `ExcpEnum_defaultEncoding_DSI; + end + end + end + + assign DBusCachedPlugin_exceptionBus_payload_imm = 7'h0; + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_badAddr = 32'h0; + DBusCachedPlugin_exceptionBus_payload_badAddr = writeBack_PC; + end + + always @ (*) begin + decodeExceptionPort_payload_codePPC = (5'bxxxxx); + decodeExceptionPort_payload_codePPC = (5'bxxxxx); + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_ILL; + end + if(_zz_420_)begin + decodeExceptionPort_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_PRV; + end + end + end + + assign decodeExceptionPort_payload_imm = 7'h0; + always @ (*) begin + decodeExceptionPort_payload_badAddr = 32'h0; + decodeExceptionPort_payload_badAddr = 32'h0; + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_badAddr = decode_PC; + end + if(_zz_420_)begin + decodeExceptionPort_payload_badAddr = decode_PC; + end + end + end + + assign BranchPlugin_branchExceptionPort_payload_codePPC = (5'bxxxxx); + assign BranchPlugin_branchExceptionPort_payload_imm = 7'h0; + always @ (*) begin + BranchPlugin_branchExceptionPort_payload_badAddr = 32'h0; + BranchPlugin_branchExceptionPort_payload_badAddr = memory_BRANCH_CALC; + end + + always @ (*) begin + SPRPlugin_jumpInterface_valid = 1'b0; + if(_zz_408_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_409_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_410_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_411_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_412_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_413_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + if(_zz_414_)begin + SPRPlugin_jumpInterface_valid = 1'b1; + end + end + + always @ (*) begin + SPRPlugin_jumpInterface_payload = 32'h0; + if(_zz_408_)begin + SPRPlugin_jumpInterface_payload = _zz_345_; + end + if(_zz_409_)begin + SPRPlugin_jumpInterface_payload = (writeBack_PC + 32'h00000004); + end + if(_zz_410_)begin + SPRPlugin_jumpInterface_payload = 32'h00000c00; + end + if(_zz_411_)begin + SPRPlugin_jumpInterface_payload = 32'h00000c00; + end + if(_zz_413_)begin + SPRPlugin_jumpInterface_payload = SPRPlugin_srr0; + end + end + + assign SPRPlugin_forceMachineWire = 1'b0; + always @ (*) begin + SPRPlugin_selfException_payload_codePPC = (5'bxxxxx); + SPRPlugin_selfException_payload_codePPC = `ExcpEnum_defaultEncoding_NONE; + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_payload_codePPC = `ExcpEnum_defaultEncoding_PGM_PRV; + end + end + + assign _zz_1588_ = zz_SPRPlugin_selfException_payload_imm(1'b0); + always @ (*) SPRPlugin_selfException_payload_imm = _zz_1588_; + always @ (*) begin + SPRPlugin_selfException_payload_badAddr = 32'h0; + SPRPlugin_selfException_payload_badAddr = execute_PC; + end + + assign SPRPlugin_allowInterrupts = 1'b1; + assign SPRPlugin_allowException = 1'b1; + assign IBusCachedPlugin_externalFlush = ({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,{execute_arbitration_flushNext,decode_arbitration_flushNext}}} != (4'b0000)); + assign IBusCachedPlugin_jump_pcLoad_valid = ({SPRPlugin_jumpInterface_valid,{BranchPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}} != (3'b000)); + assign _zz_132_ = {BranchPlugin_jumpInterface_valid,{SPRPlugin_jumpInterface_valid,DBusCachedPlugin_redoBranch_valid}}; + assign _zz_133_ = (_zz_132_ & (~ _zz_498_)); + assign _zz_134_ = _zz_133_[1]; + assign _zz_135_ = _zz_133_[2]; + assign IBusCachedPlugin_jump_pcLoad_payload = _zz_393_; + always @ (*) begin + IBusCachedPlugin_fetchPc_correction = 1'b0; + if(IBusCachedPlugin_fetchPc_predictionPcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_correction = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_corrected = (IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_correctionReg); + assign IBusCachedPlugin_fetchPc_pcRegPropagate = 1'b0; + always @ (*) begin + IBusCachedPlugin_fetchPc_pc = (IBusCachedPlugin_fetchPc_pcReg + _zz_500_); + if(IBusCachedPlugin_fetchPc_predictionPcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_predictionPcLoad_payload; + end + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_fetchPc_redo_payload; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_pc = IBusCachedPlugin_jump_pcLoad_payload; + end + IBusCachedPlugin_fetchPc_pc[0] = 1'b0; + end + + always @ (*) begin + IBusCachedPlugin_fetchPc_flushed = 1'b0; + if(IBusCachedPlugin_fetchPc_redo_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + if(IBusCachedPlugin_jump_pcLoad_valid)begin + IBusCachedPlugin_fetchPc_flushed = 1'b1; + end + end + + assign IBusCachedPlugin_fetchPc_output_valid = ((! IBusCachedPlugin_fetcherHalt) && IBusCachedPlugin_fetchPc_booted); + assign IBusCachedPlugin_fetchPc_output_payload = IBusCachedPlugin_fetchPc_pc; + always @ (*) begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b0; + if(IBusCachedPlugin_rsp_redoFetch)begin + IBusCachedPlugin_iBusRsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_iBusRsp_stages_0_input_valid = IBusCachedPlugin_fetchPc_output_valid; + assign IBusCachedPlugin_fetchPc_output_ready = IBusCachedPlugin_iBusRsp_stages_0_input_ready; + assign IBusCachedPlugin_iBusRsp_stages_0_input_payload = IBusCachedPlugin_fetchPc_output_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_prefetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_0_halt = 1'b1; + end + end + + assign _zz_136_ = (! IBusCachedPlugin_iBusRsp_stages_0_halt); + assign IBusCachedPlugin_iBusRsp_stages_0_input_ready = (IBusCachedPlugin_iBusRsp_stages_0_output_ready && _zz_136_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_valid = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && _zz_136_); + assign IBusCachedPlugin_iBusRsp_stages_0_output_payload = IBusCachedPlugin_iBusRsp_stages_0_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b0; + if(IBusCachedPlugin_cache_io_cpu_fetch_haltIt)begin + IBusCachedPlugin_iBusRsp_stages_1_halt = 1'b1; + end + end + + assign _zz_137_ = (! IBusCachedPlugin_iBusRsp_stages_1_halt); + assign IBusCachedPlugin_iBusRsp_stages_1_input_ready = (IBusCachedPlugin_iBusRsp_stages_1_output_ready && _zz_137_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_valid = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && _zz_137_); + assign IBusCachedPlugin_iBusRsp_stages_1_output_payload = IBusCachedPlugin_iBusRsp_stages_1_input_payload; + always @ (*) begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b0; + if((_zz_127_ || IBusCachedPlugin_rsp_iBusRspOutputHalt))begin + IBusCachedPlugin_iBusRsp_stages_2_halt = 1'b1; + end + end + + assign _zz_138_ = (! IBusCachedPlugin_iBusRsp_stages_2_halt); + assign IBusCachedPlugin_iBusRsp_stages_2_input_ready = (IBusCachedPlugin_iBusRsp_stages_2_output_ready && _zz_138_); + assign IBusCachedPlugin_iBusRsp_stages_2_output_valid = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && _zz_138_); + assign IBusCachedPlugin_iBusRsp_stages_2_output_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_fetchPc_redo_valid = IBusCachedPlugin_iBusRsp_redoFetch; + assign IBusCachedPlugin_fetchPc_redo_payload = IBusCachedPlugin_iBusRsp_stages_2_input_payload; + assign IBusCachedPlugin_iBusRsp_flush = ((decode_arbitration_removeIt || (decode_arbitration_flushNext && (! decode_arbitration_isStuck))) || IBusCachedPlugin_iBusRsp_redoFetch); + assign IBusCachedPlugin_iBusRsp_stages_0_output_ready = ((1'b0 && (! _zz_139_)) || IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_139_ = _zz_140_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_valid = _zz_139_; + assign IBusCachedPlugin_iBusRsp_stages_1_input_payload = _zz_141_; + assign IBusCachedPlugin_iBusRsp_stages_1_output_ready = ((1'b0 && (! _zz_142_)) || IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_142_ = _zz_143_; + assign IBusCachedPlugin_iBusRsp_stages_2_input_valid = _zz_142_; + assign IBusCachedPlugin_iBusRsp_stages_2_input_payload = _zz_144_; + always @ (*) begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b1; + if((! IBusCachedPlugin_pcValids_0))begin + IBusCachedPlugin_iBusRsp_readyForError = 1'b0; + end + end + + assign IBusCachedPlugin_pcValids_0 = IBusCachedPlugin_injector_nextPcCalc_valids_1; + assign IBusCachedPlugin_pcValids_1 = IBusCachedPlugin_injector_nextPcCalc_valids_2; + assign IBusCachedPlugin_pcValids_2 = IBusCachedPlugin_injector_nextPcCalc_valids_3; + assign IBusCachedPlugin_pcValids_3 = IBusCachedPlugin_injector_nextPcCalc_valids_4; + assign IBusCachedPlugin_iBusRsp_output_ready = (! decode_arbitration_isStuck); + assign decode_arbitration_isValid = IBusCachedPlugin_iBusRsp_output_valid; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_valid = IBusCachedPlugin_predictor_historyWrite_valid; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address = (IBusCachedPlugin_predictor_historyWrite_payload_address - 10'h001); + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source = IBusCachedPlugin_predictor_historyWrite_payload_data_source; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish = IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish; + assign IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target = IBusCachedPlugin_predictor_historyWrite_payload_data_target; + assign _zz_145_ = (IBusCachedPlugin_iBusRsp_stages_0_input_payload >>> 2); + assign _zz_146_ = _zz_389_; + assign IBusCachedPlugin_predictor_buffer_line_source = _zz_146_[19 : 0]; + assign IBusCachedPlugin_predictor_buffer_line_branchWish = _zz_146_[21 : 20]; + assign IBusCachedPlugin_predictor_buffer_line_target = _zz_146_[53 : 22]; + assign IBusCachedPlugin_predictor_buffer_hazard = (IBusCachedPlugin_predictor_writeLast_valid && (IBusCachedPlugin_predictor_writeLast_payload_address == _zz_503_)); + assign IBusCachedPlugin_predictor_hazard = (IBusCachedPlugin_predictor_buffer_hazard_regNextWhen || IBusCachedPlugin_predictor_buffer_pcCorrected); + assign IBusCachedPlugin_predictor_hit = (IBusCachedPlugin_predictor_line_source == _zz_504_); + assign IBusCachedPlugin_fetchPc_predictionPcLoad_valid = (((IBusCachedPlugin_predictor_line_branchWish[1] && IBusCachedPlugin_predictor_hit) && (! IBusCachedPlugin_predictor_hazard)) && IBusCachedPlugin_iBusRsp_stages_1_input_valid); + assign IBusCachedPlugin_fetchPc_predictionPcLoad_payload = IBusCachedPlugin_predictor_line_target; + assign IBusCachedPlugin_predictor_fetchContext_hazard = IBusCachedPlugin_predictor_hazard; + assign IBusCachedPlugin_predictor_fetchContext_hit = IBusCachedPlugin_predictor_hit; + assign IBusCachedPlugin_predictor_fetchContext_line_source = IBusCachedPlugin_predictor_line_source; + assign IBusCachedPlugin_predictor_fetchContext_line_branchWish = IBusCachedPlugin_predictor_line_branchWish; + assign IBusCachedPlugin_predictor_fetchContext_line_target = IBusCachedPlugin_predictor_line_target; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_hazard = IBusCachedPlugin_predictor_iBusRspContext_hazard; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_hit = IBusCachedPlugin_predictor_iBusRspContext_hit; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_source = IBusCachedPlugin_predictor_iBusRspContext_line_source; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish = IBusCachedPlugin_predictor_iBusRspContext_line_branchWish; + assign IBusCachedPlugin_predictor_iBusRspContextOutput_line_target = IBusCachedPlugin_predictor_iBusRspContext_line_target; + assign IBusCachedPlugin_predictor_injectorContext_hazard = IBusCachedPlugin_predictor_iBusRspContextOutput_hazard; + assign IBusCachedPlugin_predictor_injectorContext_hit = IBusCachedPlugin_predictor_iBusRspContextOutput_hit; + assign IBusCachedPlugin_predictor_injectorContext_line_source = IBusCachedPlugin_predictor_iBusRspContextOutput_line_source; + assign IBusCachedPlugin_predictor_injectorContext_line_branchWish = IBusCachedPlugin_predictor_iBusRspContextOutput_line_branchWish; + assign IBusCachedPlugin_predictor_injectorContext_line_target = IBusCachedPlugin_predictor_iBusRspContextOutput_line_target; + assign IBusCachedPlugin_fetchPrediction_cmd_hadBranch = ((memory_PREDICTION_CONTEXT_hit && (! memory_PREDICTION_CONTEXT_hazard)) && memory_PREDICTION_CONTEXT_line_branchWish[1]); + assign IBusCachedPlugin_fetchPrediction_cmd_targetPc = memory_PREDICTION_CONTEXT_line_target; + always @ (*) begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b0; + if(IBusCachedPlugin_fetchPrediction_rsp_wasRight)begin + IBusCachedPlugin_predictor_historyWrite_valid = memory_PREDICTION_CONTEXT_hit; + end else begin + if(memory_PREDICTION_CONTEXT_hit)begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b1; + end else begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b1; + end + end + if((memory_PREDICTION_CONTEXT_hazard || (! memory_arbitration_isFiring)))begin + IBusCachedPlugin_predictor_historyWrite_valid = 1'b0; + end + end + + assign IBusCachedPlugin_predictor_historyWrite_payload_address = IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord[11 : 2]; + assign IBusCachedPlugin_predictor_historyWrite_payload_data_source = (IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord >>> 12); + assign IBusCachedPlugin_predictor_historyWrite_payload_data_target = IBusCachedPlugin_fetchPrediction_rsp_finalPc; + always @ (*) begin + if(IBusCachedPlugin_fetchPrediction_rsp_wasRight)begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (_zz_505_ - _zz_509_); + end else begin + if(memory_PREDICTION_CONTEXT_hit)begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (_zz_510_ + _zz_514_); + end else begin + IBusCachedPlugin_predictor_historyWrite_payload_data_branchWish = (2'b10); + end + end + end + + assign iBus_cmd_valid = IBusCachedPlugin_cache_io_mem_cmd_valid; + always @ (*) begin + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + iBus_cmd_payload_address = IBusCachedPlugin_cache_io_mem_cmd_payload_address; + end + + assign iBus_cmd_payload_size = IBusCachedPlugin_cache_io_mem_cmd_payload_size; + assign IBusCachedPlugin_s0_tightlyCoupledHit = 1'b0; + assign _zz_368_ = (IBusCachedPlugin_iBusRsp_stages_0_input_valid && (! IBusCachedPlugin_s0_tightlyCoupledHit)); + assign IBusCachedPlugin_s1_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + assign _zz_369_ = (IBusCachedPlugin_iBusRsp_stages_1_input_valid && (! IBusCachedPlugin_s1_tightlyCoupledHit)); + assign _zz_370_ = (! IBusCachedPlugin_iBusRsp_stages_1_input_ready); + assign _zz_371_ = (! SPRPlugin_msr_ir); + assign IBusCachedPlugin_s2_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + assign _zz_372_ = (IBusCachedPlugin_iBusRsp_stages_2_input_valid && (! IBusCachedPlugin_s2_tightlyCoupledHit)); + assign _zz_373_ = (! IBusCachedPlugin_iBusRsp_stages_2_input_ready); + assign _zz_374_ = (SPRPlugin_privilege == (2'b00)); + always @ (*) begin + if(IBusCachedPlugin_s2_bigEndian)begin + _zz_128_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : IBusCachedPlugin_cache_io_cpu_fetch_data); + end else begin + _zz_128_ = (decode_arbitration_isStuck ? decode_INSTRUCTION : {{{IBusCachedPlugin_cache_io_cpu_fetch_data[7 : 0],IBusCachedPlugin_cache_io_cpu_fetch_data[15 : 8]},IBusCachedPlugin_cache_io_cpu_fetch_data[23 : 16]},IBusCachedPlugin_cache_io_cpu_fetch_data[31 : 24]}); + end + end + + assign IBusCachedPlugin_rsp_iBusRspOutputHalt = 1'b0; + assign IBusCachedPlugin_rsp_issueDetected = 1'b0; + always @ (*) begin + IBusCachedPlugin_rsp_redoFetch = 1'b0; + if(_zz_406_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + if(_zz_401_)begin + IBusCachedPlugin_rsp_redoFetch = 1'b1; + end + end + + assign IBusCachedPlugin_rsp_bigEndian = (decode_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + _zz_375_ = (IBusCachedPlugin_rsp_redoFetch && (! IBusCachedPlugin_cache_io_cpu_decode_mmuRefilling)); + if(_zz_401_)begin + _zz_375_ = 1'b1; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_valid = 1'b0; + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_valid = IBusCachedPlugin_iBusRsp_readyForError; + end + end + + always @ (*) begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'bxxxx); + if(_zz_405_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1011); + end + if(_zz_403_)begin + if(_zz_404_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b1100); + end + end + if(_zz_402_)begin + IBusCachedPlugin_decodeExceptionPort_payload_code = (4'b0001); + end + end + + assign IBusCachedPlugin_iBusRsp_output_valid = IBusCachedPlugin_iBusRsp_stages_2_output_valid; + assign IBusCachedPlugin_iBusRsp_stages_2_output_ready = IBusCachedPlugin_iBusRsp_output_ready; + always @ (*) begin + if(IBusCachedPlugin_rsp_bigEndian)begin + IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = IBusCachedPlugin_cache_io_cpu_decode_data; + end else begin + IBusCachedPlugin_iBusRsp_output_payload_rsp_inst = {{{IBusCachedPlugin_cache_io_cpu_decode_data[7 : 0],IBusCachedPlugin_cache_io_cpu_decode_data[15 : 8]},IBusCachedPlugin_cache_io_cpu_decode_data[23 : 16]},IBusCachedPlugin_cache_io_cpu_decode_data[31 : 24]}; + end + end + + assign IBusCachedPlugin_iBusRsp_output_payload_pc = IBusCachedPlugin_iBusRsp_stages_2_output_payload; + assign IBusCachedPlugin_mmuBus_cmd_isValid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_isValid; + assign IBusCachedPlugin_mmuBus_cmd_virtualAddress = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_cmd_bypassTranslation = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_cmd_bypassTranslation; + assign IBusCachedPlugin_mmuBus_spr_valid = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_valid; + assign IBusCachedPlugin_mmuBus_spr_payload_id = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_id; + assign IBusCachedPlugin_mmuBus_spr_payload_data = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_spr_payload_data; + assign IBusCachedPlugin_mmuBus_end = IBusCachedPlugin_cache_io_cpu_fetch_mmuBus_end; + assign _zz_367_ = (decode_arbitration_isValid && decode_FLUSH_ALL); + assign _zz_388_ = ((1'b1 && (! dataCache_1__io_mem_cmd_m2sPipe_valid)) || dataCache_1__io_mem_cmd_m2sPipe_ready); + assign dataCache_1__io_mem_cmd_m2sPipe_valid = dataCache_1__io_mem_cmd_m2sPipe_rValid; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_wr = dataCache_1__io_mem_cmd_m2sPipe_rData_wr; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_address = dataCache_1__io_mem_cmd_m2sPipe_rData_address; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_data = dataCache_1__io_mem_cmd_m2sPipe_rData_data; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_mask = dataCache_1__io_mem_cmd_m2sPipe_rData_mask; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_length = dataCache_1__io_mem_cmd_m2sPipe_rData_length; + assign dataCache_1__io_mem_cmd_m2sPipe_payload_last = dataCache_1__io_mem_cmd_m2sPipe_rData_last; + assign dBus_cmd_valid = dataCache_1__io_mem_cmd_m2sPipe_valid; + assign dataCache_1__io_mem_cmd_m2sPipe_ready = dBus_cmd_ready; + assign dBus_cmd_payload_wr = dataCache_1__io_mem_cmd_m2sPipe_payload_wr; + assign dBus_cmd_payload_address = dataCache_1__io_mem_cmd_m2sPipe_payload_address; + assign dBus_cmd_payload_data = dataCache_1__io_mem_cmd_m2sPipe_payload_data; + assign dBus_cmd_payload_mask = dataCache_1__io_mem_cmd_m2sPipe_payload_mask; + assign dBus_cmd_payload_length = dataCache_1__io_mem_cmd_m2sPipe_payload_length; + assign dBus_cmd_payload_last = dataCache_1__io_mem_cmd_m2sPipe_payload_last; + assign execute_DBusCachedPlugin_bigEndian = (execute_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + case(execute_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + execute_DBusCachedPlugin_size = (2'b00); + end + `DataSizeEnum_defaultEncoding_H : begin + execute_DBusCachedPlugin_size = (2'b01); + end + `DataSizeEnum_defaultEncoding_W : begin + execute_DBusCachedPlugin_size = (2'b10); + end + default : begin + execute_DBusCachedPlugin_size = (2'b00); + end + endcase + end + + assign _zz_377_ = (execute_arbitration_isValid && execute_MEMORY_ENABLE); + assign _zz_378_ = execute_SRC_ADD[31 : 0]; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_149_ = {{{execute_RS[7 : 0],execute_RS[7 : 0]},execute_RS[7 : 0]},execute_RS[7 : 0]}; + end + 2'b01 : begin + _zz_149_ = {execute_RS[15 : 0],execute_RS[15 : 0]}; + end + default : begin + _zz_149_ = execute_RS; + end + endcase + end + + always @ (*) begin + if(execute_DBusCachedPlugin_bigEndian)begin + _zz_379_ = _zz_149_; + end else begin + _zz_379_ = _zz_152_; + end + end + + assign _zz_150_ = execute_RS[15 : 0]; + assign _zz_151_ = execute_RS[15 : 0]; + always @ (*) begin + case(execute_DBusCachedPlugin_size) + 2'b00 : begin + _zz_152_ = {{{execute_RS[7 : 0],execute_RS[7 : 0]},execute_RS[7 : 0]},execute_RS[7 : 0]}; + end + 2'b01 : begin + _zz_152_ = {{_zz_150_[7 : 0],_zz_150_[15 : 8]},{_zz_151_[7 : 0],_zz_151_[15 : 8]}}; + end + default : begin + _zz_152_ = {{{execute_RS[7 : 0],execute_RS[15 : 8]},execute_RS[23 : 16]},execute_RS[31 : 24]}; + end + endcase + end + + assign _zz_387_ = (execute_arbitration_isValid && execute_MEMORY_MANAGMENT); + always @ (*) begin + if(execute_STORE_UPDATE)begin + _zz_124_ = execute_SRC_ADD; + end + if(execute_DECODER_stageables_54)begin + if(ALU2_sprReadValid)begin + _zz_124_ = ALU2_XER; + end else begin + if(execute_DECODER_stageables_23)begin + _zz_124_ = _zz_259_; + end else begin + if(execute_DECODER_stageables_2)begin + if(_zz_260_)begin + _zz_124_ = 32'hffffffff; + end else begin + if(_zz_261_)begin + _zz_124_ = 32'h00000001; + end else begin + _zz_124_ = 32'h0; + end + end + end else begin + if(execute_DECODER_stageables_27)begin + _zz_124_ = (_zz_553_[_zz_554_] ? execute_SRC1 : execute_SRC2); + end else begin + _zz_124_ = sprReadBU_payload_data; + end + end + end + end + end else begin + _zz_124_ = _zz_262_; + end + end + + assign _zz_380_ = ((((memory_arbitration_isValid && memory_MEMORY_ENABLE) && (! DBusCachedPlugin_exceptionBus_valid)) && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign _zz_381_ = memory_REGFILE_WRITE_DATA; + assign _zz_383_ = (! SPRPlugin_msr_dr); + assign DBusCachedPlugin_mmuBus_cmd_isValid = dataCache_1__io_cpu_memory_mmuBus_cmd_isValid; + assign DBusCachedPlugin_mmuBus_cmd_virtualAddress = dataCache_1__io_cpu_memory_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_cmd_bypassTranslation = dataCache_1__io_cpu_memory_mmuBus_cmd_bypassTranslation; + always @ (*) begin + _zz_382_ = DBusCachedPlugin_mmuBus_rsp_isIoAccess; + if((1'b0 && (! dataCache_1__io_cpu_memory_isWrite)))begin + _zz_382_ = 1'b1; + end + end + + assign DBusCachedPlugin_mmuBus_spr_valid = dataCache_1__io_cpu_memory_mmuBus_spr_valid; + assign DBusCachedPlugin_mmuBus_spr_payload_id = dataCache_1__io_cpu_memory_mmuBus_spr_payload_id; + assign DBusCachedPlugin_mmuBus_spr_payload_data = dataCache_1__io_cpu_memory_mmuBus_spr_payload_data; + assign DBusCachedPlugin_mmuBus_end = dataCache_1__io_cpu_memory_mmuBus_end; + assign _zz_384_ = (writeBack_arbitration_isValid && writeBack_MEMORY_ENABLE); + assign _zz_385_ = (SPRPlugin_privilege == (2'b00)); + assign _zz_386_ = writeBack_REGFILE_WRITE_DATA; + assign writeBack_DBusCachedPlugin_bigEndian = (writeBack_MSR_ENDIAN == `EndianEnum_defaultEncoding_BE); + always @ (*) begin + DBusCachedPlugin_redoBranch_valid = 1'b0; + if(_zz_415_)begin + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_redoBranch_valid = 1'b1; + end + end + end + + assign DBusCachedPlugin_redoBranch_payload = writeBack_PC; + always @ (*) begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_valid = 1'b1; + end + if(dataCache_1__io_cpu_redo)begin + DBusCachedPlugin_exceptionBus_valid = 1'b0; + end + end + end + + always @ (*) begin + DBusCachedPlugin_exceptionBus_payload_code = (4'bxxxx); + if(_zz_415_)begin + if(dataCache_1__io_cpu_writeBack_accessError)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_515_}; + end + if(_zz_416_)begin + if(_zz_417_)begin + DBusCachedPlugin_exceptionBus_payload_code = (4'b0000); + end else begin + if(_zz_418_)begin + DBusCachedPlugin_exceptionBus_payload_code = (4'b0000); + end + end + end + if(dataCache_1__io_cpu_writeBack_unalignedAccess)begin + DBusCachedPlugin_exceptionBus_payload_code = {1'd0, _zz_516_}; + end + if(dataCache_1__io_cpu_writeBack_mmuException)begin + DBusCachedPlugin_exceptionBus_payload_code = (writeBack_MEMORY_WR ? (4'b1111) : (4'b1101)); + end + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspShifted = dataCache_1__io_cpu_writeBack_data; + if(writeBack_DBusCachedPlugin_bigEndian)begin + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b00 : begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + `DataSizeEnum_defaultEncoding_H : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + default : begin + end + endcase + end + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[23 : 16]; + end + 2'b10 : begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + default : begin + end + endcase + end + default : begin + end + endcase + end else begin + case(writeBack_MEMORY_ADDRESS_LOW) + 2'b01 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[15 : 8]; + end + 2'b10 : begin + writeBack_DBusCachedPlugin_rspShifted[15 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 16]; + end + 2'b11 : begin + writeBack_DBusCachedPlugin_rspShifted[7 : 0] = dataCache_1__io_cpu_writeBack_data[31 : 24]; + end + default : begin + end + endcase + end + end + + always @ (*) begin + writeBack_DBusCachedPlugin_rspHW = 16'h0; + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + end + `DataSizeEnum_defaultEncoding_H : begin + if((writeBack_MEMORY_ADDRESS_LOW == (2'b00)))begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspHW = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + end else begin + writeBack_DBusCachedPlugin_rspHW = {_zz_153_[7 : 0],_zz_153_[15 : 8]}; + end + end else begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspHW = writeBack_DBusCachedPlugin_rspShifted[31 : 16]; + end else begin + writeBack_DBusCachedPlugin_rspHW = {_zz_154_[7 : 0],_zz_154_[15 : 8]}; + end + end + end + default : begin + end + endcase + end + + always @ (*) begin + case(writeBack_DATA_SIZE) + `DataSizeEnum_defaultEncoding_B : begin + writeBack_DBusCachedPlugin_rspFormated = {24'h0,writeBack_DBusCachedPlugin_rspShifted[7 : 0]}; + end + `DataSizeEnum_defaultEncoding_H : begin + if(writeBack_SIGN_EXTEND)begin + writeBack_DBusCachedPlugin_rspFormated = {_zz_156_,writeBack_DBusCachedPlugin_rspHW}; + end else begin + writeBack_DBusCachedPlugin_rspFormated = {16'h0,writeBack_DBusCachedPlugin_rspHW}; + end + end + default : begin + if(writeBack_DBusCachedPlugin_bigEndian)begin + writeBack_DBusCachedPlugin_rspFormated = writeBack_DBusCachedPlugin_rspShifted; + end else begin + writeBack_DBusCachedPlugin_rspFormated = {{{writeBack_DBusCachedPlugin_rspShifted[7 : 0],writeBack_DBusCachedPlugin_rspShifted[15 : 8]},writeBack_DBusCachedPlugin_rspShifted[23 : 16]},writeBack_DBusCachedPlugin_rspShifted[31 : 24]}; + end + end + endcase + end + + assign _zz_153_ = writeBack_DBusCachedPlugin_rspShifted[15 : 0]; + assign _zz_154_ = writeBack_DBusCachedPlugin_rspShifted[31 : 16]; + assign _zz_155_ = writeBack_DBusCachedPlugin_rspHW[15]; + always @ (*) begin + _zz_156_[15] = _zz_155_; + _zz_156_[14] = _zz_155_; + _zz_156_[13] = _zz_155_; + _zz_156_[12] = _zz_155_; + _zz_156_[11] = _zz_155_; + _zz_156_[10] = _zz_155_; + _zz_156_[9] = _zz_155_; + _zz_156_[8] = _zz_155_; + _zz_156_[7] = _zz_155_; + _zz_156_[6] = _zz_155_; + _zz_156_[5] = _zz_155_; + _zz_156_[4] = _zz_155_; + _zz_156_[3] = _zz_155_; + _zz_156_[2] = _zz_155_; + _zz_156_[1] = _zz_155_; + _zz_156_[0] = _zz_155_; + end + + assign IBusCachedPlugin_mmuBus_rsp_physicalAddress = IBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign IBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign IBusCachedPlugin_mmuBus_rsp_isIoAccess = (IBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)); + assign IBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign IBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign IBusCachedPlugin_mmuBus_busy = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_physicalAddress = DBusCachedPlugin_mmuBus_cmd_virtualAddress; + assign DBusCachedPlugin_mmuBus_rsp_allowRead = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowWrite = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_allowExecute = 1'b1; + assign DBusCachedPlugin_mmuBus_rsp_isIoAccess = (DBusCachedPlugin_mmuBus_rsp_physicalAddress[31 : 28] == (4'b1111)); + assign DBusCachedPlugin_mmuBus_rsp_exception = 1'b0; + assign DBusCachedPlugin_mmuBus_rsp_refilling = 1'b0; + assign DBusCachedPlugin_mmuBus_busy = 1'b0; + assign _zz_158_ = ((decode_INSTRUCTION & 32'h00000300) == 32'h00000100); + assign _zz_159_ = ((decode_INSTRUCTION & 32'h50000000) == 32'h10000000); + assign _zz_160_ = ((decode_INSTRUCTION & 32'h80000000) == 32'h80000000); + assign _zz_161_ = ((decode_INSTRUCTION & 32'h78000138) == 32'h78000100); + assign _zz_162_ = ((decode_INSTRUCTION & 32'h00000500) == 32'h00000400); + assign _zz_163_ = ((decode_INSTRUCTION & 32'h00000040) == 32'h00000040); + assign _zz_164_ = ((decode_INSTRUCTION & 32'he0000000) == 32'h20000000); + assign _zz_165_ = ((decode_INSTRUCTION & 32'h90000000) == 32'h90000000); + assign _zz_166_ = ((decode_INSTRUCTION & 32'h780001b8) == 32'h78000020); + assign _zz_167_ = ((decode_INSTRUCTION & 32'h78000038) == 32'h78000018); + assign _zz_168_ = ((decode_INSTRUCTION & 32'h28000000) == 32'h0); + assign _zz_169_ = ((decode_INSTRUCTION & 32'h70000000) == 32'h60000000); + assign _zz_170_ = ((decode_INSTRUCTION & 32'hd4000000) == 32'h84000000); + assign _zz_171_ = ((decode_INSTRUCTION & 32'h78000416) == 32'h78000004); + assign _zz_172_ = ((decode_INSTRUCTION & 32'hf8040000) == 32'h38040000); + assign _zz_173_ = ((decode_INSTRUCTION & 32'hf8080000) == 32'h38080000); + assign _zz_174_ = ((decode_INSTRUCTION & 32'hf8010000) == 32'h38010000); + assign _zz_175_ = ((decode_INSTRUCTION & 32'hf8020000) == 32'h38020000); + assign _zz_176_ = ((decode_INSTRUCTION & 32'hec000000) == 32'h20000000); + assign _zz_177_ = ((decode_INSTRUCTION & 32'hd4020000) == 32'h80020000); + assign _zz_178_ = ((decode_INSTRUCTION & 32'hd4080000) == 32'h80080000); + assign _zz_179_ = ((decode_INSTRUCTION & 32'hd4040000) == 32'h80040000); + assign _zz_180_ = ((decode_INSTRUCTION & 32'hd4010000) == 32'h80010000); + assign _zz_181_ = ((decode_INSTRUCTION & 32'hcc080000) == 32'h80080000); + assign _zz_182_ = ((decode_INSTRUCTION & 32'he4020000) == 32'h80020000); + assign _zz_183_ = ((decode_INSTRUCTION & 32'hcc020000) == 32'h80020000); + assign _zz_184_ = ((decode_INSTRUCTION & 32'he4040000) == 32'h80040000); + assign _zz_185_ = ((decode_INSTRUCTION & 32'hcc010000) == 32'h80010000); + assign _zz_186_ = ((decode_INSTRUCTION & 32'he4080000) == 32'h80080000); + assign _zz_187_ = ((decode_INSTRUCTION & 32'hf8000000) == 32'h28000000); + assign _zz_188_ = ((decode_INSTRUCTION & 32'hcc040000) == 32'h80040000); + assign _zz_189_ = ((decode_INSTRUCTION & 32'he4010000) == 32'h80010000); + assign _zz_190_ = ((decode_INSTRUCTION & 32'h78000382) == 32'h78000180); + assign _zz_191_ = ((decode_INSTRUCTION & 32'h70000000) == 32'h50000000); + assign _zz_192_ = ((decode_INSTRUCTION & 32'h48000000) == 32'h40000000); + assign _zz_193_ = ((decode_INSTRUCTION & 32'h78000698) == 32'h78000080); + assign _zz_194_ = ((decode_INSTRUCTION & 32'h78000034) == 32'h78000010); + assign _zz_195_ = ((decode_INSTRUCTION & 32'h01f0707f) == 32'h0000500f); + assign _zz_196_ = ((decode_INSTRUCTION & 32'h7800022a) == 32'h78000002); + assign _zz_197_ = ((decode_INSTRUCTION & 32'h9c000000) == 32'h08000000); + assign _zz_198_ = ((decode_INSTRUCTION & 32'hf4000000) == 32'h54000000); + assign _zz_199_ = ((decode_INSTRUCTION & 32'h7c0004a0) == 32'h4c0000a0); + assign _zz_200_ = ((decode_INSTRUCTION & 32'h7c000460) == 32'h4c000060); + assign _zz_201_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h1c000000); + assign _zz_202_ = ((decode_INSTRUCTION & 32'hd40f0000) == 32'h80000000); + assign _zz_203_ = ((decode_INSTRUCTION & 32'h78000498) == 32'h78000080); + assign _zz_204_ = ((decode_INSTRUCTION & 32'h7800002c) == 32'h78000008); + assign _zz_205_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h44000000); + assign _zz_206_ = ((decode_INSTRUCTION & 32'h90100000) == 32'h80100000); + assign _zz_207_ = ((decode_INSTRUCTION & 32'h7800030a) == 32'h78000102); + assign _zz_208_ = ((decode_INSTRUCTION & 32'h78000328) == 32'h78000300); + assign _zz_209_ = ((decode_INSTRUCTION & 32'h381f0038) == 32'h38000028); + assign _zz_210_ = ((decode_INSTRUCTION & 32'h381f0038) == 32'h38000018); + assign _zz_211_ = ((decode_INSTRUCTION & 32'h781f0000) == 32'h38000000); + assign _zz_212_ = ((decode_INSTRUCTION & 32'h801f0000) == 32'h80000000); + assign _zz_213_ = ((decode_INSTRUCTION & 32'hfc000000) == 32'h0c000000); + assign _zz_214_ = ((decode_INSTRUCTION & 32'hdc000000) == 32'h94000000); + assign _zz_215_ = ((decode_INSTRUCTION & 32'hf4000000) == 32'h94000000); + assign _zz_216_ = ((decode_INSTRUCTION & 32'hbc000000) == 32'h1c000000); + assign _zz_217_ = ((decode_INSTRUCTION & 32'hb8000000) == 32'h30000000); + assign _zz_218_ = ((decode_INSTRUCTION & 32'he4000000) == 32'h84000000); + assign _zz_219_ = ((decode_INSTRUCTION & 32'hd8000000) == 32'h50000000); + assign _zz_220_ = ((decode_INSTRUCTION & 32'hf0000000) == 32'h60000000); + assign _zz_221_ = ((decode_INSTRUCTION & 32'hcc000000) == 32'h84000000); + assign _zz_222_ = ((decode_INSTRUCTION & 32'hfc000002) == 32'h44000002); + assign _zz_157_ = {({(_zz_742_ == _zz_743_),{_zz_744_,{_zz_745_,_zz_746_}}} != (4'b0000)),{({_zz_159_,_zz_747_} != (2'b00)),{(_zz_748_ != (1'b0)),{(_zz_749_ != _zz_750_),{_zz_751_,{_zz_752_,_zz_753_}}}}}}; + assign _zz_223_ = _zz_157_[2 : 0]; + assign _zz_120_ = _zz_223_; + assign _zz_224_ = _zz_157_[4 : 3]; + assign _zz_119_ = _zz_224_; + assign _zz_225_ = _zz_157_[11 : 10]; + assign _zz_118_ = _zz_225_; + assign _zz_226_ = _zz_157_[13 : 12]; + assign _zz_117_ = _zz_226_; + assign _zz_227_ = _zz_157_[17 : 17]; + assign _zz_116_ = _zz_227_; + assign _zz_228_ = _zz_157_[20 : 18]; + assign _zz_115_ = _zz_228_; + assign _zz_229_ = _zz_157_[25 : 23]; + assign _zz_114_ = _zz_229_; + assign _zz_230_ = _zz_157_[31 : 28]; + assign _zz_113_ = _zz_230_; + assign _zz_231_ = _zz_157_[34 : 32]; + assign _zz_112_ = _zz_231_; + assign _zz_232_ = _zz_157_[42 : 40]; + assign _zz_111_ = _zz_232_; + assign _zz_233_ = _zz_157_[56 : 54]; + assign _zz_110_ = _zz_233_; + assign _zz_234_ = _zz_157_[62 : 62]; + assign _zz_109_ = _zz_234_; + assign _zz_235_ = _zz_157_[70 : 67]; + assign _zz_108_ = _zz_235_; + assign _zz_236_ = _zz_157_[73 : 72]; + assign _zz_107_ = _zz_236_; + always @ (*) begin + decodeExceptionPort_valid = 1'b0; + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_valid = 1'b1; + end + if(_zz_420_)begin + decodeExceptionPort_valid = 1'b1; + end + end + end + + always @ (*) begin + decodeExceptionPort_payload_code = (4'bxxxx); + if(decode_arbitration_isValid)begin + if(_zz_419_)begin + decodeExceptionPort_payload_code = (4'b0010); + end + if(_zz_420_)begin + decodeExceptionPort_payload_code = (4'b0010); + end + end + end + + assign _zz_376_ = _zz_517_[9 : 0]; + assign decode_RegFilePlugin_regFileReadAddress1 = decode_INSTRUCTION_ANTICIPATED[20 : 16]; + assign decode_RegFilePlugin_regFileReadAddress2 = decode_INSTRUCTION_ANTICIPATED[15 : 11]; + assign decode_RegFilePlugin_raData_pre = _zz_390_; + assign decode_RegFilePlugin_rbData_pre = _zz_391_; + assign decode_RegFilePlugin_regFileReadAddress3 = decode_INSTRUCTION_ANTICIPATED[25 : 21]; + assign decode_RegFilePlugin_rsData = _zz_392_; + always @ (*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RS : begin + decode_RegFilePlugin_raData = decode_RegFilePlugin_rsData; + end + default : begin + decode_RegFilePlugin_raData = decode_RegFilePlugin_raData_pre; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RA : begin + decode_RegFilePlugin_rbData = decode_RegFilePlugin_raData; + end + default : begin + decode_RegFilePlugin_rbData = decode_RegFilePlugin_rbData_pre; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RS : begin + _zz_238_ = decode_INSTRUCTION[25 : 21]; + end + default : begin + _zz_238_ = decode_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RA : begin + _zz_239_ = decode_INSTRUCTION[20 : 16]; + end + default : begin + _zz_239_ = decode_INSTRUCTION[15 : 11]; + end + endcase + end + + always @ (*) begin + case(decode_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : begin + _zz_240_ = decode_INSTRUCTION[25 : 21]; + end + default : begin + _zz_240_ = decode_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_valid = (_zz_102_ && writeBack_arbitration_isFiring); + end else begin + lastStageRegFileWrite_valid = 1'b1; + end + if(_zz_241_)begin + lastStageRegFileWrite_valid = 1'b1; + end + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_payload_address = writeBack_REGFILE_WRITE_ADDR; + end else begin + lastStageRegFileWrite_payload_address = UpdateRegFileWrite_payload_address; + end + end + + always @ (*) begin + if(_zz_421_)begin + lastStageRegFileWrite_payload_data = _zz_121_; + end else begin + lastStageRegFileWrite_payload_data = UpdateRegFileWrite_payload_data; + end + end + + always @ (*) begin + if(writeBack_arbitration_isFiring)begin + writeBack_RegFilePlugin_crBusPort_valid = ((1'b1 || writeBack_BRANCH_DEC) || writeBack_BRANCH_LINK); + end else begin + writeBack_RegFilePlugin_crBusPort_valid = 1'b0; + end + end + + always @ (*) begin + if((writeBack_BRANCH_DEC && writeBack_BRANCH_LINK))begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_DECLNK; + end else begin + if(writeBack_BRANCH_DEC)begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_DEC; + end else begin + if(writeBack_BRANCH_LINK)begin + writeBack_RegFilePlugin_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_LNK; + end else begin + writeBack_RegFilePlugin_crBusPort_payload_op = writeBack_CR_WRITE_op; + end + end + end + end + + assign writeBack_RegFilePlugin_crBusPort_payload_ba = writeBack_CR_WRITE_ba; + assign writeBack_RegFilePlugin_crBusPort_payload_bb = writeBack_CR_WRITE_bb; + assign writeBack_RegFilePlugin_crBusPort_payload_bt = writeBack_CR_WRITE_bt; + always @ (*) begin + if(writeBack_BRANCH_LINK)begin + writeBack_RegFilePlugin_crBusPort_payload_imm = _zz_518_; + end else begin + writeBack_RegFilePlugin_crBusPort_payload_imm = writeBack_CR_WRITE_imm; + end + end + + assign writeBack_RegFilePlugin_crBusPort_payload_fxm = writeBack_CR_WRITE_fxm; + always @ (*) begin + if(writeBack_arbitration_isFiring)begin + writeBack_RegFilePlugin_xerBusPort_valid = (writeBack_XER_WRITE_validOV || writeBack_XER_WRITE_validCA); + end else begin + writeBack_RegFilePlugin_xerBusPort_valid = 1'b0; + end + end + + assign writeBack_RegFilePlugin_xerBusPort_payload_validOV = writeBack_XER_WRITE_validOV; + assign writeBack_RegFilePlugin_xerBusPort_payload_validCA = writeBack_XER_WRITE_validCA; + assign writeBack_RegFilePlugin_xerBusPort_payload_imm = writeBack_XER_WRITE_imm; + always @ (*) begin + case(writeBack_SPR_ID) + 11'b00000000001 : begin + writeBack_RegFilePlugin_sprWriteXERPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + default : begin + writeBack_RegFilePlugin_sprWriteXERPort_valid = 1'b0; + end + endcase + end + + assign writeBack_RegFilePlugin_sprWriteXERPort_payload_id = 10'h0; + assign writeBack_RegFilePlugin_sprWriteXERPort_payload_data = writeBack_SRC1; + always @ (*) begin + case(writeBack_SPR_ID) + 11'b00000001001 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + 11'b00000001000 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + 11'b01100101111 : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = (writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring); + end + default : begin + writeBack_RegFilePlugin_sprWriteCLTPort_valid = 1'b0; + end + endcase + end + + assign writeBack_RegFilePlugin_sprWriteCLTPort_payload_id = _zz_519_[9 : 0]; + assign writeBack_RegFilePlugin_sprWriteCLTPort_payload_data = writeBack_SRC1; + always @ (*) begin + _zz_237_ = 1'b0; + if((writeBack_DECODER_stageables_32 && writeBack_arbitration_isFiring))begin + case(writeBack_SPR_ID) + 11'b01111101000 : begin + _zz_237_ = 1'b1; + end + 11'b01111101001 : begin + _zz_237_ = 1'b1; + end + 11'b01111101010 : begin + _zz_237_ = 1'b1; + end + default : begin + end + endcase + end + end + + always @ (*) begin + _zz_243_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_243_ = writeBack_RegFilePlugin_xerBusPort_payload_validCA; + end + end + + always @ (*) begin + _zz_242_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_242_ = writeBack_RegFilePlugin_xerBusPort_payload_validOV; + end + end + + always @ (*) begin + _zz_244_ = (2'bxx); + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_244_ = writeBack_RegFilePlugin_xerBusPort_payload_imm; + end + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b00000000001 : begin + ALU2_sprReadValid = execute_DECODER_stageables_54; + end + default : begin + ALU2_sprReadValid = 1'b0; + end + endcase + end + + always @ (*) begin + _zz_245_ = 1'b0; + if(writeBack_RegFilePlugin_xerBusPort_valid)begin + _zz_245_ = 1'b1; + end + end + + assign _zz_246_ = execute_SRC1[7]; + always @ (*) begin + _zz_247_[23] = _zz_246_; + _zz_247_[22] = _zz_246_; + _zz_247_[21] = _zz_246_; + _zz_247_[20] = _zz_246_; + _zz_247_[19] = _zz_246_; + _zz_247_[18] = _zz_246_; + _zz_247_[17] = _zz_246_; + _zz_247_[16] = _zz_246_; + _zz_247_[15] = _zz_246_; + _zz_247_[14] = _zz_246_; + _zz_247_[13] = _zz_246_; + _zz_247_[12] = _zz_246_; + _zz_247_[11] = _zz_246_; + _zz_247_[10] = _zz_246_; + _zz_247_[9] = _zz_246_; + _zz_247_[8] = _zz_246_; + _zz_247_[7] = _zz_246_; + _zz_247_[6] = _zz_246_; + _zz_247_[5] = _zz_246_; + _zz_247_[4] = _zz_246_; + _zz_247_[3] = _zz_246_; + _zz_247_[2] = _zz_246_; + _zz_247_[1] = _zz_246_; + _zz_247_[0] = _zz_246_; + end + + assign _zz_248_ = execute_SRC1[15]; + always @ (*) begin + _zz_249_[15] = _zz_248_; + _zz_249_[14] = _zz_248_; + _zz_249_[13] = _zz_248_; + _zz_249_[12] = _zz_248_; + _zz_249_[11] = _zz_248_; + _zz_249_[10] = _zz_248_; + _zz_249_[9] = _zz_248_; + _zz_249_[8] = _zz_248_; + _zz_249_[7] = _zz_248_; + _zz_249_[6] = _zz_248_; + _zz_249_[5] = _zz_248_; + _zz_249_[4] = _zz_248_; + _zz_249_[3] = _zz_248_; + _zz_249_[2] = _zz_248_; + _zz_249_[1] = _zz_248_; + _zz_249_[0] = _zz_248_; + end + + always @ (*) begin + case(execute_DECODER_stageables_19) + `AluBitwiseCtrlEnum_defaultEncoding_AND_1 : begin + ALU2_bitwise = (execute_SRC1 & execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_ANDC : begin + ALU2_bitwise = (execute_SRC1 & (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_OR_1 : begin + ALU2_bitwise = (execute_SRC1 | execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_ORC : begin + ALU2_bitwise = (execute_SRC1 | (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_XOR_1 : begin + ALU2_bitwise = (execute_SRC1 ^ execute_SRC2); + end + `AluBitwiseCtrlEnum_defaultEncoding_XORC : begin + ALU2_bitwise = (execute_SRC1 ^ (~ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_NAND_1 : begin + ALU2_bitwise = (~ (execute_SRC1 & execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_NOR_1 : begin + ALU2_bitwise = (~ (execute_SRC1 | execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_EQV : begin + ALU2_bitwise = (~ (execute_SRC1 ^ execute_SRC2)); + end + `AluBitwiseCtrlEnum_defaultEncoding_EXTSB : begin + ALU2_bitwise = {_zz_247_,execute_SRC1[7 : 0]}; + end + default : begin + ALU2_bitwise = {_zz_249_,execute_SRC1[15 : 0]}; + end + endcase + end + + always @ (*) begin + ALU2_bitwise_enc_cr[1] = ALU2_bitwise[31]; + ALU2_bitwise_enc_cr[0] = (ALU2_bitwise == 32'h0); + end + + always @ (*) begin + case(ALU2_bitwise_enc_cr) + 2'b00 : begin + ALU2_bitwise_cr = (3'b010); + end + 2'b01 : begin + ALU2_bitwise_cr = (3'b001); + end + default : begin + ALU2_bitwise_cr = (3'b100); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_44) + `AluRimiAmtEnum_defaultEncoding_IMM : begin + ALU2_amount = execute_INSTRUCTION[15 : 11]; + end + default : begin + ALU2_amount = execute_SRC2[4 : 0]; + end + endcase + end + + assign ALU2_maskMB = execute_INSTRUCTION[10 : 6]; + assign ALU2_maskME = execute_INSTRUCTION[5 : 1]; + always @ (*) begin + ALU2_maskNorm[0] = 1'b0; + if(((ALU2_maskMB <= 5'h1f) && (5'h1f <= ALU2_maskME)))begin + ALU2_maskNorm[0] = 1'b1; + end + ALU2_maskNorm[1] = 1'b0; + if(((ALU2_maskMB <= 5'h1e) && (5'h1e <= ALU2_maskME)))begin + ALU2_maskNorm[1] = 1'b1; + end + ALU2_maskNorm[2] = 1'b0; + if(((ALU2_maskMB <= 5'h1d) && (5'h1d <= ALU2_maskME)))begin + ALU2_maskNorm[2] = 1'b1; + end + ALU2_maskNorm[3] = 1'b0; + if(((ALU2_maskMB <= 5'h1c) && (5'h1c <= ALU2_maskME)))begin + ALU2_maskNorm[3] = 1'b1; + end + ALU2_maskNorm[4] = 1'b0; + if(((ALU2_maskMB <= 5'h1b) && (5'h1b <= ALU2_maskME)))begin + ALU2_maskNorm[4] = 1'b1; + end + ALU2_maskNorm[5] = 1'b0; + if(((ALU2_maskMB <= 5'h1a) && (5'h1a <= ALU2_maskME)))begin + ALU2_maskNorm[5] = 1'b1; + end + ALU2_maskNorm[6] = 1'b0; + if(((ALU2_maskMB <= 5'h19) && (5'h19 <= ALU2_maskME)))begin + ALU2_maskNorm[6] = 1'b1; + end + ALU2_maskNorm[7] = 1'b0; + if(((ALU2_maskMB <= 5'h18) && (5'h18 <= ALU2_maskME)))begin + ALU2_maskNorm[7] = 1'b1; + end + ALU2_maskNorm[8] = 1'b0; + if(((ALU2_maskMB <= 5'h17) && (5'h17 <= ALU2_maskME)))begin + ALU2_maskNorm[8] = 1'b1; + end + ALU2_maskNorm[9] = 1'b0; + if(((ALU2_maskMB <= 5'h16) && (5'h16 <= ALU2_maskME)))begin + ALU2_maskNorm[9] = 1'b1; + end + ALU2_maskNorm[10] = 1'b0; + if(((ALU2_maskMB <= 5'h15) && (5'h15 <= ALU2_maskME)))begin + ALU2_maskNorm[10] = 1'b1; + end + ALU2_maskNorm[11] = 1'b0; + if(((ALU2_maskMB <= 5'h14) && (5'h14 <= ALU2_maskME)))begin + ALU2_maskNorm[11] = 1'b1; + end + ALU2_maskNorm[12] = 1'b0; + if(((ALU2_maskMB <= 5'h13) && (5'h13 <= ALU2_maskME)))begin + ALU2_maskNorm[12] = 1'b1; + end + ALU2_maskNorm[13] = 1'b0; + if(((ALU2_maskMB <= 5'h12) && (5'h12 <= ALU2_maskME)))begin + ALU2_maskNorm[13] = 1'b1; + end + ALU2_maskNorm[14] = 1'b0; + if(((ALU2_maskMB <= 5'h11) && (5'h11 <= ALU2_maskME)))begin + ALU2_maskNorm[14] = 1'b1; + end + ALU2_maskNorm[15] = 1'b0; + if(((ALU2_maskMB <= 5'h10) && (5'h10 <= ALU2_maskME)))begin + ALU2_maskNorm[15] = 1'b1; + end + ALU2_maskNorm[16] = 1'b0; + if(((ALU2_maskMB <= 5'h0f) && (5'h0f <= ALU2_maskME)))begin + ALU2_maskNorm[16] = 1'b1; + end + ALU2_maskNorm[17] = 1'b0; + if(((ALU2_maskMB <= 5'h0e) && (5'h0e <= ALU2_maskME)))begin + ALU2_maskNorm[17] = 1'b1; + end + ALU2_maskNorm[18] = 1'b0; + if(((ALU2_maskMB <= 5'h0d) && (5'h0d <= ALU2_maskME)))begin + ALU2_maskNorm[18] = 1'b1; + end + ALU2_maskNorm[19] = 1'b0; + if(((ALU2_maskMB <= 5'h0c) && (5'h0c <= ALU2_maskME)))begin + ALU2_maskNorm[19] = 1'b1; + end + ALU2_maskNorm[20] = 1'b0; + if(((ALU2_maskMB <= 5'h0b) && (5'h0b <= ALU2_maskME)))begin + ALU2_maskNorm[20] = 1'b1; + end + ALU2_maskNorm[21] = 1'b0; + if(((ALU2_maskMB <= 5'h0a) && (5'h0a <= ALU2_maskME)))begin + ALU2_maskNorm[21] = 1'b1; + end + ALU2_maskNorm[22] = 1'b0; + if(((ALU2_maskMB <= 5'h09) && (5'h09 <= ALU2_maskME)))begin + ALU2_maskNorm[22] = 1'b1; + end + ALU2_maskNorm[23] = 1'b0; + if(((ALU2_maskMB <= 5'h08) && (5'h08 <= ALU2_maskME)))begin + ALU2_maskNorm[23] = 1'b1; + end + ALU2_maskNorm[24] = 1'b0; + if(((ALU2_maskMB <= 5'h07) && (5'h07 <= ALU2_maskME)))begin + ALU2_maskNorm[24] = 1'b1; + end + ALU2_maskNorm[25] = 1'b0; + if(((ALU2_maskMB <= 5'h06) && (5'h06 <= ALU2_maskME)))begin + ALU2_maskNorm[25] = 1'b1; + end + ALU2_maskNorm[26] = 1'b0; + if(((ALU2_maskMB <= 5'h05) && (5'h05 <= ALU2_maskME)))begin + ALU2_maskNorm[26] = 1'b1; + end + ALU2_maskNorm[27] = 1'b0; + if(((ALU2_maskMB <= 5'h04) && (5'h04 <= ALU2_maskME)))begin + ALU2_maskNorm[27] = 1'b1; + end + ALU2_maskNorm[28] = 1'b0; + if(((ALU2_maskMB <= 5'h03) && (5'h03 <= ALU2_maskME)))begin + ALU2_maskNorm[28] = 1'b1; + end + ALU2_maskNorm[29] = 1'b0; + if(((ALU2_maskMB <= 5'h02) && (5'h02 <= ALU2_maskME)))begin + ALU2_maskNorm[29] = 1'b1; + end + ALU2_maskNorm[30] = 1'b0; + if(((ALU2_maskMB <= 5'h01) && (5'h01 <= ALU2_maskME)))begin + ALU2_maskNorm[30] = 1'b1; + end + ALU2_maskNorm[31] = 1'b0; + if(((ALU2_maskMB <= 5'h0) && (5'h0 <= ALU2_maskME)))begin + ALU2_maskNorm[31] = 1'b1; + end + end + + always @ (*) begin + ALU2_maskInvt[0] = 1'b0; + if(((5'h1f <= ALU2_maskME) || (ALU2_maskMB <= 5'h1f)))begin + ALU2_maskInvt[0] = 1'b1; + end + ALU2_maskInvt[1] = 1'b0; + if(((5'h1e <= ALU2_maskME) || (ALU2_maskMB <= 5'h1e)))begin + ALU2_maskInvt[1] = 1'b1; + end + ALU2_maskInvt[2] = 1'b0; + if(((5'h1d <= ALU2_maskME) || (ALU2_maskMB <= 5'h1d)))begin + ALU2_maskInvt[2] = 1'b1; + end + ALU2_maskInvt[3] = 1'b0; + if(((5'h1c <= ALU2_maskME) || (ALU2_maskMB <= 5'h1c)))begin + ALU2_maskInvt[3] = 1'b1; + end + ALU2_maskInvt[4] = 1'b0; + if(((5'h1b <= ALU2_maskME) || (ALU2_maskMB <= 5'h1b)))begin + ALU2_maskInvt[4] = 1'b1; + end + ALU2_maskInvt[5] = 1'b0; + if(((5'h1a <= ALU2_maskME) || (ALU2_maskMB <= 5'h1a)))begin + ALU2_maskInvt[5] = 1'b1; + end + ALU2_maskInvt[6] = 1'b0; + if(((5'h19 <= ALU2_maskME) || (ALU2_maskMB <= 5'h19)))begin + ALU2_maskInvt[6] = 1'b1; + end + ALU2_maskInvt[7] = 1'b0; + if(((5'h18 <= ALU2_maskME) || (ALU2_maskMB <= 5'h18)))begin + ALU2_maskInvt[7] = 1'b1; + end + ALU2_maskInvt[8] = 1'b0; + if(((5'h17 <= ALU2_maskME) || (ALU2_maskMB <= 5'h17)))begin + ALU2_maskInvt[8] = 1'b1; + end + ALU2_maskInvt[9] = 1'b0; + if(((5'h16 <= ALU2_maskME) || (ALU2_maskMB <= 5'h16)))begin + ALU2_maskInvt[9] = 1'b1; + end + ALU2_maskInvt[10] = 1'b0; + if(((5'h15 <= ALU2_maskME) || (ALU2_maskMB <= 5'h15)))begin + ALU2_maskInvt[10] = 1'b1; + end + ALU2_maskInvt[11] = 1'b0; + if(((5'h14 <= ALU2_maskME) || (ALU2_maskMB <= 5'h14)))begin + ALU2_maskInvt[11] = 1'b1; + end + ALU2_maskInvt[12] = 1'b0; + if(((5'h13 <= ALU2_maskME) || (ALU2_maskMB <= 5'h13)))begin + ALU2_maskInvt[12] = 1'b1; + end + ALU2_maskInvt[13] = 1'b0; + if(((5'h12 <= ALU2_maskME) || (ALU2_maskMB <= 5'h12)))begin + ALU2_maskInvt[13] = 1'b1; + end + ALU2_maskInvt[14] = 1'b0; + if(((5'h11 <= ALU2_maskME) || (ALU2_maskMB <= 5'h11)))begin + ALU2_maskInvt[14] = 1'b1; + end + ALU2_maskInvt[15] = 1'b0; + if(((5'h10 <= ALU2_maskME) || (ALU2_maskMB <= 5'h10)))begin + ALU2_maskInvt[15] = 1'b1; + end + ALU2_maskInvt[16] = 1'b0; + if(((5'h0f <= ALU2_maskME) || (ALU2_maskMB <= 5'h0f)))begin + ALU2_maskInvt[16] = 1'b1; + end + ALU2_maskInvt[17] = 1'b0; + if(((5'h0e <= ALU2_maskME) || (ALU2_maskMB <= 5'h0e)))begin + ALU2_maskInvt[17] = 1'b1; + end + ALU2_maskInvt[18] = 1'b0; + if(((5'h0d <= ALU2_maskME) || (ALU2_maskMB <= 5'h0d)))begin + ALU2_maskInvt[18] = 1'b1; + end + ALU2_maskInvt[19] = 1'b0; + if(((5'h0c <= ALU2_maskME) || (ALU2_maskMB <= 5'h0c)))begin + ALU2_maskInvt[19] = 1'b1; + end + ALU2_maskInvt[20] = 1'b0; + if(((5'h0b <= ALU2_maskME) || (ALU2_maskMB <= 5'h0b)))begin + ALU2_maskInvt[20] = 1'b1; + end + ALU2_maskInvt[21] = 1'b0; + if(((5'h0a <= ALU2_maskME) || (ALU2_maskMB <= 5'h0a)))begin + ALU2_maskInvt[21] = 1'b1; + end + ALU2_maskInvt[22] = 1'b0; + if(((5'h09 <= ALU2_maskME) || (ALU2_maskMB <= 5'h09)))begin + ALU2_maskInvt[22] = 1'b1; + end + ALU2_maskInvt[23] = 1'b0; + if(((5'h08 <= ALU2_maskME) || (ALU2_maskMB <= 5'h08)))begin + ALU2_maskInvt[23] = 1'b1; + end + ALU2_maskInvt[24] = 1'b0; + if(((5'h07 <= ALU2_maskME) || (ALU2_maskMB <= 5'h07)))begin + ALU2_maskInvt[24] = 1'b1; + end + ALU2_maskInvt[25] = 1'b0; + if(((5'h06 <= ALU2_maskME) || (ALU2_maskMB <= 5'h06)))begin + ALU2_maskInvt[25] = 1'b1; + end + ALU2_maskInvt[26] = 1'b0; + if(((5'h05 <= ALU2_maskME) || (ALU2_maskMB <= 5'h05)))begin + ALU2_maskInvt[26] = 1'b1; + end + ALU2_maskInvt[27] = 1'b0; + if(((5'h04 <= ALU2_maskME) || (ALU2_maskMB <= 5'h04)))begin + ALU2_maskInvt[27] = 1'b1; + end + ALU2_maskInvt[28] = 1'b0; + if(((5'h03 <= ALU2_maskME) || (ALU2_maskMB <= 5'h03)))begin + ALU2_maskInvt[28] = 1'b1; + end + ALU2_maskInvt[29] = 1'b0; + if(((5'h02 <= ALU2_maskME) || (ALU2_maskMB <= 5'h02)))begin + ALU2_maskInvt[29] = 1'b1; + end + ALU2_maskInvt[30] = 1'b0; + if(((5'h01 <= ALU2_maskME) || (ALU2_maskMB <= 5'h01)))begin + ALU2_maskInvt[30] = 1'b1; + end + ALU2_maskInvt[31] = 1'b0; + if(((5'h0 <= ALU2_maskME) || (ALU2_maskMB <= 5'h0)))begin + ALU2_maskInvt[31] = 1'b1; + end + end + + always @ (*) begin + if((ALU2_maskMB <= ALU2_maskME))begin + ALU2_mask = ALU2_maskNorm; + end else begin + ALU2_mask = ALU2_maskInvt; + end + end + + assign _zz_250_ = execute_SRC1; + assign _zz_251_ = execute_SRC1; + always @ (*) begin + case(execute_DECODER_stageables_16) + `AluRimiCtrlEnum_defaultEncoding_ROT : begin + _zz_252_ = (_zz_93_ & ALU2_mask); + end + `AluRimiCtrlEnum_defaultEncoding_INS : begin + _zz_252_ = ((_zz_88_ & ALU2_mask) | (execute_SRC2 & (~ ALU2_mask))); + end + `AluRimiCtrlEnum_defaultEncoding_SHIFTL : begin + _zz_252_ = _zz_520_[31 : 0]; + end + `AluRimiCtrlEnum_defaultEncoding_SHIFTR : begin + _zz_252_ = _zz_521_[31 : 0]; + end + default : begin + _zz_252_ = _zz_522_[31 : 0]; + end + endcase + end + + assign ALU2_rimi = _zz_252_; + always @ (*) begin + ALU2_sraw_ca = 1'b0; + if((ALU2_amount != 5'h0))begin + ALU2_sraw_ca = (execute_SRC1[31] && ((ALU2_sraw_wtf & execute_SRC1) != 32'h0)); + end + end + + assign ALU2_sraw_wtf = (_zz_526_ >>> _zz_527_); + always @ (*) begin + ALU2_rimi_enc_cr[1] = ALU2_rimi[31]; + ALU2_rimi_enc_cr[0] = (ALU2_rimi == 32'h0); + end + + always @ (*) begin + case(ALU2_rimi_enc_cr) + 2'b00 : begin + ALU2_rimi_cr = (3'b010); + end + 2'b01 : begin + ALU2_rimi_cr = (3'b001); + end + default : begin + ALU2_rimi_cr = (3'b100); + end + endcase + end + + always @ (*) begin + _zz_253_[0] = execute_SRC1[31]; + _zz_253_[1] = execute_SRC1[30]; + _zz_253_[2] = execute_SRC1[29]; + _zz_253_[3] = execute_SRC1[28]; + _zz_253_[4] = execute_SRC1[27]; + _zz_253_[5] = execute_SRC1[26]; + _zz_253_[6] = execute_SRC1[25]; + _zz_253_[7] = execute_SRC1[24]; + _zz_253_[8] = execute_SRC1[23]; + _zz_253_[9] = execute_SRC1[22]; + _zz_253_[10] = execute_SRC1[21]; + _zz_253_[11] = execute_SRC1[20]; + _zz_253_[12] = execute_SRC1[19]; + _zz_253_[13] = execute_SRC1[18]; + _zz_253_[14] = execute_SRC1[17]; + _zz_253_[15] = execute_SRC1[16]; + _zz_253_[16] = execute_SRC1[15]; + _zz_253_[17] = execute_SRC1[14]; + _zz_253_[18] = execute_SRC1[13]; + _zz_253_[19] = execute_SRC1[12]; + _zz_253_[20] = execute_SRC1[11]; + _zz_253_[21] = execute_SRC1[10]; + _zz_253_[22] = execute_SRC1[9]; + _zz_253_[23] = execute_SRC1[8]; + _zz_253_[24] = execute_SRC1[7]; + _zz_253_[25] = execute_SRC1[6]; + _zz_253_[26] = execute_SRC1[5]; + _zz_253_[27] = execute_SRC1[4]; + _zz_253_[28] = execute_SRC1[3]; + _zz_253_[29] = execute_SRC1[2]; + _zz_253_[30] = execute_SRC1[1]; + _zz_253_[31] = execute_SRC1[0]; + end + + always @ (*) begin + cntzero_msb = 6'h0; + if(_zz_253_[31])begin + cntzero_msb = 6'h1f; + end + if(_zz_253_[30])begin + cntzero_msb = 6'h1e; + end + if(_zz_253_[29])begin + cntzero_msb = 6'h1d; + end + if(_zz_253_[28])begin + cntzero_msb = 6'h1c; + end + if(_zz_253_[27])begin + cntzero_msb = 6'h1b; + end + if(_zz_253_[26])begin + cntzero_msb = 6'h1a; + end + if(_zz_253_[25])begin + cntzero_msb = 6'h19; + end + if(_zz_253_[24])begin + cntzero_msb = 6'h18; + end + if(_zz_253_[23])begin + cntzero_msb = 6'h17; + end + if(_zz_253_[22])begin + cntzero_msb = 6'h16; + end + if(_zz_253_[21])begin + cntzero_msb = 6'h15; + end + if(_zz_253_[20])begin + cntzero_msb = 6'h14; + end + if(_zz_253_[19])begin + cntzero_msb = 6'h13; + end + if(_zz_253_[18])begin + cntzero_msb = 6'h12; + end + if(_zz_253_[17])begin + cntzero_msb = 6'h11; + end + if(_zz_253_[16])begin + cntzero_msb = 6'h10; + end + if(_zz_253_[15])begin + cntzero_msb = 6'h0f; + end + if(_zz_253_[14])begin + cntzero_msb = 6'h0e; + end + if(_zz_253_[13])begin + cntzero_msb = 6'h0d; + end + if(_zz_253_[12])begin + cntzero_msb = 6'h0c; + end + if(_zz_253_[11])begin + cntzero_msb = 6'h0b; + end + if(_zz_253_[10])begin + cntzero_msb = 6'h0a; + end + if(_zz_253_[9])begin + cntzero_msb = 6'h09; + end + if(_zz_253_[8])begin + cntzero_msb = 6'h08; + end + if(_zz_253_[7])begin + cntzero_msb = 6'h07; + end + if(_zz_253_[6])begin + cntzero_msb = 6'h06; + end + if(_zz_253_[5])begin + cntzero_msb = 6'h05; + end + if(_zz_253_[4])begin + cntzero_msb = 6'h04; + end + if(_zz_253_[3])begin + cntzero_msb = 6'h03; + end + if(_zz_253_[2])begin + cntzero_msb = 6'h02; + end + if(_zz_253_[1])begin + cntzero_msb = 6'h01; + end + if(_zz_253_[0])begin + cntzero_msb = 6'h0; + end + end + + always @ (*) begin + if((cntzero_msb == 6'h0))begin + if(execute_SRC1[31])begin + cntzero_lz = 6'h0; + end else begin + cntzero_lz = 6'h20; + end + end else begin + cntzero_lz = cntzero_msb; + end + end + + always @ (*) begin + cntzero_lsb = 6'h0; + if(execute_SRC1[31])begin + cntzero_lsb = 6'h1f; + end + if(execute_SRC1[30])begin + cntzero_lsb = 6'h1e; + end + if(execute_SRC1[29])begin + cntzero_lsb = 6'h1d; + end + if(execute_SRC1[28])begin + cntzero_lsb = 6'h1c; + end + if(execute_SRC1[27])begin + cntzero_lsb = 6'h1b; + end + if(execute_SRC1[26])begin + cntzero_lsb = 6'h1a; + end + if(execute_SRC1[25])begin + cntzero_lsb = 6'h19; + end + if(execute_SRC1[24])begin + cntzero_lsb = 6'h18; + end + if(execute_SRC1[23])begin + cntzero_lsb = 6'h17; + end + if(execute_SRC1[22])begin + cntzero_lsb = 6'h16; + end + if(execute_SRC1[21])begin + cntzero_lsb = 6'h15; + end + if(execute_SRC1[20])begin + cntzero_lsb = 6'h14; + end + if(execute_SRC1[19])begin + cntzero_lsb = 6'h13; + end + if(execute_SRC1[18])begin + cntzero_lsb = 6'h12; + end + if(execute_SRC1[17])begin + cntzero_lsb = 6'h11; + end + if(execute_SRC1[16])begin + cntzero_lsb = 6'h10; + end + if(execute_SRC1[15])begin + cntzero_lsb = 6'h0f; + end + if(execute_SRC1[14])begin + cntzero_lsb = 6'h0e; + end + if(execute_SRC1[13])begin + cntzero_lsb = 6'h0d; + end + if(execute_SRC1[12])begin + cntzero_lsb = 6'h0c; + end + if(execute_SRC1[11])begin + cntzero_lsb = 6'h0b; + end + if(execute_SRC1[10])begin + cntzero_lsb = 6'h0a; + end + if(execute_SRC1[9])begin + cntzero_lsb = 6'h09; + end + if(execute_SRC1[8])begin + cntzero_lsb = 6'h08; + end + if(execute_SRC1[7])begin + cntzero_lsb = 6'h07; + end + if(execute_SRC1[6])begin + cntzero_lsb = 6'h06; + end + if(execute_SRC1[5])begin + cntzero_lsb = 6'h05; + end + if(execute_SRC1[4])begin + cntzero_lsb = 6'h04; + end + if(execute_SRC1[3])begin + cntzero_lsb = 6'h03; + end + if(execute_SRC1[2])begin + cntzero_lsb = 6'h02; + end + if(execute_SRC1[1])begin + cntzero_lsb = 6'h01; + end + if(execute_SRC1[0])begin + cntzero_lsb = 6'h0; + end + end + + always @ (*) begin + if((cntzero_lsb == 6'h0))begin + if(execute_SRC1[0])begin + cntzero_tz = 6'h0; + end else begin + cntzero_tz = 6'h20; + end + end else begin + cntzero_tz = cntzero_lsb; + end + end + + assign _zz_254_ = execute_SRC1[31 : 24]; + assign popcnt_pb3 = _zz_87_; + assign _zz_255_ = execute_SRC1[23 : 16]; + assign popcnt_pb2 = _zz_86_; + assign _zz_256_ = execute_SRC1[15 : 8]; + assign popcnt_pb1 = _zz_85_; + assign _zz_257_ = execute_SRC1[7 : 0]; + assign popcnt_pb0 = _zz_84_; + assign _zz_258_ = execute_SRC1[31 : 0]; + assign popcnt_pw0 = _zz_83_; + always @ (*) begin + if((execute_SRC1[31 : 24] == execute_SRC2[31 : 24]))begin + popcnt_cmpb[31 : 24] = 8'hff; + end else begin + popcnt_cmpb[31 : 24] = 8'h0; + end + if((execute_SRC1[23 : 16] == execute_SRC2[23 : 16]))begin + popcnt_cmpb[23 : 16] = 8'hff; + end else begin + popcnt_cmpb[23 : 16] = 8'h0; + end + if((execute_SRC1[15 : 8] == execute_SRC2[15 : 8]))begin + popcnt_cmpb[15 : 8] = 8'hff; + end else begin + popcnt_cmpb[15 : 8] = 8'h0; + end + if((execute_SRC1[7 : 0] == execute_SRC2[7 : 0]))begin + popcnt_cmpb[7 : 0] = 8'hff; + end else begin + popcnt_cmpb[7 : 0] = 8'h0; + end + end + + assign popcnt_prtyw = (((execute_SRC1[24] ^ execute_SRC1[16]) ^ execute_SRC1[8]) ^ execute_SRC1[0]); + always @ (*) begin + case(execute_DECODER_stageables_0) + `AluSpecCtrlEnum_defaultEncoding_CNTLZW : begin + ALU2_spec = {26'h0,cntzero_lz}; + end + `AluSpecCtrlEnum_defaultEncoding_CNTTZW : begin + ALU2_spec = {26'h0,cntzero_tz}; + end + `AluSpecCtrlEnum_defaultEncoding_POPCNTB : begin + ALU2_spec = {{{{{{{(4'b0000),popcnt_pb3},(4'b0000)},popcnt_pb2},(4'b0000)},popcnt_pb1},(4'b0000)},popcnt_pb0}; + end + `AluSpecCtrlEnum_defaultEncoding_POPCNTW : begin + ALU2_spec = {26'h0,popcnt_pw0}; + end + `AluSpecCtrlEnum_defaultEncoding_CMPB : begin + ALU2_spec = popcnt_cmpb; + end + default : begin + ALU2_spec = {31'h0,popcnt_prtyw}; + end + endcase + end + + always @ (*) begin + case(_zz_441_) + 8'b10000000 : begin + _zz_259_ = {_zz_529_[31 : 28],28'h0}; + end + 8'b01000000 : begin + _zz_259_ = {{(4'b0000),_zz_530_[27 : 24]},24'h0}; + end + 8'b00100000 : begin + _zz_259_ = {{8'h0,_zz_531_[23 : 20]},20'h0}; + end + 8'b00010000 : begin + _zz_259_ = {{12'h0,_zz_532_[19 : 16]},16'h0}; + end + 8'b00001000 : begin + _zz_259_ = {{16'h0,_zz_533_[15 : 12]},12'h0}; + end + 8'b00000100 : begin + _zz_259_ = {{20'h0,_zz_534_[11 : 8]},8'h0}; + end + 8'b00000010 : begin + _zz_259_ = {{24'h0,_zz_535_[7 : 4]},(4'b0000)}; + end + default : begin + _zz_259_ = {28'h0,_zz_536_[3 : 0]}; + end + endcase + end + + always @ (*) begin + case(_zz_442_) + 3'b000 : begin + _zz_260_ = _zz_537_[31]; + end + 3'b001 : begin + _zz_260_ = _zz_538_[27]; + end + 3'b010 : begin + _zz_260_ = _zz_539_[23]; + end + 3'b011 : begin + _zz_260_ = _zz_540_[19]; + end + 3'b100 : begin + _zz_260_ = _zz_541_[15]; + end + 3'b101 : begin + _zz_260_ = _zz_542_[11]; + end + 3'b110 : begin + _zz_260_ = _zz_543_[7]; + end + default : begin + _zz_260_ = _zz_544_[3]; + end + endcase + end + + always @ (*) begin + case(_zz_443_) + 3'b000 : begin + _zz_261_ = _zz_545_[30]; + end + 3'b001 : begin + _zz_261_ = _zz_546_[26]; + end + 3'b010 : begin + _zz_261_ = _zz_547_[22]; + end + 3'b011 : begin + _zz_261_ = _zz_548_[18]; + end + 3'b100 : begin + _zz_261_ = _zz_549_[14]; + end + 3'b101 : begin + _zz_261_ = _zz_550_[10]; + end + 3'b110 : begin + _zz_261_ = _zz_551_[6]; + end + default : begin + _zz_261_ = _zz_552_[2]; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_BIT_1 : begin + _zz_262_ = ALU2_bitwise; + end + `AluCtrlEnum_defaultEncoding_ADD : begin + _zz_262_ = execute_SRC_ADD; + end + `AluCtrlEnum_defaultEncoding_RIMI : begin + _zz_262_ = ALU2_rimi; + end + default : begin + _zz_262_ = ALU2_spec; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_12) + `TgtCtrlEnum_defaultEncoding_RT : begin + _zz_263_ = execute_INSTRUCTION[25 : 21]; + end + default : begin + _zz_263_ = execute_INSTRUCTION[20 : 16]; + end + endcase + end + + always @ (*) begin + if(execute_DECODER_stageables_6)begin + _zz_79_ = 11'h402; + end else begin + if(execute_DECODER_stageables_14)begin + _zz_79_ = 11'h401; + end else begin + _zz_79_ = {{(1'b0),execute_INSTRUCTION[15 : 11]},execute_INSTRUCTION[20 : 16]}; + end + end + end + + always @ (*) begin + ALU2_xer_ca = 1'b0; + if((execute_DECODER_stageables_16 == `AluRimiCtrlEnum_defaultEncoding_SHIFTRA))begin + ALU2_xer_ca = ALU2_sraw_ca; + end else begin + ALU2_xer_ca = execute_SRC_CAOV[1]; + end + end + + assign ALU2_xer_ov = execute_SRC_CAOV[0]; + assign ALU2_xer_so = (ALU2_XER[31] || ALU2_xer_ov); + assign ALU2_xerBus_validOV = (execute_DECODER_stageables_18 && execute_INSTRUCTION[10]); + assign ALU2_xerBus_validCA = execute_DECODER_stageables_11; + assign ALU2_xerBus_imm = {ALU2_xer_ov,ALU2_xer_ca}; + always @ (*) begin + case(execute_SRC_CR) + 2'b00 : begin + ALU2_alu_cr = (3'b010); + end + 2'b01 : begin + ALU2_alu_cr = (3'b001); + end + default : begin + ALU2_alu_cr = (3'b100); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_8) + `AluCtrlEnum_defaultEncoding_BIT_1 : begin + ALU2_cr0_val_a = ALU2_bitwise_cr; + end + `AluCtrlEnum_defaultEncoding_ADD : begin + ALU2_cr0_val_a = ALU2_alu_cr; + end + `AluCtrlEnum_defaultEncoding_RIMI : begin + ALU2_cr0_val_a = ALU2_rimi_cr; + end + default : begin + ALU2_cr0_val_a = (3'b000); + end + endcase + end + + assign ALU2_cr0_val = {ALU2_cr0_val_a,ALU2_xer_so}; + assign ALU2_cr_record = ((! execute_DECODER_stageables_21) && (execute_DECODER_stageables_57 || (execute_DECODER_stageables_28 && (execute_INSTRUCTION[0] == 1'b1)))); + assign ALU2_cr_mcrf = (execute_DECODER_stageables_51 == `CRMoveCtrlEnum_defaultEncoding_MCRF); + assign ALU2_cr_update_valid = (((ALU2_cr_record || execute_DECODER_stageables_34) || execute_DECODER_stageables_46) || execute_DECODER_stageables_21); + always @ (*) begin + if(ALU2_cr_record)begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + if(execute_DECODER_stageables_21)begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_CMP; + end else begin + if(execute_DECODER_stageables_34)begin + case(execute_DECODER_stageables_20) + `CRLogCtrlEnum_defaultEncoding_AND_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_AND_1; + end + `CRLogCtrlEnum_defaultEncoding_OR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_OR_1; + end + `CRLogCtrlEnum_defaultEncoding_XOR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_XOR_1; + end + `CRLogCtrlEnum_defaultEncoding_NAND_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NAND_1; + end + `CRLogCtrlEnum_defaultEncoding_NOR_1 : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NOR_1; + end + `CRLogCtrlEnum_defaultEncoding_EQV : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_EQV; + end + `CRLogCtrlEnum_defaultEncoding_ANDC : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_ANDC; + end + default : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_ORC; + end + endcase + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRF : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MCRF; + end + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MTCRF; + end + default : begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_MTCRF; + end + endcase + end else begin + ALU2_crBus_op = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_ba = execute_INSTRUCTION[20 : 16]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_ba = {(2'b00),execute_INSTRUCTION[20 : 18]}; + end else begin + ALU2_crBus_ba = 5'h0; + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_bb = execute_INSTRUCTION[15 : 11]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_bb = 5'h0; + end else begin + ALU2_crBus_bb = 5'h0; + end + end + end + + always @ (*) begin + if(execute_DECODER_stageables_34)begin + ALU2_crBus_bt = execute_INSTRUCTION[25 : 21]; + end else begin + if(ALU2_cr_mcrf)begin + ALU2_crBus_bt = {(2'b00),execute_INSTRUCTION[25 : 23]}; + end else begin + ALU2_crBus_bt = 5'h0; + end + end + end + + always @ (*) begin + if(ALU2_cr_record)begin + ALU2_crBus_imm = {28'h0,ALU2_cr0_val}; + end else begin + if(execute_DECODER_stageables_21)begin + ALU2_crBus_imm = {28'h0,ALU2_cr0_val}; + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_imm = {{{{28'h0,ALU2_XER[30]},ALU2_XER[19]},ALU2_XER[29]},ALU2_XER[18]}; + end + default : begin + ALU2_crBus_imm = execute_SRC1; + end + endcase + end else begin + ALU2_crBus_imm = 32'h0; + end + end + end + end + + always @ (*) begin + ALU2_crBus_fxm = 8'h0; + if(execute_DECODER_stageables_21)begin + ALU2_crBus_fxm[_zz_555_] = 1'b1; + end else begin + if(execute_DECODER_stageables_46)begin + case(execute_DECODER_stageables_51) + `CRMoveCtrlEnum_defaultEncoding_MCRXRX : begin + ALU2_crBus_fxm = execute_INSTRUCTION[19 : 12]; + end + default : begin + ALU2_crBus_fxm = execute_INSTRUCTION[19 : 12]; + end + endcase + end + end + end + + assign _zz_76_ = ALU2_crBus_op; + always @ (*) begin + if(ALU2_cr_update_valid)begin + case(ALU2_crBus_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_75_ = 8'h80; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_75_ = 8'h40; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_75_ = 8'h02; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_75_ = ALU2_crBus_fxm; + end + default : begin + _zz_75_ = 8'hff; + end + endcase + end else begin + _zz_75_ = 8'h0; + end + end + + assign SRC1_ra = execute_INSTRUCTION[20 : 16]; + assign SRC1_rb = execute_INSTRUCTION[15 : 11]; + assign SRC1_rs = execute_INSTRUCTION[25 : 21]; + assign SRC1_rt = execute_INSTRUCTION[25 : 21]; + always @ (*) begin + case(execute_DECODER_stageables_38) + `Src1CtrlEnum_defaultEncoding_RA : begin + _zz_264_ = _zz_73_; + end + `Src1CtrlEnum_defaultEncoding_RA_N : begin + _zz_264_ = (~ _zz_73_); + end + `Src1CtrlEnum_defaultEncoding_RA_0 : begin + _zz_264_ = _zz_556_; + end + `Src1CtrlEnum_defaultEncoding_RA_NIA : begin + _zz_264_ = _zz_72_; + end + default : begin + _zz_264_ = execute_RS; + end + endcase + end + + assign _zz_265_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_266_[15] = _zz_265_; + _zz_266_[14] = _zz_265_; + _zz_266_[13] = _zz_265_; + _zz_266_[12] = _zz_265_; + _zz_266_[11] = _zz_265_; + _zz_266_[10] = _zz_265_; + _zz_266_[9] = _zz_265_; + _zz_266_[8] = _zz_265_; + _zz_266_[7] = _zz_265_; + _zz_266_[6] = _zz_265_; + _zz_266_[5] = _zz_265_; + _zz_266_[4] = _zz_265_; + _zz_266_[3] = _zz_265_; + _zz_266_[2] = _zz_265_; + _zz_266_[1] = _zz_265_; + _zz_266_[0] = _zz_265_; + end + + always @ (*) begin + case(execute_DECODER_stageables_26) + `Src2CtrlEnum_defaultEncoding_RB : begin + _zz_267_ = execute_RB; + end + `Src2CtrlEnum_defaultEncoding_RB_0 : begin + _zz_267_ = _zz_557_; + end + `Src2CtrlEnum_defaultEncoding_RB_M1 : begin + _zz_267_ = _zz_558_; + end + `Src2CtrlEnum_defaultEncoding_RB_UI : begin + _zz_267_ = {16'h0,execute_INSTRUCTION[15 : 0]}; + end + `Src2CtrlEnum_defaultEncoding_RB_SI : begin + _zz_267_ = {_zz_266_,execute_INSTRUCTION[15 : 0]}; + end + `Src2CtrlEnum_defaultEncoding_RB_SH : begin + _zz_267_ = {execute_INSTRUCTION[15 : 0],16'h0}; + end + `Src2CtrlEnum_defaultEncoding_RB_PCISD : begin + _zz_267_ = {{{execute_INSTRUCTION[15 : 6],execute_INSTRUCTION[20 : 16]},execute_INSTRUCTION[0]},16'h0004}; + end + default : begin + _zz_267_ = _zz_73_; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_1) + `Src3CtrlEnum_defaultEncoding_CA : begin + _zz_268_ = execute_XER_CA; + end + `Src3CtrlEnum_defaultEncoding_CA_0 : begin + _zz_268_ = (1'b0); + end + default : begin + _zz_268_ = (1'b1); + end + endcase + end + + assign SRC2_ra = execute_SRC1; + assign SRC2_rb = execute_SRC2; + assign SRC2_cin = execute_SRC3; + assign SRC2_adder = (_zz_559_ + _zz_560_); + assign SRC2_add_cr = {SRC2_adder[31],(SRC2_adder[31 : 0] == 32'h0)}; + assign SRC2_cmp_cr = (execute_DECODER_stageables_48 ? {(SRC2_ra < SRC2_rb),(SRC2_ra == SRC2_rb)} : {($signed(_zz_561_) < $signed(_zz_562_)),(SRC2_ra == SRC2_rb)}); + assign SRC2_ca = SRC2_adder[32]; + assign SRC2_ov = ((SRC2_adder[32] ^ SRC2_adder[31]) && (! (SRC2_ra[31] ^ SRC2_rb[31]))); + assign UpdateRegFileWrite_valid = _zz_269_; + assign UpdateRegFileWrite_payload_address = _zz_270_; + assign UpdateRegFileWrite_payload_data = _zz_271_; + assign MUL1_a = execute_SRC1; + assign MUL1_b = execute_SRC2; + assign MUL1_aSigned = execute_DECODER_stageables_35; + assign MUL1_bSigned = execute_DECODER_stageables_35; + assign MUL1_aULow = MUL1_a[15 : 0]; + assign MUL1_bULow = MUL1_b[15 : 0]; + assign MUL1_aSLow = {1'b0,MUL1_a[15 : 0]}; + assign MUL1_bSLow = {1'b0,MUL1_b[15 : 0]}; + assign MUL1_aHigh = {(MUL1_aSigned && MUL1_a[31]),MUL1_a[31 : 16]}; + assign MUL1_bHigh = {(MUL1_bSigned && MUL1_b[31]),MUL1_b[31 : 16]}; + assign MUL3_result = ($signed(_zz_563_) + $signed(_zz_564_)); + assign MUL3_xer_ov = MUL3_result[32]; + always @ (*) begin + MUL3_xer_so = 1'b0; + if((writeBack_DECODER_stageables_36 && writeBack_INSTRUCTION[10]))begin + MUL3_xer_so = (writeBack_XER_SO || MUL3_xer_ov); + end else begin + MUL3_xer_so = writeBack_XER_SO; + end + end + + always @ (*) begin + if(writeBack_DECODER_stageables_55)begin + MUL3_result32 = _zz_565_; + end else begin + MUL3_result32 = _zz_566_; + end + end + + assign MUL3_cr = {MUL3_result32[31],(MUL3_result32[31 : 0] == 32'h0)}; + always @ (*) begin + case(writeBack_SRC_CR) + 2'b00 : begin + MUL3_cr_decode = {(3'b010),MUL3_xer_so}; + end + 2'b01 : begin + MUL3_cr_decode = {(3'b001),MUL3_xer_so}; + end + default : begin + MUL3_cr_decode = {(3'b100),MUL3_xer_so}; + end + endcase + end + + always @ (*) begin + _zz_272_ = 1'b0; + if(_zz_400_)begin + _zz_272_ = 1'b1; + end + end + + always @ (*) begin + _zz_273_ = (5'bxxxxx); + if(MUL3_cr_record)begin + _zz_273_ = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + _zz_273_ = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + + always @ (*) begin + _zz_274_ = 32'h0; + _zz_274_ = {28'h0,MUL3_cr_decode}; + end + + assign MUL3_cr_record = (writeBack_DECODER_stageables_24 && writeBack_INSTRUCTION[0]); + assign MULDIV_frontendOk = 1'b1; + always @ (*) begin + MULDIV1_counter_willIncrement = 1'b0; + if(_zz_399_)begin + if(_zz_422_)begin + MULDIV1_counter_willIncrement = 1'b1; + end + end + end + + always @ (*) begin + MULDIV1_counter_willClear = 1'b0; + if(_zz_423_)begin + MULDIV1_counter_willClear = 1'b1; + end + end + + assign MULDIV1_counter_willOverflowIfInc = (MULDIV1_counter_value == 6'h21); + assign MULDIV1_counter_willOverflow = (MULDIV1_counter_willOverflowIfInc && MULDIV1_counter_willIncrement); + always @ (*) begin + if(MULDIV1_counter_willOverflow)begin + MULDIV1_counter_valueNext = 6'h0; + end else begin + MULDIV1_counter_valueNext = (MULDIV1_counter_value + _zz_568_); + end + if(MULDIV1_counter_willClear)begin + MULDIV1_counter_valueNext = 6'h0; + end + end + + always @ (*) begin + MULDIV1_crBusPort_valid = 1'b0; + if(_zz_399_)begin + MULDIV1_crBusPort_valid = 1'b1; + end + end + + always @ (*) begin + MULDIV1_crBusPort_payload_op = (5'bxxxxx); + if(_zz_399_)begin + if(memory_INSTRUCTION[0])begin + MULDIV1_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_CR0; + end else begin + MULDIV1_crBusPort_payload_op = `CRBusCmdEnum_defaultEncoding_NOP; + end + end + end + + assign MULDIV1_crBusPort_payload_ba = 5'h0; + assign MULDIV1_crBusPort_payload_bb = 5'h0; + assign MULDIV1_crBusPort_payload_bt = 5'h0; + always @ (*) begin + MULDIV1_crBusPort_payload_imm = 32'h0; + if(_zz_399_)begin + MULDIV1_crBusPort_payload_imm = {28'h0,_zz_279_}; + end + end + + assign MULDIV1_crBusPort_payload_fxm = 8'h0; + always @ (*) begin + MULDIV1_xerBusPort_valid = 1'b0; + if(_zz_399_)begin + MULDIV1_xerBusPort_valid = 1'b1; + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_validOV = 1'bx; + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_validOV = 1'b0; + if(_zz_424_)begin + MULDIV1_xerBusPort_payload_validOV = 1'b1; + end + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_validCA = 1'bx; + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_validCA = 1'b0; + end + end + + always @ (*) begin + MULDIV1_xerBusPort_payload_imm = (2'bxx); + if(_zz_399_)begin + MULDIV1_xerBusPort_payload_imm = {_zz_277_,(1'b0)}; + end + end + + assign _zz_275_ = MULDIV_rs1[31 : 0]; + assign MULDIV1_stage_0_remainderShifted = {MULDIV_accumulator[31 : 0],_zz_275_[31]}; + assign MULDIV1_stage_0_remainderMinusDenominator = (MULDIV1_stage_0_remainderShifted - _zz_569_); + assign MULDIV1_stage_0_outRemainder = ((! MULDIV1_stage_0_remainderMinusDenominator[32]) ? _zz_570_ : _zz_571_); + assign MULDIV1_stage_0_outNumerator = _zz_572_[31:0]; + assign _zz_276_ = (memory_DECODER_stageables_15 ? MULDIV_accumulator[31 : 0] : MULDIV_rs1[31 : 0]); + assign _zz_277_ = (MULDIV_rs2 == 32'h0); + always @ (*) begin + _zz_278_ = 1'b0; + if(_zz_424_)begin + _zz_278_ = (memory_XER_SO || _zz_277_); + end else begin + _zz_278_ = memory_XER_SO; + end + end + + always @ (*) begin + case(memory_SRC_CR) + 2'b00 : begin + _zz_279_ = {(3'b010),_zz_278_}; + end + 2'b01 : begin + _zz_279_ = {(3'b001),_zz_278_}; + end + default : begin + _zz_279_ = {(3'b100),_zz_278_}; + end + endcase + end + + assign _zz_280_ = (execute_SRC2[31] && execute_DECODER_stageables_3); + assign _zz_281_ = (1'b0 || ((execute_DECODER_stageables_43 && execute_SRC1[31]) && execute_DECODER_stageables_29)); + always @ (*) begin + _zz_282_[32] = (execute_DECODER_stageables_29 && execute_SRC1[31]); + _zz_282_[31 : 0] = execute_SRC1; + end + + always @ (*) begin + _zz_283_ = 1'b0; + if(_zz_425_)begin + if(_zz_426_)begin + if(_zz_287_)begin + _zz_283_ = 1'b1; + end + end + end + if(_zz_427_)begin + if(_zz_428_)begin + if(_zz_290_)begin + _zz_283_ = 1'b1; + end + end + end + if(_zz_429_)begin + if(_zz_430_)begin + if(_zz_293_)begin + _zz_283_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_10))begin + _zz_283_ = 1'b0; + end + end + + always @ (*) begin + _zz_284_ = 1'b0; + if(_zz_425_)begin + if(_zz_426_)begin + if(_zz_288_)begin + _zz_284_ = 1'b1; + end + end + end + if(_zz_427_)begin + if(_zz_428_)begin + if(_zz_291_)begin + _zz_284_ = 1'b1; + end + end + end + if(_zz_429_)begin + if(_zz_430_)begin + if(_zz_294_)begin + _zz_284_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_47))begin + _zz_284_ = 1'b0; + end + end + + always @ (*) begin + _zz_285_ = 1'b0; + if((writeBack_arbitration_isValid && writeBack_DECODER_stageables_45))begin + if(((1'b0 || (! _zz_286_)) || (! 1'b1)))begin + if(_zz_289_)begin + _zz_285_ = 1'b1; + end + end + end + if((memory_arbitration_isValid && memory_DECODER_stageables_45))begin + if(((1'b0 || (! memory_DECODER_stageables_5)) || (! 1'b1)))begin + if(_zz_292_)begin + _zz_285_ = 1'b1; + end + end + end + if((execute_arbitration_isValid && execute_DECODER_stageables_45))begin + if(((1'b0 || (! execute_DECODER_stageables_25)) || (! 1'b1)))begin + if(_zz_295_)begin + _zz_285_ = 1'b1; + end + end + end + if((! decode_DECODER_stageables_50))begin + _zz_285_ = 1'b0; + end + end + + assign Hazards_writeBackWrites_valid = (_zz_102_ && writeBack_arbitration_isFiring); + assign Hazards_writeBackWrites_payload_address = writeBack_RT_ADDR; + assign Hazards_writeBackWrites_payload_data = _zz_121_; + assign Hazards_addr0Match = (Hazards_writeBackBuffer_payload_address == decode_R0_ADDR); + assign Hazards_addr1Match = (Hazards_writeBackBuffer_payload_address == decode_R1_ADDR); + assign Hazards_addr2Match = (Hazards_writeBackBuffer_payload_address == decode_R2_ADDR); + assign _zz_286_ = 1'b1; + assign _zz_287_ = (writeBack_RT_ADDR == decode_R0_ADDR); + assign _zz_288_ = (writeBack_RT_ADDR == decode_R1_ADDR); + assign _zz_289_ = (writeBack_RT_ADDR == decode_R2_ADDR); + assign _zz_290_ = (memory_RT_ADDR == decode_R0_ADDR); + assign _zz_291_ = (memory_RT_ADDR == decode_R1_ADDR); + assign _zz_292_ = (memory_RT_ADDR == decode_R2_ADDR); + assign _zz_293_ = (execute_RT_ADDR == decode_R0_ADDR); + assign _zz_294_ = (execute_RT_ADDR == decode_R1_ADDR); + assign _zz_295_ = (execute_RT_ADDR == decode_R2_ADDR); + always @ (*) begin + _zz_296_ = 1'b0; + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + if(! _zz_303_) begin + _zz_296_ = 1'b1; + end + end else begin + _zz_296_ = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_297_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_297_ = (_zz_309_ && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_298_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_298_ = (((execute_DECODER_stageables_54 && (execute_SPR_ID == 11'h001)) || _zz_308_) && (memory_XER_WRITE_validCA || memory_XER_WRITE_validOV)); + end + end + + always @ (*) begin + _zz_299_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_299_ = ((memory_DECODER_stageables_32 && (memory_SPR_ID == 11'h001)) && _zz_308_); + end + end + + always @ (*) begin + _zz_300_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_300_ = ((((((memory_SPR_ID == _zz_1580_) && memory_DECODER_stageables_32) && _zz_311_) || (((memory_SPR_ID == _zz_1581_) && memory_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCCTR))) || (((memory_SPR_ID == 11'h32f) && memory_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCTAR))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_301_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_301_ = (((memory_BRANCH_LINK && ((execute_SPR_ID == 11'h008) && (! execute_DECODER_stageables_32))) || (memory_BRANCH_DEC && ((execute_SPR_ID == 11'h009) && (! execute_DECODER_stageables_32)))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_302_ = 1'b0; + if((memory_arbitration_isValid && execute_arbitration_isValid))begin + _zz_302_ = (((memory_BRANCH_LINK && _zz_311_) || (memory_BRANCH_DEC && execute_BRANCH_DEC)) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_303_ = 1'b0; + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + _zz_303_ = (_zz_305_ && _zz_306_); + end + end + end + end + + always @ (*) begin + _zz_304_ = (4'b0000); + if(_zz_431_)begin + if(_zz_432_)begin + if(_zz_433_)begin + if(_zz_303_)begin + _zz_304_ = memory_CR_WRITE_imm[3 : 0]; + end + end + end + end + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_305_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + _zz_305_ = 1'b1; + end + default : begin + _zz_305_ = 1'b0; + end + endcase + end + + always @ (*) begin + _zz_306_ = 1'b0; + if((! (memory_DECODER_stageables_31 || memory_DECODER_stageables_43)))begin + _zz_306_ = _zz_307_; + end + end + + always @ (*) begin + case(memory_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_307_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_307_ = 1'b1; + end + default : begin + _zz_307_ = 1'b0; + end + endcase + end + + assign _zz_308_ = (execute_DECODER_stageables_1 == `Src3CtrlEnum_defaultEncoding_CA); + always @ (*) begin + _zz_309_ = 1'b0; + if(memory_DECODER_stageables_32)begin + _zz_309_ = _zz_310_; + end + end + + always @ (*) begin + case(_zz_444_) + 2'b10 : begin + _zz_310_ = 1'b1; + end + 2'b01 : begin + _zz_310_ = execute_DECODER_stageables_54; + end + default : begin + _zz_310_ = (execute_DECODER_stageables_54 && (execute_SPR_ID == memory_SPR_ID)); + end + endcase + end + + assign _zz_311_ = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCLR); + always @ (*) begin + _zz_312_ = 1'b0; + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + if(! _zz_319_) begin + _zz_312_ = 1'b1; + end + end else begin + _zz_312_ = 1'b1; + end + end + end + end + + always @ (*) begin + _zz_313_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_313_ = (_zz_324_ && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_314_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_314_ = (((execute_DECODER_stageables_54 && (execute_SPR_ID == 11'h001)) || _zz_323_) && (writeBack_XER_WRITE_validCA || writeBack_XER_WRITE_validOV)); + end + end + + always @ (*) begin + _zz_315_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_315_ = ((writeBack_DECODER_stageables_32 && (writeBack_SPR_ID == 11'h001)) && _zz_323_); + end + end + + always @ (*) begin + _zz_316_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_316_ = ((((((writeBack_SPR_ID == 11'h008) && writeBack_DECODER_stageables_32) && _zz_326_) || (((writeBack_SPR_ID == 11'h009) && writeBack_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCCTR))) || (((writeBack_SPR_ID == 11'h32f) && writeBack_DECODER_stageables_32) && (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCTAR))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_317_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_317_ = (((writeBack_BRANCH_LINK && ((execute_SPR_ID == 11'h008) && (! execute_DECODER_stageables_32))) || (writeBack_BRANCH_DEC && ((execute_SPR_ID == 11'h009) && (! execute_DECODER_stageables_32)))) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_318_ = 1'b0; + if((writeBack_arbitration_isValid && execute_arbitration_isValid))begin + _zz_318_ = (((writeBack_BRANCH_LINK && _zz_326_) || (writeBack_BRANCH_DEC && execute_BRANCH_DEC)) && ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00))); + end + end + + always @ (*) begin + _zz_319_ = 1'b0; + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + _zz_319_ = (_zz_321_ && _zz_322_); + end + end + end + end + + always @ (*) begin + _zz_320_ = (4'b0000); + if(_zz_434_)begin + if(_zz_435_)begin + if(_zz_436_)begin + if(_zz_319_)begin + _zz_320_ = writeBack_CR_WRITE_imm[3 : 0]; + end + end + end + end + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_321_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + _zz_321_ = 1'b1; + end + default : begin + _zz_321_ = 1'b0; + end + endcase + end + + always @ (*) begin + case(writeBack_CR_WRITE_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + _zz_322_ = 1'b1; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + _zz_322_ = 1'b1; + end + default : begin + _zz_322_ = 1'b0; + end + endcase + end + + assign _zz_323_ = (execute_DECODER_stageables_1 == `Src3CtrlEnum_defaultEncoding_CA); + always @ (*) begin + _zz_324_ = 1'b0; + if(writeBack_DECODER_stageables_32)begin + _zz_324_ = _zz_325_; + end + end + + always @ (*) begin + case(_zz_445_) + 2'b10 : begin + _zz_325_ = 1'b1; + end + 2'b01 : begin + _zz_325_ = execute_DECODER_stageables_54; + end + default : begin + _zz_325_ = (execute_DECODER_stageables_54 && (execute_SPR_ID == writeBack_SPR_ID)); + end + endcase + end + + assign _zz_326_ = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BCLR); + always @ (*) begin + case(decode_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BC : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + decode_BranchPlugin_bc = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + decode_BranchPlugin_bc = 1'b1; + end + default : begin + decode_BranchPlugin_bc = 1'b0; + end + endcase + end + + assign decode_BranchPlugin_bi = decode_INSTRUCTION[20 : 16]; + assign decode_BranchPlugin_crbiField = decode_BranchPlugin_bi[4 : 2]; + assign decode_BranchPlugin_bo = decode_INSTRUCTION[25 : 21]; + assign decode_BranchPlugin_crbiRead = ((decode_BranchPlugin_bc && (! decode_BranchPlugin_bo[4])) && ((decode_DECODER_stageables_13 != `BranchCtrlEnum_defaultEncoding_BU) && (decode_DECODER_stageables_13 != `BranchCtrlEnum_defaultEncoding_NONE))); + always @ (*) begin + case(decode_BranchPlugin_crbiField) + 3'b000 : begin + decode_BranchPlugin_crFieldRd = {decode_BranchPlugin_crbiRead,7'h0}; + end + 3'b001 : begin + decode_BranchPlugin_crFieldRd = {{(1'b0),decode_BranchPlugin_crbiRead},6'h0}; + end + 3'b010 : begin + decode_BranchPlugin_crFieldRd = {{(2'b00),decode_BranchPlugin_crbiRead},5'h0}; + end + 3'b011 : begin + decode_BranchPlugin_crFieldRd = {{(3'b000),decode_BranchPlugin_crbiRead},(4'b0000)}; + end + 3'b100 : begin + decode_BranchPlugin_crFieldRd = {{(4'b0000),decode_BranchPlugin_crbiRead},(3'b000)}; + end + 3'b101 : begin + decode_BranchPlugin_crFieldRd = {{5'h0,decode_BranchPlugin_crbiRead},(2'b00)}; + end + 3'b110 : begin + decode_BranchPlugin_crFieldRd = {{6'h0,decode_BranchPlugin_crbiRead},(1'b0)}; + end + default : begin + decode_BranchPlugin_crFieldRd = {7'h0,decode_BranchPlugin_crbiRead}; + end + endcase + end + + always @ (*) begin + if(decode_BranchPlugin_crbiRead)begin + _zz_64_ = decode_BranchPlugin_crFieldRd; + end else begin + if(decode_DECODER_stageables_6)begin + _zz_64_ = 8'hff; + end else begin + _zz_64_ = 8'h0; + end + end + end + + assign execute_BranchPlugin_ctrOne = (execute_BranchPlugin_CTR == 32'h00000001); + always @ (*) begin + case(execute_SPR_ID) + 11'b00000001001 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_CTR; + end + 11'b00000001000 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_LR; + end + 11'b01100101111 : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_TAR; + end + default : begin + execute_BranchPlugin_sprReadData = execute_BranchPlugin_CR; + end + endcase + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000010 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b00000001001 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b00000001000 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + 11'b01100101111 : begin + execute_BranchPlugin_sprReadValid = execute_DECODER_stageables_54; + end + default : begin + execute_BranchPlugin_sprReadValid = 1'b0; + end + endcase + end + + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000010 : begin + execute_BranchPlugin_crReadValid = execute_DECODER_stageables_54; + end + default : begin + execute_BranchPlugin_crReadValid = 1'b0; + end + endcase + end + + assign sprReadBU_valid = execute_BranchPlugin_sprReadValid; + assign sprReadBU_payload_data = execute_BranchPlugin_sprReadData; + assign execute_BranchPlugin_crBusPort_valid = ((writeBack_RegFilePlugin_crBusPort_valid || _zz_272_) || MULDIV1_crBusPort_valid); + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_op = writeBack_RegFilePlugin_crBusPort_payload_op; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_op = _zz_273_; + end else begin + execute_BranchPlugin_crBusPort_op = MULDIV1_crBusPort_payload_op; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_ba = writeBack_RegFilePlugin_crBusPort_payload_ba; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_ba = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_ba = MULDIV1_crBusPort_payload_ba; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_bb = writeBack_RegFilePlugin_crBusPort_payload_bb; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_bb = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_bb = MULDIV1_crBusPort_payload_bb; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_bt = writeBack_RegFilePlugin_crBusPort_payload_bt; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_bt = 5'h0; + end else begin + execute_BranchPlugin_crBusPort_bt = MULDIV1_crBusPort_payload_bt; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_imm = writeBack_RegFilePlugin_crBusPort_payload_imm; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_imm = _zz_274_; + end else begin + execute_BranchPlugin_crBusPort_imm = MULDIV1_crBusPort_payload_imm; + end + end + end + + always @ (*) begin + if(writeBack_RegFilePlugin_crBusPort_valid)begin + execute_BranchPlugin_crBusPort_fxm = writeBack_RegFilePlugin_crBusPort_payload_fxm; + end else begin + if(_zz_272_)begin + execute_BranchPlugin_crBusPort_fxm = 8'h0; + end else begin + execute_BranchPlugin_crBusPort_fxm = MULDIV1_crBusPort_payload_fxm; + end + end + end + + always @ (*) begin + case(_zz_446_) + 3'b000 : begin + _zz_327_ = execute_BranchPlugin_CR[31 : 28]; + end + 3'b001 : begin + _zz_327_ = execute_BranchPlugin_CR[27 : 24]; + end + 3'b010 : begin + _zz_327_ = execute_BranchPlugin_CR[23 : 20]; + end + 3'b011 : begin + _zz_327_ = execute_BranchPlugin_CR[19 : 16]; + end + 3'b100 : begin + _zz_327_ = execute_BranchPlugin_CR[15 : 12]; + end + 3'b101 : begin + _zz_327_ = execute_BranchPlugin_CR[11 : 8]; + end + 3'b110 : begin + _zz_327_ = execute_BranchPlugin_CR[7 : 4]; + end + default : begin + _zz_327_ = execute_BranchPlugin_CR[3 : 0]; + end + endcase + end + + assign _zz_328_ = execute_BranchPlugin_crBusPort_imm[3 : 0]; + assign _zz_329_ = execute_INSTRUCTION[25]; + always @ (*) begin + _zz_330_[5] = _zz_329_; + _zz_330_[4] = _zz_329_; + _zz_330_[3] = _zz_329_; + _zz_330_[2] = _zz_329_; + _zz_330_[1] = _zz_329_; + _zz_330_[0] = _zz_329_; + end + + assign execute_BranchPlugin_li = {{_zz_330_,execute_INSTRUCTION[25 : 2]},(2'b00)}; + assign _zz_331_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_332_[15] = _zz_331_; + _zz_332_[14] = _zz_331_; + _zz_332_[13] = _zz_331_; + _zz_332_[12] = _zz_331_; + _zz_332_[11] = _zz_331_; + _zz_332_[10] = _zz_331_; + _zz_332_[9] = _zz_331_; + _zz_332_[8] = _zz_331_; + _zz_332_[7] = _zz_331_; + _zz_332_[6] = _zz_331_; + _zz_332_[5] = _zz_331_; + _zz_332_[4] = _zz_331_; + _zz_332_[3] = _zz_331_; + _zz_332_[2] = _zz_331_; + _zz_332_[1] = _zz_331_; + _zz_332_[0] = _zz_331_; + end + + assign execute_BranchPlugin_bd = {{_zz_332_,execute_INSTRUCTION[15 : 2]},(2'b00)}; + assign _zz_333_ = (! execute_INSTRUCTION[1]); + always @ (*) begin + execute_BranchPlugin_aaMask[31] = _zz_333_; + execute_BranchPlugin_aaMask[30] = _zz_333_; + execute_BranchPlugin_aaMask[29] = _zz_333_; + execute_BranchPlugin_aaMask[28] = _zz_333_; + execute_BranchPlugin_aaMask[27] = _zz_333_; + execute_BranchPlugin_aaMask[26] = _zz_333_; + execute_BranchPlugin_aaMask[25] = _zz_333_; + execute_BranchPlugin_aaMask[24] = _zz_333_; + execute_BranchPlugin_aaMask[23] = _zz_333_; + execute_BranchPlugin_aaMask[22] = _zz_333_; + execute_BranchPlugin_aaMask[21] = _zz_333_; + execute_BranchPlugin_aaMask[20] = _zz_333_; + execute_BranchPlugin_aaMask[19] = _zz_333_; + execute_BranchPlugin_aaMask[18] = _zz_333_; + execute_BranchPlugin_aaMask[17] = _zz_333_; + execute_BranchPlugin_aaMask[16] = _zz_333_; + execute_BranchPlugin_aaMask[15] = _zz_333_; + execute_BranchPlugin_aaMask[14] = _zz_333_; + execute_BranchPlugin_aaMask[13] = _zz_333_; + execute_BranchPlugin_aaMask[12] = _zz_333_; + execute_BranchPlugin_aaMask[11] = _zz_333_; + execute_BranchPlugin_aaMask[10] = _zz_333_; + execute_BranchPlugin_aaMask[9] = _zz_333_; + execute_BranchPlugin_aaMask[8] = _zz_333_; + execute_BranchPlugin_aaMask[7] = _zz_333_; + execute_BranchPlugin_aaMask[6] = _zz_333_; + execute_BranchPlugin_aaMask[5] = _zz_333_; + execute_BranchPlugin_aaMask[4] = _zz_333_; + execute_BranchPlugin_aaMask[3] = _zz_333_; + execute_BranchPlugin_aaMask[2] = _zz_333_; + execute_BranchPlugin_aaMask[1] = _zz_333_; + execute_BranchPlugin_aaMask[0] = _zz_333_; + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BCLR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_LR; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_CTR; + end + `BranchCtrlEnum_defaultEncoding_BCTAR : begin + execute_BranchPlugin_branch_tgt0 = execute_BranchPlugin_TAR; + end + default : begin + execute_BranchPlugin_branch_tgt0 = 32'h0; + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BU : begin + execute_BranchPlugin_branch_tgt1 = (execute_PC & execute_BranchPlugin_aaMask); + end + `BranchCtrlEnum_defaultEncoding_BC : begin + execute_BranchPlugin_branch_tgt1 = (execute_PC & execute_BranchPlugin_aaMask); + end + default : begin + execute_BranchPlugin_branch_tgt1 = 32'h0; + end + endcase + end + + assign execute_BranchPlugin_use_li = (execute_DECODER_stageables_13 == `BranchCtrlEnum_defaultEncoding_BU); + assign execute_BranchPlugin_branch_tgt2 = (execute_BranchPlugin_use_li ? _zz_606_ : _zz_607_); + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_BU : begin + execute_BranchPlugin_branchAdder = _zz_608_; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + execute_BranchPlugin_branchAdder = _zz_609_; + end + default : begin + execute_BranchPlugin_branchAdder = execute_BranchPlugin_branch_tgt0; + end + endcase + end + + assign execute_BranchPlugin_opbi = execute_INSTRUCTION[20 : 16]; + assign execute_BranchPlugin_crbiField = execute_BranchPlugin_opbi[4 : 2]; + assign execute_BranchPlugin_crbiBit = execute_BranchPlugin_opbi[1 : 0]; + assign execute_BranchPlugin_bo = execute_INSTRUCTION[25 : 21]; + assign execute_BranchPlugin_crBypassPort_valid = (_zz_303_ || _zz_319_); + always @ (*) begin + if(_zz_303_)begin + execute_BranchPlugin_crBypassPort_field = _zz_304_; + end else begin + execute_BranchPlugin_crBypassPort_field = _zz_320_; + end + end + + always @ (*) begin + if(execute_BranchPlugin_crBypassPort_valid)begin + execute_BranchPlugin_crbi = execute_BranchPlugin_crBypassPort_field[_zz_610_]; + end else begin + case(execute_BranchPlugin_crbiField) + 3'b000 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_611_]; + end + 3'b001 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_614_]; + end + 3'b010 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_617_]; + end + 3'b011 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_620_]; + end + 3'b100 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_623_]; + end + 3'b101 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_626_]; + end + 3'b110 : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_629_]; + end + default : begin + execute_BranchPlugin_crbi = execute_BranchPlugin_CR[_zz_632_]; + end + endcase + end + end + + assign execute_BranchPlugin_ctrOK = (execute_BranchPlugin_bo[2] || ((! execute_BranchPlugin_ctrOne) ^ execute_BranchPlugin_bo[1])); + assign execute_BranchPlugin_condOK = (execute_BranchPlugin_bo[4] || (! (execute_BranchPlugin_crbi ^ execute_BranchPlugin_bo[3]))); + assign execute_BranchPlugin_lk = execute_INSTRUCTION[0]; + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_334_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_334_ = 1'b1; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_334_ = execute_BranchPlugin_condOK; + end + default : begin + _zz_334_ = (execute_BranchPlugin_ctrOK && execute_BranchPlugin_condOK); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_335_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_335_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_335_ = 1'b0; + end + default : begin + _zz_335_ = (! execute_BranchPlugin_bo[2]); + end + endcase + end + + always @ (*) begin + case(execute_DECODER_stageables_13) + `BranchCtrlEnum_defaultEncoding_NONE : begin + _zz_336_ = 1'b0; + end + `BranchCtrlEnum_defaultEncoding_BU : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BC : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BCLR : begin + _zz_336_ = execute_BranchPlugin_lk; + end + `BranchCtrlEnum_defaultEncoding_BCCTR : begin + _zz_336_ = execute_BranchPlugin_lk; + end + default : begin + _zz_336_ = execute_BranchPlugin_lk; + end + endcase + end + + assign memory_BranchPlugin_predictionMissmatch = ((IBusCachedPlugin_fetchPrediction_cmd_hadBranch != memory_BRANCH_DO) || (memory_BRANCH_DO && memory_TARGET_MISSMATCH2)); + assign IBusCachedPlugin_fetchPrediction_rsp_wasRight = (! memory_BranchPlugin_predictionMissmatch); + assign IBusCachedPlugin_fetchPrediction_rsp_finalPc = memory_BRANCH_CALC; + assign IBusCachedPlugin_fetchPrediction_rsp_sourceLastWord = memory_PC; + assign BranchPlugin_jumpInterface_valid = ((memory_arbitration_isValid && memory_BranchPlugin_predictionMissmatch) && (! 1'b0)); + assign BranchPlugin_jumpInterface_payload = (memory_BRANCH_DO ? memory_BRANCH_CALC : memory_NEXT_PC2); + assign BranchPlugin_branchExceptionPort_valid = ((memory_arbitration_isValid && memory_BRANCH_DO) && memory_BRANCH_CALC[1]); + assign BranchPlugin_branchExceptionPort_payload_code = (4'b0000); + always @ (*) begin + SPRPlugin_msr_ir = MSR_IR; + if(_zz_410_)begin + SPRPlugin_msr_ir = 1'b0; + end + if(_zz_411_)begin + SPRPlugin_msr_ir = 1'b0; + end + if(_zz_413_)begin + SPRPlugin_msr_ir = SPRPlugin_srr1[5]; + end + end + + assign SPRPlugin_msr_dr = MSR_DR; + assign SPRPlugin_msr_pr = MSR_PR; + assign SPRPlugin_incTB = 1'b1; + always @ (*) begin + SPRPlugin_intDecTkn = 1'b0; + if(_zz_408_)begin + SPRPlugin_intDecTkn = (SPRPlugin_intType == `ExcpEnum_defaultEncoding_DEC); + end + end + + assign _zz_338_ = {decodeExceptionPort_valid,IBusCachedPlugin_decodeExceptionPort_valid}; + assign _zz_339_ = _zz_634_[0]; + assign _zz_340_ = (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_codePPC : decodeExceptionPort_payload_codePPC); + assign _zz_337_ = _zz_340_; + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + if(_zz_407_)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b1; + end + if(decode_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_decode = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + if(SPRPlugin_selfException_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b1; + end + if(execute_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_execute = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + if(BranchPlugin_branchExceptionPort_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b1; + end + if(memory_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_memory = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + if(DBusCachedPlugin_exceptionBus_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b1; + end + if(writeBack_arbitration_isFlushed)begin + SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack = 1'b0; + end + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_341_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_341_ = 1'b0; + end + default : begin + _zz_341_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_342_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_342_ = 1'b0; + end + default : begin + _zz_342_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_343_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_343_ = 1'b0; + end + default : begin + _zz_343_ = 1'b1; + end + endcase + end + + always @ (*) begin + case(SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC) + `ExcpEnum_defaultEncoding_SC : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_SCV : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_TRAP : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFI : begin + _zz_344_ = 1'b0; + end + `ExcpEnum_defaultEncoding_RFSCV : begin + _zz_344_ = 1'b0; + end + default : begin + _zz_344_ = 1'b1; + end + endcase + end + + assign SPRPlugin_exceptionPendings_0 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode; + assign SPRPlugin_exceptionPendings_1 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute; + assign SPRPlugin_exceptionPendings_2 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory; + assign SPRPlugin_exceptionPendings_3 = SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack; + assign SPRPlugin_pipelineLiberator_active = ((SPRPlugin_interrupt_valid && SPRPlugin_allowInterrupts) && decode_arbitration_isValid); + always @ (*) begin + SPRPlugin_pipelineLiberator_done = SPRPlugin_pipelineLiberator_pcValids_2; + if(({SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack,{SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory,SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute}} != (3'b000)))begin + SPRPlugin_pipelineLiberator_done = 1'b0; + end + if(SPRPlugin_hadException)begin + SPRPlugin_pipelineLiberator_done = 1'b0; + end + end + + assign SPRPlugin_exception = (SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack && SPRPlugin_allowException); + always @ (*) begin + SPRPlugin_interruptJump = 1'b0; + if(_zz_437_)begin + SPRPlugin_interruptJump = ((SPRPlugin_interrupt_valid && SPRPlugin_pipelineLiberator_done) && SPRPlugin_allowInterrupts); + end + end + + always @ (*) begin + SPRPlugin_intType = `ExcpEnum_defaultEncoding_NONE; + if(_zz_408_)begin + if(SPRPlugin_interruptJump)begin + case(SPRPlugin_interrupt_code) + 4'b1001 : begin + SPRPlugin_intType = `ExcpEnum_defaultEncoding_DEC; + end + default : begin + end + endcase + end else begin + SPRPlugin_intType = SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC; + end + end + end + + always @ (*) begin + SPRPlugin_intSRR0 = 32'h0; + if(_zz_408_)begin + if(SPRPlugin_interruptJump)begin + SPRPlugin_intSRR0 = writeBack_PC; + end else begin + SPRPlugin_intSRR0 = SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr; + end + end + end + + always @ (*) begin + case(SPRPlugin_intType) + `ExcpEnum_defaultEncoding_SR : begin + _zz_345_ = 32'h00000100; + end + `ExcpEnum_defaultEncoding_MC : begin + _zz_345_ = 32'h00000200; + end + `ExcpEnum_defaultEncoding_EXT : begin + _zz_345_ = 32'h00000500; + end + `ExcpEnum_defaultEncoding_DEC : begin + _zz_345_ = 32'h00000900; + end + `ExcpEnum_defaultEncoding_PM : begin + _zz_345_ = 32'h00000f00; + end + `ExcpEnum_defaultEncoding_DSI : begin + _zz_345_ = 32'h00000300; + end + `ExcpEnum_defaultEncoding_DSI_PROT : begin + _zz_345_ = 32'h00000300; + end + `ExcpEnum_defaultEncoding_ISI : begin + _zz_345_ = 32'h00000400; + end + `ExcpEnum_defaultEncoding_ISI_PROT : begin + _zz_345_ = 32'h00000400; + end + `ExcpEnum_defaultEncoding_ALG : begin + _zz_345_ = 32'h00000600; + end + `ExcpEnum_defaultEncoding_PGM_ILL : begin + _zz_345_ = 32'h00000700; + end + `ExcpEnum_defaultEncoding_PGM_PRV : begin + _zz_345_ = 32'h00000700; + end + `ExcpEnum_defaultEncoding_FP : begin + _zz_345_ = 32'h00000800; + end + `ExcpEnum_defaultEncoding_TR : begin + _zz_345_ = 32'h00000d00; + end + `ExcpEnum_defaultEncoding_VEC : begin + _zz_345_ = 32'h00000f20; + end + `ExcpEnum_defaultEncoding_VSX : begin + _zz_345_ = 32'h00000f40; + end + `ExcpEnum_defaultEncoding_FAC : begin + _zz_345_ = 32'h00000f60; + end + default : begin + _zz_345_ = 32'h0; + end + endcase + end + + always @ (*) begin + if(MSR_LE)begin + _zz_63_ = `EndianEnum_defaultEncoding_LE; + end else begin + _zz_63_ = `EndianEnum_defaultEncoding_BE; + end + end + + assign execute_SPRPLUGIN_blockedBySideEffects = ({writeBack_arbitration_isValid,memory_arbitration_isValid} != (2'b00)); + always @ (*) begin + case(execute_SPR_ID) + 11'b10000000001 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000011010 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000011011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010010 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00100001100 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00000010110 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + 11'b00100000011 : begin + execute_SPRPLUGIN_sprHere = 1'b1; + end + default : begin + execute_SPRPLUGIN_sprHere = 1'b0; + end + endcase + end + + always @ (*) begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + if((! execute_SPRPLUGIN_sprHere))begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_arbitration_isValid)begin + if((execute_DECODER_stageables_30 && SPRPlugin_msr_pr))begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + end + end + if(execute_SPRPLUGIN_SPR_1025)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_26)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_27)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_19)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_259)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_18)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_268)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_SPR_22)begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + if(execute_SPRPLUGIN_privViolation)begin + execute_SPRPLUGIN_illegalAccess = 1'b1; + end + if(((! execute_arbitration_isValid) || (! execute_DECODER_stageables_40)))begin + execute_SPRPLUGIN_illegalAccess = 1'b0; + end + end + + always @ (*) begin + SPRPlugin_selfException_valid = 1'b0; + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_valid = 1'b1; + end + end + + always @ (*) begin + SPRPlugin_selfException_payload_code = (4'bxxxx); + if(execute_SPRPLUGIN_illegalAccess)begin + SPRPlugin_selfException_payload_code = (4'b0010); + end + end + + assign _zz_346_ = execute_INSTRUCTION[15]; + always @ (*) begin + _zz_347_[15] = _zz_346_; + _zz_347_[14] = _zz_346_; + _zz_347_[13] = _zz_346_; + _zz_347_[12] = _zz_346_; + _zz_347_[11] = _zz_346_; + _zz_347_[10] = _zz_346_; + _zz_347_[9] = _zz_346_; + _zz_347_[8] = _zz_346_; + _zz_347_[7] = _zz_346_; + _zz_347_[6] = _zz_346_; + _zz_347_[5] = _zz_346_; + _zz_347_[4] = _zz_346_; + _zz_347_[3] = _zz_346_; + _zz_347_[2] = _zz_346_; + _zz_347_[1] = _zz_346_; + _zz_347_[0] = _zz_346_; + end + + assign execute_SPRPLUGIN_si = {_zz_347_,execute_INSTRUCTION[15 : 0]}; + assign execute_SPRPLUGIN_tmask = execute_INSTRUCTION[25 : 21]; + always @ (*) begin + execute_SPRPLUGIN_trap = 1'b0; + if(execute_arbitration_isValid)begin + if(_zz_394_)begin + if(($signed(_zz_636_) < $signed(_zz_637_)))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[4]; + end else begin + if(($signed(_zz_638_) < $signed(_zz_639_)))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[3]; + end else begin + if((execute_SRC1 == execute_SRC2))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[2]; + end else begin + if((execute_SRC1 < execute_SRC2))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[1]; + end else begin + if((execute_SRC2 < execute_SRC1))begin + execute_SPRPLUGIN_trap = execute_SPRPLUGIN_tmask[0]; + end + end + end + end + end + end + end + end + + assign execute_SPRPLUGIN_opExcp_codePPC = `ExcpEnum_defaultEncoding_NONE; + assign execute_SPRPLUGIN_opExcp_imm = 7'h0; + assign execute_SPRPLUGIN_opExcp_badAddr = execute_PC; + always @ (*) begin + _zz_348_ = 1'b0; + if(($signed(_zz_640_) < $signed(_zz_641_)))begin + _zz_348_ = execute_SPRPLUGIN_tmask[4]; + end else begin + if(($signed(_zz_642_) < $signed(_zz_643_)))begin + _zz_348_ = execute_SPRPLUGIN_tmask[3]; + end else begin + if((execute_SRC1 == execute_SPRPLUGIN_si))begin + _zz_348_ = execute_SPRPLUGIN_tmask[2]; + end else begin + if((execute_SRC1 < execute_SPRPLUGIN_si))begin + _zz_348_ = execute_SPRPLUGIN_tmask[1]; + end else begin + if((execute_SPRPLUGIN_si < execute_SRC1))begin + _zz_348_ = execute_SPRPLUGIN_tmask[0]; + end + end + end + end + end + end + + assign execute_SPRPLUGIN_readToWriteData = execute_SPRPLUGIN_readData; + assign execute_SPRPLUGIN_sprg3read = 1'b0; + assign execute_SPRPLUGIN_privViolation = ((execute_SPRPLUGIN_sprHere && MSR_PR) && (! execute_SPRPLUGIN_sprg3read)); + assign execute_SPRPLUGIN_readInstruction = ((((execute_arbitration_isValid && execute_SPRPLUGIN_sprHere) && execute_DECODER_stageables_54) && execute_DECODER_stageables_40) && (! execute_SPRPLUGIN_privViolation)); + assign execute_SPRPLUGIN_readEnable = ((execute_SPRPLUGIN_readInstruction && (! execute_SPRPLUGIN_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + assign execute_SPRPLUGIN_writeInstruction = ((((execute_arbitration_isValid && execute_SPRPLUGIN_sprHere) && execute_DECODER_stageables_32) && execute_DECODER_stageables_40) && (! execute_SPRPLUGIN_privViolation)); + assign execute_SPRPLUGIN_writeEnable = ((execute_SPRPLUGIN_writeInstruction && (! execute_SPRPLUGIN_blockedBySideEffects)) && (! execute_arbitration_isStuckByOthers)); + always @ (*) begin + execute_SPRPLUGIN_SPRAddress = {(1'b0),execute_SPR_ID[9 : 0]}; + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MFMSR))begin + execute_SPRPLUGIN_SPRAddress = 11'h401; + end else begin + if((execute_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MTMSR))begin + execute_SPRPLUGIN_SPRAddress = 11'h401; + end + end + end + + assign contextSwitching = SPRPlugin_jumpInterface_valid; + assign _zz_58_ = decode_DECODER_stageables_44; + assign _zz_56_ = _zz_109_; + assign _zz_99_ = decode_to_execute_DECODER_stageables_44; + assign _zz_55_ = decode_DECODER_stageables_49; + assign _zz_61_ = execute_DECODER_stageables_49; + assign _zz_52_ = memory_DECODER_stageables_49; + assign _zz_53_ = _zz_108_; + assign _zz_62_ = decode_to_execute_DECODER_stageables_49; + assign _zz_50_ = execute_to_memory_DECODER_stageables_49; + assign _zz_59_ = memory_to_writeBack_DECODER_stageables_49; + assign _zz_49_ = decode_DECODER_stageables_13; + assign _zz_65_ = _zz_115_; + assign _zz_67_ = decode_to_execute_DECODER_stageables_13; + assign _zz_47_ = decode_DECODER_stageables_20; + assign _zz_45_ = _zz_112_; + assign _zz_77_ = decode_to_execute_DECODER_stageables_20; + assign _zz_44_ = decode_DECODER_stageables_16; + assign _zz_42_ = _zz_114_; + assign _zz_98_ = decode_to_execute_DECODER_stageables_16; + assign _zz_41_ = decode_DECODER_stageables_0; + assign _zz_39_ = _zz_120_; + assign _zz_82_ = decode_to_execute_DECODER_stageables_0; + assign _zz_38_ = execute_CR_WRITE_op; + assign _zz_35_ = memory_CR_WRITE_op; + assign _zz_36_ = _zz_76_; + assign _zz_66_ = execute_to_memory_CR_WRITE_op; + assign _zz_101_ = memory_to_writeBack_CR_WRITE_op; + assign _zz_33_ = decode_DECODER_stageables_19; + assign _zz_31_ = _zz_113_; + assign _zz_100_ = decode_to_execute_DECODER_stageables_19; + assign _zz_30_ = decode_MSR_ENDIAN; + assign _zz_28_ = execute_MSR_ENDIAN; + assign _zz_26_ = memory_MSR_ENDIAN; + assign _zz_129_ = _zz_63_; + assign _zz_126_ = decode_to_execute_MSR_ENDIAN; + assign _zz_24_ = execute_to_memory_MSR_ENDIAN; + assign _zz_123_ = memory_to_writeBack_MSR_ENDIAN; + assign _zz_23_ = decode_DECODER_stageables_51; + assign _zz_21_ = _zz_107_; + assign _zz_78_ = decode_to_execute_DECODER_stageables_51; + assign _zz_20_ = decode_DECODER_stageables_7; + assign _zz_17_ = execute_DATA_SIZE; + assign _zz_15_ = memory_DECODER_stageables_7; + assign _zz_18_ = _zz_118_; + assign _zz_125_ = decode_to_execute_DECODER_stageables_7; + assign _zz_13_ = execute_to_memory_DECODER_stageables_7; + assign _zz_122_ = memory_to_writeBack_DECODER_stageables_7; + assign _zz_12_ = decode_DECODER_stageables_1; + assign _zz_10_ = _zz_119_; + assign _zz_70_ = decode_to_execute_DECODER_stageables_1; + assign _zz_9_ = decode_DECODER_stageables_8; + assign _zz_7_ = _zz_117_; + assign _zz_81_ = decode_to_execute_DECODER_stageables_8; + assign _zz_6_ = decode_DECODER_stageables_26; + assign _zz_105_ = _zz_111_; + assign _zz_71_ = decode_to_execute_DECODER_stageables_26; + assign _zz_4_ = decode_DECODER_stageables_38; + assign _zz_106_ = _zz_110_; + assign _zz_74_ = decode_to_execute_DECODER_stageables_38; + assign _zz_2_ = decode_DECODER_stageables_12; + assign _zz_104_ = _zz_116_; + assign _zz_80_ = decode_to_execute_DECODER_stageables_12; + assign decode_arbitration_isFlushed = (({writeBack_arbitration_flushNext,{memory_arbitration_flushNext,execute_arbitration_flushNext}} != (3'b000)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,{execute_arbitration_flushIt,decode_arbitration_flushIt}}} != (4'b0000))); + assign execute_arbitration_isFlushed = (({writeBack_arbitration_flushNext,memory_arbitration_flushNext} != (2'b00)) || ({writeBack_arbitration_flushIt,{memory_arbitration_flushIt,execute_arbitration_flushIt}} != (3'b000))); + assign memory_arbitration_isFlushed = ((writeBack_arbitration_flushNext != (1'b0)) || ({writeBack_arbitration_flushIt,memory_arbitration_flushIt} != (2'b00))); + assign writeBack_arbitration_isFlushed = (1'b0 || (writeBack_arbitration_flushIt != (1'b0))); + assign decode_arbitration_isStuckByOthers = (decode_arbitration_haltByOther || (((1'b0 || execute_arbitration_isStuck) || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign decode_arbitration_isStuck = (decode_arbitration_haltItself || decode_arbitration_isStuckByOthers); + assign decode_arbitration_isMoving = ((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)); + assign decode_arbitration_isFiring = ((decode_arbitration_isValid && (! decode_arbitration_isStuck)) && (! decode_arbitration_removeIt)); + assign execute_arbitration_isStuckByOthers = (execute_arbitration_haltByOther || ((1'b0 || memory_arbitration_isStuck) || writeBack_arbitration_isStuck)); + assign execute_arbitration_isStuck = (execute_arbitration_haltItself || execute_arbitration_isStuckByOthers); + assign execute_arbitration_isMoving = ((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)); + assign execute_arbitration_isFiring = ((execute_arbitration_isValid && (! execute_arbitration_isStuck)) && (! execute_arbitration_removeIt)); + assign memory_arbitration_isStuckByOthers = (memory_arbitration_haltByOther || (1'b0 || writeBack_arbitration_isStuck)); + assign memory_arbitration_isStuck = (memory_arbitration_haltItself || memory_arbitration_isStuckByOthers); + assign memory_arbitration_isMoving = ((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)); + assign memory_arbitration_isFiring = ((memory_arbitration_isValid && (! memory_arbitration_isStuck)) && (! memory_arbitration_removeIt)); + assign writeBack_arbitration_isStuckByOthers = (writeBack_arbitration_haltByOther || 1'b0); + assign writeBack_arbitration_isStuck = (writeBack_arbitration_haltItself || writeBack_arbitration_isStuckByOthers); + assign writeBack_arbitration_isMoving = ((! writeBack_arbitration_isStuck) && (! writeBack_arbitration_removeIt)); + assign writeBack_arbitration_isFiring = ((writeBack_arbitration_isValid && (! writeBack_arbitration_isStuck)) && (! writeBack_arbitration_removeIt)); + always @ (*) begin + _zz_349_ = {{(1'b0),decode_INSTRUCTION[15 : 11]},decode_INSTRUCTION[20 : 16]}; + if((decode_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MFMSR))begin + _zz_349_ = 11'h401; + end else begin + if((decode_DECODER_stageables_49 == `EnvCtrlEnum_defaultEncoding_MTMSR))begin + _zz_349_ = 11'h401; + end + end + end + + always @ (*) begin + _zz_350_ = 32'h0; + if(execute_SPRPLUGIN_SPR_1025)begin + _zz_350_[23 : 23] = MSR_VSX; + _zz_350_[8 : 8] = MSR_FE1; + _zz_350_[11 : 11] = MSR_FE0; + _zz_350_[2 : 2] = MSR_PMM; + _zz_350_[5 : 5] = MSR_IR; + _zz_350_[14 : 14] = MSR_PR; + _zz_350_[13 : 13] = MSR_FP; + _zz_350_[4 : 4] = MSR_DR; + _zz_350_[25 : 25] = MSR_VEC; + _zz_350_[1 : 1] = MSR_RI; + _zz_350_[12 : 12] = MSR_ME; + _zz_350_[15 : 15] = MSR_EE; + _zz_350_[0 : 0] = MSR_LE; + end + end + + always @ (*) begin + _zz_351_ = 32'h0; + if(execute_SPRPLUGIN_SPR_26)begin + _zz_351_[31 : 0] = SPRPlugin_srr0; + end + end + + always @ (*) begin + _zz_352_ = 32'h0; + if(execute_SPRPLUGIN_SPR_27)begin + _zz_352_[31 : 0] = SPRPlugin_srr1; + end + end + + always @ (*) begin + _zz_353_ = 32'h0; + if(execute_SPRPLUGIN_SPR_19)begin + _zz_353_[31 : 0] = SPRPlugin_dar; + end + end + + always @ (*) begin + _zz_354_ = 32'h0; + if(execute_SPRPLUGIN_SPR_259)begin + _zz_354_[31 : 0] = SPRPlugin_sprg3; + end + end + + always @ (*) begin + _zz_355_ = 32'h0; + if(execute_SPRPLUGIN_SPR_18)begin + _zz_355_[31 : 0] = SPRPlugin_dsisr; + end + end + + always @ (*) begin + _zz_356_ = 32'h0; + if(execute_SPRPLUGIN_SPR_268)begin + _zz_356_[31 : 0] = SPRPlugin_tb; + end + end + + always @ (*) begin + _zz_357_ = 32'h0; + if(execute_SPRPLUGIN_SPR_22)begin + _zz_357_[31 : 0] = SPRPlugin_dec; + end + end + + assign execute_SPRPLUGIN_readData = (((_zz_350_ | _zz_351_) | (_zz_352_ | _zz_353_)) | ((_zz_354_ | _zz_355_) | (_zz_356_ | _zz_357_))); + assign iBusWB_ADR = {_zz_657_,_zz_358_}; + assign iBusWB_CTI = ((_zz_358_ == (3'b111)) ? (3'b111) : (3'b010)); + assign iBusWB_BTE = (2'b00); + assign iBusWB_SEL = (4'b1111); + assign iBusWB_WE = 1'b0; + assign iBusWB_DAT_MOSI = 32'h0; + always @ (*) begin + iBusWB_CYC = 1'b0; + if(_zz_438_)begin + iBusWB_CYC = 1'b1; + end + end + + always @ (*) begin + iBusWB_STB = 1'b0; + if(_zz_438_)begin + iBusWB_STB = 1'b1; + end + end + + assign iBus_cmd_ready = (iBus_cmd_valid && iBusWB_ACK); + assign iBus_rsp_valid = _zz_359_; + assign iBus_rsp_payload_data = iBusWB_DAT_MISO_regNext; + assign iBus_rsp_payload_error = 1'b0; + assign _zz_365_ = (dBus_cmd_payload_length != (3'b000)); + assign _zz_361_ = dBus_cmd_valid; + assign _zz_363_ = dBus_cmd_payload_wr; + assign _zz_364_ = (_zz_360_ == dBus_cmd_payload_length); + assign dBus_cmd_ready = (_zz_362_ && (_zz_363_ || _zz_364_)); + assign dBusWB_ADR = ((_zz_365_ ? {{dBus_cmd_payload_address[31 : 5],_zz_360_},(2'b00)} : {dBus_cmd_payload_address[31 : 2],(2'b00)}) >>> 2); + assign dBusWB_CTI = (_zz_365_ ? (_zz_364_ ? (3'b111) : (3'b010)) : (3'b000)); + assign dBusWB_BTE = (2'b00); + assign dBusWB_SEL = (_zz_363_ ? dBus_cmd_payload_mask : (4'b1111)); + assign dBusWB_WE = _zz_363_; + assign dBusWB_DAT_MOSI = dBus_cmd_payload_data; + assign _zz_362_ = (_zz_361_ && dBusWB_ACK); + assign dBusWB_CYC = _zz_361_; + assign dBusWB_STB = _zz_361_; + assign dBus_rsp_valid = _zz_366_; + assign dBus_rsp_payload_data = dBusWB_DAT_MISO_regNext; + assign dBus_rsp_payload_error = 1'b0; + always @ (posedge clk or posedge reset) begin + if (reset) begin + IBusCachedPlugin_fetchPc_pcReg <= externalResetVector; + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + IBusCachedPlugin_fetchPc_booted <= 1'b0; + IBusCachedPlugin_fetchPc_inc <= 1'b0; + _zz_140_ <= 1'b0; + _zz_143_ <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + IBusCachedPlugin_rspCounter <= _zz_147_; + IBusCachedPlugin_rspCounter <= 32'h0; + dataCache_1__io_mem_cmd_m2sPipe_rValid <= 1'b0; + DBusCachedPlugin_rspCounter <= _zz_148_; + DBusCachedPlugin_rspCounter <= 32'h0; + _zz_241_ <= 1'b1; + ALU2_XER <= 32'h0; + MULDIV1_counter_value <= 6'h0; + Hazards_writeBackBuffer_valid <= 1'b0; + execute_BranchPlugin_CR <= 32'h0; + execute_BranchPlugin_CTR <= 32'h0; + execute_BranchPlugin_LR <= 32'h0; + execute_BranchPlugin_TAR <= 32'h0; + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + MSR_LE <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= 1'b0; + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + SPRPlugin_interrupt_valid <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + SPRPlugin_hadException <= 1'b0; + execute_arbitration_isValid <= 1'b0; + memory_arbitration_isValid <= 1'b0; + writeBack_arbitration_isValid <= 1'b0; + memory_to_writeBack_REGFILE_WRITE_DATA <= 32'h0; + memory_to_writeBack_INSTRUCTION <= 32'h0; + _zz_358_ <= (3'b000); + _zz_359_ <= 1'b0; + _zz_360_ <= (3'b000); + _zz_366_ <= 1'b0; + end else begin + if(IBusCachedPlugin_fetchPc_correction)begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b1; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_correctionReg <= 1'b0; + end + IBusCachedPlugin_fetchPc_booted <= 1'b1; + if((IBusCachedPlugin_fetchPc_correction || IBusCachedPlugin_fetchPc_pcRegPropagate))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_output_valid && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b1; + end + if(((! IBusCachedPlugin_fetchPc_output_valid) && IBusCachedPlugin_fetchPc_output_ready))begin + IBusCachedPlugin_fetchPc_inc <= 1'b0; + end + if((IBusCachedPlugin_fetchPc_booted && ((IBusCachedPlugin_fetchPc_output_ready || IBusCachedPlugin_fetchPc_correction) || IBusCachedPlugin_fetchPc_pcRegPropagate)))begin + IBusCachedPlugin_fetchPc_pcReg <= IBusCachedPlugin_fetchPc_pc; + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_140_ <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_140_ <= (IBusCachedPlugin_iBusRsp_stages_0_output_valid && (! 1'b0)); + end + if(IBusCachedPlugin_iBusRsp_flush)begin + _zz_143_ <= 1'b0; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_143_ <= (IBusCachedPlugin_iBusRsp_stages_1_output_valid && (! IBusCachedPlugin_iBusRsp_flush)); + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_1_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_0 <= 1'b1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if((! (! IBusCachedPlugin_iBusRsp_stages_2_input_ready)))begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= IBusCachedPlugin_injector_nextPcCalc_valids_0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_1 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if((! execute_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= IBusCachedPlugin_injector_nextPcCalc_valids_1; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_2 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if((! memory_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= IBusCachedPlugin_injector_nextPcCalc_valids_2; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_3 <= 1'b0; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if((! writeBack_arbitration_isStuck))begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= IBusCachedPlugin_injector_nextPcCalc_valids_3; + end + if(IBusCachedPlugin_fetchPc_flushed)begin + IBusCachedPlugin_injector_nextPcCalc_valids_4 <= 1'b0; + end + if(iBus_rsp_valid)begin + IBusCachedPlugin_rspCounter <= (IBusCachedPlugin_rspCounter + 32'h00000001); + end + if(_zz_388_)begin + dataCache_1__io_mem_cmd_m2sPipe_rValid <= dataCache_1__io_mem_cmd_valid; + end + if(dBus_rsp_valid)begin + DBusCachedPlugin_rspCounter <= (DBusCachedPlugin_rspCounter + 32'h00000001); + end + _zz_241_ <= 1'b0; + ALU2_XER[31 : 29] <= ALU2_XER[31 : 29]; + if(_zz_245_)begin + if(_zz_242_)begin + ALU2_XER[30] <= _zz_244_[1]; + ALU2_XER[31] <= (ALU2_XER[31] || _zz_244_[1]); + end + if(_zz_243_)begin + ALU2_XER[29] <= _zz_244_[0]; + end + end + if(writeBack_RegFilePlugin_sprWriteXERPort_valid)begin + ALU2_XER <= writeBack_RegFilePlugin_sprWriteXERPort_payload_data; + end + MULDIV1_counter_value <= MULDIV1_counter_valueNext; + Hazards_writeBackBuffer_valid <= Hazards_writeBackWrites_valid; + if(writeBack_RegFilePlugin_sprWriteCLTPort_valid)begin + case(writeBack_RegFilePlugin_sprWriteCLTPort_payload_id) + 10'b0000001001 : begin + execute_BranchPlugin_CTR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + 10'b0000001000 : begin + execute_BranchPlugin_LR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + 10'b1100101111 : begin + execute_BranchPlugin_TAR <= writeBack_RegFilePlugin_sprWriteCLTPort_payload_data; + end + default : begin + end + endcase + end + if(execute_BranchPlugin_crBusPort_valid)begin + case(execute_BranchPlugin_crBusPort_op) + `CRBusCmdEnum_defaultEncoding_CR0 : begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CR1 : begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CR6 : begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + `CRBusCmdEnum_defaultEncoding_CMP : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_AND_1 : begin + execute_BranchPlugin_CR[_zz_582_] <= (execute_BranchPlugin_CR[_zz_583_] && execute_BranchPlugin_CR[_zz_584_]); + end + `CRBusCmdEnum_defaultEncoding_OR_1 : begin + execute_BranchPlugin_CR[_zz_585_] <= (execute_BranchPlugin_CR[_zz_586_] || execute_BranchPlugin_CR[_zz_587_]); + end + `CRBusCmdEnum_defaultEncoding_XOR_1 : begin + execute_BranchPlugin_CR[_zz_588_] <= (execute_BranchPlugin_CR[_zz_589_] ^ execute_BranchPlugin_CR[_zz_590_]); + end + `CRBusCmdEnum_defaultEncoding_NAND_1 : begin + execute_BranchPlugin_CR[_zz_591_] <= (! (execute_BranchPlugin_CR[_zz_592_] && execute_BranchPlugin_CR[_zz_593_])); + end + `CRBusCmdEnum_defaultEncoding_NOR_1 : begin + execute_BranchPlugin_CR[_zz_594_] <= (! (execute_BranchPlugin_CR[_zz_595_] || execute_BranchPlugin_CR[_zz_596_])); + end + `CRBusCmdEnum_defaultEncoding_EQV : begin + execute_BranchPlugin_CR[_zz_597_] <= (! (execute_BranchPlugin_CR[_zz_598_] ^ execute_BranchPlugin_CR[_zz_599_])); + end + `CRBusCmdEnum_defaultEncoding_ANDC : begin + execute_BranchPlugin_CR[_zz_600_] <= (execute_BranchPlugin_CR[_zz_601_] && (! execute_BranchPlugin_CR[_zz_602_])); + end + `CRBusCmdEnum_defaultEncoding_ORC : begin + execute_BranchPlugin_CR[_zz_603_] <= (execute_BranchPlugin_CR[_zz_604_] || (! execute_BranchPlugin_CR[_zz_605_])); + end + `CRBusCmdEnum_defaultEncoding_MCRF : begin + case(execute_BranchPlugin_crBusPort_bt) + 5'b00000 : begin + execute_BranchPlugin_CR[31 : 28] <= _zz_327_; + end + 5'b00001 : begin + execute_BranchPlugin_CR[27 : 24] <= _zz_327_; + end + 5'b00010 : begin + execute_BranchPlugin_CR[23 : 20] <= _zz_327_; + end + 5'b00011 : begin + execute_BranchPlugin_CR[19 : 16] <= _zz_327_; + end + 5'b00100 : begin + execute_BranchPlugin_CR[15 : 12] <= _zz_327_; + end + 5'b00101 : begin + execute_BranchPlugin_CR[11 : 8] <= _zz_327_; + end + 5'b00110 : begin + execute_BranchPlugin_CR[7 : 4] <= _zz_327_; + end + 5'b00111 : begin + execute_BranchPlugin_CR[3 : 0] <= _zz_327_; + end + default : begin + end + endcase + end + `CRBusCmdEnum_defaultEncoding_MCRXRX : begin + case(execute_BranchPlugin_crBusPort_bt) + 5'b00000 : begin + execute_BranchPlugin_CR[31 : 28] <= _zz_328_; + end + 5'b00001 : begin + execute_BranchPlugin_CR[27 : 24] <= _zz_328_; + end + 5'b00010 : begin + execute_BranchPlugin_CR[23 : 20] <= _zz_328_; + end + 5'b00011 : begin + execute_BranchPlugin_CR[19 : 16] <= _zz_328_; + end + 5'b00100 : begin + execute_BranchPlugin_CR[15 : 12] <= _zz_328_; + end + 5'b00101 : begin + execute_BranchPlugin_CR[11 : 8] <= _zz_328_; + end + 5'b00110 : begin + execute_BranchPlugin_CR[7 : 4] <= _zz_328_; + end + 5'b00111 : begin + execute_BranchPlugin_CR[3 : 0] <= _zz_328_; + end + default : begin + end + endcase + end + `CRBusCmdEnum_defaultEncoding_MTCRF : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[31 : 28]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[27 : 24]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[23 : 20]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[19 : 16]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[15 : 12]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[11 : 8]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[7 : 4]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_MTOCRF : begin + if(execute_BranchPlugin_crBusPort_fxm[7])begin + execute_BranchPlugin_CR[31 : 28] <= execute_BranchPlugin_crBusPort_imm[31 : 28]; + end + if(execute_BranchPlugin_crBusPort_fxm[6])begin + execute_BranchPlugin_CR[27 : 24] <= execute_BranchPlugin_crBusPort_imm[27 : 24]; + end + if(execute_BranchPlugin_crBusPort_fxm[5])begin + execute_BranchPlugin_CR[23 : 20] <= execute_BranchPlugin_crBusPort_imm[23 : 20]; + end + if(execute_BranchPlugin_crBusPort_fxm[4])begin + execute_BranchPlugin_CR[19 : 16] <= execute_BranchPlugin_crBusPort_imm[19 : 16]; + end + if(execute_BranchPlugin_crBusPort_fxm[3])begin + execute_BranchPlugin_CR[15 : 12] <= execute_BranchPlugin_crBusPort_imm[15 : 12]; + end + if(execute_BranchPlugin_crBusPort_fxm[2])begin + execute_BranchPlugin_CR[11 : 8] <= execute_BranchPlugin_crBusPort_imm[11 : 8]; + end + if(execute_BranchPlugin_crBusPort_fxm[1])begin + execute_BranchPlugin_CR[7 : 4] <= execute_BranchPlugin_crBusPort_imm[7 : 4]; + end + if(execute_BranchPlugin_crBusPort_fxm[0])begin + execute_BranchPlugin_CR[3 : 0] <= execute_BranchPlugin_crBusPort_imm[3 : 0]; + end + end + `CRBusCmdEnum_defaultEncoding_DEC : begin + execute_BranchPlugin_CTR <= (execute_BranchPlugin_CTR - 32'h00000001); + end + `CRBusCmdEnum_defaultEncoding_LNK : begin + execute_BranchPlugin_LR <= execute_BranchPlugin_crBusPort_imm; + end + `CRBusCmdEnum_defaultEncoding_DECLNK : begin + execute_BranchPlugin_CTR <= (execute_BranchPlugin_CTR - 32'h00000001); + execute_BranchPlugin_LR <= execute_BranchPlugin_crBusPort_imm; + end + default : begin + end + endcase + end + if((! decode_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= 1'b0; + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_decode <= SPRPlugin_exceptionPortCtrl_exceptionValids_decode; + end + if((! execute_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= (SPRPlugin_exceptionPortCtrl_exceptionValids_decode && (! decode_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_execute <= SPRPlugin_exceptionPortCtrl_exceptionValids_execute; + end + if((! memory_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= (SPRPlugin_exceptionPortCtrl_exceptionValids_execute && (! execute_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_memory <= SPRPlugin_exceptionPortCtrl_exceptionValids_memory; + end + if((! writeBack_arbitration_isStuck))begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= (SPRPlugin_exceptionPortCtrl_exceptionValids_memory && (! memory_arbitration_isStuck)); + end else begin + SPRPlugin_exceptionPortCtrl_exceptionValidsRegs_writeBack <= 1'b0; + end + SPRPlugin_interrupt_valid <= 1'b0; + if(_zz_439_)begin + if(_zz_440_)begin + SPRPlugin_interrupt_valid <= 1'b1; + end + end + if(SPRPlugin_pipelineLiberator_active)begin + if((! execute_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_1 <= SPRPlugin_pipelineLiberator_pcValids_0; + end + if((! writeBack_arbitration_isStuck))begin + SPRPlugin_pipelineLiberator_pcValids_2 <= SPRPlugin_pipelineLiberator_pcValids_1; + end + end + if(((! SPRPlugin_pipelineLiberator_active) || decode_arbitration_removeIt))begin + SPRPlugin_pipelineLiberator_pcValids_0 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_1 <= 1'b0; + SPRPlugin_pipelineLiberator_pcValids_2 <= 1'b0; + end + SPRPlugin_hadException <= SPRPlugin_exception; + if(_zz_437_)begin + if(SPRPlugin_interruptJump)begin + SPRPlugin_interrupt_valid <= 1'b0; + end + end + if(_zz_408_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_410_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_411_)begin + MSR_VEC <= 1'b0; + MSR_VSX <= 1'b0; + MSR_EE <= 1'b0; + MSR_PR <= 1'b0; + MSR_FP <= 1'b0; + MSR_ME <= 1'b0; + MSR_FE0 <= 1'b0; + MSR_FE1 <= 1'b0; + MSR_IR <= 1'b0; + MSR_DR <= 1'b0; + MSR_PMM <= 1'b0; + MSR_RI <= 1'b0; + end + if(_zz_413_)begin + MSR_VEC <= SPRPlugin_srr1[25]; + MSR_VSX <= SPRPlugin_srr1[23]; + MSR_EE <= SPRPlugin_srr1[15]; + MSR_PR <= SPRPlugin_srr1[14]; + MSR_FP <= SPRPlugin_srr1[13]; + MSR_ME <= SPRPlugin_srr1[12]; + MSR_FE0 <= SPRPlugin_srr1[11]; + MSR_FE1 <= SPRPlugin_srr1[8]; + MSR_IR <= SPRPlugin_srr1[5]; + MSR_DR <= SPRPlugin_srr1[4]; + MSR_PMM <= SPRPlugin_srr1[2]; + MSR_RI <= SPRPlugin_srr1[1]; + MSR_LE <= SPRPlugin_srr1[0]; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_DATA <= _zz_69_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_INSTRUCTION <= memory_INSTRUCTION; + end + if(((! execute_arbitration_isStuck) || execute_arbitration_removeIt))begin + execute_arbitration_isValid <= 1'b0; + end + if(((! decode_arbitration_isStuck) && (! decode_arbitration_removeIt)))begin + execute_arbitration_isValid <= decode_arbitration_isValid; + end + if(((! memory_arbitration_isStuck) || memory_arbitration_removeIt))begin + memory_arbitration_isValid <= 1'b0; + end + if(((! execute_arbitration_isStuck) && (! execute_arbitration_removeIt)))begin + memory_arbitration_isValid <= execute_arbitration_isValid; + end + if(((! writeBack_arbitration_isStuck) || writeBack_arbitration_removeIt))begin + writeBack_arbitration_isValid <= 1'b0; + end + if(((! memory_arbitration_isStuck) && (! memory_arbitration_removeIt)))begin + writeBack_arbitration_isValid <= memory_arbitration_isValid; + end + if(execute_SPRPLUGIN_SPR_1025)begin + if(execute_SPRPLUGIN_writeEnable)begin + MSR_VSX <= _zz_644_[0]; + MSR_FE1 <= _zz_645_[0]; + MSR_FE0 <= _zz_646_[0]; + MSR_PMM <= _zz_647_[0]; + MSR_IR <= _zz_648_[0]; + MSR_PR <= _zz_649_[0]; + MSR_FP <= _zz_650_[0]; + MSR_DR <= _zz_651_[0]; + MSR_VEC <= _zz_652_[0]; + MSR_RI <= _zz_653_[0]; + MSR_ME <= _zz_654_[0]; + MSR_EE <= _zz_655_[0]; + MSR_LE <= _zz_656_[0]; + end + end + if(_zz_438_)begin + if(iBusWB_ACK)begin + _zz_358_ <= (_zz_358_ + (3'b001)); + end + end + _zz_359_ <= (iBusWB_CYC && iBusWB_ACK); + if((_zz_361_ && _zz_362_))begin + _zz_360_ <= (_zz_360_ + (3'b001)); + if(_zz_364_)begin + _zz_360_ <= (3'b000); + end + end + _zz_366_ <= ((_zz_361_ && (! dBusWB_WE)) && dBusWB_ACK); + end + end + + always @ (posedge clk) begin + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + _zz_141_ <= IBusCachedPlugin_iBusRsp_stages_0_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + _zz_144_ <= IBusCachedPlugin_iBusRsp_stages_1_output_payload; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_writeLast_valid <= IBusCachedPlugin_predictor_historyWriteDelayPatched_valid; + IBusCachedPlugin_predictor_writeLast_payload_address <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_address; + IBusCachedPlugin_predictor_writeLast_payload_data_source <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_source; + IBusCachedPlugin_predictor_writeLast_payload_data_branchWish <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_branchWish; + IBusCachedPlugin_predictor_writeLast_payload_data_target <= IBusCachedPlugin_predictor_historyWriteDelayPatched_payload_data_target; + end + if(IBusCachedPlugin_iBusRsp_stages_0_input_ready)begin + IBusCachedPlugin_predictor_buffer_pcCorrected <= IBusCachedPlugin_fetchPc_corrected; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_line_source <= IBusCachedPlugin_predictor_buffer_line_source; + IBusCachedPlugin_predictor_line_branchWish <= IBusCachedPlugin_predictor_buffer_line_branchWish; + IBusCachedPlugin_predictor_line_target <= IBusCachedPlugin_predictor_buffer_line_target; + end + if(IBusCachedPlugin_iBusRsp_stages_0_output_ready)begin + IBusCachedPlugin_predictor_buffer_hazard_regNextWhen <= IBusCachedPlugin_predictor_buffer_hazard; + end + if(IBusCachedPlugin_iBusRsp_stages_1_output_ready)begin + IBusCachedPlugin_predictor_iBusRspContext_hazard <= IBusCachedPlugin_predictor_fetchContext_hazard; + IBusCachedPlugin_predictor_iBusRspContext_hit <= IBusCachedPlugin_predictor_fetchContext_hit; + IBusCachedPlugin_predictor_iBusRspContext_line_source <= IBusCachedPlugin_predictor_fetchContext_line_source; + IBusCachedPlugin_predictor_iBusRspContext_line_branchWish <= IBusCachedPlugin_predictor_fetchContext_line_branchWish; + IBusCachedPlugin_predictor_iBusRspContext_line_target <= IBusCachedPlugin_predictor_fetchContext_line_target; + end + if(IBusCachedPlugin_iBusRsp_stages_1_input_ready)begin + IBusCachedPlugin_s1_tightlyCoupledHit <= IBusCachedPlugin_s0_tightlyCoupledHit; + end + if(IBusCachedPlugin_iBusRsp_stages_2_input_ready)begin + IBusCachedPlugin_s2_tightlyCoupledHit <= IBusCachedPlugin_s1_tightlyCoupledHit; + end + if(_zz_388_)begin + dataCache_1__io_mem_cmd_m2sPipe_rData_wr <= dataCache_1__io_mem_cmd_payload_wr; + dataCache_1__io_mem_cmd_m2sPipe_rData_address <= dataCache_1__io_mem_cmd_payload_address; + dataCache_1__io_mem_cmd_m2sPipe_rData_data <= dataCache_1__io_mem_cmd_payload_data; + dataCache_1__io_mem_cmd_m2sPipe_rData_mask <= dataCache_1__io_mem_cmd_payload_mask; + dataCache_1__io_mem_cmd_m2sPipe_rData_length <= dataCache_1__io_mem_cmd_payload_length; + dataCache_1__io_mem_cmd_m2sPipe_rData_last <= dataCache_1__io_mem_cmd_payload_last; + end + _zz_269_ <= (writeBack_arbitration_isFiring && writeBack_DECODER_stageables_9); + _zz_270_ <= writeBack_LOAD_UPDATE_ADDR; + _zz_271_ <= writeBack_LOAD_UPDATE_DATA; + if((MULDIV1_counter_value == 6'h20))begin + MULDIV1_done <= 1'b1; + end + if((! memory_arbitration_isStuck))begin + MULDIV1_done <= 1'b0; + end + if(_zz_399_)begin + if(_zz_422_)begin + MULDIV_rs1[31 : 0] <= MULDIV1_stage_0_outNumerator; + MULDIV_accumulator[31 : 0] <= MULDIV1_stage_0_outRemainder; + if((MULDIV1_counter_value == 6'h20))begin + MULDIV1_result <= _zz_573_[31:0]; + end + end + end + if(_zz_423_)begin + MULDIV_accumulator <= 65'h0; + MULDIV_rs1 <= ((_zz_281_ ? (~ _zz_282_) : _zz_282_) + _zz_579_); + MULDIV_rs2 <= ((_zz_280_ ? (~ execute_SRC2) : execute_SRC2) + _zz_581_); + MULDIV1_needRevert <= ((_zz_281_ ^ _zz_280_) && (! ((execute_SRC2 == 32'h0) && execute_DECODER_stageables_3))); + end + Hazards_writeBackBuffer_payload_address <= Hazards_writeBackWrites_payload_address; + Hazards_writeBackBuffer_payload_data <= Hazards_writeBackWrites_payload_data; + SPRPlugin_dec31Prev <= SPRPlugin_dec[31]; + if((SPRPlugin_dec31Prev && (! SPRPlugin_dec[31])))begin + SPRPlugin_intDec <= 1'b0; + end else begin + if(((! SPRPlugin_dec31Prev) && SPRPlugin_dec[31]))begin + SPRPlugin_intDec <= 1'b1; + end else begin + if(SPRPlugin_intDecTkn)begin + SPRPlugin_intDec <= 1'b0; + end + end + end + if(writeBack_arbitration_isFiring)begin + SPRPlugin_minstret <= (SPRPlugin_minstret + 32'h00000001); + end + if(_zz_407_)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_code : decodeExceptionPort_payload_code); + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_badAddr : decodeExceptionPort_payload_badAddr); + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= _zz_337_; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= (_zz_339_ ? IBusCachedPlugin_decodeExceptionPort_payload_imm : decodeExceptionPort_payload_imm); + end + if(SPRPlugin_selfException_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= SPRPlugin_selfException_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= SPRPlugin_selfException_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= SPRPlugin_selfException_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= SPRPlugin_selfException_payload_imm; + end + if(BranchPlugin_branchExceptionPort_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= BranchPlugin_branchExceptionPort_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= BranchPlugin_branchExceptionPort_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= BranchPlugin_branchExceptionPort_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= BranchPlugin_branchExceptionPort_payload_imm; + end + if(DBusCachedPlugin_exceptionBus_valid)begin + SPRPlugin_exceptionPortCtrl_exceptionContext_code <= DBusCachedPlugin_exceptionBus_payload_code; + SPRPlugin_exceptionPortCtrl_exceptionContext_badAddr <= DBusCachedPlugin_exceptionBus_payload_badAddr; + SPRPlugin_exceptionPortCtrl_exceptionContext_codePPC <= DBusCachedPlugin_exceptionBus_payload_codePPC; + SPRPlugin_exceptionPortCtrl_exceptionContext_imm <= DBusCachedPlugin_exceptionBus_payload_imm; + end + if(_zz_439_)begin + if(_zz_440_)begin + SPRPlugin_interrupt_code <= (4'b1001); + SPRPlugin_interrupt_targetPrivilege <= (2'b11); + end + end + SPRPlugin_darSave <= writeBack_SRC_ADD; + if(_zz_408_)begin + SPRPlugin_srr0 <= SPRPlugin_intSRR0; + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1582_,_zz_1583_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_PGM_ILL))begin + SPRPlugin_srr1[19] <= 1'b1; + end + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_PGM_PRV))begin + SPRPlugin_srr1[18] <= 1'b1; + end + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ISI))begin + SPRPlugin_srr1[30] <= 1'b1; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ISI_PROT))begin + SPRPlugin_srr1[29] <= 1'b1; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_DSI))begin + SPRPlugin_dsisr <= 32'h0; + SPRPlugin_dsisr[30] <= 1'b1; + SPRPlugin_dar <= SPRPlugin_darSave; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_DSI_PROT))begin + SPRPlugin_dsisr <= 32'h0; + SPRPlugin_dsisr[27] <= 1'b1; + SPRPlugin_dar <= SPRPlugin_darSave; + end else begin + if((SPRPlugin_intType == `ExcpEnum_defaultEncoding_ALG))begin + SPRPlugin_dar <= SPRPlugin_darSave; + end + end + end + end + end + end + if(! (execute_SPRPLUGIN_writeEnable && (execute_SPR_ID == 11'h10c))) begin + if(SPRPlugin_incTB)begin + SPRPlugin_tb <= (SPRPlugin_tb + 32'h00000001); + end + end + if(! (execute_SPRPLUGIN_writeEnable && (execute_SPR_ID == 11'h016))) begin + SPRPlugin_dec <= (SPRPlugin_dec - 32'h00000001); + end + if(_zz_410_)begin + SPRPlugin_srr0 <= (writeBack_PC + 32'h00000004); + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1584_,_zz_1585_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + end + if(_zz_411_)begin + SPRPlugin_srr0 <= (writeBack_PC + 32'h00000004); + SPRPlugin_srr1 <= {{{{{{{{{{{{_zz_1586_,_zz_1587_},MSR_ME},MSR_FE0},(2'b00)},MSR_FE1},(2'b00)},MSR_IR},MSR_DR},(1'b0)},MSR_PMM},MSR_RI},MSR_LE}; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RB <= decode_RB; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HH <= execute_MUL_HH; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_HH <= memory_MUL_HH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_28 <= decode_DECODER_stageables_28; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_44 <= _zz_57_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SPR_ID <= execute_SPR_ID; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SPR_ID <= memory_SPR_ID; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_36 <= decode_DECODER_stageables_36; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_36 <= execute_DECODER_stageables_36; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_36 <= memory_DECODER_stageables_36; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PREDICTION_CONTEXT_hazard <= decode_PREDICTION_CONTEXT_hazard; + decode_to_execute_PREDICTION_CONTEXT_hit <= decode_PREDICTION_CONTEXT_hit; + decode_to_execute_PREDICTION_CONTEXT_line_source <= decode_PREDICTION_CONTEXT_line_source; + decode_to_execute_PREDICTION_CONTEXT_line_branchWish <= decode_PREDICTION_CONTEXT_line_branchWish; + decode_to_execute_PREDICTION_CONTEXT_line_target <= decode_PREDICTION_CONTEXT_line_target; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PREDICTION_CONTEXT_hazard <= execute_PREDICTION_CONTEXT_hazard; + execute_to_memory_PREDICTION_CONTEXT_hit <= execute_PREDICTION_CONTEXT_hit; + execute_to_memory_PREDICTION_CONTEXT_line_source <= execute_PREDICTION_CONTEXT_line_source; + execute_to_memory_PREDICTION_CONTEXT_line_branchWish <= execute_PREDICTION_CONTEXT_line_branchWish; + execute_to_memory_PREDICTION_CONTEXT_line_target <= execute_PREDICTION_CONTEXT_line_target; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_49 <= _zz_54_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_49 <= _zz_60_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_49 <= _zz_51_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_48 <= decode_DECODER_stageables_48; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_XER_WRITE_validOV <= execute_XER_WRITE_validOV; + execute_to_memory_XER_WRITE_validCA <= execute_XER_WRITE_validCA; + execute_to_memory_XER_WRITE_imm <= execute_XER_WRITE_imm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_XER_WRITE_validOV <= memory_XER_WRITE_validOV; + memory_to_writeBack_XER_WRITE_validCA <= memory_XER_WRITE_validCA; + memory_to_writeBack_XER_WRITE_imm <= memory_XER_WRITE_imm; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_LOAD_UPDATE_DATA <= execute_LOAD_UPDATE_DATA; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_LOAD_UPDATE_DATA <= memory_LOAD_UPDATE_DATA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_13 <= _zz_48_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_55 <= decode_DECODER_stageables_55; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_55 <= execute_DECODER_stageables_55; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_55 <= memory_DECODER_stageables_55; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_57 <= decode_DECODER_stageables_57; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_20 <= _zz_46_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_DATA <= _zz_68_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_54 <= decode_DECODER_stageables_54; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_32 <= decode_DECODER_stageables_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_32 <= execute_DECODER_stageables_32; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_32 <= memory_DECODER_stageables_32; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MEMORY_ADDRESS_LOW <= execute_MEMORY_ADDRESS_LOW; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MEMORY_ADDRESS_LOW <= memory_MEMORY_ADDRESS_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_22 <= decode_DECODER_stageables_22; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_FORMAL_PC_NEXT <= decode_FORMAL_PC_NEXT; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_FORMAL_PC_NEXT <= execute_FORMAL_PC_NEXT; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_FORMAL_PC_NEXT <= _zz_131_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LL <= execute_MUL_LL; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_LOAD_UPDATE_ADDR <= execute_LOAD_UPDATE_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_LOAD_UPDATE_ADDR <= memory_LOAD_UPDATE_ADDR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_30 <= decode; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_52 <= decode_MEMORY_ENABLE; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_52 <= execute_MEMORY_ENABLE; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_52 <= memory_MEMORY_ENABLE; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_R0_ADDR <= decode_R0_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_CALC <= execute_BRANCH_CALC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_11 <= decode_DECODER_stageables_11; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_16 <= _zz_43_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_56 <= decode_DECODER_stageables_56; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_56 <= execute_MEMORY_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_56 <= memory_DECODER_stageables_56; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_39 <= decode_DECODER_stageables_39; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_39 <= execute_DECODER_stageables_39; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_39 <= memory_DECODER_stageables_39; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DO <= execute_BRANCH_DO; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_LINK <= execute_BRANCH_LINK; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_BRANCH_LINK <= memory_BRANCH_LINK; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_0 <= _zz_40_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_15 <= decode_DECODER_stageables_15; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_15 <= execute_DECODER_stageables_15; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_5 <= decode_DECODER_stageables_5; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_5 <= execute_DECODER_stageables_5; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CR_WRITE_op <= _zz_37_; + execute_to_memory_CR_WRITE_ba <= execute_CR_WRITE_ba; + execute_to_memory_CR_WRITE_bb <= execute_CR_WRITE_bb; + execute_to_memory_CR_WRITE_bt <= execute_CR_WRITE_bt; + execute_to_memory_CR_WRITE_imm <= execute_CR_WRITE_imm; + execute_to_memory_CR_WRITE_fxm <= execute_CR_WRITE_fxm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CR_WRITE_op <= _zz_34_; + memory_to_writeBack_CR_WRITE_ba <= memory_CR_WRITE_ba; + memory_to_writeBack_CR_WRITE_bb <= memory_CR_WRITE_bb; + memory_to_writeBack_CR_WRITE_bt <= memory_CR_WRITE_bt; + memory_to_writeBack_CR_WRITE_imm <= memory_CR_WRITE_imm; + memory_to_writeBack_CR_WRITE_fxm <= memory_CR_WRITE_fxm; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MUL_LOW <= memory_MUL_LOW; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_42 <= decode_DECODER_stageables_42; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RT_ADDR <= decode_RT_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_RT_ADDR <= execute_RT_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_RT_ADDR <= memory_RT_ADDR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_45 <= decode_DECODER_stageables_45; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_45 <= execute_DECODER_stageables_45; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_45 <= memory_DECODER_stageables_45; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_9 <= decode_DECODER_stageables_9; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_9 <= execute_DECODER_stageables_9; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_9 <= memory_DECODER_stageables_9; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_INSTRUCTION <= decode_INSTRUCTION; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_INSTRUCTION <= execute_INSTRUCTION; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_19 <= _zz_32_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_18 <= decode_DECODER_stageables_18; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_34 <= decode_DECODER_stageables_34; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_24 <= decode_DECODER_stageables_24; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_24 <= execute_DECODER_stageables_24; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_24 <= memory_DECODER_stageables_24; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_MSR_ENDIAN <= _zz_29_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MSR_ENDIAN <= _zz_27_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_MSR_ENDIAN <= _zz_25_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC1 <= execute_SRC1; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC1 <= memory_SRC1; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_14 <= decode_DECODER_stageables_14; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_3 <= decode_DECODER_stageables_3; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC_CR <= execute_SRC_CR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC_CR <= memory_SRC_CR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_BRANCH_DEC <= execute_BRANCH_DEC; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_BRANCH_DEC <= memory_BRANCH_DEC; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RA <= decode_RA; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_2 <= decode_DECODER_stageables_2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_6 <= decode_DECODER_stageables_6; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_40 <= decode_DECODER_stageables_40; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_LH <= execute_MUL_LH; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_31 <= decode_DECODER_stageables_31; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_31 <= execute_DECODER_stageables_31; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_31 <= memory_DECODER_stageables_31; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_TARGET_MISSMATCH2 <= execute_TARGET_MISSMATCH2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_35 <= decode_DECODER_stageables_35; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_REGFILE_WRITE_ADDR <= execute_REGFILE_WRITE_ADDR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_REGFILE_WRITE_ADDR <= memory_REGFILE_WRITE_ADDR; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_MUL_HL <= execute_MUL_HL; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_53 <= decode_DECODER_stageables_53; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_53 <= execute_DECODER_stageables_53; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_53 <= memory_DECODER_stageables_53; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_51 <= _zz_22_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_7 <= _zz_19_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_7 <= _zz_16_; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_DECODER_stageables_7 <= _zz_14_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_CR_FIELD_WR <= execute_CR_FIELD_WR; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_CR_FIELD_WR <= memory_CR_FIELD_WR; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_1 <= _zz_11_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_RS <= decode_RS; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_46 <= decode_DECODER_stageables_46; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_SRC_ADD <= execute_SRC_ADD; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_SRC_ADD <= memory_SRC_ADD; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_23 <= decode_DECODER_stageables_23; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_8 <= _zz_8_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_37 <= decode_DECODER_stageables_37; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_37 <= execute_DECODER_stageables_37; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_21 <= decode_DECODER_stageables_21; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_26 <= _zz_5_; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_CR_FIELD_RD <= decode_CR_FIELD_RD; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_27 <= decode_DECODER_stageables_27; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_43 <= decode_DECODER_stageables_43; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_DECODER_stageables_43 <= execute_DECODER_stageables_43; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_38 <= _zz_3_; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_XER_SO <= execute_XER_SO; + end + if((! writeBack_arbitration_isStuck))begin + memory_to_writeBack_XER_SO <= memory_XER_SO; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_PC <= decode_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_PC <= _zz_72_; + end + if(((! writeBack_arbitration_isStuck) && (! SPRPlugin_exceptionPortCtrl_exceptionValids_writeBack)))begin + memory_to_writeBack_PC <= memory_PC; + end + if((! memory_arbitration_isStuck))begin + execute_to_memory_NEXT_PC2 <= execute_NEXT_PC2; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_25 <= decode_DECODER_stageables_25; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_29 <= decode_DECODER_stageables_29; + end + if((! execute_arbitration_isStuck))begin + decode_to_execute_DECODER_stageables_12 <= _zz_1_; + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_1025 <= (_zz_349_ == 11'h401); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_26 <= (_zz_349_ == 11'h01a); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_27 <= (_zz_349_ == 11'h01b); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_19 <= (_zz_349_ == 11'h013); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_259 <= (_zz_349_ == 11'h103); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_18 <= (_zz_349_ == 11'h012); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_268 <= (_zz_349_ == 11'h10c); + end + if((! execute_arbitration_isStuck))begin + execute_SPRPLUGIN_SPR_22 <= (_zz_349_ == 11'h016); + end + if(execute_SPRPLUGIN_SPR_26)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_srr0 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_27)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_srr1 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_19)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dar <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_259)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_sprg3 <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_18)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dsisr <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_268)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_tb <= execute_SRC1[31 : 0]; + end + end + if(execute_SPRPLUGIN_SPR_22)begin + if(execute_SPRPLUGIN_writeEnable)begin + SPRPlugin_dec <= execute_SRC1[31 : 0]; + end + end + iBusWB_DAT_MISO_regNext <= iBusWB_DAT_MISO; + dBusWB_DAT_MISO_regNext <= dBusWB_DAT_MISO; + end + + +endmodule diff --git a/sim/soc/bios.s b/sim/soc/bios.s new file mode 100644 index 0000000..26a11f7 --- /dev/null +++ b/sim/soc/bios.s @@ -0,0 +1,17887 @@ + +build/cmod7/software/bios/bios.elf: file format elf32-powerpc + +Contents of section .text: + 0000 480004e4 00000000 00000000 00000000 H............... + 0010 00000000 00000000 00000000 00000000 ................ + 0020 00000000 00000000 00000000 00000000 ................ + 0030 00000000 00000000 00000000 00000000 ................ + 0040 00000000 00000000 00000000 00000000 ................ + 0050 00000000 00000000 00000000 00000000 ................ + 0060 00000000 00000000 00000000 00000000 ................ + 0070 00000000 00000000 00000000 00000000 ................ + 0080 00000000 00000000 00000000 00000000 ................ + 0090 00000000 00000000 00000000 00000000 ................ + 00a0 00000000 00000000 00000000 00000000 ................ + 00b0 00000000 00000000 00000000 00000000 ................ + 00c0 00000000 00000000 00000000 00000000 ................ + 00d0 00000000 00000000 00000000 00000000 ................ + 00e0 00000000 00000000 00000000 00000000 ................ + 00f0 00000000 00000000 00000000 00000000 ................ + 0100 48000000 480000fc 60000000 60000000 H...H...`...`... + 0110 60000000 60000000 60000000 60000000 `...`...`...`... + 0120 60000000 60000000 60000000 60000000 `...`...`...`... + 0130 60000000 60000000 60000000 60000000 `...`...`...`... + 0140 60000000 60000000 60000000 60000000 `...`...`...`... + 0150 60000000 60000000 60000000 60000000 `...`...`...`... + 0160 60000000 60000000 60000000 60000000 `...`...`...`... + 0170 60000000 60000000 60000000 60000000 `...`...`...`... + 0180 60000000 60000000 60000000 60000000 `...`...`...`... + 0190 60000000 60000000 60000000 60000000 `...`...`...`... + 01a0 60000000 60000000 60000000 60000000 `...`...`...`... + 01b0 60000000 60000000 60000000 60000000 `...`...`...`... + 01c0 60000000 60000000 60000000 60000000 `...`...`...`... + 01d0 60000000 60000000 60000000 60000000 `...`...`...`... + 01e0 60000000 60000000 60000000 60000000 `...`...`...`... + 01f0 60000000 60000000 60000000 60000000 `...`...`...`... + 0200 48000000 480000fc 60000000 60000000 H...H...`...`... + 0210 60000000 60000000 60000000 60000000 `...`...`...`... + 0220 60000000 60000000 60000000 60000000 `...`...`...`... + 0230 60000000 60000000 60000000 60000000 `...`...`...`... + 0240 60000000 60000000 60000000 60000000 `...`...`...`... + 0250 60000000 60000000 60000000 60000000 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K...A..( + 4270 5528f87e 552907fe 7d2900d0 7129d008 U(.~U)..})..q).. + 4280 7d294278 5528103a 7d5e412e 394a0001 })BxU(.:}^A.9J.. + 4290 4bffff7c 39290001 5529043e 4bffffe8 K..|9)..U).>K... + 42a0 39290001 5529043e 4bffff94 38600000 9)..U).>K...8`.. + 42b0 4e800020 9421ffc0 7c0802a6 7d800026 N.. .!..|...}..& + 42c0 39610040 90010044 4bffc2c1 91810014 9a.@...DK....... + 42d0 2e060000 7c7e1b78 7cbd2b78 7cd93378 ....|~.x|.+x|.3x + 42e0 549af0be 419200a4 81260004 83660000 T...A....&...f.. + 42f0 2c090000 40820040 3f000000 3be00001 ,...@..@?...;... + 4300 3b800000 2d9d0000 3b185d36 7c1cd000 ;...-...;.]6|... + 4310 5785103a 4082007c 3c600000 7fc4f378 W..:@..|<`.....x + 4320 38635d36 4bfffced 3c600000 386348dc 8c]6K...<`..8cH. + 4330 4bffeb4d 4bfffb91 3ec00000 3be00001 K..MK...>...;... + 4340 3b000000 3b800000 2d9d0000 2d1b0000 ;...;...-...-... + 4350 3ad65d3f 7c1ae000 4082007c 2c1b0000 :.]?|...@..|,... + 4360 418200fc 3c600000 5745103a 7fc4f378 A...<`..WE.:...x + 4370 38635d3f 4bfffc9d 3c600000 386348dc 8c]?K...<`..8cH. + 4380 4bffeafd 480000d8 3b600001 4bffff6c K...H...;`..K..l + 4390 418e003c 57e9f87e 57ff07fe 7fff00d0 A..N.. = .. + 4840 61294008 80690000 7c630034 5463d97e a)@..i..|c.4Tc.~ + 4850 4e800020 3d40fff0 614a4004 812a0000 N.. =@..aJ@..*.. + 4860 2c090000 4082fff8 3d20fff0 39400001 ,...@...= ..9@.. + 4870 61294000 90690000 91490010 4e800020 a)@..i...I..N.. + 4880 3d20fff0 61294010 81490000 91490000 = ..a)@..I...I.. + 4890 39400003 91490004 4e800020 3d40fff0 9@...I..N.. =@.. + 48a0 614a4004 812a0000 2c090000 4082fff8 aJ@..*..,...@... + 48b0 4e800020 N.. +Contents of section .rodata: + 48b4 00000000 45786563 7574696e 6720626f ....Executing bo + 48c4 6f746564 2070726f 6772616d 20617420 oted program at + 48d4 30782530 386c780a 0a002d2d 3d3d3d3d 0x%08lx...--==== + 48e4 3d3d3d3d 3d3d3d3d 3d201b5b 316d4c69 ========= .[1mLi + 48f4 66746f66 66211b5b 306d203d 3d3d3d3d ftoff!.[0m ===== + 4904 3d3d3d3d 3d3d3d3d 3d3d2d2d 0a00426f ==========--..Bo + 4914 6f74696e 67206672 6f6d2073 65726961 oting from seria + 4924 6c2e2e2e 0a005072 65737320 51206f72 l.....Press Q or + 4934 20455343 20746f20 61626f72 7420626f ESC to abort bo + 4944 6f742063 6f6d706c 6574656c 792e0a00 ot completely... + 4954 546f6f20 6d616e79 20636f6e 73656375 Too many consecu + 4964 74697665 20657272 6f72732c 2061626f tive errors, abo + 4974 7274696e 67005469 6d656f75 740a0043 rting.Timeout..C + 4984 616e6365 6c6c6564 0a000000 734c3544 ancelled....sL5D + 4994 64534d6d 6b656b72 6f0a0000 7a364948 dSMmkekro...z6IH + 49a4 47376359 44494436 6f0a4d65 6d6f7279 G7cYDID6o.Memory + 49b4 2064756d 703a000a 30782530 386c7820 dump:..0x%08lx + 49c4 20002530 32782000 20202000 25630020 .%02x . .%c. + 49d4 42494f53 20435243 20706173 73656420 BIOS CRC passed + 49e4 28253038 78290a00 2042494f 53204352 (%08x).. BIOS CR + 49f4 43206661 696c6564 20286578 70656374 C failed (expect + 4a04 65642025 3038782c 20676f74 20253038 ed %08x, got %08 + 4a14 78290a00 20546865 20737973 74656d20 x).. The system + 4a24 77696c6c 20636f6e 74696e75 652c2062 will continue, b + 4a34 75742065 78706563 74207072 6f626c65 ut expect proble + 4a44 6d732e0a 002d000a 4c697465 58204249 ms...-..LiteX BI + 4a54 4f532c20 61766169 6c61626c 6520636f OS, available co + 4a64 6d6d616e 64733a0a 00252d32 3473202d mmands:..%-24s - + 4a74 2025730a 00427574 746f6e73 2076616c %s..Buttons val + 4a84 75653a20 30782578 00496465 6e743a20 ue: 0x%x.Ident: + 4a94 2573006c 65647320 3c76616c 75653e00 %s.leds . + 4aa4 496e636f 72726563 74207661 6c756500 Incorrect value. + 4ab4 53657474 696e6773 204c6564 7320746f Settings Leds to + 4ac4 20307825 78006372 63203c61 64647265 0x%x.crc .Inc + 4ae4 6f727265 63742061 64647265 73730043 orrect address.C + 4af4 52433332 3a202530 3878006c 65647300 RC32: %08x.leds. + 4b04 53657420 4c656473 2076616c 75650062 Set Leds value.b + 4b14 7574746f 6e730047 65742042 7574746f uttons.Get Butto + 4b24 6e732076 616c7565 00666c75 73685f63 ns value.flush_c + 4b34 70755f64 63616368 6500466c 75736820 pu_dcache.Flush + 4b44 43505520 64617461 20636163 68650063 CPU data cache.c + 4b54 72630043 6f6d7075 74652043 52433332 rc.Compute CRC32 + 4b64 206f6620 61207061 7274206f 66207468 of a part of th + 4b74 65206164 64726573 73207370 61636500 e address space. + 4b84 6964656e 74004964 656e7469 66696572 ident.Identifier + 4b94 206f6620 74686520 73797374 656d0050 of the system.P + 4ba4 72696e74 20746869 73206865 6c700041 rint this help.A + 4bb4 7661696c 61626c65 206d656d 6f727920 vailable memory + 4bc4 72656769 6f6e733a 0a00524f 4d202020 regions:..ROM + 4bd4 20202020 30783030 30303030 30302030 0x00000000 0 + 4be4 78313030 3030200a 5352414d 20202020 x10000 .SRAM + 4bf4 20203078 30303031 30303030 20307831 0x00010000 0x1 + 4c04 30303030 200a4d41 494e5f52 414d2020 0000 .MAIN_RAM + 4c14 30783031 30303030 30302030 78313030 0x01000000 0x100 + 4c24 30303030 200a4353 52202020 20202020 0000 .CSR + 4c34 30786666 66303030 30302030 78313030 0xfff00000 0x100 + 4c44 30302000 6d656d5f 77726974 65203c61 00 .mem_write + 4c64 5b636f75 6e745d20 5b73697a 655d0049 [count] [size].I + 4c74 6e636f72 72656374 20636f75 6e740049 ncorrect count.I + 4c84 6e636f72 72656374 2073697a 65006d65 ncorrect size.me + 4c94 6d5f636f 7079203c 6473743e 203c7372 m_copy [count].Incor + 4cb4 72656374 20646573 74696e61 74696f6e rect destination + 4cc4 20616464 72657373 00496e63 6f727265 address.Incorre + 4cd4 63742073 6f757263 65206164 64726573 ct source addres + 4ce4 73006d65 6d5f636d 70203c61 64647231 s.mem_cmp .Incorrect addr + 4d14 3100496e 636f7272 65637420 61646472 1.Incorrect addr + 4d24 32004469 66666572 656e7420 6d656d6f 2.Different memo + 4d34 72792063 6f6e7465 6e743a0a 61646472 ry content:.addr + 4d44 313a2030 78253038 6c782c20 636f6e74 1: 0x%08lx, cont + 4d54 656e743a 20307825 3038780a 61646472 ent: 0x%08x.addr + 4d64 323a2030 78253038 6c782c20 636f6e74 2: 0x%08lx, cont + 4d74 656e743a 20307825 3038780a 006d656d ent: 0x%08x..mem + 4d84 5f636d70 2066696e 69736865 642c2073 _cmp finished, s + 4d94 616d6520 636f6e74 656e742e 006d656d ame content..mem + 4da4 5f636d70 2066696e 69736865 642c2064 _cmp finished, d + 4db4 69666665 72656e74 20636f6e 74656e74 ifferent content + 4dc4 2e006d65 6d5f7265 6164203c 61646472 ..mem_read [length]..I + 4de4 6e636f72 72656374 206c656e 67746800 ncorrect length. + 4df4 6d656d5f 74657374 203c6164 64723e20 mem_test + 4e04 5b3c6d61 7873697a 653e5d00 6d656d5f [].mem_ + 4e14 73706565 64203c61 6464723e 203c7369 speed [] + 4e34 205b3c72 616e646f 6d3e5d00 496e636f [].Inco + 4e44 72726563 74207265 61646f6e 6c792076 rrect readonly v + 4e54 616c7565 00496e63 6f727265 63742072 alue.Incorrect r + 4e64 616e646f 6d207661 6c756500 6d656d5f andom value.mem_ + 4e74 636d7000 436f6d70 61726520 6d656d6f cmp.Compare memo + 4e84 72792063 6f6e7465 6e74006d 656d5f73 ry content.mem_s + 4e94 70656564 00546573 74206d65 6d6f7279 peed.Test memory + 4ea4 20737065 6564006d 656d5f74 65737400 speed.mem_test. + 4eb4 54657374 206d656d 6f727920 61636365 Test memory acce + 4ec4 7373006d 656d5f63 6f707900 436f7079 ss.mem_copy.Copy + 4ed4 20616464 72657373 20737061 6365006d address space.m + 4ee4 656d5f77 72697465 00577269 74652061 em_write.Write a + 4ef4 64647265 73732073 70616365 006d656d ddress space.mem + 4f04 5f726561 64005265 61642061 64647265 _read.Read addre + 4f14 73732073 70616365 006d656d 5f6c6973 ss space.mem_lis + 4f24 74004c69 73742061 7661696c 61626c65 t.List available + 4f34 206d656d 6f727920 72656769 6f6e7300 memory regions. + 4f44 626f6f74 203c6164 64726573 733e205b boot
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(c) Copyrigh + 5094 74203230 31322d32 30323220 456e6a6f t 2012-2022 Enjo + 50a4 792d4469 67697461 6c0a0020 28632920 y-Digital.. (c) + 50b4 436f7079 72696768 74203230 30372d32 Copyright 2007-2 + 50c4 30313520 4d2d4c61 62730a00 2042494f 015 M-Labs.. BIO + 50d4 53206275 696c7420 6f6e2041 75672032 S built on Aug 2 + 50e4 37203230 32322031 303a3434 3a34320a 7 2022 10:44:42. + 50f4 00204c69 74655820 67697420 73686131 . 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exiting memtest. + 5d34 0a002020 57726974 653a0020 20205265 .. Write:. Re + 5d44 61643a00 4d656d73 70656564 20617420 ad:.Memspeed at + 5d54 25702028 0052616e 646f6d2c 20005365 %p (.Random, .Se + 5d64 7175656e 7469616c 2c200029 2e2e2e0a quential, .).... + 5d74 00202057 72697465 20737065 65643a20 . Write speed: + 5d84 002f7300 20202052 65616420 73706565 ./s. Read spee + 5d94 643a2000 4d656d74 65737420 61742025 d: .Memtest at % + 5da4 70202800 20206275 73206572 726f7273 p (. bus errors + 5db4 3a202025 642f256c 640a0020 20616464 : %d/%ld.. add + 5dc4 72206572 726f7273 3a202564 2f256c64 r errors: %d/%ld + 5dd4 0a002020 64617461 20657272 6f72733a .. data errors: + 5de4 2025642f 256c640a 004d656d 74657374 %d/%ld..Memtest + 5df4 204b4f0a 004d656d 74657374 204f4b0a KO..Memtest OK. + 5e04 00000000 .... +Contents of section .commands: + 5e08 00010000 00010010 00010020 00010030 ........... ...0 + 5e18 00010040 00010050 00010060 00010070 ...@...P...`...p + 5e28 00010080 00010090 000100a0 000100b0 ................ + 5e38 000100c0 000100d0 000100e0 000100f0 ................ +Contents of section .data: + 10000 00001388 00004aff 00004b04 00000000 ......J...K..... + 10010 0000130c 00004b13 00004b1b 00000000 ......K...K..... + 10020 00001254 00004b2d 00004b3e 00000000 ...T..K-..K>.... + 10030 00001408 00004b53 00004b57 00000000 ......KS..KW.... + 10040 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.9.I....B......? + 3d10 19030e3a 0b3b0b39 0b271911 01120640 ...:.;.9.'.....@ + 3d20 18974219 0000102e 01030e3a 0b3b0539 ..B........:.;.9 + 3d30 0b271920 0b011300 00110500 03083a0b .'. ..........:. + 3d40 3b05390b 49130000 122e0003 0e3a0b3b ;.9.I........:.; + 3d50 05390b27 19491320 0b000013 2e00030e .9.'.I. ........ + 3d60 3a0b3b0b 390b2719 4913200b 0000142e :.;.9.'.I. ..... + 3d70 01030e3a 0b3b0b39 0b271920 0b011300 ...:.;.9.'. .... + 3d80 00150500 03083a0b 3b0b390b 49130000 ......:.;.9.I... + 3d90 162e0103 0e3a0b3b 0b390b27 19491320 .....:.;.9.'.I. + 3da0 0b011300 00172e01 030e3a0b 3b0b390b ..........:.;.9. + 3db0 2719200b 000000 '. .... +Contents of section .debug_aranges: + 0000 0000001c 00020000 00000400 00000000 ................ + 0010 00000000 00000604 00000000 00000000 ................ + 0020 0000001c 00020000 00260400 00000000 .........&...... + 0030 00000610 00000064 00000000 00000000 .......d........ + 0040 0000001c 00020000 004c0400 00000000 .........L...... + 0050 00000674 00000878 00000000 00000000 ...t...x........ + 0060 0000001c 00020000 13810400 00000000 ................ + 0070 00000eec 00000368 00000000 00000000 .......h........ + 0080 0000001c 00020000 19730400 00000000 .........s...... + 0090 00001254 00000260 00000000 00000000 ...T...`........ + 00a0 0000001c 00020000 212f0400 00000000 ........!/...... + 00b0 000014b4 000005f4 00000000 00000000 ................ + 00c0 0000001c 00020000 2b270400 00000000 ........+'...... + 00d0 00001aa8 00000130 00000000 00000000 .......0........ + 00e0 0000001c 00020000 2ff90400 00000000 ......../....... + 00f0 00001bd8 000001e8 00000000 00000000 ................ + 0100 0000001c 00020000 36a40400 00000000 ........6....... + 0110 00001dc0 000002fc 00000000 00000000 ................ + 0120 0000001c 00020000 3df90400 00000000 ........=....... + 0130 000020bc 000008d4 00000000 00000000 .. ............. + 0140 00000014 00020000 4b250400 00000000 ........K%...... + 0150 00000000 00000000 00000014 00020000 ................ + 0160 52c80400 00000000 00000000 00000000 R............... + 0170 0000001c 00020000 534a0400 00000000 ........SJ...... + 0180 00002990 00000074 00000000 00000000 ..)....t........ + 0190 00000024 00020000 5bc00400 00000000 ...$....[....... + 01a0 00002a04 0000017c 00002b80 0000000c ..*....|..+..... + 01b0 00000000 00000000 0000001c 00020000 ................ + 01c0 65b90400 00000000 00002b8c 00000038 e.........+....8 + 01d0 00000000 00000000 0000001c 00020000 ................ + 01e0 6e0c0400 00000000 00002bc4 00000024 n.........+....$ + 01f0 00000000 00000000 0000001c 00020000 ................ + 0200 76240400 00000000 00002be8 00000058 v$........+....X + 0210 00000000 00000000 0000001c 00020000 ................ + 0220 7e1e0400 00000000 00002c40 0000001c ~.........,@.... + 0230 00000000 00000000 0000001c 00020000 ................ + 0240 7efb0400 00000000 00002c5c 00000020 ~.........,\... + 0250 00000000 00000000 0000001c 00020000 ................ + 0260 7fcc0400 00000000 00002c7c 00000040 ..........,|...@ + 0270 00000000 00000000 0000001c 00020000 ................ + 0280 80ad0400 00000000 00002cbc 00000054 ..........,....T + 0290 00000000 00000000 0000001c 00020000 ................ + 02a0 81c40400 00000000 00002d10 0000002c ..........-...., + 02b0 00000000 00000000 00000024 00020000 ...........$.... + 02c0 82ae0400 00000000 00000000 0000007c ...............| + 02d0 00000000 00000010 00000000 00000000 ................ + 02e0 0000001c 00020000 8bb70400 00000000 ................ + 02f0 00002d3c 0000008c 00000000 00000000 ..-<............ + 0300 0000001c 00020000 8eb00400 00000000 ................ + 0310 00002dc8 00000048 00000000 00000000 ..-....H........ + 0320 0000001c 00020000 90d70400 00000000 ................ + 0330 00002e10 0000006c 00000000 00000000 .......l........ + 0340 0000001c 00020000 93210400 00000000 .........!...... + 0350 00002e7c 0000006c 00000000 00000000 ...|...l........ + 0360 0000001c 00020000 95a20400 00000000 ................ + 0370 00002ee8 0000007c 00000000 00000000 .......|........ + 0380 00000024 00020000 97dd0400 00000000 ...$............ + 0390 00002f64 000001a0 00003104 0000085c ../d......1....\ + 03a0 00000000 00000000 0000001c 00020000 ................ + 03b0 a9550400 00000000 00003960 000000bc .U........9`.... + 03c0 00000000 00000000 0000001c 00020000 ................ + 03d0 aa4b0400 00000000 00003a1c 00000064 .K........:....d + 03e0 00000000 00000000 0000001c 00020000 ................ + 03f0 acdb0400 00000000 00003a80 000002ac ..........:..... + 0400 00000000 00000000 0000001c 00020000 ................ + 0410 aecc0400 00000000 00003d2c 00000008 ..........=,.... + 0420 00000000 00000000 0000001c 00020000 ................ + 0430 afe10400 00000000 00003d34 00000058 ..........=4...X + 0440 00000000 00000000 0000001c 00020000 ................ + 0450 b0b50400 00000000 00003d8c 00000138 ..........=....8 + 0460 00000000 00000000 0000001c 00020000 ................ + 0470 b17b0400 00000000 00003ec4 000000bc .{........>..... + 0480 00000000 00000000 0000001c 00020000 ................ + 0490 b7190400 00000000 00003f80 00000888 ..........?..... + 04a0 00000000 00000000 0000001c 00020000 ................ + 04b0 ccdc0400 00000000 00004808 000000ac ..........H..... + 04c0 00000000 00000000 ........ +Contents of section .debug_str: + 00000 2f646174 612f7072 6f6a6563 74732f61 /data/projects/a + 00010 32702f62 75696c64 2f6c6974 65782f66 2p/build/litex/f + 00020 756c6c2d 6c697465 782f6132 705f6e65 ull-litex/a2p_ne + 00030 772f6372 74302e53 002f6461 74612f70 w/crt0.S./data/p + 00040 726f6a65 6374732f 6132702f 6275696c rojects/a2p/buil + 00050 642f6c69 7465782f 66756c6c 2d6c6974 d/litex/full-lit + 00060 65782f62 75696c64 2f636d6f 64372f73 ex/build/cmod7/s + 00070 6f667477 6172652f 62696f73 00474e55 oftware/bios.GNU + 00080 20415320 322e3334 002f6461 74612f70 AS 2.34./data/p + 00090 726f6a65 6374732f 6132702f 6275696c rojects/a2p/buil + 000a0 642f6c69 7465782f 66756c6c 2d6c6974 d/litex/full-lit + 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5f454e43 4f44494e 475f4953 4f5f3838 _ENCODING_ISO_88 + 003d0 35395f31 31200074 696d656f 75740043 59_11 .timeout.C + 003e0 4f4e4649 475f4350 555f5459 50455f41 ONFIG_CPU_TYPE_A + 003f0 32502000 5f49434f 4e565f46 524f4d5f 2P ._ICONV_FROM_ + 00400 454e434f 44494e47 5f57494e 5f313235 ENCODING_WIN_125 + 00410 37200050 52497836 34205f5f 50524936 7 .PRIx64 __PRI6 + 00420 34287829 005f434c 4f434b5f 545f2075 4(x)._CLOCK_T_ u + 00430 6e736967 6e656420 6c6f6e67 005f5f42 nsigned long.__B + 00440 4f4f545f 4820005f 5f505452 44494646 OOT_H .__PTRDIFF + 00450 5f4d4158 5f5f2030 78376666 66666666 _MAX__ 0x7ffffff + 00460 66005f54 68726561 645f6c6f 63616c20 f._Thread_local + 00470 5f5f7468 72656164 005f494e 544d4158 __thread._INTMAX + 00480 5f545f44 45434c41 52454420 005f5f46 _T_DECLARED .__F + 00490 4c543634 5f4d494e 5f31305f 4558505f LT64_MIN_10_EXP_ + 004a0 5f20282d 33303729 006d656d 6d6f7665 _ (-307).memmove + 004b0 28647374 2c737263 2c6c656e 29205f5f (dst,src,len) __ + 004c0 7373705f 626f735f 63686563 6b33286d ssp_bos_check3(m + 004d0 656d6d6f 76652c20 6473742c 20737263 emmove, dst, src + 004e0 2c206c65 6e290046 4c545f52 4f554e44 , len).FLT_ROUND + 004f0 53005f5f 474e5543 4c494b45 5f425549 S.__GNUCLIKE_BUI + 00500 4c54494e 5f434f4e 5354414e 545f5020 LTIN_CONSTANT_P + 00510 31005f5f 75696e74 385f7400 50524958 1.__uint8_t.PRIX + 00520 3634205f 5f505249 36342858 29005f5f 64 __PRI64(X).__ + 00530 7072696e 74666c69 6b652866 6d746172 printflike(fmtar + 00540 672c6669 72737476 61726172 6729205f g,firstvararg) _ + 00550 5f617474 72696275 74655f5f 28285f5f _attribute__((__ + 00560 666f726d 61745f5f 20285f5f 7072696e format__ (__prin + 00570 74665f5f 2c20666d 74617267 2c206669 tf__, fmtarg, fi + 00580 72737476 61726172 67292929 005f5f53 rstvararg))).__S + 00590 5444435f 5f203100 7061796c 6f616400 TDC__ 1.payload. + 005a0 5f4e756c 6c5f756e 73706563 69666965 _Null_unspecifie + 005b0 64200055 494e545f 4c454153 5436345f d .UINT_LEAST64_ + 005c0 4d415820 285f5f55 494e545f 4c454153 MAX (__UINT_LEAS + 005d0 5436345f 4d41585f 5f290050 52497846 T64_MAX__).PRIxF + 005e0 41535431 36205f5f 50524931 36464153 AST16 __PRI16FAS + 005f0 54287829 005f5245 41445f57 52495445 T(x)._READ_WRITE + 00600 5f425546 53495a45 5f545950 4520696e _BUFSIZE_TYPE in + 00610 7400464c 545f4449 47005f5f 464c5433 t.FLT_DIG.__FLT3 + 00620 325f4d41 585f4558 505f5f20 31323800 2_MAX_EXP__ 128. + 00630 5f5f464c 4f41545f 574f5244 5f4f5244 __FLOAT_WORD_ORD + 00640 45525f5f 205f5f4f 52444552 5f424947 ER__ __ORDER_BIG + 00650 5f454e44 49414e5f 5f005f5f 44454331 _ENDIAN__.__DEC1 + 00660 32385f4d 494e5f45 58505f5f 20282d36 28_MIN_EXP__ (-6 + 00670 31343229 006a736d 6e746f6b 00434f4e 142).jsmntok.CON + 00680 4649475f 42494f53 5f4e4f5f 424f4f54 FIG_BIOS_NO_BOOT + 00690 2031005f 5f55494e 5436345f 54595045 1.__UINT64_TYPE + 006a0 5f5f206c 6f6e6720 6c6f6e67 20756e73 __ long long uns + 006b0 69676e65 6420696e 74004c44 424c5f4d igned int.LDBL_M + 006c0 41585f45 5850205f 5f4c4442 4c5f4d41 AX_EXP __LDBL_MA + 006d0 585f4558 505f5f00 5f5f4442 4c5f4d41 X_EXP__.__DBL_MA + 006e0 585f3130 5f455850 5f5f2033 3038005f X_10_EXP__ 308._ + 006f0 49434f4e 565f4652 4f4d5f45 4e434f44 ICONV_FROM_ENCOD + 00700 494e475f 57494e5f 31323538 20005f5f ING_WIN_1258 .__ + 00710 5544505f 48200050 52497546 41535436 UDP_H .PRIuFAST6 + 00720 34205f5f 50524936 34464153 54287529 4 __PRI64FAST(u) + 00730 005f5f47 4e55434c 494b455f 5f5f5459 .__GNUCLIKE___TY + 00740 50454f46 20310049 4e543332 5f432878 PEOF 1.INT32_C(x + 00750 29205f5f 494e5433 325f4328 78290046 ) __INT32_C(x).F + 00760 465f4653 5f455846 41542030 005f5f45 F_FS_EXFAT 0.__E + 00770 4c465f5f 20310046 465f4e4f 5254435f LF__ 1.FF_NORTC_ + 00780 4d4f4e20 31005f5f 53495a45 4f465f4c MON 1.__SIZEOF_L + 00790 4f4e475f 5f203400 5f5f494e 54363420 ONG__ 4.__INT64 + 007a0 226c6c22 005f5f6e 6565645f 77696e74 "ll".__need_wint + 007b0 5f742000 5f49434f 4e565f46 524f4d5f _t ._ICONV_FROM_ + 007c0 454e434f 44494e47 5f554353 5f344c45 ENCODING_UCS_4LE + 007d0 20004841 56455f50 49434f4c 4942435f .HAVE_PICOLIBC_ + 007e0 544c535f 41504900 665f726d 64697228 TLS_API.f_rmdir( + 007f0 70617468 2920665f 756e6c69 6e6b2870 path) f_unlink(p + 00800 61746829 00494e54 36345f43 28782920 ath).INT64_C(x) + 00810 5f5f494e 5436345f 43287829 005f5f4c __INT64_C(x).__L + 00820 4f4e475f 444f5542 4c455f49 424d3132 ONG_DOUBLE_IBM12 + 00830 385f5f20 31005f5f 57434841 525f545f 8__ 1.__WCHAR_T_ + 00840 5f200074 696d6572 305f7265 6c6f6164 _ .timer0_reload + 00850 5f777269 74650049 50544f49 4e542861 _write.IPTOINT(a + 00860 2c622c63 2c642920 28286120 3c3c2032 ,b,c,d) ((a << 2 + 00870 34297c28 62203c3c 20313629 7c286320 4)|(b << 16)|(c + 00880 3c3c2038 297c6429 0053434e 754d4158 << 8)|d).SCNuMAX + 00890 205f5f53 434e4d41 58287529 00737472 __SCNMAX(u).str + 008a0 6e637079 28647374 2c737263 2c6c656e ncpy(dst,src,len + 008b0 29205f5f 7373705f 626f735f 63686563 ) __ssp_bos_chec + 008c0 6b332873 74726e63 70792c20 6473742c k3(strncpy, dst, + 008d0 20737263 2c206c65 6e29005f 49434f4e src, len)._ICON + 008e0 565f544f 5f454e43 4f44494e 475f4350 V_TO_ENCODING_CP + 008f0 37373520 005f4943 4f4e565f 544f5f45 775 ._ICONV_TO_E + 00900 4e434f44 494e475f 49534f5f 38383539 NCODING_ISO_8859 + 00910 5f313320 00435352 5f554152 545f4556 _13 .CSR_UART_EV + 00920 5f454e41 424c455f 54585f53 495a4520 _ENABLE_TX_SIZE + 00930 31005052 49754641 53543820 5f5f5052 1.PRIuFAST8 __PR + 00940 49384641 53542875 29005f41 6c69676e I8FAST(u)._Align + 00950 61732878 29205f5f 616c6967 6e656428 as(x) __aligned( + 00960 7829005f 5f534852 545f5749 4454485f x).__SHRT_WIDTH_ + 00970 5f203136 00435352 5f554152 545f4556 _ 16.CSR_UART_EV + 00980 5f50454e 44494e47 5f54585f 4f464653 _PENDING_TX_OFFS + 00990 45542030 005f5f50 2870726f 746f7329 ET 0.__P(protos) + 009a0 2070726f 746f7300 5f5f494e 54505452 protos.__INTPTR + 009b0 5f545950 455f5f20 696e7400 5f5f5f69 _TYPE__ int.___i + 009c0 6e745f6c 65617374 33325f74 5f646566 nt_least32_t_def + 009d0 696e6564 2031005f 5f494e54 5f464153 ined 1.__INT_FAS + 009e0 5431365f 57494454 485f5f20 3332005f T16_WIDTH__ 32._ + 009f0 5f484156 455f4c4f 43414c45 5f494e46 _HAVE_LOCALE_INF + 00a00 4f5f4558 54454e44 45445f5f 005f5f46 O_EXTENDED__.__F + 00a10 4c545f48 41535f49 4e46494e 4954595f LT_HAS_INFINITY_ + 00a20 5f203100 53434e75 50545220 5f5f5343 _ 1.SCNuPTR __SC + 00a30 4e505452 28752900 5f5f5354 44435f49 NPTR(u).__STDC_I + 00a40 534f5f31 30363436 5f5f2032 30313730 SO_10646__ 20170 + 00a50 364c0044 424c5f4d 494e5f45 5850205f 6L.DBL_MIN_EXP _ + 00a60 5f44424c 5f4d494e 5f455850 5f5f005f _DBL_MIN_EXP__._ + 00a70 5f574348 41525f4d 494e5f5f 20282d5f _WCHAR_MIN__ (-_ + 00a80 5f574348 41525f4d 41585f5f 202d2031 _WCHAR_MAX__ - 1 + 00a90 29005f5f 44454336 345f4d49 4e5f4558 ).__DEC64_MIN_EX + 00aa0 505f5f20 282d3338 3229006a 736d6e5f P__ (-382).jsmn_ + 00ab0 70617273 655f7374 72696e67 00505249 parse_string.PRI + 00ac0 784c4541 53543820 5f5f5052 49384c45 xLEAST8 __PRI8LE + 00ad0 41535428 7829005f 5f464c54 3332585f AST(x).__FLT32X_ + 00ae0 4d414e54 5f444947 5f5f2035 3300494e MANT_DIG__ 53.IN + 00af0 545f4641 53543634 5f4d494e 20282d5f T_FAST64_MIN (-_ + 00b00 5f494e54 5f464153 5436345f 4d41585f _INT_FAST64_MAX_ + 00b10 5f202d20 31290074 696d6572 305f6c6f _ - 1).timer0_lo + 00b20 61640053 434e6931 36205f5f 53434e31 ad.SCNi16 __SCN1 + 00b30 36286929 005f5f70 72656469 63745f74 6(i).__predict_t + 00b40 72756528 65787029 205f5f62 75696c74 rue(exp) __built + 00b50 696e5f65 78706563 74282865 7870292c in_expect((exp), + 00b60 20312900 5052496f 3634205f 5f505249 1).PRIo64 __PRI + 00b70 3634286f 2900504f 5349585f 494f2000 64(o).POSIX_IO . + 00b80 50524969 4c454153 54313620 5f5f5052 PRIiLEAST16 __PR + 00b90 4931364c 45415354 28692900 5f55494e I16LEAST(i)._UIN + 00ba0 5436345f 545f4445 434c4152 45442000 T64_T_DECLARED . + 00bb0 5f5f4442 4c5f4445 4e4f524d 5f4d494e __DBL_DENORM_MIN + 00bc0 5f5f2028 28646f75 626c6529 342e3934 __ ((double)4.94 + 00bd0 30363536 34353834 31323436 35343431 0656458412465441 + 00be0 37363536 38373932 38363832 3231652d 76568792868221e- + 00bf0 3332344c 29005f5f 616c6967 6e656428 324L).__aligned( + 00c00 7829205f 5f617474 72696275 74655f5f x) __attribute__ + 00c10 28285f5f 616c6967 6e65645f 5f287829 ((__aligned__(x) + 00c20 29290043 53525f55 4152545f 45565f50 )).CSR_UART_EV_P + 00c30 454e4449 4e475f53 495a4520 31005f4e ENDING_SIZE 1._N + 00c40 45574c49 425f5f20 34005f5f 4c44424c EWLIB__ 4.__LDBL + 00c50 5f444947 5f5f2033 31005f5f 4743435f _DIG__ 31.__GCC_ + 00c60 41544f4d 49435f49 4e545f4c 4f434b5f ATOMIC_INT_LOCK_ + 00c70 46524545 2032005f 5f464153 54382022 FREE 2.__FAST8 " + 00c80 68682200 48415645 5f414c4c 4f435f53 hh".HAVE_ALLOC_S + 00c90 495a4500 5f49434f 4e565f46 524f4d5f IZE._ICONV_FROM_ + 00ca0 454e434f 44494e47 5f554353 5f344245 ENCODING_UCS_4BE + 00cb0 20004353 525f4944 454e5449 46494552 .CSR_IDENTIFIER + 00cc0 5f4d454d 5f424153 45202843 53525f42 _MEM_BASE (CSR_B + 00cd0 41534520 2b203078 33303030 4c29005f ASE + 0x3000L)._ + 00ce0 5f756e62 6f756e64 65642000 5f5f494e _unbounded .__IN + 00cf0 545f4c45 41535431 365f5749 4454485f T_LEAST16_WIDTH_ + 00d00 5f203136 005f4943 4f4e565f 46524f4d _ 16._ICONV_FROM + 00d10 5f454e43 4f44494e 475f5543 535f324c _ENCODING_UCS_2L + 00d20 45200045 54484d41 435f4556 5f535241 E .ETHMAC_EV_SRA + 00d30 4d5f5752 49544552 20307831 00534545 M_WRITER 0x1.SEE + 00d40 4b5f5345 54203000 5f5f5052 49333228 K_SET 0.__PRI32( + 00d50 7829205f 5f494e54 3332205f 5f535452 x) __INT32 __STR + 00d60 494e4749 46592878 29005f5f 474e5543 INGIFY(x).__GNUC + 00d70 4c494b45 5f425549 4c54494e 5f564141 LIKE_BUILTIN_VAA + 00d80 4c495354 2031004d 425f4355 525f4d41 LIST 1.MB_CUR_MA + 00d90 58205f5f 6c6f6361 6c655f6d 625f6375 X __locale_mb_cu + 00da0 725f6d61 78282900 5f5f4442 4c5f4841 r_max().__DBL_HA + 00db0 535f494e 46494e49 54595f5f 2031005f S_INFINITY__ 1._ + 00dc0 4d425f4c 454e5f4d 41582031 005f5f6e MB_LEN_MAX 1.__n + 00dd0 6f5f6c6f 636b5f61 6e616c79 73697320 o_lock_analysis + 00de0 5f5f6c6f 636b5f61 6e6e6f74 61746528 __lock_annotate( + 00df0 6e6f5f74 68726561 645f7361 66657479 no_thread_safety + 00e00 5f616e61 6c797369 7329005f 49434f4e _analysis)._ICON + 00e10 565f544f 5f454e43 4f44494e 475f4953 V_TO_ENCODING_IS + 00e20 4f5f3838 35395f31 3520005f 56415f4c O_8859_15 ._VA_L + 00e30 4953545f 44454649 4e454420 005f5f44 IST_DEFINED .__D + 00e40 45433132 385f4d41 4e545f44 49475f5f EC128_MANT_DIG__ + 00e50 20333400 494e545f 46415354 33325f4d 34.INT_FAST32_M + 00e60 494e2028 2d5f5f49 4e545f46 41535433 IN (-__INT_FAST3 + 00e70 325f4d41 585f5f20 2d203129 005f5f53 2_MAX__ - 1).__S + 00e80 4852545f 4d41585f 5f203078 37666666 HRT_MAX__ 0x7fff + 00e90 0046465f 5553455f 53545246 554e4320 .FF_USE_STRFUNC + 00ea0 30005f49 434f4e56 5f544f5f 454e434f 0._ICONV_TO_ENCO + 00eb0 44494e47 5f455543 5f545720 00494e54 DING_EUC_TW .INT + 00ec0 4d41585f 4d494e20 282d494e 544d4158 MAX_MIN (-INTMAX + 00ed0 5f4d4158 202d2031 2900494e 545f4c45 _MAX - 1).INT_LE + 00ee0 41535433 325f4d41 5820285f 5f494e54 AST32_MAX (__INT + 00ef0 5f4c4541 53543332 5f4d4158 5f5f2900 _LEAST32_MAX__). + 00f00 5f49434f 4e565f54 4f5f454e 434f4449 _ICONV_TO_ENCODI + 00f10 4e475f55 43535f32 20004646 5f564f4c NG_UCS_2 .FF_VOL + 00f20 554d4553 2031005f 5f464c54 33325f48 UMES 1.__FLT32_H + 00f30 41535f49 4e46494e 4954595f 5f203100 AS_INFINITY__ 1. + 00f40 4a534d4e 5f554e44 4546494e 45440046 JSMN_UNDEFINED.F + 00f50 4c545f4d 494e5f45 5850205f 5f464c54 LT_MIN_EXP __FLT + 00f60 5f4d494e 5f455850 5f5f0049 4e543634 _MIN_EXP__.INT64 + 00f70 5f4d494e 20282d5f 5f494e54 36345f4d _MIN (-__INT64_M + 00f80 41585f5f 202d2031 29005f5f 66617374 AX__ - 1).__fast + 00f90 63616c6c 205f5f61 74747269 62757465 call __attribute + 00fa0 5f5f2828 5f5f6661 73746361 6c6c5f5f __((__fastcall__ + 00fb0 29290050 52496f38 205f5f50 52493828 )).PRIo8 __PRI8( + 00fc0 6f290046 465f494e 54444546 2032005f o).FF_INTDEF 2._ + 00fd0 4e4f494e 4c494e45 205f5f61 74747269 NOINLINE __attri + 00fe0 62757465 5f5f2028 285f5f6e 6f696e6c bute__ ((__noinl + 00ff0 696e655f 5f292900 5f5f494e 545f4641 ine__)).__INT_FA + 01000 53543634 5f4d4158 5f5f2030 78376666 ST64_MAX__ 0x7ff + 01010 66666666 66666666 66666666 664c4c00 fffffffffffffLL. + 01020 5f524545 4e545f47 4c4f4241 4c5f4154 _REENT_GLOBAL_AT + 01030 45584954 005f5f6c 6f6e675f 646f7562 EXIT.__long_doub + 01040 6c655f74 206c6f6e 6720646f 75626c65 le_t long double + 01050 005f5f47 43435f41 544f4d49 435f4348 .__GCC_ATOMIC_CH + 01060 41525f4c 4f434b5f 46524545 2032005f AR_LOCK_FREE 2._ + 01070 5f55494e 545f4641 53543136 5f545950 _UINT_FAST16_TYP + 01080 455f5f20 756e7369 676e6564 20696e74 E__ unsigned int + 01090 00435352 5f54494d 4552305f 56414c55 .CSR_TIMER0_VALU + 010a0 455f5349 5a452031 005f5f55 494e5436 E_SIZE 1.__UINT6 + 010b0 345f4d41 585f5f20 30786666 66666666 4_MAX__ 0xffffff + 010c0 66666666 66666666 6666554c 4c005f5f ffffffffffULL.__ + 010d0 4c44424c 5f4d4158 5f5f2031 2e373937 LDBL_MAX__ 1.797 + 010e0 36393331 33343836 32333135 38303739 6931348623158079 + 010f0 33373238 39373134 30353330 31652b33 3728971405301e+3 + 01100 30384c00 5f5f6e6f 73616e69 74697a65 08L.__nosanitize + 01110 61646472 65737320 005f5f53 495a454f address .__SIZEO + 01120 465f494e 545f5f20 34005343 4e643820 F_INT__ 4.SCNd8 + 01130 5f5f5343 4e382864 29005f5f 464c5433 __SCN8(d).__FLT3 + 01140 32585f4d 41585f31 305f4558 505f5f20 2X_MAX_10_EXP__ + 01150 33303800 74696d65 72305f76 616c7565 308.timer0_value + 01160 5f726561 64005f54 5f505452 44494646 _read._T_PTRDIFF + 01170 5f20005f 5f696e74 32305f5f 005f5f57 _ .__int20__.__W + 01180 43484152 5f574944 54485f5f 20333200 CHAR_WIDTH__ 32. + 01190 5f5f5349 475f4154 4f4d4943 5f545950 __SIG_ATOMIC_TYP + 011a0 455f5f20 696e7400 5f425344 5f53495a E__ int._BSD_SIZ + 011b0 455f545f 44454649 4e45445f 20005f5f E_T_DEFINED_ .__ + 011c0 42494747 4553545f 414c4947 4e4d454e BIGGEST_ALIGNMEN + 011d0 545f5f20 3136005f 5f494e54 5f4c4541 T__ 16.__INT_LEA + 011e0 53543634 5f4d4158 5f5f2030 78376666 ST64_MAX__ 0x7ff + 011f0 66666666 66666666 66666666 664c4c00 fffffffffffffLL. + 01200 73686f72 7400665f 72657769 6e642866 short.f_rewind(f + 01210 70292066 5f6c7365 656b2828 6670292c p) f_lseek((fp), + 01220 20302900 5f5f5343 4e313646 41535428 0).__SCN16FAST( + 01230 7829205f 5f464153 54313620 5f5f5354 x) __FAST16 __ST + 01240 52494e47 49465928 7829005f 5f55494e RINGIFY(x).__UIN + 01250 5431365f 43286329 2063005f 5f505241 T16_C(c) c.__PRA + 01260 474d415f 52454445 46494e45 5f455854 GMA_REDEFINE_EXT + 01270 4e414d45 2031005f 5f494e54 5f4c4541 NAME 1.__INT_LEA + 01280 53543634 5f545950 455f5f20 6c6f6e67 ST64_TYPE__ long + 01290 206c6f6e 6720696e 74005f49 434f4e56 long int._ICONV + 012a0 5f46524f 4d5f454e 434f4449 4e475f55 _FROM_ENCODING_U + 012b0 43535f32 42452000 46465f46 535f5245 CS_2BE .FF_FS_RE + 012c0 41444f4e 4c592031 00746f6b 73757065 ADONLY 1.toksupe + 012d0 72005343 4e693332 205f5f53 434e3332 r.SCNi32 __SCN32 + 012e0 28692900 5f5f7379 6d5f636f 6d706174 (i).__sym_compat + 012f0 2873796d 2c696d70 6c2c7665 72696429 (sym,impl,verid) + 01300 205f5f61 736d5f5f 28222e73 796d7665 __asm__(".symve + 01310 72202220 23696d70 6c20222c 20222023 r " #impl ", " # + 01320 73796d20 22402220 23766572 69642900 sym "@" #verid). + 01330 5f5f7265 71756972 65735f75 6e6c6f63 __requires_unloc + 01340 6b656428 2e2e2e29 205f5f6c 6f636b5f ked(...) __lock_ + 01350 616e6e6f 74617465 286c6f63 6b735f65 annotate(locks_e + 01360 78636c75 64656428 5f5f5641 5f415247 xcluded(__VA_ARG + 01370 535f5f29 29005f5f 50524936 34287829 S__)).__PRI64(x) + 01380 205f5f49 4e543634 205f5f53 5452494e __INT64 __STRIN + 01390 47494659 28782900 44424c5f 4d41585f GIFY(x).DBL_MAX_ + 013a0 31305f45 5850205f 5f44424c 5f4d4158 10_EXP __DBL_MAX + 013b0 5f31305f 4558505f 5f005f5f 48415645 _10_EXP__.__HAVE + 013c0 5f535045 43554c41 54494f4e 5f534146 _SPECULATION_SAF + 013d0 455f5641 4c554520 31004641 4c4c5448 E_VALUE 1.FALLTH + 013e0 524f5547 48205f5f 61747472 69627574 ROUGH __attribut + 013f0 655f5f28 2866616c 6c746872 6f756768 e__((fallthrough + 01400 2929005f 5f424547 494e5f44 45434c53 )).__BEGIN_DECLS + 01410 20005052 49584641 53543332 205f5f50 .PRIXFAST32 __P + 01420 52493332 46415354 28582900 5f49434f RI32FAST(X)._ICO + 01430 4e565f46 524f4d5f 454e434f 44494e47 NV_FROM_ENCODING + 01440 5f49534f 5f383835 395f3133 20005f4c _ISO_8859_13 ._L + 01450 44424c5f 45515f44 424c0066 6c757368 DBL_EQ_DBL.flush + 01460 0046465f 5553455f 5452494d 2030005f .FF_USE_TRIM 0._ + 01470 5f737370 5f626f73 5f636865 636b3328 _ssp_bos_check3( + 01480 66756e2c 6473742c 7372632c 6c656e29 fun,dst,src,len) + 01490 2028285f 5f737370 5f626f73 30286473 ((__ssp_bos0(ds + 014a0 74292021 3d202873 697a655f 74292d31 t) != (size_t)-1 + 014b0 29203f20 5f5f6275 696c7469 6e5f5f5f ) ? __builtin___ + 014c0 20232320 66756e20 2323205f 63686b28 ## fun ## _chk( + 014d0 6473742c 20737263 2c206c65 6e2c205f dst, src, len, _ + 014e0 5f737370 5f626f73 30286473 74292920 _ssp_bos0(dst)) + 014f0 3a205f5f 20232320 66756e20 2323205f : __ ## fun ## _ + 01500 6963686b 28647374 2c207372 632c206c ichk(dst, src, l + 01510 656e2929 005f4841 56455f4c 4f4e475f en))._HAVE_LONG_ + 01520 444f5542 4c452000 4353525f 42555454 DOUBLE .CSR_BUTT + 01530 4f4e535f 42415345 20284353 525f4241 ONS_BASE (CSR_BA + 01540 5345202b 20307832 3030304c 29005f5f SE + 0x2000L).__ + 01550 76615f6c 6973745f 5f200053 434e6f33 va_list__ .SCNo3 + 01560 32205f5f 53434e33 32286f29 005f5f64 2 __SCN32(o).__d + 01570 65616432 205f5f61 74747269 62757465 ead2 __attribute + 01580 5f5f2828 5f5f6e6f 72657475 726e5f5f __((__noreturn__ + 01590 2929005f 5f55494e 54385f54 5950455f )).__UINT8_TYPE_ + 015a0 5f20756e 7369676e 65642063 68617200 _ unsigned char. + 015b0 5f637372 5f72645f 62756628 612c6275 _csr_rd_buf(a,bu + 015c0 662c636e 7429207b 20696e74 20692c20 f,cnt) { int i, + 015d0 6a2c206f 66667365 742c206e 73756272 j, offset, nsubr + 015e0 6567732c 206e7375 62656c65 6d733b20 egs, nsubelems; + 015f0 75696e74 36345f74 20723b20 69662028 uint64_t r; if ( + 01600 73697a65 6f662862 75665b30 5d29203e sizeof(buf[0]) > + 01610 3d204353 525f4457 5f425954 45532920 = CSR_DW_BYTES) + 01620 7b20666f 72202869 3d303b20 693c636e { for (i=0; i= 0; j + 01770 2d2d2920 7b206966 20282869 202a206e --) { if ((i * n + 01780 73756265 6c656d73 202b206a 202d206f subelems + j - o + 01790 66667365 7429203e 3d203029 207b2062 ffset) >= 0) { b + 017a0 75665b69 202a206e 73756265 6c656d73 uf[i * nsubelems + 017b0 202b206a 202d206f 66667365 745d203d + j - offset] = + 017c0 20723b20 72203e3e 3d207369 7a656f66 r; r >>= sizeof + 017d0 28627566 5b305d29 202a2038 3b207d20 (buf[0]) * 8; } + 017e0 7d206120 2b3d2043 53525f4f 46465345 } a += CSR_OFFSE + 017f0 545f4259 5445533b 207d207d 207d005f T_BYTES; } } }._ + 01800 454e445f 5354445f 43200055 494e5433 END_STD_C .UINT3 + 01810 325f4328 7829205f 5f55494e 5433325f 2_C(x) __UINT32_ + 01820 43287829 005f5f46 4c543332 5f4d494e C(x).__FLT32_MIN + 01830 5f31305f 4558505f 5f20282d 33372900 _10_EXP__ (-37). + 01840 5f534f46 545f444f 55424c45 2031005f _SOFT_DOUBLE 1._ + 01850 49434f4e 565f544f 5f454e43 4f44494e ICONV_TO_ENCODIN + 01860 475f4b4f 49385f55 4e492000 5f5f5354 G_KOI8_UNI .__ST + 01870 44435f55 54465f33 325f5f20 31005f49 DC_UTF_32__ 1._I + 01880 434f4e56 5f544f5f 454e434f 44494e47 CONV_TO_ENCODING + 01890 5f455543 5f4b5220 005f5f49 4e545f4c _EUC_KR .__INT_L + 018a0 45415354 31365f4d 41585f5f 20307837 EAST16_MAX__ 0x7 + 018b0 66666600 53434e75 38205f5f 53434e38 fff.SCNu8 __SCN8 + 018c0 28752900 5f5f636f 6e737420 636f6e73 (u).__const cons + 018d0 74005343 4e784641 53543136 205f5f53 t.SCNxFAST16 __S + 018e0 434e3136 46415354 28782900 74696d65 CN16FAST(x).time + 018f0 72305f75 70646174 655f7661 6c75655f r0_update_value_ + 01900 77726974 65005f4d 41434853 54444c49 write._MACHSTDLI + 01910 425f485f 20004353 525f5449 4d455230 B_H_ .CSR_TIMER0 + 01920 5f4c4f41 445f5349 5a452031 005f4943 _LOAD_SIZE 1._IC + 01930 4f4e565f 46524f4d 5f454e43 4f44494e ONV_FROM_ENCODIN + 01940 475f4b4f 49385f52 55200066 5f656f66 G_KOI8_RU .f_eof + 01950 28667029 20282869 6e742928 28667029 (fp) ((int)((fp) + 01960 2d3e6670 7472203d 3d202866 70292d3e ->fptr == (fp)-> + 01970 6f626a2e 6f626a73 697a6529 2900434f obj.objsize)).CO + 01980 4e464947 5f435352 5f414c49 474e4d45 NFIG_CSR_ALIGNME + 01990 4e542033 32005343 4e6f5054 52205f5f NT 32.SCNoPTR __ + 019a0 53434e50 5452286f 29004841 56455f42 SCNPTR(o).HAVE_B + 019b0 55494c54 494e5f49 53494e46 2000464d UILTIN_ISINF .FM + 019c0 5f455846 41542030 78303400 5f414e53 _EXFAT 0x04._ANS + 019d0 49444543 4c5f485f 20005f5f 55494e54 IDECL_H_ .__UINT + 019e0 31365f54 5950455f 5f207368 6f727420 16_TYPE__ short + 019f0 756e7369 676e6564 20696e74 00505245 unsigned int.PRE + 01a00 4645525f 53495a45 5f4f5645 525f5350 FER_SIZE_OVER_SP + 01a10 45454420 00505249 784c4541 53543634 EED .PRIxLEAST64 + 01a20 205f5f50 52493634 4c454153 54287829 __PRI64LEAST(x) + 01a30 005f5f73 73705f62 6f735f69 63686563 .__ssp_bos_ichec + 01a40 6b325f72 65737472 69637428 66756e2c k2_restrict(fun, + 01a50 74797065 312c7479 70653229 205f5f73 type1,type2) __s + 01a60 73705f69 6e6c696e 65207479 70653120 sp_inline type1 + 01a70 5f5f2023 23206675 6e202323 205f6963 __ ## fun ## _ic + 01a80 686b2874 79706531 2c207479 70653229 hk(type1, type2) + 01a90 3b205f5f 7373705f 696e6c69 6e652074 ; __ssp_inline t + 01aa0 79706531 205f5f20 23232066 756e2023 ype1 __ ## fun # + 01ab0 23205f69 63686b28 74797065 31205f5f # _ichk(type1 __ + 01ac0 72657374 72696374 20647374 2c207479 restrict dst, ty + 01ad0 70653220 5f5f7265 73747269 63742073 pe2 __restrict s + 01ae0 72632920 7b207265 7475726e 205f5f62 rc) { return __b + 01af0 75696c74 696e5f5f 5f202323 2066756e uiltin___ ## fun + 01b00 20232320 5f63686b 28647374 2c207372 ## _chk(dst, sr + 01b10 632c205f 5f737370 5f626f73 30286473 c, __ssp_bos0(ds + 01b20 7429293b 207d0046 465f564f 4c554d45 t)); }.FF_VOLUME + 01b30 5f535452 53202252 414d222c 224e414e _STRS "RAM","NAN + 01b40 44222c22 4346222c 22534422 2c225344 D","CF","SD","SD + 01b50 32222c22 55534222 2c225553 4232222c 2","USB","USB2", + 01b60 22555342 3322005f 545f5349 5a455f20 "USB3"._T_SIZE_ + 01b70 00435352 5f554152 545f4556 5f50454e .CSR_UART_EV_PEN + 01b80 44494e47 5f414444 52202843 53525f42 DING_ADDR (CSR_B + 01b90 41534520 2b203078 34303130 4c29005f ASE + 0x4010L)._ + 01ba0 5f464c54 3332585f 4841535f 494e4649 _FLT32X_HAS_INFI + 01bb0 4e495459 5f5f2031 00434f4e 4649475f NITY__ 1.CONFIG_ + 01bc0 4255535f 44415441 5f574944 54482033 BUS_DATA_WIDTH 3 + 01bd0 32005346 4c5f4143 4b5f5355 43434553 2.SFL_ACK_SUCCES + 01be0 5320274b 27005f5f 5645435f 454c454d S 'K'.__VEC_ELEM + 01bf0 454e545f 5245475f 4f524445 525f5f20 ENT_REG_ORDER__ + 01c00 5f5f4f52 4445525f 4249475f 454e4449 __ORDER_BIG_ENDI + 01c10 414e5f5f 005f5f42 55494c54 494e5f43 AN__.__BUILTIN_C + 01c20 50555f53 5550504f 5254535f 5f203100 PU_SUPPORTS__ 1. + 01c30 5f4e414e 4f5f464f 524d4154 5445445f _NANO_FORMATTED_ + 01c40 494f005f 5f737370 5f726564 69726563 IO.__ssp_redirec + 01c50 74287274 7970652c 66756e2c 61726773 t(rtype,fun,args + 01c60 2c63616c 6c29205f 5f737370 5f726564 ,call) __ssp_red + 01c70 69726563 745f7261 77287274 7970652c irect_raw(rtype, + 01c80 2066756e 2c206172 67732c20 63616c6c fun, args, call + 01c90 2c20312c 205f5f73 73705f62 6f732900 , 1, __ssp_bos). + 01ca0 5f5f494e 54385f43 28632920 63005f5f __INT8_C(c) c.__ + 01cb0 4c44424c 5f444543 494d414c 5f444947 LDBL_DECIMAL_DIG + 01cc0 5f5f2033 33005052 49783136 205f5f50 __ 33.PRIx16 __P + 01cd0 52493136 28782900 50524958 4d415820 RI16(x).PRIXMAX + 01ce0 5f5f5052 494d4158 28582900 5f5f7072 __PRIMAX(X).__pr + 01cf0 696e7466 306c696b 6528666d 74617267 intf0like(fmtarg + 01d00 2c666972 73747661 72617267 29200048 ,firstvararg) .H + 01d10 4156455f 494e4954 5f46494e 4920005f AVE_INIT_FINI ._ + 01d20 5f55494e 5436345f 43286329 20632023 _UINT64_C(c) c # + 01d30 2320554c 4c005f5f 464c545f 4d41585f # ULL.__FLT_MAX_ + 01d40 4558505f 5f203132 38005052 49583136 EXP__ 128.PRIX16 + 01d50 205f5f50 52493136 28582900 5f5f494e __PRI16(X).__IN + 01d60 5436345f 4d41585f 5f203078 37666666 T64_MAX__ 0x7fff + 01d70 66666666 66666666 66666666 4c4c005f ffffffffffffLL._ + 01d80 5f43435f 53555050 4f525453 5f5f5f49 _CC_SUPPORTS___I + 01d90 4e4c494e 45203100 5f5f4154 4f4d4943 NLINE 1.__ATOMIC + 01da0 5f534551 5f435354 2035005f 4743435f _SEQ_CST 5._GCC_ + 01db0 53495a45 5f542000 665f6572 726f7228 SIZE_T .f_error( + 01dc0 66702920 28286670 292d3e65 72722900 fp) ((fp)->err). + 01dd0 4353525f 54494d45 52305f45 565f454e CSR_TIMER0_EV_EN + 01de0 41424c45 5f5a4552 4f5f5349 5a452031 ABLE_ZERO_SIZE 1 + 01df0 005f5f46 4c543332 5f4d414e 545f4449 .__FLT32_MANT_DI + 01e00 475f5f20 3234005f 5f44424c 5f444947 G__ 24.__DBL_DIG + 01e10 5f5f2031 35004841 56455f49 4e495446 __ 15.HAVE_INITF + 01e20 494e495f 41525241 5920005f 5f455850 INI_ARRAY .__EXP + 01e30 28782920 5f5f2023 23782023 235f5f00 (x) __ ##x ##__. + 01e40 46415f4f 50454e5f 414c5741 59532030 FA_OPEN_ALWAYS 0 + 01e50 78313000 55494e54 31365f4d 41582028 x10.UINT16_MAX ( + 01e60 5f5f5549 4e543136 5f4d4158 5f5f2900 __UINT16_MAX__). + 01e70 5f542878 29207800 73747063 70792864 _T(x) x.stpcpy(d + 01e80 73742c73 72632920 5f5f7373 705f626f st,src) __ssp_bo + 01e90 735f6368 65636b32 28737470 6370792c s_check2(stpcpy, + 01ea0 20647374 2c207372 6329005f 5f726571 dst, src).__req + 01eb0 75697265 735f6578 636c7573 69766528 uires_exclusive( + 01ec0 2e2e2e29 205f5f6c 6f636b5f 616e6e6f ...) __lock_anno + 01ed0 74617465 28657863 6c757369 76655f6c tate(exclusive_l + 01ee0 6f636b73 5f726571 75697265 64285f5f ocks_required(__ + 01ef0 56415f41 5247535f 5f292900 5f5f4445 VA_ARGS__)).__DE + 01f00 5155414c 49465928 74797065 2c766172 QUALIFY(type,var + 01f10 29202828 74797065 29285f5f 75696e74 ) ((type)(__uint + 01f20 7074725f 74292863 6f6e7374 20766f6c ptr_t)(const vol + 01f30 6174696c 6520766f 6964202a 29287661 atile void *)(va + 01f40 72292900 5f5f6861 735f6665 61747572 r)).__has_featur + 01f50 65287829 20300046 4c545f4d 414e545f e(x) 0.FLT_MANT_ + 01f60 44494720 5f5f464c 545f4d41 4e545f44 DIG __FLT_MANT_D + 01f70 49475f5f 005f5f52 414e445f 4d415820 IG__.__RAND_MAX + 01f80 30783766 66666666 66660053 434e7546 0x7fffffff.SCNuF + 01f90 41535438 205f5f53 434e3846 41535428 AST8 __SCN8FAST( + 01fa0 75290053 434e7838 205f5f53 434e3828 u).SCNx8 __SCN8( + 01fb0 78290049 4e543634 5f4d4158 20285f5f x).INT64_MAX (__ + 01fc0 494e5436 345f4d41 585f5f29 004a534d INT64_MAX__).JSM + 01fd0 4e5f4152 52415900 4353525f 55415254 N_ARRAY.CSR_UART + 01fe0 5f525846 554c4c5f 53495a45 20310046 _RXFULL_SIZE 1.F + 01ff0 4d5f5346 44203078 3038005f 46444556 M_SFD 0x08._FDEV + 02000 5f455252 20282d31 29005343 4e6f4641 _ERR (-1).SCNoFA + 02010 53543332 205f5f53 434e3332 46415354 ST32 __SCN32FAST + 02020 286f2900 5f5f6174 74726962 7574655f (o).__attribute_ + 02030 6d616c6c 6f635f5f 20005f53 495a455f malloc__ ._SIZE_ + 02040 545f4445 434c4152 45442000 5f5f5549 T_DECLARED .__UI + 02050 4e545f4c 45415354 33325f4d 41585f5f NT_LEAST32_MAX__ + 02060 20307866 66666666 66666655 005f5f41 0xffffffffU.__A + 02070 54545249 42555445 5f494d50 5552455f TTRIBUTE_IMPURE_ + 02080 5054525f 5f205f5f 61747472 69627574 PTR__ __attribut + 02090 655f5f28 285f5f73 65637469 6f6e5f5f e__((__section__ + 020a0 28222e73 64617461 22292929 005f5f4c (".sdata"))).__L + 020b0 44424c5f 45505349 4c4f4e5f 5f20342e DBL_EPSILON__ 4. + 020c0 39343036 35363435 38343132 34363534 9406564584124654 + 020d0 34313736 35363837 39323836 38323231 4176568792868221 + 020e0 652d3332 344c005f 49434f4e 565f4652 e-324L._ICONV_FR + 020f0 4f4d5f45 4e434f44 494e475f 49534f5f OM_ENCODING_ISO_ + 02100 38383539 5f313520 005f4245 47494e5f 8859_15 ._BEGIN_ + 02110 5354445f 43200066 5f726577 696e6464 STD_C .f_rewindd + 02120 69722864 70292066 5f726561 64646972 ir(dp) f_readdir + 02130 28286470 292c2030 29005f5f 4445434f ((dp), 0).__DECO + 02140 4e535428 74797065 2c766172 29202828 NST(type,var) (( + 02150 74797065 29285f5f 75696e74 7074725f type)(__uintptr_ + 02160 74292863 6f6e7374 20766f69 64202a29 t)(const void *) + 02170 28766172 2929005f 48415645 5f43435f (var))._HAVE_CC_ + 02180 494e4849 4249545f 4c4f4f50 5f544f5f INHIBIT_LOOP_TO_ + 02190 4c494243 414c4c20 005f5f46 4c543332 LIBCALL .__FLT32 + 021a0 585f4d49 4e5f5f20 322e3232 35303733 X_MIN__ 2.225073 + 021b0 38353835 30373230 31333833 30393032 8585072013830902 + 021c0 33323731 37333332 3430652d 33303846 3271733240e-308F + 021d0 33327800 464c545f 4d415820 5f5f464c 32x.FLT_MAX __FL + 021e0 545f4d41 585f5f00 5f49434f 4e565f54 T_MAX__._ICONV_T + 021f0 4f5f454e 434f4449 4e475f55 43535f32 O_ENCODING_UCS_2 + 02200 5f494e54 45524e41 4c200049 4e545f46 _INTERNAL .INT_F + 02210 41535431 365f4d41 5820285f 5f494e54 AST16_MAX (__INT + 02220 5f464153 5431365f 4d41585f 5f290053 _FAST16_MAX__).S + 02230 434e7546 41535436 34205f5f 53434e36 CNuFAST64 __SCN6 + 02240 34464153 54287529 0046465f 5354525f 4FAST(u).FF_STR_ + 02250 564f4c55 4d455f49 44203000 4353525f VOLUME_ID 0.CSR_ + 02260 4354524c 5f534352 41544348 5f414444 CTRL_SCRATCH_ADD + 02270 52202843 53525f42 41534520 2b203078 R (CSR_BASE + 0x + 02280 32383034 4c29005f 5f464c54 33325f4d 2804L).__FLT32_M + 02290 494e5f45 58505f5f 20282d31 32352900 IN_EXP__ (-125). + 022a0 74797065 00505249 6f313620 5f5f5052 type.PRIo16 __PR + 022b0 49313628 6f29005f 5f444543 494d414c I16(o).__DECIMAL + 022c0 5f444947 5f5f2033 33005f43 414c4c5f _DIG__ 33._CALL_ + 022d0 53595356 20310043 53525f43 54524c5f SYSV 1.CSR_CTRL_ + 022e0 4255535f 4552524f 52535f53 495a4520 BUS_ERRORS_SIZE + 022f0 3100616c 6c6f6361 00505249 78333220 1.alloca.PRIx32 + 02300 5f5f5052 49333228 78290073 74726361 __PRI32(x).strca + 02310 74286473 742c7372 6329205f 5f737370 t(dst,src) __ssp + 02320 5f626f73 5f636865 636b3228 73747263 _bos_check2(strc + 02330 61742c20 6473742c 20737263 29005f5f at, dst, src).__ + 02340 696e7432 30202b32 005f4743 435f5054 int20 +2._GCC_PT + 02350 52444946 465f5420 00435352 5f435452 RDIFF_T .CSR_CTR + 02360 4c5f5245 5345545f 41444452 20284353 L_RESET_ADDR (CS + 02370 525f4241 5345202b 20307832 3830304c R_BASE + 0x2800L + 02380 29005f49 434f4e56 5f46524f 4d5f454e )._ICONV_FROM_EN + 02390 434f4449 4e475f55 43535f34 5f494e54 CODING_UCS_4_INT + 023a0 45524e41 4c200049 4e545f4c 45415354 ERNAL .INT_LEAST + 023b0 36345f4d 41582028 5f5f494e 545f4c45 64_MAX (__INT_LE + 023c0 41535436 345f4d41 585f5f29 005f5354 AST64_MAX__)._ST + 023d0 44444546 5f485f20 005f5f50 49434f4c DDEF_H_ .__PICOL + 023e0 4942435f 554e4745 54435f53 495a4520 IBC_UNGETC_SIZE + 023f0 32004353 525f5449 4d455230 5f56414c 2.CSR_TIMER0_VAL + 02400 55455f41 44445220 28435352 5f424153 UE_ADDR (CSR_BAS + 02410 45202b20 30783338 31304c29 005f5f75 E + 0x3810L).__u + 02420 696e7431 365f7400 5f49434f 4e565f46 int16_t._ICONV_F + 02430 524f4d5f 454e434f 44494e47 5f455543 ROM_ENCODING_EUC + 02440 5f4b5220 00464c54 5f4d494e 5f455850 _KR .FLT_MIN_EXP + 02450 004a534d 4e5f4552 524f525f 4e4f4d45 .JSMN_ERROR_NOME + 02460 4d005f5f 53524420 30783030 3031005f M.__SRD 0x0001._ + 02470 5f474e55 434c494b 455f4153 4d203300 _GNUCLIKE_ASM 3. + 02480 5f5f5054 52444946 465f5749 4454485f __PTRDIFF_WIDTH_ + 02490 5f203332 005f5f46 42534449 44287329 _ 32.__FBSDID(s) + 024a0 20737472 75637420 5f5f6861 636b005f struct __hack._ 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7373705f 696e6c69 6e652074 79706531 ssp_inline type1 + 03100 205f5f20 23232066 756e2023 23205f69 __ ## fun ## _i + 03110 63686b28 74797065 312c2074 79706532 chk(type1, type2 + 03120 2c207369 7a655f74 293b205f 5f737370 , size_t); __ssp + 03130 5f696e6c 696e6520 74797065 31205f5f _inline type1 __ + 03140 20232320 66756e20 2323205f 6963686b ## fun ## _ichk + 03150 28747970 65312064 73742c20 74797065 (type1 dst, type + 03160 32207372 632c2073 697a655f 74206c65 2 src, size_t le + 03170 6e29207b 20726574 75726e20 5f5f6275 n) { return __bu + 03180 696c7469 6e5f5f5f 20232320 66756e20 iltin___ ## fun + 03190 2323205f 63686b28 6473742c 20737263 ## _chk(dst, src + 031a0 2c206c65 6e2c205f 5f737370 5f626f73 , len, __ssp_bos + 031b0 30286473 7429293b 207d005f 5f76615f 0(dst)); }.__va_ + 031c0 636f7079 28642c73 29205f5f 6275696c copy(d,s) __buil + 031d0 74696e5f 76615f63 6f707928 642c7329 tin_va_copy(d,s) + 031e0 005f5f47 4e55435f 56415f4c 4953545f .__GNUC_VA_LIST_ + 031f0 434f4d50 41544942 494c4954 59203100 COMPATIBILITY 1. + 03200 48415645 5f434f4d 504c4558 20005052 HAVE_COMPLEX .PR + 03210 49754c45 41535438 205f5f50 5249384c IuLEAST8 __PRI8L + 03220 45415354 28752900 4a534d4e 5f455252 EAST(u).JSMN_ERR + 03230 4f525f49 4e56414c 00505249 69464153 OR_INVAL.PRIiFAS + 03240 54333220 5f5f5052 49333246 41535428 T32 __PRI32FAST( + 03250 69290046 465f5553 455f4649 4e442030 i).FF_USE_FIND 0 + 03260 005f5f46 4c543332 5f4d4158 5f5f2033 .__FLT32_MAX__ 3 + 03270 2e343032 38323334 36363338 35323838 .402823466385288 + 03280 35393831 31373034 31383334 38343531 5981170418348451 + 03290 37652b33 38463332 005f5f5f 696e7431 7e+38F32.___int1 + 032a0 365f745f 64656669 6e656420 31006a73 6_t_defined 1.js + 032b0 6d6e5f61 6c6c6f63 5f746f6b 656e005f mn_alloc_token._ + 032c0 5f474e55 434c494b 455f4d41 54485f42 _GNUCLIKE_MATH_B + 032d0 55494c54 494e5f52 454c4f50 5320005f UILTIN_RELOPS ._ + 032e0 55494e54 31365f54 5f444543 4c415245 UINT16_T_DECLARE + 032f0 4420005f 49434f4e 565f4652 4f4d5f45 D ._ICONV_FROM_E + 03300 4e434f44 494e475f 49534f5f 38383539 NCODING_ISO_8859 + 03310 5f342000 48415645 5f494545 4546505f _4 .HAVE_IEEEFP_ + 03320 46554e43 53004646 5f46535f 54494e59 FUNCS.FF_FS_TINY + 03330 20310066 6465765f 636c6f73 65286629 1.fdev_close(f) + 03340 20286666 6c757368 28662929 00737464 (fflush(f)).std + 03350 6f757400 5f5f4445 4333325f 4d494e5f out.__DEC32_MIN_ + 03360 5f203145 2d393544 46005f5f 464c545f _ 1E-95DF.__FLT_ + 03370 4d494e5f 4558505f 5f20282d 31323529 MIN_EXP__ (-125) + 03380 005f4943 4f4e565f 544f5f45 4e434f44 ._ICONV_TO_ENCOD + 03390 494e475f 57494e5f 31323535 20004646 ING_WIN_1255 .FF + 033a0 5f555345 5f455850 414e4420 30004d45 _USE_EXPAND 0.ME + 033b0 4d5f5245 47494f4e 53202252 4f4d2020 M_REGIONS "ROM + 033c0 20202020 20307830 30303030 30303020 0x00000000 + 033d0 30783130 30303020 5c6e5352 414d2020 0x10000 \nSRAM + 033e0 20202020 30783030 30313030 30302030 0x00010000 0 + 033f0 78313030 3030205c 6e4d4149 4e5f5241 x10000 \nMAIN_RA + 03400 4d202030 78303130 30303030 30203078 M 0x01000000 0x + 03410 31303030 30303020 5c6e4353 52202020 1000000 \nCSR + 03420 20202020 30786666 66303030 30302030 0xfff00000 0 + 03430 78313030 30302022 00484156 455f4643 x10000 ".HAVE_FC + 03440 4e544c00 5f504f49 4e544552 5f494e54 NTL._POINTER_INT + 03450 206c6f6e 6700434f 4e464947 5f435352 long.CONFIG_CSR + 03460 5f444154 415f5749 44544820 3332005f _DATA_WIDTH 32._ + 03470 5f747279 6c6f636b 735f6578 636c7573 _trylocks_exclus + 03480 69766528 2e2e2e29 205f5f6c 6f636b5f ive(...) __lock_ + 03490 616e6e6f 74617465 28657863 6c757369 annotate(exclusi + 034a0 76655f74 72796c6f 636b5f66 756e6374 ve_trylock_funct + 034b0 696f6e28 5f5f5641 5f415247 535f5f29 ion(__VA_ARGS__) + 034c0 29005f5f 464c545f 52414449 585f5f20 ).__FLT_RADIX__ + 034d0 32005f5f 494e5433 325f4328 63292063 2.__INT32_C(c) c + 034e0 005f414e 53495f53 54444152 475f485f ._ANSI_STDARG_H_ + 034f0 2000696e 74202b32 00435352 5f554152 .int +2.CSR_UAR + 03500 545f4556 5f535441 5455535f 54585f53 T_EV_STATUS_TX_S + 03510 495a4520 31005f5f 464c5433 32585f44 IZE 1.__FLT32X_D + 03520 49475f5f 20313500 5f5f4558 43455054 IG__ 15.__EXCEPT + 03530 494f4e53 2031005f 5f616c6c 6f635f73 IONS 1.__alloc_s + 03540 697a6528 78292000 50524958 46415354 ize(x) .PRIXFAST + 03550 3136205f 5f505249 31364641 53542858 16 __PRI16FAST(X + 03560 29005f5f 48415645 5f425357 41505f5f ).__HAVE_BSWAP__ + 03570 2031005f 5f464c54 5f455641 4c5f4d45 1.__FLT_EVAL_ME + 03580 54484f44 5f54535f 31383636 315f335f THOD_TS_18661_3_ + 03590 5f203000 53434e75 4c454153 54363420 _ 0.SCNuLEAST64 + 035a0 5f5f5343 4e36344c 45415354 28752900 __SCN64LEAST(u). + 035b0 4d495353 494e475f 53595343 414c4c5f MISSING_SYSCALL_ + 035c0 4e414d45 53005f5f 55494e54 4d41585f NAMES.__UINTMAX_ + 035d0 4d41585f 5f203078 66666666 66666666 MAX__ 0xffffffff + 035e0 66666666 66666666 554c4c00 5f49434f ffffffffULL._ICO + 035f0 4e565f46 524f4d5f 454e434f 44494e47 NV_FROM_ENCODING + 03600 5f49534f 5f383835 395f3520 0044424c _ISO_8859_5 .DBL + 03610 5f444947 205f5f44 424c5f44 49475f5f _DIG __DBL_DIG__ + 03620 005f5641 5f4c4953 545f2000 464c545f ._VA_LIST_ .FLT_ + 03630 4d494e20 5f5f464c 545f4d49 4e5f5f00 MIN __FLT_MIN__. + 03640 5f5f5050 43203100 5f5f4445 43313238 __PPC 1.__DEC128 + 03650 5f4d4158 5f455850 5f5f2036 31343500 _MAX_EXP__ 6145. + 03660 5f5f4e4f 5f465052 535f5f20 31005f46 __NO_FPRS__ 1._F + 03670 4445565f 53455455 505f5752 49544520 DEV_SETUP_WRITE + 03680 5f5f5357 52005449 4d455230 5f494e54 __SWR.TIMER0_INT + 03690 45525255 50542031 0053434e 75464153 ERRUPT 1.SCNuFAS + 036a0 54333220 5f5f5343 4e333246 41535428 T32 __SCN32FAST( + 036b0 7529005f 5f737370 5f646563 6c287274 u).__ssp_decl(rt + 036c0 7970652c 66756e2c 61726773 29207274 ype,fun,args) rt + 036d0 79706520 5f5f7373 705f7265 616c5f28 ype __ssp_real_( + 036e0 66756e29 20617267 73205f5f 61736d5f fun) args __asm_ + 036f0 5f285f5f 41534d4e 414d4528 2366756e _(__ASMNAME(#fun + 03700 29293b20 5f5f7373 705f696e 6c696e65 )); __ssp_inline + 03710 20727479 70652066 756e2061 72677300 rtype fun args. + 03720 5f49434f 4e565f54 4f5f454e 434f4449 _ICONV_TO_ENCODI + 03730 4e475f57 494e5f31 32353620 005f5f44 NG_WIN_1256 .__D + 03740 45433332 5f535542 4e4f524d 414c5f4d EC32_SUBNORMAL_M + 03750 494e5f5f 20302e30 30303030 31452d39 IN__ 0.000001E-9 + 03760 35444600 5f5f7373 705f7265 64697265 5DF.__ssp_redire + 03770 63745f72 61772872 74797065 2c66756e ct_raw(rtype,fun + 03780 2c617267 732c6361 6c6c2c63 6f6e642c ,args,call,cond, + 03790 626f7329 205f5f73 73705f64 65636c28 bos) __ssp_decl( + 037a0 72747970 652c2066 756e2c20 61726773 rtype, fun, args + 037b0 29207b20 69662028 636f6e64 29205f5f ) { if (cond) __ + 037c0 7373705f 63686563 6b285f5f 6275662c ssp_check(__buf, + 037d0 205f5f6c 656e2c20 626f7329 3b207265 __len, bos); re + 037e0 7475726e 205f5f73 73705f72 65616c5f turn __ssp_real_ + 037f0 2866756e 29206361 6c6c3b20 7d004c44 (fun) call; }.LD + 03800 424c5f4d 414e545f 44494700 53434e78 BL_MANT_DIG.SCNx + 03810 4c454153 54333220 5f5f5343 4e33324c LEAST32 __SCN32L + 03820 45415354 28782900 5f5f4e45 574c4942 EAST(x).__NEWLIB + 03830 5f504154 43484c45 56454c5f 5f203000 _PATCHLEVEL__ 0. + 03840 5052496f 4c454153 5438205f 5f505249 PRIoLEAST8 __PRI + 03850 384c4541 5354286f 29005f5f 464c545f 8LEAST(o).__FLT_ + 03860 4d494e5f 31305f45 58505f5f 20282d33 MIN_10_EXP__ (-3 + 03870 3729005f 5f55494e 545f4641 5354385f 7).__UINT_FAST8_ + 03880 54595045 5f5f2075 6e736967 6e656420 TYPE__ unsigned + 03890 63686172 00434d44 5f54494d 454f5554 char.CMD_TIMEOUT + 038a0 5f44454c 41592043 4f4e4649 475f434c _DELAY CONFIG_CL + 038b0 4f434b5f 46524551 55454e43 592f3136 OCK_FREQUENCY/16 + 038c0 005f494e 5433325f 545f4445 434c4152 ._INT32_T_DECLAR + 038d0 45442000 5f5f494e 545f5749 4454485f ED .__INT_WIDTH_ + 038e0 5f203332 00464643 4f4e465f 44454620 _ 32.FFCONF_DEF + 038f0 38363630 36004353 525f4c45 44535f4f 86606.CSR_LEDS_O + 03900 55545f53 495a4520 3100494e 545f4641 UT_SIZE 1.INT_FA + 03910 5354385f 4d415820 285f5f49 4e545f46 ST8_MAX (__INT_F + 03920 41535438 5f4d4158 5f5f2900 5f5f5359 AST8_MAX__).__SY + 03930 5354454d 5f482000 464c545f 4d41585f STEM_H .FLT_MAX_ + 03940 45585020 5f5f464c 545f4d41 585f4558 EXP __FLT_MAX_EX + 03950 505f5f00 46465f55 53455f4c 4142454c P__.FF_USE_LABEL + 03960 2030006e 756d5f74 6f6b656e 73005343 0.num_tokens.SC + 03970 4e783634 205f5f53 434e3634 28782900 Nx64 __SCN64(x). + 03980 4c44424c 5f4d494e 5f455850 005f5f69 LDBL_MIN_EXP.__i + 03990 6e745f66 61737438 5f745f64 6566696e nt_fast8_t_defin + 039a0 65642031 005f5f44 424c5f4d 494e5f5f ed 1.__DBL_MIN__ + 039b0 20282864 6f75626c 6529322e 32323530 ((double)2.2250 + 039c0 37333835 38353037 32303133 38333039 7385850720138309 + 039d0 30323332 37313733 33323430 652d3330 023271733240e-30 + 039e0 384c2900 5052496f 50545220 5f5f5052 8L).PRIoPTR __PR + 039f0 49505452 286f2900 5f5f7765 616b5f72 IPTR(o).__weak_r + 03a00 65666572 656e6365 2873796d 2c616c69 eference(sym,ali + 03a10 61732920 5f5f6173 6d5f5f28 222e7765 as) __asm__(".we + 03a20 616b2022 2023616c 69617329 3b205f5f ak " #alias); __ + 03a30 61736d5f 5f28222e 65717520 22202361 asm__(".equ " #a + 03a40 6c696173 20222c20 22202373 796d2900 lias ", " #sym). + 03a50 48415645 5f425549 4c54494e 5f464653 HAVE_BUILTIN_FFS + 03a60 4c200046 4d5f4641 54203078 30310050 L .FM_FAT 0x01.P + 03a70 52497838 205f5f50 52493828 7829005f RIx8 __PRI8(x)._ + 03a80 5f6e6565 645f4e55 4c4c2000 5f5f474e _need_NULL .__GN + 03a90 55434c49 4b455f42 55494c54 494e5f4e UCLIKE_BUILTIN_N + 03aa0 4558545f 41524720 31005f49 434f4e56 EXT_ARG 1._ICONV + 03ab0 5f544f5f 454e434f 44494e47 5f57494e _TO_ENCODING_WIN + 03ac0 5f313235 3720005f 49434f4e 565f544f _1257 ._ICONV_TO + 03ad0 5f454e43 4f44494e 475f4350 38353520 _ENCODING_CP855 + 03ae0 005f5f46 4c543634 5f4d4158 5f5f2031 .__FLT64_MAX__ 1 + 03af0 2e373937 36393331 33343836 32333135 .797693134862315 + 03b00 37303831 34353237 34323337 33313730 7081452742373170 + 03b10 34652b33 30384636 3400524f 4d5f5349 4e+308F64.ROM_SI + 03b20 5a452030 78303030 31303030 30005f5f ZE 0x00010000.__ + 03b30 464c5433 32585f44 4543494d 414c5f44 FLT32X_DECIMAL_D + 03b40 49475f5f 20313700 5f5f4743 435f4154 IG__ 17.__GCC_AT + 03b50 4f4d4943 5f434841 5233325f 545f4c4f OMIC_CHAR32_T_LO + 03b60 434b5f46 52454520 32005f5f 494e5433 CK_FREE 2.__INT3 + 03b70 3220005f 5f494e54 31365f54 5950455f 2 .__INT16_TYPE_ + 03b80 5f207368 6f727420 696e7400 4353525f _ short int.CSR_ + 03b90 54494d45 52305f52 454c4f41 445f4144 TIMER0_RELOAD_AD + 03ba0 44522028 4353525f 42415345 202b2030 DR (CSR_BASE + 0 + 03bb0 78333830 344c2900 5f5f696e 745f6661 x3804L).__int_fa + 03bc0 73743136 5f745f64 6566696e 65642031 st16_t_defined 1 + 03bd0 005f5f47 4e55434c 494b455f 4255494c .__GNUCLIKE_BUIL + 03be0 54494e5f 4d454d43 50592031 00474e55 TIN_MEMCPY 1.GNU + 03bf0 20433939 20392e34 2e30202d 6d736563 C99 9.4.0 -msec + 03c00 7572652d 706c7420 2d6d3332 202d6d62 ure-plt -m32 -mb + 03c10 69672d65 6e646961 6e202d6d 6e6f2d6d ig-endian -mno-m + 03c20 756c7469 706c6520 2d6d736f 66742d66 ultiple -msoft-f + 03c30 6c6f6174 202d6733 202d4f73 202d7374 loat -g3 -Os -st + 03c40 643d676e 75393920 2d666f6d 69742d66 d=gnu99 -fomit-f + 03c50 72616d65 2d706f69 6e746572 202d666e rame-pointer -fn + 03c60 6f2d6275 696c7469 6e202d66 6e6f2d73 o-builtin -fno-s + 03c70 7461636b 2d70726f 74656374 6f72202d tack-protector - + 03c80 66657863 65707469 6f6e7300 5f5f7379 fexceptions.__sy + 03c90 6d5f6465 6661756c 74287379 6d2c696d m_default(sym,im + 03ca0 706c2c76 65726964 29205f5f 61736d5f pl,verid) __asm_ + 03cb0 5f28222e 73796d76 65722022 2023696d _(".symver " #im + 03cc0 706c2022 2c202220 2373796d 20224040 pl ", " #sym "@@ + 03cd0 22202376 65726964 29005f5f 55494e54 " #verid).__UINT + 03ce0 5f4c4541 53543332 5f545950 455f5f20 _LEAST32_TYPE__ + 03cf0 756e7369 676e6564 20696e74 00435352 unsigned int.CSR + 03d00 5f554152 545f4556 5f535441 5455535f _UART_EV_STATUS_ + 03d10 53495a45 2031005f 5f505249 36344c45 SIZE 1.__PRI64LE + 03d20 41535428 7829205f 5f4c4541 53543634 AST(x) __LEAST64 + 03d30 205f5f53 5452494e 47494659 28782900 __STRINGIFY(x). + 03d40 5f5f4743 435f4154 4f4d4943 5f4c4f4e __GCC_ATOMIC_LON + 03d50 475f4c4f 434b5f46 52454520 32005f49 G_LOCK_FREE 2._I + 03d60 434f4e56 5f46524f 4d5f454e 434f4449 CONV_FROM_ENCODI + 03d70 4e475f49 534f5f38 3835395f 3720005f NG_ISO_8859_7 ._ + 03d80 5f464c54 36345f45 5053494c 4f4e5f5f _FLT64_EPSILON__ + 03d90 20322e32 32303434 36303439 32353033 2.2204460492503 + 03da0 31333038 30383437 32363333 33363138 1308084726333618 + 03db0 31363465 2d313646 3634005f 5f696e74 164e-16F64.__int + 03dc0 5f666173 7433325f 745f6465 66696e65 _fast32_t_define + 03dd0 64203100 5f49434f 4e565f46 524f4d5f d 1._ICONV_FROM_ + 03de0 454e434f 44494e47 5f49534f 5f383835 ENCODING_ISO_885 + 03df0 395f3620 005f5245 54415247 45544142 9_6 ._RETARGETAB + 03e00 4c455f4c 4f434b49 4e472000 5f5f5343 LE_LOCKING .__SC + 03e10 4e363446 41535428 7829205f 5f464153 N64FAST(x) __FAS + 03e20 54363420 5f5f5354 52494e47 49465928 T64 __STRINGIFY( + 03e30 7829005f 5359535f 5f4c4f43 414c455f x)._SYS__LOCALE_ + 03e40 48200050 5249694c 45415354 38205f5f H .PRIiLEAST8 __ + 03e50 50524938 4c454153 54286929 005f5f69 PRI8LEAST(i).__i + 03e60 6e686962 69745f6e 65775f62 75696c74 nhibit_new_built + 03e70 696e5f63 616c6c73 20005f5f 464c5433 in_calls .__FLT3 + 03e80 32585f4d 41585f5f 20312e37 39373639 2X_MAX__ 1.79769 + 03e90 33313334 38363233 31353730 38313435 3134862315708145 + 03ea0 32373432 33373331 37303465 2b333038 27423731704e+308 + 03eb0 46333278 0044424c 5f4d414e 545f4449 F32x.DBL_MANT_DI + 03ec0 47205f5f 44424c5f 4d414e54 5f444947 G __DBL_MANT_DIG + 03ed0 5f5f005f 49434f4e 565f544f 5f454e43 __._ICONV_TO_ENC + 03ee0 4f44494e 475f4953 4f5f3838 35395f31 ODING_ISO_8859_1 + 03ef0 3420005f 5f636f6d 70696c65 725f6d65 4 .__compiler_me + 03f00 6d626172 2829205f 5f61736d 205f5f76 mbar() __asm __v + 03f10 6f6c6174 696c6528 22202220 3a203a20 olatile(" " : : + 03f20 3a20226d 656d6f72 79222900 48415645 : "memory").HAVE + 03f30 5f425549 4c54494e 5f434f50 59534947 _BUILTIN_COPYSIG + 03f40 4e20005f 5f535649 445f5649 5349424c N .__SVID_VISIBL + 03f50 45203100 5f5f7373 705f626f 73287074 E 1.__ssp_bos(pt + 03f60 7229205f 5f627569 6c74696e 5f6f626a r) __builtin_obj + 03f70 6563745f 73697a65 28707472 2c205f5f ect_size(ptr, __ + 03f80 5353505f 464f5254 4946595f 4c455645 SSP_FORTIFY_LEVE + 03f90 4c203e20 31290050 52495846 41535438 L > 1).PRIXFAST8 + 03fa0 205f5f50 52493846 41535428 58290063 __PRI8FAST(X).c + 03fb0 6c656172 6572726f 72287329 20646f20 learerror(s) do + 03fc0 7b202873 292d3e66 6c616773 20263d20 { (s)->flags &= + 03fd0 7e285f5f 53455252 207c205f 5f53454f ~(__SERR | __SEO + 03fe0 46293b20 7d207768 696c6528 30290046 F); } while(0).F + 03ff0 535f4641 54313220 31004653 5f464154 S_FAT12 1.FS_FAT + 04000 33322033 0041544f 4d49435f 554e4745 32 3.ATOMIC_UNGE + 04010 5443005f 5f70745f 67756172 6465645f TC.__pt_guarded_ + 04020 62792878 29205f5f 6c6f636b 5f616e6e by(x) __lock_ann + 04030 6f746174 65287074 5f677561 72646564 otate(pt_guarded + 04040 5f627928 78292900 66646576 5f736574 _by(x)).fdev_set + 04050 75705f73 74726561 6d287374 7265616d up_stream(stream + 04060 2c702c67 2c666c2c 66292064 6f207b20 ,p,g,fl,f) do { + 04070 28737472 65616d29 2d3e666c 61677320 (stream)->flags + 04080 3d20663b 20287374 7265616d 292d3e70 = f; (stream)->p + 04090 7574203d 20703b20 28737472 65616d29 ut = p; (stream) + 040a0 2d3e6765 74203d20 673b2028 73747265 ->get = g; (stre + 040b0 616d292d 3e666c75 7368203d 20666c3b am)->flush = fl; + 040c0 207d2077 68696c65 28302900 4353525f } while(0).CSR_ + 040d0 55415254 5f525846 554c4c5f 41444452 UART_RXFULL_ADDR + 040e0 20284353 525f4241 5345202b 20307834 (CSR_BASE + 0x4 + 040f0 3031634c 29005343 4e644c45 41535431 01cL).SCNdLEAST1 + 04100 36205f5f 53434e31 364c4541 53542864 6 __SCN16LEAST(d + 04110 29005f53 4f46545f 464c4f41 54203100 )._SOFT_FLOAT 1. + 04120 5f474343 5f574348 41525f54 20005f57 _GCC_WCHAR_T ._W + 04130 43484152 5f545f44 4546494e 45445f20 CHAR_T_DEFINED_ + 04140 00505249 644c4541 53543136 205f5f50 .PRIdLEAST16 __P + 04150 52493136 4c454153 54286429 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41535431 365f4d41 585f5f20 2d203129 AST16_MAX__ - 1) + 052d0 005f5741 4e545f52 45454e54 5f534d41 ._WANT_REENT_SMA + 052e0 4c4c005f 5f737370 5f6f7665 726c6170 LL.__ssp_overlap + 052f0 28612c62 2c6c2920 28282861 29203c3d (a,b,l) (((a) <= + 05300 20286229 20262620 28622920 3c202861 (b) && (b) < (a + 05310 29202b20 286c2929 207c7c20 28286229 ) + (l)) || ((b) + 05320 203c3d20 28612920 26262028 6129203c <= (a) && (a) < + 05330 20286229 202b2028 6c292929 00505249 (b) + (l))).PRI + 05340 784c4541 53543332 205f5f50 52493332 xLEAST32 __PRI32 + 05350 4c454153 54287829 005f5f6c 6f636b73 LEAST(x).__locks + 05360 5f736861 72656428 2e2e2e29 205f5f6c _shared(...) __l + 05370 6f636b5f 616e6e6f 74617465 28736861 ock_annotate(sha + 05380 7265645f 6c6f636b 5f66756e 6374696f red_lock_functio + 05390 6e285f5f 56415f41 5247535f 5f292900 n(__VA_ARGS__)). + 053a0 48415645 5f424954 4649454c 44535f49 HAVE_BITFIELDS_I + 053b0 4e5f5041 434b4544 5f535452 55435453 N_PACKED_STRUCTS + 053c0 20005346 4c5f4d41 4749435f 4c454e20 .SFL_MAGIC_LEN + 053d0 3134005f 5f505249 31362878 29205f5f 14.__PRI16(x) __ + 053e0 494e5431 36205f5f 53545249 4e474946 INT16 __STRINGIF + 053f0 59287829 005f5f53 495a455f 4d41585f Y(x).__SIZE_MAX_ + 05400 5f203078 66666666 66666666 55005f5f _ 0xffffffffU.__ + 05410 53495a45 4f465f53 495a455f 545f5f20 SIZEOF_SIZE_T__ + 05420 34005343 4e645054 52205f5f 53434e50 4.SCNdPTR __SCNP + 05430 54522864 29005f5f 464c545f 4d41585f TR(d).__FLT_MAX_ + 05440 31305f45 58505f5f 20333800 5f5f474e 10_EXP__ 38.__GN + 05450 55434c49 4b455f43 544f525f 53454354 UCLIKE_CTOR_SECT + 05460 494f4e5f 48414e44 4c494e47 20310053 ION_HANDLING 1.S + 05470 434e7846 41535438 205f5f53 434e3846 CNxFAST8 __SCN8F + 05480 41535428 78290043 4f4e4649 475f434c AST(x).CONFIG_CL + 05490 4f434b5f 46524551 55454e43 59203130 OCK_FREQUENCY 10 + 054a0 30303030 30303000 5f5f4c44 424c5f4d 0000000.__LDBL_M + 054b0 494e5f31 305f4558 505f5f20 282d3239 IN_10_EXP__ (-29 + 054c0 31290055 494e5431 365f4328 7829205f 1).UINT16_C(x) _ + 054d0 5f55494e 5431365f 43287829 0055494e _UINT16_C(x).UIN + 054e0 545f4641 53543136 5f4d4158 20285f5f T_FAST16_MAX (__ + 054f0 55494e54 5f464153 5431365f 4d41585f UINT_FAST16_MAX_ + 05500 5f290043 4c4b4745 4e5f5354 41545553 _).CLKGEN_STATUS + 05510 5f425553 59203078 31005f5f 6e656564 _BUSY 0x1.__need + 05520 5f4e554c 4c006f66 66736574 6f662854 _NULL.offsetof(T + 05530 5950452c 4d454d42 45522920 5f5f6275 YPE,MEMBER) __bu + 05540 696c7469 6e5f6f66 66736574 6f662028 iltin_offsetof ( + 05550 54595045 2c204d45 4d424552 29005f5f TYPE, MEMBER).__ + 05560 636f6e74 61696e65 726f6628 782c732c containerof(x,s, + 05570 6d292028 7b20636f 6e737420 766f6c61 m) ({ const vola + 05580 74696c65 205f5f74 7970656f 66282828 tile __typeof((( + 05590 73202a29 30292d3e 6d29202a 5f5f7820 s *)0)->m) *__x + 055a0 3d202878 293b205f 5f444551 55414c49 = (x); __DEQUALI + 055b0 46592873 202a2c20 28636f6e 73742076 FY(s *, (const v + 055c0 6f6c6174 696c6520 63686172 202a295f olatile char *)_ + 055d0 5f78202d 205f5f6f 66667365 746f6628 _x - __offsetof( + 055e0 732c206d 29293b7d 29005343 4e694c45 s, m));}).SCNiLE + 055f0 41535438 205f5f53 434e384c 45415354 AST8 __SCN8LEAST + 05600 28692900 5f54494d 45525f54 5f20756e (i)._TIMER_T_ un + 05610 7369676e 6564206c 6f6e6700 5f5f7061 signed long.__pa + 05620 636b6564 205f5f61 74747269 62757465 cked __attribute + 05630 5f5f2828 5f5f7061 636b6564 5f5f2929 __((__packed__)) + 05640 0053434e 6f313620 5f5f5343 4e313628 .SCNo16 __SCN16( + 05650 6f29005f 57414e54 5f494f5f 4c4f4e47 o)._WANT_IO_LONG + 05660 5f4c4f4e 47206661 6c736500 5f5f4743 _LONG false.__GC + 05670 435f4841 56455f53 594e435f 434f4d50 C_HAVE_SYNC_COMP + 05680 4152455f 414e445f 53574150 5f312031 ARE_AND_SWAP_1 1 + 05690 005f4e45 574c4942 5f414c4c 4f43415f ._NEWLIB_ALLOCA_ + 056a0 48200053 434e7833 32205f5f 53434e33 H .SCNx32 __SCN3 + 056b0 32287829 0053434e 694d4158 205f5f53 2(x).SCNiMAX __S + 056c0 434e4d41 58286929 00434f4e 4649475f CNMAX(i).CONFIG_ + 056d0 4d41494e 5f52414d 5f494e49 54203100 MAIN_RAM_INIT 1. + 056e0 4e45574c 49425f54 48524541 445f4c4f NEWLIB_THREAD_LO + 056f0 43414c20 005f5f55 494e5433 325f5459 CAL .__UINT32_TY + 05700 50455f5f 20756e73 69676e65 6420696e PE__ unsigned in + 05710 74005343 4e6f4641 53543820 5f5f5343 t.SCNoFAST8 __SC + 05720 4e384641 5354286f 29005f5f 6d696e5f N8FAST(o).__min_ + 05730 73697a65 28782920 73746174 69632028 size(x) static ( + 05740 78290050 5249694c 45415354 3332205f x).PRIiLEAST32 _ + 05750 5f505249 33324c45 41535428 6929005f _PRI32LEAST(i)._ + 05760 5359535f 5f545950 45535f48 20005f5f SYS__TYPES_H .__ + 05770 53444341 52445f48 20005f5f 4c4f4e47 SDCARD_H .__LONG + 05780 5f4d4158 5f5f2030 78376666 66666666 _MAX__ 0x7ffffff + 05790 664c0043 53525f4c 4544535f 4f55545f fL.CSR_LEDS_OUT_ + 057a0 41444452 20284353 525f4241 5345202b ADDR (CSR_BASE + + 057b0 20307831 3830304c 29005f5f 52435349 0x1800L).__RCSI + 057c0 44287329 20737472 75637420 5f5f6861 D(s) struct __ha + 057d0 636b005f 5f454e44 5f444543 4c532000 ck.__END_DECLS . + 057e0 4353525f 54494d45 52305f45 565f454e CSR_TIMER0_EV_EN + 057f0 41424c45 5f414444 52202843 53525f42 ABLE_ADDR (CSR_B + 05800 41534520 2b203078 33383163 4c29005f ASE + 0x381cL)._ + 05810 48415645 5f4e4f5f 4255494c 54494e5f HAVE_NO_BUILTIN_ + 05820 41545452 49425554 45005f5f 7373705f ATTRIBUTE.__ssp_ + 05830 626f7330 28707472 29205f5f 6275696c bos0(ptr) __buil + 05840 74696e5f 6f626a65 63745f73 697a6528 tin_object_size( + 05850 7074722c 20302900 5f5f4445 4336345f ptr, 0).__DEC64_ + 05860 45505349 4c4f4e5f 5f203145 2d313544 EPSILON__ 1E-15D + 05870 44007368 6f727420 2b310043 53525f54 D.short +1.CSR_T + 05880 494d4552 305f4556 5f535441 5455535f IMER0_EV_STATUS_ + 05890 5a45524f 5f4f4646 53455420 3000494e ZERO_OFFSET 0.IN + 058a0 544d4158 5f4d4158 20285f5f 494e544d TMAX_MAX (__INTM + 058b0 41585f4d 41585f5f 29005049 434f4c49 AX_MAX__).PICOLI + 058c0 42435f53 5444494f 5f474c4f 42414c53 BC_STDIO_GLOBALS + 058d0 20005f49 434f4e56 5f46524f 4d5f454e ._ICONV_FROM_EN + 058e0 434f4449 4e475f45 55435f4a 5020005f CODING_EUC_JP ._ + 058f0 5f444543 33325f4d 41585f45 58505f5f _DEC32_MAX_EXP__ + 05900 20393700 5f5f5354 52494e47 49465928 97.__STRINGIFY( + 05910 61292023 61004353 525f5349 5a452030 a) #a.CSR_SIZE 0 + 05920 78303030 31303030 30004841 56455f42 x00010000.HAVE_B + 05930 55494c54 494e5f43 4f505953 49474e4c UILTIN_COPYSIGNL + 05940 20006661 696c7572 65730046 465f5553 .failures.FF_US + 05950 455f4c46 4e203100 48415645 5f425549 E_LFN 1.HAVE_BUI + 05960 4c54494e 5f464653 20006a73 6d6e7479 LTIN_FFS .jsmnty + 05970 70655f74 00464d5f 414e5920 30783037 pe_t.FM_ANY 0x07 + 05980 005f5f73 697a655f 745f5f20 00666c75 .__size_t__ .flu + 05990 73685f63 70755f69 63616368 65005f5f sh_cpu_icache.__ + 059a0 5359535f 434f4e46 49475f48 5f5f2000 SYS_CONFIG_H__ . + 059b0 5f5f7072 65646963 745f6661 6c736528 __predict_false( + 059c0 65787029 205f5f62 75696c74 696e5f65 exp) __builtin_e + 059d0 78706563 74282865 7870292c 20302900 xpect((exp), 0). + 059e0 5f5f4558 504f5254 20005f5f 43484152 __EXPORT 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6861735f 696e636c 7564655f .__has_include_ + 05b00 6e657874 28535452 29205f5f 6861735f next(STR) __has_ + 05b10 696e636c 7564655f 6e657874 5f5f2853 include_next__(S + 05b20 54522900 756e7369 676e6564 20736967 TR).unsigned sig + 05b30 6e656400 50524975 4d415820 5f5f5052 ned.PRIuMAX __PR + 05b40 494d4158 28752900 5f5f494e 5433325f IMAX(u).__INT32_ + 05b50 54595045 5f5f2069 6e74005f 5f494e54 TYPE__ int.__INT + 05b60 5054525f 4d41585f 5f203078 37666666 PTR_MAX__ 0x7fff + 05b70 66666666 00737470 6e637079 28647374 ffff.stpncpy(dst + 05b80 2c737263 2c6c656e 29205f5f 7373705f ,src,len) __ssp_ + 05b90 626f735f 63686563 6b332873 74706e63 bos_check3(stpnc + 05ba0 70792c20 6473742c 20737263 2c206c65 py, dst, src, le + 05bb0 6e29005f 5f505249 50545228 7829205f n).__PRIPTR(x) _ + 05bc0 5f535452 494e4749 46592878 29005f57 _STRINGIFY(x)._W + 05bd0 414e545f 494f5f43 39395f46 4f524d41 ANT_IO_C99_FORMA + 05be0 54532000 53434e69 4c454153 54363420 TS .SCNiLEAST64 + 05bf0 5f5f5343 4e36344c 45415354 28692900 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53434e33 32287529 005f414e 53495f53 SCN32(u)._ANSI_S + 05d10 54444445 465f4820 005f464f 52544946 TDDEF_H ._FORTIF + 05d20 595f534f 55524345 2032005f 5f434f4e Y_SOURCE 2.__CON + 05d30 534f4c45 5f482000 57494e54 5f4d494e SOLE_H .WINT_MIN + 05d40 20285f5f 57494e54 5f4d494e 5f5f2900 (__WINT_MIN__). + 05d50 5f5f5343 4e31364c 45415354 28782920 __SCN16LEAST(x) + 05d60 5f5f4c45 41535431 36205f5f 53545249 __LEAST16 __STRI + 05d70 4e474946 59287829 005f4943 4f4e565f NGIFY(x)._ICONV_ + 05d80 544f5f45 4e434f44 494e475f 57494e5f TO_ENCODING_WIN_ + 05d90 31323531 20005f49 434f4e56 5f46524f 1251 ._ICONV_FRO + 05da0 4d5f454e 434f4449 4e475f55 54465f38 M_ENCODING_UTF_8 + 05db0 20005f43 4c4f434b 49445f54 5f20756e ._CLOCKID_T_ un + 05dc0 7369676e 6564206c 6f6e6700 5f5f4343 signed long.__CC + 05dd0 5f535550 504f5254 535f5641 52414449 _SUPPORTS_VARADI + 05de0 435f5858 58203100 53434e64 46415354 C_XXX 1.SCNdFAST + 05df0 3634205f 5f53434e 36344641 53542864 64 __SCN64FAST(d + 05e00 29005052 49644c45 41535433 32205f5f ).PRIdLEAST32 __ + 05e10 50524933 324c4541 53542864 29005f5f PRI32LEAST(d).__ + 05e20 55494e54 33325f43 28632920 63202323 UINT32_C(c) c ## + 05e30 2055005f 5f464c54 36345f4d 41585f45 U.__FLT64_MAX_E + 05e40 58505f5f 20313032 34005f5f 53504953 XP__ 1024.__SPIS + 05e50 44434152 445f4820 005f5f68 61735f65 DCARD_H .__has_e + 05e60 7874656e 73696f6e 205f5f68 61735f66 xtension __has_f + 05e70 65617475 72650046 4c545f4d 41585f45 eature.FLT_MAX_E + 05e80 58500073 74726e63 61742864 73742c73 XP.strncat(dst,s + 05e90 72632c6c 656e2920 5f5f7373 705f626f rc,len) __ssp_bo + 05ea0 735f6368 65636b33 28737472 6e636174 s_check3(strncat + 05eb0 2c206473 742c2073 72632c20 6c656e29 , dst, src, len) + 05ec0 005f5f4c 45415354 33322000 5f5f756e .__LEAST32 .__un + 05ed0 6c6f636b 73282e2e 2e29205f 5f6c6f63 locks(...) __loc + 05ee0 6b5f616e 6e6f7461 74652875 6e6c6f63 k_annotate(unloc + 05ef0 6b5f6675 6e637469 6f6e285f 5f56415f k_function(__VA_ + 05f00 41524753 5f5f2929 00435352 5f54494d ARGS__)).CSR_TIM + 05f10 4552305f 45565f53 54415455 535f4144 ER0_EV_STATUS_AD + 05f20 44522028 4353525f 42415345 202b2030 DR (CSR_BASE + 0 + 05f30 78333831 344c2900 5f5f464c 5436345f x3814L).__FLT64_ + 05f40 44454e4f 524d5f4d 494e5f5f 20342e39 DENORM_MIN__ 4.9 + 05f50 34303635 36343538 34313234 36353434 4065645841246544 + 05f60 31373635 36383739 32383638 32323165 176568792868221e + 05f70 2d333234 46363400 5f494e54 54595045 -324F64._INTTYPE + 05f80 535f4820 005f4644 45565f53 45545550 S_H ._FDEV_SETUP + 05f90 5f524541 44205f5f 53524400 4353525f _READ __SRD.CSR_ + 05fa0 42555454 4f4e535f 494e5f41 44445220 BUTTONS_IN_ADDR + 05fb0 28435352 5f424153 45202b20 30783230 (CSR_BASE + 0x20 + 05fc0 30304c29 00505249 69363420 5f5f5052 00L).PRIi64 __PR + 05fd0 49363428 69290053 45454b5f 43555220 I64(i).SEEK_CUR + 05fe0 31005f49 434f4e56 5f46524f 4d5f454e 1._ICONV_FROM_EN + 05ff0 434f4449 4e475f4b 4f49385f 5220005f CODING_KOI8_R ._ + 06000 49454545 5f4c4942 4d200043 53525f43 IEEE_LIBM .CSR_C + 06010 54524c5f 4255535f 4552524f 52535f41 TRL_BUS_ERRORS_A + 06020 44445220 28435352 5f424153 45202b20 DDR (CSR_BASE + + 06030 30783238 30384c29 005f5f77 61726e5f 0x2808L).__warn_ + 06040 72656665 72656e63 65732873 796d2c6d references(sym,m + 06050 73672920 5f5f6173 6d5f5f28 222e7365 sg) __asm__(".se + 06060 6374696f 6e202e67 6e752e77 61726e69 ction .gnu.warni + 06070 6e672e22 20237379 6d293b20 5f5f6173 ng." #sym); __as + 06080 6d5f5f28 222e6173 63697a20 5c222220 m__(".asciz \"" + 06090 6d736720 225c2222 293b205f 5f61736d msg "\""); __asm + 060a0 5f5f2822 2e707265 76696f75 73222900 __(".previous"). + 060b0 5f5f6765 6e657269 63286578 70722c74 __generic(expr,t + 060c0 2c796573 2c6e6f29 205f5f62 75696c74 ,yes,no) __built + 060d0 696e5f63 686f6f73 655f6578 70722820 in_choose_expr( + 060e0 5f5f6275 696c7469 6e5f7479 7065735f __builtin_types_ + 060f0 636f6d70 61746962 6c655f70 285f5f74 compatible_p(__t + 06100 7970656f 66286578 7072292c 2074292c ypeof(expr), t), + 06110 20796573 2c206e6f 29005f5f 6c696e75 yes, no).__linu + 06120 785f5f20 31005052 49644641 53543136 x__ 1.PRIdFAST16 + 06130 205f5f50 52493136 46415354 28642900 __PRI16FAST(d). + 06140 67657463 68617228 29206667 65746328 getchar() fgetc( + 06150 73746469 6e29005f 5f524547 49535445 stdin).__REGISTE + 06160 525f5052 45464958 5f5f2000 5f5f4f42 R_PREFIX__ .__OB + 06170 534f4c45 54455f4d 4154485f 44454641 SOLETE_MATH_DEFA + 06180 554c545f 464c4f41 54203100 5f5f4745 ULT_FLOAT 1.__GE + 06190 4e455241 5445445f 4d454d5f 48200055 NERATED_MEM_H .U + 061a0 494e544d 41585f43 28782920 5f5f5549 INTMAX_C(x) __UI + 061b0 4e544d41 585f4328 78290043 53525f43 NTMAX_C(x).CSR_C + 061c0 54524c5f 42415345 20284353 525f4241 TRL_BASE (CSR_BA + 061d0 5345202b 20307832 3830304c 29004641 SE + 0x2800L).FA + 061e0 5f435245 4154455f 4e455720 30783034 _CREATE_NEW 0x04 + 061f0 005f4943 4f4e565f 46524f4d 5f454e43 ._ICONV_FROM_ENC + 06200 4f44494e 475f5749 4e5f3132 35302000 ODING_WIN_1250 . + 06210 6972715f 7365746d 61736b00 5f5f7074 irq_setmask.__pt + 06220 725f7420 766f6964 202a005f 5f535350 r_t void *.__SSP + 06230 5f464f52 54494659 5f4c4556 454c2032 _FORTIFY_LEVEL 2 + 06240 0053434e 78464153 54333220 5f5f5343 .SCNxFAST32 __SC + 06250 4e333246 41535428 78290075 6e736967 N32FAST(x).unsig + 06260 6e656400 6373725f 77726974 655f7369 ned.csr_write_si + 06270 6d706c65 0046415f 43524541 54455f41 mple.FA_CREATE_A + 06280 4c574159 53203078 3038005f 5f4c4152 LWAYS 0x08.__LAR + 06290 47454649 4c455f56 49534942 4c452030 GEFILE_VISIBLE 0 + 062a0 00484156 455f4255 494c5449 4e5f4558 .HAVE_BUILTIN_EX + 062b0 50454354 20005f5f 55494e54 4d41585f PECT .__UINTMAX_ + 062c0 43286329 20632023 2320554c 4c006a73 C(c) c ## ULL.js + 062d0 6d6e5f66 696c6c5f 746f6b65 6e004353 mn_fill_token.CS + 062e0 525f4354 524c5f52 45534554 5f534f43 R_CTRL_RESET_SOC + 062f0 5f525354 5f4f4646 53455420 30004353 _RST_OFFSET 0.CS + 06300 525f5449 4d455230 5f45565f 50454e44 R_TIMER0_EV_PEND + 06310 494e475f 41444452 20284353 525f4241 ING_ADDR (CSR_BA + 06320 5345202b 20307833 3831384c 29005f5f SE + 0x3818L).__ + 06330 48415645 5f4c4f43 414c455f 494e464f HAVE_LOCALE_INFO + 06340 5f5f0046 465f4c46 4e5f4255 46203235 __.FF_LFN_BUF 25 + 06350 35005052 49784641 53543820 5f5f5052 5.PRIxFAST8 __PR + 06360 49384641 53542878 29005f5f 494e545f I8FAST(x).__INT_ + 06370 4c454153 5433325f 4d41585f 5f203078 LEAST32_MAX__ 0x + 06380 37666666 66666666 00756172 745f7772 7fffffff.uart_wr + 06390 69746500 5052496f 4c454153 54363420 ite.PRIoLEAST64 + 063a0 5f5f5052 4936344c 45415354 286f2900 __PRI64LEAST(o). + 063b0 434f4e46 49475f43 50555f52 45534554 CONFIG_CPU_RESET + 063c0 5f414444 52203000 55494e54 385f4d41 _ADDR 0.UINT8_MA + 063d0 5820285f 5f55494e 54385f4d 41585f5f X (__UINT8_MAX__ + 063e0 29004353 525f4354 524c5f52 45534554 ).CSR_CTRL_RESET + 063f0 5f435055 5f525354 5f53495a 45203100 _CPU_RST_SIZE 1. + 06400 5f5f4442 4c5f4841 535f4445 4e4f524d __DBL_HAS_DENORM + 06410 5f5f2031 005f5f41 5446494c 455f5649 __ 1.__ATFILE_VI + 06420 5349424c 45203100 5f5f5549 4e543332 SIBLE 1.__UINT32 + 06430 5f4d4158 5f5f2030 78666666 66666666 _MAX__ 0xfffffff + 06440 6655005f 5f464c54 36345f4d 41585f31 fU.__FLT64_MAX_1 + 06450 305f4558 505f5f20 33303800 5f5f636f 0_EXP__ 308.__co + 06460 6d706172 5f666e5f 745f6465 66696e65 mpar_fn_t_define + 06470 6420005f 5f505249 31364c45 41535428 d .__PRI16LEAST( + 06480 7829205f 5f4c4541 53543136 205f5f53 x) __LEAST16 __S + 06490 5452494e 47494659 28782900 50524978 TRINGIFY(x).PRIx + 064a0 4d415820 5f5f5052 494d4158 28782900 MAX __PRIMAX(x). + 064b0 50524958 4c454153 54313620 5f5f5052 PRIXLEAST16 __PR + 064c0 4931364c 45415354 28582900 5352414d I16LEAST(X).SRAM + 064d0 5f424153 45203078 30303031 30303030 _BASE 0x00010000 + 064e0 4c00494e 544d4158 5f432878 29205f5f L.INTMAX_C(x) __ + 064f0 494e544d 41585f43 28782900 4c44424c INTMAX_C(x).LDBL + 06500 5f4d494e 205f5f4c 44424c5f 4d494e5f _MIN __LDBL_MIN_ + 06510 5f005f5f 696e7432 305f5f20 2b320043 _.__int20__ +2.C + 06520 4c4b4745 4e5f5354 41545553 5f50524f LKGEN_STATUS_PRO + 06530 47444f4e 45203078 32005f5f 4743435f GDONE 0x2.__GCC_ + 06540 41544f4d 49435f43 48415231 365f545f ATOMIC_CHAR16_T_ + 06550 4c4f434b 5f465245 45203200 5f5f4442 LOCK_FREE 2.__DB + 06560 4c5f4d41 585f5f20 2828646f 75626c65 L_MAX__ ((double + 06570 29312e37 39373639 33313334 38363233 )1.7976931348623 + 06580 31353730 38313435 32373432 33373331 1570814527423731 + 06590 37303465 2b333038 4c290043 53525f44 704e+308L).CSR_D + 065a0 575f4259 54455320 28434f4e 4649475f W_BYTES (CONFIG_ + 065b0 4353525f 44415441 5f574944 54482f38 CSR_DATA_WIDTH/8 + 065c0 29005f5f 474e5543 5f535444 435f494e ).__GNUC_STDC_IN + 065d0 4c494e45 5f5f2031 00505249 64313620 LINE__ 1.PRId16 + 065e0 5f5f5052 49313628 6429005f 49434f4e __PRI16(d)._ICON + 065f0 565f544f 5f454e43 4f44494e 475f5543 V_TO_ENCODING_UC + 06600 535f344c 45200053 434e7546 41535431 S_4LE .SCNuFAST1 + 06610 36205f5f 53434e31 36464153 54287529 6 __SCN16FAST(u) + 06620 00435352 5f554152 545f4556 5f454e41 .CSR_UART_EV_ENA + 06630 424c455f 52585f53 495a4520 31005343 BLE_RX_SIZE 1.SC + 06640 4e693820 5f5f5343 4e382869 29004653 Ni8 __SCN8(i).FS + 06650 5f455846 41542034 00435352 5f54494d _EXFAT 4.CSR_TIM + 06660 4552305f 42415345 20284353 525f4241 ER0_BASE (CSR_BA + 06670 5345202b 20307833 3830304c 29007374 SE + 0x3800L).st + 06680 72746f64 66207374 72746f66 005f5f50 rtodf strtof.__P + 06690 4d542861 72677329 20617267 73005052 MT(args) args.PR + 066a0 496f4641 53543820 5f5f5052 49384641 IoFAST8 __PRI8FA + 066b0 5354286f 29005343 4e783136 205f5f53 ST(o).SCNx16 __S + 066c0 434e3136 28782900 5f5f5853 495f5649 CN16(x).__XSI_VI + 066d0 5349424c 45203000 5f5f5052 49313646 SIBLE 0.__PRI16F + 066e0 41535428 7829205f 5f464153 54313620 AST(x) __FAST16 + 066f0 5f5f5354 52494e47 49465928 7829005f __STRINGIFY(x)._ + 06700 5f737472 6674696d 656c696b 6528666d _strftimelike(fm + 06710 74617267 2c666972 73747661 72617267 targ,firstvararg + 06720 29205f5f 61747472 69627574 655f5f28 ) __attribute__( + 06730 285f5f66 6f726d61 745f5f20 285f5f73 (__format__ (__s + 06740 74726674 696d655f 5f2c2066 6d746172 trftime__, fmtar + 06750 672c2066 69727374 76617261 72672929 g, firstvararg)) + 06760 29005f49 434f4e56 5f46524f 4d5f454e )._ICONV_FROM_EN + 06770 434f4449 4e475f45 55435f54 5720005f CODING_EUC_TW ._ + 06780 5f505452 44494646 5f542000 50524958 _PTRDIFF_T .PRIX + 06790 4c454153 54333220 5f5f5052 4933324c LEAST32 __PRI32L + 067a0 45415354 28582900 4c44424c 5f4d4158 EAST(X).LDBL_MAX + 067b0 5f31305f 45585020 5f5f4c44 424c5f4d _10_EXP __LDBL_M + 067c0 41585f31 305f4558 505f5f00 5052496f AX_10_EXP__.PRIo + 067d0 46415354 3634205f 5f505249 36344641 FAST64 __PRI64FA + 067e0 5354286f 2900464c 545f524f 554e4453 ST(o).FLT_ROUNDS + 067f0 2031005f 49434f4e 565f544f 5f454e43 1._ICONV_TO_ENC + 06800 4f44494e 475f5553 5f415343 49492000 ODING_US_ASCII . + 06810 6972715f 73657469 65005f5f 4c454153 irq_setie.__LEAS + 06820 54382022 68682200 5f5f464c 5433325f T8 "hh".__FLT32_ + 06830 4841535f 44454e4f 524d5f5f 2031005f HAS_DENORM__ 1._ + 06840 5f737472 666d6f6e 6c696b65 28666d74 _strfmonlike(fmt + 06850 6172672c 66697273 74766172 61726729 arg,firstvararg) + 06860 205f5f61 74747269 62757465 5f5f2828 __attribute__(( + 06870 5f5f666f 726d6174 5f5f2028 5f5f7374 __format__ (__st + 06880 72666d6f 6e5f5f2c 20666d74 6172672c rfmon__, fmtarg, + 06890 20666972 73747661 72617267 29292900 firstvararg))). + 068a0 6a736d6e 65727200 5052496f 4d415820 jsmnerr.PRIoMAX + 068b0 5f5f5052 494d4158 286f2900 5f5f616c __PRIMAX(o).__al + 068c0 77617973 5f696e6c 696e6520 5f5f696e ways_inline __in + 068d0 6c696e65 5f5f205f 5f617474 72696275 line__ __attribu + 068e0 74655f5f 28285f5f 616c7761 79735f69 te__((__always_i + 068f0 6e6c696e 655f5f29 29004353 525f5541 nline__)).CSR_UA + 06900 52545f45 565f5354 41545553 5f54585f RT_EV_STATUS_TX_ + 06910 4f464653 45542030 0046415f 4f50454e OFFSET 0.FA_OPEN + 06920 5f455849 5354494e 47203078 3030005f _EXISTING 0x00._ + 06930 5f53495a 455f5420 0046465f 5553455f _SIZE_T .FF_USE_ + 06940 464f5257 41524420 30005f5f 464c5433 FORWARD 0.__FLT3 + 06950 325f4550 53494c4f 4e5f5f20 312e3139 2_EPSILON__ 1.19 + 06960 32303932 38393535 30373831 32353030 2092895507812500 + 06970 30303030 30303030 30303030 3030652d 00000000000000e- + 06980 37463332 00435352 5f554152 545f5258 7F32.CSR_UART_RX + 06990 54585f53 495a4520 3100756e 67657400 TX_SIZE 1.unget. + 069a0 5f49434f 4e565f46 524f4d5f 454e434f _ICONV_FROM_ENCO + 069b0 44494e47 5f4b4f49 385f5520 005f494e DING_KOI8_U ._IN + 069c0 435f5443 48415220 005f5f70 75726532 C_TCHAR .__pure2 + 069d0 205f5f61 74747269 62757465 5f5f2828 __attribute__(( + 069e0 5f5f636f 6e73745f 5f292900 5f5f4743 __const__)).__GC + 069f0 435f4154 4f4d4943 5f53484f 52545f4c C_ATOMIC_SHORT_L + 06a00 4f434b5f 46524545 2032006d 61782878 OCK_FREE 2.max(x + 06a10 2c792920 28282878 29203e20 28792929 ,y) (((x) > (y)) + 06a20 203f2028 7829203a 20287929 29005052 ? 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5443485f 53495a45 20310050 52497531 TCH_SIZE 1.PRIu1 + 06b40 36205f5f 50524931 36287529 005f4943 6 __PRI16(u)._IC + 06b50 4f4e565f 46524f4d 5f454e43 4f44494e ONV_FROM_ENCODIN + 06b60 475f4350 38363620 00435352 5f554152 G_CP866 .CSR_UAR + 06b70 545f5458 46554c4c 5f414444 52202843 T_TXFULL_ADDR (C + 06b80 53525f42 41534520 2b203078 34303034 SR_BASE + 0x4004 + 06b90 4c29005f 5f55494e 544d4158 5f545950 L).__UINTMAX_TYP + 06ba0 455f5f20 6c6f6e67 206c6f6e 6720756e E__ long long un + 06bb0 7369676e 65642069 6e74005f 5f434841 signed int.__CHA + 06bc0 5233325f 54595045 5f5f2075 6e736967 R32_TYPE__ unsig + 06bd0 6e656420 696e7400 50524964 46415354 ned int.PRIdFAST + 06be0 38205f5f 50524938 46415354 28642900 8 __PRI8FAST(d). + 06bf0 5f5f4c4f 4e47444f 55424c45 31323820 __LONGDOUBLE128 + 06c00 31007375 626f7074 61726700 434f4e46 1.suboptarg.CONF + 06c10 49475f43 50555f4e 4f502022 6e6f7022 IG_CPU_NOP "nop" + 06c20 0041434b 5f4f4b00 5f5f494e 54505452 .ACK_OK.__INTPTR + 06c30 5f574944 54485f5f 20333200 4d41494e _WIDTH__ 32.MAIN + 06c40 5f52414d 5f424153 45203078 30313030 _RAM_BASE 0x0100 + 06c50 30303030 4c005f5f 696e7432 30005343 0000L.__int20.SC + 06c60 4e754c45 41535431 36205f5f 53434e31 NuLEAST16 __SCN1 + 06c70 364c4541 53542875 29005f5f 7472796c 6LEAST(u).__tryl + 06c80 6f636b73 5f736861 72656428 2e2e2e29 ocks_shared(...) + 06c90 205f5f6c 6f636b5f 616e6e6f 74617465 __lock_annotate + 06ca0 28736861 7265645f 7472796c 6f636b5f (shared_trylock_ + 06cb0 66756e63 74696f6e 285f5f56 415f4152 function(__VA_AR + 06cc0 47535f5f 2929005f 5f434f4e 43415431 GS__)).__CONCAT1 + 06cd0 28782c79 29207820 23232079 005f5f48 (x,y) x ## y.__H + 06ce0 575f434f 4d4d4f4e 5f482000 5f5f7265 W_COMMON_H .__re + 06cf0 73756c74 5f757365 5f636865 636b205f sult_use_check _ + 06d00 5f617474 72696275 74655f5f 28285f5f _attribute__((__ + 06d10 7761726e 5f756e75 7365645f 72657375 warn_unused_resu + 06d20 6c745f5f 2929005f 5f474e55 435f5052 lt__)).__GNUC_PR + 06d30 45524551 286d616a 2c6d696e 29202828 EREQ(maj,min) (( + 06d40 5f5f474e 55435f5f 203c3c20 31362920 __GNUC__ << 16) + 06d50 2b205f5f 474e5543 5f4d494e 4f525f5f + __GNUC_MINOR__ + 06d60 203e3d20 28286d61 6a29203c 3c203136 >= ((maj) << 16 + 06d70 29202b20 286d696e 2929005f 5f424947 ) + (min)).__BIG + 06d80 5f454e44 49414e5f 5f203100 53434e78 _ENDIAN__ 1.SCNx + 06d90 4c454153 5438205f 5f53434e 384c4541 LEAST8 __SCN8LEA + 06da0 53542878 29005f5f 464c5436 345f4841 ST(x).__FLT64_HA + 06db0 535f494e 46494e49 54595f5f 2031004c S_INFINITY__ 1.L + 06dc0 44424c5f 4d415800 50524969 46415354 DBL_MAX.PRIiFAST + 06dd0 3634205f 5f505249 36344641 53542869 64 __PRI64FAST(i + 06de0 29006163 6b5f7374 61747573 005f5f4c ).ack_status.__L + 06df0 4f4e475f 4c4f4e47 5f4d4158 5f5f2030 ONG_LONG_MAX__ 0 + 06e00 78376666 66666666 66666666 66666666 x7ffffffffffffff + 06e10 664c4c00 494e5438 5f4d494e 20282d5f fLL.INT8_MIN (-_ + 06e20 5f494e54 385f4d41 585f5f20 2d203129 _INT8_MAX__ - 1) + 06e30 005f545f 57434841 525f2000 55494e54 ._T_WCHAR_ .UINT + 06e40 36345f43 28782920 5f5f5549 4e543634 64_C(x) __UINT64 + 06e50 5f432878 29005f5f 53544443 5f564552 _C(x).__STDC_VER + 06e60 53494f4e 5f5f2031 39393930 314c005f SION__ 199901L._ + 06e70 504f5349 585f435f 534f5552 43450046 POSIX_C_SOURCE.F + 06e80 465f4653 5f525041 54482030 005f5f52 F_FS_RPATH 0.__R + 06e90 43534944 5f534f55 52434528 73292073 CSID_SOURCE(s) s + 06ea0 74727563 74205f5f 6861636b 00505249 truct __hack.PRI + 06eb0 64333220 5f5f5052 49333228 6429005f d32 __PRI32(d)._ + 06ec0 5f49534f 5f435f56 49534942 4c452031 _ISO_C_VISIBLE 1 + 06ed0 39393900 53434e75 4c454153 54333220 999.SCNuLEAST32 + 06ee0 5f5f5343 4e33324c 45415354 28752900 __SCN32LEAST(u). + 06ef0 5f49434f 4e565f45 4e41424c 455f4558 _ICONV_ENABLE_EX + 06f00 5445524e 414c5f43 43530046 465f4653 TERNAL_CCS.FF_FS + 06f10 5f4e4f52 54432031 005f5359 535f4344 _NORTC 1._SYS_CD + 06f20 4546535f 485f2000 5f4e414e 4f5f4d41 EFS_H_ ._NANO_MA + 06f30 4c4c4f43 20005f5f 5049434f 4c494243 LLOC .__PICOLIBC + 06f40 5f504154 43484c45 56454c5f 5f203300 _PATCHLEVEL__ 3. + 06f50 4c44424c 5f455053 494c4f4e 205f5f4c LDBL_EPSILON __L + 06f60 44424c5f 45505349 4c4f4e5f 5f005052 DBL_EPSILON__.PR + 06f70 496f3332 205f5f50 52493332 286f2900 Io32 __PRI32(o). + 06f80 5f464445 565f5345 5455505f 52572028 _FDEV_SETUP_RW ( + 06f90 5f5f5352 447c5f5f 53575229 005f5f46 __SRD|__SWR).__F + 06fa0 4c545f45 5053494c 4f4e5f5f 20312e31 LT_EPSILON__ 1.1 + 06fb0 39323039 32383935 35303738 31323530 9209289550781250 + 06fc0 30303030 30303030 30303030 30303065 000000000000000e + 06fd0 2d374600 5f5f4c4f 4e475f4c 4f4e475f -7F.__LONG_LONG_ + 06fe0 57494454 485f5f20 36340046 4445565f WIDTH__ 64.FDEV_ + 06ff0 53455455 505f5354 5245414d 28702c67 SETUP_STREAM(p,g + 07000 2c666c2c 6629207b 202e666c 61677320 ,fl,f) { .flags + 07010 3d20662c 202e7075 74203d20 702c202e = f, .put = p, . + 07020 67657420 3d20672c 202e666c 75736820 get = g, .flush + 07030 3d20666c 2c207d00 50524975 46415354 = fl, }.PRIuFAST + 07040 3332205f 5f505249 33324641 53542875 32 __PRI32FAST(u + 07050 29007469 6d657230 5f6c6f61 645f7772 ).timer0_load_wr + 07060 69746500 5f5f4442 4c5f4d41 4e545f44 ite.__DBL_MANT_D + 07070 49475f5f 20353300 5f49434f 4e565f54 IG__ 53._ICONV_T + 07080 4f5f454e 434f4449 4e475f4b 4f49385f O_ENCODING_KOI8_ + 07090 5520005f 49434f4e 565f544f 5f454e43 U ._ICONV_TO_ENC + 070a0 4f44494e 475f5543 535f3442 45200055 ODING_UCS_4BE .U + 070b0 494e545f 46415354 33325f4d 41582028 INT_FAST32_MAX ( + 070c0 5f5f5549 4e545f46 41535433 325f4d41 __UINT_FAST32_MA + 070d0 585f5f29 00415445 5849545f 4d415820 X__).ATEXIT_MAX + 070e0 33320045 54484d41 435f4556 5f535241 32.ETHMAC_EV_SRA + 070f0 4d5f5245 41444552 20307831 00737464 M_READER 0x1.std + 07100 696e0050 5249644c 45415354 38205f5f in.PRIdLEAST8 __ + 07110 50524938 4c454153 54286429 0052414e PRI8LEAST(d).RAN + 07120 445f4d41 58205f5f 52414e44 5f4d4158 D_MAX __RAND_MAX + 07130 00434c4b 47454e5f 53544154 55535f4c .CLKGEN_STATUS_L + 07140 4f434b45 44203078 34005f5f 55494e54 OCKED 0x4.__UINT + 07150 5f4c4541 53543136 5f545950 455f5f20 _LEAST16_TYPE__ + 07160 73686f72 7420756e 7369676e 65642069 short unsigned i + 07170 6e740043 53525f55 4152545f 45565f50 nt.CSR_UART_EV_P + 07180 454e4449 4e475f54 585f5349 5a452031 ENDING_TX_SIZE 1 + 07190 005f5f4c 44424c5f 4841535f 51554945 .__LDBL_HAS_QUIE + 071a0 545f4e41 4e5f5f20 31005f5f 5f696e74 T_NAN__ 1.___int + 071b0 5f776368 61725f74 5f682000 434f4e46 _wchar_t_h .CONF + 071c0 49475f52 4f4d5f49 4e495420 31005f5f IG_ROM_INIT 1.__ + 071d0 54465450 5f482000 45584954 5f535543 TFTP_H .EXIT_SUC + 071e0 43455353 20300076 615f656e 64287629 CESS 0.va_end(v) + 071f0 205f5f62 75696c74 696e5f76 615f656e __builtin_va_en + 07200 64287629 005f504f 5349585f 435f534f d(v)._POSIX_C_SO + 07210 55524345 20323030 3830394c 00494e54 URCE 200809L.INT + 07220 5054525f 4d415820 285f5f49 4e545054 PTR_MAX (__INTPT + 07230 525f4d41 585f5f29 00505249 6f464153 R_MAX__).PRIoFAS + 07240 54313620 5f5f5052 49313646 41535428 T16 __PRI16FAST( + 07250 6f290041 4d5f4152 43203078 32300053 o).AM_ARC 0x20.S + 07260 464c5f43 4d445f4a 554d5020 30783032 FL_CMD_JUMP 0x02 + 07270 00435352 5f554152 545f4556 5f454e41 .CSR_UART_EV_ENA + 07280 424c455f 52585f4f 46465345 54203100 BLE_RX_OFFSET 1. + 07290 5f5f4745 4e455241 5445445f 534f435f __GENERATED_SOC_ + 072a0 4820005f 49434f4e 565f544f 5f454e43 H ._ICONV_TO_ENC + 072b0 4f44494e 475f5554 465f3136 4c452000 ODING_UTF_16LE . + 072c0 55494e54 5f4c4541 53543136 5f4d4158 UINT_LEAST16_MAX + 072d0 20285f5f 55494e54 5f4c4541 53543136 (__UINT_LEAST16 + 072e0 5f4d4158 5f5f2900 5f53495a 455f545f _MAX__)._SIZE_T_ + 072f0 44454649 4e454420 00505249 64505452 DEFINED .PRIdPTR + 07300 205f5f50 52495054 52286429 00494e54 __PRIPTR(d).INT + 07310 385f4d41 5820285f 5f494e54 385f4d41 8_MAX (__INT8_MA + 07320 585f5f29 005f4943 4f4e565f 544f5f45 X__)._ICONV_TO_E + 07330 4e434f44 494e475f 5543535f 3420005f NCODING_UCS_4 ._ + 07340 5f5f696e 74385f74 5f646566 696e6564 __int8_t_defined + 07350 2031005f 5f534947 5f41544f 4d49435f 1.__SIG_ATOMIC_ + 07360 57494454 485f5f20 3332005f 5f464153 WIDTH__ 32.__FAS + 07370 54363420 226c6c22 005f5f70 6f776572 T64 "ll".__power + 07380 70635f5f 2031005f 4e6f7265 7475726e pc__ 1._Noreturn + 07390 205f5f64 65616432 005f5f75 696e7470 __dead2.__uintp + 073a0 74725f74 0055494e 545f4c45 41535438 tr_t.UINT_LEAST8 + 073b0 5f4d4158 20285f5f 55494e54 5f4c4541 _MAX (__UINT_LEA + 073c0 5354385f 4d41585f 5f29005f 5f425344 ST8_MAX__).__BSD + 073d0 5f564953 49424c45 20310050 52497536 _VISIBLE 1.PRIu6 + 073e0 34205f5f 50524936 34287529 00494e54 4 __PRI64(u).INT + 073f0 5f4c4541 5354385f 4d494e20 282d5f5f _LEAST8_MIN (-__ + 07400 494e545f 4c454153 54385f4d 41585f5f INT_LEAST8_MAX__ + 07410 202d2031 29005f49 4e545054 525f545f - 1)._INTPTR_T_ + 07420 4445434c 41524544 20005f5f 696e6869 DECLARED .__inhi + 07430 6269745f 6c6f6f70 5f746f5f 6c696263 bit_loop_to_libc + 07440 616c6c20 5f5f6174 74726962 7574655f all __attribute_ + 07450 5f202828 5f5f6f70 74696d69 7a655f5f _ ((__optimize__ + 07460 2028222d 666e6f2d 74726565 2d6c6f6f ("-fno-tree-loo + 07470 702d6469 73747269 62757465 2d706174 p-distribute-pat + 07480 7465726e 73222929 29004a53 4d4e5f48 terns"))).JSMN_H + 07490 20005f54 5f505452 44494646 20005f53 ._T_PTRDIFF ._S + 074a0 53505f53 54444c49 425f485f 20004e55 SP_STDLIB_H_ .NU + 074b0 4c4c2028 28766f69 64202a29 30290062 LL ((void *)0).b + 074c0 7a65726f 28647374 2c6c656e 29202828 zero(dst,len) (( + 074d0 5f5f7373 705f626f 73302864 73742920 __ssp_bos0(dst) + 074e0 213d2028 73697a65 5f74292d 3129203f != (size_t)-1) ? + 074f0 205f5f62 75696c74 696e5f5f 5f6d656d __builtin___mem + 07500 7365745f 63686b28 6473742c 20302c20 set_chk(dst, 0, + 07510 6c656e2c 205f5f73 73705f62 6f733028 len, __ssp_bos0( + 07520 64737429 29203a20 5f5f6d65 6d736574 dst)) : __memset + 07530 5f696368 6b286473 742c2030 2c206c65 _ichk(dst, 0, le + 07540 6e292900 5f494e54 5054525f 45515f49 n))._INTPTR_EQ_I + 07550 4e542000 5049434f 4c494243 5f544c53 NT .PICOLIBC_TLS + 07560 005f5f4f 52444552 5f424947 5f454e44 .__ORDER_BIG_END + 07570 49414e5f 5f203433 3231005f 5f676e75 IAN__ 4321.__gnu + 07580 5f6c696e 75785f5f 2031005f 49434f4e _linux__ 1._ICON + 07590 565f4652 4f4d5f45 4e434f44 494e475f V_FROM_ENCODING_ + 075a0 49534f5f 49525f31 31312000 5f5f5343 ISO_IR_111 .__SC + 075b0 414e465f 41545452 49425554 455f5f28 ANF_ATTRIBUTE__( + 075c0 5f5f732c 5f662920 5f5f464f 524d4154 __s,_f) __FORMAT + 075d0 5f415454 52494255 54455f5f 28736361 _ATTRIBUTE__(sca + 075e0 6e662c20 5f5f732c 205f5f66 29005f5f nf, __s, __f).__ + 075f0 4743435f 48415645 5f53594e 435f434f GCC_HAVE_SYNC_CO + 07600 4d504152 455f414e 445f5357 41505f32 MPARE_AND_SWAP_2 + 07610 2031005f 4d414348 494e455f 5f444546 1._MACHINE__DEF + 07620 41554c54 5f545950 45535f48 20005f5f AULT_TYPES_H .__ + 07630 55494e54 5f464153 5433325f 54595045 UINT_FAST32_TYPE + 07640 5f5f2075 6e736967 6e656420 696e7400 __ unsigned int. + 07650 5f5f5349 475f4154 4f4d4943 5f4d494e __SIG_ATOMIC_MIN + 07660 5f5f2028 2d5f5f53 49475f41 544f4d49 __ (-__SIG_ATOMI + 07670 435f4d41 585f5f20 2d203129 00484156 C_MAX__ - 1).HAV + 07680 455f4255 494c5449 4e5f4354 5a20005f E_BUILTIN_CTZ ._ + 07690 5f535444 435f4945 435f3535 395f434f _STDC_IEC_559_CO + 076a0 4d504c45 585f5f20 31005549 4e543332 MPLEX__ 1.UINT32 + 076b0 5f4d4158 20285f5f 55494e54 33325f4d _MAX (__UINT32_M + 076c0 41585f5f 29005549 4e545f4c 45415354 AX__).UINT_LEAST + 076d0 33325f4d 41582028 5f5f5549 4e545f4c 32_MAX (__UINT_L + 076e0 45415354 33325f4d 41585f5f 29005f5f EAST32_MAX__).__ + 076f0 7373705f 626f735f 63686563 6b322866 ssp_bos_check2(f + 07700 756e2c64 73742c73 72632920 28285f5f un,dst,src) ((__ + 07710 7373705f 626f7330 28647374 2920213d ssp_bos0(dst) != + 07720 20287369 7a655f74 292d3129 203f205f (size_t)-1) ? _ + 07730 5f627569 6c74696e 5f5f5f20 23232066 _builtin___ ## f + 07740 756e2023 23205f63 686b2864 73742c20 un ## _chk(dst, + 07750 7372632c 205f5f73 73705f62 6f733028 src, __ssp_bos0( + 07760 64737429 29203a20 5f5f2023 23206675 dst)) : __ ## fu + 07770 6e202323 205f6963 686b2864 73742c20 n ## _ichk(dst, + 07780 73726329 29005f5f 6e656564 5f776368 src)).__need_wch + 07790 61725f74 005f5f46 4c545f44 4543494d ar_t.__FLT_DECIM + 077a0 414c5f44 49475f5f 2039005f 49434f4e AL_DIG__ 9._ICON + 077b0 565f4652 4f4d5f45 4e434f44 494e475f V_FROM_ENCODING_ + 077c0 20004353 525f5449 4d455230 5f4c4f41 .CSR_TIMER0_LOA + 077d0 445f4144 44522028 4353525f 42415345 D_ADDR (CSR_BASE + 077e0 202b2030 78333830 304c2900 55415254 + 0x3800L).UART + 077f0 5f45565f 54582030 7831005f 49434f4e _EV_TX 0x1._ICON + 07800 565f544f 5f454e43 4f44494e 475f5554 V_TO_ENCODING_UT + 07810 465f3136 42452000 4353525f 4354524c F_16BE .CSR_CTRL + 07820 5f524553 45545f53 4f435f52 53545f53 _RESET_SOC_RST_S + 07830 495a4520 31007661 5f617267 28762c6c IZE 1.va_arg(v,l + 07840 29205f5f 6275696c 74696e5f 76615f61 ) __builtin_va_a + 07850 72672876 2c6c2900 50524969 4c454153 rg(v,l).PRIiLEAS + 07860 54363420 5f5f5052 4936344c 45415354 T64 __PRI64LEAST + 07870 28692900 5f5f6e6f 73616e69 74697a65 (i).__nosanitize + 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+ 088e0 636c7573 69766528 2e2e2e29 205f5f6c clusive(...) __l + 088f0 6f636b5f 616e6e6f 74617465 28657863 ock_annotate(exc + 08900 6c757369 76655f6c 6f636b5f 66756e63 lusive_lock_func + 08910 74696f6e 285f5f56 415f4152 47535f5f tion(__VA_ARGS__ + 08920 29290046 465f5346 4e5f4255 46203132 )).FF_SFN_BUF 12 + 08930 005f5f4c 44424c5f 4d494e5f 5f20322e .__LDBL_MIN__ 2. + 08940 30303431 36383336 30303038 39373237 0041683600089727 + 08950 37373939 36313038 30353133 35303136 7799610805135016 + 08960 652d3239 324c0049 4e545f46 41535438 e-292L.INT_FAST8 + 08970 5f4d494e 20282d5f 5f494e54 5f464153 _MIN (-__INT_FAS + 08980 54385f4d 41585f5f 202d2031 29005f5f T8_MAX__ - 1).__ + 08990 4743435f 41544f4d 49435f57 43484152 GCC_ATOMIC_WCHAR + 089a0 5f545f4c 4f434b5f 46524545 2032005f _T_LOCK_FREE 2._ + 089b0 5f494e54 5f4c4541 53543332 5f545950 _INT_LEAST32_TYP + 089c0 455f5f20 696e7400 5f5f5349 5a454f46 E__ int.__SIZEOF + 089d0 5f505452 44494646 5f545f5f 2034005f _PTRDIFF_T__ 4._ + 089e0 5f737370 5f726561 6c5f2866 756e2920 _ssp_real_(fun) + 089f0 5f5f7373 705f7265 616c5f20 23232066 __ssp_real_ ## f + 08a00 756e0044 424c5f4d 41585f45 5850205f un.DBL_MAX_EXP _ + 08a10 5f44424c 5f4d4158 5f455850 5f5f0070 _DBL_MAX_EXP__.p + 08a20 75746368 6172285f 5f632920 66707574 utchar(__c) fput + 08a30 63285f5f 632c2073 74646f75 7429005f c(__c, stdout)._ + 08a40 5f53434e 31362878 29205f5f 494e5431 _SCN16(x) __INT1 + 08a50 36205f5f 53545249 4e474946 59287829 6 __STRINGIFY(x) + 08a60 005f5f5f 696e7433 325f745f 64656669 .___int32_t_defi + 08a70 6e656420 31005f5f 50524936 34464153 ned 1.__PRI64FAS + 08a80 54287829 205f5f46 41535436 34205f5f T(x) __FAST64 __ + 08a90 53545249 4e474946 59287829 0066656f STRINGIFY(x).feo + 08aa0 66287329 20282873 292d3e66 6c616773 f(s) ((s)->flags + 08ab0 2026205f 5f53454f 46290063 68617220 & __SEOF).char + 08ac0 2b30005f 55494e54 33325f54 5f444543 +0._UINT32_T_DEC + 08ad0 4c415245 4420005f 56415f4c 4953545f LARED ._VA_LIST_ + 08ae0 545f4820 005f5f46 4c543332 585f4841 T_H .__FLT32X_HA + 08af0 535f5155 4945545f 4e414e5f 5f203100 S_QUIET_NAN__ 1. + 08b00 46535f46 41543136 2032005f 41544649 FS_FAT16 2._ATFI + 08b10 4c455f53 4f555243 45004e45 574c4942 LE_SOURCE.NEWLIB + 08b20 5f544c53 005f4943 4f4e565f 544f5f45 _TLS._ICONV_TO_E + 08b30 4e434f44 494e475f 4b4f4938 5f522000 NCODING_KOI8_R . + 08b40 5f49434f 4e565f54 4f5f454e 434f4449 _ICONV_TO_ENCODI + 08b50 4e475f42 49473520 005f5f50 54524449 NG_BIG5 .__PTRDI + 08b60 46465f54 5950455f 5f20696e 74005343 FF_TYPE__ int.SC + 08b70 4e784c45 41535431 36205f5f 53434e31 NxLEAST16 __SCN1 + 08b80 364c4541 53542878 29005f49 434f4e56 6LEAST(x)._ICONV + 08b90 5f544f5f 454e434f 44494e47 5f49534f _TO_ENCODING_ISO + 08ba0 5f383835 395f3420 005f4943 4f4e565f _8859_4 ._ICONV_ + 08bb0 46524f4d 5f454e43 4f44494e 475f5553 FROM_ENCODING_US + 08bc0 5f415343 49492000 5f5f4442 4c5f4d49 _ASCII .__DBL_MI + 08bd0 4e5f4558 505f5f20 282d3130 32312900 N_EXP__ (-1021). + 08be0 5f5f6578 706f7274 6564205f 5f617474 __exported __att + 08bf0 72696275 74655f5f 28285f5f 76697369 ribute__((__visi + 08c00 62696c69 74795f5f 28226465 6661756c bility__("defaul + 08c10 74222929 2900434f 4e464947 5f425553 t"))).CONFIG_BUS + 08c20 5f535441 4e444152 44202257 49534842 _STANDARD "WISHB + 08c30 4f4e4522 00435352 5f54494d 4552305f ONE".CSR_TIMER0_ + 08c40 55504441 54455f56 414c5545 5f414444 UPDATE_VALUE_ADD + 08c50 52202843 53525f42 41534520 2b203078 R (CSR_BASE + 0x + 08c60 33383063 4c29005f 5f4e554c 4c414249 380cL).__NULLABI + 08c70 4c495459 5f505241 474d415f 50555348 LITY_PRAGMA_PUSH + 08c80 20005f5f 46415354 31362000 494e545f .__FAST16 .INT_ + 08c90 4c454153 5436345f 4d494e20 282d5f5f LEAST64_MIN (-__ + 08ca0 494e545f 4c454153 5436345f 4d41585f INT_LEAST64_MAX_ + 08cb0 5f202d20 3129005f 46565752 4954455f _ - 1)._FVWRITE_ + 08cc0 494e5f53 54524541 4d494f00 5f637372 IN_STREAMIO._csr + 08cd0 5f77725f 62756628 612c6275 662c636e _wr_buf(a,buf,cn + 08ce0 7429207b 20696e74 20692c20 6a2c206f t) { int i, j, o + 08cf0 66667365 742c206e 73756272 6567732c ffset, nsubregs, + 08d00 206e7375 62656c65 6d733b20 75696e74 nsubelems; uint + 08d10 36345f74 20763b20 69662028 73697a65 64_t v; if (size + 08d20 6f662862 75665b30 5d29203e 3d204353 of(buf[0]) >= CS + 08d30 525f4457 5f425954 45532920 7b20666f R_DW_BYTES) { fo + 08d40 72202869 203d2030 3b206920 3c20636e r (i = 0; i < cn + 08d50 743b2069 2b2b2920 7b205f63 73725f77 t; i++) { _csr_w + 08d60 7228612c 20627566 5b695d2c 2073697a r(a, buf[i], siz + 08d70 656f6628 6275665b 305d2929 3b206120 eof(buf[0])); a + 08d80 2b3d2043 53525f4f 46465345 545f4259 += CSR_OFFSET_BY + 08d90 54455320 2a206e75 6d5f7375 62726567 TES * num_subreg + 08da0 73287369 7a656f66 28627566 5b305d29 s(sizeof(buf[0]) + 08db0 293b207d 207d2065 6c736520 7b206e73 ); } } else { ns + 08dc0 75627265 6773203d 206e756d 5f737562 ubregs = num_sub + 08dd0 72656773 2873697a 656f6628 6275665b regs(sizeof(buf[ + 08de0 305d2920 2a20636e 74293b20 6e737562 0]) * cnt); nsub + 08df0 656c656d 73203d20 4353525f 44575f42 elems = CSR_DW_B + 08e00 59544553 202f2073 697a656f 66286275 YTES / sizeof(bu + 08e10 665b305d 293b206f 66667365 74203d20 f[0]); offset = + 08e20 6e737562 72656773 2a6e7375 62656c65 nsubregs*nsubele + 08e30 6d73202d 20636e74 3b20666f 72202869 ms - cnt; for (i + 08e40 203d2030 3b206920 3c206e73 75627265 = 0; i < nsubre + 08e50 67733b20 692b2b29 207b2076 203d2030 gs; i++) { v = 0 + 08e60 3b20666f 7220286a 3d20303b 206a203c ; for (j= 0; j < + 08e70 206e7375 62656c65 6d733b20 6a2b2b29 nsubelems; j++) + 08e80 207b2069 66202828 69202a20 6e737562 { if ((i * nsub + 08e90 656c656d 73202b20 6a202d20 6f666673 elems + j - offs + 08ea0 65742920 3e3d2030 29207b20 76203c3c et) >= 0) { v << + 08eb0 3d207369 7a656f66 28627566 5b305d29 = sizeof(buf[0]) + 08ec0 202a2038 3b207620 7c3d2062 75665b69 * 8; v |= buf[i + 08ed0 202a206e 73756265 6c656d73 202b206a * nsubelems + j + 08ee0 202d206f 66667365 745d3b20 7d207d20 - offset]; } } + 08ef0 6373725f 77726974 655f7369 6d706c65 csr_write_simple + 08f00 28762c20 61293b20 61202b3d 20435352 (v, a); a += CSR + 08f10 5f4f4646 5345545f 42595445 533b207d _OFFSET_BYTES; } + 08f20 207d207d 006a736d 6e746f6b 5f740053 } }.jsmntok_t.S + 08f30 49475f41 544f4d49 435f4d41 5820285f IG_ATOMIC_MAX (_ + 08f40 5f535444 494e545f 45585028 494e545f _STDINT_EXP(INT_ + 08f50 4d415829 29005f5f 43435f53 5550504f MAX)).__CC_SUPPO + 08f60 5254535f 44594e41 4d49435f 41525241 RTS_DYNAMIC_ARRA + 08f70 595f494e 49542031 005f5f49 4e543332 Y_INIT 1.__INT32 + 08f80 5f4d4158 5f5f2030 78376666 66666666 _MAX__ 0x7ffffff + 08f90 66005f5f 4c44424c 5f4d4158 5f31305f f.__LDBL_MAX_10_ + 08fa0 4558505f 5f203330 38004646 5f4d4158 EXP__ 308.FF_MAX + 08fb0 5f535320 35313200 5f5f494d 504f5254 _SS 512.__IMPORT + 08fc0 20005f5f 41544f4d 49435f52 454c4158 .__ATOMIC_RELAX + 08fd0 45442030 0055494e 545f4641 5354385f ED 0.UINT_FAST8_ + 08fe0 4d415820 285f5f55 494e545f 46415354 MAX (__UINT_FAST + 08ff0 385f4d41 585f5f29 005f5049 434f4c49 8_MAX__)._PICOLI + 09000 42435f4d 494e4f52 5f5f2037 005f5f43 BC_MINOR__ 7.__C + 09010 435f5355 50504f52 54535f57 41524e49 C_SUPPORTS_WARNI + 09020 4e472031 005f5f49 4e543634 5f545950 NG 1.__INT64_TYP + 09030 455f5f20 6c6f6e67 206c6f6e 6720696e E__ long long in + 09040 74005f5f 72616e67 656f6628 74797065 t.__rangeof(type + 09050 2c737461 72742c65 6e642920 285f5f6f ,start,end) (__o + 09060 66667365 746f6628 74797065 2c20656e ffsetof(type, en + 09070 6429202d 205f5f6f 66667365 746f6628 d) - __offsetof( + 09080 74797065 2c207374 61727429 29004646 type, start)).FF + 09090 5f444546 494e4544 20383636 3036004c _DEFINED 86606.L + 090a0 44424c5f 45505349 4c4f4e00 5f5f5f69 DBL_EPSILON.___i + 090b0 6e745f70 74726469 66665f74 5f682000 nt_ptrdiff_t_h . + 090c0 46465f4d 494e5f47 50542030 78313030 FF_MIN_GPT 0x100 + 090d0 30303030 3030005f 49434f4e 565f544f 000000._ICONV_TO + 090e0 5f454e43 4f44494e 475f4953 4f5f3838 _ENCODING_ISO_88 + 090f0 35395f35 20004646 5f46535f 54494d45 59_5 .FF_FS_TIME + 09100 4f555420 31303030 005f4e4f 494e4c49 OUT 1000._NOINLI + 09110 4e455f53 54415449 43205f4e 4f494e4c NE_STATIC _NOINL + 09120 494e4520 73746174 6963005f 4c4f4e47 INE static._LONG + 09130 5f444f55 424c4520 6c6f6e67 20646f75 _DOUBLE long dou + 09140 626c6500 5f5f7573 6564205f 5f617474 ble.__used __att + 09150 72696275 74655f5f 28285f5f 75736564 ribute__((__used + 09160 5f5f2929 00435352 5f554152 545f5458 __)).CSR_UART_TX + 09170 46554c4c 5f53495a 45203100 5f5f4f42 FULL_SIZE 1.__OB + 09180 534f4c45 54455f4d 41544820 5f5f4f42 SOLETE_MATH __OB + 09190 534f4c45 54455f4d 4154485f 44454641 SOLETE_MATH_DEFA + 091a0 554c5400 5f5f464c 54333258 5f484153 ULT.__FLT32X_HAS + 091b0 5f44454e 4f524d5f 5f203100 53464c5f _DENORM__ 1.SFL_ + 091c0 41434b5f 554e4b4e 4f574e20 27552700 ACK_UNKNOWN 'U'. + 091d0 5f5f464c 5433325f 4841535f 51554945 __FLT32_HAS_QUIE + 091e0 545f4e41 4e5f5f20 31004353 525f4c45 T_NAN__ 1.CSR_LE + 091f0 44535f42 41534520 28435352 5f424153 DS_BASE (CSR_BAS + 09200 45202b20 30783138 30304c29 00707269 E + 0x1800L).pri + 09210 6e74665f 666c6f61 74287829 20282864 ntf_float(x) ((d + 09220 6f75626c 65292028 78292900 6373725f ouble) (x)).csr_ + 09230 72656164 5f73696d 706c6500 73666c5f read_simple.sfl_ + 09240 6672616d 6500464c 545f4d49 4e00756e frame.FLT_MIN.un + 09250 7369676e 6564202b 30004558 49545f46 signed +0.EXIT_F + 09260 41494c55 52452031 00505249 69313620 AILURE 1.PRIi16 + 09270 5f5f5052 49313628 6929005f 5f464c54 __PRI16(i).__FLT + 09280 3332585f 45505349 4c4f4e5f 5f20322e 32X_EPSILON__ 2. + 09290 32323034 34363034 39323530 33313330 2204460492503130 + 092a0 38303834 37323633 33333631 38313634 8084726333618164 + 092b0 652d3136 46333278 005f5f44 45433132 e-16F32x.__DEC12 + 092c0 385f5355 424e4f52 4d414c5f 4d494e5f 8_SUBNORMAL_MIN_ + 092d0 5f20302e 30303030 30303030 30303030 _ 0.000000000000 + 092e0 30303030 30303030 30303030 30303030 0000000000000000 + 092f0 30303030 31452d36 31343344 4c005f49 00001E-6143DL._I + 09300 434f4e56 5f544f5f 454e434f 44494e47 CONV_TO_ENCODING + 09310 5f49534f 5f383835 395f3620 00535241 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53544154 55535f52 585f5349 5a452031 STATUS_RX_SIZE 1 + 09430 00636f6d 70757465 645f6372 63005f49 .computed_crc._I + 09440 434f4e56 5f544f5f 454e434f 44494e47 CONV_TO_ENCODING + 09450 5f4b4f49 385f5255 20005f5f 53434e38 _KOI8_RU .__SCN8 + 09460 28782920 5f5f494e 5438205f 5f535452 (x) __INT8 __STR + 09470 494e4749 46592878 29005052 49584641 INGIFY(x).PRIXFA + 09480 53543634 205f5f50 52493634 46415354 ST64 __PRI64FAST + 09490 28582900 5f5f434f 4e434154 28782c79 (X).__CONCAT(x,y + 094a0 29205f5f 434f4e43 41543128 782c7929 ) __CONCAT1(x,y) + 094b0 00435352 5f54494d 4552305f 45565f50 .CSR_TIMER0_EV_P + 094c0 454e4449 4e475f53 495a4520 31005f5f ENDING_SIZE 1.__ + 094d0 44424c5f 4841535f 51554945 545f4e41 DBL_HAS_QUIET_NA + 094e0 4e5f5f20 31004353 525f4255 54544f4e N__ 1.CSR_BUTTON + 094f0 535f494e 5f53495a 45203100 5f5f5343 S_IN_SIZE 1.__SC + 09500 4e363428 7829205f 5f494e54 3634205f N64(x) __INT64 _ + 09510 5f535452 494e4749 46592878 29005f5f _STRINGIFY(x).__ + 09520 44454333 325f4d41 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5f5f7373 705f626f 735f6368 65636b33 __ssp_bos_check3 + 09950 286d656d 6370792c 20647374 2c207372 (memcpy, dst, sr + 09960 632c206c 656e2900 6a736d6e 5f706172 c, len).jsmn_par + 09970 73657200 5f5f5349 5a454f46 5f464c4f ser.__SIZEOF_FLO + 09980 41545f5f 20340046 465f4653 5f4e4f46 AT__ 4.FF_FS_NOF + 09990 53494e46 4f203000 5f5f4445 43313238 SINFO 0.__DEC128 + 099a0 5f455053 494c4f4e 5f5f2031 452d3333 _EPSILON__ 1E-33 + 099b0 444c005f 5f53495a 455f545f 5f20005f DL.__SIZE_T__ ._ + 099c0 5f53495a 455f5459 50455f5f 20756e73 _SIZE_TYPE__ uns + 099d0 69676e65 6420696e 74005549 4e544d41 igned int.UINTMA + 099e0 585f4d41 5820285f 5f55494e 544d4158 X_MAX (__UINTMAX + 099f0 5f4d4158 5f5f2900 4c44424c 5f444947 _MAX__).LDBL_DIG + 09a00 205f5f4c 44424c5f 4449475f 5f005f41 __LDBL_DIG__._A + 09a10 6c69676e 6f662878 29205f5f 616c6967 lignof(x) __alig + 09a20 6e6f6628 7829005f 5f6f6666 7365746f nof(x).__offseto + 09a30 66287479 70652c66 69656c64 29206f66 f(type,field) of + 09a40 66736574 6f662874 7970652c 20666965 fsetof(type, fie + 09a50 6c642900 5f494e54 385f545f 4445434c ld)._INT8_T_DECL + 09a60 41524544 20005f5f 55494e54 5f4c4541 ARED .__UINT_LEA + 09a70 5354385f 54595045 5f5f2075 6e736967 ST8_TYPE__ unsig + 09a80 6e656420 63686172 005f4943 4f4e565f ned char._ICONV_ + 09a90 544f5f45 4e434f44 494e475f 49534f5f TO_ENCODING_ISO_ + 09aa0 38383539 5f392000 494e545f 4c454153 8859_9 .INT_LEAS + 09ab0 5431365f 4d415820 285f5f49 4e545f4c T16_MAX (__INT_L + 09ac0 45415354 31365f4d 41585f5f 29005f5f EAST16_MAX__).__ + 09ad0 756e7265 61636861 626c6528 29205f5f unreachable() __ + 09ae0 6275696c 74696e5f 756e7265 61636861 builtin_unreacha + 09af0 626c6528 29004641 5f4f5045 4e5f4150 ble().FA_OPEN_AP + 09b00 50454e44 20307833 30005f5f 53545249 PEND 0x30.__STRI + 09b10 4e472878 29202378 005f4943 4f4e565f NG(x) #x._ICONV_ + 09b20 544f5f45 4e434f44 494e475f 20005f49 TO_ENCODING_ ._I + 09b30 4e543634 5f545f44 45434c41 52454420 NT64_T_DECLARED + 09b40 005f4943 4f4e565f 544f5f45 4e434f44 ._ICONV_TO_ENCOD + 09b50 494e475f 5554465f 31362000 5f535953 ING_UTF_16 ._SYS + 09b60 5f5f494e 54535550 5f482000 5f5f4348 __INTSUP_H .__CH + 09b70 41523136 5f545950 455f5f20 73686f72 AR16_TYPE__ shor + 09b80 7420756e 7369676e 65642069 6e740043 t unsigned int.C + 09b90 53525f43 54524c5f 52455345 545f4350 SR_CTRL_RESET_CP + 09ba0 555f5253 545f4f46 46534554 20310053 U_RST_OFFSET 1.S + 09bb0 434e7846 41535436 34205f5f 53434e36 CNxFAST64 __SCN6 + 09bc0 34464153 54287829 005f5f53 434e4d41 4FAST(x).__SCNMA + 09bd0 58287829 205f5f53 5452494e 47494659 X(x) __STRINGIFY + 09be0 286c6c20 23237829 005f554e 4255465f (ll ##x)._UNBUF_ + 09bf0 53545245 414d5f4f 5054005f 5f6d616c STREAM_OPT.__mal + 09c00 6c6f635f 6c696b65 205f5f61 74747269 loc_like __attri + 09c10 62757465 5f5f2828 5f5f6d61 6c6c6f63 bute__((__malloc + 09c20 5f5f2929 00505249 7538205f 5f505249 __)).PRIu8 __PRI + 09c30 38287529 00484156 455f414c 4941535f 8(u).HAVE_ALIAS_ + 09c40 41545452 49425554 45200053 464c5f43 ATTRIBUTE .SFL_C + 09c50 4d445f41 424f5254 20307830 30005f5f MD_ABORT 0x00.__ + 09c60 5448524f 57200057 43484152 5f4d494e THROW .WCHAR_MIN + 09c70 20285f5f 57434841 525f4d49 4e5f5f29 (__WCHAR_MIN__) + 09c80 00505249 69464153 5438205f 5f505249 .PRIiFAST8 __PRI + 09c90 38464153 54286929 006a756d 705f6164 8FAST(i).jump_ad + 09ca0 64720043 53525f55 4152545f 5458454d dr.CSR_UART_TXEM + 09cb0 5054595f 53495a45 2031005f 49434f4e PTY_SIZE 1._ICON + 09cc0 565f4652 4f4d5f45 4e434f44 494e475f V_FROM_ENCODING_ + 09cd0 57494e5f 31323534 20005f5f 5052494d WIN_1254 .__PRIM + 09ce0 41582878 29205f5f 53545249 4e474946 AX(x) __STRINGIF + 09cf0 59286c6c 20232378 29005052 49644c45 Y(ll ##x).PRIdLE + 09d00 41535436 34205f5f 50524936 344c4541 AST64 __PRI64LEA + 09d10 53542864 29005f5f 7373705f 696e6c69 ST(d).__ssp_inli + 09d20 6e652065 78746572 6e205f5f 696e6c69 ne extern __inli + 09d30 6e655f5f 205f5f61 74747269 62757465 ne__ __attribute + 09d40 5f5f2828 5f5f616c 77617973 5f696e6c __((__always_inl + 09d50 696e655f 5f2c205f 5f676e75 5f696e6c ine__, __gnu_inl + 09d60 696e655f 5f292900 626f6f74 5f68656c ine__)).boot_hel + 09d70 70657200 5f5f6d65 6d637079 5f696368 per.__memcpy_ich + 09d80 6b005f49 434f4e56 5f46524f 4d5f454e k._ICONV_FROM_EN + 09d90 434f4449 4e475f55 54465f31 36424520 CODING_UTF_16BE + 09da0 004c4442 4c5f4d41 4e545f44 4947205f .LDBL_MANT_DIG _ + 09db0 5f4c4442 4c5f4d41 4e545f44 49475f5f _LDBL_MANT_DIG__ + 09dc0 00665f74 656c6c28 66702920 28286670 .f_tell(fp) ((fp + 09dd0 292d3e66 70747229 00505249 64464153 )->fptr).PRIdFAS + 09de0 54333220 5f5f5052 49333246 41535428 T32 __PRI32FAST( + 09df0 64290054 494e595f 53544449 4f20005f d).TINY_STDIO ._ + 09e00 4d414348 494e455f 5f545950 45535f48 MACHINE__TYPES_H + 09e10 20005f5f 474e5543 5f4d494e 4f525f5f .__GNUC_MINOR__ + 09e20 2034005f 5f535444 435f5554 465f3136 4.__STDC_UTF_16 + 09e30 5f5f2031 005f5f73 73705f62 6f735f69 __ 1.__ssp_bos_i + 09e40 63686563 6b335f72 65737472 69637428 check3_restrict( + 09e50 66756e2c 74797065 312c7479 70653229 fun,type1,type2) + 09e60 205f5f73 73705f69 6e6c696e 65207479 __ssp_inline ty + 09e70 70653120 5f5f2023 23206675 6e202323 pe1 __ ## fun ## + 09e80 205f6963 686b2874 79706531 205f5f72 _ichk(type1 __r + 09e90 65737472 6963742c 20747970 6532205f estrict, type2 _ + 09ea0 5f726573 74726963 742c2073 697a655f _restrict, size_ + 09eb0 74293b20 5f5f7373 705f696e 6c696e65 t); __ssp_inline + 09ec0 20747970 6531205f 5f202323 2066756e type1 __ ## fun + 09ed0 20232320 5f696368 6b287479 70653120 ## _ichk(type1 + 09ee0 5f5f7265 73747269 63742064 73742c20 __restrict dst, + 09ef0 74797065 32205f5f 72657374 72696374 type2 __restrict + 09f00 20737263 2c207369 7a655f74 206c656e src, size_t len + 09f10 29207b20 72657475 726e205f 5f627569 ) { return __bui + 09f20 6c74696e 5f5f5f20 23232066 756e2023 ltin___ ## fun # + 09f30 23205f63 686b2864 73742c20 7372632c # _chk(dst, src, + 09f40 206c656e 2c205f5f 7373705f 626f7330 len, __ssp_bos0 + 09f50 28647374 29293b20 7d005f5f 494e544d (dst)); }.__INTM + 09f60 41585f54 5950455f 5f206c6f 6e67206c AX_TYPE__ long l + 09f70 6f6e6720 696e7400 53434e64 3332205f ong int.SCNd32 _ + 09f80 5f53434e 33322864 29005f5f 55494e54 _SCN32(d).__UINT + 09f90 5f464153 5436345f 4d41585f 5f203078 _FAST64_MAX__ 0x + 09fa0 66666666 66666666 66666666 66666666 ffffffffffffffff + 09fb0 554c4c00 5f5f4442 4c5f4d49 4e5f3130 ULL.__DBL_MIN_10 + 09fc0 5f455850 5f5f2028 2d333037 29005f46 _EXP__ (-307)._F + 09fd0 4445565f 454f4620 282d3229 005f5f47 DEV_EOF (-2).__G + 09fe0 4e55435f 5f203900 5f464c4f 41545f48 NUC__ 9._FLOAT_H + 09ff0 5f5f5f20 005f5f49 4e545f46 41535438 ___ .__INT_FAST8 + 0a000 5f574944 54485f5f 20380041 4d5f5359 _WIDTH__ 8.AM_SY + 0a010 53203078 3034005f 49434f4e 565f4652 S 0x04._ICONV_FR + 0a020 4f4d5f45 4e434f44 494e475f 57494e5f OM_ENCODING_WIN_ + 0a030 31323535 20005541 52545f50 4f4c4c49 1255 .UART_POLLI + 0a040 4e472000 48415645 5f464f52 4d41545f NG .HAVE_FORMAT_ + 0a050 41545452 49425554 45200053 434e6946 ATTRIBUTE .SCNiF + 0a060 41535431 36205f5f 53434e31 36464153 AST16 __SCN16FAS + 0a070 54286929 005f5354 44415247 5f482000 T(i)._STDARG_H . + 0a080 72656164 63686172 20676574 63686172 readchar getchar + 0a090 00435352 5f54494d 4552305f 45565f45 .CSR_TIMER0_EV_E + 0a0a0 4e41424c 455f5349 5a452031 005f5f55 NABLE_SIZE 1.__U + 0a0b0 494e545f 4c454153 54385f4d 41585f5f INT_LEAST8_MAX__ + 0a0c0 20307866 6600665f 73697a65 28667029 0xff.f_size(fp) + 0a0d0 20282866 70292d3e 6f626a2e 6f626a73 ((fp)->obj.objs + 0a0e0 697a6529 00666c61 6773005f 5f494e54 ize).flags.__INT + 0a0f0 5f4c4541 5354385f 4d41585f 5f203078 _LEAST8_MAX__ 0x + 0a100 3766005f 5f53434e 50545228 7829205f 7f.__SCNPTR(x) _ + 0a110 5f535452 494e4749 46592878 29005749 _STRINGIFY(x).WI + 0a120 4e545f4d 41582028 5f5f5749 4e545f4d NT_MAX (__WINT_M + 0a130 41585f5f 29005346 4c5f434d 445f4c4f AX__).SFL_CMD_LO + 0a140 41442030 78303100 5f5f5743 4841525f AD 0x01.__WCHAR_ + 0a150 4d41585f 5f203078 37666666 66666666 MAX__ 0x7fffffff + 0a160 4c004353 525f5541 52545f45 565f5045 L.CSR_UART_EV_PE + 0a170 4e44494e 475f5258 5f53495a 45203100 NDING_RX_SIZE 1. + 0a180 5f5f4f42 534f4c45 54455f4d 4154485f __OBSOLETE_MATH_ + 0a190 444f5542 4c45205f 5f4f4253 4f4c4554 DOUBLE __OBSOLET + 0a1a0 455f4d41 54485f44 45464155 4c545f44 E_MATH_DEFAULT_D + 0a1b0 4f55424c 45005f5f 474e5543 5f504154 OUBLE.__GNUC_PAT + 0a1c0 43484c45 56454c5f 5f203000 494e5433 CHLEVEL__ 0.INT3 + 0a1d0 325f4d41 5820285f 5f494e54 33325f4d 2_MAX (__INT32_M + 0a1e0 41585f5f 29005f66 74657874 004b4559 AX__)._ftext.KEY + 0a1f0 5f455241 53455f4c 494e4520 43544c5f _ERASE_LINE CTL_ + 0a200 43482827 78272900 2f646174 612f7072 CH('x')./data/pr + 0a210 6f6a6563 74732f6c 69746578 2f6c6974 ojects/litex/lit + 0a220 65782f73 6f632f73 6f667477 6172652f ex/soc/software/ + 0a230 62696f73 2f68656c 70657273 2e63004d bios/helpers.c.M + 0a240 41585f50 4152414d 2038004c 49544545 AX_PARAM 8.LITEE + 0a250 54485f43 4d445320 36004c49 54455344 TH_CMDS 6.LITESD + 0a260 43415244 5f434d44 53203700 4b45595f CARD_CMDS 7.KEY_ + 0a270 4c454654 2043544c 5f434828 27622729 LEFT CTL_CH('b') + 0a280 00524546 52455348 5f544f5f 454f4c28 .REFRESH_TO_EOL( + 0a290 29207b20 69662028 6e756d20 3c20656f ) { if (num < eo + 0a2a0 6c5f6e75 6d29207b 20776c65 6e203d20 l_num) { wlen = + 0a2b0 656f6c5f 6e756d20 2d206e75 6d3b2070 eol_num - num; p + 0a2c0 75746e73 74722862 7566202b 206e756d utnstr(buf + num + 0a2d0 2c20776c 656e293b 206e756d 203d2065 , wlen); num = e + 0a2e0 6f6c5f6e 756d3b20 7d207d00 4b45595f ol_num; } }.KEY_ + 0a2f0 444f574e 2043544c 5f434828 276e2729 DOWN CTL_CH('n') + 0a300 005f5f62 696f735f 696e6974 5f737461 .__bios_init_sta + 0a310 7274004e 425f4f46 5f47524f 55505320 rt.NB_OF_GROUPS + 0a320 39004352 4541445f 48495354 5f434841 9.CREAD_HIST_CHA + 0a330 52202827 21272900 53504946 4c415348 R ('!').SPIFLASH + 0a340 5f434d44 53203300 43544c5f 4241434b _CMDS 3.CTL_BACK + 0a350 53504143 45202827 5c622729 0064756d SPACE ('\b').dum + 0a360 705f6279 74657300 696e6974 5f66756e p_bytes.init_fun + 0a370 63004c49 54454452 414d5f43 4d445320 c.LITEDRAM_CMDS + 0a380 35006e62 5f706172 616d004b 45595f50 5.nb_param.KEY_P + 0a390 41474555 50203133 35004b45 595f454e AGEUP 135.KEY_EN + 0a3a0 44203133 33004245 47494e4e 494e475f D 133.BEGINNING_ + 0a3b0 4f465f4c 494e4528 29207b20 7768696c OF_LINE() { whil + 0a3c0 6520286e 756d2920 7b206765 74636d64 e (num) { getcmd + 0a3d0 5f707574 63682843 544c5f42 41434b53 _putch(CTL_BACKS + 0a3e0 50414345 293b206e 756d2d2d 3b207d20 PACE); num--; } + 0a3f0 7d004849 53545f44 45505448 20313000 }.HIST_DEPTH 10. + 0a400 64656669 6e655f69 6e69745f 66756e63 define_init_func + 0a410 28662920 636f6e73 7420696e 69745f66 (f) const init_f + 0a420 756e6320 5f5f6269 6f735f69 6e69745f unc __bios_init_ + 0a430 20232366 205f5f61 74747269 62757465 ##f __attribute + 0a440 5f5f2828 5f5f7573 65645f5f 2929205f __((__used__)) _ + 0a450 5f617474 72696275 74655f5f 28285f5f _attribute__((__ + 0a460 73656374 696f6e5f 5f28222e 62696f73 section__(".bios + 0a470 5f696e69 74222929 29203d20 66004445 _init"))) = f.DE + 0a480 4c203235 35004b45 595f5041 4745444f L 255.KEY_PAGEDO + 0a490 574e2031 33360048 4953545f 4d415820 WN 136.HIST_MAX + 0a4a0 3130005f 5f434f4d 4d414e44 5f485f5f 10.__COMMAND_H__ + 0a4b0 20006578 70656374 65645f63 72630073 .expected_crc.s + 0a4c0 7472636d 70004b45 595f5245 46524553 trcmp.KEY_REFRES + 0a4d0 485f544f 5f454f4c 2043544c 5f434828 H_TO_EOL CTL_CH( + 0a4e0 27652729 00707574 6e737472 28737472 'e').putnstr(str + 0a4f0 2c6e2920 646f207b 20707269 6e746620 ,n) do { printf + 0a500 2822252e 2a73222c 206e2c20 73747229 ("%.*s", n, str) + 0a510 3b207d20 7768696c 65202830 2900414e ; } while (0).AN + 0a520 53495f43 4c454152 5f534352 45454e20 SI_CLEAR_SCREEN + 0a530 225c655b 324a5c65 5b3b4822 005f5f62 "\e[2J\e[;H".__b + 0a540 696f735f 696e6974 5f656e64 00434d44 ios_init_end.CMD + 0a550 5f4c494e 455f4255 46464552 5f53495a _LINE_BUFFER_SIZ + 0a560 45203634 004d454d 5f434d44 53203200 E 64.MEM_CMDS 2. + 0a570 4b45595f 55502043 544c5f43 48282770 KEY_UP CTL_CH('p + 0a580 27290067 726f7570 00637263 33320053 ').group.crc32.S + 0a590 59535445 4d5f434d 44532030 00637263 YSTEM_CMDS 0.crc + 0a5a0 62696f73 00696e69 745f6469 73706174 bios.init_dispat + 0a5b0 63686572 005f5f62 696f735f 636d645f cher.__bios_cmd_ + 0a5c0 73746172 74005f65 64617461 5f726f6d start._edata_rom + 0a5d0 004b4559 5f44454c 20313337 00455343 .KEY_DEL 137.ESC + 0a5e0 20323700 4c495445 53415441 5f434d44 27.LITESATA_CMD + 0a5f0 53203800 5f5f6269 6f735f63 6d645f65 S 8.__bios_cmd_e + 0a600 6e64004b 45595f48 4f4d4520 43544c5f nd.KEY_HOME CTL_ + 0a610 43482827 61272900 50524f4d 50542022 CH('a').PROMPT " + 0a620 5c655b39 323b316d 6c697465 785c655b \e[92;1mlitex\e[ + 0a630 306d3e20 22006e62 5f706172 616d7300 0m> ".nb_params. + 0a640 45524153 455f544f 5f454f4c 2829207b ERASE_TO_EOL() { + 0a650 20696620 286e756d 203c2065 6f6c5f6e if (num < eol_n + 0a660 756d2920 7b20696e 7420743b 20666f72 um) { int t; for + 0a670 20287420 3d206e75 6d3b2074 203c2065 (t = num; t < e + 0a680 6f6c5f6e 756d3b20 742b2b29 20676574 ol_num; t++) get + 0a690 636d645f 70757463 68282720 27293b20 cmd_putch(' '); + 0a6a0 7768696c 65202874 2d2d203e 206e756d while (t-- > num + 0a6b0 29206765 74636d64 5f707574 63682843 ) getcmd_putch(C + 0a6c0 544c5f42 41434b53 50414345 293b2065 TL_BACKSPACE); e + 0a6d0 6f6c5f6e 756d203d 206e756d 3b207d20 ol_num = num; } + 0a6e0 7d004e55 4d424552 5f4f465f 42595445 }.NUMBER_OF_BYTE + 0a6f0 535f4f4e 5f415f4c 494e4520 31360061 S_ON_A_LINE 16.a + 0a700 63747561 6c5f6372 63006f66 66736574 ctual_crc.offset + 0a710 5f62696f 73004b45 595f434c 4541525f _bios.KEY_CLEAR_ + 0a720 53435245 454e2043 544c5f43 4828276c SCREEN CTL_CH('l + 0a730 27290064 6566696e 655f636f 6d6d616e ').define_comman + 0a740 6428636d 645f6e61 6d652c68 616e646c d(cmd_name,handl + 0a750 65722c68 656c705f 7478742c 67726f75 er,help_txt,grou + 0a760 705f6964 29207374 72756374 20636f6d p_id) struct com + 0a770 6d616e64 5f737472 75637420 735f2023 mand_struct s_ # + 0a780 23636d64 5f6e616d 65203d20 7b202e66 #cmd_name = { .f + 0a790 756e6320 3d202863 6d645f68 616e646c unc = (cmd_handl + 0a7a0 65722968 616e646c 65722c20 2e6e616d er)handler, .nam + 0a7b0 65203d20 23636d64 5f6e616d 652c202e e = #cmd_name, . + 0a7c0 68656c70 203d2068 656c705f 7478742c help = help_txt, + 0a7d0 202e6772 6f757020 3d206772 6f75705f .group = group_ + 0a7e0 69642c20 7d3b2063 6f6e7374 20737472 id, }; const str + 0a7f0 75637420 636f6d6d 616e645f 73747275 uct command_stru + 0a800 6374202a 5f5f6269 6f735f63 6d645f20 ct *__bios_cmd_ + 0a810 2323636d 645f6e61 6d65205f 5f617474 ##cmd_name __att + 0a820 72696275 74655f5f 28285f5f 75736564 ribute__((__used + 0a830 5f5f2929 205f5f61 74747269 62757465 __)) __attribute + 0a840 5f5f2828 5f5f7365 6374696f 6e5f5f28 __((__section__( + 0a850 222e6269 6f735f63 6d642229 2929203d ".bios_cmd"))) = + 0a860 2026735f 20232363 6d645f6e 616d6500 &s_ ##cmd_name. + 0a870 636f6d6d 616e6400 6765745f 70617261 command.get_para + 0a880 6d004d41 585f434d 44425546 5f53495a m.MAX_CMDBUF_SIZ + 0a890 45203235 3600636f 6d6d616e 645f7374 E 256.command_st + 0a8a0 72756374 005f5f48 454c5045 52535f48 ruct.__HELPERS_H + 0a8b0 5f5f2000 43544c5f 43482863 29202828 __ .CTL_CH(c) (( + 0a8c0 6329202d 20276127 202b2031 29006765 c) - 'a' + 1).ge + 0a8d0 74636d64 5f707574 63682863 68292070 tcmd_putch(ch) p + 0a8e0 75746368 61722863 68290049 32435f43 utchar(ch).I2C_C + 0a8f0 4d445320 34004b45 595f4445 4c372031 MDS 4.KEY_DEL7 1 + 0a900 3237004b 45595f49 4e534552 54204354 27.KEY_INSERT CT + 0a910 4c5f4348 28276f27 29006670 75747300 L_CH('o').fputs. + 0a920 6c696e65 5f627974 6573005f 5f524541 line_bytes.__REA + 0a930 444c494e 455f485f 5f200067 6574636d DLINE_H__ .getcm + 0a940 645f6362 65657028 29206765 74636d64 d_cbeep() getcmd + 0a950 5f707574 63682827 5c612729 004b4559 _putch('\a').KEY + 0a960 5f455241 53455f54 4f5f454f 4c204354 _ERASE_TO_EOL CT + 0a970 4c5f4348 28276b27 2900424f 4f545f43 L_CH('k').BOOT_C + 0a980 4d445320 3100636f 6d6d616e 645f6469 MDS 1.command_di + 0a990 73706174 63686572 004b4559 5f524947 spatcher.KEY_RIG + 0a9a0 48542043 544c5f43 48282766 2729005f HT CTL_CH('f')._ + 0a9b0 5f62696f 735f636d 645f6372 63005f5f _bios_cmd_crc.__ + 0a9c0 62696f73 5f636d64 5f627574 746f6e73 bios_cmd_buttons + 0a9d0 005f5f62 696f735f 636d645f 6c656473 .__bios_cmd_leds + 0a9e0 00696465 6e745f68 616e646c 65720062 .ident_handler.b + 0a9f0 75666665 72005f5f 62696f73 5f636d64 uffer.__bios_cmd + 0aa00 5f68656c 70006c65 64735f68 616e646c _help.leds_handl + 0aa10 65720073 7472746f 756c005f 5f62696f er.strtoul.__bio + 0aa20 735f636d 645f666c 7573685f 6370755f s_cmd_flush_cpu_ + 0aa30 64636163 68650068 656c705f 68616e64 dcache.help_hand + 0aa40 6c657200 6372635f 68616e64 6c657200 ler.crc_handler. + 0aa50 735f666c 7573685f 6370755f 64636163 s_flush_cpu_dcac + 0aa60 68650073 5f696465 6e740073 5f627574 he.s_ident.s_but + 0aa70 746f6e73 0073696d 5f6d6172 6b5f6675 tons.sim_mark_fu + 0aa80 6e632829 2073696d 5f6d6172 6b285f5f nc() sim_mark(__ + 0aa90 66756e63 5f5f2900 6c656473 5f6f7574 func__).leds_out + 0aaa0 5f777269 74650073 5f6c6564 73005f5f _write.s_leds.__ + 0aab0 62696f73 5f636d64 5f696465 6e740062 bios_cmd_ident.b + 0aac0 7574746f 6e735f68 616e646c 6572002f uttons_handler./ + 0aad0 64617461 2f70726f 6a656374 732f6c69 data/projects/li + 0aae0 7465782f 6c697465 782f736f 632f736f tex/litex/soc/so + 0aaf0 66747761 72652f62 696f732f 636d6473 ftware/bios/cmds + 0ab00 2f636d64 5f62696f 732e6300 735f6372 /cmd_bios.c.s_cr + 0ab10 6300735f 68656c70 00627574 746f6e73 c.s_help.buttons + 0ab20 5f696e5f 72656164 00494445 4e545f53 _in_read.IDENT_S + 0ab30 495a4500 6e6f745f 656d7074 7900636d IZE.not_empty.cm + 0ab40 645f6861 6e646c65 72005f5f 53494d5f d_handler.__SIM_ + 0ab50 44454255 475f4820 00735f6d 656d5f74 DEBUG_H .s_mem_t + 0ab60 65737400 5f5f6269 6f735f63 6d645f6d est.__bios_cmd_m + 0ab70 656d5f74 65737400 6d656d5f 636d705f em_test.mem_cmp_ + 0ab80 68616e64 6c657200 5f5f6269 6f735f63 handler.__bios_c + 0ab90 6d645f6d 656d5f63 6d70006d 656d5f77 md_mem_cmp.mem_w + 0aba0 72697465 5f68616e 646c6572 00647374 rite_handler.dst + 0abb0 61646472 006d656d 5f746573 745f6861 addr.mem_test_ha + 0abc0 6e646c65 72007472 75652031 006d656d ndler.true 1.mem + 0abd0 5f636f70 795f6861 6e646c65 72006d65 _copy_handler.me + 0abe0 6d5f6c69 73745f68 616e646c 65720073 m_list_handler.s + 0abf0 5f6d656d 5f636f70 79006d65 6d5f7265 _mem_copy.mem_re + 0ac00 61645f68 616e646c 65720073 5f6d656d ad_handler.s_mem + 0ac10 5f726561 64005f5f 62696f73 5f636d64 _read.__bios_cmd + 0ac20 5f6d656d 5f636f70 79005f5f 62696f73 _mem_copy.__bios + 0ac30 5f636d64 5f6d656d 5f726561 6400735f _cmd_mem_read.s_ + 0ac40 6d656d5f 77726974 65007265 61645f6f mem_write.read_o + 0ac50 6e6c7900 6d656d74 65737400 735f6d65 nly.memtest.s_me + 0ac60 6d5f6c69 73740066 616c7365 2030006d m_list.false 0.m + 0ac70 61787369 7a65002f 64617461 2f70726f axsize./data/pro + 0ac80 6a656374 732f6c69 7465782f 6c697465 jects/litex/lite + 0ac90 782f736f 632f736f 66747761 72652f62 x/soc/software/b + 0aca0 696f732f 636d6473 2f636d64 5f6d656d ios/cmds/cmd_mem + 0acb0 2e630073 616d6500 4d454d54 4553545f .c.same.MEMTEST_ + 0acc0 44415441 5f53495a 45202832 2a313032 DATA_SIZE (2*102 + 0acd0 342a3130 32342900 735f6d65 6d5f636d 4*1024).s_mem_cm + 0ace0 70005f5f 4d454d54 4553545f 48200073 p.__MEMTEST_H .s + 0acf0 72636164 6472006d 656d7370 65656400 rcaddr.memspeed. + 0ad00 735f6d65 6d5f7370 65656400 5f5f6269 s_mem_speed.__bi + 0ad10 6f735f63 6d645f6d 656d5f77 72697465 os_cmd_mem_write + 0ad20 005f5f62 696f735f 636d645f 6d656d5f .__bios_cmd_mem_ + 0ad30 73706565 64005f5f 62696f73 5f636d64 speed.__bios_cmd + 0ad40 5f6d656d 5f6c6973 74007261 6e646f6d _mem_list.random + 0ad50 005f5354 44424f4f 4c5f4820 005f5f62 ._STDBOOL_H .__b + 0ad60 6f6f6c5f 74727565 5f66616c 73655f61 ool_true_false_a + 0ad70 72655f64 6566696e 65642031 006d656d re_defined 1.mem + 0ad80 5f737065 65645f68 616e646c 65720061 _speed_handler.a + 0ad90 64647231 00616464 72320062 6f6f6c20 ddr1.addr2.bool + 0ada0 5f426f6f 6c005f5f 62696f73 5f636d64 _Bool.__bios_cmd + 0adb0 5f726562 6f6f7400 2f646174 612f7072 _reboot./data/pr + 0adc0 6f6a6563 74732f6c 69746578 2f6c6974 ojects/litex/lit + 0add0 65782f73 6f632f73 6f667477 6172652f ex/soc/software/ + 0ade0 62696f73 2f636d64 732f636d 645f626f bios/cmds/cmd_bo + 0adf0 6f742e63 00637472 6c5f7265 7365745f ot.c.ctrl_reset_ + 0ae00 77726974 6500735f 73657269 616c626f write.s_serialbo + 0ae10 6f740073 5f726562 6f6f7400 5f5f6269 ot.s_reboot.__bi + 0ae20 6f735f63 6d645f73 65726961 6c626f6f os_cmd_serialboo + 0ae30 74005f5f 62696f73 5f636d64 5f626f6f t.__bios_cmd_boo + 0ae40 74007265 626f6f74 5f68616e 646c6572 t.reboot_handler + 0ae50 00735f62 6f6f7400 72656164 6c696e65 .s_boot.readline + 0ae60 005f5f49 32435f48 20007364 725f6f6b .__I2C_H .sdr_ok + 0ae70 004d4449 4f5f4f45 20307830 32004d44 .MDIO_OE 0x02.MD + 0ae80 494f5f53 54415254 20307831 00535049 IO_START 0x1.SPI + 0ae90 5f464c41 53485f42 4c4f434b 5f53495a _FLASH_BLOCK_SIZ + 0aea0 45203235 36007561 72745f69 6e697400 E 256.uart_init. + 0aeb0 6d61696e 004d4449 4f5f5752 49544520 main.MDIO_WRITE + 0aec0 30783100 4c495445 585f4749 545f5348 0x1.LITEX_GIT_SH + 0aed0 41312022 33336165 33303164 22005f5f A1 "33ae301d".__ + 0aee0 4c495445 5350495f 464c4153 485f4820 LITESPI_FLASH_H + 0aef0 005f5f53 5049464c 4153485f 48200043 .__SPIFLASH_H .C + 0af00 52433332 5f455241 5345445f 464c4153 RC32_ERASED_FLAS + 0af10 48203078 46454138 41383231 005f5f4d H 0xFEA8A821.__M + 0af20 44494f5f 4820004d 44494f5f 434c4b20 DIO_H .MDIO_CLK + 0af30 30783031 004d4449 4f5f5245 41442030 0x01.MDIO_READ 0 + 0af40 7832002f 64617461 2f70726f 6a656374 x2./data/project + 0af50 732f6c69 7465782f 6c697465 782f736f s/litex/litex/so + 0af60 632f736f 66747761 72652f62 696f732f c/software/bios/ + 0af70 6d61696e 2e63004d 44494f5f 44492030 main.c.MDIO_DI 0 + 0af80 78303100 4d44494f 5f545552 4e5f4152 x01.MDIO_TURN_AR + 0af90 4f554e44 20307832 005f5f47 454e4552 OUND 0x2.__GENER + 0afa0 41544544 5f474954 5f482000 4932435f ATED_GIT_H .I2C_ + 0afb0 46524551 5f485a20 35303030 30005f5f FREQ_HZ 50000.__ + 0afc0 53445241 4d5f4820 00686973 745f696e SDRAM_H .hist_in + 0afd0 69740049 32435f41 4444525f 57522861 it.I2C_ADDR_WR(a + 0afe0 64647229 20282861 64647229 203c3c20 ddr) ((addr) << + 0aff0 3129004d 44494f5f 444f2030 78303400 1).MDIO_DO 0x04. + 0b000 4d44494f 5f505245 414d424c 45203078 MDIO_PREAMBLE 0x + 0b010 66666666 66666666 00493243 5f414444 ffffffff.I2C_ADD + 0b020 525f5244 28616464 72292028 28286164 R_RD(addr) (((ad + 0b030 64722920 3c3c2031 29207c20 31752900 dr) << 1) | 1u). + 0b040 6f757470 6f730063 68616e67 65640073 outpos.changed.s + 0b050 7472696e 675f6c69 73745f61 64640063 tring_list_add.c + 0b060 6f6d6d61 6e645f63 6f6d706c 65746500 ommand_complete. + 0b070 72657072 696e7400 6c697374 5f666972 reprint.list_fir + 0b080 73745f65 6e747279 005f5f73 74726e63 st_entry.__strnc + 0b090 70795f69 63686b00 7461625f 70726573 py_ichk.tab_pres + 0b0a0 73656400 73747269 6e675f6c 6973745f sed.string_list_ + 0b0b0 7072696e 745f6279 5f636f6c 756d6e00 print_by_column. + 0b0c0 5f5f6275 696c7469 6e5f7374 726e6370 __builtin_strncp + 0b0d0 79007374 72696e67 5f6c6973 745f656d y.string_list_em + 0b0e0 70747900 2f646174 612f7072 6f6a6563 pty./data/projec + 0b0f0 74732f6c 69746578 2f6c6974 65782f73 ts/litex/litex/s + 0b100 6f632f73 6f667477 6172652f 62696f73 oc/software/bios + 0b110 2f636f6d 706c6574 652e6300 7374726e /complete.c.strn + 0b120 636d7000 5f5f434f 4d504c45 54455f48 cmp.__COMPLETE_H + 0b130 5f5f2000 73747269 6e675f6c 6973745f __ .string_list_ + 0b140 636f756e 74006f75 74737472 00736c5f count.outstr.sl_ + 0b150 69647800 7374726c 656e0069 6e737472 idx.strlen.instr + 0b160 00737472 696e675f 6c697374 5f696e69 .string_list_ini + 0b170 74004f50 454e5f4d 41582036 3400696e t.OPEN_MAX 64.in + 0b180 73657274 00666765 74630042 435f4449 sert.fgetc.BC_DI + 0b190 4d5f4d41 58203230 34380053 43484152 M_MAX 2048.SCHAR + 0b1a0 5f4d4158 205f5f53 43484152 5f4d4158 _MAX __SCHAR_MAX + 0b1b0 5f5f0049 4e545f4d 494e005f 504f5349 __.INT_MIN._POSI + 0b1c0 58325f52 455f4455 505f4d41 58203235 X2_RE_DUP_MAX 25 + 0b1d0 35005f5f 43545950 455f5054 5220285f 5.__CTYPE_PTR (_ + 0b1e0 5f6c6f63 616c655f 63747970 655f7074 _locale_ctype_pt + 0b1f0 72202829 29005f43 20303430 004c4f4e r ())._C 040.LON + 0b200 475f4c4f 4e475f4d 494e2028 2d4c4f4e G_LONG_MIN (-LON + 0b210 475f4c4f 4e475f4d 4158202d 20314c4c G_LONG_MAX - 1LL + 0b220 29006973 6c6f7765 72285f5f 63292028 ).islower(__c) ( + 0b230 285f5f63 74797065 5f6c6f6f 6b757028 (__ctype_lookup( + 0b240 5f5f6329 26285f55 7c5f4c29 293d3d5f __c)&(_U|_L))==_ + 0b250 4c290069 73737061 6365285f 5f632920 L).isspace(__c) + 0b260 285f5f63 74797065 5f6c6f6f 6b757028 (__ctype_lookup( + 0b270 5f5f6329 265f5329 005f746f 6c6f7765 __c)&_S)._tolowe + 0b280 72285f5f 63292028 28756e73 69676e65 r(__c) ((unsigne + 0b290 64206368 61722928 5f5f6329 202d2027 d char)(__c) - ' + 0b2a0 4127202b 20276127 29006973 70756e63 A' + 'a').ispunc + 0b2b0 74285f5f 63292028 5f5f6374 7970655f t(__c) (__ctype_ + 0b2c0 6c6f6f6b 7570285f 5f632926 5f502900 lookup(__c)&_P). + 0b2d0 53485254 5f4d494e 005f5520 30310069 SHRT_MIN._U 01.i + 0b2e0 73617363 6969285f 5f632920 2828756e sascii(__c) ((un + 0b2f0 7369676e 65642928 5f5f6329 3c3d3031 signed)(__c)<=01 + 0b300 37372900 554c4c4f 4e475f4d 41582028 77).ULLONG_MAX ( + 0b310 4c4c4f4e 475f4d41 58202a20 32554c4c LLONG_MAX * 2ULL + 0b320 202b2031 554c4c29 00434849 4c445f4d + 1ULL).CHILD_M + 0b330 41582034 30006973 78646967 69745f6c AX 40.isxdigit_l + 0b340 285f5f63 2c5f5f6c 2920285f 5f637479 (__c,__l) (__cty + 0b350 70655f6c 6f6f6b75 705f6c28 5f5f632c pe_lookup_l(__c, + 0b360 5f5f6c29 26285f58 7c5f4e29 29006973 __l)&(_X|_N)).is + 0b370 616c6e75 6d285f5f 63292028 5f5f6374 alnum(__c) (__ct + 0b380 7970655f 6c6f6f6b 7570285f 5f632926 ype_lookup(__c)& + 0b390 285f557c 5f4c7c5f 4e292900 746f6173 (_U|_L|_N)).toas + 0b3a0 6369695f 6c285f5f 632c5f5f 6c292028 cii_l(__c,__l) ( + 0b3b0 285f5f6c 292c285f 5f632926 30313737 (__l),(__c)&0177 + 0b3c0 2900494e 545f4d41 58205f5f 494e545f ).INT_MAX __INT_ + 0b3d0 4d41585f 5f004c4f 4e475f4c 4f4e475f MAX__.LONG_LONG_ + 0b3e0 4d415820 5f5f4c4f 4e475f4c 4f4e475f MAX __LONG_LONG_ + 0b3f0 4d41585f 5f00554c 4f4e475f 4c4f4e47 MAX__.ULONG_LONG + 0b400 5f4d4158 20284c4f 4e475f4c 4f4e475f _MAX (LONG_LONG_ + 0b410 4d415820 2a203255 4c4c202b 2031554c MAX * 2ULL + 1UL + 0b420 4c29005f 746f7570 70657228 5f5f6329 L)._toupper(__c) + 0b430 20282875 6e736967 6e656420 63686172 ((unsigned char + 0b440 29285f5f 6329202d 20276127 202b2027 )(__c) - 'a' + ' + 0b450 41272900 69737570 7065725f 6c285f5f A').isupper_l(__ + 0b460 632c5f5f 6c292028 285f5f63 74797065 c,__l) ((__ctype + 0b470 5f6c6f6f 6b75705f 6c285f5f 632c5f5f _lookup_l(__c,__ + 0b480 6c292628 5f557c5f 4c29293d 3d5f5529 l)&(_U|_L))==_U) + 0b490 00657363 636d6473 004c4f4e 475f4d41 .esccmds.LONG_MA + 0b4a0 58205f5f 4c4f4e47 5f4d4158 5f5f0053 X __LONG_MAX__.S + 0b4b0 4852545f 4d415820 5f5f5348 52545f4d HRT_MAX __SHRT_M + 0b4c0 41585f5f 005f5f62 75696c74 696e5f6d AX__.__builtin_m + 0b4d0 656d6d6f 7665004c 4f4e475f 4c4f4e47 emmove.LONG_LONG + 0b4e0 5f4d494e 004d4158 5f494e50 55542032 _MIN.MAX_INPUT 2 + 0b4f0 35350053 43484152 5f4d494e 20282d53 55.SCHAR_MIN (-S + 0b500 43484152 5f4d4158 202d2031 29004e47 CHAR_MAX - 1).NG + 0b510 524f5550 535f4d41 58203136 00686c69 ROUPS_MAX 16.hli + 0b520 6e65005f 5f737472 6370795f 6963686b ne.__strcpy_ichk + 0b530 005f5020 30323000 554c4f4e 475f4c4f ._P 020.ULONG_LO + 0b540 4e475f4d 4158005f 4e203034 00686973 NG_MAX._N 04.his + 0b550 745f6164 645f6964 78005f58 20303130 t_add_idx._X 010 + 0b560 30006869 73745f6c 696e6573 004c4f4e 0.hist_lines.LON + 0b570 475f4d49 4e20282d 4c4f4e47 5f4d4158 G_MIN (-LONG_MAX + 0b580 202d2031 4c29005f 5359535f 5359534c - 1L)._SYS_SYSL + 0b590 494d4954 535f485f 2000434f 4c4c5f57 IMITS_H_ .COLL_W + 0b5a0 45494748 54535f4d 41582030 00534348 EIGHTS_MAX 0.SCH + 0b5b0 41525f4d 4158005f 4c494243 5f4c494d AR_MAX._LIBC_LIM + 0b5c0 4954535f 485f2031 00746f61 73636969 ITS_H_ 1.toascii + 0b5d0 285f5f63 29202828 5f5f6329 26303137 (__c) ((__c)&017 + 0b5e0 37290074 6f757070 6572285f 5f632920 7).toupper(__c) + 0b5f0 5f5f6578 74656e73 696f6e5f 5f20287b __extension__ ({ + 0b600 205f5f74 7970656f 665f5f20 285f5f63 __typeof__ (__c + 0b610 29205f5f 78203d20 285f5f63 293b2069 ) __x = (__c); i + 0b620 736c6f77 65722028 5f5f7829 203f2028 slower (__x) ? ( + 0b630 696e7429 205f5f78 202d2027 6127202b int) __x - 'a' + + 0b640 20274127 203a2028 696e7429 205f5f78 'A' : (int) __x + 0b650 3b7d2900 6973626c 616e6b5f 6c285f5f ;}).isblank_l(__ + 0b660 632c5f5f 6c29205f 5f657874 656e7369 c,__l) __extensi + 0b670 6f6e5f5f 20287b20 5f5f7479 70656f66 on__ ({ __typeof + 0b680 5f5f2028 5f5f6329 205f5f78 203d2028 __ (__c) __x = ( + 0b690 5f5f6329 3b20285f 5f637479 70655f6c __c); (__ctype_l + 0b6a0 6f6f6b75 705f6c28 5f5f782c 5f5f6c29 ookup_l(__x,__l) + 0b6b0 265f4229 207c7c20 28696e74 2920285f &_B) || (int) (_ + 0b6c0 5f782920 3d3d2027 5c74273b 7d29006f _x) == '\t';}).o + 0b6d0 6c645f63 75720065 73635f63 6d647300 ld_cur.esc_cmds. + 0b6e0 4c4c4f4e 475f4d49 4e005f43 54595045 LLONG_MIN._CTYPE + 0b6f0 5f485f20 00434841 525f4249 54005f5f _H_ .CHAR_BIT.__ + 0b700 6c6f6361 6c655f63 74797065 5f707472 locale_ctype_ptr + 0b710 2829205f 63747970 655f0049 4f565f4d () _ctype_.IOV_M + 0b720 41582031 30323400 42435f53 43414c45 AX 1024.BC_SCALE + 0b730 5f4d4158 20393900 55494e54 5f4d4158 _MAX 99.UINT_MAX + 0b740 2028494e 545f4d41 58202a20 3255202b (INT_MAX * 2U + + 0b750 20315529 00697370 756e6374 5f6c285f 1U).ispunct_l(_ + 0b760 5f632c5f 5f6c2920 285f5f63 74797065 _c,__l) (__ctype + 0b770 5f6c6f6f 6b75705f 6c285f5f 632c5f5f _lookup_l(__c,__ + 0b780 6c29265f 50290069 63686172 00554c4c l)&_P).ichar.ULL + 0b790 4f4e475f 4d415800 5f422030 32303000 ONG_MAX._B 0200. + 0b7a0 55534852 545f4d41 58006973 616c7068 USHRT_MAX.isalph + 0b7b0 61285f5f 63292028 5f5f6374 7970655f a(__c) (__ctype_ + 0b7c0 6c6f6f6b 7570285f 5f632926 285f557c lookup(__c)&(_U| + 0b7d0 5f4c2929 00415247 5f4d4158 20363535 _L)).ARG_MAX 655 + 0b7e0 33360068 6973745f 63757200 4c4c4f4e 36.hist_cur.LLON + 0b7f0 475f4d41 58205f5f 4c4f4e47 5f4c4f4e G_MAX __LONG_LON + 0b800 475f4d41 585f5f00 636f6d70 6c657465 G_MAX__.complete + 0b810 73747200 69737570 70657228 5f5f6329 str.isupper(__c) + 0b820 2028285f 5f637479 70655f6c 6f6f6b75 ((__ctype_looku + 0b830 70285f5f 63292628 5f557c5f 4c29293d p(__c)&(_U|_L))= + 0b840 3d5f5529 00697367 72617068 5f6c285f =_U).isgraph_l(_ + 0b850 5f632c5f 5f6c2920 285f5f63 74797065 _c,__l) (__ctype + 0b860 5f6c6f6f 6b75705f 6c285f5f 632c5f5f _lookup_l(__c,__ + 0b870 6c292628 5f507c5f 557c5f4c 7c5f4e29 l)&(_P|_U|_L|_N) + 0b880 29007265 61645f6b 65790042 435f5354 ).read_key.BC_ST + 0b890 52494e47 5f4d4158 20313030 30004c4c RING_MAX 1000.LL + 0b8a0 4f4e475f 4d494e20 282d4c4c 4f4e475f ONG_MIN (-LLONG_ + 0b8b0 4d415820 2d20314c 4c290069 73707269 MAX - 1LL).ispri + 0b8c0 6e745f6c 285f5f63 2c5f5f6c 2920285f nt_l(__c,__l) (_ + 0b8d0 5f637479 70655f6c 6f6f6b75 705f6c28 _ctype_lookup_l( + 0b8e0 5f5f632c 5f5f6c29 26285f50 7c5f557c __c,__l)&(_P|_U| + 0b8f0 5f4c7c5f 4e7c5f42 2929004c 494e4b5f _L|_N|_B)).LINK_ + 0b900 4d415820 33323736 37005553 4852545f MAX 32767.USHRT_ + 0b910 4d415820 28534852 545f4d41 58202a20 MAX (SHRT_MAX * + 0b920 32202b20 31290069 73616c6e 756d5f6c 2 + 1).isalnum_l + 0b930 285f5f63 2c5f5f6c 2920285f 5f637479 (__c,__l) (__cty + 0b940 70655f6c 6f6f6b75 705f6c28 5f5f632c pe_lookup_l(__c, + 0b950 5f5f6c29 26285f55 7c5f4c7c 5f4e2929 __l)&(_U|_L|_N)) + 0b960 00455850 525f4e45 53545f4d 41582033 .EXPR_NEST_MAX 3 + 0b970 32006973 64696769 74285f5f 63292028 2.isdigit(__c) ( + 0b980 5f5f6374 7970655f 6c6f6f6b 7570285f __ctype_lookup(_ + 0b990 5f632926 5f4e2900 53485254 5f4d494e _c)&_N).SHRT_MIN + 0b9a0 20282d53 4852545f 4d415820 2d203129 (-SHRT_MAX - 1) + 0b9b0 00776c65 6e005343 4841525f 4d494e00 .wlen.SCHAR_MIN. + 0b9c0 554c4f4e 475f4d41 5820284c 4f4e475f ULONG_MAX (LONG_ + 0b9d0 4d415820 2a203255 4c202b20 31554c29 MAX * 2UL + 1UL) + 0b9e0 004d425f 4c454e5f 4d415820 5f4d425f .MB_LEN_MAX _MB_ + 0b9f0 4c454e5f 4d415800 69737072 696e7428 LEN_MAX.isprint( + 0ba00 5f5f6329 20285f5f 63747970 655f6c6f __c) (__ctype_lo + 0ba10 6f6b7570 285f5f63 2926285f 507c5f55 okup(__c)&(_P|_U + 0ba20 7c5f4c7c 5f4e7c5f 42292900 6973636e |_L|_N|_B)).iscn + 0ba30 74726c5f 6c285f5f 632c5f5f 6c292028 trl_l(__c,__l) ( + 0ba40 5f5f6374 7970655f 6c6f6f6b 75705f6c __ctype_lookup_l + 0ba50 285f5f63 2c5f5f6c 29265f43 29005f5f (__c,__l)&_C).__ + 0ba60 63747970 655f6c6f 6f6b7570 00697364 ctype_lookup.isd + 0ba70 69676974 5f6c285f 5f632c5f 5f6c2920 igit_l(__c,__l) + 0ba80 285f5f63 74797065 5f6c6f6f 6b75705f (__ctype_lookup_ + 0ba90 6c285f5f 632c5f5f 6c29265f 4e29004d l(__c,__l)&_N).M + 0baa0 41585f43 414e4f4e 20323535 0055494e AX_CANON 255.UIN + 0bab0 545f4d41 58006372 6561645f 6164645f T_MAX.cread_add_ + 0bac0 63686172 0069736c 6f776572 5f6c285f char.islower_l(_ + 0bad0 5f632c5f 5f6c2920 28285f5f 63747970 _c,__l) ((__ctyp + 0bae0 655f6c6f 6f6b7570 5f6c285f 5f632c5f e_lookup_l(__c,_ + 0baf0 5f6c2926 285f557c 5f4c2929 3d3d5f4c _l)&(_U|_L))==_L + 0bb00 2900656f 6c5f6e75 6d005f4c 494d4954 ).eol_num._LIMIT + 0bb10 535f485f 5f5f2000 68697374 5f6e756d S_H___ .hist_num + 0bb20 00504154 485f4d41 58203130 32340050 .PATH_MAX 1024.P + 0bb30 4950455f 42554620 35313200 4c494e45 IPE_BUF 512.LINE + 0bb40 5f4d4158 20323034 3800554c 4f4e475f _MAX 2048.ULONG_ + 0bb50 4d415800 66707574 63004348 41525f42 MAX.fputc.CHAR_B + 0bb60 4954205f 5f434841 525f4249 545f5f00 IT __CHAR_BIT__. + 0bb70 746f6c6f 77657228 5f5f6329 205f5f65 tolower(__c) __e + 0bb80 7874656e 73696f6e 5f5f2028 7b205f5f xtension__ ({ __ + 0bb90 74797065 6f665f5f 20285f5f 6329205f typeof__ (__c) _ + 0bba0 5f78203d 20285f5f 63293b20 69737570 _x = (__c); isup + 0bbb0 70657220 285f5f78 29203f20 28696e74 per (__x) ? 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6f617420 2d67202d msoft-float -g - + 0bfe0 6733202d 4f73202d 4f73202d 7374643d g3 -Os -Os -std= + 0bff0 63313720 2d666675 6e637469 6f6e2d73 c17 -ffunction-s + 0c000 65637469 6f6e7320 2d666f6d 69742d66 ections -fomit-f + 0c010 72616d65 2d706f69 6e746572 202d666e rame-pointer -fn + 0c020 6f2d6275 696c7469 6e202d66 65786365 o-builtin -fexce + 0c030 7074696f 6e73202d 666e6f2d 73746163 ptions -fno-stac + 0c040 6b2d7072 6f746563 746f7220 2d666e6f k-protector -fno + 0c050 2d636f6d 6d6f6e20 2d66726f 756e6469 -common -froundi + 0c060 6e672d6d 61746800 5f435f63 74797065 ng-math._C_ctype + 0c070 5f6c6f63 616c6500 464c545f 4841535f _locale.FLT_HAS_ + 0c080 5355424e 4f524d20 5f5f464c 545f4841 SUBNORM __FLT_HA + 0c090 535f4445 4e4f524d 5f5f0044 424c5f54 S_DENORM__.DBL_T + 0c0a0 5255455f 4d494e20 5f5f4442 4c5f4445 RUE_MIN __DBL_DE + 0c0b0 4e4f524d 5f4d494e 5f5f004c 435f5449 NORM_MIN__.LC_TI + 0c0c0 4d452035 006c635f 63747970 655f5400 ME 5.lc_ctype_T. + 0c0d0 4c44424c 5f545255 455f4d49 4e205f5f LDBL_TRUE_MIN __ + 0c0e0 4c44424c 5f44454e 4f524d5f 4d494e5f LDBL_DENORM_MIN_ + 0c0f0 5f006c63 5f6e756d 65726963 5f540069 _.lc_numeric_T.i + 0c100 6e745f66 7261635f 64696769 7473004c nt_frac_digits.L + 0c110 435f434f 4c4c4154 45203100 585f666d C_COLLATE 1.X_fm + 0c120 74004c43 5f4e554d 45524943 5f4d4153 t.LC_NUMERIC_MAS + 0c130 4b202831 203c3c20 4c435f4e 554d4552 K (1 << LC_NUMER + 0c140 49432900 706f7369 74697665 5f736967 IC).positive_sig + 0c150 6e005f5f 77636800 63747970 655f636f n.__wch.ctype_co + 0c160 64657365 74006d6f 6e5f6465 63696d61 deset.mon_decima + 0c170 6c5f706f 696e7400 5f5f6765 745f676c l_point.__get_gl + 0c180 6f62616c 5f6c6f63 616c6528 29202826 obal_locale() (& + 0c190 5f5f676c 6f62616c 5f6c6f63 616c6529 __global_locale) + 0c1a0 005f4354 5950455f 44415441 5f313238 ._CTYPE_DATA_128 + 0c1b0 5f323535 20302c20 302c2030 2c20302c _255 0, 0, 0, 0, + 0c1c0 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c1d0 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c1e0 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c1f0 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c200 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c210 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c220 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c230 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c240 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c250 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c260 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c270 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c280 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c290 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c2a0 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c2b0 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c2c0 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c2d0 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c2e0 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c2f0 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c300 2c20302c 20302c20 302c2030 2c20302c , 0, 0, 0, 0, 0, + 0c310 20302c20 302c2030 2c20302c 20302c20 0, 0, 0, 0, 0, + 0c320 302c2030 2c20302c 20302c20 302c2030 0, 0, 0, 0, 0, 0 + 0c330 2c203000 696e745f 6e5f6373 5f707265 , 0.int_n_cs_pre + 0c340 63656465 73004e45 574c4942 5f544852 cedes.NEWLIB_THR + 0c350 4541445f 4c4f4341 4c5f4c4f 43414c45 EAD_LOCAL_LOCALE + 0c360 2000616c 745f6d6f 6e746800 6c635f6d .alt_month.lc_m + 0c370 65737361 6765735f 5400464f 524d4154 essages_T.FORMAT + 0c380 5f444546 41554c54 5f494e54 45474552 _DEFAULT_INTEGER + 0c390 20310070 75747763 68617228 77632920 1.putwchar(wc) + 0c3a0 66707574 77632828 7763292c 20737464 fputwc((wc), std + 0c3b0 6f757429 005f5f76 616c7565 00616d70 out).__value.amp + 0c3c0 6d5f666d 74005f5f 53544443 5f564552 m_fmt.__STDC_VER + 0c3d0 53494f4e 5f5f2032 30313731 304c006c SION__ 201710L.l + 0c3e0 635f6d6f 6e657461 72795f54 005f435f c_monetary_T._C_ + 0c3f0 6e756d65 7269635f 6c6f6361 6c650061 numeric_locale.a + 0c400 6c745f64 69676974 73005f5f 504f5349 lt_digits.__POSI + 0c410 585f5649 5349424c 45203000 5f5f5354 X_VISIBLE 0.__ST + 0c420 52494354 5f414e53 495f5f20 31006d64 RICT_ANSI__ 1.md + 0c430 5f6f7264 65720063 74797065 5f707472 _order.ctype_ptr + 0c440 004c435f 4d455353 41474553 5f4d4153 .LC_MESSAGES_MAS + 0c450 4b202831 203c3c20 4c435f4d 45535341 K (1 << LC_MESSA + 0c460 47455329 004c4442 4c5f4841 535f5355 GES).LDBL_HAS_SU + 0c470 424e4f52 4d005f5f 67656e65 72696328 BNORM.__generic( + 0c480 65787072 2c742c79 65732c6e 6f29205f expr,t,yes,no) _ + 0c490 47656e65 72696328 65787072 2c20743a Generic(expr, t: + 0c4a0 20796573 2c206465 6661756c 743a206e yes, default: n + 0c4b0 6f29004c 435f414c 4c203000 7765656b o).LC_ALL 0.week + 0c4c0 64617900 6d6f6e5f 74686f75 73616e64 day.mon_thousand + 0c4d0 735f7365 70004c44 424c5f48 41535f53 s_sep.LDBL_HAS_S + 0c4e0 55424e4f 524d205f 5f4c4442 4c5f4841 UBNORM __LDBL_HA + 0c4f0 535f4445 4e4f524d 5f5f0046 4c545f44 S_DENORM__.FLT_D + 0c500 4543494d 414c5f44 49470069 6e745f70 ECIMAL_DIG.int_p + 0c510 5f63735f 70726563 65646573 00464c54 _cs_precedes.FLT + 0c520 5f545255 455f4d49 4e205f5f 464c545f _TRUE_MIN __FLT_ + 0c530 44454e4f 524d5f4d 494e5f5f 005f5f67 DENORM_MIN__.__g + 0c540 6c6f6261 6c5f6c6f 63616c65 005f5f4d lobal_locale.__M + 0c550 4953435f 56495349 424c4520 30005f4c ISC_VISIBLE 0._L + 0c560 4f43414c 455f485f 20005f4c 435f4c41 OCALE_H_ ._LC_LA + 0c570 53542037 00636a6b 5f6c616e 67006572 ST 7.cjk_lang.er + 0c580 615f645f 745f666d 74004c43 5f4d4f4e a_d_t_fmt.LC_MON + 0c590 45544152 595f4d41 534b2028 31203c3c ETARY_MASK (1 << + 0c5a0 204c435f 4d4f4e45 54415259 29006572 LC_MONETARY).er + 0c5b0 615f645f 666d7400 6e656761 74697665 a_d_fmt.negative + 0c5c0 5f736967 6e004c43 5f414c4c 5f4d4153 _sign.LC_ALL_MAS + 0c5d0 4b202831 203c3c20 4c435f41 4c4c2900 K (1 << LC_ALL). + 0c5e0 5f5f6765 745f6375 7272656e 745f6c6f __get_current_lo + 0c5f0 63616c65 2829205f 6c6f6361 6c650045 cale() _locale.E + 0c600 4e434f44 494e475f 4c454e20 3331004c NCODING_LEN 31.L + 0c610 435f4d45 53534147 45532036 004c4442 C_MESSAGES 6.LDB + 0c620 4c5f4445 43494d41 4c5f4449 47005f46 L_DECIMAL_DIG._F + 0c630 494c455f 4f464653 45545f42 49545320 ILE_OFFSET_BITS + 0c640 36340046 4c545f54 5255455f 4d494e00 64.FLT_TRUE_MIN. + 0c650 6d657373 6167655f 636f6465 73657400 message_codeset. + 0c660 696e745f 6e5f7365 705f6279 5f737061 int_n_sep_by_spa + 0c670 63650061 6d5f706d 00785f66 6d74005f ce.am_pm.x_fmt._ + 0c680 435f6d6f 6e657461 72795f6c 6f63616c C_monetary_local + 0c690 65006c63 5f74696d 655f5400 5f4d4253 e.lc_time_T._MBS + 0c6a0 54415445 5f542000 5f5f4253 445f5649 TATE_T .__BSD_VI + 0c6b0 5349424c 45203000 4c435f43 54595045 SIBLE 0.LC_CTYPE + 0c6c0 20320064 6174655f 666d7400 6e6f6578 2.date_fmt.noex + 0c6d0 70720063 5f666d74 004c4442 4c5f4445 pr.c_fmt.LDBL_DE + 0c6e0 43494d41 4c5f4449 47205f5f 4c44424c CIMAL_DIG __LDBL + 0c6f0 5f444543 494d414c 5f444947 5f5f005f _DECIMAL_DIG__._ + 0c700 5345544c 4f43414c 455f485f 20005f5f SETLOCALE_H_ .__ + 0c710 41544649 4c455f56 49534942 4c452030 ATFILE_VISIBLE 0 + 0c720 005f5f63 6f756e74 005f5f49 534f5f43 .__count.__ISO_C + 0c730 5f564953 49424c45 20323031 31005f57 _VISIBLE 2011._W + 0c740 43484152 5f485f20 006e6f73 7472005f CHAR_H_ .nostr._ + 0c750 5f776368 62004442 4c5f4841 535f5355 _wchb.DBL_HAS_SU + 0c760 424e4f52 4d205f5f 44424c5f 4841535f BNORM __DBL_HAS_ + 0c770 44454e4f 524d5f5f 00696e74 5f705f73 DENORM__.int_p_s + 0c780 65705f62 795f7370 61636500 4c435f4d ep_by_space.LC_M + 0c790 4f4e4554 41525920 33007965 73657870 ONETARY 3.yesexp + 0c7a0 72004c43 5f474c4f 42414c5f 4c4f4341 r.LC_GLOBAL_LOCA + 0c7b0 4c452028 28737472 75637420 5f5f6c6f LE ((struct __lo + 0c7c0 63616c65 5f74202a 29202d31 29005f6d cale_t *) -1)._m + 0c7d0 62737461 74655f74 005f4743 435f4d41 bstate_t._GCC_MA + 0c7e0 585f414c 49474e5f 5420005f 435f6d65 X_ALIGN_T ._C_me + 0c7f0 73736167 65735f6c 6f63616c 65006375 ssages_locale.cu + 0c800 7272656e 63795f73 796d626f 6c006d6f rrency_symbol.mo + 0c810 6e5f6772 6f757069 6e670067 65747763 n_grouping.getwc + 0c820 28667029 20666765 74776328 66702900 (fp) fgetwc(fp). + 0c830 464c545f 4841535f 5355424e 4f524d00 FLT_HAS_SUBNORM. + 0c840 5f5f5353 505f464f 52544946 595f4c45 __SSP_FORTIFY_LE + 0c850 56454c20 3000696e 745f705f 7369676e VEL 0.int_p_sign + 0c860 5f706f73 6e004442 4c5f4445 43494d41 _posn.DBL_DECIMA + 0c870 4c5f4449 47205f5f 44424c5f 44454349 L_DIG __DBL_DECI + 0c880 4d414c5f 4449475f 5f006c63 6f6e7600 MAL_DIG__.lconv. + 0c890 77646179 00464c54 5f444543 494d414c wday.FLT_DECIMAL + 0c8a0 5f444947 205f5f46 4c545f44 4543494d _DIG __FLT_DECIM + 0c8b0 414c5f44 49475f5f 00696e74 5f6e5f73 AL_DIG__.int_n_s + 0c8c0 69676e5f 706f736e 00707574 77632877 ign_posn.putwc(w + 0c8d0 632c6670 29206670 75747763 28287763 c,fp) fputwc((wc + 0c8e0 292c2028 66702929 00696e74 5f637572 ), (fp)).int_cur + 0c8f0 725f7379 6d626f6c 004c4442 4c5f5452 r_symbol.LDBL_TR + 0c900 55455f4d 494e0065 72615f74 5f666d74 UE_MIN.era_t_fmt + 0c910 004c435f 4e554d45 52494320 34005f43 .LC_NUMERIC 4._C + 0c920 54595045 5f444154 415f305f 31323720 TYPE_DATA_0_127 + 0c930 5f432c20 5f432c20 5f432c20 5f432c20 _C, _C, _C, _C, + 0c940 5f432c20 5f432c20 5f432c20 5f432c20 _C, _C, _C, _C, + 0c950 5f432c20 5f437c5f 532c205f 437c5f53 _C, _C|_S, _C|_S + 0c960 2c205f43 7c5f532c 205f437c 5f532c20 , _C|_S, _C|_S, + 0c970 5f437c5f 532c205f 432c205f 432c205f _C|_S, _C, _C, _ + 0c980 432c205f 432c205f 432c205f 432c205f C, _C, _C, _C, _ + 0c990 432c205f 432c205f 432c205f 432c205f C, _C, _C, _C, _ + 0c9a0 432c205f 432c205f 432c205f 432c205f C, _C, _C, _C, _ + 0c9b0 432c205f 432c205f 432c205f 432c205f C, _C, _C, _C, _ + 0c9c0 537c5f42 2c205f50 2c205f50 2c205f50 S|_B, _P, _P, _P + 0c9d0 2c205f50 2c205f50 2c205f50 2c205f50 , _P, _P, _P, _P + 0c9e0 2c205f50 2c205f50 2c205f50 2c205f50 , _P, _P, _P, _P + 0c9f0 2c205f50 2c205f50 2c205f50 2c205f50 , _P, _P, _P, _P + 0ca00 2c205f4e 2c205f4e 2c205f4e 2c205f4e , _N, _N, _N, _N + 0ca10 2c205f4e 2c205f4e 2c205f4e 2c205f4e , _N, _N, _N, _N + 0ca20 2c205f4e 2c205f4e 2c205f50 2c205f50 , _N, _N, _P, _P + 0ca30 2c205f50 2c205f50 2c205f50 2c205f50 , _P, _P, _P, _P + 0ca40 2c205f50 2c205f55 7c5f582c 205f557c , _P, _U|_X, _U| + 0ca50 5f582c20 5f557c5f 582c205f 557c5f58 _X, _U|_X, _U|_X + 0ca60 2c205f55 7c5f582c 205f557c 5f582c20 , _U|_X, _U|_X, + 0ca70 5f552c20 5f552c20 5f552c20 5f552c20 _U, _U, _U, _U, + 0ca80 5f552c20 5f552c20 5f552c20 5f552c20 _U, _U, _U, _U, + 0ca90 5f552c20 5f552c20 5f552c20 5f552c20 _U, _U, _U, _U, + 0caa0 5f552c20 5f552c20 5f552c20 5f552c20 _U, _U, _U, _U, + 0cab0 5f552c20 5f552c20 5f552c20 5f552c20 _U, _U, _U, _U, + 0cac0 5f502c20 5f502c20 5f502c20 5f502c20 _P, _P, _P, _P, + 0cad0 5f502c20 5f502c20 5f4c7c5f 582c205f _P, _P, _L|_X, _ + 0cae0 4c7c5f58 2c205f4c 7c5f582c 205f4c7c L|_X, _L|_X, _L| + 0caf0 5f582c20 5f4c7c5f 582c205f 4c7c5f58 _X, _L|_X, _L|_X + 0cb00 2c205f4c 2c205f4c 2c205f4c 2c205f4c , _L, _L, _L, _L + 0cb10 2c205f4c 2c205f4c 2c205f4c 2c205f4c , _L, _L, _L, _L + 0cb20 2c205f4c 2c205f4c 2c205f4c 2c205f4c , _L, _L, _L, _L + 0cb30 2c205f4c 2c205f4c 2c205f4c 2c205f4c , _L, _L, _L, _L + 0cb40 2c205f4c 2c205f4c 2c205f4c 2c205f4c , _L, _L, _L, _L + 0cb50 2c205f50 2c205f50 2c205f50 2c205f50 , _P, _P, _P, _P + 0cb60 2c205f43 005f435f 74696d65 5f6c6f63 , _C._C_time_loc + 0cb70 616c6500 2f646174 612f7072 6f6a6563 ale./data/projec + 0cb80 74732f61 32702f62 75696c64 2f6c6974 ts/a2p/build/lit + 0cb90 65782f66 756c6c2d 6c697465 782f6275 ex/full-litex/bu + 0cba0 696c642f 636d6f64 372f736f 66747761 ild/cmod7/softwa + 0cbb0 72652f6c 69626300 79657373 7472005f re/libc.yesstr._ + 0cbc0 434f4d50 494c494e 475f4e45 574c4942 COMPILING_NEWLIB + 0cbd0 20310063 61746567 6f726965 73004341 1.categories.CA + 0cbe0 5445474f 52595f4c 454e2031 31004c43 TEGORY_LEN 11.LC + 0cbf0 5f435459 50455f4d 41534b20 2831203c _CTYPE_MASK (1 < + 0cc00 3c204c43 5f435459 50452900 4550464e < LC_CTYPE).EPFN + 0cc10 4f535550 504f5254 20393600 454e4f42 OSUPPORT 96.ENOB + 0cc20 55465320 31303500 45535243 48203300 UFS 105.ESRCH 3. + 0cc30 454d4649 4c452032 34006572 726e6f00 EMFILE 24.errno. + 0cc40 454e4f50 524f544f 4f505420 31303900 ENOPROTOOPT 109. + 0cc50 45494452 4d203336 00657272 6e6f2829 EIDRM 36.errno() + 0cc60 20286572 726e6f29 00454445 53544144 (errno).EDESTAD + 0cc70 44525245 51203132 31004554 4f4f4d41 DRREQ 121.ETOOMA + 0cc80 4e595245 46532031 32390045 4e4f4d45 NYREFS 129.ENOME + 0cc90 4d203132 00455449 4d45444f 55542031 M 12.ETIMEDOUT 1 + 0cca0 31360045 524f4653 20333000 454e4f53 16.EROFS 30.ENOS + 0ccb0 54522036 30005f5f 454c4153 54455252 TR 60.__ELASTERR + 0ccc0 4f522032 30303000 45444f4d 20333300 OR 2000.EDOM 33. + 0ccd0 454e4f54 54592032 35004558 44455620 ENOTTY 25.EXDEV + 0cce0 31380045 32424947 20370045 4e4f5452 18.E2BIG 7.ENOTR + 0ccf0 45434f56 45524142 4c452031 34310045 ECOVERABLE 141.E + 0cd00 4348494c 44203130 00454143 43455320 CHILD 10.EACCES + 0cd10 31330045 42555359 20313600 454e4f54 13.EBUSY 16.ENOT + 0cd20 44495220 32300045 4e4f5350 43203238 DIR 20.ENOSPC 28 + 0cd30 002e2e2f 2e2e2f2e 2e2f2e2e 2f2e2e2f .../../../../../ + 0cd40 2e2e2f2e 2e2f2e2e 2f2e2e2f 2e2e2f68 ../../../../../h + 0cd50 6f6d652f 7774662f 2e6c6f63 616c2f6c ome/wtf/.local/l + 0cd60 69622f70 7974686f 6e332e38 2f736974 ib/python3.8/sit + 0cd70 652d7061 636b6167 65732f70 7974686f e-packages/pytho + 0cd80 6e646174 615f736f 66747761 72655f70 ndata_software_p + 0cd90 69636f6c 6962632f 64617461 2f6e6577 icolibc/data/new + 0cda0 6c69622f 6c696263 2f657272 6e6f2f65 lib/libc/errno/e + 0cdb0 72726e6f 2e630045 434f4e4e 41424f52 rrno.c.ECONNABOR + 0cdc0 54454420 31313300 45465459 50452037 TED 113.EFTYPE 7 + 0cdd0 39004543 414e4345 4c454420 31343000 9.ECANCELED 140. + 0cde0 4550524f 544f4e4f 53555050 4f525420 EPROTONOSUPPORT + 0cdf0 31323300 5f737973 5f6e6572 72004546 123._sys_nerr.EF + 0ce00 42494720 32370045 494e5641 4c203232 BIG 27.EINVAL 22 + 0ce10 004e4557 4c49425f 54485245 41445f4c .NEWLIB_THREAD_L + 0ce20 4f43414c 5f455252 4e4f204e 45574c49 OCAL_ERRNO NEWLI + 0ce30 425f5448 52454144 5f4c4f43 414c005f B_THREAD_LOCAL._ + 0ce40 5f657272 6f725f74 5f646566 696e6564 _error_t_defined + 0ce50 20310045 4e46494c 45203233 00454e45 1.ENFILE 23.ENE + 0ce60 54524553 45542031 32360045 4e4f4d53 TRESET 126.ENOMS + 0ce70 47203335 00454144 44524e4f 54415641 G 35.EADDRNOTAVA + 0ce80 494c2031 32350045 484f5354 554e5245 IL 125.EHOSTUNRE + 0ce90 41434820 31313800 454e414d 45544f4f ACH 118.ENAMETOO + 0cea0 4c4f4e47 20393100 45504950 45203332 LONG 91.EPIPE 32 + 0ceb0 0045484f 5354444f 574e2031 31370045 .EHOSTDOWN 117.E + 0cec0 42414446 20390045 4e4f454e 54203200 BADF 9.ENOENT 2. + 0ced0 45434f4e 4e524546 55534544 20313131 ECONNREFUSED 111 + 0cee0 0045434f 4e4e5245 53455420 31303400 .ECONNRESET 104. + 0cef0 454e4f4c 434b2034 36004557 4f554c44 ENOLCK 46.EWOULD + 0cf00 424c4f43 4b204541 4741494e 00455354 BLOCK EAGAIN.EST + 0cf10 414c4520 31333300 4550524f 544f2037 ALE 133.EPROTO 7 + 0cf20 31004549 4f203500 454e4f44 41544120 1.EIO 5.ENODATA + 0cf30 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545f4e41 52524f57 2030004d 5f535152 T_NARROW 0.M_SQR + 0edf0 54322031 2e343134 32313335 36323337 T2 1.41421356237 + 0ee00 33303935 30343838 30006c6f 67637461 309504880.logcta + 0ee10 696c0044 544f415f 44494720 31370073 il.DTOA_DIG 17.s + 0ee20 74725f6c 70616400 6670636c 61737369 tr_lpad.fpclassi + 0ee30 6679285f 5f782920 285f5f62 75696c74 fy(__x) (__built + 0ee40 696e5f66 70636c61 73736966 79202846 in_fpclassify (F + 0ee50 505f4e41 4e2c2046 505f494e 46494e49 P_NAN, FP_INFINI + 0ee60 54452c20 46505f4e 4f524d41 4c2c2046 TE, FP_NORMAL, F + 0ee70 505f5355 424e4f52 4d414c2c 2046505f P_SUBNORMAL, FP_ + 0ee80 5a45524f 2c205f5f 78292900 5f494545 ZERO, __x))._IEE + 0ee90 455f202d 31006d79 5f707574 6328632c E_ -1.my_putc(c, + 0eea0 73747265 616d2920 646f207b 202b2b73 stream) do { ++s + 0eeb0 74726561 6d5f6c65 6e3b2070 75746328 tream_len; putc( + 0eec0 632c2073 74726561 6d293b20 7d207768 c, stream); } wh + 0eed0 696c6528 3029005f 5f494545 455f4442 ile(0).__IEEE_DB + 0eee0 4c5f4558 50424941 53203130 3233004d L_EXPBIAS 1023.M + 0eef0 4154485f 4552524e 4f203100 46505f4e ATH_ERRNO 1.FP_N + 0ef00 4f524d41 4c203400 4d5f4956 4c4e3130 ORMAL 4.M_IVLN10 + 0ef10 20302e34 33343239 34343831 39303332 0.4342944819032 + 0ef20 35313832 37363500 696e766c 6e324e00 5182765.invln2N. + 0ef30 53495a45 4f465f55 4c544f41 205f5f53 SIZEOF_ULTOA __S + 0ef40 495a454f 465f4c4f 4e475f4c 4f4e475f IZEOF_LONG_LONG_ + 0ef50 5f004558 505f504f 4c595f57 49444520 _.EXP_POLY_WIDE + 0ef60 30005f5f 756c746f 615f696e 76657274 0.__ultoa_invert + 0ef70 005f5f70 6f77665f 6c6f6732 5f646174 .__powf_log2_dat + 0ef80 61004d5f 494e564c 4e322031 2e343432 a.M_INVLN2 1.442 + 0ef90 36393530 34303838 38393633 33383730 6950408889633870 + 0efa0 4530005f 64746f61 2028752e 5f5f6474 E0._dtoa (u.__dt + 0efb0 6f612900 544f4c4f 57286329 20282863 oa).TOLOW(c) ((c + 0efc0 29207c20 43415345 5f434f4e 56455254 ) | CASE_CONVERT + 0efd0 29005f5f 65787032 665f6461 74610045 ).__exp2f_data.E + 0efe0 58545f46 5241434c 42495453 2044424c XT_FRACLBITS DBL + 0eff0 5f4d414e 545f4449 4700464c 5f5a4649 _MANT_DIG.FL_ZFI + 0f000 4c4c2030 78303030 31005549 4e54464c LL 0x0001.UINTFL + 0f010 4f415420 75696e74 36345f74 0046505f OAT uint64_t.FP_ + 0f020 5244495f 544f5a20 3000464c 5f4c4f4e RDI_TOZ 0.FL_LON + 0f030 47203078 30303830 005f5f64 746f615f G 0x0080.__dtoa_ + 0f040 7363616c 655f646f 776e0044 544f415f scale_down.DTOA_ + 0f050 5343414c 455f5550 5f4e554d 20390069 SCALE_UP_NUM 9.i + 0f060 73736967 6e616c69 6e67285f 5f782920 ssignaling(__x) + 0f070 28287369 7a656f66 285f5f78 29203d3d ((sizeof(__x) == + 0f080 2073697a 656f6628 666c6f61 74292920 sizeof(float)) + 0f090 3f205f5f 69737369 676e616c 696e6766 ? __issignalingf + 0f0a0 285f5f78 29203a20 2873697a 656f6628 (__x) : (sizeof( + 0f0b0 5f5f7829 203d3d20 73697a65 6f662864 __x) == sizeof(d + 0f0c0 6f75626c 65292920 3f205f5f 69737369 ouble)) ? __issi + 0f0d0 676e616c 696e6720 2828646f 75626c65 gnaling ((double + 0f0e0 2920285f 5f782929 203a205f 5f697373 ) (__x)) : __iss + 0f0f0 69676e61 6c696e67 6c28286c 6f6e6720 ignalingl((long + 0f100 646f7562 6c652920 285f5f78 29292900 double) (__x))). + 0f110 5f44544f 415f454e 47494e45 5f485f20 _DTOA_ENGINE_H_ + 0f120 00455854 5f465241 43484249 54532044 .EXT_FRACHBITS D + 0f130 424c5f4d 414e545f 44494700 4c4f4732 BL_MANT_DIG.LOG2 + 0f140 5f504f4c 595f4f52 44455220 37007369 _POLY_ORDER 7.si + 0f150 676e6761 6d004855 47455f56 414c4620 gngam.HUGE_VALF + 0f160 285f5f62 75696c74 696e5f68 7567655f (__builtin_huge_ + 0f170 76616c66 28292900 5f5f7569 6e743634 valf()).__uint64 + 0f180 5f740075 6e6c696b 656c7928 7829205f _t.unlikely(x) _ + 0f190 5f627569 6c74696e 5f657870 65637420 _builtin_expect + 0f1a0 28782c20 3029005f 5f6c6f67 665f6461 (x, 0).__logf_da + 0f1b0 74610061 72675f74 6f5f7369 676e6564 ta.arg_to_signed + 0f1c0 28666c61 67732c72 6573756c 745f7661 (flags,result_va + 0f1d0 72292061 72675f74 6f5f7428 28666c61 r) arg_to_t((fla + 0f1e0 6773292c 20736967 6e65642c 20287265 gs), signed, (re + 0f1f0 73756c74 5f766172 2929004c 4f475f50 sult_var)).LOG_P + 0f200 4f4c595f 4f524445 52203600 4558545f OLY_ORDER 6.EXT_ + 0f210 4558505f 494e464e 414e2028 2831203c EXP_INFNAN ((1 < + 0f220 3c204558 545f4558 50424954 5329202d < EXT_EXPBITS) - + 0f230 20312900 44544f41 5f524f55 4e445f4e 1).DTOA_ROUND_N + 0f240 554d2028 44544f41 5f444947 202b2031 UM (DTOA_DIG + 1 + 0f250 29005f58 544f415f 46415354 5f485f20 )._XTOA_FAST_H_ + 0f260 005f4d41 54485f45 52524841 4e444c49 ._MATH_ERRHANDLI + 0f270 4e475f45 52524e4f 20300069 736e616e NG_ERRNO 0.isnan + 0f280 285f5f78 2920285f 5f627569 6c74696e (__x) (__builtin + 0f290 5f69736e 616e2028 5f5f7829 2900464c _isnan (__x)).FL + 0f2a0 5f4e4547 41544956 45203078 30343030 _NEGATIVE 0x0400 + 0f2b0 005f5f6c 6f673266 5f646174 6100504f .__log2f_data.PO + 0f2c0 57465f53 43414c45 5f424954 53203000 WF_SCALE_BITS 0. + 0f2d0 464c5f41 4c545550 50203078 30383030 FL_ALTUPP 0x0800 + 0f2e0 0044544f 415f5a45 524f2032 00504f57 .DTOA_ZERO 2.POW + 0f2f0 5f4c4f47 5f544142 4c455f42 49545320 _LOG_TABLE_BITS + 0f300 37004d5f 4c4e3248 4920362e 39333134 7.M_LN2HI 6.9314 + 0f310 37313830 33363931 32333831 36343945 718036912381649E + 0f320 2d310054 4f434153 45286329 20282863 -1.TOCASE(c) ((c + 0f330 29202d20 63617365 5f636f6e 76657274 ) - case_convert + 0f340 29005052 494e5446 5f4c4556 454c2050 ).PRINTF_LEVEL P + 0f350 52494e54 465f5354 44006c6f 67322878 RINTF_STD.log2(x + 0f360 2920286c 6f672028 7829202f 205f4d5f ) (log (x) / _M_ + 0f370 4c4e3229 00464c4f 41542064 6f75626c LN2).FLOAT doubl + 0f380 6500464c 5f505245 43203078 30303430 e.FL_PREC 0x0040 + 0f390 0057414e 545f524f 554e4449 4e472031 .WANT_ROUNDING 1 + 0f3a0 004c4f47 465f504f 4c595f4f 52444552 .LOGF_POLY_ORDER + 0f3b0 20340046 4c5f5245 50445f54 59504520 4.FL_REPD_TYPE + 0f3c0 30783032 3030005f 5f706f77 5f6c6f67 0x0200.__pow_log + 0f3d0 5f646174 61005f5f 49454545 5f464c54 _data.__IEEE_FLT + 0f3e0 5f455850 42494153 20313237 0058544f _EXPBIAS 127.XTO + 0f3f0 415f5052 45464958 20307830 31303000 A_PREFIX 0x0100. + 0f400 5f5f6578 705f6461 7461005f 5f64746f __exp_data.__dto + 0f410 615f7363 616c655f 75700069 73677265 a_scale_up.isgre + 0f420 61746572 285f5f78 2c5f5f79 2920285f ater(__x,__y) (_ + 0f430 5f627569 6c74696e 5f697367 72656174 _builtin_isgreat + 0f440 65722028 5f5f782c 205f5f79 29290048 er (__x, __y)).H + 0f450 5547455f 56414c20 285f5f62 75696c74 UGE_VAL (__built + 0f460 696e5f68 7567655f 76616c28 2929005f in_huge_val())._ + 0f470 5f6d6174 685f7769 74685f65 72726e6f _math_with_errno + 0f480 28782c65 29202878 29004650 5f585f55 (x,e) (x).FP_X_U + 0f490 464c2030 78303200 43484543 4b5f4c4f FL 0x02.CHECK_LO + 0f4a0 4e474c4f 4e472874 79706529 20656c73 NGLONG(type) els + 0f4b0 65206966 20287369 7a656f66 28747970 e if (sizeof(typ + 0f4c0 6529203d 3d207369 7a656f66 286c6f6e e) == sizeof(lon + 0f4d0 67206c6f 6e672929 20666c61 6773207c g long)) flags | + 0f4e0 3d20464c 5f4c4f4e 477c464c 5f524550 = FL_LONG|FL_REP + 0f4f0 445f5459 50453b00 4d5f5351 52545049 D_TYPE;.M_SQRTPI + 0f500 20312e37 37323435 33383530 39303535 1.7724538509055 + 0f510 31363032 37393239 38310046 4c5f414c 1602792981.FL_AL + 0f520 54203078 30303130 0075696e 7437325f T 0x0010.uint72_ + 0f530 74004558 505f4249 41532031 30323300 t.EXP_BIAS 1023. + 0f540 44544f41 5f434152 52592031 36006e65 DTOA_CARRY 16.ne + 0f550 676c6e32 68694e00 4d5f5049 5f322031 gln2hiN.M_PI_2 1 + 0f560 2e353730 37393633 32363739 34383936 .570796326794896 + 0f570 36313932 33006973 6e6f726d 616c285f 61923.isnormal(_ + 0f580 5f782920 285f5f62 75696c74 696e5f69 _x) (__builtin_i + 0f590 736e6f72 6d616c20 285f5f78 29290046 snormal (__x)).F + 0f5a0 505f5a45 524f2032 005f5f6c 6f675f64 P_ZERO 2.__log_d + 0f5b0 61746100 6d617468 5f657272 68616e64 ata.math_errhand + 0f5c0 6c696e67 20285f4d 4154485f 45525248 ling (_MATH_ERRH + 0f5d0 414e444c 494e475f 4552524e 4f207c20 ANDLING_ERRNO | + 0f5e0 5f4d4154 485f4552 5248414e 444c494e _MATH_ERRHANDLIN + 0f5f0 475f4552 52455843 45505429 004d5f33 G_ERREXCEPT).M_3 + 0f600 50495f34 20322e33 35363139 34343930 PI_4 2.356194490 + 0f610 31393233 34343833 37304530 00484156 1923448370E0.HAV + 0f620 455f4641 53545f46 4d412030 00434845 E_FAST_FMA 0.CHE + 0f630 434b5f49 4e545f53 495a4528 6c657474 CK_INT_SIZE(lett + 0f640 65722c74 79706529 20696620 2863203d er,type) if (c = + 0f650 3d206c65 74746572 29207b20 69662028 = letter) { if ( + 0f660 73697a65 6f662874 79706529 203d3d20 sizeof(type) == + 0f670 73697a65 6f662869 6e742929 203b2065 sizeof(int)) ; e + 0f680 6c736520 69662028 73697a65 6f662874 lse if (sizeof(t + 0f690 79706529 203d3d20 73697a65 6f66286c ype) == sizeof(l + 0f6a0 6f6e6729 2920666c 61677320 7c3d2046 ong)) flags |= F + 0f6b0 4c5f4c4f 4e473b20 43484543 4b5f4c4f L_LONG; CHECK_LO + 0f6c0 4e474c4f 4e472874 79706529 20656c73 NGLONG(type) els + 0f6d0 65206966 20287369 7a656f66 28747970 e if (sizeof(typ + 0f6e0 6529203d 3d207369 7a656f66 2873686f e) == sizeof(sho + 0f6f0 72742929 20666c61 6773207c 3d20464c rt)) flags |= FL + 0f700 5f53484f 52543b20 636f6e74 696e7565 _SHORT; continue + 0f710 3b207d00 5f4d4154 485f434f 4e464947 ; }._MATH_CONFIG + 0f720 5f482000 74616232 004d5f32 5f504920 _H .tab2.M_2_PI + 0f730 302e3633 36363139 37373233 36373538 0.63661977236758 + 0f740 31333433 30380050 4f575f4c 4f475f50 134308.POW_LOG_P + 0f750 4f4c595f 4f524445 52203800 48415645 OLY_ORDER 8.HAVE + 0f760 5f464153 545f464d 41462030 004d5f4c _FAST_FMAF 0.M_L + 0f770 4f47325f 45205f4d 5f4c4e32 00455854 OG2_E _M_LN2.EXT + 0f780 5f465241 43424954 53202845 58545f46 _FRACBITS (EXT_F + 0f790 5241434c 42495453 202b2045 58545f46 RACLBITS + EXT_F + 0f7a0 52414348 42495453 29004d5f 50492033 RACHBITS).M_PI 3 + 0f7b0 2e313431 35393236 35333538 39373933 .141592653589793 + 0f7c0 32333834 36005f5f 49454545 5f44424c 23846.__IEEE_DBL + 0f7d0 5f455850 4c454e20 3131005f 5f696565 _EXPLEN 11.__iee + 0f7e0 655f6578 745f6669 656c645f 74797065 e_ext_field_type + 0f7f0 20756e73 69676e65 64206c6f 6e67206c unsigned long l + 0f800 6f6e6700 696e766c 6e325f73 63616c65 ong.invln2_scale + 0f810 64004841 56455f46 4153545f 4c524f55 d.HAVE_FAST_LROU + 0f820 4e442030 00657870 325f706f 6c790069 ND 0.exp2_poly.i + 0f830 6e766300 5f5f4945 45455f44 424c5f46 nvc.__IEEE_DBL_F + 0f840 5241434c 454e2028 3634202d 20285f5f RACLEN (64 - (__ + 0f850 49454545 5f44424c 5f455850 4c454e20 IEEE_DBL_EXPLEN + 0f860 2b203129 29004d5f 50495f34 20302e37 + 1)).M_PI_4 0.7 + 0f870 38353339 38313633 33393734 34383330 8539816339744830 + 0f880 39363200 73686966 74373274 6f363400 962.shift72to64. + 0f890 46505f58 5f494d50 20307830 3100706f FP_X_IMP 0x01.po + 0f8a0 6c795f73 63616c65 64004454 4f415f4d ly_scaled.DTOA_M + 0f8b0 41585f31 305f4558 50204442 4c5f4d41 AX_10_EXP DBL_MA + 0f8c0 585f3130 5f455850 00544f49 4e545f49 X_10_EXP.TOINT_I + 0f8d0 4e545249 4e534943 53203000 6469766d NTRINSICS 0.divm + 0f8e0 6f645f74 0046505f 585f494e 56203078 od_t.FP_X_INV 0x + 0f8f0 31300046 4c5f464c 54464958 20307838 10.FL_FLTFIX 0x8 + 0f900 30303000 5f504f53 49585f20 30005f5f 000._POSIX_ 0.__ + 0f910 65637674 5f627566 0046505f 4e414e20 ecvt_buf.FP_NAN + 0f920 30004d5f 4c4f4731 30452030 2e343334 0.M_LOG10E 0.434 + 0f930 32393434 38313930 33323531 38323736 2944819032518276 + 0f940 35004d5f 4c4e3220 5f4d5f4c 4e320044 5.M_LN2 _M_LN2.D + 0f950 544f415f 4d494e5f 31305f45 58502044 TOA_MIN_10_EXP D + 0f960 424c5f4d 494e5f31 305f4558 50006d75 BL_MIN_10_EXP.mu + 0f970 6c353100 73686966 74373200 5f5f6474 l51.shift72.__dt + 0f980 6f615f72 6f756e64 005f5f49 4545455f oa_round.__IEEE_ + 0f990 464c545f 46524143 4c454e20 28333220 FLT_FRACLEN (32 + 0f9a0 2d20285f 5f494545 455f464c 545f4558 - (__IEEE_FLT_EX + 0f9b0 504c454e 202b2031 29290046 505f524d PLEN + 1)).FP_RM + 0f9c0 20310062 75662028 752e5f5f 62756629 1.buf (u.__buf) + 0f9d0 006c6f67 63004945 45455f37 35345f32 .logc.IEEE_754_2 + 0f9e0 3030385f 534e414e 2031005f 4d415448 008_SNAN 1._MATH + 0f9f0 5f455252 48414e44 4c494e47 5f455252 _ERRHANDLING_ERR + 0fa00 45584345 50542030 0044544f 415f494e EXCEPT 0.DTOA_IN + 0fa10 46203400 5f5f4945 45455f46 4c545f45 F 4.__IEEE_FLT_E + 0fa20 58504c45 4e203800 77696474 68004d5f XPLEN 8.width.M_ + 0fa30 325f5351 52545049 20312e31 32383337 2_SQRTPI 1.12837 + 0fa40 39313637 30393535 31323537 33393000 916709551257390. + 0fa50 73747265 616d5f6c 656e004e 4f494e4c stream_len.NOINL + 0fa60 494e4520 5f5f6174 74726962 7574655f INE __attribute_ + 0fa70 5f202828 6e6f696e 6c696e65 2929004c _ ((noinline)).L + 0fa80 4f47325f 5441424c 455f4249 54532036 OG2_TABLE_BITS 6 + 0fa90 00484156 455f4641 53545f52 4f554e44 .HAVE_FAST_ROUND + 0faa0 20300046 505f5355 424e4f52 4d414c20 0.FP_SUBNORMAL + 0fab0 33004c4f 475f504f 4c59315f 4f524445 3.LOG_POLY1_ORDE + 0fac0 52203132 004c4f47 325f504f 4c59315f R 12.LOG2_POLY1_ + 0fad0 4f524445 52203131 004c4f47 465f5441 ORDER 11.LOGF_TA + 0fae0 424c455f 42495453 20340046 505f494c BLE_BITS 4.FP_IL + 0faf0 4f47424e 414e205f 5f494e54 5f4d4158 OGBNAN __INT_MAX + 0fb00 5f5f0069 6e766c6e 32686900 5f5f6275 __.invln2hi.__bu + 0fb10 66007369 676e6269 74285f5f 78292028 f.signbit(__x) ( + 0fb20 2873697a 656f6628 5f5f7829 203d3d20 (sizeof(__x) == + 0fb30 73697a65 6f662866 6c6f6174 2929203f sizeof(float)) ? + 0fb40 205f5f62 75696c74 696e5f73 69676e62 __builtin_signb + 0fb50 69746628 5f5f7829 203a2028 2873697a itf(__x) : ((siz + 0fb60 656f6628 5f5f7829 203d3d20 73697a65 eof(__x) == size + 0fb70 6f662864 6f75626c 65292920 3f205f5f of(double)) ? __ + 0fb80 6275696c 74696e5f 7369676e 62697420 builtin_signbit + 0fb90 2828646f 75626c65 29285f5f 78292920 ((double)(__x)) + 0fba0 3a205f5f 6275696c 74696e5f 7369676e : __builtin_sign + 0fbb0 6269746c 28286c6f 6e672064 6f75626c bitl((long doubl + 0fbc0 6529285f 5f782929 29290046 4c5f5350 e)(__x)))).FL_SP + 0fbd0 41434520 30783030 3034004c 4f473246 ACE 0x0004.LOG2F + 0fbe0 5f544142 4c455f42 49545320 3400464c _TABLE_BITS 4.FL + 0fbf0 5f574944 54482030 78303032 30006973 _WIDTH 0x0020.is + 0fc00 6c657373 285f5f78 2c5f5f79 2920285f less(__x,__y) (_ + 0fc10 5f627569 6c74696e 5f69736c 65737320 _builtin_isless + 0fc20 285f5f78 2c205f5f 79292900 46505f52 (__x, __y)).FP_R + 0fc30 4e203000 45585032 465f5441 424c455f N 0.EXP2F_TABLE_ + 0fc40 42495453 20350050 4f57465f 5343414c BITS 5.POWF_SCAL + 0fc50 45202828 646f7562 6c652920 2831203c E ((double) (1 < + 0fc60 3c20504f 57465f53 43414c45 5f424954 < POWF_SCALE_BIT + 0fc70 53292900 4d5f5351 52543320 312e3733 S)).M_SQRT3 1.73 + 0fc80 32303530 38303735 36383837 37313930 2050807568877190 + 0fc90 30300044 544f415f 4e414e20 3800464c 00.DTOA_NAN 8.FL + 0fca0 5f4c5041 44203078 30303038 00494e46 _LPAD 0x0008.INF + 0fcb0 494e4954 5920285f 5f627569 6c74696e INITY (__builtin + 0fcc0 5f696e66 66282929 0044544f 415f4d49 _inff()).DTOA_MI + 0fcd0 4e555320 31006973 756e6f72 64657265 NUS 1.isunordere + 0fce0 64285f5f 782c5f5f 79292028 5f5f6275 d(__x,__y) (__bu + 0fcf0 696c7469 6e5f6973 756e6f72 64657265 iltin_isunordere + 0fd00 6420285f 5f782c20 5f5f7929 29004650 d (__x, __y)).FP + 0fd10 5f524449 5f524420 31006172 675f746f _RDI_RD 1.arg_to + 0fd20 5f742866 6c616773 2c5f735f 2c5f7265 _t(flags,_s_,_re + 0fd30 73756c74 5f292069 66202828 666c6167 sult_) if ((flag + 0fd40 73292026 20464c5f 4c4f4e47 29207b20 s) & FL_LONG) { + 0fd50 69662028 28666c61 67732920 2620464c if ((flags) & FL + 0fd60 5f524550 445f5459 50452920 285f7265 _REPD_TYPE) (_re + 0fd70 73756c74 5f29203d 2076615f 61726728 sult_) = va_arg( + 0fd80 61702c20 5f735f20 6c6f6e67 206c6f6e ap, _s_ long lon + 0fd90 67293b20 656c7365 20285f72 6573756c g); else (_resul + 0fda0 745f2920 3d207661 5f617267 2861702c t_) = va_arg(ap, + 0fdb0 205f735f 206c6f6e 67293b20 7d20656c _s_ long); } el + 0fdc0 7365207b 20285f72 6573756c 745f2920 se { (_result_) + 0fdd0 3d207661 5f617267 2861702c 205f735f = va_arg(ap, _s_ + 0fde0 20696e74 293b2069 66202828 666c6167 int); if ((flag + 0fdf0 73292026 20464c5f 53484f52 5429207b s) & FL_SHORT) { + 0fe00 20696620 2828666c 61677329 20262046 if ((flags) & F + 0fe10 4c5f5245 50445f54 59504529 20285f72 L_REPD_TYPE) (_r + 0fe20 6573756c 745f2920 3d20285f 735f2063 esult_) = (_s_ c + 0fe30 68617229 20285f72 6573756c 745f293b har) (_result_); + 0fe40 20656c73 6520285f 72657375 6c745f29 else (_result_) + 0fe50 203d2028 5f735f20 73686f72 74292028 = (_s_ short) ( + 0fe60 5f726573 756c745f 293b207d 207d005f _result_); } }._ + 0fe70 49454545 5f46505f 485f2000 706f6c79 IEEE_FP_H_ .poly + 0fe80 3100696e 766c6e32 6c6f0070 72656300 1.invln2lo.prec. + 0fe90 4d5f5351 5254315f 3220302e 37303731 M_SQRT1_2 0.7071 + 0fea0 30363738 31313836 35343735 32343430 0678118654752440 + 0feb0 00504f57 465f4c4f 47325f54 41424c45 .POWF_LOG2_TABLE + 0fec0 5f424954 53203400 6275665f 6c656e00 _BITS 4.buf_len. + 0fed0 5f5f4945 45455f46 4c545f4d 4158504f __IEEE_FLT_MAXPO + 0fee0 5754574f 20282866 6c6f6174 2928314c WTWO ((float)(1L + 0fef0 203c3c20 2833322d 3829202d 20312929 << (32-8) - 1)) + 0ff00 00756c74 6f615f73 69676e65 645f7400 .ultoa_signed_t. + 0ff10 5052494e 54465f4c 4f4e474c 4f4e4720 PRINTF_LONGLONG + 0ff20 00505249 4e54465f 464c4f41 545f4152 .PRINTF_FLOAT_AR + 0ff30 47286170 29207661 5f617267 2861702c G(ap) va_arg(ap, + 0ff40 20646f75 626c6529 0069736c 65737365 double).islesse + 0ff50 7175616c 285f5f78 2c5f5f79 2920285f qual(__x,__y) (_ + 0ff60 5f627569 6c74696e 5f69736c 65737365 _builtin_islesse + 0ff70 7175616c 20285f5f 782c205f 5f792929 qual (__x, __y)) + 0ff80 00455850 325f504f 4c595f4f 52444552 .EXP2_POLY_ORDER + 0ff90 20350045 58505f54 41424c45 5f424954 5.EXP_TABLE_BIT + 0ffa0 53203700 6172675f 746f5f75 6e736967 S 7.arg_to_unsig + 0ffb0 6e656428 666c6167 732c7265 73756c74 ned(flags,result + 0ffc0 5f766172 29206172 675f746f 5f742828 _var) arg_to_t(( + 0ffd0 666c6167 73292c20 756e7369 676e6564 flags), unsigned + 0ffe0 2c202872 6573756c 745f7661 72292900 , (result_var)). + 0fff0 5f5f4945 45455f44 424c5f4e 414e5f45 __IEEE_DBL_NAN_E + 10000 58502030 78376666 005f5f49 4545455f XP 0x7ff.__IEEE_ + 10010 44424c5f 4d415850 4f575457 4f202828 DBL_MAXPOWTWO (( + 10020 646f7562 6c652928 314c203c 3c203332 double)(1L << 32 + 10030 202d2032 29202a20 28314c20 3c3c2028 - 2) * (1L << ( + 10040 33322d31 3129202d 20333220 2b203129 32-11) - 32 + 1) + 10050 29004650 5f585f4f 464c2030 78303400 ).FP_X_OFL 0x04. + 10060 4d5f4c4e 324c4f20 312e3930 38323134 M_LN2LO 1.908214 + 10070 39323932 37303538 37373030 30452d31 9292705877000E-1 + 10080 30004d5f 4c4f4732 4520312e 34343236 0.M_LOG2E 1.4426 + 10090 39353034 30383838 39363334 30373400 950408889634074. + 100a0 474e5520 43313720 392e342e 30202d6d GNU C17 9.4.0 -m + 100b0 73656375 72652d70 6c74202d 6d333220 secure-plt -m32 + 100c0 2d6d6269 672d656e 6469616e 202d6d6e -mbig-endian -mn + 100d0 6f2d6d75 6c746970 6c65202d 6d736f66 o-multiple -msof + 100e0 742d666c 6f617420 2d67202d 6733202d t-float -g -g3 - + 100f0 4f73202d 4f73202d 4f33202d 7374643d Os -Os -O3 -std= + 10100 63313720 2d666675 6e637469 6f6e2d73 c17 -ffunction-s + 10110 65637469 6f6e7320 2d666f6d 69742d66 ections -fomit-f + 10120 72616d65 2d706f69 6e746572 202d666e rame-pointer -fn + 10130 6f2d6275 696c7469 6e202d66 65786365 o-builtin -fexce + 10140 7074696f 6e73202d 666e6f2d 73746163 ptions -fno-stac + 10150 6b2d7072 6f746563 746f7220 2d666e6f k-protector -fno + 10160 2d636f6d 6d6f6e20 2d66726f 756e6469 -common -froundi + 10170 6e672d6d 61746800 2e2e2f2e 2e2f2e2e ng-math.../../.. + 10180 2f2e2e2f 2e2e2f2e 2e2f2e2e 2f2e2e2f /../../../../../ + 10190 2e2e2f2e 2e2f686f 6d652f77 74662f2e ../../home/wtf/. + 101a0 6c6f6361 6c2f6c69 622f7079 74686f6e local/lib/python + 101b0 332e382f 73697465 2d706163 6b616765 3.8/site-package + 101c0 732f7079 74686f6e 64617461 5f736f66 s/pythondata_sof + 101d0 74776172 655f7069 636f6c69 62632f64 tware_picolibc/d + 101e0 6174612f 6e65776c 69622f6c 6962632f ata/newlib/libc/ + 101f0 73747269 6e672f73 7472636d 702e6300 string/strcmp.c. + 10200 5f5f7374 64696f00 434f4e46 49475f43 __stdio.CONFIG_C + 10210 50555f48 554d414e 5f4e414d 45202261 PU_HUMAN_NAME "a + 10220 32705f57 4222002f 64617461 2f70726f 2p_WB"./data/pro + 10230 6a656374 732f6c69 7465782f 6c697465 jects/litex/lite + 10240 782f736f 632f736f 66747761 72652f6c x/soc/software/l + 10250 6962632f 73746469 6f2e6300 6c697465 ibc/stdio.c.lite + 10260 785f7075 7463006c 69746578 5f676574 x_putc.litex_get + 10270 63006361 72727900 494e545f 454e4449 c.carry.INT_ENDI + 10280 414e4e45 53535f48 20007564 776f7264 ANNESS_H .udword + 10290 73006e5f 7564776f 72645f62 69747300 s.n_udword_bits. + 102a0 494e545f 5554494c 5f482000 5f595547 INT_UTIL_H ._YUG + 102b0 415f4c49 54544c45 5f454e44 49414e20 A_LITTLE_ENDIAN + 102c0 3000554e 55534544 205f5f61 74747269 0.UNUSED __attri + 102d0 62757465 5f5f2828 756e7573 65642929 bute__((unused)) + 102e0 00686967 6800464e 414c4941 5328616c .high.FNALIAS(al + 102f0 6961735f 6e616d65 2c6f7269 67696e61 ias_name,origina + 10300 6c5f6e61 6d652920 766f6964 20616c69 l_name) void ali + 10310 61735f6e 616d6528 29205f5f 61747472 as_name() __attr + 10320 69627574 655f5f28 28616c69 61732823 ibute__((alias(# + 10330 6f726967 696e616c 5f6e616d 65292929 original_name))) + 10340 002f6461 74612f70 726f6a65 6374732f ./data/projects/ + 10350 70797468 6f6e6461 74612d73 6f667477 pythondata-softw + 10360 6172652d 636f6d70 696c6572 5f72742f are-compiler_rt/ + 10370 70797468 6f6e6461 74615f73 6f667477 pythondata_softw + 10380 6172655f 636f6d70 696c6572 5f72742f are_compiler_rt/ + 10390 64617461 2f6c6962 2f627569 6c74696e data/lib/builtin + 103a0 732f7564 69766d6f 64646934 2e630049 s/udivmoddi4.c.I + 103b0 4e545f54 59504553 5f482000 434f4d50 NT_TYPES_H .COMP + 103c0 494c455f 54494d45 5f415353 45525432 ILE_TIME_ASSERT2 + 103d0 28657870 722c636e 74292074 79706564 (expr,cnt) typed + 103e0 65662063 68617220 63745f61 73736572 ef char ct_asser + 103f0 745f2023 23636e74 5b286578 70722920 t_ ##cnt[(expr) + 10400 3f203120 3a202d31 5d20554e 55534544 ? 1 : -1] UNUSED + 10410 00434f4d 50494c45 5f54494d 455f4153 .COMPILE_TIME_AS + 10420 53455254 31286578 70722c63 6e742920 SERT1(expr,cnt) + 10430 434f4d50 494c455f 54494d45 5f415353 COMPILE_TIME_ASS + 10440 45525432 28657870 722c2063 6e742900 ERT2(expr, cnt). + 10450 4e4f5245 5455524e 205f5f61 74747269 NORETURN __attri + 10460 62757465 5f5f2828 6e6f7265 7475726e bute__((noreturn + 10470 29290063 6f6d706c 65782064 6f75626c )).complex doubl + 10480 65005f59 5547415f 4249475f 454e4449 e._YUGA_BIG_ENDI + 10490 414e2031 00494e54 5f4c4942 5f482000 AN 1.INT_LIB_H . + 104a0 474e5520 43393920 392e342e 30202d6d GNU C99 9.4.0 -m + 104b0 73656375 72652d70 6c74202d 6d333220 secure-plt -m32 + 104c0 2d6d6269 672d656e 6469616e 202d6d6e -mbig-endian -mn + 104d0 6f2d6d75 6c746970 6c65202d 6d736f66 o-multiple -msof + 104e0 742d666c 6f617420 2d673320 2d4f7320 t-float -g3 -Os + 104f0 2d737464 3d676e75 3939202d 666f6d69 -std=gnu99 -fomi + 10500 742d6672 616d652d 706f696e 74657220 t-frame-pointer + 10510 2d666e6f 2d627569 6c74696e 202d666e -fno-builtin -fn + 10520 6f2d7374 61636b2d 70726f74 6563746f o-stack-protecto + 10530 72202d66 65786365 7074696f 6e73202d r -fexceptions - + 10540 666e6f2d 6c746f00 434f4d50 494c455f fno-lto.COMPILE_ + 10550 54494d45 5f415353 45525428 65787072 TIME_ASSERT(expr + 10560 2920434f 4d50494c 455f5449 4d455f41 ) COMPILE_TIME_A + 10570 53534552 54312865 7870722c 205f5f43 SSERT1(expr, __C + 10580 4f554e54 45525f5f 2900434f 4d504c45 OUNTER__).COMPLE + 10590 585f5245 414c2878 29205f5f 7265616c X_REAL(x) __real + 105a0 5f5f2878 2900636f 6d706c65 78206c6f __(x).complex lo + 105b0 6e672064 6f75626c 65002f64 6174612f ng double./data/ + 105c0 70726f6a 65637473 2f613270 2f627569 projects/a2p/bui + 105d0 6c642f6c 69746578 2f66756c 6c2d6c69 ld/litex/full-li + 105e0 7465782f 6275696c 642f636d 6f64372f tex/build/cmod7/ + 105f0 736f6674 77617265 2f6c6962 636f6d70 software/libcomp + 10600 696c6572 5f727400 414c5741 59535f49 iler_rt.ALWAYS_I + 10610 4e4c494e 45205f5f 61747472 69627574 NLINE __attribut + 10620 655f5f28 28616c77 6179735f 696e6c69 e__((always_inli + 10630 6e652929 004e4f49 4e4c494e 45205f5f ne)).NOINLINE __ + 10640 61747472 69627574 655f5f28 286e6f69 attribute__((noi + 10650 6e6c696e 65292900 636f6d70 6c657820 nline)).complex + 10660 666c6f61 74004152 4d5f4541 42495f46 float.ARM_EABI_F + 10670 4e414c49 41532861 65616269 5f6e616d NALIAS(aeabi_nam + 10680 652c6e61 6d652920 0073755f 696e7400 e,name) .su_int. + 10690 64695f69 6e740043 4f4d5049 4c45525f di_int.COMPILER_ + 106a0 52545f41 42492000 5f5f7564 69766d6f RT_ABI .__udivmo + 106b0 64646934 00636f6d 70696c65 7272745f ddi4.compilerrt_ + 106c0 61626f72 74282920 636f6d70 696c6572 abort() compiler + 106d0 72745f61 626f7274 5f696d70 6c285f5f rt_abort_impl(__ + 106e0 46494c45 5f5f2c20 5f5f4c49 4e455f5f FILE__, __LINE__ + 106f0 2c205f5f 66756e63 5f5f2900 434f4d50 , __func__).COMP + 10700 4c45585f 494d4147 494e4152 59287829 LEX_IMAGINARY(x) + 10710 205f5f69 6d61675f 5f287829 006e5f75 __imag__(x).n_u + 10720 776f7264 5f626974 73006475 5f696e74 word_bits.du_int + 10730 005f5f75 64697664 6933002f 64617461 .__udivdi3./data + 10740 2f70726f 6a656374 732f7079 74686f6e /projects/python + 10750 64617461 2d736f66 74776172 652d636f data-software-co + 10760 6d70696c 65725f72 742f7079 74686f6e mpiler_rt/python + 10770 64617461 5f736f66 74776172 655f636f data_software_co + 10780 6d70696c 65725f72 742f6461 74612f6c mpiler_rt/data/l + 10790 69622f62 75696c74 696e732f 75646976 ib/builtins/udiv + 107a0 6469332e 63002f64 6174612f 70726f6a di3.c./data/proj + 107b0 65637473 2f613270 2f627569 6c642f6c ects/a2p/build/l + 107c0 69746578 2f66756c 6c2d6c69 7465782f itex/full-litex/ + 107d0 6275696c 642f636d 6f64372f 736f6674 build/cmod7/soft + 107e0 77617265 2f6c6962 62617365 002f6461 ware/libbase./da + 107f0 74612f70 726f6a65 6374732f 6c697465 ta/projects/lite + 10800 782f6c69 7465782f 736f632f 736f6674 x/litex/soc/soft + 10810 77617265 2f6c6962 62617365 2f637263 ware/libbase/crc + 10820 31362e63 00637263 31365f74 61626c65 16.c.crc16_table + 10830 00444f31 28627566 29206372 63203d20 .DO1(buf) crc = + 10840 6372635f 7461626c 655b2828 696e7429 crc_table[((int) + 10850 63726320 5e20282a 6275662b 2b292920 crc ^ (*buf++)) + 10860 26203078 66665d20 5e202863 7263203e & 0xff] ^ (crc > + 10870 3e203829 3b00444f 34286275 66292044 > 8);.DO4(buf) D + 10880 4f322862 7566293b 20444f32 28627566 O2(buf); DO2(buf + 10890 293b0044 4f382862 75662920 444f3428 );.DO8(buf) DO4( + 108a0 62756629 3b20444f 34286275 66293b00 buf); DO4(buf);. + 108b0 444f3228 62756629 20444f31 28627566 DO2(buf) DO1(buf + 108c0 293b2044 4f312862 7566293b 00637263 ); DO1(buf);.crc + 108d0 5f746162 6c65002f 64617461 2f70726f _table./data/pro + 108e0 6a656374 732f6c69 7465782f 6c697465 jects/litex/lite + 108f0 782f736f 632f736f 66747761 72652f6c x/soc/software/l + 10900 69626261 73652f63 72633332 2e630062 ibbase/crc32.c.b + 10910 7573795f 77616974 5f757300 62757379 usy_wait_us.busy + 10920 5f776169 74002f64 6174612f 70726f6a _wait./data/proj + 10930 65637473 2f6c6974 65782f6c 69746578 ects/litex/litex + 10940 2f736f63 2f736f66 74776172 652f6c69 /soc/software/li + 10950 62626173 652f7379 7374656d 2e63004d bbase/system.c.M + 10960 454d5445 53545f44 4154415f 52414e44 EMTEST_DATA_RAND + 10970 4f4d2031 00736565 645f3332 00637472 OM 1.seed_32.ctr + 10980 6c5f6275 735f6572 726f7273 5f726561 l_bus_errors_rea + 10990 64007264 61746100 4f4e455a 45524f20 d.rdata.ONEZERO + 109a0 30786161 61616161 61610064 6174615f 0xaaaaaaaa.data_ + 109b0 6572726f 7273004d 454d5445 53545f44 errors.MEMTEST_D + 109c0 4154415f 52455452 49455320 30004d45 ATA_RETRIES 0.ME + 109d0 4d544553 545f4144 44525f52 414e444f MTEST_ADDR_RANDO + 109e0 4d203000 4d494220 284b4942 2a313032 M 0.MIB (KIB*102 + 109f0 3429006c 6673725f 74617073 00707269 4).lfsr_taps.pri + 10a00 6e745f73 697a6500 73656564 00616464 nt_size.seed.add + 10a10 725f6572 726f7273 00707472 5f6d6178 r_errors.ptr_max + 10a20 00686561 64657200 6275735f 6572726f .header.bus_erro + 10a30 7273006e 756d6572 61746f72 00707269 rs.numerator.pri + 10a40 6e745f73 70656564 00617272 61790073 nt_speed.array.s + 10a50 686f775f 70726f67 72657373 006d656d how_progress.mem + 10a60 74657374 5f616363 65737300 4d454d54 test_access.MEMT + 10a70 4553545f 41444452 5f53495a 45202833 EST_ADDR_SIZE (3 + 10a80 322a3130 32342900 6f6e5f65 72726f72 2*1024).on_error + 10a90 5f63616c 6c626163 6b007365 65645f74 _callback.seed_t + 10aa0 6f5f6461 74615f31 36006275 7273745f o_data_16.burst_ + 10ab0 73697a65 004d454d 54455354 5f444542 size.MEMTEST_DEB + 10ac0 55475f4d 41585f45 52524f52 53203430 UG_MAX_ERRORS 40 + 10ad0 30006461 74615f73 697a6500 73656564 0.data_size.seed + 10ae0 5f746f5f 64617461 5f333200 4d454d54 _to_data_32.MEMT + 10af0 4553545f 4255535f 53495a45 20283531 EST_BUS_SIZE (51 + 10b00 3229004b 49422031 30323400 6d656d74 2).KIB 1024.memt + 10b10 6573745f 636f6e66 69670047 49422028 est_config.GIB ( + 10b20 4d49422a 31303234 29005a45 524f4f4e MIB*1024).ZEROON + 10b30 45203078 35353535 35353535 006d656d E 0x55555555.mem + 10b40 74657374 5f616464 72002f64 6174612f test_addr./data/ + 10b50 70726f6a 65637473 2f6c6974 65782f6c projects/litex/l + 10b60 69746578 2f736f63 2f736f66 74776172 itex/soc/softwar + 10b70 652f6c69 62626173 652f6d65 6d746573 e/libbase/memtes + 10b80 742e6300 6f666673 65740070 72696e74 t.c.offset.print + 10b90 5f70726f 67726573 73006164 64725f73 _progress.addr_s + 10ba0 697a6500 6d656d74 6573745f 62757300 ize.memtest_bus. + 10bb0 72656164 5f737065 65640062 75735f73 read_speed.bus_s + 10bc0 697a6500 6f6e5f65 72726f72 0064656e ize.on_error.den + 10bd0 6f6d696e 61746f72 006f6b5f 6174006c ominator.ok_at.l + 10be0 66737200 77726974 655f7370 65656400 fsr.write_speed. + 10bf0 6d656d74 6573745f 64617461 00736565 memtest_data.see + 10c00 645f3136 002f6461 74612f70 726f6a65 d_16./data/proje + 10c10 6374732f 6c697465 782f6c69 7465782f cts/litex/litex/ + 10c20 736f632f 736f6674 77617265 2f6c6962 soc/software/lib + 10c30 62617365 2f756172 742e6300 75617274 base/uart.c.uart + 10c40 5f65765f 656e6162 6c655f77 72697465 _ev_enable_write + 10c50 00756172 745f7278 656d7074 795f7265 .uart_rxempty_re + 10c60 61640075 6172745f 72787478 5f777269 ad.uart_rxtx_wri + 10c70 74650075 6172745f 65765f70 656e6469 te.uart_ev_pendi + 10c80 6e675f72 65616400 75617274 5f65765f ng_read.uart_ev_ + 10c90 70656e64 696e675f 77726974 65007561 pending_write.ua + 10ca0 72745f72 7874785f 72656164 00756172 rt_rxtx_read.uar + 10cb0 745f6973 72007561 72745f74 7866756c t_isr.uart_txful + 10cc0 6c5f7265 616400 l_read. +Contents of section .debug_loc: + 0000 00000000 00010100 00010100 00020200 ................ + 0010 00030300 00000000 06d80000 07380001 .............8.. + 0020 6e000007 4c000007 bc00016e 000007bc n...L......n.... + 0030 000007c0 00038e7f 9f000007 c0000007 ................ + 0040 d000016e 000007d8 00000800 00016e00 ...n..........n. + 0050 00080000 00080800 02309f00 00081400 .........0...... + 0060 00081400 016e0000 08140000 08380002 .....n.......8.. + 0070 309f0000 08380000 08380001 6e000008 0....8...8..n... + 0080 38000008 54000230 9f000008 54000008 8...T..0....T... + 0090 6400016e 00000000 00000000 00000000 d..n............ + 00a0 000005f0 0000063c 00016f00 00065c00 .......<..o...\. + 00b0 00066800 016f0000 00000000 00000000 ..h..o.......... + 00c0 00000000 06500000 065c0002 309f0000 .....P...\..0... + 00d0 08640000 08780002 319f0000 00000000 .d...x..1....... + 00e0 00000700 00000000 06d80000 06e00002 ................ + 00f0 309f0000 07140000 07380001 6f000000 0........8..o... + 0100 00000000 00080000 00000000 00000000 ................ + 0110 00000006 d8000007 38000231 9f000007 ........8..1.... + 0120 4c000007 9c000231 9f000007 9c000007 L......1........ + 0130 d0000230 9f000007 d8000007 e4000231 ...0...........1 + 0140 9f000007 e4000008 08000230 9f000008 ...........0.... + 0150 14000008 64000230 9f000000 00000000 ....d..0........ + 0160 00000000 00000000 00000000 0007ac00 ................ + 0170 0007b800 0773000a ffff1a9f 000007e4 .....s.......... + 0180 00000804 00077300 0affff1a 9f000008 ......s......... + 0190 14000008 1c000773 000affff 1a9f0000 .......s........ + 01a0 08380000 083c0007 73000aff ff1a9f00 .8...<..s....... + 01b0 00085400 00085800 0773000a ffff1a9f ..T...X..s...... + 01c0 00000000 00000000 00000000 07a80000 ................ + 01d0 07ab0014 91c97d94 0108ff1a 382491ca ......}.....8$.. + 01e0 7d940108 ff1a219f 00000000 00000000 }.....!......... + 01f0 05000000 08140000 082b0003 91cc7d00 .........+....}. + 0200 00000000 00000003 05000008 14000008 ................ + 0210 14000491 cc7d9f00 00000000 00000007 .....}.......... + 0220 00000000 00081400 00082800 0b91c87d ..........(....} + 0230 940108ff 1a341c9f 00000828 0000082b .....4.....(...+ + 0240 00015500 00000000 00000007 00000000 ..U............. + 0250 00000008 14000008 20000491 d07d9f00 ........ ....}.. + 0260 00082000 00082b00 01540000 082b0000 .. ...+..T...+.. + 0270 082c0004 91d07d9f 00000000 00000000 .,....}......... + 0280 07000000 08140000 082b0003 91cc7d00 .........+....}. + 0290 00000000 00000003 00000008 40000008 ............@... + 02a0 53002a91 cc7d9401 08ff1a48 2491cd7d S.*..}.....H$..} + 02b0 940108ff 1a402421 91ce7d94 0108ff1a .....@$!..}..... + 02c0 38242191 cf7d9401 08ff1a21 9f000000 8$!..}.....!.... + 02d0 00000000 00010300 00084000 00084000 ..........@...@. + 02e0 0491cc7d 9f000000 00000000 00010000 ...}............ + 02f0 0006f400 00070800 060c005f 5e109f00 ..........._^... + 0300 00000000 00000003 00000006 f4000006 ................ + 0310 f8000230 9f000000 00000000 00050000 ...0............ + 0320 0006f400 0006f800 051188f0 409f0000 ............@... + 0330 00000000 00000500 000006f4 000006f8 ................ + 0340 0002309f 00000000 00000000 02000000 ..0............. + 0350 06f80000 06fc0002 309f0000 00000000 ........0....... + 0360 00000400 000006f8 000006fc 00051184 ................ + 0370 f0409f00 00000000 00000004 00000006 .@.............. + 0380 f8000006 fc000230 9f000000 00000000 .......0........ + 0390 00020000 0006fc00 00070000 060c005f ..............._ + 03a0 5e109f00 00000000 00000004 00000006 ^............... + 03b0 fc000007 00000511 80f0409f 00000000 ..........@..... + 03c0 00000000 04000000 06fc0000 07000006 ................ + 03d0 0c005f5e 109f0000 00000000 00000200 .._^............ + 03e0 00000704 00000708 0002319f 00000000 ..........1..... + 03f0 00000000 04000000 07040000 07080005 ................ + 0400 118cf040 9f000000 00000000 00040000 ...@............ + 0410 00070400 00070800 02319f00 00000000 .........1...... + 0420 00000002 00000007 00000007 04000231 ...............1 + 0430 9f000000 00000000 00040000 00070000 ................ + 0440 00070400 051188f0 409f0000 00000000 ........@....... + 0450 00000400 00000700 00000704 0002319f ..............1. + 0460 00000000 00000000 02000000 07200000 ............. .. + 0470 07240005 1190f040 9f000000 00000000 .$.....@........ + 0480 00010000 00071400 00071c00 02319f00 .............1.. + 0490 00000000 00000003 00000007 14000007 ................ + 04a0 1c000511 8cf0409f 00000000 00000000 ......@......... + 04b0 03000000 07140000 071c0002 319f0000 ............1... + 04c0 00000000 00000000 00000000 00000644 ...............D + 04d0 00000650 00016f00 00066800 0006d800 ...P..o...h..... + 04e0 016f0000 07380000 074c0001 6f000000 .o...8...L..o... + 04f0 00000000 00050000 0005fc00 00064400 ..............D. + 0500 060c017d 78409f00 00000000 00000007 ...}x@.......... + 0510 00000005 fc000006 1c000230 9f000000 ...........0.... + 0520 00000000 00090000 0005fc00 00061c00 ................ + 0530 051188f0 409f0000 00000000 00000900 ....@........... + 0540 000005fc 0000061c 0002309f 00000000 ..........0..... + 0550 00000000 02000000 061c0000 06240002 .............$.. + 0560 309f0000 00000000 00000400 0000061c 0............... + 0570 00000624 00051184 f0409f00 00000000 ...$.....@...... + 0580 00000004 00000006 1c000006 24000230 ............$..0 + 0590 9f000000 00000000 00020000 00062400 ..............$. + 05a0 00062800 060c017d 78409f00 00000000 ..(....}x@...... + 05b0 00000004 00000006 24000006 28000511 ........$...(... + 05c0 80f0409f 00000000 00000000 04000000 ..@............. + 05d0 06240000 06280006 0c017d78 409f0000 .$...(....}x@... + 05e0 00000000 00000200 00000630 00000634 ...........0...4 + 05f0 0002319f 00000000 00000000 04000000 ..1............. + 0600 06300000 06340005 118cf040 9f000000 .0...4.....@.... + 0610 00000000 00040000 00063000 00063400 ..........0...4. + 0620 02319f00 00000000 00000002 00000006 .1.............. + 0630 28000006 30000231 9f000000 00000000 (...0..1........ + 0640 00040000 00062800 00063000 051188f0 ......(...0..... + 0650 409f0000 00000000 00000400 00000628 @..............( + 0660 00000630 0002319f 00000000 00000000 ...0..1......... + 0670 04000000 06440000 06480005 1190f040 .....D...H.....@ + 0680 9f000000 00000000 00020000 00074400 ..............D. + 0690 00074c00 02319f00 00000000 00000004 ..L..1.......... + 06a0 00000007 44000007 48000511 8cf0409f ....D...H.....@. + 06b0 00000000 00000000 04000000 07440000 .............D.. + 06c0 07480002 319f0000 00000000 00000000 .H..1........... + 06d0 00000000 00000678 000006d8 00015300 .......x......S. + 06e0 00073800 00073c00 01530000 08640000 ..8...<..S...d.. + 06f0 08680001 53000000 00000000 00000000 .h..S........... + 0700 00000005 58000005 6c000153 0000056c ....X...l..S...l + 0710 000005b8 00016f00 00000000 00000000 ......o......... + 0720 00000000 00055800 00057c00 01540000 ......X...|..T.. + 0730 057c0000 05b80001 6e000000 00000000 .|......n....... + 0740 00000000 00000005 58000005 8b000155 ........X......U + 0750 0000058b 000005b8 0002916c 00000000 ...........l.... + 0760 00000000 00000000 00000558 0000058b ...........X.... + 0770 00015600 00058b00 0005b800 02916800 ..V...........h. + 0780 00000000 00000000 00000000 00000303 ................ + 0790 00000000 00000000 00000000 48000153 ............H..S + 07a0 00000048 0000007c 00015900 00007c00 ...H...|..Y...|. + 07b0 0000ac00 04f30153 9f000000 ac000002 .......S........ + 07c0 b4000159 000002b4 000002bc 0004f301 ...Y............ + 07d0 539f0000 02bc0000 051c0001 59000005 S...........Y... + 07e0 1c000005 400004f3 01539f00 00000000 ....@....S...... + 07f0 00000000 00000000 03030000 00000000 ................ + 0800 00000000 00008000 01540000 00800000 .........T...... + 0810 00ac0004 f301549f 000000ac 000002b4 ......T......... + 0820 00015400 0002b400 0002bc00 04f30154 ..T............T + 0830 9f000002 bc000005 1c000154 0000051c ...........T.... + 0840 00000540 0004f301 549f0000 00000000 ...@....T....... + 0850 00000000 00000003 03000000 00000000 ................ + 0860 00000000 00980001 55000000 98000000 ........U....... + 0870 ac0004f3 01559f00 0000ac00 0002b400 .....U.......... + 0880 01550000 02b40000 02bc0004 f301559f .U............U. + 0890 000002bc 0000051c 00015500 00051c00 ..........U..... + 08a0 00054000 04f30155 9f000000 00000000 ..@....U........ + 08b0 00000000 00000000 00000303 00000000 ................ + 08c0 00000000 00000000 58000156 00000058 ........X..V...X + 08d0 00000084 00015800 00008400 0000a400 ......X......... + 08e0 0378789f 000000a4 000000ac 00038b78 .xx............x + 08f0 9f000000 ac000002 b4000158 000002b4 ...........X.... + 0900 000002bc 00038b78 9f000002 bc000005 .......x........ + 0910 1c000158 0000051c 00000540 00037878 ...X.......@..xx + 0920 9f000000 00000000 00000000 00000303 ................ + 0930 00000000 00000000 00000000 98000157 ...............W + 0940 00000098 000000ac 0004f301 579f0000 ............W... + 0950 00ac0000 02b40001 57000002 b4000002 ........W....... + 0960 bc0004f3 01579f00 0002bc00 00051c00 .....W.......... + 0970 01570000 051c0000 05400004 f301579f .W.......@....W. + 0980 00000000 00000000 01030103 02040500 ................ + 0990 01000000 02b40000 02b40003 09fd9f00 ................ + 09a0 0002d800 0002d800 0309ff9f 00000300 ................ + 09b0 00000300 0002309f 00000300 0000032c ......0........, + 09c0 0002309f 000003e4 000003e8 000309fe ..0............. + 09d0 9f000000 00000000 00000000 00000000 ................ + 09e0 00000000 00008800 0000a400 015a0000 .............Z.. + 09f0 01800000 01ac0001 56000002 20000002 ........V... ... + 0a00 90000156 00000440 000004a0 00016700 ...V...@......g. + 0a10 00051c00 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+00004153 +43494900 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000000 +00000300 +00003A48 +00003A1C +00000000 +00010100 +0001026C +0001026C +0001026C +00000000 +22D4007D diff --git a/sim/soc/readme.md b/sim/soc/readme.md new file mode 100644 index 0000000..286b3ad --- /dev/null +++ b/sim/soc/readme.md @@ -0,0 +1,52 @@ +# Testing full Litex software build + +* manually update/install litex picolib for 32BE + +* fixes for BE in A2P_4K1W.v + +* cp A2P_4K1W.v A2P_WB.v + and edit to rename to module A2P_WB + +``` +cd ../../build/litex +a2p_a2o_32.py --csr-csv csr.csv +powerpc-linux-gnu-objdump -d build/cmod7/software/bios/bios.elf > bios.d +powerpc-linux-gnu-objdump -s build/cmod7/software/bios/bios.elf > bios.s +bin2init build/cmod7/software/bios/bios.bin + +#if rtl updated +#cp a2p/verilog/A2P_WB.v ../../../sim/soc/. +#cp build/cmod7/gateware/cmod.v ../../../sim/soc/soc.v +#sed -i "s/module cmod7/module soc/" soc.v # keep consistent naming for top + +cp bios.d ../../../sim/soc/. +cp bios.s ../../../sim/soc/. +cp build/cmod7/software/bios/bios.bin.hex ../../../sim/soc/cmod7_rom.init + + +cd ../../../sim/soc +top=cmod7 +mod=soc +#if rtl updated +#sed -i "s/module $top/module $mod/" $mod.v # keep consistent naming for top + +############################################### +# build with or without tracing ############### + +dir=obj_dir_${mod} +verilator -cc --exe --CFLAGS -DUART=2593 --trace --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iunisims soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt +make -j6 -C $dir -f V$mod.mk V$mod +$dir/V$mod | tee sim_soc.txt + +dir=obj_dir_${mod}_notrace +verilator -cc --exe --CFLAGS -DUART=2593 --CFLAGS -DNO_TRACE=1 --Mdir $dir --language 1364-2001 -Wno-fatal -Wno-LITENDIAN --error-limit 1 -Iunisims soc $mod tb_litex_$mod.cpp |& tee verilator_$mod.txt +make -j6 -C $dir -f V$mod.mk V$mod +$dir/V$mod + +################################################ + + +vcd2fst a2plitex.vcd soc.fst +rm a2p_soc.vcd +gtkwave soc.fst soc.gtkw +``` \ No newline at end of file diff --git a/sim/soc/soc.v b/sim/soc/soc.v new file mode 100644 index 0000000..5846b71 --- /dev/null +++ b/sim/soc/soc.v @@ -0,0 +1,1958 @@ +// ----------------------------------------------------------------------------- +// Auto-Generated by: __ _ __ _ __ +// / / (_) /____ | |/_/ +// / /__/ / __/ -_)> < +// /____/_/\__/\__/_/|_| +// Build your hardware, easily! +// https://github.com/enjoy-digital/litex +// +// Filename : cmod7.v +// Device : xc7a35t-CPG236-1 +// LiteX sha1 : 33ae301d +// Date : 2022-08-23 17:08:47 +//------------------------------------------------------------------------------ + + +//------------------------------------------------------------------------------ +// Module +//------------------------------------------------------------------------------ + +module soc ( + output reg serial_tx, + input wire serial_rx, + (* dont_touch = "true" *) input wire clk12, + output wire user_led0, + output wire user_led1, + input wire user_btn0, + input wire user_btn1 +); + + +//------------------------------------------------------------------------------ +// Signals +//------------------------------------------------------------------------------ + +reg main_basesoc_soc_rst = 1'd0; +wire main_basesoc_cpu_rst; +reg [1:0] main_basesoc_reset_storage = 2'd0; +reg main_basesoc_reset_re = 1'd0; +reg [31:0] main_basesoc_scratch_storage = 32'd305419896; +reg main_basesoc_scratch_re = 1'd0; +wire [31:0] main_basesoc_bus_errors_status; +wire main_basesoc_bus_errors_we; +reg main_basesoc_bus_errors_re = 1'd0; +wire main_basesoc_bus_error; +reg [31:0] main_basesoc_bus_errors = 32'd0; +wire main_basesoc_reset; +reg [31:0] main_basesoc_interrupt = 32'd0; +reg main_basesoc_interruptS = 1'd0; +wire [29:0] main_basesoc_ibus_adr; +wire [31:0] main_basesoc_ibus_dat_w; +wire [31:0] main_basesoc_ibus_dat_r; +wire [3:0] main_basesoc_ibus_sel; +wire main_basesoc_ibus_cyc; +wire main_basesoc_ibus_stb; +wire main_basesoc_ibus_ack; +wire main_basesoc_ibus_we; +wire [2:0] main_basesoc_ibus_cti; +wire [1:0] main_basesoc_ibus_bte; +wire main_basesoc_ibus_err; +wire [29:0] main_basesoc_dbus_adr; +wire [31:0] main_basesoc_dbus_dat_w; +wire [31:0] main_basesoc_dbus_dat_r; +wire [3:0] main_basesoc_dbus_sel; +wire main_basesoc_dbus_cyc; +wire main_basesoc_dbus_stb; +wire main_basesoc_dbus_ack; +wire main_basesoc_dbus_we; +wire [2:0] main_basesoc_dbus_cti; +wire [1:0] main_basesoc_dbus_bte; +wire main_basesoc_dbus_err; +reg [31:0] main_basesoc_a2p = 32'd0; +wire main_basesoc_tx_sink_valid; +reg main_basesoc_tx_sink_ready = 1'd0; +wire main_basesoc_tx_sink_first; +wire main_basesoc_tx_sink_last; +wire [7:0] main_basesoc_tx_sink_payload_data; +reg [7:0] main_basesoc_tx_data = 8'd0; +reg [3:0] main_basesoc_tx_count = 4'd0; +reg main_basesoc_tx_enable = 1'd0; +reg main_basesoc_tx_tick = 1'd0; +reg [31:0] main_basesoc_tx_phase = 32'd0; +reg main_basesoc_rx_source_valid = 1'd0; +wire main_basesoc_rx_source_ready; +reg main_basesoc_rx_source_first = 1'd0; +reg main_basesoc_rx_source_last = 1'd0; +reg [7:0] main_basesoc_rx_source_payload_data = 8'd0; +reg [7:0] main_basesoc_rx_data = 8'd0; +reg [3:0] main_basesoc_rx_count = 4'd0; +reg main_basesoc_rx_enable = 1'd0; +reg main_basesoc_rx_tick = 1'd0; +reg [31:0] main_basesoc_rx_phase = 32'd0; +wire main_basesoc_rx_rx; +reg main_basesoc_rx_rx_d = 1'd0; +reg main_basesoc_uart_rxtx_re = 1'd0; +wire [7:0] main_basesoc_uart_rxtx_r; +reg main_basesoc_uart_rxtx_we = 1'd0; +wire [7:0] main_basesoc_uart_rxtx_w; +wire main_basesoc_uart_txfull_status; +wire main_basesoc_uart_txfull_we; +reg main_basesoc_uart_txfull_re = 1'd0; +wire main_basesoc_uart_rxempty_status; +wire main_basesoc_uart_rxempty_we; +reg main_basesoc_uart_rxempty_re = 1'd0; +wire main_basesoc_uart_irq; +wire main_basesoc_uart_tx_status; +reg main_basesoc_uart_tx_pending = 1'd0; +wire main_basesoc_uart_tx_trigger; +reg main_basesoc_uart_tx_clear = 1'd0; +reg main_basesoc_uart_tx_trigger_d = 1'd0; +wire main_basesoc_uart_rx_status; +reg main_basesoc_uart_rx_pending = 1'd0; +wire main_basesoc_uart_rx_trigger; +reg main_basesoc_uart_rx_clear = 1'd0; +reg main_basesoc_uart_rx_trigger_d = 1'd0; +wire main_basesoc_uart_tx0; +wire main_basesoc_uart_rx0; +reg [1:0] main_basesoc_uart_status_status = 2'd0; +wire main_basesoc_uart_status_we; +reg main_basesoc_uart_status_re = 1'd0; +wire main_basesoc_uart_tx1; +wire main_basesoc_uart_rx1; +reg [1:0] main_basesoc_uart_pending_status = 2'd0; +wire main_basesoc_uart_pending_we; +reg main_basesoc_uart_pending_re = 1'd0; +reg [1:0] main_basesoc_uart_pending_r = 2'd0; +wire main_basesoc_uart_tx2; +wire main_basesoc_uart_rx2; +reg [1:0] main_basesoc_uart_enable_storage = 2'd0; +reg main_basesoc_uart_enable_re = 1'd0; +wire main_basesoc_uart_txempty_status; +wire main_basesoc_uart_txempty_we; +reg main_basesoc_uart_txempty_re = 1'd0; +wire main_basesoc_uart_rxfull_status; +wire main_basesoc_uart_rxfull_we; +reg main_basesoc_uart_rxfull_re = 1'd0; +wire main_basesoc_uart_uart_sink_valid; +wire main_basesoc_uart_uart_sink_ready; +wire main_basesoc_uart_uart_sink_first; +wire main_basesoc_uart_uart_sink_last; +wire [7:0] main_basesoc_uart_uart_sink_payload_data; +wire main_basesoc_uart_uart_source_valid; +wire main_basesoc_uart_uart_source_ready; +wire main_basesoc_uart_uart_source_first; +wire main_basesoc_uart_uart_source_last; +wire [7:0] main_basesoc_uart_uart_source_payload_data; +wire main_basesoc_uart_tx_fifo_sink_valid; +wire main_basesoc_uart_tx_fifo_sink_ready; +reg main_basesoc_uart_tx_fifo_sink_first = 1'd0; +reg main_basesoc_uart_tx_fifo_sink_last = 1'd0; +wire [7:0] main_basesoc_uart_tx_fifo_sink_payload_data; +wire main_basesoc_uart_tx_fifo_source_valid; +wire main_basesoc_uart_tx_fifo_source_ready; +wire main_basesoc_uart_tx_fifo_source_first; +wire main_basesoc_uart_tx_fifo_source_last; +wire [7:0] main_basesoc_uart_tx_fifo_source_payload_data; +wire main_basesoc_uart_tx_fifo_re; +reg main_basesoc_uart_tx_fifo_readable = 1'd0; +wire main_basesoc_uart_tx_fifo_syncfifo_we; +wire main_basesoc_uart_tx_fifo_syncfifo_writable; +wire main_basesoc_uart_tx_fifo_syncfifo_re; +wire main_basesoc_uart_tx_fifo_syncfifo_readable; +wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_din; +wire [9:0] main_basesoc_uart_tx_fifo_syncfifo_dout; +reg [4:0] main_basesoc_uart_tx_fifo_level0 = 5'd0; +reg main_basesoc_uart_tx_fifo_replace = 1'd0; +reg [3:0] main_basesoc_uart_tx_fifo_produce = 4'd0; +reg [3:0] main_basesoc_uart_tx_fifo_consume = 4'd0; +reg [3:0] main_basesoc_uart_tx_fifo_wrport_adr = 4'd0; +wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_r; +wire main_basesoc_uart_tx_fifo_wrport_we; +wire [9:0] main_basesoc_uart_tx_fifo_wrport_dat_w; +wire main_basesoc_uart_tx_fifo_do_read; +wire [3:0] main_basesoc_uart_tx_fifo_rdport_adr; +wire [9:0] main_basesoc_uart_tx_fifo_rdport_dat_r; +wire main_basesoc_uart_tx_fifo_rdport_re; +wire [4:0] main_basesoc_uart_tx_fifo_level1; +wire [7:0] main_basesoc_uart_tx_fifo_fifo_in_payload_data; +wire main_basesoc_uart_tx_fifo_fifo_in_first; +wire main_basesoc_uart_tx_fifo_fifo_in_last; +wire [7:0] main_basesoc_uart_tx_fifo_fifo_out_payload_data; +wire main_basesoc_uart_tx_fifo_fifo_out_first; +wire main_basesoc_uart_tx_fifo_fifo_out_last; +wire main_basesoc_uart_rx_fifo_sink_valid; +wire main_basesoc_uart_rx_fifo_sink_ready; +wire main_basesoc_uart_rx_fifo_sink_first; +wire main_basesoc_uart_rx_fifo_sink_last; +wire [7:0] main_basesoc_uart_rx_fifo_sink_payload_data; +wire main_basesoc_uart_rx_fifo_source_valid; +wire main_basesoc_uart_rx_fifo_source_ready; +wire main_basesoc_uart_rx_fifo_source_first; +wire main_basesoc_uart_rx_fifo_source_last; +wire [7:0] main_basesoc_uart_rx_fifo_source_payload_data; +wire main_basesoc_uart_rx_fifo_re; +reg main_basesoc_uart_rx_fifo_readable = 1'd0; +wire main_basesoc_uart_rx_fifo_syncfifo_we; +wire main_basesoc_uart_rx_fifo_syncfifo_writable; +wire main_basesoc_uart_rx_fifo_syncfifo_re; +wire main_basesoc_uart_rx_fifo_syncfifo_readable; +wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_din; +wire [9:0] main_basesoc_uart_rx_fifo_syncfifo_dout; +reg [4:0] main_basesoc_uart_rx_fifo_level0 = 5'd0; +reg main_basesoc_uart_rx_fifo_replace = 1'd0; +reg [3:0] main_basesoc_uart_rx_fifo_produce = 4'd0; +reg [3:0] main_basesoc_uart_rx_fifo_consume = 4'd0; +reg [3:0] main_basesoc_uart_rx_fifo_wrport_adr = 4'd0; +wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_r; +wire main_basesoc_uart_rx_fifo_wrport_we; +wire [9:0] main_basesoc_uart_rx_fifo_wrport_dat_w; +wire main_basesoc_uart_rx_fifo_do_read; +wire [3:0] main_basesoc_uart_rx_fifo_rdport_adr; +wire [9:0] main_basesoc_uart_rx_fifo_rdport_dat_r; +wire main_basesoc_uart_rx_fifo_rdport_re; +wire [4:0] main_basesoc_uart_rx_fifo_level1; +wire [7:0] main_basesoc_uart_rx_fifo_fifo_in_payload_data; +wire main_basesoc_uart_rx_fifo_fifo_in_first; +wire main_basesoc_uart_rx_fifo_fifo_in_last; +wire [7:0] main_basesoc_uart_rx_fifo_fifo_out_payload_data; +wire main_basesoc_uart_rx_fifo_fifo_out_first; +wire main_basesoc_uart_rx_fifo_fifo_out_last; +reg [31:0] main_basesoc_timer_load_storage = 32'd0; +reg main_basesoc_timer_load_re = 1'd0; +reg [31:0] main_basesoc_timer_reload_storage = 32'd0; +reg main_basesoc_timer_reload_re = 1'd0; +reg main_basesoc_timer_en_storage = 1'd0; +reg main_basesoc_timer_en_re = 1'd0; +reg main_basesoc_timer_update_value_storage = 1'd0; +reg main_basesoc_timer_update_value_re = 1'd0; +reg [31:0] main_basesoc_timer_value_status = 32'd0; +wire main_basesoc_timer_value_we; +reg main_basesoc_timer_value_re = 1'd0; +wire main_basesoc_timer_irq; +wire main_basesoc_timer_zero_status; +reg main_basesoc_timer_zero_pending = 1'd0; +wire main_basesoc_timer_zero_trigger; +reg main_basesoc_timer_zero_clear = 1'd0; +reg main_basesoc_timer_zero_trigger_d = 1'd0; +wire main_basesoc_timer_zero0; +wire main_basesoc_timer_status_status; +wire main_basesoc_timer_status_we; +reg main_basesoc_timer_status_re = 1'd0; +wire main_basesoc_timer_zero1; +wire main_basesoc_timer_pending_status; +wire main_basesoc_timer_pending_we; +reg main_basesoc_timer_pending_re = 1'd0; +reg main_basesoc_timer_pending_r = 1'd0; +wire main_basesoc_timer_zero2; +reg main_basesoc_timer_enable_storage = 1'd0; +reg main_basesoc_timer_enable_re = 1'd0; +reg [31:0] main_basesoc_timer_value = 32'd0; +reg main_crg_rst = 1'd0; +(* dont_touch = "true" *) wire sys_clk; +wire sys_rst; +wire sys2x_clk; +wire idelay_clk; +wire idelay_rst; +wire main_crg_reset; +reg main_crg_power_down = 1'd0; +wire main_crg_locked; +(* dont_touch = "true" *) wire main_crg_clkin; +wire main_crg_clkout0; +wire main_crg_clkout_buf0; +wire main_crg_clkout1; +wire main_crg_clkout_buf1; +wire main_crg_clkout2; +wire main_crg_clkout_buf2; +reg [3:0] main_crg_reset_counter = 4'd15; +reg main_crg_ic_reset = 1'd1; +wire [29:0] main_basesoc_ram_bus_adr; +wire [31:0] main_basesoc_ram_bus_dat_w; +wire [31:0] main_basesoc_ram_bus_dat_r; +wire [3:0] main_basesoc_ram_bus_sel; +wire main_basesoc_ram_bus_cyc; +wire main_basesoc_ram_bus_stb; +reg main_basesoc_ram_bus_ack = 1'd0; +wire main_basesoc_ram_bus_we; +wire [2:0] main_basesoc_ram_bus_cti; +wire [1:0] main_basesoc_ram_bus_bte; +reg main_basesoc_ram_bus_err = 1'd0; +reg main_basesoc_adr_burst = 1'd0; +wire [13:0] main_basesoc_adr; +wire [31:0] main_basesoc_dat_r; +wire [29:0] main_basesoc_interface0_ram_bus_adr; +wire [31:0] main_basesoc_interface0_ram_bus_dat_w; +wire [31:0] main_basesoc_interface0_ram_bus_dat_r; +wire [3:0] main_basesoc_interface0_ram_bus_sel; +wire main_basesoc_interface0_ram_bus_cyc; +wire main_basesoc_interface0_ram_bus_stb; +reg main_basesoc_interface0_ram_bus_ack = 1'd0; +wire main_basesoc_interface0_ram_bus_we; +wire [2:0] main_basesoc_interface0_ram_bus_cti; +wire [1:0] main_basesoc_interface0_ram_bus_bte; +reg main_basesoc_interface0_ram_bus_err = 1'd0; +reg main_basesoc_sram0_adr_burst = 1'd0; +wire [13:0] main_basesoc_sram0_adr; +wire [31:0] main_basesoc_sram0_dat_r; +reg [3:0] main_basesoc_sram0_we = 4'd0; +wire [31:0] main_basesoc_sram0_dat_w; +wire [29:0] main_basesoc_interface1_ram_bus_adr; +wire [31:0] main_basesoc_interface1_ram_bus_dat_w; +wire [31:0] main_basesoc_interface1_ram_bus_dat_r; +wire [3:0] main_basesoc_interface1_ram_bus_sel; +wire main_basesoc_interface1_ram_bus_cyc; +wire main_basesoc_interface1_ram_bus_stb; +reg main_basesoc_interface1_ram_bus_ack = 1'd0; +wire main_basesoc_interface1_ram_bus_we; +wire [2:0] main_basesoc_interface1_ram_bus_cti; +wire [1:0] main_basesoc_interface1_ram_bus_bte; +reg main_basesoc_interface1_ram_bus_err = 1'd0; +reg main_basesoc_sram1_adr_burst = 1'd0; +wire [21:0] main_basesoc_sram1_adr; +wire [31:0] main_basesoc_sram1_dat_r; +reg [3:0] main_basesoc_sram1_we = 4'd0; +wire [31:0] main_basesoc_sram1_dat_w; +reg [1:0] main_leds_storage = 2'd0; +reg main_leds_re = 1'd0; +reg [1:0] main_leds_chaser = 2'd0; +reg main_leds_mode = 1'd0; +wire main_leds_wait; +wire main_leds_done; +reg [24:0] main_leds_count = 25'd25000000; +reg [1:0] main_leds_leds = 2'd0; +wire [1:0] main_buttons_status; +wire main_buttons_we; +reg main_buttons_re = 1'd0; +reg [13:0] builder_basesoc_adr = 14'd0; +reg builder_basesoc_we = 1'd0; +reg [31:0] builder_basesoc_dat_w = 32'd0; +wire [31:0] builder_basesoc_dat_r; +wire [29:0] builder_basesoc_wishbone_adr; +wire [31:0] builder_basesoc_wishbone_dat_w; +reg [31:0] builder_basesoc_wishbone_dat_r = 32'd0; +wire [3:0] builder_basesoc_wishbone_sel; +wire builder_basesoc_wishbone_cyc; +wire builder_basesoc_wishbone_stb; +reg builder_basesoc_wishbone_ack = 1'd0; +wire builder_basesoc_wishbone_we; +wire [2:0] builder_basesoc_wishbone_cti; +wire [1:0] builder_basesoc_wishbone_bte; +reg builder_basesoc_wishbone_err = 1'd0; +wire [29:0] builder_shared_adr; +wire [31:0] builder_shared_dat_w; +reg [31:0] builder_shared_dat_r = 32'd0; +wire [3:0] builder_shared_sel; +wire builder_shared_cyc; +wire builder_shared_stb; +reg builder_shared_ack = 1'd0; +wire builder_shared_we; +wire [2:0] builder_shared_cti; +wire [1:0] builder_shared_bte; +wire builder_shared_err; +wire [1:0] builder_request; +reg builder_grant = 1'd0; +reg [3:0] builder_slave_sel = 4'd0; +reg [3:0] builder_slave_sel_r = 4'd0; +reg builder_error = 1'd0; +wire builder_wait; +wire builder_done; +reg [19:0] builder_count = 20'd1000000; +wire [13:0] builder_csr_bankarray_interface0_bank_bus_adr; +wire builder_csr_bankarray_interface0_bank_bus_we; +wire [31:0] builder_csr_bankarray_interface0_bank_bus_dat_w; +reg [31:0] builder_csr_bankarray_interface0_bank_bus_dat_r = 32'd0; +reg builder_csr_bankarray_csrbank0_in_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank0_in_r; +reg builder_csr_bankarray_csrbank0_in_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank0_in_w; +wire builder_csr_bankarray_csrbank0_sel; +wire [13:0] builder_csr_bankarray_interface1_bank_bus_adr; +wire builder_csr_bankarray_interface1_bank_bus_we; +wire [31:0] builder_csr_bankarray_interface1_bank_bus_dat_w; +reg [31:0] builder_csr_bankarray_interface1_bank_bus_dat_r = 32'd0; +reg builder_csr_bankarray_csrbank1_reset0_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank1_reset0_r; +reg builder_csr_bankarray_csrbank1_reset0_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank1_reset0_w; +reg builder_csr_bankarray_csrbank1_scratch0_re = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank1_scratch0_r; +reg builder_csr_bankarray_csrbank1_scratch0_we = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank1_scratch0_w; +reg builder_csr_bankarray_csrbank1_bus_errors_re = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank1_bus_errors_r; +reg builder_csr_bankarray_csrbank1_bus_errors_we = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank1_bus_errors_w; +wire builder_csr_bankarray_csrbank1_sel; +wire [13:0] builder_csr_bankarray_sram_bus_adr; +wire builder_csr_bankarray_sram_bus_we; +wire [31:0] builder_csr_bankarray_sram_bus_dat_w; +reg [31:0] builder_csr_bankarray_sram_bus_dat_r = 32'd0; +wire [4:0] builder_csr_bankarray_adr; +wire [7:0] builder_csr_bankarray_dat_r; +wire builder_csr_bankarray_sel; +reg builder_csr_bankarray_sel_r = 1'd0; +wire [13:0] builder_csr_bankarray_interface2_bank_bus_adr; +wire builder_csr_bankarray_interface2_bank_bus_we; +wire [31:0] builder_csr_bankarray_interface2_bank_bus_dat_w; +reg [31:0] builder_csr_bankarray_interface2_bank_bus_dat_r = 32'd0; +reg builder_csr_bankarray_csrbank2_out0_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank2_out0_r; +reg builder_csr_bankarray_csrbank2_out0_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank2_out0_w; +wire builder_csr_bankarray_csrbank2_sel; +wire [13:0] builder_csr_bankarray_interface3_bank_bus_adr; +wire builder_csr_bankarray_interface3_bank_bus_we; +wire [31:0] builder_csr_bankarray_interface3_bank_bus_dat_w; +reg [31:0] builder_csr_bankarray_interface3_bank_bus_dat_r = 32'd0; +reg builder_csr_bankarray_csrbank3_load0_re = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_load0_r; +reg builder_csr_bankarray_csrbank3_load0_we = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_load0_w; +reg builder_csr_bankarray_csrbank3_reload0_re = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_reload0_r; +reg builder_csr_bankarray_csrbank3_reload0_we = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_reload0_w; +reg builder_csr_bankarray_csrbank3_en0_re = 1'd0; +wire builder_csr_bankarray_csrbank3_en0_r; +reg builder_csr_bankarray_csrbank3_en0_we = 1'd0; +wire builder_csr_bankarray_csrbank3_en0_w; +reg builder_csr_bankarray_csrbank3_update_value0_re = 1'd0; +wire builder_csr_bankarray_csrbank3_update_value0_r; +reg builder_csr_bankarray_csrbank3_update_value0_we = 1'd0; +wire builder_csr_bankarray_csrbank3_update_value0_w; +reg builder_csr_bankarray_csrbank3_value_re = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_value_r; +reg builder_csr_bankarray_csrbank3_value_we = 1'd0; +wire [31:0] builder_csr_bankarray_csrbank3_value_w; +reg builder_csr_bankarray_csrbank3_ev_status_re = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_status_r; +reg builder_csr_bankarray_csrbank3_ev_status_we = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_status_w; +reg builder_csr_bankarray_csrbank3_ev_pending_re = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_pending_r; +reg builder_csr_bankarray_csrbank3_ev_pending_we = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_pending_w; +reg builder_csr_bankarray_csrbank3_ev_enable0_re = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_enable0_r; +reg builder_csr_bankarray_csrbank3_ev_enable0_we = 1'd0; +wire builder_csr_bankarray_csrbank3_ev_enable0_w; +wire builder_csr_bankarray_csrbank3_sel; +wire [13:0] builder_csr_bankarray_interface4_bank_bus_adr; +wire builder_csr_bankarray_interface4_bank_bus_we; +wire [31:0] builder_csr_bankarray_interface4_bank_bus_dat_w; +reg [31:0] builder_csr_bankarray_interface4_bank_bus_dat_r = 32'd0; +reg builder_csr_bankarray_csrbank4_txfull_re = 1'd0; +wire builder_csr_bankarray_csrbank4_txfull_r; +reg builder_csr_bankarray_csrbank4_txfull_we = 1'd0; +wire builder_csr_bankarray_csrbank4_txfull_w; +reg builder_csr_bankarray_csrbank4_rxempty_re = 1'd0; +wire builder_csr_bankarray_csrbank4_rxempty_r; +reg builder_csr_bankarray_csrbank4_rxempty_we = 1'd0; +wire builder_csr_bankarray_csrbank4_rxempty_w; +reg builder_csr_bankarray_csrbank4_ev_status_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_status_r; +reg builder_csr_bankarray_csrbank4_ev_status_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_status_w; +reg builder_csr_bankarray_csrbank4_ev_pending_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_pending_r; +reg builder_csr_bankarray_csrbank4_ev_pending_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_pending_w; +reg builder_csr_bankarray_csrbank4_ev_enable0_re = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_enable0_r; +reg builder_csr_bankarray_csrbank4_ev_enable0_we = 1'd0; +wire [1:0] builder_csr_bankarray_csrbank4_ev_enable0_w; +reg builder_csr_bankarray_csrbank4_txempty_re = 1'd0; +wire builder_csr_bankarray_csrbank4_txempty_r; +reg builder_csr_bankarray_csrbank4_txempty_we = 1'd0; +wire builder_csr_bankarray_csrbank4_txempty_w; +reg builder_csr_bankarray_csrbank4_rxfull_re = 1'd0; +wire builder_csr_bankarray_csrbank4_rxfull_r; +reg builder_csr_bankarray_csrbank4_rxfull_we = 1'd0; +wire builder_csr_bankarray_csrbank4_rxfull_w; +wire builder_csr_bankarray_csrbank4_sel; +wire [13:0] builder_csr_interconnect_adr; +wire builder_csr_interconnect_we; +wire [31:0] builder_csr_interconnect_dat_w; +wire [31:0] builder_csr_interconnect_dat_r; +reg builder_basesoc_rs232phytx_state = 1'd0; +reg builder_basesoc_rs232phytx_next_state = 1'd0; +reg [3:0] main_basesoc_tx_count_rs232phytx_next_value0 = 4'd0; +reg main_basesoc_tx_count_rs232phytx_next_value_ce0 = 1'd0; +reg main_basesoc_serial_tx_rs232phytx_next_value1 = 1'd0; +reg main_basesoc_serial_tx_rs232phytx_next_value_ce1 = 1'd0; +reg [7:0] main_basesoc_tx_data_rs232phytx_next_value2 = 8'd0; +reg main_basesoc_tx_data_rs232phytx_next_value_ce2 = 1'd0; +reg builder_basesoc_rs232phyrx_state = 1'd0; +reg builder_basesoc_rs232phyrx_next_state = 1'd0; +reg [3:0] main_basesoc_rx_count_rs232phyrx_next_value0 = 4'd0; +reg main_basesoc_rx_count_rs232phyrx_next_value_ce0 = 1'd0; +reg [7:0] main_basesoc_rx_data_rs232phyrx_next_value1 = 8'd0; +reg main_basesoc_rx_data_rs232phyrx_next_value_ce1 = 1'd0; +wire builder_basesoc_reset0; +wire builder_basesoc_reset1; +wire builder_basesoc_reset2; +wire builder_basesoc_reset3; +wire builder_basesoc_reset4; +wire builder_basesoc_reset5; +wire builder_basesoc_reset6; +wire builder_basesoc_reset7; +wire builder_basesoc_mmcm_fb; +reg builder_basesoc_state = 1'd0; +reg builder_basesoc_next_state = 1'd0; +reg [29:0] builder_array_muxed0 = 30'd0; +reg [31:0] builder_array_muxed1 = 32'd0; +reg [3:0] builder_array_muxed2 = 4'd0; +reg builder_array_muxed3 = 1'd0; +reg builder_array_muxed4 = 1'd0; +reg builder_array_muxed5 = 1'd0; +reg [2:0] builder_array_muxed6 = 3'd0; +reg [1:0] builder_array_muxed7 = 2'd0; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs0 = 1'd0; +(* async_reg = "true", dont_touch = "true" *) reg builder_xilinxmultiregimpl0_regs1 = 1'd0; +wire builder_xilinxasyncresetsynchronizerimpl0; +wire builder_xilinxasyncresetsynchronizerimpl0_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1; +wire builder_xilinxasyncresetsynchronizerimpl1_rst_meta; +wire builder_xilinxasyncresetsynchronizerimpl1_expr; +wire builder_xilinxasyncresetsynchronizerimpl2; +wire builder_xilinxasyncresetsynchronizerimpl2_rst_meta; +(* async_reg = "true", mr_ff = "true", dont_touch = "true" *) reg [1:0] builder_xilinxmultiregimpl1_regs0 = 2'd0; +(* async_reg = "true", dont_touch = "true" *) reg [1:0] builder_xilinxmultiregimpl1_regs1 = 2'd0; +wire builder_xilinxmultiregimpl1; + +//------------------------------------------------------------------------------ +// Combinatorial Logic +//------------------------------------------------------------------------------ + +assign main_basesoc_reset = (main_basesoc_soc_rst | main_basesoc_cpu_rst); +always @(*) begin + main_crg_rst <= 1'd0; + if (main_basesoc_soc_rst) begin + main_crg_rst <= 1'd1; + end +end +assign main_basesoc_bus_error = builder_error; +always @(*) begin + main_basesoc_interrupt <= 32'd0; + main_basesoc_interrupt[1] <= main_basesoc_timer_irq; + main_basesoc_interrupt[0] <= main_basesoc_uart_irq; +end +assign main_basesoc_bus_errors_status = main_basesoc_bus_errors; +always @(*) begin + main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd0; + main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd0; + main_basesoc_tx_sink_ready <= 1'd0; + main_basesoc_tx_data_rs232phytx_next_value2 <= 8'd0; + main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd0; + main_basesoc_tx_enable <= 1'd0; + builder_basesoc_rs232phytx_next_state <= 1'd0; + main_basesoc_tx_count_rs232phytx_next_value0 <= 4'd0; + main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd0; + builder_basesoc_rs232phytx_next_state <= builder_basesoc_rs232phytx_state; + case (builder_basesoc_rs232phytx_state) + 1'd1: begin + main_basesoc_tx_enable <= 1'd1; + if (main_basesoc_tx_tick) begin + main_basesoc_serial_tx_rs232phytx_next_value1 <= main_basesoc_tx_data; + main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; + main_basesoc_tx_count_rs232phytx_next_value0 <= (main_basesoc_tx_count + 1'd1); + main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd1; + main_basesoc_tx_data_rs232phytx_next_value2 <= {1'd1, main_basesoc_tx_data[7:1]}; + main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd1; + if ((main_basesoc_tx_count == 4'd9)) begin + main_basesoc_tx_sink_ready <= 1'd1; + builder_basesoc_rs232phytx_next_state <= 1'd0; + end + end + end + default: begin + main_basesoc_tx_count_rs232phytx_next_value0 <= 1'd0; + main_basesoc_tx_count_rs232phytx_next_value_ce0 <= 1'd1; + main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd1; + main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; + if (main_basesoc_tx_sink_valid) begin + main_basesoc_serial_tx_rs232phytx_next_value1 <= 1'd0; + main_basesoc_serial_tx_rs232phytx_next_value_ce1 <= 1'd1; + main_basesoc_tx_data_rs232phytx_next_value2 <= main_basesoc_tx_sink_payload_data; + main_basesoc_tx_data_rs232phytx_next_value_ce2 <= 1'd1; + builder_basesoc_rs232phytx_next_state <= 1'd1; + end + end + endcase +end +always @(*) begin + main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd0; + main_basesoc_rx_data_rs232phyrx_next_value1 <= 8'd0; + main_basesoc_rx_source_valid <= 1'd0; + main_basesoc_rx_data_rs232phyrx_next_value_ce1 <= 1'd0; + main_basesoc_rx_source_payload_data <= 8'd0; + main_basesoc_rx_enable <= 1'd0; + builder_basesoc_rs232phyrx_next_state <= 1'd0; + main_basesoc_rx_count_rs232phyrx_next_value0 <= 4'd0; + builder_basesoc_rs232phyrx_next_state <= builder_basesoc_rs232phyrx_state; + case (builder_basesoc_rs232phyrx_state) + 1'd1: begin + main_basesoc_rx_enable <= 1'd1; + if (main_basesoc_rx_tick) begin + main_basesoc_rx_count_rs232phyrx_next_value0 <= (main_basesoc_rx_count + 1'd1); + main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd1; + main_basesoc_rx_data_rs232phyrx_next_value1 <= {main_basesoc_rx_rx, main_basesoc_rx_data[7:1]}; + main_basesoc_rx_data_rs232phyrx_next_value_ce1 <= 1'd1; + if ((main_basesoc_rx_count == 4'd9)) begin + main_basesoc_rx_source_valid <= (main_basesoc_rx_rx == 1'd1); + main_basesoc_rx_source_payload_data <= main_basesoc_rx_data; + builder_basesoc_rs232phyrx_next_state <= 1'd0; + end + end + end + default: begin + main_basesoc_rx_count_rs232phyrx_next_value0 <= 1'd0; + main_basesoc_rx_count_rs232phyrx_next_value_ce0 <= 1'd1; + if (((main_basesoc_rx_rx == 1'd0) & (main_basesoc_rx_rx_d == 1'd1))) begin + builder_basesoc_rs232phyrx_next_state <= 1'd1; + end + end + endcase +end +assign main_basesoc_uart_uart_sink_valid = main_basesoc_rx_source_valid; +assign main_basesoc_rx_source_ready = main_basesoc_uart_uart_sink_ready; +assign main_basesoc_uart_uart_sink_first = main_basesoc_rx_source_first; +assign main_basesoc_uart_uart_sink_last = main_basesoc_rx_source_last; +assign main_basesoc_uart_uart_sink_payload_data = main_basesoc_rx_source_payload_data; +assign main_basesoc_tx_sink_valid = main_basesoc_uart_uart_source_valid; +assign main_basesoc_uart_uart_source_ready = main_basesoc_tx_sink_ready; +assign main_basesoc_tx_sink_first = main_basesoc_uart_uart_source_first; +assign main_basesoc_tx_sink_last = main_basesoc_uart_uart_source_last; +assign main_basesoc_tx_sink_payload_data = main_basesoc_uart_uart_source_payload_data; +assign main_basesoc_uart_tx_fifo_sink_valid = main_basesoc_uart_rxtx_re; +assign main_basesoc_uart_tx_fifo_sink_payload_data = main_basesoc_uart_rxtx_r; +assign main_basesoc_uart_uart_source_valid = main_basesoc_uart_tx_fifo_source_valid; +assign main_basesoc_uart_tx_fifo_source_ready = main_basesoc_uart_uart_source_ready; +assign main_basesoc_uart_uart_source_first = main_basesoc_uart_tx_fifo_source_first; +assign main_basesoc_uart_uart_source_last = main_basesoc_uart_tx_fifo_source_last; +assign main_basesoc_uart_uart_source_payload_data = main_basesoc_uart_tx_fifo_source_payload_data; +assign main_basesoc_uart_txfull_status = (~main_basesoc_uart_tx_fifo_sink_ready); +assign main_basesoc_uart_txempty_status = (~main_basesoc_uart_tx_fifo_source_valid); +assign main_basesoc_uart_tx_trigger = main_basesoc_uart_tx_fifo_sink_ready; +assign main_basesoc_uart_rx_fifo_sink_valid = main_basesoc_uart_uart_sink_valid; +assign main_basesoc_uart_uart_sink_ready = main_basesoc_uart_rx_fifo_sink_ready; +assign main_basesoc_uart_rx_fifo_sink_first = main_basesoc_uart_uart_sink_first; +assign main_basesoc_uart_rx_fifo_sink_last = main_basesoc_uart_uart_sink_last; +assign main_basesoc_uart_rx_fifo_sink_payload_data = main_basesoc_uart_uart_sink_payload_data; +assign main_basesoc_uart_rxtx_w = main_basesoc_uart_rx_fifo_source_payload_data; +assign main_basesoc_uart_rx_fifo_source_ready = (main_basesoc_uart_rx_clear | (1'd0 & main_basesoc_uart_rxtx_we)); +assign main_basesoc_uart_rxempty_status = (~main_basesoc_uart_rx_fifo_source_valid); +assign main_basesoc_uart_rxfull_status = (~main_basesoc_uart_rx_fifo_sink_ready); +assign main_basesoc_uart_rx_trigger = main_basesoc_uart_rx_fifo_source_valid; +assign main_basesoc_uart_tx0 = main_basesoc_uart_tx_status; +assign main_basesoc_uart_tx1 = main_basesoc_uart_tx_pending; +always @(*) begin + main_basesoc_uart_tx_clear <= 1'd0; + if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[0])) begin + main_basesoc_uart_tx_clear <= 1'd1; + end +end +assign main_basesoc_uart_rx0 = main_basesoc_uart_rx_status; +assign main_basesoc_uart_rx1 = main_basesoc_uart_rx_pending; +always @(*) begin + main_basesoc_uart_rx_clear <= 1'd0; + if ((main_basesoc_uart_pending_re & main_basesoc_uart_pending_r[1])) begin + main_basesoc_uart_rx_clear <= 1'd1; + end +end +assign main_basesoc_uart_irq = ((main_basesoc_uart_pending_status[0] & main_basesoc_uart_enable_storage[0]) | (main_basesoc_uart_pending_status[1] & main_basesoc_uart_enable_storage[1])); +assign main_basesoc_uart_tx_status = main_basesoc_uart_tx_trigger; +assign main_basesoc_uart_rx_status = main_basesoc_uart_rx_trigger; +assign main_basesoc_uart_tx_fifo_syncfifo_din = {main_basesoc_uart_tx_fifo_fifo_in_last, main_basesoc_uart_tx_fifo_fifo_in_first, main_basesoc_uart_tx_fifo_fifo_in_payload_data}; +assign {main_basesoc_uart_tx_fifo_fifo_out_last, main_basesoc_uart_tx_fifo_fifo_out_first, main_basesoc_uart_tx_fifo_fifo_out_payload_data} = main_basesoc_uart_tx_fifo_syncfifo_dout; +assign main_basesoc_uart_tx_fifo_sink_ready = main_basesoc_uart_tx_fifo_syncfifo_writable; +assign main_basesoc_uart_tx_fifo_syncfifo_we = main_basesoc_uart_tx_fifo_sink_valid; +assign main_basesoc_uart_tx_fifo_fifo_in_first = main_basesoc_uart_tx_fifo_sink_first; +assign main_basesoc_uart_tx_fifo_fifo_in_last = main_basesoc_uart_tx_fifo_sink_last; +assign main_basesoc_uart_tx_fifo_fifo_in_payload_data = main_basesoc_uart_tx_fifo_sink_payload_data; +assign main_basesoc_uart_tx_fifo_source_valid = main_basesoc_uart_tx_fifo_readable; +assign main_basesoc_uart_tx_fifo_source_first = main_basesoc_uart_tx_fifo_fifo_out_first; +assign main_basesoc_uart_tx_fifo_source_last = main_basesoc_uart_tx_fifo_fifo_out_last; +assign main_basesoc_uart_tx_fifo_source_payload_data = main_basesoc_uart_tx_fifo_fifo_out_payload_data; +assign main_basesoc_uart_tx_fifo_re = main_basesoc_uart_tx_fifo_source_ready; +assign main_basesoc_uart_tx_fifo_syncfifo_re = (main_basesoc_uart_tx_fifo_syncfifo_readable & ((~main_basesoc_uart_tx_fifo_readable) | main_basesoc_uart_tx_fifo_re)); +assign main_basesoc_uart_tx_fifo_level1 = (main_basesoc_uart_tx_fifo_level0 + main_basesoc_uart_tx_fifo_readable); +always @(*) begin + main_basesoc_uart_tx_fifo_wrport_adr <= 4'd0; + if (main_basesoc_uart_tx_fifo_replace) begin + main_basesoc_uart_tx_fifo_wrport_adr <= (main_basesoc_uart_tx_fifo_produce - 1'd1); + end else begin + main_basesoc_uart_tx_fifo_wrport_adr <= main_basesoc_uart_tx_fifo_produce; + end +end +assign main_basesoc_uart_tx_fifo_wrport_dat_w = main_basesoc_uart_tx_fifo_syncfifo_din; +assign main_basesoc_uart_tx_fifo_wrport_we = (main_basesoc_uart_tx_fifo_syncfifo_we & (main_basesoc_uart_tx_fifo_syncfifo_writable | main_basesoc_uart_tx_fifo_replace)); +assign main_basesoc_uart_tx_fifo_do_read = (main_basesoc_uart_tx_fifo_syncfifo_readable & main_basesoc_uart_tx_fifo_syncfifo_re); +assign main_basesoc_uart_tx_fifo_rdport_adr = main_basesoc_uart_tx_fifo_consume; +assign main_basesoc_uart_tx_fifo_syncfifo_dout = main_basesoc_uart_tx_fifo_rdport_dat_r; +assign main_basesoc_uart_tx_fifo_rdport_re = main_basesoc_uart_tx_fifo_do_read; +assign main_basesoc_uart_tx_fifo_syncfifo_writable = (main_basesoc_uart_tx_fifo_level0 != 5'd16); +assign main_basesoc_uart_tx_fifo_syncfifo_readable = (main_basesoc_uart_tx_fifo_level0 != 1'd0); +assign main_basesoc_uart_rx_fifo_syncfifo_din = {main_basesoc_uart_rx_fifo_fifo_in_last, main_basesoc_uart_rx_fifo_fifo_in_first, main_basesoc_uart_rx_fifo_fifo_in_payload_data}; +assign {main_basesoc_uart_rx_fifo_fifo_out_last, main_basesoc_uart_rx_fifo_fifo_out_first, main_basesoc_uart_rx_fifo_fifo_out_payload_data} = main_basesoc_uart_rx_fifo_syncfifo_dout; +assign main_basesoc_uart_rx_fifo_sink_ready = main_basesoc_uart_rx_fifo_syncfifo_writable; +assign main_basesoc_uart_rx_fifo_syncfifo_we = main_basesoc_uart_rx_fifo_sink_valid; +assign main_basesoc_uart_rx_fifo_fifo_in_first = main_basesoc_uart_rx_fifo_sink_first; +assign main_basesoc_uart_rx_fifo_fifo_in_last = main_basesoc_uart_rx_fifo_sink_last; +assign main_basesoc_uart_rx_fifo_fifo_in_payload_data = main_basesoc_uart_rx_fifo_sink_payload_data; +assign main_basesoc_uart_rx_fifo_source_valid = main_basesoc_uart_rx_fifo_readable; +assign main_basesoc_uart_rx_fifo_source_first = main_basesoc_uart_rx_fifo_fifo_out_first; +assign main_basesoc_uart_rx_fifo_source_last = main_basesoc_uart_rx_fifo_fifo_out_last; +assign main_basesoc_uart_rx_fifo_source_payload_data = main_basesoc_uart_rx_fifo_fifo_out_payload_data; +assign main_basesoc_uart_rx_fifo_re = main_basesoc_uart_rx_fifo_source_ready; +assign main_basesoc_uart_rx_fifo_syncfifo_re = (main_basesoc_uart_rx_fifo_syncfifo_readable & ((~main_basesoc_uart_rx_fifo_readable) | main_basesoc_uart_rx_fifo_re)); +assign main_basesoc_uart_rx_fifo_level1 = (main_basesoc_uart_rx_fifo_level0 + main_basesoc_uart_rx_fifo_readable); +always @(*) begin + main_basesoc_uart_rx_fifo_wrport_adr <= 4'd0; + if (main_basesoc_uart_rx_fifo_replace) begin + main_basesoc_uart_rx_fifo_wrport_adr <= (main_basesoc_uart_rx_fifo_produce - 1'd1); + end else begin + main_basesoc_uart_rx_fifo_wrport_adr <= main_basesoc_uart_rx_fifo_produce; + end +end +assign main_basesoc_uart_rx_fifo_wrport_dat_w = main_basesoc_uart_rx_fifo_syncfifo_din; +assign main_basesoc_uart_rx_fifo_wrport_we = (main_basesoc_uart_rx_fifo_syncfifo_we & (main_basesoc_uart_rx_fifo_syncfifo_writable | main_basesoc_uart_rx_fifo_replace)); +assign main_basesoc_uart_rx_fifo_do_read = (main_basesoc_uart_rx_fifo_syncfifo_readable & main_basesoc_uart_rx_fifo_syncfifo_re); +assign main_basesoc_uart_rx_fifo_rdport_adr = main_basesoc_uart_rx_fifo_consume; +assign main_basesoc_uart_rx_fifo_syncfifo_dout = main_basesoc_uart_rx_fifo_rdport_dat_r; +assign main_basesoc_uart_rx_fifo_rdport_re = main_basesoc_uart_rx_fifo_do_read; +assign main_basesoc_uart_rx_fifo_syncfifo_writable = (main_basesoc_uart_rx_fifo_level0 != 5'd16); +assign main_basesoc_uart_rx_fifo_syncfifo_readable = (main_basesoc_uart_rx_fifo_level0 != 1'd0); +assign main_basesoc_timer_zero_trigger = (main_basesoc_timer_value == 1'd0); +assign main_basesoc_timer_zero0 = main_basesoc_timer_zero_status; +assign main_basesoc_timer_zero1 = main_basesoc_timer_zero_pending; +always @(*) begin + main_basesoc_timer_zero_clear <= 1'd0; + if ((main_basesoc_timer_pending_re & main_basesoc_timer_pending_r)) begin + main_basesoc_timer_zero_clear <= 1'd1; + end +end +assign main_basesoc_timer_irq = (main_basesoc_timer_pending_status & main_basesoc_timer_enable_storage); +assign main_basesoc_timer_zero_status = main_basesoc_timer_zero_trigger; +assign main_crg_reset = main_crg_rst; +assign main_crg_clkin = clk12; +assign sys_clk = main_crg_clkout_buf0; +assign sys2x_clk = main_crg_clkout_buf1; +assign idelay_clk = main_crg_clkout_buf2; +assign main_basesoc_adr = main_basesoc_ram_bus_adr[13:0]; +assign main_basesoc_ram_bus_dat_r = main_basesoc_dat_r; +always @(*) begin + main_basesoc_sram0_we <= 4'd0; + main_basesoc_sram0_we[0] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[0]); + main_basesoc_sram0_we[1] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[1]); + main_basesoc_sram0_we[2] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[2]); + main_basesoc_sram0_we[3] <= (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & main_basesoc_interface0_ram_bus_we) & main_basesoc_interface0_ram_bus_sel[3]); +end +assign main_basesoc_sram0_adr = main_basesoc_interface0_ram_bus_adr[13:0]; +assign main_basesoc_interface0_ram_bus_dat_r = main_basesoc_sram0_dat_r; +assign main_basesoc_sram0_dat_w = main_basesoc_interface0_ram_bus_dat_w; +always @(*) begin + main_basesoc_sram1_we <= 4'd0; + main_basesoc_sram1_we[0] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[0]); + main_basesoc_sram1_we[1] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[1]); + main_basesoc_sram1_we[2] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[2]); + main_basesoc_sram1_we[3] <= (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & main_basesoc_interface1_ram_bus_we) & main_basesoc_interface1_ram_bus_sel[3]); +end +assign main_basesoc_sram1_adr = main_basesoc_interface1_ram_bus_adr[21:0]; +assign main_basesoc_interface1_ram_bus_dat_r = main_basesoc_sram1_dat_r; +assign main_basesoc_sram1_dat_w = main_basesoc_interface1_ram_bus_dat_w; +assign main_leds_wait = (~main_leds_done); +always @(*) begin + main_leds_leds <= 2'd0; + if ((main_leds_mode == 1'd1)) begin + main_leds_leds <= main_leds_storage; + end else begin + main_leds_leds <= main_leds_chaser; + end +end +assign {user_led1, user_led0} = (main_leds_leds ^ 1'd0); +assign main_leds_done = (main_leds_count == 1'd0); +always @(*) begin + builder_basesoc_we <= 1'd0; + builder_basesoc_dat_w <= 32'd0; + builder_basesoc_wishbone_ack <= 1'd0; + builder_basesoc_wishbone_dat_r <= 32'd0; + builder_basesoc_next_state <= 1'd0; + builder_basesoc_adr <= 14'd0; + builder_basesoc_next_state <= builder_basesoc_state; + case (builder_basesoc_state) + 1'd1: begin + builder_basesoc_wishbone_ack <= 1'd1; + builder_basesoc_wishbone_dat_r <= builder_basesoc_dat_r; + builder_basesoc_next_state <= 1'd0; + end + default: begin + builder_basesoc_dat_w <= builder_basesoc_wishbone_dat_w; + if ((builder_basesoc_wishbone_cyc & builder_basesoc_wishbone_stb)) begin + builder_basesoc_adr <= builder_basesoc_wishbone_adr; + builder_basesoc_we <= (builder_basesoc_wishbone_we & (builder_basesoc_wishbone_sel != 1'd0)); + builder_basesoc_next_state <= 1'd1; + end + end + endcase +end +assign builder_shared_adr = builder_array_muxed0; +assign builder_shared_dat_w = builder_array_muxed1; +assign builder_shared_sel = builder_array_muxed2; +assign builder_shared_cyc = builder_array_muxed3; +assign builder_shared_stb = builder_array_muxed4; +assign builder_shared_we = builder_array_muxed5; +assign builder_shared_cti = builder_array_muxed6; +assign builder_shared_bte = builder_array_muxed7; +assign main_basesoc_ibus_dat_r = builder_shared_dat_r; +assign main_basesoc_dbus_dat_r = builder_shared_dat_r; +assign main_basesoc_ibus_ack = (builder_shared_ack & (builder_grant == 1'd0)); +assign main_basesoc_dbus_ack = (builder_shared_ack & (builder_grant == 1'd1)); +assign main_basesoc_ibus_err = (builder_shared_err & (builder_grant == 1'd0)); +assign main_basesoc_dbus_err = (builder_shared_err & (builder_grant == 1'd1)); +assign builder_request = {main_basesoc_dbus_cyc, main_basesoc_ibus_cyc}; +always @(*) begin + builder_slave_sel <= 4'd0; + builder_slave_sel[0] <= (builder_shared_adr[29:14] == 1'd0); + builder_slave_sel[1] <= (builder_shared_adr[29:14] == 1'd1); + builder_slave_sel[2] <= (builder_shared_adr[29:22] == 1'd1); + builder_slave_sel[3] <= (builder_shared_adr[29:14] == 16'd65520); +end +assign main_basesoc_ram_bus_adr = builder_shared_adr; +assign main_basesoc_ram_bus_dat_w = builder_shared_dat_w; +assign main_basesoc_ram_bus_sel = builder_shared_sel; +assign main_basesoc_ram_bus_stb = builder_shared_stb; +assign main_basesoc_ram_bus_we = builder_shared_we; +assign main_basesoc_ram_bus_cti = builder_shared_cti; +assign main_basesoc_ram_bus_bte = builder_shared_bte; +assign main_basesoc_interface0_ram_bus_adr = builder_shared_adr; +assign main_basesoc_interface0_ram_bus_dat_w = builder_shared_dat_w; +assign main_basesoc_interface0_ram_bus_sel = builder_shared_sel; +assign main_basesoc_interface0_ram_bus_stb = builder_shared_stb; +assign main_basesoc_interface0_ram_bus_we = builder_shared_we; +assign main_basesoc_interface0_ram_bus_cti = builder_shared_cti; +assign main_basesoc_interface0_ram_bus_bte = builder_shared_bte; +assign main_basesoc_interface1_ram_bus_adr = builder_shared_adr; +assign main_basesoc_interface1_ram_bus_dat_w = builder_shared_dat_w; +assign main_basesoc_interface1_ram_bus_sel = builder_shared_sel; +assign main_basesoc_interface1_ram_bus_stb = builder_shared_stb; +assign main_basesoc_interface1_ram_bus_we = builder_shared_we; +assign main_basesoc_interface1_ram_bus_cti = builder_shared_cti; +assign main_basesoc_interface1_ram_bus_bte = builder_shared_bte; +assign builder_basesoc_wishbone_adr = builder_shared_adr; +assign builder_basesoc_wishbone_dat_w = builder_shared_dat_w; +assign builder_basesoc_wishbone_sel = builder_shared_sel; +assign builder_basesoc_wishbone_stb = builder_shared_stb; +assign builder_basesoc_wishbone_we = builder_shared_we; +assign builder_basesoc_wishbone_cti = builder_shared_cti; +assign builder_basesoc_wishbone_bte = builder_shared_bte; +assign main_basesoc_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[0]); +assign main_basesoc_interface0_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[1]); +assign main_basesoc_interface1_ram_bus_cyc = (builder_shared_cyc & builder_slave_sel[2]); +assign builder_basesoc_wishbone_cyc = (builder_shared_cyc & builder_slave_sel[3]); +assign builder_shared_err = (((main_basesoc_ram_bus_err | main_basesoc_interface0_ram_bus_err) | main_basesoc_interface1_ram_bus_err) | builder_basesoc_wishbone_err); +assign builder_wait = ((builder_shared_stb & builder_shared_cyc) & (~builder_shared_ack)); +always @(*) begin + builder_error <= 1'd0; + builder_shared_ack <= 1'd0; + builder_shared_dat_r <= 32'd0; + builder_shared_ack <= (((main_basesoc_ram_bus_ack | main_basesoc_interface0_ram_bus_ack) | main_basesoc_interface1_ram_bus_ack) | builder_basesoc_wishbone_ack); + builder_shared_dat_r <= (((({32{builder_slave_sel_r[0]}} & main_basesoc_ram_bus_dat_r) | ({32{builder_slave_sel_r[1]}} & main_basesoc_interface0_ram_bus_dat_r)) | ({32{builder_slave_sel_r[2]}} & main_basesoc_interface1_ram_bus_dat_r)) | ({32{builder_slave_sel_r[3]}} & builder_basesoc_wishbone_dat_r)); + if (builder_done) begin + builder_shared_dat_r <= 32'd4294967295; + builder_shared_ack <= 1'd1; + builder_error <= 1'd1; + end +end +assign builder_done = (builder_count == 1'd0); +assign builder_csr_bankarray_csrbank0_sel = (builder_csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd4); +assign builder_csr_bankarray_csrbank0_in_r = builder_csr_bankarray_interface0_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank0_in_re <= 1'd0; + builder_csr_bankarray_csrbank0_in_we <= 1'd0; + if ((builder_csr_bankarray_csrbank0_sel & (builder_csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin + builder_csr_bankarray_csrbank0_in_re <= builder_csr_bankarray_interface0_bank_bus_we; + builder_csr_bankarray_csrbank0_in_we <= (~builder_csr_bankarray_interface0_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank0_in_w = main_buttons_status[1:0]; +assign main_buttons_we = builder_csr_bankarray_csrbank0_in_we; +assign builder_csr_bankarray_csrbank1_sel = (builder_csr_bankarray_interface1_bank_bus_adr[13:9] == 3'd5); +assign builder_csr_bankarray_csrbank1_reset0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank1_reset0_re <= 1'd0; + builder_csr_bankarray_csrbank1_reset0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin + builder_csr_bankarray_csrbank1_reset0_re <= builder_csr_bankarray_interface1_bank_bus_we; + builder_csr_bankarray_csrbank1_reset0_we <= (~builder_csr_bankarray_interface1_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank1_scratch0_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csr_bankarray_csrbank1_scratch0_re <= 1'd0; + builder_csr_bankarray_csrbank1_scratch0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin + builder_csr_bankarray_csrbank1_scratch0_re <= builder_csr_bankarray_interface1_bank_bus_we; + builder_csr_bankarray_csrbank1_scratch0_we <= (~builder_csr_bankarray_interface1_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank1_bus_errors_r = builder_csr_bankarray_interface1_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csr_bankarray_csrbank1_bus_errors_we <= 1'd0; + builder_csr_bankarray_csrbank1_bus_errors_re <= 1'd0; + if ((builder_csr_bankarray_csrbank1_sel & (builder_csr_bankarray_interface1_bank_bus_adr[8:0] == 2'd2))) begin + builder_csr_bankarray_csrbank1_bus_errors_re <= builder_csr_bankarray_interface1_bank_bus_we; + builder_csr_bankarray_csrbank1_bus_errors_we <= (~builder_csr_bankarray_interface1_bank_bus_we); + end +end +always @(*) begin + main_basesoc_soc_rst <= 1'd0; + if (main_basesoc_reset_re) begin + main_basesoc_soc_rst <= main_basesoc_reset_storage[0]; + end +end +assign main_basesoc_cpu_rst = main_basesoc_reset_storage[1]; +assign builder_csr_bankarray_csrbank1_reset0_w = main_basesoc_reset_storage[1:0]; +assign builder_csr_bankarray_csrbank1_scratch0_w = main_basesoc_scratch_storage[31:0]; +assign builder_csr_bankarray_csrbank1_bus_errors_w = main_basesoc_bus_errors_status[31:0]; +assign main_basesoc_bus_errors_we = builder_csr_bankarray_csrbank1_bus_errors_we; +assign builder_csr_bankarray_sel = (builder_csr_bankarray_sram_bus_adr[13:9] == 3'd6); +always @(*) begin + builder_csr_bankarray_sram_bus_dat_r <= 32'd0; + if (builder_csr_bankarray_sel_r) begin + builder_csr_bankarray_sram_bus_dat_r <= builder_csr_bankarray_dat_r; + end +end +assign builder_csr_bankarray_adr = builder_csr_bankarray_sram_bus_adr[4:0]; +assign builder_csr_bankarray_csrbank2_sel = (builder_csr_bankarray_interface2_bank_bus_adr[13:9] == 2'd3); +assign builder_csr_bankarray_csrbank2_out0_r = builder_csr_bankarray_interface2_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank2_out0_re <= 1'd0; + builder_csr_bankarray_csrbank2_out0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank2_sel & (builder_csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin + builder_csr_bankarray_csrbank2_out0_re <= builder_csr_bankarray_interface2_bank_bus_we; + builder_csr_bankarray_csrbank2_out0_we <= (~builder_csr_bankarray_interface2_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank2_out0_w = main_leds_storage[1:0]; +assign builder_csr_bankarray_csrbank3_sel = (builder_csr_bankarray_interface3_bank_bus_adr[13:9] == 3'd7); +assign builder_csr_bankarray_csrbank3_load0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csr_bankarray_csrbank3_load0_re <= 1'd0; + builder_csr_bankarray_csrbank3_load0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin + builder_csr_bankarray_csrbank3_load0_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_load0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_reload0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csr_bankarray_csrbank3_reload0_we <= 1'd0; + builder_csr_bankarray_csrbank3_reload0_re <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd1))) begin + builder_csr_bankarray_csrbank3_reload0_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_reload0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_en0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank3_en0_re <= 1'd0; + builder_csr_bankarray_csrbank3_en0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin + builder_csr_bankarray_csrbank3_en0_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_en0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_update_value0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank3_update_value0_we <= 1'd0; + builder_csr_bankarray_csrbank3_update_value0_re <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd3))) begin + builder_csr_bankarray_csrbank3_update_value0_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_update_value0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_value_r = builder_csr_bankarray_interface3_bank_bus_dat_w[31:0]; +always @(*) begin + builder_csr_bankarray_csrbank3_value_we <= 1'd0; + builder_csr_bankarray_csrbank3_value_re <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd4))) begin + builder_csr_bankarray_csrbank3_value_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_value_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_ev_status_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank3_ev_status_re <= 1'd0; + builder_csr_bankarray_csrbank3_ev_status_we <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin + builder_csr_bankarray_csrbank3_ev_status_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_ev_status_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_ev_pending_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank3_ev_pending_re <= 1'd0; + builder_csr_bankarray_csrbank3_ev_pending_we <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd6))) begin + builder_csr_bankarray_csrbank3_ev_pending_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_ev_pending_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_ev_enable0_r = builder_csr_bankarray_interface3_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank3_ev_enable0_we <= 1'd0; + builder_csr_bankarray_csrbank3_ev_enable0_re <= 1'd0; + if ((builder_csr_bankarray_csrbank3_sel & (builder_csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd7))) begin + builder_csr_bankarray_csrbank3_ev_enable0_re <= builder_csr_bankarray_interface3_bank_bus_we; + builder_csr_bankarray_csrbank3_ev_enable0_we <= (~builder_csr_bankarray_interface3_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank3_load0_w = main_basesoc_timer_load_storage[31:0]; +assign builder_csr_bankarray_csrbank3_reload0_w = main_basesoc_timer_reload_storage[31:0]; +assign builder_csr_bankarray_csrbank3_en0_w = main_basesoc_timer_en_storage; +assign builder_csr_bankarray_csrbank3_update_value0_w = main_basesoc_timer_update_value_storage; +assign builder_csr_bankarray_csrbank3_value_w = main_basesoc_timer_value_status[31:0]; +assign main_basesoc_timer_value_we = builder_csr_bankarray_csrbank3_value_we; +assign main_basesoc_timer_status_status = main_basesoc_timer_zero0; +assign builder_csr_bankarray_csrbank3_ev_status_w = main_basesoc_timer_status_status; +assign main_basesoc_timer_status_we = builder_csr_bankarray_csrbank3_ev_status_we; +assign main_basesoc_timer_pending_status = main_basesoc_timer_zero1; +assign builder_csr_bankarray_csrbank3_ev_pending_w = main_basesoc_timer_pending_status; +assign main_basesoc_timer_pending_we = builder_csr_bankarray_csrbank3_ev_pending_we; +assign main_basesoc_timer_zero2 = main_basesoc_timer_enable_storage; +assign builder_csr_bankarray_csrbank3_ev_enable0_w = main_basesoc_timer_enable_storage; +assign builder_csr_bankarray_csrbank4_sel = (builder_csr_bankarray_interface4_bank_bus_adr[13:9] == 4'd8); +assign main_basesoc_uart_rxtx_r = builder_csr_bankarray_interface4_bank_bus_dat_w[7:0]; +always @(*) begin + main_basesoc_uart_rxtx_we <= 1'd0; + main_basesoc_uart_rxtx_re <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin + main_basesoc_uart_rxtx_re <= builder_csr_bankarray_interface4_bank_bus_we; + main_basesoc_uart_rxtx_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_txfull_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank4_txfull_re <= 1'd0; + builder_csr_bankarray_csrbank4_txfull_we <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd1))) begin + builder_csr_bankarray_csrbank4_txfull_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_txfull_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_rxempty_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank4_rxempty_re <= 1'd0; + builder_csr_bankarray_csrbank4_rxempty_we <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd2))) begin + builder_csr_bankarray_csrbank4_rxempty_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_rxempty_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_ev_status_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank4_ev_status_we <= 1'd0; + builder_csr_bankarray_csrbank4_ev_status_re <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 2'd3))) begin + builder_csr_bankarray_csrbank4_ev_status_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_ev_status_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_ev_pending_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank4_ev_pending_we <= 1'd0; + builder_csr_bankarray_csrbank4_ev_pending_re <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd4))) begin + builder_csr_bankarray_csrbank4_ev_pending_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_ev_pending_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_ev_enable0_r = builder_csr_bankarray_interface4_bank_bus_dat_w[1:0]; +always @(*) begin + builder_csr_bankarray_csrbank4_ev_enable0_re <= 1'd0; + builder_csr_bankarray_csrbank4_ev_enable0_we <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd5))) begin + builder_csr_bankarray_csrbank4_ev_enable0_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_ev_enable0_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_txempty_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank4_txempty_we <= 1'd0; + builder_csr_bankarray_csrbank4_txempty_re <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd6))) begin + builder_csr_bankarray_csrbank4_txempty_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_txempty_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_rxfull_r = builder_csr_bankarray_interface4_bank_bus_dat_w[0]; +always @(*) begin + builder_csr_bankarray_csrbank4_rxfull_we <= 1'd0; + builder_csr_bankarray_csrbank4_rxfull_re <= 1'd0; + if ((builder_csr_bankarray_csrbank4_sel & (builder_csr_bankarray_interface4_bank_bus_adr[8:0] == 3'd7))) begin + builder_csr_bankarray_csrbank4_rxfull_re <= builder_csr_bankarray_interface4_bank_bus_we; + builder_csr_bankarray_csrbank4_rxfull_we <= (~builder_csr_bankarray_interface4_bank_bus_we); + end +end +assign builder_csr_bankarray_csrbank4_txfull_w = main_basesoc_uart_txfull_status; +assign main_basesoc_uart_txfull_we = builder_csr_bankarray_csrbank4_txfull_we; +assign builder_csr_bankarray_csrbank4_rxempty_w = main_basesoc_uart_rxempty_status; +assign main_basesoc_uart_rxempty_we = builder_csr_bankarray_csrbank4_rxempty_we; +always @(*) begin + main_basesoc_uart_status_status <= 2'd0; + main_basesoc_uart_status_status[0] <= main_basesoc_uart_tx0; + main_basesoc_uart_status_status[1] <= main_basesoc_uart_rx0; +end +assign builder_csr_bankarray_csrbank4_ev_status_w = main_basesoc_uart_status_status[1:0]; +assign main_basesoc_uart_status_we = builder_csr_bankarray_csrbank4_ev_status_we; +always @(*) begin + main_basesoc_uart_pending_status <= 2'd0; + main_basesoc_uart_pending_status[0] <= main_basesoc_uart_tx1; + main_basesoc_uart_pending_status[1] <= main_basesoc_uart_rx1; +end +assign builder_csr_bankarray_csrbank4_ev_pending_w = main_basesoc_uart_pending_status[1:0]; +assign main_basesoc_uart_pending_we = builder_csr_bankarray_csrbank4_ev_pending_we; +assign main_basesoc_uart_tx2 = main_basesoc_uart_enable_storage[0]; +assign main_basesoc_uart_rx2 = main_basesoc_uart_enable_storage[1]; +assign builder_csr_bankarray_csrbank4_ev_enable0_w = main_basesoc_uart_enable_storage[1:0]; +assign builder_csr_bankarray_csrbank4_txempty_w = main_basesoc_uart_txempty_status; +assign main_basesoc_uart_txempty_we = builder_csr_bankarray_csrbank4_txempty_we; +assign builder_csr_bankarray_csrbank4_rxfull_w = main_basesoc_uart_rxfull_status; +assign main_basesoc_uart_rxfull_we = builder_csr_bankarray_csrbank4_rxfull_we; +assign builder_csr_interconnect_adr = builder_basesoc_adr; +assign builder_csr_interconnect_we = builder_basesoc_we; +assign builder_csr_interconnect_dat_w = builder_basesoc_dat_w; +assign builder_basesoc_dat_r = builder_csr_interconnect_dat_r; +assign builder_csr_bankarray_interface0_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_interface1_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_interface2_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_interface3_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_interface4_bank_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_sram_bus_adr = builder_csr_interconnect_adr; +assign builder_csr_bankarray_interface0_bank_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_interface1_bank_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_interface2_bank_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_interface3_bank_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_interface4_bank_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_sram_bus_we = builder_csr_interconnect_we; +assign builder_csr_bankarray_interface0_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_bankarray_interface1_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_bankarray_interface2_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_bankarray_interface3_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_bankarray_interface4_bank_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_bankarray_sram_bus_dat_w = builder_csr_interconnect_dat_w; +assign builder_csr_interconnect_dat_r = (((((builder_csr_bankarray_interface0_bank_bus_dat_r | builder_csr_bankarray_interface1_bank_bus_dat_r) | builder_csr_bankarray_interface2_bank_bus_dat_r) | builder_csr_bankarray_interface3_bank_bus_dat_r) | builder_csr_bankarray_interface4_bank_bus_dat_r) | builder_csr_bankarray_sram_bus_dat_r); +always @(*) begin + builder_array_muxed0 <= 30'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed0 <= main_basesoc_ibus_adr; + end + default: begin + builder_array_muxed0 <= main_basesoc_dbus_adr; + end + endcase +end +always @(*) begin + builder_array_muxed1 <= 32'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed1 <= main_basesoc_ibus_dat_w; + end + default: begin + builder_array_muxed1 <= main_basesoc_dbus_dat_w; + end + endcase +end +always @(*) begin + builder_array_muxed2 <= 4'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed2 <= main_basesoc_ibus_sel; + end + default: begin + builder_array_muxed2 <= main_basesoc_dbus_sel; + end + endcase +end +always @(*) begin + builder_array_muxed3 <= 1'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed3 <= main_basesoc_ibus_cyc; + end + default: begin + builder_array_muxed3 <= main_basesoc_dbus_cyc; + end + endcase +end +always @(*) begin + builder_array_muxed4 <= 1'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed4 <= main_basesoc_ibus_stb; + end + default: begin + builder_array_muxed4 <= main_basesoc_dbus_stb; + end + endcase +end +always @(*) begin + builder_array_muxed5 <= 1'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed5 <= main_basesoc_ibus_we; + end + default: begin + builder_array_muxed5 <= main_basesoc_dbus_we; + end + endcase +end +always @(*) begin + builder_array_muxed6 <= 3'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed6 <= main_basesoc_ibus_cti; + end + default: begin + builder_array_muxed6 <= main_basesoc_dbus_cti; + end + endcase +end +always @(*) begin + builder_array_muxed7 <= 2'd0; + case (builder_grant) + 1'd0: begin + builder_array_muxed7 <= main_basesoc_ibus_bte; + end + default: begin + builder_array_muxed7 <= main_basesoc_dbus_bte; + end + endcase +end +assign main_basesoc_rx_rx = builder_xilinxmultiregimpl0_regs1; +assign builder_xilinxasyncresetsynchronizerimpl0 = (~main_crg_locked); +assign builder_xilinxasyncresetsynchronizerimpl1 = (~main_crg_locked); +assign builder_xilinxasyncresetsynchronizerimpl2 = (~main_crg_locked); +assign main_buttons_status = builder_xilinxmultiregimpl1_regs1; +assign builder_xilinxmultiregimpl1 = {user_btn1, user_btn0}; + + +//------------------------------------------------------------------------------ +// Synchronous Logic +//------------------------------------------------------------------------------ + +always @(posedge idelay_clk) begin + if ((main_crg_reset_counter != 1'd0)) begin + main_crg_reset_counter <= (main_crg_reset_counter - 1'd1); + end else begin + main_crg_ic_reset <= 1'd0; + end + if (idelay_rst) begin + main_crg_reset_counter <= 4'd15; + main_crg_ic_reset <= 1'd1; + end +end + +always @(posedge sys_clk) begin + if ((main_basesoc_bus_errors != 32'd4294967295)) begin + if (main_basesoc_bus_error) begin + main_basesoc_bus_errors <= (main_basesoc_bus_errors + 1'd1); + end + end + {main_basesoc_tx_tick, main_basesoc_tx_phase} <= 23'd4947802; + if (main_basesoc_tx_enable) begin + {main_basesoc_tx_tick, main_basesoc_tx_phase} <= (main_basesoc_tx_phase + 23'd4947802); + end + builder_basesoc_rs232phytx_state <= builder_basesoc_rs232phytx_next_state; + if (main_basesoc_tx_count_rs232phytx_next_value_ce0) begin + main_basesoc_tx_count <= main_basesoc_tx_count_rs232phytx_next_value0; + end + if (main_basesoc_serial_tx_rs232phytx_next_value_ce1) begin + serial_tx <= main_basesoc_serial_tx_rs232phytx_next_value1; + end + if (main_basesoc_tx_data_rs232phytx_next_value_ce2) begin + main_basesoc_tx_data <= main_basesoc_tx_data_rs232phytx_next_value2; + end + main_basesoc_rx_rx_d <= main_basesoc_rx_rx; + {main_basesoc_rx_tick, main_basesoc_rx_phase} <= 32'd2147483648; + if (main_basesoc_rx_enable) begin + {main_basesoc_rx_tick, main_basesoc_rx_phase} <= (main_basesoc_rx_phase + 23'd4947802); + end + builder_basesoc_rs232phyrx_state <= builder_basesoc_rs232phyrx_next_state; + if (main_basesoc_rx_count_rs232phyrx_next_value_ce0) begin + main_basesoc_rx_count <= main_basesoc_rx_count_rs232phyrx_next_value0; + end + if (main_basesoc_rx_data_rs232phyrx_next_value_ce1) begin + main_basesoc_rx_data <= main_basesoc_rx_data_rs232phyrx_next_value1; + end + if (main_basesoc_uart_tx_clear) begin + main_basesoc_uart_tx_pending <= 1'd0; + end + main_basesoc_uart_tx_trigger_d <= main_basesoc_uart_tx_trigger; + if ((main_basesoc_uart_tx_trigger & (~main_basesoc_uart_tx_trigger_d))) begin + main_basesoc_uart_tx_pending <= 1'd1; + end + if (main_basesoc_uart_rx_clear) begin + main_basesoc_uart_rx_pending <= 1'd0; + end + main_basesoc_uart_rx_trigger_d <= main_basesoc_uart_rx_trigger; + if ((main_basesoc_uart_rx_trigger & (~main_basesoc_uart_rx_trigger_d))) begin + main_basesoc_uart_rx_pending <= 1'd1; + end + if (main_basesoc_uart_tx_fifo_syncfifo_re) begin + main_basesoc_uart_tx_fifo_readable <= 1'd1; + end else begin + if (main_basesoc_uart_tx_fifo_re) begin + main_basesoc_uart_tx_fifo_readable <= 1'd0; + end + end + if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin + main_basesoc_uart_tx_fifo_produce <= (main_basesoc_uart_tx_fifo_produce + 1'd1); + end + if (main_basesoc_uart_tx_fifo_do_read) begin + main_basesoc_uart_tx_fifo_consume <= (main_basesoc_uart_tx_fifo_consume + 1'd1); + end + if (((main_basesoc_uart_tx_fifo_syncfifo_we & main_basesoc_uart_tx_fifo_syncfifo_writable) & (~main_basesoc_uart_tx_fifo_replace))) begin + if ((~main_basesoc_uart_tx_fifo_do_read)) begin + main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 + 1'd1); + end + end else begin + if (main_basesoc_uart_tx_fifo_do_read) begin + main_basesoc_uart_tx_fifo_level0 <= (main_basesoc_uart_tx_fifo_level0 - 1'd1); + end + end + if (main_basesoc_uart_rx_fifo_syncfifo_re) begin + main_basesoc_uart_rx_fifo_readable <= 1'd1; + end else begin + if (main_basesoc_uart_rx_fifo_re) begin + main_basesoc_uart_rx_fifo_readable <= 1'd0; + end + end + if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin + main_basesoc_uart_rx_fifo_produce <= (main_basesoc_uart_rx_fifo_produce + 1'd1); + end + if (main_basesoc_uart_rx_fifo_do_read) begin + main_basesoc_uart_rx_fifo_consume <= (main_basesoc_uart_rx_fifo_consume + 1'd1); + end + if (((main_basesoc_uart_rx_fifo_syncfifo_we & main_basesoc_uart_rx_fifo_syncfifo_writable) & (~main_basesoc_uart_rx_fifo_replace))) begin + if ((~main_basesoc_uart_rx_fifo_do_read)) begin + main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 + 1'd1); + end + end else begin + if (main_basesoc_uart_rx_fifo_do_read) begin + main_basesoc_uart_rx_fifo_level0 <= (main_basesoc_uart_rx_fifo_level0 - 1'd1); + end + end + if (main_basesoc_timer_en_storage) begin + if ((main_basesoc_timer_value == 1'd0)) begin + main_basesoc_timer_value <= main_basesoc_timer_reload_storage; + end else begin + main_basesoc_timer_value <= (main_basesoc_timer_value - 1'd1); + end + end else begin + main_basesoc_timer_value <= main_basesoc_timer_load_storage; + end + if (main_basesoc_timer_update_value_re) begin + main_basesoc_timer_value_status <= main_basesoc_timer_value; + end + if (main_basesoc_timer_zero_clear) begin + main_basesoc_timer_zero_pending <= 1'd0; + end + main_basesoc_timer_zero_trigger_d <= main_basesoc_timer_zero_trigger; + if ((main_basesoc_timer_zero_trigger & (~main_basesoc_timer_zero_trigger_d))) begin + main_basesoc_timer_zero_pending <= 1'd1; + end + main_basesoc_ram_bus_ack <= 1'd0; + if (((main_basesoc_ram_bus_cyc & main_basesoc_ram_bus_stb) & ((~main_basesoc_ram_bus_ack) | main_basesoc_adr_burst))) begin + main_basesoc_ram_bus_ack <= 1'd1; + end + main_basesoc_interface0_ram_bus_ack <= 1'd0; + if (((main_basesoc_interface0_ram_bus_cyc & main_basesoc_interface0_ram_bus_stb) & ((~main_basesoc_interface0_ram_bus_ack) | main_basesoc_sram0_adr_burst))) begin + main_basesoc_interface0_ram_bus_ack <= 1'd1; + end + main_basesoc_interface1_ram_bus_ack <= 1'd0; + if (((main_basesoc_interface1_ram_bus_cyc & main_basesoc_interface1_ram_bus_stb) & ((~main_basesoc_interface1_ram_bus_ack) | main_basesoc_sram1_adr_burst))) begin + main_basesoc_interface1_ram_bus_ack <= 1'd1; + end + if (main_leds_done) begin + main_leds_chaser <= {main_leds_chaser, (~main_leds_chaser[1])}; + end + if (main_leds_re) begin + main_leds_mode <= 1'd1; + end + if (main_leds_wait) begin + if ((~main_leds_done)) begin + main_leds_count <= (main_leds_count - 1'd1); + end + end else begin + main_leds_count <= 25'd25000000; + end + builder_basesoc_state <= builder_basesoc_next_state; + case (builder_grant) + 1'd0: begin + if ((~builder_request[0])) begin + if (builder_request[1]) begin + builder_grant <= 1'd1; + end + end + end + 1'd1: begin + if ((~builder_request[1])) begin + if (builder_request[0]) begin + builder_grant <= 1'd0; + end + end + end + endcase + builder_slave_sel_r <= builder_slave_sel; + if (builder_wait) begin + if ((~builder_done)) begin + builder_count <= (builder_count - 1'd1); + end + end else begin + builder_count <= 20'd1000000; + end + builder_csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; + if (builder_csr_bankarray_csrbank0_sel) begin + case (builder_csr_bankarray_interface0_bank_bus_adr[8:0]) + 1'd0: begin + builder_csr_bankarray_interface0_bank_bus_dat_r <= builder_csr_bankarray_csrbank0_in_w; + end + endcase + end + main_buttons_re <= builder_csr_bankarray_csrbank0_in_re; + builder_csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; + if (builder_csr_bankarray_csrbank1_sel) begin + case (builder_csr_bankarray_interface1_bank_bus_adr[8:0]) + 1'd0: begin + builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_reset0_w; + end + 1'd1: begin + builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_scratch0_w; + end + 2'd2: begin + builder_csr_bankarray_interface1_bank_bus_dat_r <= builder_csr_bankarray_csrbank1_bus_errors_w; + end + endcase + end + if (builder_csr_bankarray_csrbank1_reset0_re) begin + main_basesoc_reset_storage[1:0] <= builder_csr_bankarray_csrbank1_reset0_r; + end + main_basesoc_reset_re <= builder_csr_bankarray_csrbank1_reset0_re; + if (builder_csr_bankarray_csrbank1_scratch0_re) begin + main_basesoc_scratch_storage[31:0] <= builder_csr_bankarray_csrbank1_scratch0_r; + end + main_basesoc_scratch_re <= builder_csr_bankarray_csrbank1_scratch0_re; + main_basesoc_bus_errors_re <= builder_csr_bankarray_csrbank1_bus_errors_re; + builder_csr_bankarray_sel_r <= builder_csr_bankarray_sel; + builder_csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; + if (builder_csr_bankarray_csrbank2_sel) begin + case (builder_csr_bankarray_interface2_bank_bus_adr[8:0]) + 1'd0: begin + builder_csr_bankarray_interface2_bank_bus_dat_r <= builder_csr_bankarray_csrbank2_out0_w; + end + endcase + end + if (builder_csr_bankarray_csrbank2_out0_re) begin + main_leds_storage[1:0] <= builder_csr_bankarray_csrbank2_out0_r; + end + main_leds_re <= builder_csr_bankarray_csrbank2_out0_re; + builder_csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; + if (builder_csr_bankarray_csrbank3_sel) begin + case (builder_csr_bankarray_interface3_bank_bus_adr[8:0]) + 1'd0: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_load0_w; + end + 1'd1: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_reload0_w; + end + 2'd2: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_en0_w; + end + 2'd3: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_update_value0_w; + end + 3'd4: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_value_w; + end + 3'd5: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_status_w; + end + 3'd6: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_pending_w; + end + 3'd7: begin + builder_csr_bankarray_interface3_bank_bus_dat_r <= builder_csr_bankarray_csrbank3_ev_enable0_w; + end + endcase + end + if (builder_csr_bankarray_csrbank3_load0_re) begin + main_basesoc_timer_load_storage[31:0] <= builder_csr_bankarray_csrbank3_load0_r; + end + main_basesoc_timer_load_re <= builder_csr_bankarray_csrbank3_load0_re; + if (builder_csr_bankarray_csrbank3_reload0_re) begin + main_basesoc_timer_reload_storage[31:0] <= builder_csr_bankarray_csrbank3_reload0_r; + end + main_basesoc_timer_reload_re <= builder_csr_bankarray_csrbank3_reload0_re; + if (builder_csr_bankarray_csrbank3_en0_re) begin + main_basesoc_timer_en_storage <= builder_csr_bankarray_csrbank3_en0_r; + end + main_basesoc_timer_en_re <= builder_csr_bankarray_csrbank3_en0_re; + if (builder_csr_bankarray_csrbank3_update_value0_re) begin + main_basesoc_timer_update_value_storage <= builder_csr_bankarray_csrbank3_update_value0_r; + end + main_basesoc_timer_update_value_re <= builder_csr_bankarray_csrbank3_update_value0_re; + main_basesoc_timer_value_re <= builder_csr_bankarray_csrbank3_value_re; + main_basesoc_timer_status_re <= builder_csr_bankarray_csrbank3_ev_status_re; + if (builder_csr_bankarray_csrbank3_ev_pending_re) begin + main_basesoc_timer_pending_r <= builder_csr_bankarray_csrbank3_ev_pending_r; + end + main_basesoc_timer_pending_re <= builder_csr_bankarray_csrbank3_ev_pending_re; + if (builder_csr_bankarray_csrbank3_ev_enable0_re) begin + main_basesoc_timer_enable_storage <= builder_csr_bankarray_csrbank3_ev_enable0_r; + end + main_basesoc_timer_enable_re <= builder_csr_bankarray_csrbank3_ev_enable0_re; + builder_csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; + if (builder_csr_bankarray_csrbank4_sel) begin + case (builder_csr_bankarray_interface4_bank_bus_adr[8:0]) + 1'd0: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= main_basesoc_uart_rxtx_w; + end + 1'd1: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_txfull_w; + end + 2'd2: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_rxempty_w; + end + 2'd3: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_status_w; + end + 3'd4: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_pending_w; + end + 3'd5: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_ev_enable0_w; + end + 3'd6: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_txempty_w; + end + 3'd7: begin + builder_csr_bankarray_interface4_bank_bus_dat_r <= builder_csr_bankarray_csrbank4_rxfull_w; + end + endcase + end + main_basesoc_uart_txfull_re <= builder_csr_bankarray_csrbank4_txfull_re; + main_basesoc_uart_rxempty_re <= builder_csr_bankarray_csrbank4_rxempty_re; + main_basesoc_uart_status_re <= builder_csr_bankarray_csrbank4_ev_status_re; + if (builder_csr_bankarray_csrbank4_ev_pending_re) begin + main_basesoc_uart_pending_r[1:0] <= builder_csr_bankarray_csrbank4_ev_pending_r; + end + main_basesoc_uart_pending_re <= builder_csr_bankarray_csrbank4_ev_pending_re; + if (builder_csr_bankarray_csrbank4_ev_enable0_re) begin + main_basesoc_uart_enable_storage[1:0] <= builder_csr_bankarray_csrbank4_ev_enable0_r; + end + main_basesoc_uart_enable_re <= builder_csr_bankarray_csrbank4_ev_enable0_re; + main_basesoc_uart_txempty_re <= builder_csr_bankarray_csrbank4_txempty_re; + main_basesoc_uart_rxfull_re <= builder_csr_bankarray_csrbank4_rxfull_re; + if (sys_rst) begin + main_basesoc_reset_storage <= 2'd0; + main_basesoc_reset_re <= 1'd0; + main_basesoc_scratch_storage <= 32'd305419896; + main_basesoc_scratch_re <= 1'd0; + main_basesoc_bus_errors_re <= 1'd0; + main_basesoc_bus_errors <= 32'd0; + serial_tx <= 1'd1; + main_basesoc_tx_tick <= 1'd0; + main_basesoc_rx_tick <= 1'd0; + main_basesoc_rx_rx_d <= 1'd0; + main_basesoc_uart_txfull_re <= 1'd0; + main_basesoc_uart_rxempty_re <= 1'd0; + main_basesoc_uart_tx_pending <= 1'd0; + main_basesoc_uart_tx_trigger_d <= 1'd0; + main_basesoc_uart_rx_pending <= 1'd0; + main_basesoc_uart_rx_trigger_d <= 1'd0; + main_basesoc_uart_status_re <= 1'd0; + main_basesoc_uart_pending_re <= 1'd0; + main_basesoc_uart_pending_r <= 2'd0; + main_basesoc_uart_enable_storage <= 2'd0; + main_basesoc_uart_enable_re <= 1'd0; + main_basesoc_uart_txempty_re <= 1'd0; + main_basesoc_uart_rxfull_re <= 1'd0; + main_basesoc_uart_tx_fifo_readable <= 1'd0; + main_basesoc_uart_tx_fifo_level0 <= 5'd0; + main_basesoc_uart_tx_fifo_produce <= 4'd0; + main_basesoc_uart_tx_fifo_consume <= 4'd0; + main_basesoc_uart_rx_fifo_readable <= 1'd0; + main_basesoc_uart_rx_fifo_level0 <= 5'd0; + main_basesoc_uart_rx_fifo_produce <= 4'd0; + main_basesoc_uart_rx_fifo_consume <= 4'd0; + main_basesoc_timer_load_storage <= 32'd0; + main_basesoc_timer_load_re <= 1'd0; + main_basesoc_timer_reload_storage <= 32'd0; + main_basesoc_timer_reload_re <= 1'd0; + main_basesoc_timer_en_storage <= 1'd0; + main_basesoc_timer_en_re <= 1'd0; + main_basesoc_timer_update_value_storage <= 1'd0; + main_basesoc_timer_update_value_re <= 1'd0; + main_basesoc_timer_value_status <= 32'd0; + main_basesoc_timer_value_re <= 1'd0; + main_basesoc_timer_zero_pending <= 1'd0; + main_basesoc_timer_zero_trigger_d <= 1'd0; + main_basesoc_timer_status_re <= 1'd0; + main_basesoc_timer_pending_re <= 1'd0; + main_basesoc_timer_pending_r <= 1'd0; + main_basesoc_timer_enable_storage <= 1'd0; + main_basesoc_timer_enable_re <= 1'd0; + main_basesoc_timer_value <= 32'd0; + main_basesoc_ram_bus_ack <= 1'd0; + main_basesoc_interface0_ram_bus_ack <= 1'd0; + main_basesoc_interface1_ram_bus_ack <= 1'd0; + main_leds_storage <= 2'd0; + main_leds_re <= 1'd0; + main_leds_chaser <= 2'd0; + main_leds_mode <= 1'd0; + main_leds_count <= 25'd25000000; + main_buttons_re <= 1'd0; + builder_grant <= 1'd0; + builder_slave_sel_r <= 4'd0; + builder_count <= 20'd1000000; + builder_csr_bankarray_sel_r <= 1'd0; + builder_basesoc_rs232phytx_state <= 1'd0; + builder_basesoc_rs232phyrx_state <= 1'd0; + builder_basesoc_state <= 1'd0; + end + builder_xilinxmultiregimpl0_regs0 <= serial_rx; + builder_xilinxmultiregimpl0_regs1 <= builder_xilinxmultiregimpl0_regs0; + builder_xilinxmultiregimpl1_regs0 <= {user_btn1, user_btn0}; + builder_xilinxmultiregimpl1_regs1 <= builder_xilinxmultiregimpl1_regs0; +end + + +//------------------------------------------------------------------------------ +// Specialized Logic +//------------------------------------------------------------------------------ + +//------------------------------------------------------------------------------ +// Memory mem: 24-words x 8-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [7:0] mem[0:23]; +initial begin + $readmemh("cmod7_mem.init", mem); +end +reg [4:0] mem_adr0; +always @(posedge sys_clk) begin + mem_adr0 <= builder_csr_bankarray_adr; +end +assign builder_csr_bankarray_dat_r = mem[mem_adr0]; + + +//------------------------------------------------------------------------------ +// Memory storage: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage[0:15]; +reg [9:0] storage_dat0; +reg [9:0] storage_dat1; +always @(posedge sys_clk) begin + if (main_basesoc_uart_tx_fifo_wrport_we) + storage[main_basesoc_uart_tx_fifo_wrport_adr] <= main_basesoc_uart_tx_fifo_wrport_dat_w; + storage_dat0 <= storage[main_basesoc_uart_tx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (main_basesoc_uart_tx_fifo_rdport_re) + storage_dat1 <= storage[main_basesoc_uart_tx_fifo_rdport_adr]; +end +assign main_basesoc_uart_tx_fifo_wrport_dat_r = storage_dat0; +assign main_basesoc_uart_tx_fifo_rdport_dat_r = storage_dat1; + + +//------------------------------------------------------------------------------ +// Memory storage_1: 16-words x 10-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 +// Port 1 | Read: Sync | Write: ---- | +reg [9:0] storage_1[0:15]; +reg [9:0] storage_1_dat0; +reg [9:0] storage_1_dat1; +always @(posedge sys_clk) begin + if (main_basesoc_uart_rx_fifo_wrport_we) + storage_1[main_basesoc_uart_rx_fifo_wrport_adr] <= main_basesoc_uart_rx_fifo_wrport_dat_w; + storage_1_dat0 <= storage_1[main_basesoc_uart_rx_fifo_wrport_adr]; +end +always @(posedge sys_clk) begin + if (main_basesoc_uart_rx_fifo_rdport_re) + storage_1_dat1 <= storage_1[main_basesoc_uart_rx_fifo_rdport_adr]; +end +assign main_basesoc_uart_rx_fifo_wrport_dat_r = storage_1_dat0; +assign main_basesoc_uart_rx_fifo_rdport_dat_r = storage_1_dat1; + + +BUFG BUFG( + .I(main_crg_clkout0), + .O(main_crg_clkout_buf0) +); + +BUFG BUFG_1( + .I(main_crg_clkout1), + .O(main_crg_clkout_buf1) +); + +BUFG BUFG_2( + .I(main_crg_clkout2), + .O(main_crg_clkout_buf2) +); + +IDELAYCTRL IDELAYCTRL( + .REFCLK(idelay_clk), + .RST(main_crg_ic_reset) +); + +//------------------------------------------------------------------------------ +// Memory rom: 16384-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: ---- | +reg [31:0] rom[0:16383]; +initial begin + $readmemh("cmod7_rom.init", rom); +end +reg [31:0] rom_dat0; +always @(posedge sys_clk) begin + rom_dat0 <= rom[main_basesoc_adr]; +end +assign main_basesoc_dat_r = rom_dat0; + + +//------------------------------------------------------------------------------ +// Memory sram: 16384-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] sram[0:16383]; +initial begin + $readmemh("cmod7_sram.init", sram); +end +reg [13:0] sram_adr0; +always @(posedge sys_clk) begin + if (main_basesoc_sram0_we[0]) + sram[main_basesoc_sram0_adr][7:0] <= main_basesoc_sram0_dat_w[7:0]; + if (main_basesoc_sram0_we[1]) + sram[main_basesoc_sram0_adr][15:8] <= main_basesoc_sram0_dat_w[15:8]; + if (main_basesoc_sram0_we[2]) + sram[main_basesoc_sram0_adr][23:16] <= main_basesoc_sram0_dat_w[23:16]; + if (main_basesoc_sram0_we[3]) + sram[main_basesoc_sram0_adr][31:24] <= main_basesoc_sram0_dat_w[31:24]; + sram_adr0 <= main_basesoc_sram0_adr; +end +assign main_basesoc_sram0_dat_r = sram[sram_adr0]; + + +//------------------------------------------------------------------------------ +// Memory main_ram: 4194304-words x 32-bit +//------------------------------------------------------------------------------ +// Port 0 | Read: Sync | Write: Sync | Mode: Write-First | Write-Granularity: 8 +reg [31:0] main_ram[0:4194303]; +initial begin + $readmemh("cmod7_main_ram.init", main_ram); +end +reg [21:0] main_ram_adr0; +always @(posedge sys_clk) begin + if (main_basesoc_sram1_we[0]) + main_ram[main_basesoc_sram1_adr][7:0] <= main_basesoc_sram1_dat_w[7:0]; + if (main_basesoc_sram1_we[1]) + main_ram[main_basesoc_sram1_adr][15:8] <= main_basesoc_sram1_dat_w[15:8]; + if (main_basesoc_sram1_we[2]) + main_ram[main_basesoc_sram1_adr][23:16] <= main_basesoc_sram1_dat_w[23:16]; + if (main_basesoc_sram1_we[3]) + main_ram[main_basesoc_sram1_adr][31:24] <= main_basesoc_sram1_dat_w[31:24]; + main_ram_adr0 <= main_basesoc_sram1_adr; +end +assign main_basesoc_sram1_dat_r = main_ram[main_ram_adr0]; + + +A2P_WB A2P_WB( + .clk(sys_clk), + .dBusWB_ACK(main_basesoc_dbus_ack), + .dBusWB_DAT_MISO(main_basesoc_dbus_dat_r), + .dBusWB_ERR(main_basesoc_dbus_err), + .externalInterrupt(main_basesoc_interrupt[0]), + .externalInterruptS(main_basesoc_interruptS), + .externalResetVector(main_basesoc_a2p), + .iBusWB_ACK(main_basesoc_ibus_ack), + .iBusWB_DAT_MISO(main_basesoc_ibus_dat_r), + .iBusWB_ERR(main_basesoc_ibus_err), + .reset((sys_rst | main_basesoc_reset)), + .softwareInterrupt(1'd0), + .timerInterrupt(1'd0), + .dBusWB_ADR(main_basesoc_dbus_adr), + .dBusWB_BTE(main_basesoc_dbus_bte), + .dBusWB_CTI(main_basesoc_dbus_cti), + .dBusWB_CYC(main_basesoc_dbus_cyc), + .dBusWB_DAT_MOSI(main_basesoc_dbus_dat_w), + .dBusWB_SEL(main_basesoc_dbus_sel), + .dBusWB_STB(main_basesoc_dbus_stb), + .dBusWB_WE(main_basesoc_dbus_we), + .iBusWB_ADR(main_basesoc_ibus_adr), + .iBusWB_BTE(main_basesoc_ibus_bte), + .iBusWB_CTI(main_basesoc_ibus_cti), + .iBusWB_CYC(main_basesoc_ibus_cyc), + .iBusWB_DAT_MOSI(main_basesoc_ibus_dat_w), + .iBusWB_SEL(main_basesoc_ibus_sel), + .iBusWB_STB(main_basesoc_ibus_stb), + .iBusWB_WE(main_basesoc_ibus_we) +); + +FDCE FDCE( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(main_crg_reset), + .Q(builder_basesoc_reset0) +); + +FDCE FDCE_1( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset0), + .Q(builder_basesoc_reset1) +); + +FDCE FDCE_2( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset1), + .Q(builder_basesoc_reset2) +); + +FDCE FDCE_3( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset2), + .Q(builder_basesoc_reset3) +); + +FDCE FDCE_4( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset3), + .Q(builder_basesoc_reset4) +); + +FDCE FDCE_5( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset4), + .Q(builder_basesoc_reset5) +); + +FDCE FDCE_6( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset5), + .Q(builder_basesoc_reset6) +); + +FDCE FDCE_7( + .C(main_crg_clkin), + .CE(1'd1), + .CLR(1'd0), + .D(builder_basesoc_reset6), + .Q(builder_basesoc_reset7) +); + +MMCME2_ADV #( + .BANDWIDTH("OPTIMIZED"), + .CLKFBOUT_MULT_F(6'd50), + .CLKIN1_PERIOD(83.33333333333333), + .CLKOUT0_DIVIDE_F(3'd6), + .CLKOUT0_PHASE(1'd0), + .CLKOUT1_DIVIDE(2'd3), + .CLKOUT1_PHASE(1'd0), + .CLKOUT2_DIVIDE(2'd3), + .CLKOUT2_PHASE(1'd0), + .DIVCLK_DIVIDE(1'd1), + .REF_JITTER1(0.01) +) MMCME2_ADV ( + .CLKFBIN(builder_basesoc_mmcm_fb), + .CLKIN1(main_crg_clkin), + .PWRDWN(main_crg_power_down), + .RST(builder_basesoc_reset7), + .CLKFBOUT(builder_basesoc_mmcm_fb), + .CLKOUT0(main_crg_clkout0), + .CLKOUT1(main_crg_clkout1), + .CLKOUT2(main_crg_clkout2), + .LOCKED(main_crg_locked) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE ( + .C(sys_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(builder_xilinxasyncresetsynchronizerimpl0_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_1 ( + .C(sys_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl0_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl0), + .Q(sys_rst) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_2 ( + .C(sys2x_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_3 ( + .C(sys2x_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl1_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl1), + .Q(builder_xilinxasyncresetsynchronizerimpl1_expr) +); + +(* ars_ff1 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_4 ( + .C(idelay_clk), + .CE(1'd1), + .D(1'd0), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(builder_xilinxasyncresetsynchronizerimpl2_rst_meta) +); + +(* ars_ff2 = "true", async_reg = "true" *) FDPE #( + .INIT(1'd1) +) FDPE_5 ( + .C(idelay_clk), + .CE(1'd1), + .D(builder_xilinxasyncresetsynchronizerimpl2_rst_meta), + .PRE(builder_xilinxasyncresetsynchronizerimpl2), + .Q(idelay_rst) +); + +endmodule + +// ----------------------------------------------------------------------------- +// Auto-Generated by LiteX on 2022-08-23 17:08:47. +//------------------------------------------------------------------------------ diff --git a/sim/soc/tb_litex_soc.cpp b/sim/soc/tb_litex_soc.cpp new file mode 100644 index 0000000..1d8176a --- /dev/null +++ b/sim/soc/tb_litex_soc.cpp @@ -0,0 +1,455 @@ +// simple verilator top +// litex soc w/a2p + +#ifndef NO_TRACE +#define TRACING +#endif + +// old public access method +//#define OLD_PUBLIC + +#include +#include +#include +#include +#include + +#include "verilated.h" +#include "Vsoc.h" + +#ifndef OLD_PUBLIC +// internal nets +#include "Vsoc___024root.h" +#endif + +#include "Vsoc_soc.h" +#include "Vsoc_A2P_WB.h" + +#ifdef TRACING +#include "verilated_vcd_c.h" +VerilatedVcdC *t; +#else +unsigned int t = 0; +#endif + +// using https://github.com/ZipCPU/wbuart32 sim driver +// how does cpp get compiled in without this? can verilator be told to add more cpp? see a2p! +// UART=port +// 0xA20 = 2592 +// A2P = 2593 +#ifdef UART +#include "wbuart32/bench/cpp/uartsim.h" +#include "wbuart32/bench/cpp/uartsim.cpp" +#endif + +Vsoc* m; +#ifdef OLD_PUBLIC +Vsoc* root; +#else +Vsoc___024root* root; +#endif + +vluint64_t main_time = 0; // in units of timeprecision used in verilog or --timescale-override + +double sc_time_stamp() { // $time in verilog + return main_time; +} + +const char* tbName = "tb_litex_soc"; +const int resetCycle = 10; +const int threadRunCycle = resetCycle + 5; +const int runCycles = 1000000000; +const int hbCycles = 500; +const int quiesceCycles = 50; +const int threads = 1; +const std::string testFile = ""; +const unsigned int bootAdr = 0x00000000; +const bool failMaxCycles = true; +const unsigned int stopOnHang = 500; +const unsigned int stopOnLoop = 20; +const unsigned long iarPass = 0x7F0; +const unsigned long iarFail = 0x7F4; +const bool debugWB = true; +const bool debugWBReq = false; + +// Cythonize this and use it for cocotb too... + +class Memory { + std::unordered_map mem; + public: + bool le; + bool logStores; + int defaultVal; + Memory(); + void loadFile(std::string filename, unsigned int adr=0, bool le=false, std::string format="ascii"); + int read(unsigned int adr); + void write(unsigned int adr, unsigned int dat); + void write(unsigned int adr, unsigned int be, unsigned int dat); +}; + +Memory::Memory() { + + this->defaultVal = 0; + this->le = false; + this->logStores = true; + +} + +void Memory::loadFile(std::string filename, unsigned int adr, bool le, std::string format) { + + unsigned int dat; + std::ifstream f; + f.open(filename, std::fstream::in); + // "ascii" + //while (f.peek()!=EOF) { + //f >> std::hex >> dat; + // f >> dat; + while (f >> std::hex >> dat) { + this->write(adr, dat); + adr += 4; + } + +} + +// adr is word-aligned byte address +int Memory::read(unsigned int adr) { + if (this->mem.find(adr) != this->mem.end()) { + return this->mem[adr]; + } else { + return this->defaultVal; + } +} + +// adr is word-aligned byte address +void Memory::write(unsigned int adr, unsigned int dat) { + unsigned int startDat = this->read(adr); + this->write(adr, 0xF, dat); +} + +void Memory::write(unsigned int adr, unsigned int be, unsigned int dat) { + if (be == 0) return; + + int mask = 0, startDat; + if (be >= 8) { + be = be - 8; + mask = 0xFF000000; + } else { + mask = 0; + } + if (be >= 4) { + be = be - 4; + mask |= 0x00FF0000; + } + if (be >= 2) { + be = be - 2; + mask |= 0x0000FF00; + } + if (be = 1) { + mask |= 0x000000FF; + } + + startDat = this->read(adr); + this->mem[adr] = (startDat & ~mask) | (dat & mask); + if (this->logStores) { + std::cout << " * Mem Update @" << std::setw(8) << std::setfill('0') << std::uppercase << std::hex << adr << + " " <" <read(adr) << std::endl; + } +} + +Memory mem; + +int main(int argc, char **argv) { + using namespace std; + + cout << setfill('0'); + + Verilated::commandArgs(argc, argv); + m = new Vsoc; +#ifdef OLD_PUBLIC + root = m; +#else + root = m->rootp; +#endif + +#ifdef TRACING + Verilated::traceEverOn(true); + t = new VerilatedVcdC; + m->trace(t, 99); + t->open("a2plitex.vcd"); + cout << "Tracing enabled." << endl; +#endif + + unsigned int i, v; + bool ok = true; + bool done = false; + bool resetDone = false; + bool booted = false; + unsigned int quiesceCount = 0; + unsigned int threadStop = 0x3; + + unsigned int tick = 0; + unsigned int cycle = 1; + unsigned int readPending = 0; + unsigned int readAddr = 0; + unsigned int readTag = 0; + unsigned int readTID = 0; + unsigned int countReads = 0; + unsigned int lastCompCycle = 0; + unsigned int lastCompSame = 0; + unsigned int lastCompIAR = 0x0000001; + unsigned int gpr[32]; + bool wbRdPending = false, wbWrPending = false; + + // memory setup + //mem.write(0xFFFFFFFC, 0x48000002); + //mem.loadFile(testFile); + + // uart setup + /* + // i_setup[30] True if we are not using hardware flow control. This bit +// is ignored within this module, as any receive hardware flow +// control will need to be implemented elsewhere. +// +// i_setup[29:28] Indicates the number of data bits per word. This will +// either be 2'b00 for an 8-bit word, 2'b01 for a 7-bit word, 2'b10 +// for a six bit word, or 2'b11 for a five bit word. +// +// i_setup[27] Indicates whether or not to use one or two stop bits. +// Set this to one to expect two stop bits, zero for one. +// +// i_setup[26] Indicates whether or not a parity bit exists. Set this +// to 1'b1 to include parity. +// +// i_setup[25] Indicates whether or not the parity bit is fixed. Set +// to 1'b1 to include a fixed bit of parity, 1'b0 to allow the +// parity to be set based upon data. (Both assume the parity +// enable value is set.) +// +// i_setup[24] This bit is ignored if parity is not used. Otherwise, +// in the case of a fixed parity bit, this bit indicates whether +// mark (1'b1) or space (1'b0) parity is used. Likewise if the +// parity is not fixed, a 1'b1 selects even parity, and 1'b0 +// selects odd. +// +// i_setup[23:0] Indicates the speed of the UART in terms of clocks. +// So, for example, if you have a 200 MHz clock and wish to +// run your UART at 9600 baud, you would take 200 MHz and divide +// by 9600 to set this value to 24'd20834. Likewise if you wished +// to run this serial port at 115200 baud from a 200 MHz clock, +// you would set the value to 24'd1736 + */ + /* + m_baud_counts = (isetup & 0x0ffffff); + m_nbits = 8-((isetup >> 28)&0x03); + m_nstop =((isetup >> 27)&1)+1; + m_nparity = (isetup >> 26)&1; + m_fixdp = (isetup >> 25)&1; + m_evenp = (isetup >> 24)&1; + */ + + // 100MHz, 115200 = 868 + #ifdef UART + UARTSIM *uart; + int uartPort = UART; // 0-stdin/stdout + //unsigned uartConfig = 1736; + unsigned uartConfig = 868; + //unsigned uartConfig = 434; + //unsigned uartConfig = 217; + //unsigned uartConfig = 217; + + cout << "Initializing UART on port " << uartPort << " with config=" << hex << setw(8) << setfill('0') << uartConfig << endl; + uart = new UARTSIM(uartPort); + uart->setup(uartConfig); + cout << "litex_term socket://localhost:" << uartPort << " in a console, then hit enter here...." << endl; + cin.get(); + #endif + + + // do something + + for (i = 0; i < 32; i++) { + gpr[i] = 0; + } + + //just use hardware reset + //root->soc->main_basesoc_soc_rst = 1; + //cout << dec << setw(8) << cycle << " Resetting..." << endl; + + const int clocks[2] = {0x1, 0x0}; // 1x + const int ticks1x = 2; + + while (!Verilated::gotFinish() && (ok | quiesceCount > 0) && cycle <= runCycles && !done) { + + if (!resetDone && (cycle > resetCycle)) { + //root->soc->main_basesoc_soc_rst = 0; + //cout << dec << setw(8) << cycle << " Releasing reset." << endl; + resetDone = true; + } + + if (threadStop && (cycle > threadRunCycle)) { + //threadStop = 0x0; + //m->an_ac_pm_thread_stop = threadStop; + //cout << dec << setw(8) << cycle << " Thread stop=" << threadStop << endl; + } + + m->clk12 = clocks[tick % ticks1x]; + m->eval(); + + // 1x clock + if ((tick % ticks1x) == 0) { + + // core + + // completion + if (root->soc->A2P_WB->lastStageIsFiring) { + v = root->soc->A2P_WB->lastStagePc; + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " C0: CP"; + cout << " 0:" << setw(6) << setfill('0') << hex << v; + cout << " [" << setw(6) << setfill('0') << hex << root->soc->A2P_WB->lastStageInstruction << "]" << endl; + if (quiesceCount > 0) { + /* skip remaining checks */ + } else if (v == iarPass) { + cout << "*** Passing IAR detected ***" << endl; + quiesceCount = 5; + } else if (v == iarFail) { + cout << "*** Failing IAR detected ***" << endl; + ok = false; + quiesceCount = 5; + } else if (v == lastCompIAR) { + lastCompSame++; + if (stopOnLoop && (lastCompSame == stopOnLoop)) { + ok = false; + cout << "*** Loop detected for " << dec << stopOnLoop << " iterations ***" << endl; + } + } else { + lastCompIAR = v; + lastCompSame = 0; + } + } + + // gpr change - really need to use these (to detect write w/same data) + //reg [4:0] lastStageRegFileWrite_payload_address /* verilator public */ ; + //reg [31:0] lastStageRegFileWrite_payload_data /* verilator public */ ; + //wire UpdateRegFileWrite_valid /* verilator public */ ; + //wire UpdateRegFileWrite_payload_valid /* verilator public */ ; + //wire [4:0] UpdateRegFileWrite_payload_address /* verilator public */ ; + //wire [31:0] UpdateRegFileWrite_payload_data /* verilator public */ ; + + for (i = 0; i < 32; i++) { + v = root->soc->A2P_WB->RegFilePlugin_regFile[i]; + if (v != gpr[i]) { + gpr[i] = v; + cout << dec << setw(8) << setfill('0') << cycle << " C0: GPR Update: R"; + cout << dec << setw(2) << setfill('0') << i << "="; + cout << hex << setw(8) << setfill('0') << uppercase << v << " "; + cout << endl; + } + } + + + // completion + + // wb - soc can monitor-only + if (wbRdPending) { + if (root->soc->A2P_WB->dBusWB_ACK) + if (debugWB) + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << + " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl; + + wbRdPending = false; + + } else if (wbWrPending) { + if (root->soc->A2P_WB->dBusWB_ACK) + if (debugWB) + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << + " SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL << + " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl; + wbWrPending = false; + + } else if (root->soc->A2P_WB->dBusWB_CYC && root->soc->A2P_WB->dBusWB_STB) { + if (!root->soc->A2P_WB->dBusWB_WE) { + if (root->soc->A2P_WB->dBusWB_ACK) { + if (debugWB) + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << + " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MISO << endl; + } else if (!wbRdPending && debugWBReq) { + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB RD RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << endl; + wbRdPending = true; + } + } else { + if (debugWB) { + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR ACK RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << + " SEL=" << setw(1) << setfill('0') << uppercase << hex << (unsigned int)root->soc->A2P_WB->dBusWB_SEL << + " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl; + } else if (!wbWrPending && debugWBReq) { + cout << dec << setw(8) << setfill('0') << uppercase << cycle << " WB WR RA=" << setw(8) << hex << setfill('0') << (root->soc->A2P_WB->dBusWB_ADR << 2) << + " SEL=" << root->soc->A2P_WB->dBusWB_SEL << " DATA=" << setw(8) << hex << setfill('0') << root->soc->A2P_WB->dBusWB_DAT_MOSI << endl; + wbWrPending = true; + } + } + } + + // leds, btns, mem, etc. + + } else { + + if (resetDone) { + #ifdef UART + m->serial_rx = (*uart)(m->serial_tx); + #endif + } + + } + + m->eval(); // NEED THIS!!!! + + // finish clock stuff + if ((tick % ticks1x) == 0) { + cycle++; + if ((cycle % hbCycles) == 0) { + cout << dec << setw(8) << setfill('0') << cycle << " ...tick..." << endl; + } + if (failMaxCycles && (cycle == runCycles)) { + cout << "*** Max cycles reached ***" << endl; + ok = false; + } + } + + tick++; + + #ifdef TRACING + t->dump(tick); + t->flush(); + #endif + + // check for fails + + if (!ok && quiesceCount == 0) { + quiesceCount = quiesceCycles; + cout << "Quiescing..." << endl; + } else if (quiesceCount > 0) { + quiesceCount--; + if (ok && quiesceCount == 0) { + done = true; + } + } + + } + +#ifdef TRACING + t->close(); +#endif + m->final(); + + cout << endl << endl << tbName << endl; + cout << endl << "Cycles run=" << dec << cycle << endl << endl; + if (!ok) { + cout << "You are worthless and weak." << endl; + exit(EXIT_FAILURE); + } else { + cout << "You has opulence." << endl; + exit(EXIT_SUCCESS); + } + +} \ No newline at end of file diff --git a/sim/soc/unisims/BUFG.v b/sim/soc/unisims/BUFG.v new file mode 100644 index 0000000..81c0b8e --- /dev/null +++ b/sim/soc/unisims/BUFG.v @@ -0,0 +1,4 @@ +module BUFG (output O, input I); + assign O = I; +endmodule + diff --git a/sim/soc/unisims/DNA_PORT.v b/sim/soc/unisims/DNA_PORT.v new file mode 100644 index 0000000..d5933e6 --- /dev/null +++ b/sim/soc/unisims/DNA_PORT.v @@ -0,0 +1,10 @@ +module DNA_PORT (DOUT, CLK, DIN, READ, SHIFT); + + parameter [56:0] SIM_DNA_VALUE = 57'h0; + + output DOUT; + input CLK, DIN, READ, SHIFT; + + assign DOUT = 1'b0; + +endmodule \ No newline at end of file diff --git a/sim/soc/unisims/FD.v b/sim/soc/unisims/FD.v new file mode 100644 index 0000000..824ad57 --- /dev/null +++ b/sim/soc/unisims/FD.v @@ -0,0 +1,21 @@ + +`timescale 1 ps / 1 ps + +module FD (Q, C, D); + + parameter INIT = 1'b0; + + output Q; + input C, D; + + wire Q; + reg q_out; + + initial q_out = INIT; + + always @(posedge C) + q_out <= D; + + assign Q = q_out; + +endmodule diff --git a/sim/soc/unisims/FDCE.v b/sim/soc/unisims/FDCE.v new file mode 100644 index 0000000..62ae70e --- /dev/null +++ b/sim/soc/unisims/FDCE.v @@ -0,0 +1,24 @@ +`timescale 1 ps / 1 ps + +module FDCE (C, CE, CLR, D, Q); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, CLR; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C or posedge CLR) + if (CLR) + q_out <= 0; + else if (CE) + q_out <= D; + +endmodule diff --git a/sim/soc/unisims/FDPE.v b/sim/soc/unisims/FDPE.v new file mode 100644 index 0000000..2d4e3ce --- /dev/null +++ b/sim/soc/unisims/FDPE.v @@ -0,0 +1,24 @@ +`timescale 1 ps / 1 ps + +module FDPE (Q, C, CE, D, PRE); + + parameter INIT = 1'b1; + + output Q; + + input C, CE, D, PRE; + + wire Q; + reg q_out; + + initial q_out = INIT; + + assign Q = q_out; + + always @(posedge C or posedge PRE) + if (PRE) + q_out <= 1; + else if (CE) + q_out <= D; + +endmodule diff --git a/sim/soc/unisims/IDELAYCTRL.v b/sim/soc/unisims/IDELAYCTRL.v new file mode 100644 index 0000000..aeaf2ee --- /dev/null +++ b/sim/soc/unisims/IDELAYCTRL.v @@ -0,0 +1,10 @@ +module IDELAYCTRL #( +)( + output RDY, + input REFCLK, + input RST +); + +assign RDY = !RST; +endmodule + diff --git a/sim/soc/unisims/IDELAYE2.v b/sim/soc/unisims/IDELAYE2.v new file mode 100644 index 0000000..bba7106 --- /dev/null +++ b/sim/soc/unisims/IDELAYE2.v @@ -0,0 +1,24 @@ +// wtf didn't check what it actually does! + +module IDELAYE2 #( + parameter CINVCTRL_SEL, + parameter DELAY_SRC, + parameter HIGH_PERFORMANCE_MODE, + parameter IDELAY_TYPE, + parameter IDELAY_VALUE, + parameter PIPE_SEL, + parameter REFCLK_FREQUENCY, + parameter SIGNAL_PATTERN +)( + input C, + input CE, + input IDATAIN, + input INC, + input LD, + input LDPIPEEN, + output DATAOUT +); + +assign DATAOUT = IDATAIN; +endmodule + diff --git a/sim/soc/unisims/IOBUF.v b/sim/soc/unisims/IOBUF.v new file mode 100644 index 0000000..26019e6 --- /dev/null +++ b/sim/soc/unisims/IOBUF.v @@ -0,0 +1,13 @@ +//wtf nop + +module IOBUF #( +) +( + input I, + input T, + inout IO, + inout O +); + +endmodule + diff --git a/sim/soc/unisims/IOBUFDS.v b/sim/soc/unisims/IOBUFDS.v new file mode 100644 index 0000000..cda585e --- /dev/null +++ b/sim/soc/unisims/IOBUFDS.v @@ -0,0 +1,13 @@ +//wtf nop + +module IOBUFDS #( +) +( + input I, + input T, + inout IO, + inout IOB +); + +endmodule + diff --git a/sim/soc/unisims/ISERDESE2.v b/sim/soc/unisims/ISERDESE2.v new file mode 100644 index 0000000..a79eb10 --- /dev/null +++ b/sim/soc/unisims/ISERDESE2.v @@ -0,0 +1,31 @@ +//wtf doesnt do nothin! + +module ISERDESE2 #( + parameter DATA_RATE, + parameter DATA_WIDTH, + parameter INTERFACE_TYPE, + parameter IOBDELAY, + parameter NUM_CE, + parameter SERDES_MODE +) +( + input BITSLIP, + input CE1, + input CLK, + input CLKB, + input CLKDIV, + input DDLY, + input RST, + output Q1, + output Q2, + output Q3, + output Q4, + output Q5, + output Q6, + output Q7, + output Q8 +); + + +endmodule + diff --git a/sim/soc/unisims/MMCME2_ADV.v b/sim/soc/unisims/MMCME2_ADV.v new file mode 100644 index 0000000..6a6b409 --- /dev/null +++ b/sim/soc/unisims/MMCME2_ADV.v @@ -0,0 +1,95 @@ +`timescale 1 ps / 1 ps + +module MMCME2_ADV #( + parameter BANDWIDTH = "OPTIMIZED", + parameter real CLKFBOUT_MULT_F = 5.000, + parameter real CLKFBOUT_PHASE = 0.000, + parameter CLKFBOUT_USE_FINE_PS = "FALSE", + parameter real CLKIN1_PERIOD = 0.000, + parameter real CLKIN2_PERIOD = 0.000, + parameter real CLKOUT0_DIVIDE_F = 1.000, + parameter real CLKOUT0_DUTY_CYCLE = 0.500, + parameter real CLKOUT0_PHASE = 0.000, + parameter CLKOUT0_USE_FINE_PS = "FALSE", + parameter integer CLKOUT1_DIVIDE = 1, + parameter real CLKOUT1_DUTY_CYCLE = 0.500, + parameter real CLKOUT1_PHASE = 0.000, + parameter CLKOUT1_USE_FINE_PS = "FALSE", + parameter integer CLKOUT2_DIVIDE = 1, + parameter real CLKOUT2_DUTY_CYCLE = 0.500, + parameter real CLKOUT2_PHASE = 0.000, + parameter CLKOUT2_USE_FINE_PS = "FALSE", + parameter integer CLKOUT3_DIVIDE = 1, + parameter real CLKOUT3_DUTY_CYCLE = 0.500, + parameter real CLKOUT3_PHASE = 0.000, + parameter CLKOUT3_USE_FINE_PS = "FALSE", + parameter CLKOUT4_CASCADE = "FALSE", + parameter integer CLKOUT4_DIVIDE = 1, + parameter real CLKOUT4_DUTY_CYCLE = 0.500, + parameter real CLKOUT4_PHASE = 0.000, + parameter CLKOUT4_USE_FINE_PS = "FALSE", + parameter integer CLKOUT5_DIVIDE = 1, + parameter real CLKOUT5_DUTY_CYCLE = 0.500, + parameter real CLKOUT5_PHASE = 0.000, + parameter CLKOUT5_USE_FINE_PS = "FALSE", + parameter integer CLKOUT6_DIVIDE = 1, + parameter real CLKOUT6_DUTY_CYCLE = 0.500, + parameter real CLKOUT6_PHASE = 0.000, + parameter CLKOUT6_USE_FINE_PS = "FALSE", + parameter COMPENSATION = "ZHOLD", + parameter integer DIVCLK_DIVIDE = 1, + parameter [0:0] IS_CLKINSEL_INVERTED = 1'b0, + parameter [0:0] IS_PSEN_INVERTED = 1'b0, + parameter [0:0] IS_PSINCDEC_INVERTED = 1'b0, + parameter [0:0] IS_PWRDWN_INVERTED = 1'b0, + parameter [0:0] IS_RST_INVERTED = 1'b0, + parameter real REF_JITTER1 = 0.010, + parameter real REF_JITTER2 = 0.010, + parameter SS_EN = "FALSE", + parameter SS_MODE = "CENTER_HIGH", + parameter integer SS_MOD_PERIOD = 10000, + parameter STARTUP_WAIT = "FALSE" +)( + output CLKFBOUT, + output CLKFBOUTB, + output CLKFBSTOPPED, + output CLKINSTOPPED, + output CLKOUT0, + output CLKOUT0B, + output CLKOUT1, + output CLKOUT1B, + output CLKOUT2, + output CLKOUT2B, + output CLKOUT3, + output CLKOUT3B, + output CLKOUT4, + output CLKOUT5, + output CLKOUT6, + output [15:0] DO, + output DRDY, + output LOCKED, + output PSDONE, + + input CLKFBIN, + input CLKIN1, + input CLKIN2, + input CLKINSEL, + input [6:0] DADDR, + input DCLK, + input DEN, + input [15:0] DI, + input DWE, + input PSCLK, + input PSEN, + input PSINCDEC, + input PWRDWN, + input RST +); + + assign CLKFBOUT = 1'b0; //feedback + assign CLKOUT0 = CLKIN1; + assign CLKOUT1 = CLKIN1; + assign CLKOUT2 = CLKIN1; + assign LOCKED = 1'b1; + +endmodule diff --git a/sim/soc/unisims/OBUFDS.v b/sim/soc/unisims/OBUFDS.v new file mode 100644 index 0000000..4addb10 --- /dev/null +++ b/sim/soc/unisims/OBUFDS.v @@ -0,0 +1,12 @@ +//wtf nop + +module OBUFDS #( +) +( + input I, + inout O, + inout OB +); + +endmodule + diff --git a/sim/soc/unisims/OSERDESE2.v b/sim/soc/unisims/OSERDESE2.v new file mode 100644 index 0000000..ebbc8d8 --- /dev/null +++ b/sim/soc/unisims/OSERDESE2.v @@ -0,0 +1,33 @@ +//wtf doesnt do nothin! + +module OSERDESE2 #( + parameter DATA_RATE_OQ, + parameter DATA_RATE_TQ, + parameter DATA_WIDTH, + parameter SERDES_MODE, + parameter TRISTATE_WIDTH +) +( + input CLK, + input CLKDIV, + input DDLY, + input RST, + input D1, + input D2, + input D3, + input D4, + input D5, + input D6, + input D7, + input D8, + input OCE, + input OFB, + input T1, + input TCE, + output OQ, + output TQ +); + + +endmodule + diff --git a/sim/soc/unisims/XADC.v b/sim/soc/unisims/XADC.v new file mode 100644 index 0000000..2d3247d --- /dev/null +++ b/sim/soc/unisims/XADC.v @@ -0,0 +1,93 @@ +`timescale 1ps / 1ps + +module XADC ( + ALM, + BUSY, + CHANNEL, + DO, + DRDY, + EOC, + EOS, + JTAGBUSY, + JTAGLOCKED, + JTAGMODIFIED, + MUXADDR, + OT, + CONVST, + CONVSTCLK, + DADDR, + DCLK, + DEN, + DI, + DWE, + RESET, + VAUXN, + VAUXP, + VN, + VP + +); + + output BUSY; + output DRDY; + output EOC; + output EOS; + output JTAGBUSY; + output JTAGLOCKED; + output JTAGMODIFIED; + output OT; + output [15:0] DO; + output [7:0] ALM; + output [4:0] CHANNEL; + output [4:0] MUXADDR; + + input CONVST; + input CONVSTCLK; + input DCLK; + input DEN; + input DWE; + input RESET; + input VN; + input VP; + input [15:0] DI; + input [15:0] VAUXN; + input [15:0] VAUXP; + input [6:0] DADDR; + + parameter [15:0] INIT_40 = 16'h0; + parameter [15:0] INIT_41 = 16'h0; + parameter [15:0] INIT_42 = 16'h0800; + parameter [15:0] INIT_43 = 16'h0; + parameter [15:0] INIT_44 = 16'h0; + parameter [15:0] INIT_45 = 16'h0; + parameter [15:0] INIT_46 = 16'h0; + parameter [15:0] INIT_47 = 16'h0; + parameter [15:0] INIT_48 = 16'h0; + parameter [15:0] INIT_49 = 16'h0; + parameter [15:0] INIT_4A = 16'h0; + parameter [15:0] INIT_4B = 16'h0; + parameter [15:0] INIT_4C = 16'h0; + parameter [15:0] INIT_4D = 16'h0; + parameter [15:0] INIT_4E = 16'h0; + parameter [15:0] INIT_4F = 16'h0; + parameter [15:0] INIT_50 = 16'h0; + parameter [15:0] INIT_51 = 16'h0; + parameter [15:0] INIT_52 = 16'h0; + parameter [15:0] INIT_53 = 16'h0; + parameter [15:0] INIT_54 = 16'h0; + parameter [15:0] INIT_55 = 16'h0; + parameter [15:0] INIT_56 = 16'h0; + parameter [15:0] INIT_57 = 16'h0; + parameter [15:0] INIT_58 = 16'h0; + parameter [15:0] INIT_59 = 16'h0; + parameter [15:0] INIT_5A = 16'h0; + parameter [15:0] INIT_5B = 16'h0; + parameter [15:0] INIT_5C = 16'h0; + parameter [15:0] INIT_5D = 16'h0; + parameter [15:0] INIT_5E = 16'h0; + parameter [15:0] INIT_5F = 16'h0; + + assign BUSY = 1'b0; + assign DRDY = 1'b1; + +endmodule \ No newline at end of file diff --git a/sim/soc/wbuart32 b/sim/soc/wbuart32 new file mode 120000 index 0000000..8de3a03 --- /dev/null +++ b/sim/soc/wbuart32 @@ -0,0 +1 @@ +/home/wtf/projects/wbuart32 \ No newline at end of file