From c070e89fed7bf81e7aff432df3554c90b2cc09e5 Mon Sep 17 00:00:00 2001 From: wtf <52765606+openpowerwtf@users.noreply.ggithub.com> Date: Sat, 20 Nov 2021 16:36:25 -0600 Subject: [PATCH] arci --- software/arci/refactor/arch.py | 143 ++++++++++++++ software/arci/refactor/arcigen.py | 193 +++++++++++++++++++ software/arci/refactor/arcitst.tpl | 280 ++++++++++++++++++++++++++++ software/arci/refactor/ops_add.py | 97 ++++++++++ software/arci/refactor/ops_div.py | 72 ++++++++ software/arci/refactor/simple2.s | 288 +++++++++++++++++++++++++++++ software/arci/refactor/simple2.tst | 139 ++++++++++++++ 7 files changed, 1212 insertions(+) create mode 100644 software/arci/refactor/arch.py create mode 100755 software/arci/refactor/arcigen.py create mode 100644 software/arci/refactor/arcitst.tpl create mode 100644 software/arci/refactor/ops_add.py create mode 100644 software/arci/refactor/ops_div.py create mode 100644 software/arci/refactor/simple2.s create mode 100644 software/arci/refactor/simple2.tst diff --git a/software/arci/refactor/arch.py b/software/arci/refactor/arch.py new file mode 100644 index 0000000..9175134 --- /dev/null +++ b/software/arci/refactor/arch.py @@ -0,0 +1,143 @@ + +from types import MethodType + +class Object(dict): + __getattr__ = dict.get + __setattr__ = dict.__setitem__ + __delattr__ = dict.__delitem__ + +class Facs(Object): + + def __init__(self): + + self.facs = Object() + + self.addFac('cia', 0x120000, spr=True, rname='CIA') + + def commentCR(self): + c = '* ' + x = f'{self.value:08X}' + for i in range(8): + c += f'F{i}:{x[i]} ' + return c + self.addFac('cr', 0, spr=True, rname='CR') + self.cr.comment = MethodType(commentCR, self.cr) + + def xerSO(self): + return (self.value & 0x80000000) >> 31 + self.addFac('xer', 0, spr=True, rname='XER') + self.xer.so = MethodType(xerSO, self.xer) + + self.addFac('ctr', 0xF0000000, spr=True, rname='CTR') + self.addFac('lr', 0, spr=True, rname='LR') + self.addFac('tar', 0, spr=True, rname='TAR') + + #self.srr0 = Fac('SRR0', 0, spr=True) + #self.srr1 = Fac('SRR1', 0, spr=True) + #self.dar = Fac('DAR', 0, spr=True) + #self.dsisr = Fac('DSISR',0, spr=True) + + self.gpr = {} + self.r0 = 'r0' + self.r1 = 'r1' + self.r2 = 'r2' + self.r3 = 'r3' + self.r4 = 'r4' + self.r5 = 'r5' + self.r6 = 'r6' + self.r7 = 'r7' + self.r8 = 'r8' + self.r9 = 'r9' + self.r10 = 'r10' + self.r11 = 'r11' + self.r12 = 'r12' + self.r13 = 'r13' + self.r14 = 'r14' + self.r15 = 'r15' + self.r16 = 'r16' + self.r17 = 'r17' + self.r18 = 'r18' + self.r19 = 'r19' + self.r20 = 'r20' + self.r21 = 'r21' + self.r22 = 'r22' + self.r23 = 'r23' + self.r24 = 'r24' + self.r25 = 'r25' + self.r26 = 'r26' + self.r27 = 'r27' + self.r28 = 'r28' + self.r29 = 'r29' + self.r30 = 'r30' + self.r31 = 'r31' + + def commentGPR(self): + if self.value >= 2**31: + neg = -((self.value ^ 0xFFFFFFFF) + 1) + return f'* {self.value:10} {neg:10}' + else: + return f'* {self.value:10}' + + for i in range(32): + #name = f'R{i:02}' + name = f'r{i}' + self.gpr[name] = Fac(name, 0, gpr=True, rname=f'R{i:02}') + self.gpr[name].comment = MethodType(commentGPR, self.gpr[name]) + + def addFac(self, name, value=None, spr=False, gpr=False, fpr=False, vsr=False, rname=None): + self[name] = Fac(name, value, spr, gpr, fpr, vsr, rname) + self.facs[name] = self[name] + + def all(self): + return self.facs.items() + +class Fac: + + def __init__(self, name, value=None, spr=False, gpr=False, fpr=False, vsr=False, rname=None): + self.name = name + self.rname = name if rname is None else rname + self.init = value + self.value = value + self.spr = spr + self.gpr = gpr + self.fpr = fpr + self.vsr = vsr + self.ref = False + self.chg = False + self.undefined = False # if allowed to generate, then if true needs to propagate to destination of succeeding ops + + def comment(self): + return '' + + def print(self, lines): + lines.append(f'R {self.rname:6} {self.value:08X}') + return self + + +class Op: + + def __init__(self, name): + self.name = name + ops[name] = self + + def fmt(self, val): + return f'{val:08X}' + + def se16(self, v): + v = v & 0xFFFF + if v > 0x7FFF: + v = 0xFFFF0000 + v + return v + + # has to also keep addresses since tst can be sparse when branching (to gen'd label) + def addToStream(self, ops): + ops.append(self.op) + return self + + def print(self, lines): + lines.append(f'I {self.cia:08X} {self.op}') + for i in range(len(self.res)): + lines.append(f'R {self.res[i][0]:6} {self.res[i][1]:08X} {self.res[i][2]}') + lines.append('') + return self + diff --git a/software/arci/refactor/arcigen.py b/software/arci/refactor/arcigen.py new file mode 100755 index 0000000..a85e78a --- /dev/null +++ b/software/arci/refactor/arcigen.py @@ -0,0 +1,193 @@ +#!/usr/bin/python3 +""" +© IBM Corp. 2020 +Licensed under the Apache License, Version 2.0 (the "License"), as modified by the terms below; you may not use the files in this +repository except in compliance with the License as modified. +You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0 + +Modified Terms: + + 1) For the purpose of the patent license granted to you in Section 3 of the License, the "Work" hereby includes implementations of + the work of authorship in physical form. + + 2) Notwithstanding any terms to the contrary in the License, any licenses necessary for implementation of the Work that are available + from OpenPOWER via the Power ISA End User License Agreement (EULA) are explicitly excluded hereunder, and may be obtained from OpenPOWER + under the terms and conditions of the EULA. + +Unless required by applicable law or agreed to in writing, the reference design distributed under the License is distributed on an +"AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language +governing permissions and limitations under the License. + +Additional rights, including the ability to physically implement a softcore that is compliant with the required sections of the Power +ISA Specification, are available at no cost under the terms of the OpenPOWER Power ISA EULA, which can be obtained (along with the Power +ISA) here: https://openpowerfoundation.org. + +Brief explanation of modifications: + +Modification 1: This modification extends the patent license to an implementation of the Work in physical form – i.e., +it unambiguously permits a user to make and use the physical chip. + +Modification 2: This modification clarifies that licenses for the Power ISA are provided via the (royalty-free) Power ISA EULA, +and not under this license. To prevent fragmentation of the Power ISA, the Power ISA EULA requires that Power ISA Cores be +licensed consistent with the terms of the Power ISA EULA. By ensuring that rights available via the Power ISA EULA are received +under (and subject to) the EULA, this consistency is maintained in accordance with the terms of the EULA. Any necessary additional +licenses for the specific Power ISA Core are granted under this modified Apache license. +""" + +from string import Template +import time +from ctypes import c_uint32 + +from arch import * +from ops_add import * +from ops_div import * + +# ------------------------------------------------------------------------------------------------- +# Initialization + +header = """ +* arci v.0.0001 +* ----------------------------------------------------------------------------------------- +""" +header += f'* Generated: {time.strftime("%b %d %Y %I:%M:%S %p %Z", time.gmtime())}\n' +header += '*\n' + +magic = "0x08675309" +savespr = "tar" + +tplFileAsm = 'arcitst.tpl' +tstName = 'simple2' +outFileTst = f'{tstName}.tst' +outFileAsm = f'{tstName}.s' + +# ------------------------------------------------------------------------------------------------- +# Process command line + + +# ------------------------------------------------------------------------------------------------- +# Helpers + +# def: print if nonzero +# all=True: print all +# ref=True: print only if referenced +# chg=True: print only if changed + +def printSPR(all=False, ref=None, chg=None): + + for k,f in facs.all(): + if f.spr: + n = f.rname + v = f.value + c = f.comment() + if all or (v != 0 and ref is None and chg is None) or (ref is not None and f.ref == ref) or (chg is not None and f.chg == chg): + lines.append(f'R {n:6} {v:08X} {c}') + + +def printRegs(all=False, ref=None, chg=None): + + for i in range(32): + g = facs.gpr[f'r{i}'] + n = g.rname + v = g.value + c = g.comment() + if all or (v != 0 and ref is None and chg is None) or (ref is not None and g.ref == ref) or (chg is not None and g.chg == chg): + lines.append(f'R {n:6} {v:08X} {c}') + +def printTest(): + + for i in range(len(lines)): + print(lines[i]) + +def genAsm(tplFile, asmFile): + + f = open(tplFile, 'r') + tplString = f.read() + tpl = Template(tplString) + + tstData = { + 'tst_name': tstName, + 'tst_info': 'wtf', + 'magic': magic, + 'savespr': savespr + } + + for k,f in facs.all(): + if f.spr: + tstData[f'init_{f.rname.lower()}'] = f'0x{f.init:08X}' + tstData[f'expt_{f.rname.lower()}'] = f'0x{f.value:08X}' + + gpr = facs.gpr + for i in range(32): + v = gpr[f'r{i}'].init + tstData[f'init_r{i}'] = f'0x{v:08X}' + v = gpr[f'r{i}'].value + tstData[f'expt_r{i}'] = f'0x{v:08X}' + + stream = '' + for i in range(len(ops)): + stream += f'\t\t\t{ops[i]}\n' + + tstData['stream'] = stream[0:-1] + + tpl = tpl.substitute(tstData) + + f = open(asmFile, "w") + f.write(tpl) + f.close() + +# ------------------------------------------------------------------------------------------------- +# Init + +facs = Facs() +lines = [] +ops = [] + +# ------------------------------------------------------------------------------------------------- +# Create ops + +facs.cia.ref = True +addi = Addi(facs) +add = Add(facs) +add_r = Add(facs, rc=True) +divw = DivW(facs) +divw_r = DivW(facs, rc= True) +divwo = DivW(facs, oe=True) +divwo_r = DivW(facs, rc=True, oe=True) + +# ------------------------------------------------------------------------------------------------- +# Do something + +lines.append(header) + +lines.append('* Initialization\n') +printSPR(all=True) +printRegs(all=True) + +lines.append('\n* Instructions\n') + +# phony dumb test +def addToTest(op): + op.addToStream(ops).print(lines) +addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines) +addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines) +addi.do(facs.r3,facs.r3,1).addToStream(ops).print(lines) +addi.do(facs.r4,facs.r0,-3).addToStream(ops).print(lines) +add_r.do(facs.r4,facs.r4,facs.r3).addToStream(ops).print(lines) +addi.do(facs.r6, facs.r0, 10).addToStream(ops).print(lines) +addi.do(facs.r7, facs.r0, -5).addToStream(ops).print(lines) +addToTest(divw.do(facs.r8, facs.r6, facs.r7)) +addToTest(divw_r.do(facs.r9, facs.r6, facs.r7)) + + +lines.append('\n* Results (Changed)\n') +printSPR(chg=True) +printRegs(chg=True) + +lines.append('\n* Results\n') +printSPR(all=True) +printRegs(all=True) + +# create .tst file +printTest() +# create .s file +genAsm(tplFileAsm, outFileAsm) diff --git a/software/arci/refactor/arcitst.tpl b/software/arci/refactor/arcitst.tpl new file mode 100644 index 0000000..b9f32be --- /dev/null +++ b/software/arci/refactor/arcitst.tpl @@ -0,0 +1,280 @@ +# architst + +.include "defines.s" + +# ------------------------------------------------------------------------------------------------- +# c-accessible + +.global init_tst +.global tst_start +.global tst_end +.global tst_inits +.global tst_results +.global tst_expects + +# ------------------------------------------------------------------------------------------------- +tst_misc: + +tst_name: .asciz "$tst_name" +tst_info: .asciz "$tst_info" + +.set SAVESPR,$savespr +.set MAGIC,$magic + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_inits: + +init_r0: .long $init_r0 +init_r1: .long $init_r1 +init_r2: .long $init_r2 +init_r3: .long $init_r3 +init_r4: .long $init_r4 +init_r5: .long $init_r5 +init_r6: .long $init_r6 +init_r7: .long $init_r7 +init_r8: .long $init_r8 +init_r9: .long $init_r9 +init_r10: .long $init_r10 +init_r11: .long $init_r11 +init_r12: .long $init_r12 +init_r13: .long $init_r13 +init_r14: .long $init_r14 +init_r15: .long $init_r15 +init_r16: .long $init_r16 +init_r17: .long $init_r17 +init_r18: .long $init_r18 +init_r19: .long $init_r19 +init_r20: .long $init_r20 +init_r21: .long $init_r21 +init_r22: .long $init_r22 +init_r23: .long $init_r23 +init_r24: .long $init_r24 +init_r25: .long $init_r25 +init_r26: .long $init_r26 +init_r27: .long $init_r27 +init_r28: .long $init_r28 +init_r29: .long $init_r29 +init_r30: .long $init_r30 +init_r31: .long $init_r31 + +init_cr: .long $init_cr +init_xer: .long $init_xer +init_ctr: .long $init_ctr +init_lr: .long $init_lr +init_tar: .long $init_tar + +save_r1: .long 0 + +# ------------------------------------------------------------------------------------------------- +# r3=@tst_inits +.align 5 +init_tst: + +# save c stuff + stw r1,(save_r1-tst_inits)(r3) + +# init test regs + lwz r1,(init_cr-tst_inits)(r3) + mtcr r1 + lwz r1,(init_xer-tst_inits)(r3) + mtxer r1 + lwz r1,(init_ctr-tst_inits)(r3) + mtctr r1 + lwz r1,(init_lr-tst_inits)(r3) + mtlr r1 + lwz r1,(init_tar-tst_inits)(r3) + mtspr tar,r1 + + lwz r0,(init_r0-tst_inits)(r3) + lwz r1,(init_r1-tst_inits)(r3) + lwz r2,(init_r2-tst_inits)(r3) + lwz r4,(init_r4-tst_inits)(r3) + lwz r5,(init_r5-tst_inits)(r3) + lwz r6,(init_r6-tst_inits)(r3) + lwz r7,(init_r7-tst_inits)(r3) + lwz r8,(init_r8-tst_inits)(r3) + lwz r9,(init_r9-tst_inits)(r3) + lwz r10,(init_r10-tst_inits)(r3) + lwz r11,(init_r11-tst_inits)(r3) + lwz r12,(init_r12-tst_inits)(r3) + lwz r13,(init_r13-tst_inits)(r3) + lwz r14,(init_r14-tst_inits)(r3) + lwz r15,(init_r15-tst_inits)(r3) + lwz r16,(init_r16-tst_inits)(r3) + lwz r17,(init_r17-tst_inits)(r3) + lwz r18,(init_r18-tst_inits)(r3) + lwz r19,(init_r19-tst_inits)(r3) + lwz r20,(init_r20-tst_inits)(r3) + lwz r21,(init_r21-tst_inits)(r3) + lwz r22,(init_r22-tst_inits)(r3) + lwz r23,(init_r23-tst_inits)(r3) + lwz r24,(init_r24-tst_inits)(r3) + lwz r25,(init_r25-tst_inits)(r3) + lwz r26,(init_r26-tst_inits)(r3) + lwz r27,(init_r27-tst_inits)(r3) + lwz r28,(init_r28-tst_inits)(r3) + lwz r29,(init_r29-tst_inits)(r3) + lwz r30,(init_r30-tst_inits)(r3) + lwz r31,(init_r31-tst_inits)(r3) + lwz r3,(init_r3-tst_inits)(r3) + + b tst_start + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_start: + +# ------------------------------------------------------------------------------------------------- +$stream +# ------------------------------------------------------------------------------------------------- + +tst_end: + b save_results + +# ------------------------------------------------------------------------------------------------- +.align 5 +save_results: +# use a designated spr to save (sprgx, ...) + mtspr SAVESPR,r1 + lis r1,tst_results@h + ori r1,r1,tst_results@l + stw r0,(rslt_r0-tst_results)(r1) + stw r2,(rslt_r2-tst_results)(r1) + stw r3,(rslt_r3-tst_results)(r1) + stw r4,(rslt_r4-tst_results)(r1) + stw r5,(rslt_r5-tst_results)(r1) + stw r6,(rslt_r6-tst_results)(r1) + stw r7,(rslt_r7-tst_results)(r1) + stw r8,(rslt_r8-tst_results)(r1) + stw r9,(rslt_r9-tst_results)(r1) + stw r10,(rslt_r10-tst_results)(r1) + stw r11,(rslt_r11-tst_results)(r1) + stw r12,(rslt_r12-tst_results)(r1) + stw r13,(rslt_r13-tst_results)(r1) + stw r14,(rslt_r14-tst_results)(r1) + stw r15,(rslt_r15-tst_results)(r1) + stw r16,(rslt_r16-tst_results)(r1) + stw r17,(rslt_r17-tst_results)(r1) + stw r18,(rslt_r18-tst_results)(r1) + stw r19,(rslt_r19-tst_results)(r1) + stw r20,(rslt_r20-tst_results)(r1) + stw r21,(rslt_r21-tst_results)(r1) + stw r22,(rslt_r22-tst_results)(r1) + stw r23,(rslt_r23-tst_results)(r1) + stw r24,(rslt_r24-tst_results)(r1) + stw r25,(rslt_r25-tst_results)(r1) + stw r26,(rslt_r26-tst_results)(r1) + stw r27,(rslt_r27-tst_results)(r1) + stw r28,(rslt_r28-tst_results)(r1) + stw r29,(rslt_r29-tst_results)(r1) + stw r30,(rslt_r30-tst_results)(r1) + stw r31,(rslt_r31-tst_results)(r1) + mfspr r2,SAVESPR + stw r2,(rslt_r1-tst_results)(r1) + mfcr r2 + stw r2,(rslt_cr-tst_results)(r1) + mfxer r2 + stw r2,(rslt_xer-tst_results)(r1) + mfctr r2 + stw r2,(rslt_ctr-tst_results)(r1) + mflr r2 + stw r2,(rslt_lr-tst_results)(r1) + mfspr r2,tar + stw r2,(rslt_tar-tst_results)(r1) + +tst_cleanup: +# restore c stuff + lis r3,tst_inits@h + ori r3,r3,tst_inits@l + lwz r1,(save_r1-tst_inits)(r3) + lis r3,MAGIC@h + ori r3,r3,MAGIC@l + + b tst_done + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_results: + +rslt_r0: .long 0xFFFFFFFF +rslt_r1: .long 0xFFFFFFFF +rslt_r2: .long 0xFFFFFFFF +rslt_r3: .long 0xFFFFFFFF +rslt_r4: .long 0xFFFFFFFF +rslt_r5: .long 0xFFFFFFFF +rslt_r6: .long 0xFFFFFFFF +rslt_r7: .long 0xFFFFFFFF +rslt_r8: .long 0xFFFFFFFF +rslt_r9: .long 0xFFFFFFFF +rslt_r10: .long 0xFFFFFFFF +rslt_r11: .long 0xFFFFFFFF +rslt_r12: .long 0xFFFFFFFF +rslt_r13: .long 0xFFFFFFFF +rslt_r14: .long 0xFFFFFFFF +rslt_r15: .long 0xFFFFFFFF +rslt_r16: .long 0xFFFFFFFF +rslt_r17: .long 0xFFFFFFFF +rslt_r18: .long 0xFFFFFFFF +rslt_r19: .long 0xFFFFFFFF +rslt_r20: .long 0xFFFFFFFF +rslt_r21: .long 0xFFFFFFFF +rslt_r22: .long 0xFFFFFFFF +rslt_r23: .long 0xFFFFFFFF +rslt_r24: .long 0xFFFFFFFF +rslt_r25: .long 0xFFFFFFFF +rslt_r26: .long 0xFFFFFFFF +rslt_r27: .long 0xFFFFFFFF +rslt_r28: .long 0xFFFFFFFF +rslt_r29: .long 0xFFFFFFFF +rslt_r30: .long 0xFFFFFFFF +rslt_r31: .long 0xFFFFFFFF + +rslt_cr: .long 0xFFFFFFFF +rslt_xer: .long 0xFFFFFFFF +rslt_ctr: .long 0xFFFFFFFF +rslt_lr: .long 0xFFFFFFFF +rslt_tar: .long 0xFFFFFFFF + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_expects: + +expt_r0: .long $expt_r0 +expt_r1: .long $expt_r1 +expt_r2: .long $expt_r2 +expt_r3: .long $expt_r3 +expt_r4: .long $expt_r4 +expt_r5: .long $expt_r5 +expt_r6: .long $expt_r6 +expt_r7: .long $expt_r7 +expt_r8: .long $expt_r8 +expt_r9: .long $expt_r9 +expt_r10: .long $expt_r10 +expt_r11: .long $expt_r11 +expt_r12: .long $expt_r12 +expt_r13: .long $expt_r13 +expt_r14: .long $expt_r14 +expt_r15: .long $expt_r15 +expt_r16: .long $expt_r16 +expt_r17: .long $expt_r17 +expt_r18: .long $expt_r18 +expt_r19: .long $expt_r19 +expt_r20: .long $expt_r20 +expt_r21: .long $expt_r21 +expt_r22: .long $expt_r22 +expt_r23: .long $expt_r23 +expt_r24: .long $expt_r24 +expt_r25: .long $expt_r25 +expt_r26: .long $expt_r26 +expt_r27: .long $expt_r27 +expt_r28: .long $expt_r28 +expt_r29: .long $expt_r29 +expt_r30: .long $expt_r30 +expt_r31: .long $expt_r31 + +expt_cr: .long $expt_cr +expt_xer: .long $expt_xer +expt_ctr: .long $expt_ctr +expt_lr: .long $expt_lr +expt_tar: .long $expt_tar diff --git a/software/arci/refactor/ops_add.py b/software/arci/refactor/ops_add.py new file mode 100644 index 0000000..94ef6c3 --- /dev/null +++ b/software/arci/refactor/ops_add.py @@ -0,0 +1,97 @@ +# def ADDI0 = M"001110-----00000----------------" // 67 ra=0 +# def ADDIa = M"001110-----1--------------------" // 67 +# def ADDIb = M"001110------1-------------------" // 67 +# def ADDIc = M"001110-------1------------------" // 67 +# def ADDId = M"001110--------1-----------------" // 67 +# def ADDIe = M"001110---------1----------------" // 67 +# def ADDIS0 = M"001111-----00000----------------" // 67 ra=0 +# def ADDISa = M"001111-----1--------------------" // 67 +# def ADDISb = M"001111------1-------------------" // 67 +# def ADDISc = M"001111-------1------------------" // 67 +# def ADDISd = M"001111--------1-----------------" // 67 +# def ADDISe = M"001111---------1----------------" // 67 +# def ADDPCIS = M"010011--------------------00010-" // 68 +# def ADD = M"011111----------------100001010-" // 69 add,add.,addo,addo. +# def ADDIC = M"001100--------------------------" // 69 +# def ADDICR = M"001101--------------------------" // 69 addic. +# def ADDC = M"011111----------------000001010-" // 70 addc,addc.,addco,addco. +# def ADDE = M"011111----------------010001010-" // 71 adde,adde.,addeo,addeo. +# def ADDME = M"011111----------------011101010-" // 71 addme,addme.,addmeo,addmeo. +# def ADDZE = M"011111----------------011001010-" // 72 addze,addze.,addzeo,addzeo. + +from arch import Op + +# not sure this is really needed +from ctypes import c_uint32 + +class Addi(Op): + + def __init__(self, facs): + self.name = 'addi' + self.facs = facs + + def do(self, rt, ra, v): + gpr = self.facs.gpr + cia = self.facs.cia + self.rt = rt + self.ra = ra + self.imm = v + v = self.se16(v) + if ra == 'r0': + res = c_uint32(v).value + else: + res = c_uint32(c_uint32(gpr[ra].value).value + v).value + gpr[ra].ref = True + gpr[rt].value = res + gpr[rt].chg = True + self.cia = cia.value + cia.value += 4 + self.nia = cia.value + cia.chg = True + self.op = f'{self.name:10s} {self.rt},{self.ra},{self.imm}' + self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment()),(cia.rname, self.nia, cia.comment())] + return self + +class Add(Op): + + def __init__(self, facs, rc=False): + self.rc = rc + if rc: + self.name = 'add.' + else: + self.name = 'add' + self.facs = facs + + def do(self, rt, ra, rb): + gpr = self.facs.gpr + cia = self.facs.cia + cr = self.facs.cr + xer = self.facs.xer + self.rt = rt + self.ra = ra + self.rb = rb + res = c_uint32(c_uint32(gpr[ra].value).value + c_uint32(gpr[rb].value).value).value + gpr[rt].value = res + gpr[ra].ref = True + gpr[rb].ref = True + gpr[rt].chg = True + if self.rc: + if res == 0: + cr0 = 0x2 + elif res >= 2**31: + cr0 = 0x8 + else: + cr0 = 0x4 + cr0 = cr0 | xer.so() + cr.value = (cr.value & 0x00FFFFFF) | (cr0 << 28) + cr.chg = True + self.cia = cia.value + cia.value += 4 + self.nia = cia.value + cia.chg = True + self.op = f'{self.name:10s} {self.rt},{self.ra},{self.rb}' + self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment())] + if self.rc: + self.res.append((cr.rname, cr.value, cr.comment())) + self.res.append((cia.rname, self.nia, cia.comment())) + return self diff --git a/software/arci/refactor/ops_div.py b/software/arci/refactor/ops_div.py new file mode 100644 index 0000000..902f39d --- /dev/null +++ b/software/arci/refactor/ops_div.py @@ -0,0 +1,72 @@ +# def DIVW = M"011111----------------111101011-" // 74 divw,divw.,divwo,divwo. +# def DIVWU = M"011111----------------111001011-" // 74 divwu,divwu.,divwuo,divwuo. +# def DIVWE = M"011111----------------110101011-" // 75 divwe,divwe.,divweo,divweo. +# def DIVWEU = M"011111----------------110001011-" // 75 divweu,divweu.,divweuo,divweuo. +# def MODSW = M"011111---------------1100001011-" // 76 +# def MODUW = M"011111---------------0100001011-" // 76 + +from arch import Op + +# not sure this is really needed +from ctypes import c_uint32, c_int32 + +class DivW(Op): + + def __init__(self, facs, rc=False, oe=False): + self.name = 'divw' + self.rc = rc + self.oe = oe + if oe: + self.name += 'o' + if rc: + self.name += '.' + self.facs = facs + + # needs to satisfy dividend=(quotient*divisor)+r, where + # 0 <= r < abs(divisor) if dividend is nonnegative, + # -abs(divisor) < r <= 0 if divident is negative + # plus, + # for 0x80000000 divided by -1 or anything divided by 0, rt and cr[lt,gt,zr] are undefined and if oe=1, ov=ov32=1; so need to check in case oe=1 + #wtf are these really the only cases that ov/so get set?? are they always 0 otherwise, or need to check carries??? + def do(self, rt, ra, rb): + gpr = self.facs.gpr + cia = self.facs.cia + cr = self.facs.cr + xer = self.facs.xer + self.rt = rt + self.ra = ra + self.rb = rb + res = c_uint32(c_int32(gpr[ra].value).value // c_int32(gpr[rb].value).value).value + gpr[rt].value = res + gpr[ra].ref = True + gpr[rb].ref = True + gpr[rt].chg = True + if self.rc: + if res == 0: + cr0 = 0x2 + elif res >= 2**31: + cr0 = 0x8 + else: + cr0 = 0x4 + cr0 = cr0 | xer.so() + cr.value = (cr.value & 0x00FFFFFF) | (cr0 << 28) + cr.chg = True + if self.oe: + if (gpr[rb] == 0 or (gpr[ra] == 0x80000000 and gpr[rb] == 0xFFFFFFFF)): + xer.so = 1 + xer.ov = 1 + gpr[rt].undefined = True + else: + xer.so = 0 + xer.ov = 0 + xer.chg = True + self.cia = cia.value + cia.value += 4 + self.nia = cia.value + cia.chg = True + self.op = f'{self.name:10s} {self.rt},{self.ra},{self.rb}' + self.res = [(gpr[rt].rname, gpr[rt].value, gpr[rt].comment())] + if self.rc: + self.res.append((cr.rname, cr.value, cr.comment())) + self.res.append((cia.rname, self.nia, cia.comment())) + return self diff --git a/software/arci/refactor/simple2.s b/software/arci/refactor/simple2.s new file mode 100644 index 0000000..697b654 --- /dev/null +++ b/software/arci/refactor/simple2.s @@ -0,0 +1,288 @@ +# architst + +.include "defines.s" + +# ------------------------------------------------------------------------------------------------- +# c-accessible + +.global init_tst +.global tst_start +.global tst_end +.global tst_inits +.global tst_results +.global tst_expects + +# ------------------------------------------------------------------------------------------------- +tst_misc: + +tst_name: .asciz "simple2" +tst_info: .asciz "wtf" + +.set SAVESPR,tar +.set MAGIC,0x08675309 + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_inits: + +init_r0: .long 0x00000000 +init_r1: .long 0x00000000 +init_r2: .long 0x00000000 +init_r3: .long 0x00000000 +init_r4: .long 0x00000000 +init_r5: .long 0x00000000 +init_r6: .long 0x00000000 +init_r7: .long 0x00000000 +init_r8: .long 0x00000000 +init_r9: .long 0x00000000 +init_r10: .long 0x00000000 +init_r11: .long 0x00000000 +init_r12: .long 0x00000000 +init_r13: .long 0x00000000 +init_r14: .long 0x00000000 +init_r15: .long 0x00000000 +init_r16: .long 0x00000000 +init_r17: .long 0x00000000 +init_r18: .long 0x00000000 +init_r19: .long 0x00000000 +init_r20: .long 0x00000000 +init_r21: .long 0x00000000 +init_r22: .long 0x00000000 +init_r23: .long 0x00000000 +init_r24: .long 0x00000000 +init_r25: .long 0x00000000 +init_r26: .long 0x00000000 +init_r27: .long 0x00000000 +init_r28: .long 0x00000000 +init_r29: .long 0x00000000 +init_r30: .long 0x00000000 +init_r31: .long 0x00000000 + +init_cr: .long 0x00000000 +init_xer: .long 0x00000000 +init_ctr: .long 0xF0000000 +init_lr: .long 0x00000000 +init_tar: .long 0x00000000 + +save_r1: .long 0 + +# ------------------------------------------------------------------------------------------------- +# r3=@tst_inits +.align 5 +init_tst: + +# save c stuff + stw r1,(save_r1-tst_inits)(r3) + +# init test regs + lwz r1,(init_cr-tst_inits)(r3) + mtcr r1 + lwz r1,(init_xer-tst_inits)(r3) + mtxer r1 + lwz r1,(init_ctr-tst_inits)(r3) + mtctr r1 + lwz r1,(init_lr-tst_inits)(r3) + mtlr r1 + lwz r1,(init_tar-tst_inits)(r3) + mtspr tar,r1 + + lwz r0,(init_r0-tst_inits)(r3) + lwz r1,(init_r1-tst_inits)(r3) + lwz r2,(init_r2-tst_inits)(r3) + lwz r4,(init_r4-tst_inits)(r3) + lwz r5,(init_r5-tst_inits)(r3) + lwz r6,(init_r6-tst_inits)(r3) + lwz r7,(init_r7-tst_inits)(r3) + lwz r8,(init_r8-tst_inits)(r3) + lwz r9,(init_r9-tst_inits)(r3) + lwz r10,(init_r10-tst_inits)(r3) + lwz r11,(init_r11-tst_inits)(r3) + lwz r12,(init_r12-tst_inits)(r3) + lwz r13,(init_r13-tst_inits)(r3) + lwz r14,(init_r14-tst_inits)(r3) + lwz r15,(init_r15-tst_inits)(r3) + lwz r16,(init_r16-tst_inits)(r3) + lwz r17,(init_r17-tst_inits)(r3) + lwz r18,(init_r18-tst_inits)(r3) + lwz r19,(init_r19-tst_inits)(r3) + lwz r20,(init_r20-tst_inits)(r3) + lwz r21,(init_r21-tst_inits)(r3) + lwz r22,(init_r22-tst_inits)(r3) + lwz r23,(init_r23-tst_inits)(r3) + lwz r24,(init_r24-tst_inits)(r3) + lwz r25,(init_r25-tst_inits)(r3) + lwz r26,(init_r26-tst_inits)(r3) + lwz r27,(init_r27-tst_inits)(r3) + lwz r28,(init_r28-tst_inits)(r3) + lwz r29,(init_r29-tst_inits)(r3) + lwz r30,(init_r30-tst_inits)(r3) + lwz r31,(init_r31-tst_inits)(r3) + lwz r3,(init_r3-tst_inits)(r3) + + b tst_start + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_start: + +# ------------------------------------------------------------------------------------------------- + addi r3,r3,1 + addi r3,r3,1 + addi r3,r3,1 + addi r4,r0,-3 + add. r4,r4,r3 + addi r6,r0,10 + addi r7,r0,-5 + divw r8,r6,r7 + divw. r9,r6,r7 +# ------------------------------------------------------------------------------------------------- + +tst_end: + b save_results + +# ------------------------------------------------------------------------------------------------- +.align 5 +save_results: +# use a designated spr to save (sprgx, ...) + mtspr SAVESPR,r1 + lis r1,tst_results@h + ori r1,r1,tst_results@l + stw r0,(rslt_r0-tst_results)(r1) + stw r2,(rslt_r2-tst_results)(r1) + stw r3,(rslt_r3-tst_results)(r1) + stw r4,(rslt_r4-tst_results)(r1) + stw r5,(rslt_r5-tst_results)(r1) + stw r6,(rslt_r6-tst_results)(r1) + stw r7,(rslt_r7-tst_results)(r1) + stw r8,(rslt_r8-tst_results)(r1) + stw r9,(rslt_r9-tst_results)(r1) + stw r10,(rslt_r10-tst_results)(r1) + stw r11,(rslt_r11-tst_results)(r1) + stw r12,(rslt_r12-tst_results)(r1) + stw r13,(rslt_r13-tst_results)(r1) + stw r14,(rslt_r14-tst_results)(r1) + stw r15,(rslt_r15-tst_results)(r1) + stw r16,(rslt_r16-tst_results)(r1) + stw r17,(rslt_r17-tst_results)(r1) + stw r18,(rslt_r18-tst_results)(r1) + stw r19,(rslt_r19-tst_results)(r1) + stw r20,(rslt_r20-tst_results)(r1) + stw r21,(rslt_r21-tst_results)(r1) + stw r22,(rslt_r22-tst_results)(r1) + stw r23,(rslt_r23-tst_results)(r1) + stw r24,(rslt_r24-tst_results)(r1) + stw r25,(rslt_r25-tst_results)(r1) + stw r26,(rslt_r26-tst_results)(r1) + stw r27,(rslt_r27-tst_results)(r1) + stw r28,(rslt_r28-tst_results)(r1) + stw r29,(rslt_r29-tst_results)(r1) + stw r30,(rslt_r30-tst_results)(r1) + stw r31,(rslt_r31-tst_results)(r1) + mfspr r2,SAVESPR + stw r2,(rslt_r1-tst_results)(r1) + mfcr r2 + stw r2,(rslt_cr-tst_results)(r1) + mfxer r2 + stw r2,(rslt_xer-tst_results)(r1) + mfctr r2 + stw r2,(rslt_ctr-tst_results)(r1) + mflr r2 + stw r2,(rslt_lr-tst_results)(r1) + mfspr r2,tar + stw r2,(rslt_tar-tst_results)(r1) + +tst_cleanup: +# restore c stuff + lis r3,tst_inits@h + ori r3,r3,tst_inits@l + lwz r1,(save_r1-tst_inits)(r3) + lis r3,MAGIC@h + ori r3,r3,MAGIC@l + + b tst_done + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_results: + +rslt_r0: .long 0xFFFFFFFF +rslt_r1: .long 0xFFFFFFFF +rslt_r2: .long 0xFFFFFFFF +rslt_r3: .long 0xFFFFFFFF +rslt_r4: .long 0xFFFFFFFF +rslt_r5: .long 0xFFFFFFFF +rslt_r6: .long 0xFFFFFFFF +rslt_r7: .long 0xFFFFFFFF +rslt_r8: .long 0xFFFFFFFF +rslt_r9: .long 0xFFFFFFFF +rslt_r10: .long 0xFFFFFFFF +rslt_r11: .long 0xFFFFFFFF +rslt_r12: .long 0xFFFFFFFF +rslt_r13: .long 0xFFFFFFFF +rslt_r14: .long 0xFFFFFFFF +rslt_r15: .long 0xFFFFFFFF +rslt_r16: .long 0xFFFFFFFF +rslt_r17: .long 0xFFFFFFFF +rslt_r18: .long 0xFFFFFFFF +rslt_r19: .long 0xFFFFFFFF +rslt_r20: .long 0xFFFFFFFF +rslt_r21: .long 0xFFFFFFFF +rslt_r22: .long 0xFFFFFFFF +rslt_r23: .long 0xFFFFFFFF +rslt_r24: .long 0xFFFFFFFF +rslt_r25: .long 0xFFFFFFFF +rslt_r26: .long 0xFFFFFFFF +rslt_r27: .long 0xFFFFFFFF +rslt_r28: .long 0xFFFFFFFF +rslt_r29: .long 0xFFFFFFFF +rslt_r30: .long 0xFFFFFFFF +rslt_r31: .long 0xFFFFFFFF + +rslt_cr: .long 0xFFFFFFFF +rslt_xer: .long 0xFFFFFFFF +rslt_ctr: .long 0xFFFFFFFF +rslt_lr: .long 0xFFFFFFFF +rslt_tar: .long 0xFFFFFFFF + +# ------------------------------------------------------------------------------------------------- +.align 5 +tst_expects: + +expt_r0: .long 0x00000000 +expt_r1: .long 0x00000000 +expt_r2: .long 0x00000000 +expt_r3: .long 0x00000003 +expt_r4: .long 0x00000000 +expt_r5: .long 0x00000000 +expt_r6: .long 0x0000000A +expt_r7: .long 0xFFFFFFFB +expt_r8: .long 0xFFFFFFFE +expt_r9: .long 0xFFFFFFFE +expt_r10: .long 0x00000000 +expt_r11: .long 0x00000000 +expt_r12: .long 0x00000000 +expt_r13: .long 0x00000000 +expt_r14: .long 0x00000000 +expt_r15: .long 0x00000000 +expt_r16: .long 0x00000000 +expt_r17: .long 0x00000000 +expt_r18: .long 0x00000000 +expt_r19: .long 0x00000000 +expt_r20: .long 0x00000000 +expt_r21: .long 0x00000000 +expt_r22: .long 0x00000000 +expt_r23: .long 0x00000000 +expt_r24: .long 0x00000000 +expt_r25: .long 0x00000000 +expt_r26: .long 0x00000000 +expt_r27: .long 0x00000000 +expt_r28: .long 0x00000000 +expt_r29: .long 0x00000000 +expt_r30: .long 0x00000000 +expt_r31: .long 0x00000000 + +expt_cr: .long 0x80000000 +expt_xer: .long 0x00000000 +expt_ctr: .long 0xF0000000 +expt_lr: .long 0x00000000 +expt_tar: .long 0x00000000 diff --git a/software/arci/refactor/simple2.tst b/software/arci/refactor/simple2.tst new file mode 100644 index 0000000..0c927fc --- /dev/null +++ b/software/arci/refactor/simple2.tst @@ -0,0 +1,139 @@ + +* arci v.0.0001 +* ----------------------------------------------------------------------------------------- +* Generated: Nov 20 2021 10:34:56 PM GMT +* + +* Initialization + +R CIA 00120000 +R CR 00000000 * F0:0 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0 +R XER 00000000 +R CTR F0000000 +R LR 00000000 +R TAR 00000000 +R R00 00000000 * 0 +R R01 00000000 * 0 +R R02 00000000 * 0 +R R03 00000000 * 0 +R R04 00000000 * 0 +R R05 00000000 * 0 +R R06 00000000 * 0 +R R07 00000000 * 0 +R R08 00000000 * 0 +R R09 00000000 * 0 +R R10 00000000 * 0 +R R11 00000000 * 0 +R R12 00000000 * 0 +R R13 00000000 * 0 +R R14 00000000 * 0 +R R15 00000000 * 0 +R R16 00000000 * 0 +R R17 00000000 * 0 +R R18 00000000 * 0 +R R19 00000000 * 0 +R R20 00000000 * 0 +R R21 00000000 * 0 +R R22 00000000 * 0 +R R23 00000000 * 0 +R R24 00000000 * 0 +R R25 00000000 * 0 +R R26 00000000 * 0 +R R27 00000000 * 0 +R R28 00000000 * 0 +R R29 00000000 * 0 +R R30 00000000 * 0 +R R31 00000000 * 0 + +* Instructions + +I 00120000 addi r3,r3,1 +R R03 00000001 * 1 +R CIA 00120004 + +I 00120004 addi r3,r3,1 +R R03 00000002 * 2 +R CIA 00120008 + +I 00120008 addi r3,r3,1 +R R03 00000003 * 3 +R CIA 0012000C + +I 0012000C addi r4,r0,-3 +R R04 FFFFFFFD * 4294967293 -3 +R CIA 00120010 + +I 00120010 add. r4,r4,r3 +R R04 00000000 * 0 +R CR 20000000 * F0:2 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0 +R CIA 00120014 + +I 00120014 addi r6,r0,10 +R R06 0000000A * 10 +R CIA 00120018 + +I 00120018 addi r7,r0,-5 +R R07 FFFFFFFB * 4294967291 -5 +R CIA 0012001C + +I 0012001C divw r8,r6,r7 +R R08 FFFFFFFE * 4294967294 -2 +R CIA 00120020 + +I 00120020 divw. r9,r6,r7 +R R09 FFFFFFFE * 4294967294 -2 +R CR 80000000 * F0:8 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0 +R CIA 00120024 + + +* Results (Changed) + +R CIA 00120024 +R CR 80000000 * F0:8 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0 +R R03 00000003 * 3 +R R04 00000000 * 0 +R R06 0000000A * 10 +R R07 FFFFFFFB * 4294967291 -5 +R R08 FFFFFFFE * 4294967294 -2 +R R09 FFFFFFFE * 4294967294 -2 + +* Results + +R CIA 00120024 +R CR 80000000 * F0:8 F1:0 F2:0 F3:0 F4:0 F5:0 F6:0 F7:0 +R XER 00000000 +R CTR F0000000 +R LR 00000000 +R TAR 00000000 +R R00 00000000 * 0 +R R01 00000000 * 0 +R R02 00000000 * 0 +R R03 00000003 * 3 +R R04 00000000 * 0 +R R05 00000000 * 0 +R R06 0000000A * 10 +R R07 FFFFFFFB * 4294967291 -5 +R R08 FFFFFFFE * 4294967294 -2 +R R09 FFFFFFFE * 4294967294 -2 +R R10 00000000 * 0 +R R11 00000000 * 0 +R R12 00000000 * 0 +R R13 00000000 * 0 +R R14 00000000 * 0 +R R15 00000000 * 0 +R R16 00000000 * 0 +R R17 00000000 * 0 +R R18 00000000 * 0 +R R19 00000000 * 0 +R R20 00000000 * 0 +R R21 00000000 * 0 +R R22 00000000 * 0 +R R23 00000000 * 0 +R R24 00000000 * 0 +R R25 00000000 * 0 +R R26 00000000 * 0 +R R27 00000000 * 0 +R R28 00000000 * 0 +R R29 00000000 * 0 +R R30 00000000 * 0 +R R31 00000000 * 0