wtf 1 year ago
parent
commit
e511aaf9ef
  1. 8
      build/openroad/.gitignore
  2. 467
      build/openroad/Makefile-STA
  3. 2358
      build/openroad/allrams_100.log
  4. 2436
      build/openroad/allrams_40.log
  5. 21
      build/openroad/config.mk
  6. 27
      build/openroad/constraint.sdc
  7. BIN
      build/openroad/imaynotbea10buttheboyssayicleanupgood.png
  8. 7
      build/openroad/litex/.gitignore
  9. 1
      build/openroad/litex/a2p/__init__.py
  10. 5
      build/openroad/litex/a2p/boot-helper.S
  11. 145
      build/openroad/litex/a2p/core.py
  12. 0
      build/openroad/litex/a2p/csr-defs.h
  13. 18
      build/openroad/litex/a2p/irq.h
  14. 55
      build/openroad/litex/a2p/system.h
  15. 14185
      build/openroad/litex/a2p/verilog/A2P_WB.v
  16. 14087
      build/openroad/litex/a2p/verilog/A2P_WB_no_byps.v
  17. 14185
      build/openroad/litex/a2p/verilog/A2P_WB_no_cr_byp.v
  18. 14185
      build/openroad/litex/a2p/verilog/A2P_WB_normal.v
  19. 274
      build/openroad/litex/a2p_site.py
  20. 79
      build/openroad/litex/build/caravel_user/gateware/caravel_user.tcl
  21. 2357
      build/openroad/litex/build/caravel_user/gateware/caravel_user.v
  22. 1623
      build/openroad/litex/build/caravel_user/gateware/caravel_user.xdc
  23. 42
      build/openroad/litex/build/caravel_user/gateware/mem.init
  24. 591
      build/openroad/litex/build/caravel_user/software/include/generated/csr.h
  25. 9
      build/openroad/litex/build/caravel_user/software/include/generated/git.h
  26. 20
      build/openroad/litex/build/caravel_user/software/include/generated/mem.h
  27. 1
      build/openroad/litex/build/caravel_user/software/include/generated/output_format.ld
  28. 4
      build/openroad/litex/build/caravel_user/software/include/generated/regions.ld
  29. 55
      build/openroad/litex/build/caravel_user/software/include/generated/soc.h
  30. 25
      build/openroad/litex/build/caravel_user/software/include/generated/variables.mak
  31. 2357
      build/openroad/litex/caravel_user.v
  32. 49
      build/openroad/litex/config.mk
  33. 32
      build/openroad/litex/constraint.sdc
  34. 59
      build/openroad/litex/csr.csv
  35. 42
      build/openroad/litex/mem.init
  36. 102
      build/openroad/litex/modules/issiram.py
  37. 362
      build/openroad/litex/modules/issiram.v
  38. 80312
      build/openroad/litex/output/logs/1_1_yosys.log
  39. 2
      build/openroad/litex/output/logs/2_1_floorplan.json
  40. 328
      build/openroad/litex/output/logs/2_1_floorplan.log
  41. 2
      build/openroad/litex/output/logs/2_2_floorplan_io.json
  42. 28
      build/openroad/litex/output/logs/2_2_floorplan_io.log
  43. 2
      build/openroad/litex/output/logs/2_3_tdms.json
  44. 28
      build/openroad/litex/output/logs/2_3_tdms_place.log
  45. 2
      build/openroad/litex/output/logs/2_4_mplace.json
  46. 28
      build/openroad/litex/output/logs/2_4_mplace.log
  47. 2
      build/openroad/litex/output/logs/2_5_tapcell.json
  48. 29
      build/openroad/litex/output/logs/2_5_tapcell.log
  49. 2
      build/openroad/litex/output/logs/2_6_pdn.json
  50. 47
      build/openroad/litex/output/logs/2_6_pdn.log
  51. 2
      build/openroad/litex/output/logs/3_1_place_gp.json
  52. 519
      build/openroad/litex/output/logs/3_1_place_gp.log
  53. 2
      build/openroad/litex/output/logs/3_2_place_iop.json
  54. 39
      build/openroad/litex/output/logs/3_2_place_iop.log
  55. 2
      build/openroad/litex/output/logs/3_3_resizer.json
  56. 76320
      build/openroad/litex/output/logs/3_3_resizer.log
  57. 2
      build/openroad/litex/output/logs/3_4_opendp.json
  58. 76127
      build/openroad/litex/output/logs/3_4_opendp.log
  59. 2
      build/openroad/litex/output/logs/4_1_cts.json
  60. 309740
      build/openroad/litex/output/logs/4_1_cts.log
  61. 2
      build/openroad/litex/output/logs/4_2_cts_fillcell.json
  62. 29
      build/openroad/litex/output/logs/4_2_cts_fillcell.log
  63. 2
      build/openroad/litex/output/logs/5_1_fastroute.json
  64. 79552
      build/openroad/litex/output/logs/5_1_fastroute.log
  65. 4
      build/openroad/litex/output/logs/5_2_TritonRoute.json
  66. 1488
      build/openroad/litex/output/logs/5_2_TritonRoute.log
  67. 42
      build/openroad/litex/output/logs/6_1_merge.log
  68. 2
      build/openroad/litex/output/logs/6_report.json
  69. 79272
      build/openroad/litex/output/logs/6_report.log
  70. 0
      build/openroad/litex/output/reports/5_route_drc.rpt
  71. 4
      build/openroad/litex/output/reports/antenna.log
  72. BIN
      build/openroad/litex/output/reports/final.webp.png
  73. BIN
      build/openroad/litex/output/reports/final_clocks.webp.png
  74. BIN
      build/openroad/litex/output/reports/final_placement.webp.png
  75. BIN
      build/openroad/litex/output/reports/final_resizer.webp.png
  76. 77786
      build/openroad/litex/output/reports/synth_check.txt
  77. 154
      build/openroad/litex/output/reports/synth_stat.txt
  78. 0
      build/openroad/litex/platforms/__init__.py
  79. 124
      build/openroad/litex/platforms/caravel_user.py
  80. 80
      build/openroad/litex/platforms/virtual.py
  81. 33
      build/openroad/litex/readme.md
  82. 123
      build/openroad/litex/src/user_project_wrapper.v
  83. 393
      build/openroad/log.py
  84. 3594
      build/openroad/logs/clk_100/1_1_yosys.log
  85. 2
      build/openroad/logs/clk_100/2_1_floorplan.json
  86. 335
      build/openroad/logs/clk_100/2_1_floorplan.log
  87. 2
      build/openroad/logs/clk_100/2_2_floorplan_io.json
  88. 21
      build/openroad/logs/clk_100/2_2_floorplan_io.log
  89. 2
      build/openroad/logs/clk_100/2_3_tdms.json
  90. 18
      build/openroad/logs/clk_100/2_3_tdms_place.log
  91. 2
      build/openroad/logs/clk_100/2_4_mplace.json
  92. 18
      build/openroad/logs/clk_100/2_4_mplace.log
  93. 2
      build/openroad/logs/clk_100/2_5_tapcell.json
  94. 22
      build/openroad/logs/clk_100/2_5_tapcell.log
  95. 2
      build/openroad/logs/clk_100/2_6_pdn.json
  96. 41
      build/openroad/logs/clk_100/2_6_pdn.log
  97. 2
      build/openroad/logs/clk_100/3_1_place_gp.json
  98. 492
      build/openroad/logs/clk_100/3_1_place_gp.log
  99. 2
      build/openroad/logs/clk_100/3_2_place_iop.json
  100. 33
      build/openroad/logs/clk_100/3_2_place_iop.log
  101. Some files were not shown because too many files have changed in this diff Show More

8
build/openroad/.gitignore vendored

@ -1 +1,7 @@ @@ -1 +1,7 @@
dffram/
dffram/
*.def
*.gds
*.guide
*.spef
*.lef
*.mod

467
build/openroad/Makefile-STA

@ -0,0 +1,467 @@ @@ -0,0 +1,467 @@
# wtf partial make for synth/timing only

export SCRIPTS_DIR = ./scripts

SYNTH_SCRIPT ?= $(SCRIPTS_DIR)/synth.tcl

FLOORPLAN_SCRIPT ?= $(SCRIPTS_DIR)/floorplan.tcl
IO_PLACE_RANDOM_SCRIPT ?= $(SCRIPTS_DIR)/io_placement_random.tcl
TDMS_SCRIPT ?= $(SCRIPTS_DIR)/tdms_place.tcl
MACRO_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/macro_place.tcl

IO_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/io_placement.tcl
GLOBAL_PLACE_SCRIPT ?= $(SCRIPTS_DIR)/global_place.tcl
RESIZE_SCRIPT ?= $(SCRIPTS_DIR)/resize.tcl

RUN_ALL_SCRIPT ?= $(SCRIPTS_DIR)/run_all.tcl
FINAL_REPORT_SCRIPT ?= $(SCRIPTS_DIR)/final_report.tcl


# # Global override Floorplan
# export CORE_UTILIZATION := 30
# export CORE_ASPECT_RATIO := 1
# export CORE_MARGIN := 4

default: finish

# ==============================================================================
# ____ _____ _____ _ _ ____
# / ___|| ____|_ _| | | | _ \
# \___ \| _| | | | | | | |_) |
# ___) | |___ | | | |_| | __/
# |____/|_____| |_| \___/|_|
#
# ==============================================================================

# Include design and platform configuration
include $(DESIGN_CONFIG)

PUBLIC=nangate45 sky130hd sky130hs asap7

ifneq ($(wildcard $(PLATFORM_BASE)/$(PLATFORM)),)
export PLATFORM_DIR = $(PLATFORM_BASE)/$(PLATFORM)
else ifneq ($(findstring $(PLATFORM),$(PUBLIC)),)
export PLATFORM_DIR = ./platforms/$(PLATFORM)
else ifneq ($(wildcard ../../$(PLATFORM)),)
export PLATFORM_DIR = ../../$(PLATFORM)
else
$(error [ERROR][FLOW] Platform '$(PLATFORM)' not found)
endif

$(info [INFO][FLOW] Using platform directory $(PLATFORM_DIR))
include $(PLATFORM_DIR)/config.mk

export FLOW_VARIANT ?= base

# Setup working directories
export DESIGN_NICKNAME ?= $(DESIGN_NAME)

export LOG_DIR = ./logs/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export OBJECTS_DIR = ./objects/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export REPORTS_DIR = ./reports/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)
export RESULTS_DIR = ./results/$(PLATFORM)/$(DESIGN_NICKNAME)/$(FLOW_VARIANT)

export UTILS_DIR = ./util
export TEST_DIR = ./test

# Tool Options
SHELL = /bin/bash -o pipefail

TIME_CMD = /usr/bin/time -f "%Eelapsed %PCPU %MmemKB"
TIME_TEST = $(shell $(TIME_CMD) echo foo 2>/dev/null)
ifeq (, $(strip $(TIME_TEST)))
TIME_CMD = /usr/bin/time
endif

ifeq (, $(strip $(NPROC)))
# Linux (utility program)
NPROC := $(shell nproc 2>/dev/null)

ifeq (, $(strip $(NPROC)))
# Linux (generic)
NPROC := $(shell grep -c ^processor /proc/cpuinfo 2>/dev/null)
endif
ifeq (, $(strip $(NPROC)))
# BSD (at least FreeBSD and Mac OSX)
NPROC := $(shell sysctl -n hw.ncpu 2>/dev/null)
endif
ifeq (, $(strip $(NPROC)))
# Fallback
NPROC := 1
endif
endif
export NUM_CORES := $(NPROC)

OPENROAD_CMD = openroad -no_init -exit
OPENROAD_NO_EXIT_CMD = $(patsubst -exit,,$(OPENROAD_CMD))

WRAPPED_LEFS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/lef/$(lef:.lef=_mod.lef))
WRAPPED_LIBS = $(foreach lib,$(notdir $(WRAP_LIBS)),$(OBJECTS_DIR)/$(lib:.lib=_mod.lib))
export ADDITIONAL_LEFS += $(WRAPPED_LEFS) $(WRAP_LEFS)
export LIB_FILES += $(WRAP_LIBS) $(WRAPPED_LIBS)

export DONT_USE_LIBS = $(addprefix $(OBJECTS_DIR)/lib/, $(notdir $(LIB_FILES)))
export DONT_USE_SC_LIB ?= $(OBJECTS_DIR)/lib/$(notdir $(firstword $(LIB_FILES)))

# Stream system used for final result (GDS is default): GDS, GSDII, GDS2, OASIS, or OAS
STREAM_SYSTEM ?= GDS
ifneq ($(findstring GDS,$(shell echo $(STREAM_SYSTEM) | tr '[:lower:]' '[:upper:]')),)
export STREAM_SYSTEM_EXT := gds
GDSOAS_FILES = $(GDS_FILES)
ADDITIONAL_GDSOAS = $(ADDITIONAL_GDS)
SEAL_GDSOAS = $(SEAL_GDS)
else
export STREAM_SYSTEM_EXT := oas
GDSOAS_FILES = $(OAS_FILES)
ADDITIONAL_GDSOAS = $(ADDITIONAL_OAS)
SEAL_GDSOAS = $(SEAL_OAS)
endif
export WRAPPED_GDSOAS = $(foreach lef,$(notdir $(WRAP_LEFS)),$(OBJECTS_DIR)/$(lef:.lef=_mod.$(STREAM_SYSTEM_EXT)))

# Utility to print tool version information
#-------------------------------------------------------------------------------
.PHONY: versions.txt
versions.txt:
@yosys -V > $@
@echo openroad `$(firstword $(OPENROAD_CMD)) -version` >> $@
@klayout -zz -v >> $@

# Pre-process libraries
# ==============================================================================

# Create temporary Liberty files which have the proper dont_use properties set
# For use with Yosys and ABC
.SECONDEXPANSION:
$(DONT_USE_LIBS): $$(filter %$$(@F),$(LIB_FILES))
@mkdir -p $(OBJECTS_DIR)/lib
$(UTILS_DIR)/markDontUse.py -p "$(DONT_USE_CELLS)" -i $^ -o $@

$(OBJECTS_DIR)/lib/merged.lib:
$(UTILS_DIR)/mergeLib.pl $(PLATFORM)_merged $(DONT_USE_LIBS) > $@

# Pre-process KLayout tech
# ==============================================================================
#$(OBJECTS_DIR)/klayout_tech.lef: $(TECH_LEF)
# @mkdir -p $(OBJECTS_DIR)
# sed '/OR_DEFAULT/d' $< > $@

# $(OBJECTS_DIR)/klayout.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
# sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(SC_LEF) $(ADDITIONAL_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@

#$(OBJECTS_DIR)/klayout_wrap.lyt: $(KLAYOUT_TECH_FILE) $(OBJECTS_DIR)/klayout_tech.lef
# sed 's,<lef-files>.*</lef-files>,$(foreach file, $(OBJECTS_DIR)/klayout_tech.lef $(WRAP_LEFS),<lef-files>$(abspath $(file))</lef-files>),g' $< > $@
# Create Macro wrappers (if necessary)
# ==============================================================================
#WRAP_CFG = $(PLATFORM_DIR)/wrapper.cfg

export TCLLIBPATH := util/cell-veneer $(TCLLIBPATH)
$(WRAPPED_LEFS):
mkdir -p $(OBJECTS_DIR)/lef $(OBJECTS_DIR)/def
util/cell-veneer/wrap.tcl -cfg $(WRAP_CFG) -macro $(filter %$(notdir $(@:_mod.lef=.lef)),$(WRAP_LEFS))
mv $(notdir $@) $@
mv $(notdir $(@:lef=def)) $(dir $@)../def/$(notdir $(@:lef=def))

$(WRAPPED_LIBS):
mkdir -p $(OBJECTS_DIR)/lib
sed 's/library(\(.*\))/library(\1_mod)/g' $(filter %$(notdir $(@:_mod.lib=.lib)),$(WRAP_LIBS)) | sed 's/cell(\(.*\))/cell(\1_mod)/g' > $@

# ==============================================================================
# ______ ___ _ _____ _ _ _____ ____ ___ ____
# / ___\ \ / / \ | |_ _| | | | ____/ ___|_ _/ ___|
# \___ \\ V /| \| | | | | |_| | _| \___ \| |\___ \
# ___) || | | |\ | | | | _ | |___ ___) | | ___) |
# |____/ |_| |_| \_| |_| |_| |_|_____|____/___|____/
#
synth: versions.txt \
$(RESULTS_DIR)/1_synth.v \
$(RESULTS_DIR)/1_synth.sdc
# ==============================================================================


# Run Synthesis using yosys
#-------------------------------------------------------------------------------

$(RESULTS_DIR)/1_1_yosys.v: $(DONT_USE_LIBS) $(WRAPPED_LIBS) $(DONT_USE_SC_LIB) $(VERILOG_FILES)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
($(TIME_CMD) yosys -c $(SYNTH_SCRIPT)) 2>&1 | tee $(LOG_DIR)/1_1_yosys.log

$(RESULTS_DIR)/1_synth.v: $(RESULTS_DIR)/1_1_yosys.v
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
cp $< $@

$(RESULTS_DIR)/1_synth.sdc: $(SDC_FILE)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
cp $< $@

clean_synth:
rm -f $(RESULTS_DIR)/1_*.v $(RESULTS_DIR)/1_synth.sdc
rm -f $(REPORTS_DIR)/synth_*
rm -f $(LOG_DIR)/1_*
rm -rf _tmp_yosys-abc-*


# ==============================================================================
# _____ _ ___ ___ ____ ____ _ _ _ _
# | ___| | / _ \ / _ \| _ \| _ \| | / \ | \ | |
# | |_ | | | | | | | | | |_) | |_) | | / _ \ | \| |
# | _| | |__| |_| | |_| | _ <| __/| |___ / ___ \| |\ |
# |_| |_____\___/ \___/|_| \_\_| |_____/_/ \_\_| \_|
#
floorplan: $(RESULTS_DIR)/2_floorplan.def \
$(RESULTS_DIR)/2_floorplan.sdc
# ==============================================================================


# STEP 1: Translate verilog to def
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_1_floorplan.def: $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(TECH_LEF) $(SC_LEF) $(ADDITIONAL_LEFS) $(FOOTPRINT) $(SIG_MAP_FILE)
($(TIME_CMD) $(OPENROAD_CMD) $(FLOORPLAN_SCRIPT) -metrics $(LOG_DIR)/2_1_floorplan.json) 2>&1 | tee $(LOG_DIR)/2_1_floorplan.log


# STEP 2: IO Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_2_floorplan_io.def: $(RESULTS_DIR)/2_1_floorplan.def $(IO_CONSTRAINTS)
($(TIME_CMD) $(OPENROAD_CMD) $(IO_PLACE_RANDOM_SCRIPT) -metrics $(LOG_DIR)/2_2_floorplan_io.json) 2>&1 | tee $(LOG_DIR)/2_2_floorplan_io.log

# STEP 3: Timing Driven Mixed Sized Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_3_floorplan_tdms.def: $(RESULTS_DIR)/2_2_floorplan_io.def $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(LIB_FILES)
($(TIME_CMD) $(OPENROAD_CMD) $(TDMS_SCRIPT) -metrics $(LOG_DIR)/2_3_tdms.json) 2>&1 | tee $(LOG_DIR)/2_3_tdms_place.log

# STEP 4: Macro Placement
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/2_4_floorplan_macro.def: $(RESULTS_DIR)/2_3_floorplan_tdms.def $(RESULTS_DIR)/1_synth.v $(RESULTS_DIR)/1_synth.sdc $(MACRO_PLACEMENT)
($(TIME_CMD) $(OPENROAD_CMD) $(MACRO_PLACE_SCRIPT) -metrics $(LOG_DIR)/2_4_mplace.json) 2>&1 | tee $(LOG_DIR)/2_4_mplace.log

# STEP 5: Tapcell and Welltie insertion
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/2_5_floorplan_tapcell.def: $(RESULTS_DIR)/2_4_floorplan_macro.def $(TAPCELL_TCL)
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/tapcell.tcl -metrics $(LOG_DIR)/2_5_tapcell.json) 2>&1 | tee $(LOG_DIR)/2_5_tapcell.log

# STEP 6: PDN generation
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/2_6_floorplan_pdn.def: $(RESULTS_DIR)/2_5_floorplan_tapcell.def $(PDN_CFG)
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/pdn.tcl -metrics $(LOG_DIR)/2_6_pdn.json) 2>&1 | tee $(LOG_DIR)/2_6_pdn.log

#$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_6_floorplan_pdn.def
# cp $< $@

#$(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.def

#$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_3_floorplan_tdms.def
# cp $< $@
$(RESULTS_DIR)/2_floorplan.def: $(RESULTS_DIR)/2_4_floorplan_macro.def
cp $< $@

$(RESULTS_DIR)/2_floorplan.sdc: $(RESULTS_DIR)/2_1_floorplan.def

clean_floorplan:
rm -f $(RESULTS_DIR)/2_*floorplan*.def $(RESULTS_DIR)/2_floorplan.sdc $(RESULTS_DIR)/2_floorplan.v
rm -f $(REPORTS_DIR)/2_*
rm -f $(LOG_DIR)/2_*

# ==============================================================================
# ____ _ _ ____ _____
# | _ \| | / \ / ___| ____|
# | |_) | | / _ \| | | _|
# | __/| |___ / ___ \ |___| |___
# |_| |_____/_/ \_\____|_____|
#
place: $(RESULTS_DIR)/3_place.def \
$(RESULTS_DIR)/3_place.sdc
# ==============================================================================

#wtf this only runs if there are macros
# STEP 1: Global placement + IO placement (not random)
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/3_1_place_gp.def: $(RESULTS_DIR)/2_floorplan.def $(RESULTS_DIR)/2_floorplan.sdc $(LIB_FILES)
($(TIME_CMD) $(OPENROAD_CMD) $(GLOBAL_PLACE_SCRIPT) -metrics $(LOG_DIR)/3_1_place_gp.json) 2>&1 | tee $(LOG_DIR)/3_1_place_gp.log

# STEP 2: IO placement (non-random)
#-------------------------------------------------------------------------------
$(RESULTS_DIR)/3_2_place_iop.def: $(RESULTS_DIR)/3_1_place_gp.def $(IO_CONSTRAINTS)
($(TIME_CMD) $(OPENROAD_CMD) $(IO_PLACE_SCRIPT) -metrics $(LOG_DIR)/3_2_place_iop.json) 2>&1 | tee $(LOG_DIR)/3_2_place_iop.log

# STEP 3: Resizing & Buffering
#-------------------------------------------------------------------------------
#wtf use above steps
#$(RESULTS_DIR)/3_3_place_resized.def: $(RESULTS_DIR)/3_2_place_iop.def $(RESULTS_DIR)/2_floorplan.sdc
# ($(TIME_CMD) $(OPENROAD_CMD) $(RESIZE_SCRIPT) -metrics $(LOG_DIR)/3_3_resizer.json) 2>&1 | tee $(LOG_DIR)/3_3_resizer.log
#wtf just use fp
$(RESULTS_DIR)/3_3_place_resized.def: $(RESULTS_DIR)/2_floorplan.def $(RESULTS_DIR)/2_floorplan.sdc
($(TIME_CMD) $(OPENROAD_CMD) $(RESIZE_SCRIPT) -metrics $(LOG_DIR)/3_3_resizer.json) 2>&1 | tee $(LOG_DIR)/3_3_resizer.log


clean_resize:
rm -f $(RESULTS_DIR)/3_3_place_resized.def

# STEP 4: Detail placement
#-------------------------------------------------------------------------------
#$(RESULTS_DIR)/3_4_place_dp.def: $(RESULTS_DIR)/3_3_place_resized.def
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/detail_place.tcl -metrics $(LOG_DIR)/3_4_opendp.json) 2>&1 | tee $(LOG_DIR)/3_4_opendp.log

$(RESULTS_DIR)/3_place.def: $(RESULTS_DIR)/3_3_place_resized.def
cp $< $@

$(RESULTS_DIR)/3_place.sdc: $(RESULTS_DIR)/2_floorplan.sdc
cp $< $@

# Clean Targets
#-------------------------------------------------------------------------------
clean_place:
rm -f $(RESULTS_DIR)/3_*place*.def
rm -f $(RESULTS_DIR)/3_place.sdc
rm -f $(REPORTS_DIR)/3_*
rm -f $(LOG_DIR)/3_*

# ==============================================================================
# _____ ___ _ _ ___ ____ _ _ ___ _ _ ____
# | ___|_ _| \ | |_ _/ ___|| | | |_ _| \ | |/ ___|
# | |_ | || \| || |\___ \| |_| || || \| | | _
# | _| | || |\ || | ___) | _ || || |\ | |_| |
# |_| |___|_| \_|___|____/|_| |_|___|_| \_|\____|
#

6_FINAL_FILE = $(RESULTS_DIR)/6_final.$(STREAM_SYSTEM_EXT)
#finish: $(LOG_DIR)/6_report.log \
# $(RESULTS_DIR)/6_final.v \
# $(6_FINAL_FILE)
finish: $(LOG_DIR)/6_report.log \
$(RESULTS_DIR)/2_floorplan.v

# ==============================================================================

#ifneq ($(USE_FILL),)
#$(RESULTS_DIR)/6_1_fill.def: $(RESULTS_DIR)/5_route.def
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/density_fill.tcl -metrics $(LOG_DIR)/6_density_fill.json) 2>&1 | tee $(LOG_DIR)/6_density_fill.log
#else
#$(RESULTS_DIR)/6_1_fill.def: $(RESULTS_DIR)/5_route.def
# cp $< $@
#endif
#
#$(RESULTS_DIR)/6_1_fill.sdc: $(RESULTS_DIR)/5_route.sdc
# cp $< $@
#
#$(LOG_DIR)/6_report.log: $(RESULTS_DIR)/6_1_fill.def $(RESULTS_DIR)/6_1_fill.sdc
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/final_report.tcl -metrics $(LOG_DIR)/6_report.json) 2>&1 | tee $(LOG_DIR)/6_report.log
$(LOG_DIR)/6_report.log: $(RESULTS_DIR)/3_place.def $(RESULTS_DIR)/3_place.sdc
($(TIME_CMD) $(OPENROAD_CMD) $(FINAL_REPORT_SCRIPT) -metrics $(LOG_DIR)/6_report.json) 2>&1 | tee $(LOG_DIR)/6_report.log

#
#$(RESULTS_DIR)/6_final.def: $(LOG_DIR)/6_report.log
#
# Merge wrapped macros using Klayout
#-------------------------------------------------------------------------------
#$(WRAPPED_GDSOAS): $(OBJECTS_DIR)/klayout_wrap.lyt $(WRAPPED_LEFS)
# ($(TIME_CMD) klayout -zz -rd design_name=$(basename $(notdir $@)) \
# -rd in_def=$(OBJECTS_DIR)/def/$(notdir $(@:$(STREAM_SYSTEM_EXT)=def)) \
# -rd in_files="$(ADDITIONAL_GDSOAS)" \
# -rd config_file=$(FILL_CONFIG) \
# -rd seal_file="" \
# -rd out_file=$@ \
# -rd tech_file=$(OBJECTS_DIR)/klayout_wrap.lyt \
# -rm $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_merge_$(basename $(notdir $@)).log
#
# Merge GDS using Klayout
#-------------------------------------------------------------------------------
#6_1_MERGED_FILE = $(RESULTS_DIR)/6_1_merged.$(STREAM_SYSTEM_EXT)
#$(6_1_MERGED_FILE): $(RESULTS_DIR)/6_final.def $(OBJECTS_DIR)/klayout.lyt $(GDSOAS_FILES) $(WRAPPED_GDSOAS)
# ($(TIME_CMD) stdbuf -o L klayout -zz -rd design_name=$(DESIGN_NAME) \
# -rd in_def=$< \
# -rd in_files="$(GDSOAS_FILES) $(WRAPPED_GDSOAS)" \
# -rd config_file=$(FILL_CONFIG) \
# -rd seal_file="$(SEAL_GDSOAS)" \
# -rd out_file=$@ \
# -rd tech_file=$(OBJECTS_DIR)/klayout.lyt \
# -rm $(UTILS_DIR)/def2stream.py) 2>&1 | tee $(LOG_DIR)/6_1_merge.log
#
#$(RESULTS_DIR)/6_final.v: $(LOG_DIR)/6_report.log
#
#$(6_FINAL_FILE): $(6_1_MERGED_FILE)
# cp $^ $@
#
#drc: $(REPORTS_DIR)/6_drc.lyrdb
#
#$(REPORTS_DIR)/6_drc.lyrdb: $(6_FINAL_FILE) $(KLAYOUT_DRC_FILE)
#ifneq ($(KLAYOUT_DRC_FILE),)
# ($(TIME_CMD) klayout -zz -rd in_gds="$<" \
# -rd report_file=$(abspath $@) \
# -r $(KLAYOUT_DRC_FILE)) 2>&1 | tee $(LOG_DIR)/6_drc.log
# # Hacky way of getting DRV count (don't error on no matches)
# grep -c "<value>" $@ > $(REPORTS_DIR)/6_drc_count.rpt || [[ $$? == 1 ]]
#else
# echo "DRC not supported on this platform" > $@
#endif
#
#$(RESULTS_DIR)/6_final.cdl: $(RESULTS_DIR)/6_final.v
# ($(TIME_CMD) $(OPENROAD_CMD) $(SCRIPTS_DIR)/cdl.tcl) 2>&1 | tee $(LOG_DIR)/6_cdl.log
#
#$(OBJECTS_DIR)/6_final_concat.cdl: $(RESULTS_DIR)/6_final.cdl $(CDL_FILE)
# cat $^ > $@
#
#lvs: $(RESULTS_DIR)/6_lvs.lvsdb
#
#$(RESULTS_DIR)/6_lvs.lvsdb: $(6_FINAL_FILE) $(KLAYOUT_LVS_FILE) $(OBJECTS_DIR)/6_final_concat.cdl
#ifneq ($(KLAYOUT_LVS_FILE),)
# ($(TIME_CMD) klayout -b -rd in_gds="$<" \
# -rd cdl_file=$(abspath $(OBJECTS_DIR)/6_final_concat.cdl) \
# -rd report_file=$(abspath $@) \
# -r $(KLAYOUT_LVS_FILE)) 2>&1 | tee $(LOG_DIR)/6_lvs.log
#else
# echo "LVS not supported on this platform" > $@
#endif

clean_finish:
rm -rf $(RESULTS_DIR)/6_*.gds $(RESULTS_DIR)/6_*.oas $(RESULTS_DIR)/6_*.def $(RESULTS_DIR)/6_*.v $(RESULTS_DIR)/6_*.sdc
rm -rf $(REPORTS_DIR)/6_*.rpt
rm -f $(LOG_DIR)/6_*


# ==============================================================================
# __ __ ___ ____ ____
# | \/ |_ _/ ___| / ___|
# | |\/| || |\___ \| |
# | | | || | ___) | |___
# |_| |_|___|____/ \____|
#
# ==============================================================================

all: $(SDC_FILE) $(WRAPPED_LIBS) $(DONT_USE_LIBS) $(OBJECTS_DIR)/klayout.lyt $(WRAPPED_GDSOAS)
mkdir -p $(RESULTS_DIR) $(LOG_DIR) $(REPORTS_DIR)
($(TIME_CMD) $(OPENROAD_CMD) $(RUN_ALL_SCRIPT) -metrics $(LOG_DIR)/run_all.json) 2>&1 | tee $(LOG_DIR)/run_all.log

clean:
@echo
@echo "Make clean disabled."
@echo "Use make clean_all or clean individual steps:"
@echo " clean_synth clean_floorplan clean_place clean_cts clean_route clean_finish"
@echo

clean_all: clean_synth clean_floorplan clean_place clean_cts clean_route clean_finish
rm -rf $(OBJECTS_DIR)

nuke: clean_test clean_issues
rm -rf ./results ./logs ./reports ./objects
rm -rf layer_*.mps macrocell.list *best.plt *_pdn.def dummy.guide
rm -rf *.rpt *.rpt.old *.def.v pin_dumper.log
rm -rf versions.txt


# DEF/GDS/OAS viewer shortcuts
#-------------------------------------------------------------------------------
RESULTS_DEF = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.def)))
RESULTS_GDS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.gds)))
RESULTS_OAS = $(notdir $(sort $(wildcard $(RESULTS_DIR)/*.oas)))
$(foreach file,$(RESULTS_DEF) $(RESULTS_GDS) $(RESULTS_OAS),klayout_$(file)): klayout_%: $(OBJECTS_DIR)/klayout.lyt
klayout -nn $(OBJECTS_DIR)/klayout.lyt $(RESULTS_DIR)/$*

gui_final: gui_6_final.def

$(foreach file,$(RESULTS_DEF),gui_$(file)): gui_%:
DEF_FILE=$(RESULTS_DIR)/$* $(OPENROAD_NO_EXIT_CMD) -gui $(SCRIPTS_DIR)/gui.tcl

# Utilities
#-------------------------------------------------------------------------------
include $(UTILS_DIR)/utils.mk
export PRIVATE_DIR = ../../private_tool_scripts
-include $(PRIVATE_DIR)/util/utils.mk

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build/openroad/allrams_40.log

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21
build/openroad/config.mk

@ -3,8 +3,8 @@ export DESIGN_NICKNAME = a2p @@ -3,8 +3,8 @@ export DESIGN_NICKNAME = a2p
export DESIGN_NAME = A2P_WB
export PLATFORM = sky130hd

export VERILOG_FILES = $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
export SDC_FILE = ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc
export VERILOG_FILES := $(sort $(wildcard ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/src/*.v))
export SDC_FILE := ./designs/$(PLATFORM)/$(DESIGN_NICKNAME)/constraint.sdc

$(info Source files:)
$(info $(VERILOG_FILES))
@ -25,4 +25,21 @@ export SYNTH_MAX_TRAN ?= 100 @@ -25,4 +25,21 @@ export SYNTH_MAX_TRAN ?= 100

export REPORT_SLACK_MAX_PATHS ?= 100

#HACK! uniquify logs, objects, reports, results
export DESIGN_NICKNAME := $(DESIGN_NICKNAME)/output/$(shell date "+%Y%m%d%H%M%S")
$(info [WTF] Output Dirs: $(DESIGN_NICKNAME))


# ----------------------------------------------------------------------------------
# ----------------------------------------------------------------------------------
# CTS

# forget about this for now - occurred when added dffram dir/caches. anton says hold misses are fake anyway :)
# do i need something else from dffram build?
# Repair hold violations...
# [INFO RSZ-0046] Found 60472 endpoints with hold violations.
# [WARNING RSZ-0066] Unable to repair all hold violations.
# [INFO RSZ-0032] Inserted 213923 hold buffers.
# [ERROR DPL-0019] detailed placement failed on hold33177
# continue if cts wants to barf...
export WTF_CTS_IGNORE_HOLD_MISSES = 1

27
build/openroad/constraint.sdc

@ -1,23 +1,32 @@ @@ -1,23 +1,32 @@
# A2P single-core with DFFRAM gpr, icdir, icdata, dcdir, dcdata

# ----------------------------------------------------------------------------------
# define clock

set clk_name clk
# make it easy
set clk_period 50.0
# set clk_period 50.0 ;# make it easy for or
#set clk_period 10.0 ;# 100Mhz
#set clk_period 25.0 ;# 40Mhz
set clk_period 40.0 ;# 25Mhz

set input_delay_value 1
set output_delay_value 1
puts "\[WTF\] clk_period=$clk_period"

# define clock
set clkPort [get_ports $clk_name]
create_clock $clkPort -name clk -period $clk_period

# ----------------------------------------------------------------------------------
# apply clock to ins and outs

set input_delay_value 0.0
set output_delay_value 0.0 ;# what is this? rat? or period-rat? i think 0 is 'easiest'

set clk_index [lsearch [all_inputs] $clkPort]
set all_inputs_wo_clk [lreplace [all_inputs] $clk_index $clk_index]
set_input_delay $input_delay_value -clock [get_clocks clk] $all_inputs_wo_clk
set_output_delay $output_delay_value -clock [get_clocks clk] [all_outputs]

# ----------------------------------------------------------------------------------
# false paths
set_false_path -from [get_ports {reset}] -to [get_clocks clk]

#wtf - is this the dc write path? lots of fo
#set_false_path -from [get_nets {dBusWB_ACK}]
#causes [ERROR STA-0467] unsupported object type Net
set_false_path -from [get_ports {reset}] -to [get_clocks clk]
set_false_path -from [get_ports {externalResetVector}] -to [get_clocks clk]

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7
build/openroad/litex/.gitignore vendored

@ -0,0 +1,7 @@ @@ -0,0 +1,7 @@
dffram/
*.def
*.gds
*.guide
*.spef
*.lef
*.mod

1
build/openroad/litex/a2p/__init__.py

@ -0,0 +1 @@ @@ -0,0 +1 @@
from .core import A2P

5
build/openroad/litex/a2p/boot-helper.S

@ -0,0 +1,5 @@ @@ -0,0 +1,5 @@
.section .text, "ax", @progbits

.global boot_helper
boot_helper:
blr

145
build/openroad/litex/a2p/core.py

@ -0,0 +1,145 @@ @@ -0,0 +1,145 @@

import os

from migen import *

from litex import get_data_mod
from litex.soc.interconnect import wishbone
from litex.soc.interconnect.csr import *
from litex.soc.cores.cpu import CPU

dir = os.path.dirname(os.path.realpath(__file__))

# these select the top RTL file for each variant name
CPU_VARIANTS = {
'AXI': 'A2P_AXI',
'WB': 'A2P_WB',
'standard': 'A2P_WB' #wtf litex does this as default
}

GCC_FLAGS = {
'WB' : '-fomit-frame-pointer -Wall -fno-builtin -nostdinc -fno-stack-protector -fexceptions -Wstrict-prototypes -Wold-style-definition -Wmissing-prototypes'
}

class A2P(CPU, AutoCSR):
name = 'a2p'
human_name = 'a2p'
family = 'ppc32'
variants = CPU_VARIANTS
data_width = 32
endianness = 'big'
gcc_triple = 'powerpc-linux-gnu'
linker_output_format = 'elf32-powerpc'
nop = 'nop'
io_regions = {0x80000000: 0x80000000} # origin, length

@property
def mem_map(self):
return {
'rom': 0x00000000,
'sram': 0x00004000,
'main_ram': 0x40000000,
'csr': 0xf0000000,
}

@property
def gcc_flags(self):
flags = GCC_FLAGS[self.variant]
flags += " -D__a2p__"
return flags

def __init__(self, platform, variant='WB'):

if variant == 'standard':
variant = 'WB'

self.platform = platform
self.variant = variant
self.human_name = CPU_VARIANTS.get(variant, 'A2P')
self.external_variant = None
self.reset = Signal()
self.interrupt = Signal(32)
self.interruptS = Signal()
self.ibus = ibus = wishbone.Interface()
self.dbus = dbus = wishbone.Interface()
self.periph_buses = [ibus, dbus]
self.memory_buses = []
self.enableDebug = False
self.enableJTAG = False
self.externalResetVector = 0

# # #

self.cpu_params = dict(
i_clk = ClockSignal(),
i_reset = ResetSignal() | self.reset,

i_externalInterrupt = self.interrupt[0],
i_externalInterruptS = self.interruptS,
i_timerInterrupt = 0,
i_softwareInterrupt = 0,

o_iBusWB_ADR = ibus.adr,
o_iBusWB_DAT_MOSI = ibus.dat_w,
o_iBusWB_SEL = ibus.sel,
o_iBusWB_CYC = ibus.cyc,
o_iBusWB_STB = ibus.stb,
o_iBusWB_WE = ibus.we,
o_iBusWB_CTI = ibus.cti,
o_iBusWB_BTE = ibus.bte,
i_iBusWB_DAT_MISO = ibus.dat_r,
i_iBusWB_ACK = ibus.ack,
i_iBusWB_ERR = ibus.err,

o_dBusWB_ADR = dbus.adr,
o_dBusWB_DAT_MOSI = dbus.dat_w,
o_dBusWB_SEL = dbus.sel,
o_dBusWB_CYC = dbus.cyc,
o_dBusWB_STB = dbus.stb,
o_dBusWB_WE = dbus.we,
o_dBusWB_CTI = dbus.cti,
o_dBusWB_BTE = dbus.bte,
i_dBusWB_DAT_MISO = dbus.dat_r,
i_dBusWB_ACK = dbus.ack,
i_dBusWB_ERR = dbus.err
)

self.cpu_params['i_externalResetVector'] = self.externalResetVector

# these need to connect to top nets
if self.enableDebug:
self.cpu_params['i_debugReset'] = 0
self.cpu_params['o_debug_resetOut'] = 0
self.cpu_params['i_debug_bus_cmd_valid'] = 0
self.cpu_params['i_debug_bus_cmd_ready'] = 0
self.cpu_params['i_debug_bus_cmd_payload_wr'] = 0
self.cpu_params['i_debug_bus_cmd_payload_address'] = 0
self.cpu_params['i_debug_bus_cmd_payload_data'] = 0
self.cpu_params['o_debug_bus_rsp_data'] = 0

if self.enableJTAG:
self.cpu_params['i_jtag_tms'] = 0
self.cpu_params['i_jtag_tck'] = 0
self.cpu_params['i_jtag_tdi'] = 0
self.cpu_params['o_jtag_tdo'] = 0

def set_reset_address(self, reset_address):
assert not hasattr(self, "reset_address")
self.reset_address = reset_address
self.cpu_params.update(i_externalResetVector=Signal(32, reset=reset_address))

@staticmethod
def add_sources(platform, variant="WB"):
cpu_filename = CPU_VARIANTS[variant] + ".v"
vdir = os.path.join(dir, 'verilog')
platform.add_source(os.path.join(vdir, cpu_filename))

def use_external_variant(self, variant_filename):
self.external_variant = True
self.platform.add_source(variant_filename)

def do_finalize(self):
assert hasattr(self, "reset_address")
if not self.external_variant:
self.add_sources(self.platform, self.variant)
self.specials += Instance("A2P_WB", **self.cpu_params)

0
build/openroad/litex/a2p/csr-defs.h

18
build/openroad/litex/a2p/irq.h

@ -0,0 +1,18 @@ @@ -0,0 +1,18 @@
#ifndef __IRQ_H
#define __IRQ_H

static inline void irq_setmask(unsigned int mask) {
}

static inline unsigned int irq_getmask(void) {
return 0;
}

static inline unsigned int irq_pending(void) {
return 0;
}

static inline void irq_setie(unsigned int mask) {
}

#endif

55
build/openroad/litex/a2p/system.h

@ -0,0 +1,55 @@ @@ -0,0 +1,55 @@
// swizzlin

#ifndef __SYSTEM_H
#define __SYSTEM_H

#include <stdint.h>

/*
void flush_l2_cache(void) {
}
*/
static void flush_cpu_icache(void);
static void flush_cpu_dcache(void);

static void flush_cpu_icache(void) {
}
static void flush_cpu_dcache(void) {
}

#define CSR_ACCESSORS_DEFINED

#ifdef __ASSEMBLER__
#define MMPTR(x) x
#else /* ! __ASSEMBLER__ */

#include <generated/soc.h>
#if !defined(CONFIG_CSR_DATA_WIDTH)
#error CSR_DATA_WIDTH MUST be set before including this file!
#endif

#define MMPTR(a) (*((volatile uint32_t *)(a)))

static inline unsigned long swizzle(unsigned long v);

static inline unsigned long swizzle(unsigned long v) {
return ((v & 0x000000FF) << 24) | ((v & 0x0000FF00) << 8) | ((v & 0x00FF0000) >> 8) | ((v & 0xFF000000) >> 24);
//return v;
}

static inline void csr_write_simple(unsigned long v, unsigned long a)
{
//MMPTR(a) = v;
MMPTR(a) = swizzle(v);
}

static inline unsigned long csr_read_simple(unsigned long a)
{
//return MMPTR(a);
return swizzle(MMPTR(a));
}

#endif /* ! __ASSEMBLER__ */

#endif /* __SYSTEM_H */

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build/openroad/litex/a2p/verilog/A2P_WB_no_byps.v

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build/openroad/litex/a2p/verilog/A2P_WB_no_cr_byp.v

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274
build/openroad/litex/a2p_site.py

@ -0,0 +1,274 @@ @@ -0,0 +1,274 @@
#!/usr/bin/python3

# A2P Caravel Site Test
# python3 a2p_site.py
#
# 1 or 2 cores
# Manager (wb is only slave)
# Async RAM interface ** won't work - only half of io can be outputs **
# use custom serial interface ~ 8 pins, 4B/32B packets
# UARTs
# I2C
# special-purpose GPIO
# Mgmt interface
# Beer on tap

import os
import argparse

from migen import *

# wtf - use local platform
from platforms import caravel_user

# wtf - use local core
# help python find package
import sys
binPath = os.path.dirname(os.path.realpath(__file__))
sys.path.append(os.path.join(binPath, 'a2p'))
# get core def
from a2p import A2P
# add to litex dict
from litex.soc.cores import cpu
cpu.CPUS['a2p'] = A2P

# local modules
sys.path.append(os.path.join(binPath, 'modules'))

from litex.soc.integration.soc import colorer
from litex.soc.integration.soc import SoCRegion
from litex.soc.integration.soc_core import *
from litex.soc.integration.soc_sdram import *
from litex.soc.integration.builder import *

from litex.soc.cores.led import LedChaser
from litex.soc.cores.gpio import GPIOIn
from litex.soc.cores.gpio import GPIOOut
from litex.soc.cores.bitbang import I2CMaster

from litex.soc.interconnect import wishbone
from litex.soc.interconnect import csr

from litex.soc.cores.uart import UART
from litex.soc.cores.uart import RS232PHY

# possibly use octspi with a memory controller to send/rcv 32b/128b data with header and crc?
#from litespi.common import *
#from litespi.phy.generic_sdr import LiteSPISDRPHYCore
#from litespi.phy.generic_ddr import LiteSPIDDRPHYCore


# BaseSoC ------------------------------------------------------------------------------------------

from litex.soc.interconnect import wishbone

def _to_signal(obj):
return obj.raw_bits() if isinstance(obj, Record) else obj

class BaseSoC(SoCCore):

def __init__(self, sys_clk_freq=50e6, uart_baudrate=115200, **kwargs):

platform = caravel_user.Platform()

SoCCore.__init__(self, platform, 50e6, sys_clk_freq=50e6, cpu_type='a2p',
csr_data_width=32, with_uart=False, integrated_sram_size=0, integrated_rom_size=0,
ident='A2P Caravel Site Test', ident_version=True)

# no irq yet
self.add_constant('UART_POLLING')

self.mem_map = {
'csr': 0xFFF00000,
'sram': 0x00000000,
'mgmt': 0xE0000000
}


# I/O connections --------------------------------------------------------------------------
# clk is connected by platform
# make these exist even if unconnected so i/o are defined

# --- clk/rst
#self.sys_rst = Signal() #this creates sys_rst_1
#self.comb += self.int_rst.eq(platform.request('wb_rst_i')) no idea how to connect to top level sigs that are magically gen'd
# apprarently they give you a few things useful!
self.sys_rst = ResetSignal()
self.comb += self.sys_rst.eq(platform.request('wb_rst_i'))
# but gens some whack logic
# always @(*) begin
# sys_rst <= 1'd0;
# sys_rst <= wb_rst_i;
# sys_rst <= int_rst;
# end

self.user_clock2 = Signal()
self.comb += self.user_clock2.eq(platform.request('user_clock2'))

# --- wb
# options:
# * unused
# * user area is slave (config/test only)
# * user area is master/slave - not possible - NO MASTER SIGS!!!

# slave interface for mgmt macro (core controls, etc.); could hang csr off it and interface through them
# i suppose then you could let the csr be read/written by both sides, so you could do some polled mailbox messaging; probs could proxy i/o through pico
# they would have to be r/w by 2 different wb's
self.wb_mgmt = wishbone.Interface()
self.wb_io = Record([('cyc', 1), ('stb', 1), ('we', 1), ('sel', 4), ('adr', 32), ('ack', 1), ('dat_r', 32), ('dat_w', 32),
('cti', 1), ('bte', 32), ('err', 1)])
self.wb_io.cyc = platform.request('wbs_cyc_i')
self.wb_io.stb = platform.request('wbs_stb_i')
self.wb_io.we = platform.request('wbs_we_i')
self.wb_io.sel = platform.request('wbs_sel_i')
self.wb_io.adr = platform.request('wbs_adr_i')
self.wb_io.ack = platform.request('wbs_ack_o')
self.wb_io.dat_r = platform.request('wbs_dat_o')
self.wb_io.dat_w = platform.request('wbs_dat_i')
self.wb_io.cti = Signal()
self.wb_io.bte = Signal()
self.wb_io.err = Signal()
self.wb_mgmt.connect_to_pads(self.wb_io, mode='slave')

#somehow get this built and then connected to 2 wb
#self.wb_shared = wishbone.InterconnectShared(masters,slaves)
self.mailbox = csr.CSRStorage(size=16, name='mailbox')
self.add_csr('mailbox')

# --- gpio
self.in_in = Signal(19)
self.comb += self.in_in.eq(platform.request('in_in'))
self.in_out = Signal(19)
self.comb += self.in_out.eq(platform.request('in_out'))
self.in_oeb = Signal(19)
self.comb += self.in_oeb.eq(platform.request('in_oeb'))
# skip analog_in; too curvy

# allocate
uart_0_io = {
'rx': self.in_in[0],
'tx': self.in_out[0]
}
uart_1_io = {
'rx': self.in_in[1],
'tx': self.in_out[1]
}
i2c_io = {
'scl': self.in_out[2],
'sda': self.in_out[3]
}
dshot_io = self.in_out[3:6]
# toss
ram_io = {
'ce': Signal(1),
'oe': Signal(), # self.in_out[7],
'we': Signal(), # self.in_out[8],
'adr': Signal(19), # self.in_out[18:0],
'dat': Signal(8) # self.in_out[18:11]
}

# --- misc
self.user_irq = Signal(3)
self.comb += self.user_irq.eq(platform.request('user_irq'))

# --- la
self.la_data_in = Signal(128)
self.comb += self.la_data_in.eq(platform.request('la_data_in'))
self.la_data_out = Signal(128)
self.comb += self.la_data_out.eq(platform.request('la_data_out'))
self.la_oenb = Signal(128)
self.comb += self.la_oenb.eq(platform.request('la_oenb'))

# ON-BOARD MEM ------------------------------------------------------------------------------
# None, unless a small 'ROM'-like device
#self.add_rom('rom', origin=self.mem_map['rom'], size=rom_size, contents=romdata)

# MANAGER -----------------------------------------------------------------------------------
# service processor stuff controlled by the man

# External SRAM (512K) -----------------------------------------------------------------------
# GPIO-connected SRAM/FPGA

# *** doh, won't work - only half the i/o are outputs!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! ***
# will have to resurrect custom serial i/o with fpga on other end

from issiram import ISSIRam
platform.add_source('./momv modules/issiram.v')

sram_bus = wishbone.Interface()
sram = ISSIRam(self, ClockSignal(), ResetSignal(), sram_bus, ram_io)
self.submodules.sram = sram
# ERROR: Output port top.issiram.mem_adr (issiram) is connected to constants: { \basesoc_in_out [17:0] 1'x }
# Command exited with non-zero status 1
# Elapsed time: 0:12.27[h:]min:sec. CPU time: user 11.77 sys 0.48 (99%). Peak memory: 1468464KB.
# make: *** [Makefile:354: results/sky130hd/a2p_litex/output/20211125085224/base/1_1_yosys.v] Error 1
self.bus.add_slave('sram', sram_bus, SoCRegion(origin=self.mem_map['sram'], size=sram.size))
#self.logger.info('SRAM {} {} {}.'.format(
# colorer('sram'),
# colorer('added', color='green'),
# self.bus.regions['sram']))

# Leds n LaserBeams -----------------------------------------------------------------------
#self.submodules.leds = LedChaser(
# pads = platform.request_all('user_led'),
# sys_clk_freq = sys_clk_freq
#)
#self.add_csr('leds')

# Buttons n KillSwitches ------------------------------------------------------------------
#self.submodules.buttons = GPIOIn(
# pads = platform.request_all('user_btn')
#)
#self.add_csr('buttons')

# GPIO I2C
#wtf must be an elegant pythonic way to do this junk
pins = Record([('scl', 1), ('sda', 1)])
pins.scl = i2c_io['scl']
pins.sda = i2c_io['sda']
#wtf needs to be 'i2c' for bios for now
self.submodules.i2c = I2CMaster(pins)
self.add_csr('i2c')

# GPIO UARTs = 2 pins per -----------------------------------------------------------------
pins = Record([('rx', 1), ('tx', 1)])
pins.rx = uart_0_io['rx']
pins.tx = uart_0_io['tx']
self.submodules.uart_0_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
self.add_csr('uart_0_phy')
self.submodules.uart_0 = UART(phy=self.uart_0_phy)
self.add_csr('uart_0')

pins = Record([('rx', 1), ('tx', 1)])
pins.rx = uart_1_io['tx']
pins.tx = uart_1_io['tx']
self.submodules.uart_1_phy = RS232PHY(pins, sys_clk_freq, with_dynamic_baudrate=True)
self.add_csr('uart_1_phy')
self.submodules.uart_1 = UART(phy=self.uart_1_phy)
self.add_csr('uart_1')

# DShot M0:M3 (no telemetry) = 4 pins -----------------------------------------------------
#self.submodules.dshot = DShot(dshot_io)
#self.add_csr('dshot')

# Build -------------------------------------------------------------------------------------------

def main():

parser = argparse.ArgumentParser(description='A2P Caravel Test Site')

builder_args(parser)
soc_sdram_args(parser)
args = parser.parse_args()

soc = BaseSoC(**soc_sdram_argdict(args))
builder = Builder(soc, **builder_argdict(args))

soc.build_name = 'wtf' #wtf dont work!
builder.build_name = 'wtf' #wtf dont work!
builder.compile_software = False
builder.csr_csv = 'csr.csv'
builder.build(run=False)

if __name__ == "__main__":
main()

79
build/openroad/litex/build/caravel_user/gateware/caravel_user.tcl

@ -0,0 +1,79 @@ @@ -0,0 +1,79 @@

# Create Project

create_project -force -name caravel_user -part xc7a35t-CPG236-1
set_msg_config -id {Common 17-55} -new_severity {Warning}

# Add Sources

read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/momv modules/issiram.v}
read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/a2p/verilog/A2P_WB.v}
read_verilog {/home/wtf/projects/a2p-opf/build/openroad/litex/build/caravel_user/gateware/caravel_user.v}

# Add EDIFs


# Add IPs


# Add constraints

read_xdc caravel_user.xdc
set_property PROCESSING_ORDER EARLY [get_files caravel_user.xdc]

# Add pre-synthesis commands


# Synthesis

synth_design -directive default -top caravel_user -part xc7a35t-CPG236-1

# Synthesis report

report_timing_summary -file caravel_user_timing_synth.rpt
report_utilization -hierarchical -file caravel_user_utilization_hierarchical_synth.rpt
report_utilization -file caravel_user_utilization_synth.rpt

# Optimize design

opt_design -directive default

# Add pre-placement commands


# Placement

place_design -directive default

# Placement report

report_utilization -hierarchical -file caravel_user_utilization_hierarchical_place.rpt
report_utilization -file caravel_user_utilization_place.rpt
report_io -file caravel_user_io.rpt
report_control_sets -verbose -file caravel_user_control_sets.rpt
report_clock_utilization -file caravel_user_clock_utilization.rpt

# Add pre-routing commands


# Routing

route_design -directive default
phys_opt_design -directive default
write_checkpoint -force caravel_user_route.dcp

# Routing report

report_timing_summary -no_header -no_detailed_paths
report_route_status -file caravel_user_route_status.rpt
report_drc -file caravel_user_drc.rpt
report_timing_summary -datasheet -max_paths 10 -file caravel_user_timing.rpt
report_power -file caravel_user_power.rpt

# Bitstream generation

write_bitstream -force caravel_user.bit

# End

quit

2357
build/openroad/litex/build/caravel_user/gateware/caravel_user.v

File diff suppressed because it is too large Load Diff

1623
build/openroad/litex/build/caravel_user/gateware/caravel_user.xdc

File diff suppressed because it is too large Load Diff

42
build/openroad/litex/build/caravel_user/gateware/mem.init

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41
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50
20
43
61
72
61
76
65
6c
20
53
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65
20
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65
73
74
20
32
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2d
31
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2d
32
35
20
31
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3a
35
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3a
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32
00

591
build/openroad/litex/build/caravel_user/software/include/generated/csr.h

@ -0,0 +1,591 @@ @@ -0,0 +1,591 @@
//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#include <generated/soc.h>
#ifndef __GENERATED_CSR_H
#define __GENERATED_CSR_H
#include <stdint.h>
#include <system.h>
#ifndef CSR_ACCESSORS_DEFINED
#include <hw/common.h>
#endif /* ! CSR_ACCESSORS_DEFINED */
#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#endif

/* i2c */
#define CSR_I2C_BASE (CSR_BASE + 0x800L)
#define CSR_I2C_W_ADDR (CSR_BASE + 0x800L)
#define CSR_I2C_W_SIZE 1
static inline uint32_t i2c_w_read(void) {
return csr_read_simple(CSR_BASE + 0x800L);
}
static inline void i2c_w_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x800L);
}
#define CSR_I2C_W_SCL_OFFSET 0
#define CSR_I2C_W_SCL_SIZE 1
static inline uint32_t i2c_w_scl_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_w_scl_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_scl_extract(word);
}
static inline uint32_t i2c_w_scl_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void i2c_w_scl_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_scl_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_OE_OFFSET 1
#define CSR_I2C_W_OE_SIZE 1
static inline uint32_t i2c_w_oe_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t i2c_w_oe_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_oe_extract(word);
}
static inline uint32_t i2c_w_oe_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void i2c_w_oe_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_oe_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_W_SDA_OFFSET 2
#define CSR_I2C_W_SDA_SIZE 1
static inline uint32_t i2c_w_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 2) & mask );
}
static inline uint32_t i2c_w_sda_read(void) {
uint32_t word = i2c_w_read();
return i2c_w_sda_extract(word);
}
static inline uint32_t i2c_w_sda_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 2))) | (mask & plain_value)<< 2 ;
}
static inline void i2c_w_sda_write(uint32_t plain_value) {
uint32_t oldword = i2c_w_read();
uint32_t newword = i2c_w_sda_replace(oldword, plain_value);
i2c_w_write(newword);
}
#define CSR_I2C_R_ADDR (CSR_BASE + 0x804L)
#define CSR_I2C_R_SIZE 1
static inline uint32_t i2c_r_read(void) {
return csr_read_simple(CSR_BASE + 0x804L);
}
#define CSR_I2C_R_SDA_OFFSET 0
#define CSR_I2C_R_SDA_SIZE 1
static inline uint32_t i2c_r_sda_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t i2c_r_sda_read(void) {
uint32_t word = i2c_r_read();
return i2c_r_sda_extract(word);
}

/* uart_0_phy */
#define CSR_UART_0_PHY_BASE (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x1000L)
#define CSR_UART_0_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_0_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x1000L);
}
static inline void uart_0_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1000L);
}

/* uart_0 */
#define CSR_UART_0_BASE (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_ADDR (CSR_BASE + 0x1800L)
#define CSR_UART_0_RXTX_SIZE 1
static inline uint32_t uart_0_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x1800L);
}
static inline void uart_0_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1800L);
}
#define CSR_UART_0_TXFULL_ADDR (CSR_BASE + 0x1804L)
#define CSR_UART_0_TXFULL_SIZE 1
static inline uint32_t uart_0_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x1804L);
}
#define CSR_UART_0_RXEMPTY_ADDR (CSR_BASE + 0x1808L)
#define CSR_UART_0_RXEMPTY_SIZE 1
static inline uint32_t uart_0_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1808L);
}
#define CSR_UART_0_EV_STATUS_ADDR (CSR_BASE + 0x180cL)
#define CSR_UART_0_EV_STATUS_SIZE 1
static inline uint32_t uart_0_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x180cL);
}
#define CSR_UART_0_EV_STATUS_TX_OFFSET 0
#define CSR_UART_0_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_0_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_status_tx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_tx_extract(word);
}
#define CSR_UART_0_EV_STATUS_RX_OFFSET 1
#define CSR_UART_0_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_0_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_status_rx_read(void) {
uint32_t word = uart_0_ev_status_read();
return uart_0_ev_status_rx_extract(word);
}
#define CSR_UART_0_EV_PENDING_ADDR (CSR_BASE + 0x1810L)
#define CSR_UART_0_EV_PENDING_SIZE 1
static inline uint32_t uart_0_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x1810L);
}
static inline void uart_0_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1810L);
}
#define CSR_UART_0_EV_PENDING_TX_OFFSET 0
#define CSR_UART_0_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_0_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_pending_tx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_tx_extract(word);
}
static inline uint32_t uart_0_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_tx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_PENDING_RX_OFFSET 1
#define CSR_UART_0_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_0_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_pending_rx_read(void) {
uint32_t word = uart_0_ev_pending_read();
return uart_0_ev_pending_rx_extract(word);
}
static inline uint32_t uart_0_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_pending_read();
uint32_t newword = uart_0_ev_pending_rx_replace(oldword, plain_value);
uart_0_ev_pending_write(newword);
}
#define CSR_UART_0_EV_ENABLE_ADDR (CSR_BASE + 0x1814L)
#define CSR_UART_0_EV_ENABLE_SIZE 1
static inline uint32_t uart_0_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x1814L);
}
static inline void uart_0_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x1814L);
}
#define CSR_UART_0_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_0_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_0_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_0_ev_enable_tx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_tx_extract(word);
}
static inline uint32_t uart_0_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_0_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_tx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_0_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_0_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_0_ev_enable_rx_read(void) {
uint32_t word = uart_0_ev_enable_read();
return uart_0_ev_enable_rx_extract(word);
}
static inline uint32_t uart_0_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_0_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_0_ev_enable_read();
uint32_t newword = uart_0_ev_enable_rx_replace(oldword, plain_value);
uart_0_ev_enable_write(newword);
}
#define CSR_UART_0_TXEMPTY_ADDR (CSR_BASE + 0x1818L)
#define CSR_UART_0_TXEMPTY_SIZE 1
static inline uint32_t uart_0_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x1818L);
}
#define CSR_UART_0_RXFULL_ADDR (CSR_BASE + 0x181cL)
#define CSR_UART_0_RXFULL_SIZE 1
static inline uint32_t uart_0_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x181cL);
}

/* uart_1_phy */
#define CSR_UART_1_PHY_BASE (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_ADDR (CSR_BASE + 0x2000L)
#define CSR_UART_1_PHY_TUNING_WORD_SIZE 1
static inline uint32_t uart_1_phy_tuning_word_read(void) {
return csr_read_simple(CSR_BASE + 0x2000L);
}
static inline void uart_1_phy_tuning_word_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2000L);
}

/* uart_1 */
#define CSR_UART_1_BASE (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_ADDR (CSR_BASE + 0x2800L)
#define CSR_UART_1_RXTX_SIZE 1
static inline uint32_t uart_1_rxtx_read(void) {
return csr_read_simple(CSR_BASE + 0x2800L);
}
static inline void uart_1_rxtx_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2800L);
}
#define CSR_UART_1_TXFULL_ADDR (CSR_BASE + 0x2804L)
#define CSR_UART_1_TXFULL_SIZE 1
static inline uint32_t uart_1_txfull_read(void) {
return csr_read_simple(CSR_BASE + 0x2804L);
}
#define CSR_UART_1_RXEMPTY_ADDR (CSR_BASE + 0x2808L)
#define CSR_UART_1_RXEMPTY_SIZE 1
static inline uint32_t uart_1_rxempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2808L);
}
#define CSR_UART_1_EV_STATUS_ADDR (CSR_BASE + 0x280cL)
#define CSR_UART_1_EV_STATUS_SIZE 1
static inline uint32_t uart_1_ev_status_read(void) {
return csr_read_simple(CSR_BASE + 0x280cL);
}
#define CSR_UART_1_EV_STATUS_TX_OFFSET 0
#define CSR_UART_1_EV_STATUS_TX_SIZE 1
static inline uint32_t uart_1_ev_status_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_status_tx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_tx_extract(word);
}
#define CSR_UART_1_EV_STATUS_RX_OFFSET 1
#define CSR_UART_1_EV_STATUS_RX_SIZE 1
static inline uint32_t uart_1_ev_status_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_status_rx_read(void) {
uint32_t word = uart_1_ev_status_read();
return uart_1_ev_status_rx_extract(word);
}
#define CSR_UART_1_EV_PENDING_ADDR (CSR_BASE + 0x2810L)
#define CSR_UART_1_EV_PENDING_SIZE 1
static inline uint32_t uart_1_ev_pending_read(void) {
return csr_read_simple(CSR_BASE + 0x2810L);
}
static inline void uart_1_ev_pending_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2810L);
}
#define CSR_UART_1_EV_PENDING_TX_OFFSET 0
#define CSR_UART_1_EV_PENDING_TX_SIZE 1
static inline uint32_t uart_1_ev_pending_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_pending_tx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_tx_extract(word);
}
static inline uint32_t uart_1_ev_pending_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_pending_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_tx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_PENDING_RX_OFFSET 1
#define CSR_UART_1_EV_PENDING_RX_SIZE 1
static inline uint32_t uart_1_ev_pending_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_pending_rx_read(void) {
uint32_t word = uart_1_ev_pending_read();
return uart_1_ev_pending_rx_extract(word);
}
static inline uint32_t uart_1_ev_pending_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_pending_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_pending_read();
uint32_t newword = uart_1_ev_pending_rx_replace(oldword, plain_value);
uart_1_ev_pending_write(newword);
}
#define CSR_UART_1_EV_ENABLE_ADDR (CSR_BASE + 0x2814L)
#define CSR_UART_1_EV_ENABLE_SIZE 1
static inline uint32_t uart_1_ev_enable_read(void) {
return csr_read_simple(CSR_BASE + 0x2814L);
}
static inline void uart_1_ev_enable_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x2814L);
}
#define CSR_UART_1_EV_ENABLE_TX_OFFSET 0
#define CSR_UART_1_EV_ENABLE_TX_SIZE 1
static inline uint32_t uart_1_ev_enable_tx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t uart_1_ev_enable_tx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_tx_extract(word);
}
static inline uint32_t uart_1_ev_enable_tx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void uart_1_ev_enable_tx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_tx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_EV_ENABLE_RX_OFFSET 1
#define CSR_UART_1_EV_ENABLE_RX_SIZE 1
static inline uint32_t uart_1_ev_enable_rx_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t uart_1_ev_enable_rx_read(void) {
uint32_t word = uart_1_ev_enable_read();
return uart_1_ev_enable_rx_extract(word);
}
static inline uint32_t uart_1_ev_enable_rx_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void uart_1_ev_enable_rx_write(uint32_t plain_value) {
uint32_t oldword = uart_1_ev_enable_read();
uint32_t newword = uart_1_ev_enable_rx_replace(oldword, plain_value);
uart_1_ev_enable_write(newword);
}
#define CSR_UART_1_TXEMPTY_ADDR (CSR_BASE + 0x2818L)
#define CSR_UART_1_TXEMPTY_SIZE 1
static inline uint32_t uart_1_txempty_read(void) {
return csr_read_simple(CSR_BASE + 0x2818L);
}
#define CSR_UART_1_RXFULL_ADDR (CSR_BASE + 0x281cL)
#define CSR_UART_1_RXFULL_SIZE 1
static inline uint32_t uart_1_rxfull_read(void) {
return csr_read_simple(CSR_BASE + 0x281cL);
}

/* ctrl */
#define CSR_CTRL_BASE (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_ADDR (CSR_BASE + 0x3000L)
#define CSR_CTRL_RESET_SIZE 1
static inline uint32_t ctrl_reset_read(void) {
return csr_read_simple(CSR_BASE + 0x3000L);
}
static inline void ctrl_reset_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3000L);
}
#define CSR_CTRL_RESET_SOC_RST_OFFSET 0
#define CSR_CTRL_RESET_SOC_RST_SIZE 1
static inline uint32_t ctrl_reset_soc_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 0) & mask );
}
static inline uint32_t ctrl_reset_soc_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_soc_rst_extract(word);
}
static inline uint32_t ctrl_reset_soc_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 0))) | (mask & plain_value)<< 0 ;
}
static inline void ctrl_reset_soc_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_soc_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_RESET_CPU_RST_OFFSET 1
#define CSR_CTRL_RESET_CPU_RST_SIZE 1
static inline uint32_t ctrl_reset_cpu_rst_extract(uint32_t oldword) {
uint32_t mask = ((1 << 1)-1);
return ( (oldword >> 1) & mask );
}
static inline uint32_t ctrl_reset_cpu_rst_read(void) {
uint32_t word = ctrl_reset_read();
return ctrl_reset_cpu_rst_extract(word);
}
static inline uint32_t ctrl_reset_cpu_rst_replace(uint32_t oldword, uint32_t plain_value) {
uint32_t mask = ((1 << 1)-1);
return (oldword & (~(mask << 1))) | (mask & plain_value)<< 1 ;
}
static inline void ctrl_reset_cpu_rst_write(uint32_t plain_value) {
uint32_t oldword = ctrl_reset_read();
uint32_t newword = ctrl_reset_cpu_rst_replace(oldword, plain_value);
ctrl_reset_write(newword);
}
#define CSR_CTRL_SCRATCH_ADDR (CSR_BASE + 0x3004L)
#define CSR_CTRL_SCRATCH_SIZE 1
static inline uint32_t ctrl_scratch_read(void) {
return csr_read_simple(CSR_BASE + 0x3004L);
}
static inline void ctrl_scratch_write(uint32_t v) {
csr_write_simple(v, CSR_BASE + 0x3004L);
}
#define CSR_CTRL_BUS_ERRORS_ADDR (CSR_BASE + 0x3008L)
#define CSR_CTRL_BUS_ERRORS_SIZE 1
static inline uint32_t ctrl_bus_errors_read(void) {
return csr_read_simple(CSR_BASE + 0x3008L);
}

/* identifier_mem */
#define CSR_IDENTIFIER_MEM_BASE (CSR_BASE + 0x3800L)

/* timer0 */
#define CSR_TIMER0_BASE (CSR_BASE + 0x4000L)