# PowerP

* test environment for ASIC implementation

### FPGA Environment

* Litex SOC, Wishbone bus/peripherals

* Minimum requirement: low-cost dev board with GTP I/O (6G serial):

      https://github.com/ChinaQMTECH/XC7A100T-200T_Wukong_Board

* 2+ cores

* 2 OMI host stacks (Wishbone slaves)

* 2 OMI memory stacks (partitioned DDR)

* Wrapback serial connections for single-FPGA testing (2 pairs of OMI links)