//--------------------------------------------------------------------------------
// Auto-generated by Migen (9a0be7a) & LiteX (85d6cb4b) on 2021-11-25 13:53:32
//--------------------------------------------------------------------------------
#ifndef __GENERATED_MEM_H
#define __GENERATED_MEM_H

#ifndef SRAM_BASE
#define SRAM_BASE 0x00000000L
#define SRAM_SIZE 0x00080000
#endif

#ifndef CSR_BASE
#define CSR_BASE 0xfff00000L
#define CSR_SIZE 0x00010000
#endif

#ifndef MEM_REGIONS
#define MEM_REGIONS "SRAM      0x00000000 0x80000 \nCSR       0xfff00000 0x10000 "
#endif
#endif