// ----------------------------------------------------------------------------- // Auto-Generated by: __ _ __ _ __ // / / (_) /____ | |/_/ // / /__/ / __/ -_)> < // /____/_/\__/\__/_/|_| // Build your hardware, easily! // https://github.com/enjoy-digital/litex // // Filename : top.v // Device : caravel_user // LiteX sha1 : 85d6cb4b // Date : 2021-11-25 10:16:15 //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Module //------------------------------------------------------------------------------ module top ( input wire wb_rst_i, input wire user_clock2, input wire wbs_cyc_i, input wire wbs_stb_i, input wire wbs_we_i, input wire [3:0] wbs_sel_i, input wire [31:0] wbs_adr_i, input wire wbs_ack_o, input wire [31:0] wbs_dat_o, input wire [31:0] wbs_dat_i, input wire [18:0] in_in, input wire [18:0] in_out, input wire in_oeb, input wire [2:0] user_irq, input wire [127:0] la_data_in, input wire [127:0] la_data_out, input wire [127:0] la_oenb, input wire wb_clk_i ); //------------------------------------------------------------------------------ // Signals //------------------------------------------------------------------------------ reg basesoc_basesoc_soc_rst = 1'd0; wire basesoc_basesoc_cpu_rst; reg [1:0] basesoc_basesoc_reset_storage = 2'd0; reg basesoc_basesoc_reset_re = 1'd0; reg [31:0] basesoc_basesoc_scratch_storage = 32'd305419896; reg basesoc_basesoc_scratch_re = 1'd0; wire [31:0] basesoc_basesoc_bus_errors_status; wire basesoc_basesoc_bus_errors_we; reg basesoc_basesoc_bus_errors_re = 1'd0; wire basesoc_basesoc_bus_error; reg [31:0] basesoc_basesoc_bus_errors = 32'd0; wire basesoc_basesoc_reset; wire [31:0] basesoc_basesoc_interrupt; reg basesoc_basesoc_interruptS = 1'd0; wire [29:0] basesoc_basesoc_ibus_adr; wire [31:0] basesoc_basesoc_ibus_dat_w; wire [31:0] basesoc_basesoc_ibus_dat_r; wire [3:0] basesoc_basesoc_ibus_sel; wire basesoc_basesoc_ibus_cyc; wire basesoc_basesoc_ibus_stb; wire basesoc_basesoc_ibus_ack; wire basesoc_basesoc_ibus_we; wire [2:0] basesoc_basesoc_ibus_cti; wire [1:0] basesoc_basesoc_ibus_bte; wire basesoc_basesoc_ibus_err; wire [29:0] basesoc_basesoc_dbus_adr; wire [31:0] basesoc_basesoc_dbus_dat_w; wire [31:0] basesoc_basesoc_dbus_dat_r; wire [3:0] basesoc_basesoc_dbus_sel; wire basesoc_basesoc_dbus_cyc; wire basesoc_basesoc_dbus_stb; wire basesoc_basesoc_dbus_ack; wire basesoc_basesoc_dbus_we; wire [2:0] basesoc_basesoc_dbus_cti; wire [1:0] basesoc_basesoc_dbus_bte; wire basesoc_basesoc_dbus_err; reg [31:0] basesoc_basesoc_a2p = 32'd0; reg [31:0] basesoc_basesoc_load_storage = 32'd0; reg basesoc_basesoc_load_re = 1'd0; reg [31:0] basesoc_basesoc_reload_storage = 32'd0; reg basesoc_basesoc_reload_re = 1'd0; reg basesoc_basesoc_en_storage = 1'd0; reg basesoc_basesoc_en_re = 1'd0; reg basesoc_basesoc_update_value_storage = 1'd0; reg basesoc_basesoc_update_value_re = 1'd0; reg [31:0] basesoc_basesoc_value_status = 32'd0; wire basesoc_basesoc_value_we; reg basesoc_basesoc_value_re = 1'd0; wire basesoc_basesoc_irq; wire basesoc_basesoc_zero_status; reg basesoc_basesoc_zero_pending = 1'd0; wire basesoc_basesoc_zero_trigger; reg basesoc_basesoc_zero_clear = 1'd0; reg basesoc_basesoc_zero_trigger_d = 1'd0; wire basesoc_basesoc_zero0; wire basesoc_basesoc_status_status; wire basesoc_basesoc_status_we; reg basesoc_basesoc_status_re = 1'd0; wire basesoc_basesoc_zero1; wire basesoc_basesoc_pending_status; wire basesoc_basesoc_pending_we; reg basesoc_basesoc_pending_re = 1'd0; reg basesoc_basesoc_pending_r = 1'd0; wire basesoc_basesoc_zero2; reg basesoc_basesoc_enable_storage = 1'd0; reg basesoc_basesoc_enable_re = 1'd0; reg [31:0] basesoc_basesoc_value = 32'd0; wire basesoc_user_clock2; wire [18:0] basesoc_in_in; wire [18:0] basesoc_in_out; wire [18:0] basesoc_in_oeb; wire basesoc0; wire basesoc1; wire basesoc2; wire [18:0] basesoc3; wire [7:0] basesoc4; wire [2:0] basesoc_user_irq; wire [127:0] basesoc_la_data_in; wire [127:0] basesoc_la_data_out; wire [127:0] basesoc_la_oenb; wire [29:0] basesoc_sram_bus_adr; wire [31:0] basesoc_sram_bus_dat_w; wire [31:0] basesoc_sram_bus_dat_r; wire [3:0] basesoc_sram_bus_sel; wire basesoc_sram_bus_cyc; wire basesoc_sram_bus_stb; wire basesoc_sram_bus_ack; wire basesoc_sram_bus_we; wire [2:0] basesoc_sram_bus_cti; wire [1:0] basesoc_sram_bus_bte; reg basesoc_sram_bus_err = 1'd0; wire basesoc_scl; wire basesoc_oe; wire basesoc_sda0; reg [2:0] basesoc__w_storage = 3'd0; reg basesoc__w_re = 1'd0; wire basesoc_sda1; wire basesoc__r_status; wire basesoc__r_we; reg basesoc__r_re = 1'd0; reg [31:0] basesoc_uart_0_phy_storage = 32'd9895604; reg basesoc_uart_0_phy_re = 1'd0; wire basesoc_uart_0_phy_tx_sink_valid; reg basesoc_uart_0_phy_tx_sink_ready = 1'd0; wire basesoc_uart_0_phy_tx_sink_first; wire basesoc_uart_0_phy_tx_sink_last; wire [7:0] basesoc_uart_0_phy_tx_sink_payload_data; reg [7:0] basesoc_uart_0_phy_tx_data = 8'd0; reg [3:0] basesoc_uart_0_phy_tx_count = 4'd0; reg basesoc_uart_0_phy_tx_enable = 1'd0; reg basesoc_uart_0_phy_tx_tick = 1'd0; reg [31:0] basesoc_uart_0_phy_tx_phase = 32'd0; reg basesoc_uart_0_phy_rx_source_valid = 1'd0; wire basesoc_uart_0_phy_rx_source_ready; reg basesoc_uart_0_phy_rx_source_first = 1'd0; reg basesoc_uart_0_phy_rx_source_last = 1'd0; reg [7:0] basesoc_uart_0_phy_rx_source_payload_data = 8'd0; reg [7:0] basesoc_uart_0_phy_rx_data = 8'd0; reg [3:0] basesoc_uart_0_phy_rx_count = 4'd0; reg basesoc_uart_0_phy_rx_enable = 1'd0; reg basesoc_uart_0_phy_rx_tick = 1'd0; reg [31:0] basesoc_uart_0_phy_rx_phase = 32'd0; wire basesoc_uart_0_phy_rx_rx; reg basesoc_uart_0_phy_rx_rx_d = 1'd0; reg basesoc_uart_0_rxtx_re = 1'd0; wire [7:0] basesoc_uart_0_rxtx_r; reg basesoc_uart_0_rxtx_we = 1'd0; wire [7:0] basesoc_uart_0_rxtx_w; wire basesoc_uart_0_txfull_status; wire basesoc_uart_0_txfull_we; reg basesoc_uart_0_txfull_re = 1'd0; wire basesoc_uart_0_rxempty_status; wire basesoc_uart_0_rxempty_we; reg basesoc_uart_0_rxempty_re = 1'd0; wire basesoc_uart_0_irq; wire basesoc_uart_0_tx_status; reg basesoc_uart_0_tx_pending = 1'd0; wire basesoc_uart_0_tx_trigger; reg basesoc_uart_0_tx_clear = 1'd0; reg basesoc_uart_0_tx_trigger_d = 1'd0; wire basesoc_uart_0_rx_status; reg basesoc_uart_0_rx_pending = 1'd0; wire basesoc_uart_0_rx_trigger; reg basesoc_uart_0_rx_clear = 1'd0; reg basesoc_uart_0_rx_trigger_d = 1'd0; wire basesoc_uart_0_tx0; wire basesoc_uart_0_rx0; reg [1:0] basesoc_uart_0_status_status = 2'd0; wire basesoc_uart_0_status_we; reg basesoc_uart_0_status_re = 1'd0; wire basesoc_uart_0_tx1; wire basesoc_uart_0_rx1; reg [1:0] basesoc_uart_0_pending_status = 2'd0; wire basesoc_uart_0_pending_we; reg basesoc_uart_0_pending_re = 1'd0; reg [1:0] basesoc_uart_0_pending_r = 2'd0; wire basesoc_uart_0_tx2; wire basesoc_uart_0_rx2; reg [1:0] basesoc_uart_0_enable_storage = 2'd0; reg basesoc_uart_0_enable_re = 1'd0; wire basesoc_uart_0_txempty_status; wire basesoc_uart_0_txempty_we; reg basesoc_uart_0_txempty_re = 1'd0; wire basesoc_uart_0_rxfull_status; wire basesoc_uart_0_rxfull_we; reg basesoc_uart_0_rxfull_re = 1'd0; wire basesoc_uart_0_uart_sink_valid; wire basesoc_uart_0_uart_sink_ready; wire basesoc_uart_0_uart_sink_first; wire basesoc_uart_0_uart_sink_last; wire [7:0] basesoc_uart_0_uart_sink_payload_data; wire basesoc_uart_0_uart_source_valid; wire basesoc_uart_0_uart_source_ready; wire basesoc_uart_0_uart_source_first; wire basesoc_uart_0_uart_source_last; wire [7:0] basesoc_uart_0_uart_source_payload_data; wire basesoc_uart_0_tx_fifo_sink_valid; wire basesoc_uart_0_tx_fifo_sink_ready; reg basesoc_uart_0_tx_fifo_sink_first = 1'd0; reg basesoc_uart_0_tx_fifo_sink_last = 1'd0; wire [7:0] basesoc_uart_0_tx_fifo_sink_payload_data; wire basesoc_uart_0_tx_fifo_source_valid; wire basesoc_uart_0_tx_fifo_source_ready; wire basesoc_uart_0_tx_fifo_source_first; wire basesoc_uart_0_tx_fifo_source_last; wire [7:0] basesoc_uart_0_tx_fifo_source_payload_data; wire basesoc_uart_0_tx_fifo_re; reg basesoc_uart_0_tx_fifo_readable = 1'd0; wire basesoc_uart_0_tx_fifo_syncfifo_we; wire basesoc_uart_0_tx_fifo_syncfifo_writable; wire basesoc_uart_0_tx_fifo_syncfifo_re; wire basesoc_uart_0_tx_fifo_syncfifo_readable; wire [9:0] basesoc_uart_0_tx_fifo_syncfifo_din; wire [9:0] basesoc_uart_0_tx_fifo_syncfifo_dout; reg [4:0] basesoc_uart_0_tx_fifo_level0 = 5'd0; reg basesoc_uart_0_tx_fifo_replace = 1'd0; reg [3:0] basesoc_uart_0_tx_fifo_produce = 4'd0; reg [3:0] basesoc_uart_0_tx_fifo_consume = 4'd0; reg [3:0] basesoc_uart_0_tx_fifo_wrport_adr = 4'd0; wire [9:0] basesoc_uart_0_tx_fifo_wrport_dat_r; wire basesoc_uart_0_tx_fifo_wrport_we; wire [9:0] basesoc_uart_0_tx_fifo_wrport_dat_w; wire basesoc_uart_0_tx_fifo_do_read; wire [3:0] basesoc_uart_0_tx_fifo_rdport_adr; wire [9:0] basesoc_uart_0_tx_fifo_rdport_dat_r; wire basesoc_uart_0_tx_fifo_rdport_re; wire [4:0] basesoc_uart_0_tx_fifo_level1; wire [7:0] basesoc_uart_0_tx_fifo_fifo_in_payload_data; wire basesoc_uart_0_tx_fifo_fifo_in_first; wire basesoc_uart_0_tx_fifo_fifo_in_last; wire [7:0] basesoc_uart_0_tx_fifo_fifo_out_payload_data; wire basesoc_uart_0_tx_fifo_fifo_out_first; wire basesoc_uart_0_tx_fifo_fifo_out_last; wire basesoc_uart_0_rx_fifo_sink_valid; wire basesoc_uart_0_rx_fifo_sink_ready; wire basesoc_uart_0_rx_fifo_sink_first; wire basesoc_uart_0_rx_fifo_sink_last; wire [7:0] basesoc_uart_0_rx_fifo_sink_payload_data; wire basesoc_uart_0_rx_fifo_source_valid; wire basesoc_uart_0_rx_fifo_source_ready; wire basesoc_uart_0_rx_fifo_source_first; wire basesoc_uart_0_rx_fifo_source_last; wire [7:0] basesoc_uart_0_rx_fifo_source_payload_data; wire basesoc_uart_0_rx_fifo_re; reg basesoc_uart_0_rx_fifo_readable = 1'd0; wire basesoc_uart_0_rx_fifo_syncfifo_we; wire basesoc_uart_0_rx_fifo_syncfifo_writable; wire basesoc_uart_0_rx_fifo_syncfifo_re; wire basesoc_uart_0_rx_fifo_syncfifo_readable; wire [9:0] basesoc_uart_0_rx_fifo_syncfifo_din; wire [9:0] basesoc_uart_0_rx_fifo_syncfifo_dout; reg [4:0] basesoc_uart_0_rx_fifo_level0 = 5'd0; reg basesoc_uart_0_rx_fifo_replace = 1'd0; reg [3:0] basesoc_uart_0_rx_fifo_produce = 4'd0; reg [3:0] basesoc_uart_0_rx_fifo_consume = 4'd0; reg [3:0] basesoc_uart_0_rx_fifo_wrport_adr = 4'd0; wire [9:0] basesoc_uart_0_rx_fifo_wrport_dat_r; wire basesoc_uart_0_rx_fifo_wrport_we; wire [9:0] basesoc_uart_0_rx_fifo_wrport_dat_w; wire basesoc_uart_0_rx_fifo_do_read; wire [3:0] basesoc_uart_0_rx_fifo_rdport_adr; wire [9:0] basesoc_uart_0_rx_fifo_rdport_dat_r; wire basesoc_uart_0_rx_fifo_rdport_re; wire [4:0] basesoc_uart_0_rx_fifo_level1; wire [7:0] basesoc_uart_0_rx_fifo_fifo_in_payload_data; wire basesoc_uart_0_rx_fifo_fifo_in_first; wire basesoc_uart_0_rx_fifo_fifo_in_last; wire [7:0] basesoc_uart_0_rx_fifo_fifo_out_payload_data; wire basesoc_uart_0_rx_fifo_fifo_out_first; wire basesoc_uart_0_rx_fifo_fifo_out_last; reg [31:0] basesoc_uart_1_phy_storage = 32'd9895604; reg basesoc_uart_1_phy_re = 1'd0; wire basesoc_uart_1_phy_tx_sink_valid; reg basesoc_uart_1_phy_tx_sink_ready = 1'd0; wire basesoc_uart_1_phy_tx_sink_first; wire basesoc_uart_1_phy_tx_sink_last; wire [7:0] basesoc_uart_1_phy_tx_sink_payload_data; reg [7:0] basesoc_uart_1_phy_tx_data = 8'd0; reg [3:0] basesoc_uart_1_phy_tx_count = 4'd0; reg basesoc_uart_1_phy_tx_enable = 1'd0; reg basesoc_uart_1_phy_tx_tick = 1'd0; reg [31:0] basesoc_uart_1_phy_tx_phase = 32'd0; reg basesoc_uart_1_phy_rx_source_valid = 1'd0; wire basesoc_uart_1_phy_rx_source_ready; reg basesoc_uart_1_phy_rx_source_first = 1'd0; reg basesoc_uart_1_phy_rx_source_last = 1'd0; reg [7:0] basesoc_uart_1_phy_rx_source_payload_data = 8'd0; reg [7:0] basesoc_uart_1_phy_rx_data = 8'd0; reg [3:0] basesoc_uart_1_phy_rx_count = 4'd0; reg basesoc_uart_1_phy_rx_enable = 1'd0; reg basesoc_uart_1_phy_rx_tick = 1'd0; reg [31:0] basesoc_uart_1_phy_rx_phase = 32'd0; wire basesoc_uart_1_phy_rx_rx; reg basesoc_uart_1_phy_rx_rx_d = 1'd0; reg basesoc_uart_1_rxtx_re = 1'd0; wire [7:0] basesoc_uart_1_rxtx_r; reg basesoc_uart_1_rxtx_we = 1'd0; wire [7:0] basesoc_uart_1_rxtx_w; wire basesoc_uart_1_txfull_status; wire basesoc_uart_1_txfull_we; reg basesoc_uart_1_txfull_re = 1'd0; wire basesoc_uart_1_rxempty_status; wire basesoc_uart_1_rxempty_we; reg basesoc_uart_1_rxempty_re = 1'd0; wire basesoc_uart_1_irq; wire basesoc_uart_1_tx_status; reg basesoc_uart_1_tx_pending = 1'd0; wire basesoc_uart_1_tx_trigger; reg basesoc_uart_1_tx_clear = 1'd0; reg basesoc_uart_1_tx_trigger_d = 1'd0; wire basesoc_uart_1_rx_status; reg basesoc_uart_1_rx_pending = 1'd0; wire basesoc_uart_1_rx_trigger; reg basesoc_uart_1_rx_clear = 1'd0; reg basesoc_uart_1_rx_trigger_d = 1'd0; wire basesoc_uart_1_tx0; wire basesoc_uart_1_rx0; reg [1:0] basesoc_uart_1_status_status = 2'd0; wire basesoc_uart_1_status_we; reg basesoc_uart_1_status_re = 1'd0; wire basesoc_uart_1_tx1; wire basesoc_uart_1_rx1; reg [1:0] basesoc_uart_1_pending_status = 2'd0; wire basesoc_uart_1_pending_we; reg basesoc_uart_1_pending_re = 1'd0; reg [1:0] basesoc_uart_1_pending_r = 2'd0; wire basesoc_uart_1_tx2; wire basesoc_uart_1_rx2; reg [1:0] basesoc_uart_1_enable_storage = 2'd0; reg basesoc_uart_1_enable_re = 1'd0; wire basesoc_uart_1_txempty_status; wire basesoc_uart_1_txempty_we; reg basesoc_uart_1_txempty_re = 1'd0; wire basesoc_uart_1_rxfull_status; wire basesoc_uart_1_rxfull_we; reg basesoc_uart_1_rxfull_re = 1'd0; wire basesoc_uart_1_uart_sink_valid; wire basesoc_uart_1_uart_sink_ready; wire basesoc_uart_1_uart_sink_first; wire basesoc_uart_1_uart_sink_last; wire [7:0] basesoc_uart_1_uart_sink_payload_data; wire basesoc_uart_1_uart_source_valid; wire basesoc_uart_1_uart_source_ready; wire basesoc_uart_1_uart_source_first; wire basesoc_uart_1_uart_source_last; wire [7:0] basesoc_uart_1_uart_source_payload_data; wire basesoc_uart_1_tx_fifo_sink_valid; wire basesoc_uart_1_tx_fifo_sink_ready; reg basesoc_uart_1_tx_fifo_sink_first = 1'd0; reg basesoc_uart_1_tx_fifo_sink_last = 1'd0; wire [7:0] basesoc_uart_1_tx_fifo_sink_payload_data; wire basesoc_uart_1_tx_fifo_source_valid; wire basesoc_uart_1_tx_fifo_source_ready; wire basesoc_uart_1_tx_fifo_source_first; wire basesoc_uart_1_tx_fifo_source_last; wire [7:0] basesoc_uart_1_tx_fifo_source_payload_data; wire basesoc_uart_1_tx_fifo_re; reg basesoc_uart_1_tx_fifo_readable = 1'd0; wire basesoc_uart_1_tx_fifo_syncfifo_we; wire basesoc_uart_1_tx_fifo_syncfifo_writable; wire basesoc_uart_1_tx_fifo_syncfifo_re; wire basesoc_uart_1_tx_fifo_syncfifo_readable; wire [9:0] basesoc_uart_1_tx_fifo_syncfifo_din; wire [9:0] basesoc_uart_1_tx_fifo_syncfifo_dout; reg [4:0] basesoc_uart_1_tx_fifo_level0 = 5'd0; reg basesoc_uart_1_tx_fifo_replace = 1'd0; reg [3:0] basesoc_uart_1_tx_fifo_produce = 4'd0; reg [3:0] basesoc_uart_1_tx_fifo_consume = 4'd0; reg [3:0] basesoc_uart_1_tx_fifo_wrport_adr = 4'd0; wire [9:0] basesoc_uart_1_tx_fifo_wrport_dat_r; wire basesoc_uart_1_tx_fifo_wrport_we; wire [9:0] basesoc_uart_1_tx_fifo_wrport_dat_w; wire basesoc_uart_1_tx_fifo_do_read; wire [3:0] basesoc_uart_1_tx_fifo_rdport_adr; wire [9:0] basesoc_uart_1_tx_fifo_rdport_dat_r; wire basesoc_uart_1_tx_fifo_rdport_re; wire [4:0] basesoc_uart_1_tx_fifo_level1; wire [7:0] basesoc_uart_1_tx_fifo_fifo_in_payload_data; wire basesoc_uart_1_tx_fifo_fifo_in_first; wire basesoc_uart_1_tx_fifo_fifo_in_last; wire [7:0] basesoc_uart_1_tx_fifo_fifo_out_payload_data; wire basesoc_uart_1_tx_fifo_fifo_out_first; wire basesoc_uart_1_tx_fifo_fifo_out_last; wire basesoc_uart_1_rx_fifo_sink_valid; wire basesoc_uart_1_rx_fifo_sink_ready; wire basesoc_uart_1_rx_fifo_sink_first; wire basesoc_uart_1_rx_fifo_sink_last; wire [7:0] basesoc_uart_1_rx_fifo_sink_payload_data; wire basesoc_uart_1_rx_fifo_source_valid; wire basesoc_uart_1_rx_fifo_source_ready; wire basesoc_uart_1_rx_fifo_source_first; wire basesoc_uart_1_rx_fifo_source_last; wire [7:0] basesoc_uart_1_rx_fifo_source_payload_data; wire basesoc_uart_1_rx_fifo_re; reg basesoc_uart_1_rx_fifo_readable = 1'd0; wire basesoc_uart_1_rx_fifo_syncfifo_we; wire basesoc_uart_1_rx_fifo_syncfifo_writable; wire basesoc_uart_1_rx_fifo_syncfifo_re; wire basesoc_uart_1_rx_fifo_syncfifo_readable; wire [9:0] basesoc_uart_1_rx_fifo_syncfifo_din; wire [9:0] basesoc_uart_1_rx_fifo_syncfifo_dout; reg [4:0] basesoc_uart_1_rx_fifo_level0 = 5'd0; reg basesoc_uart_1_rx_fifo_replace = 1'd0; reg [3:0] basesoc_uart_1_rx_fifo_produce = 4'd0; reg [3:0] basesoc_uart_1_rx_fifo_consume = 4'd0; reg [3:0] basesoc_uart_1_rx_fifo_wrport_adr = 4'd0; wire [9:0] basesoc_uart_1_rx_fifo_wrport_dat_r; wire basesoc_uart_1_rx_fifo_wrport_we; wire [9:0] basesoc_uart_1_rx_fifo_wrport_dat_w; wire basesoc_uart_1_rx_fifo_do_read; wire [3:0] basesoc_uart_1_rx_fifo_rdport_adr; wire [9:0] basesoc_uart_1_rx_fifo_rdport_dat_r; wire basesoc_uart_1_rx_fifo_rdport_re; wire [4:0] basesoc_uart_1_rx_fifo_level1; wire [7:0] basesoc_uart_1_rx_fifo_fifo_in_payload_data; wire basesoc_uart_1_rx_fifo_fifo_in_first; wire basesoc_uart_1_rx_fifo_fifo_in_last; wire [7:0] basesoc_uart_1_rx_fifo_fifo_out_payload_data; wire basesoc_uart_1_rx_fifo_fifo_out_first; wire basesoc_uart_1_rx_fifo_fifo_out_last; reg rs232phytx0_state = 1'd0; reg rs232phytx0_next_state = 1'd0; reg [3:0] basesoc_uart_0_phy_tx_count_rs232phytx0_next_value0 = 4'd0; reg basesoc_uart_0_phy_tx_count_rs232phytx0_next_value_ce0 = 1'd0; reg rs232phytx0_next_value = 1'd0; reg rs232phytx0_next_value_ce = 1'd0; reg [7:0] basesoc_uart_0_phy_tx_data_rs232phytx0_next_value1 = 8'd0; reg basesoc_uart_0_phy_tx_data_rs232phytx0_next_value_ce1 = 1'd0; reg rs232phyrx0_state = 1'd0; reg rs232phyrx0_next_state = 1'd0; reg [3:0] basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value0 = 4'd0; reg basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value_ce0 = 1'd0; reg [7:0] basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value1 = 8'd0; reg basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value_ce1 = 1'd0; reg rs232phytx1_state = 1'd0; reg rs232phytx1_next_state = 1'd0; reg [3:0] basesoc_uart_1_phy_tx_count_rs232phytx1_next_value0 = 4'd0; reg basesoc_uart_1_phy_tx_count_rs232phytx1_next_value_ce0 = 1'd0; reg rs232phytx1_next_value = 1'd0; reg rs232phytx1_next_value_ce = 1'd0; reg [7:0] basesoc_uart_1_phy_tx_data_rs232phytx1_next_value1 = 8'd0; reg basesoc_uart_1_phy_tx_data_rs232phytx1_next_value_ce1 = 1'd0; reg rs232phyrx1_state = 1'd0; reg rs232phyrx1_next_state = 1'd0; reg [3:0] basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value0 = 4'd0; reg basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 = 1'd0; reg [7:0] basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value1 = 8'd0; reg basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 = 1'd0; reg [13:0] basesoc_adr = 14'd0; reg basesoc_we = 1'd0; reg [31:0] basesoc_dat_w = 32'd0; wire [31:0] basesoc_dat_r; wire [29:0] basesoc_wishbone_adr; wire [31:0] basesoc_wishbone_dat_w; reg [31:0] basesoc_wishbone_dat_r = 32'd0; wire [3:0] basesoc_wishbone_sel; wire basesoc_wishbone_cyc; wire basesoc_wishbone_stb; reg basesoc_wishbone_ack = 1'd0; wire basesoc_wishbone_we; wire [2:0] basesoc_wishbone_cti; wire [1:0] basesoc_wishbone_bte; reg basesoc_wishbone_err = 1'd0; wire [29:0] shared_adr; wire [31:0] shared_dat_w; reg [31:0] shared_dat_r = 32'd0; wire [3:0] shared_sel; wire shared_cyc; wire shared_stb; reg shared_ack = 1'd0; wire shared_we; wire [2:0] shared_cti; wire [1:0] shared_bte; wire shared_err; wire [1:0] request; reg grant = 1'd0; reg [1:0] slave_sel = 2'd0; reg [1:0] slave_sel_r = 2'd0; reg error = 1'd0; wire wait_1; wire done; reg [19:0] count = 20'd1000000; wire [13:0] csr_bankarray_interface0_bank_bus_adr; wire csr_bankarray_interface0_bank_bus_we; wire [31:0] csr_bankarray_interface0_bank_bus_dat_w; reg [31:0] csr_bankarray_interface0_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank0_reset0_re = 1'd0; wire [1:0] csr_bankarray_csrbank0_reset0_r; reg csr_bankarray_csrbank0_reset0_we = 1'd0; wire [1:0] csr_bankarray_csrbank0_reset0_w; reg csr_bankarray_csrbank0_scratch0_re = 1'd0; wire [31:0] csr_bankarray_csrbank0_scratch0_r; reg csr_bankarray_csrbank0_scratch0_we = 1'd0; wire [31:0] csr_bankarray_csrbank0_scratch0_w; reg csr_bankarray_csrbank0_bus_errors_re = 1'd0; wire [31:0] csr_bankarray_csrbank0_bus_errors_r; reg csr_bankarray_csrbank0_bus_errors_we = 1'd0; wire [31:0] csr_bankarray_csrbank0_bus_errors_w; wire csr_bankarray_csrbank0_sel; wire [13:0] csr_bankarray_interface1_bank_bus_adr; wire csr_bankarray_interface1_bank_bus_we; wire [31:0] csr_bankarray_interface1_bank_bus_dat_w; reg [31:0] csr_bankarray_interface1_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank1_w0_re = 1'd0; wire [2:0] csr_bankarray_csrbank1_w0_r; reg csr_bankarray_csrbank1_w0_we = 1'd0; wire [2:0] csr_bankarray_csrbank1_w0_w; reg csr_bankarray_csrbank1_r_re = 1'd0; wire csr_bankarray_csrbank1_r_r; reg csr_bankarray_csrbank1_r_we = 1'd0; wire csr_bankarray_csrbank1_r_w; wire csr_bankarray_csrbank1_sel; wire [13:0] csr_bankarray_sram_bus_adr; wire csr_bankarray_sram_bus_we; wire [31:0] csr_bankarray_sram_bus_dat_w; reg [31:0] csr_bankarray_sram_bus_dat_r = 32'd0; wire [5:0] csr_bankarray_adr; wire [7:0] csr_bankarray_dat_r; wire csr_bankarray_sel; reg csr_bankarray_sel_r = 1'd0; wire [13:0] csr_bankarray_interface2_bank_bus_adr; wire csr_bankarray_interface2_bank_bus_we; wire [31:0] csr_bankarray_interface2_bank_bus_dat_w; reg [31:0] csr_bankarray_interface2_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank2_load0_re = 1'd0; wire [31:0] csr_bankarray_csrbank2_load0_r; reg csr_bankarray_csrbank2_load0_we = 1'd0; wire [31:0] csr_bankarray_csrbank2_load0_w; reg csr_bankarray_csrbank2_reload0_re = 1'd0; wire [31:0] csr_bankarray_csrbank2_reload0_r; reg csr_bankarray_csrbank2_reload0_we = 1'd0; wire [31:0] csr_bankarray_csrbank2_reload0_w; reg csr_bankarray_csrbank2_en0_re = 1'd0; wire csr_bankarray_csrbank2_en0_r; reg csr_bankarray_csrbank2_en0_we = 1'd0; wire csr_bankarray_csrbank2_en0_w; reg csr_bankarray_csrbank2_update_value0_re = 1'd0; wire csr_bankarray_csrbank2_update_value0_r; reg csr_bankarray_csrbank2_update_value0_we = 1'd0; wire csr_bankarray_csrbank2_update_value0_w; reg csr_bankarray_csrbank2_value_re = 1'd0; wire [31:0] csr_bankarray_csrbank2_value_r; reg csr_bankarray_csrbank2_value_we = 1'd0; wire [31:0] csr_bankarray_csrbank2_value_w; reg csr_bankarray_csrbank2_ev_status_re = 1'd0; wire csr_bankarray_csrbank2_ev_status_r; reg csr_bankarray_csrbank2_ev_status_we = 1'd0; wire csr_bankarray_csrbank2_ev_status_w; reg csr_bankarray_csrbank2_ev_pending_re = 1'd0; wire csr_bankarray_csrbank2_ev_pending_r; reg csr_bankarray_csrbank2_ev_pending_we = 1'd0; wire csr_bankarray_csrbank2_ev_pending_w; reg csr_bankarray_csrbank2_ev_enable0_re = 1'd0; wire csr_bankarray_csrbank2_ev_enable0_r; reg csr_bankarray_csrbank2_ev_enable0_we = 1'd0; wire csr_bankarray_csrbank2_ev_enable0_w; wire csr_bankarray_csrbank2_sel; wire [13:0] csr_bankarray_interface3_bank_bus_adr; wire csr_bankarray_interface3_bank_bus_we; wire [31:0] csr_bankarray_interface3_bank_bus_dat_w; reg [31:0] csr_bankarray_interface3_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank3_txfull_re = 1'd0; wire csr_bankarray_csrbank3_txfull_r; reg csr_bankarray_csrbank3_txfull_we = 1'd0; wire csr_bankarray_csrbank3_txfull_w; reg csr_bankarray_csrbank3_rxempty_re = 1'd0; wire csr_bankarray_csrbank3_rxempty_r; reg csr_bankarray_csrbank3_rxempty_we = 1'd0; wire csr_bankarray_csrbank3_rxempty_w; reg csr_bankarray_csrbank3_ev_status_re = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_status_r; reg csr_bankarray_csrbank3_ev_status_we = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_status_w; reg csr_bankarray_csrbank3_ev_pending_re = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_pending_r; reg csr_bankarray_csrbank3_ev_pending_we = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_pending_w; reg csr_bankarray_csrbank3_ev_enable0_re = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_enable0_r; reg csr_bankarray_csrbank3_ev_enable0_we = 1'd0; wire [1:0] csr_bankarray_csrbank3_ev_enable0_w; reg csr_bankarray_csrbank3_txempty_re = 1'd0; wire csr_bankarray_csrbank3_txempty_r; reg csr_bankarray_csrbank3_txempty_we = 1'd0; wire csr_bankarray_csrbank3_txempty_w; reg csr_bankarray_csrbank3_rxfull_re = 1'd0; wire csr_bankarray_csrbank3_rxfull_r; reg csr_bankarray_csrbank3_rxfull_we = 1'd0; wire csr_bankarray_csrbank3_rxfull_w; wire csr_bankarray_csrbank3_sel; wire [13:0] csr_bankarray_interface4_bank_bus_adr; wire csr_bankarray_interface4_bank_bus_we; wire [31:0] csr_bankarray_interface4_bank_bus_dat_w; reg [31:0] csr_bankarray_interface4_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank4_tuning_word0_re = 1'd0; wire [31:0] csr_bankarray_csrbank4_tuning_word0_r; reg csr_bankarray_csrbank4_tuning_word0_we = 1'd0; wire [31:0] csr_bankarray_csrbank4_tuning_word0_w; wire csr_bankarray_csrbank4_sel; wire [13:0] csr_bankarray_interface5_bank_bus_adr; wire csr_bankarray_interface5_bank_bus_we; wire [31:0] csr_bankarray_interface5_bank_bus_dat_w; reg [31:0] csr_bankarray_interface5_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank5_txfull_re = 1'd0; wire csr_bankarray_csrbank5_txfull_r; reg csr_bankarray_csrbank5_txfull_we = 1'd0; wire csr_bankarray_csrbank5_txfull_w; reg csr_bankarray_csrbank5_rxempty_re = 1'd0; wire csr_bankarray_csrbank5_rxempty_r; reg csr_bankarray_csrbank5_rxempty_we = 1'd0; wire csr_bankarray_csrbank5_rxempty_w; reg csr_bankarray_csrbank5_ev_status_re = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_status_r; reg csr_bankarray_csrbank5_ev_status_we = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_status_w; reg csr_bankarray_csrbank5_ev_pending_re = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_pending_r; reg csr_bankarray_csrbank5_ev_pending_we = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_pending_w; reg csr_bankarray_csrbank5_ev_enable0_re = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_enable0_r; reg csr_bankarray_csrbank5_ev_enable0_we = 1'd0; wire [1:0] csr_bankarray_csrbank5_ev_enable0_w; reg csr_bankarray_csrbank5_txempty_re = 1'd0; wire csr_bankarray_csrbank5_txempty_r; reg csr_bankarray_csrbank5_txempty_we = 1'd0; wire csr_bankarray_csrbank5_txempty_w; reg csr_bankarray_csrbank5_rxfull_re = 1'd0; wire csr_bankarray_csrbank5_rxfull_r; reg csr_bankarray_csrbank5_rxfull_we = 1'd0; wire csr_bankarray_csrbank5_rxfull_w; wire csr_bankarray_csrbank5_sel; wire [13:0] csr_bankarray_interface6_bank_bus_adr; wire csr_bankarray_interface6_bank_bus_we; wire [31:0] csr_bankarray_interface6_bank_bus_dat_w; reg [31:0] csr_bankarray_interface6_bank_bus_dat_r = 32'd0; reg csr_bankarray_csrbank6_tuning_word0_re = 1'd0; wire [31:0] csr_bankarray_csrbank6_tuning_word0_r; reg csr_bankarray_csrbank6_tuning_word0_we = 1'd0; wire [31:0] csr_bankarray_csrbank6_tuning_word0_w; wire csr_bankarray_csrbank6_sel; wire [13:0] csr_interconnect_adr; wire csr_interconnect_we; wire [31:0] csr_interconnect_dat_w; wire [31:0] csr_interconnect_dat_r; reg state = 1'd0; reg next_state = 1'd0; wire sys_clk; reg sys_rst = 1'd0; wire por_clk; reg int_rst = 1'd1; reg [29:0] array_muxed0 = 30'd0; reg [31:0] array_muxed1 = 32'd0; reg [3:0] array_muxed2 = 4'd0; reg array_muxed3 = 1'd0; reg array_muxed4 = 1'd0; reg array_muxed5 = 1'd0; reg [2:0] array_muxed6 = 3'd0; reg [1:0] array_muxed7 = 2'd0; reg multiregimpl0_regs0 = 1'd0; reg multiregimpl0_regs1 = 1'd0; reg multiregimpl1_regs0 = 1'd0; reg multiregimpl1_regs1 = 1'd0; //------------------------------------------------------------------------------ // Combinatorial Logic //------------------------------------------------------------------------------ assign basesoc_basesoc_reset = (basesoc_basesoc_soc_rst | basesoc_basesoc_cpu_rst); assign basesoc_user_clock2 = user_clock2; assign basesoc_in_in = in_in; assign basesoc_in_out = in_out; assign basesoc_in_oeb = in_oeb; assign basesoc_user_irq = user_irq; assign basesoc_la_data_in = la_data_in; assign basesoc_la_data_out = la_data_out; assign basesoc_la_oenb = la_oenb; assign basesoc_basesoc_bus_error = error; assign basesoc_basesoc_interrupt[0] = basesoc_basesoc_irq; assign basesoc_basesoc_bus_errors_status = basesoc_basesoc_bus_errors; assign basesoc_basesoc_zero_trigger = (basesoc_basesoc_value == 1'd0); assign basesoc_basesoc_zero0 = basesoc_basesoc_zero_status; assign basesoc_basesoc_zero1 = basesoc_basesoc_zero_pending; always @(*) begin basesoc_basesoc_zero_clear <= 1'd0; if ((basesoc_basesoc_pending_re & basesoc_basesoc_pending_r)) begin basesoc_basesoc_zero_clear <= 1'd1; end end assign basesoc_basesoc_irq = (basesoc_basesoc_pending_status & basesoc_basesoc_enable_storage); assign basesoc_basesoc_zero_status = basesoc_basesoc_zero_trigger; always @(*) begin basesoc_uart_0_phy_tx_data_rs232phytx0_next_value_ce1 <= 1'd0; basesoc_uart_0_phy_tx_enable <= 1'd0; rs232phytx0_next_state <= 1'd0; basesoc_uart_0_phy_tx_count_rs232phytx0_next_value0 <= 4'd0; basesoc_uart_0_phy_tx_count_rs232phytx0_next_value_ce0 <= 1'd0; rs232phytx0_next_value <= 1'd0; rs232phytx0_next_value_ce <= 1'd0; basesoc_uart_0_phy_tx_sink_ready <= 1'd0; basesoc_uart_0_phy_tx_data_rs232phytx0_next_value1 <= 8'd0; rs232phytx0_next_state <= rs232phytx0_state; case (rs232phytx0_state) 1'd1: begin basesoc_uart_0_phy_tx_enable <= 1'd1; if (basesoc_uart_0_phy_tx_tick) begin rs232phytx0_next_value <= basesoc_uart_0_phy_tx_data; rs232phytx0_next_value_ce <= 1'd1; basesoc_uart_0_phy_tx_count_rs232phytx0_next_value0 <= (basesoc_uart_0_phy_tx_count + 1'd1); basesoc_uart_0_phy_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; basesoc_uart_0_phy_tx_data_rs232phytx0_next_value1 <= {1'd1, basesoc_uart_0_phy_tx_data[7:1]}; basesoc_uart_0_phy_tx_data_rs232phytx0_next_value_ce1 <= 1'd1; if ((basesoc_uart_0_phy_tx_count == 4'd9)) begin basesoc_uart_0_phy_tx_sink_ready <= 1'd1; rs232phytx0_next_state <= 1'd0; end end end default: begin basesoc_uart_0_phy_tx_count_rs232phytx0_next_value0 <= 1'd0; basesoc_uart_0_phy_tx_count_rs232phytx0_next_value_ce0 <= 1'd1; rs232phytx0_next_value <= 1'd1; rs232phytx0_next_value_ce <= 1'd1; if (basesoc_uart_0_phy_tx_sink_valid) begin rs232phytx0_next_value <= 1'd0; rs232phytx0_next_value_ce <= 1'd1; basesoc_uart_0_phy_tx_data_rs232phytx0_next_value1 <= basesoc_uart_0_phy_tx_sink_payload_data; basesoc_uart_0_phy_tx_data_rs232phytx0_next_value_ce1 <= 1'd1; rs232phytx0_next_state <= 1'd1; end end endcase end always @(*) begin basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value_ce1 <= 1'd0; basesoc_uart_0_phy_rx_source_payload_data <= 8'd0; basesoc_uart_0_phy_rx_enable <= 1'd0; rs232phyrx0_next_state <= 1'd0; basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value0 <= 4'd0; basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value_ce0 <= 1'd0; basesoc_uart_0_phy_rx_source_valid <= 1'd0; basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value1 <= 8'd0; rs232phyrx0_next_state <= rs232phyrx0_state; case (rs232phyrx0_state) 1'd1: begin basesoc_uart_0_phy_rx_enable <= 1'd1; if (basesoc_uart_0_phy_rx_tick) begin basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value0 <= (basesoc_uart_0_phy_rx_count + 1'd1); basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value1 <= {basesoc_uart_0_phy_rx_rx, basesoc_uart_0_phy_rx_data[7:1]}; basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value_ce1 <= 1'd1; if ((basesoc_uart_0_phy_rx_count == 4'd9)) begin basesoc_uart_0_phy_rx_source_valid <= (basesoc_uart_0_phy_rx_rx == 1'd1); basesoc_uart_0_phy_rx_source_payload_data <= basesoc_uart_0_phy_rx_data; rs232phyrx0_next_state <= 1'd0; end end end default: begin basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value0 <= 1'd0; basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value_ce0 <= 1'd1; if (((basesoc_uart_0_phy_rx_rx == 1'd0) & (basesoc_uart_0_phy_rx_rx_d == 1'd1))) begin rs232phyrx0_next_state <= 1'd1; end end endcase end assign basesoc_uart_0_uart_sink_valid = basesoc_uart_0_phy_rx_source_valid; assign basesoc_uart_0_phy_rx_source_ready = basesoc_uart_0_uart_sink_ready; assign basesoc_uart_0_uart_sink_first = basesoc_uart_0_phy_rx_source_first; assign basesoc_uart_0_uart_sink_last = basesoc_uart_0_phy_rx_source_last; assign basesoc_uart_0_uart_sink_payload_data = basesoc_uart_0_phy_rx_source_payload_data; assign basesoc_uart_0_phy_tx_sink_valid = basesoc_uart_0_uart_source_valid; assign basesoc_uart_0_uart_source_ready = basesoc_uart_0_phy_tx_sink_ready; assign basesoc_uart_0_phy_tx_sink_first = basesoc_uart_0_uart_source_first; assign basesoc_uart_0_phy_tx_sink_last = basesoc_uart_0_uart_source_last; assign basesoc_uart_0_phy_tx_sink_payload_data = basesoc_uart_0_uart_source_payload_data; assign basesoc_uart_0_tx_fifo_sink_valid = basesoc_uart_0_rxtx_re; assign basesoc_uart_0_tx_fifo_sink_payload_data = basesoc_uart_0_rxtx_r; assign basesoc_uart_0_uart_source_valid = basesoc_uart_0_tx_fifo_source_valid; assign basesoc_uart_0_tx_fifo_source_ready = basesoc_uart_0_uart_source_ready; assign basesoc_uart_0_uart_source_first = basesoc_uart_0_tx_fifo_source_first; assign basesoc_uart_0_uart_source_last = basesoc_uart_0_tx_fifo_source_last; assign basesoc_uart_0_uart_source_payload_data = basesoc_uart_0_tx_fifo_source_payload_data; assign basesoc_uart_0_txfull_status = (~basesoc_uart_0_tx_fifo_sink_ready); assign basesoc_uart_0_txempty_status = (~basesoc_uart_0_tx_fifo_source_valid); assign basesoc_uart_0_tx_trigger = basesoc_uart_0_tx_fifo_sink_ready; assign basesoc_uart_0_rx_fifo_sink_valid = basesoc_uart_0_uart_sink_valid; assign basesoc_uart_0_uart_sink_ready = basesoc_uart_0_rx_fifo_sink_ready; assign basesoc_uart_0_rx_fifo_sink_first = basesoc_uart_0_uart_sink_first; assign basesoc_uart_0_rx_fifo_sink_last = basesoc_uart_0_uart_sink_last; assign basesoc_uart_0_rx_fifo_sink_payload_data = basesoc_uart_0_uart_sink_payload_data; assign basesoc_uart_0_rxtx_w = basesoc_uart_0_rx_fifo_source_payload_data; assign basesoc_uart_0_rx_fifo_source_ready = (basesoc_uart_0_rx_clear | (1'd0 & basesoc_uart_0_rxtx_we)); assign basesoc_uart_0_rxempty_status = (~basesoc_uart_0_rx_fifo_source_valid); assign basesoc_uart_0_rxfull_status = (~basesoc_uart_0_rx_fifo_sink_ready); assign basesoc_uart_0_rx_trigger = basesoc_uart_0_rx_fifo_source_valid; assign basesoc_uart_0_tx0 = basesoc_uart_0_tx_status; assign basesoc_uart_0_tx1 = basesoc_uart_0_tx_pending; always @(*) begin basesoc_uart_0_tx_clear <= 1'd0; if ((basesoc_uart_0_pending_re & basesoc_uart_0_pending_r[0])) begin basesoc_uart_0_tx_clear <= 1'd1; end end assign basesoc_uart_0_rx0 = basesoc_uart_0_rx_status; assign basesoc_uart_0_rx1 = basesoc_uart_0_rx_pending; always @(*) begin basesoc_uart_0_rx_clear <= 1'd0; if ((basesoc_uart_0_pending_re & basesoc_uart_0_pending_r[1])) begin basesoc_uart_0_rx_clear <= 1'd1; end end assign basesoc_uart_0_irq = ((basesoc_uart_0_pending_status[0] & basesoc_uart_0_enable_storage[0]) | (basesoc_uart_0_pending_status[1] & basesoc_uart_0_enable_storage[1])); assign basesoc_uart_0_tx_status = basesoc_uart_0_tx_trigger; assign basesoc_uart_0_rx_status = basesoc_uart_0_rx_trigger; assign basesoc_uart_0_tx_fifo_syncfifo_din = {basesoc_uart_0_tx_fifo_fifo_in_last, basesoc_uart_0_tx_fifo_fifo_in_first, basesoc_uart_0_tx_fifo_fifo_in_payload_data}; assign {basesoc_uart_0_tx_fifo_fifo_out_last, basesoc_uart_0_tx_fifo_fifo_out_first, basesoc_uart_0_tx_fifo_fifo_out_payload_data} = basesoc_uart_0_tx_fifo_syncfifo_dout; assign basesoc_uart_0_tx_fifo_sink_ready = basesoc_uart_0_tx_fifo_syncfifo_writable; assign basesoc_uart_0_tx_fifo_syncfifo_we = basesoc_uart_0_tx_fifo_sink_valid; assign basesoc_uart_0_tx_fifo_fifo_in_first = basesoc_uart_0_tx_fifo_sink_first; assign basesoc_uart_0_tx_fifo_fifo_in_last = basesoc_uart_0_tx_fifo_sink_last; assign basesoc_uart_0_tx_fifo_fifo_in_payload_data = basesoc_uart_0_tx_fifo_sink_payload_data; assign basesoc_uart_0_tx_fifo_source_valid = basesoc_uart_0_tx_fifo_readable; assign basesoc_uart_0_tx_fifo_source_first = basesoc_uart_0_tx_fifo_fifo_out_first; assign basesoc_uart_0_tx_fifo_source_last = basesoc_uart_0_tx_fifo_fifo_out_last; assign basesoc_uart_0_tx_fifo_source_payload_data = basesoc_uart_0_tx_fifo_fifo_out_payload_data; assign basesoc_uart_0_tx_fifo_re = basesoc_uart_0_tx_fifo_source_ready; assign basesoc_uart_0_tx_fifo_syncfifo_re = (basesoc_uart_0_tx_fifo_syncfifo_readable & ((~basesoc_uart_0_tx_fifo_readable) | basesoc_uart_0_tx_fifo_re)); assign basesoc_uart_0_tx_fifo_level1 = (basesoc_uart_0_tx_fifo_level0 + basesoc_uart_0_tx_fifo_readable); always @(*) begin basesoc_uart_0_tx_fifo_wrport_adr <= 4'd0; if (basesoc_uart_0_tx_fifo_replace) begin basesoc_uart_0_tx_fifo_wrport_adr <= (basesoc_uart_0_tx_fifo_produce - 1'd1); end else begin basesoc_uart_0_tx_fifo_wrport_adr <= basesoc_uart_0_tx_fifo_produce; end end assign basesoc_uart_0_tx_fifo_wrport_dat_w = basesoc_uart_0_tx_fifo_syncfifo_din; assign basesoc_uart_0_tx_fifo_wrport_we = (basesoc_uart_0_tx_fifo_syncfifo_we & (basesoc_uart_0_tx_fifo_syncfifo_writable | basesoc_uart_0_tx_fifo_replace)); assign basesoc_uart_0_tx_fifo_do_read = (basesoc_uart_0_tx_fifo_syncfifo_readable & basesoc_uart_0_tx_fifo_syncfifo_re); assign basesoc_uart_0_tx_fifo_rdport_adr = basesoc_uart_0_tx_fifo_consume; assign basesoc_uart_0_tx_fifo_syncfifo_dout = basesoc_uart_0_tx_fifo_rdport_dat_r; assign basesoc_uart_0_tx_fifo_rdport_re = basesoc_uart_0_tx_fifo_do_read; assign basesoc_uart_0_tx_fifo_syncfifo_writable = (basesoc_uart_0_tx_fifo_level0 != 5'd16); assign basesoc_uart_0_tx_fifo_syncfifo_readable = (basesoc_uart_0_tx_fifo_level0 != 1'd0); assign basesoc_uart_0_rx_fifo_syncfifo_din = {basesoc_uart_0_rx_fifo_fifo_in_last, basesoc_uart_0_rx_fifo_fifo_in_first, basesoc_uart_0_rx_fifo_fifo_in_payload_data}; assign {basesoc_uart_0_rx_fifo_fifo_out_last, basesoc_uart_0_rx_fifo_fifo_out_first, basesoc_uart_0_rx_fifo_fifo_out_payload_data} = basesoc_uart_0_rx_fifo_syncfifo_dout; assign basesoc_uart_0_rx_fifo_sink_ready = basesoc_uart_0_rx_fifo_syncfifo_writable; assign basesoc_uart_0_rx_fifo_syncfifo_we = basesoc_uart_0_rx_fifo_sink_valid; assign basesoc_uart_0_rx_fifo_fifo_in_first = basesoc_uart_0_rx_fifo_sink_first; assign basesoc_uart_0_rx_fifo_fifo_in_last = basesoc_uart_0_rx_fifo_sink_last; assign basesoc_uart_0_rx_fifo_fifo_in_payload_data = basesoc_uart_0_rx_fifo_sink_payload_data; assign basesoc_uart_0_rx_fifo_source_valid = basesoc_uart_0_rx_fifo_readable; assign basesoc_uart_0_rx_fifo_source_first = basesoc_uart_0_rx_fifo_fifo_out_first; assign basesoc_uart_0_rx_fifo_source_last = basesoc_uart_0_rx_fifo_fifo_out_last; assign basesoc_uart_0_rx_fifo_source_payload_data = basesoc_uart_0_rx_fifo_fifo_out_payload_data; assign basesoc_uart_0_rx_fifo_re = basesoc_uart_0_rx_fifo_source_ready; assign basesoc_uart_0_rx_fifo_syncfifo_re = (basesoc_uart_0_rx_fifo_syncfifo_readable & ((~basesoc_uart_0_rx_fifo_readable) | basesoc_uart_0_rx_fifo_re)); assign basesoc_uart_0_rx_fifo_level1 = (basesoc_uart_0_rx_fifo_level0 + basesoc_uart_0_rx_fifo_readable); always @(*) begin basesoc_uart_0_rx_fifo_wrport_adr <= 4'd0; if (basesoc_uart_0_rx_fifo_replace) begin basesoc_uart_0_rx_fifo_wrport_adr <= (basesoc_uart_0_rx_fifo_produce - 1'd1); end else begin basesoc_uart_0_rx_fifo_wrport_adr <= basesoc_uart_0_rx_fifo_produce; end end assign basesoc_uart_0_rx_fifo_wrport_dat_w = basesoc_uart_0_rx_fifo_syncfifo_din; assign basesoc_uart_0_rx_fifo_wrport_we = (basesoc_uart_0_rx_fifo_syncfifo_we & (basesoc_uart_0_rx_fifo_syncfifo_writable | basesoc_uart_0_rx_fifo_replace)); assign basesoc_uart_0_rx_fifo_do_read = (basesoc_uart_0_rx_fifo_syncfifo_readable & basesoc_uart_0_rx_fifo_syncfifo_re); assign basesoc_uart_0_rx_fifo_rdport_adr = basesoc_uart_0_rx_fifo_consume; assign basesoc_uart_0_rx_fifo_syncfifo_dout = basesoc_uart_0_rx_fifo_rdport_dat_r; assign basesoc_uart_0_rx_fifo_rdport_re = basesoc_uart_0_rx_fifo_do_read; assign basesoc_uart_0_rx_fifo_syncfifo_writable = (basesoc_uart_0_rx_fifo_level0 != 5'd16); assign basesoc_uart_0_rx_fifo_syncfifo_readable = (basesoc_uart_0_rx_fifo_level0 != 1'd0); always @(*) begin basesoc_uart_1_phy_tx_enable <= 1'd0; rs232phytx1_next_state <= 1'd0; basesoc_uart_1_phy_tx_count_rs232phytx1_next_value0 <= 4'd0; basesoc_uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd0; rs232phytx1_next_value <= 1'd0; rs232phytx1_next_value_ce <= 1'd0; basesoc_uart_1_phy_tx_sink_ready <= 1'd0; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value1 <= 8'd0; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value_ce1 <= 1'd0; rs232phytx1_next_state <= rs232phytx1_state; case (rs232phytx1_state) 1'd1: begin basesoc_uart_1_phy_tx_enable <= 1'd1; if (basesoc_uart_1_phy_tx_tick) begin rs232phytx1_next_value <= basesoc_uart_1_phy_tx_data; rs232phytx1_next_value_ce <= 1'd1; basesoc_uart_1_phy_tx_count_rs232phytx1_next_value0 <= (basesoc_uart_1_phy_tx_count + 1'd1); basesoc_uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value1 <= {1'd1, basesoc_uart_1_phy_tx_data[7:1]}; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value_ce1 <= 1'd1; if ((basesoc_uart_1_phy_tx_count == 4'd9)) begin basesoc_uart_1_phy_tx_sink_ready <= 1'd1; rs232phytx1_next_state <= 1'd0; end end end default: begin basesoc_uart_1_phy_tx_count_rs232phytx1_next_value0 <= 1'd0; basesoc_uart_1_phy_tx_count_rs232phytx1_next_value_ce0 <= 1'd1; rs232phytx1_next_value <= 1'd1; rs232phytx1_next_value_ce <= 1'd1; if (basesoc_uart_1_phy_tx_sink_valid) begin rs232phytx1_next_value <= 1'd0; rs232phytx1_next_value_ce <= 1'd1; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value1 <= basesoc_uart_1_phy_tx_sink_payload_data; basesoc_uart_1_phy_tx_data_rs232phytx1_next_value_ce1 <= 1'd1; rs232phytx1_next_state <= 1'd1; end end endcase end always @(*) begin basesoc_uart_1_phy_rx_enable <= 1'd0; rs232phyrx1_next_state <= 1'd0; basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 4'd0; basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd0; basesoc_uart_1_phy_rx_source_valid <= 1'd0; basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value1 <= 8'd0; basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd0; basesoc_uart_1_phy_rx_source_payload_data <= 8'd0; rs232phyrx1_next_state <= rs232phyrx1_state; case (rs232phyrx1_state) 1'd1: begin basesoc_uart_1_phy_rx_enable <= 1'd1; if (basesoc_uart_1_phy_rx_tick) begin basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value0 <= (basesoc_uart_1_phy_rx_count + 1'd1); basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value1 <= {basesoc_uart_1_phy_rx_rx, basesoc_uart_1_phy_rx_data[7:1]}; basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value_ce1 <= 1'd1; if ((basesoc_uart_1_phy_rx_count == 4'd9)) begin basesoc_uart_1_phy_rx_source_valid <= (basesoc_uart_1_phy_rx_rx == 1'd1); basesoc_uart_1_phy_rx_source_payload_data <= basesoc_uart_1_phy_rx_data; rs232phyrx1_next_state <= 1'd0; end end end default: begin basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value0 <= 1'd0; basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value_ce0 <= 1'd1; if (((basesoc_uart_1_phy_rx_rx == 1'd0) & (basesoc_uart_1_phy_rx_rx_d == 1'd1))) begin rs232phyrx1_next_state <= 1'd1; end end endcase end assign basesoc_uart_1_uart_sink_valid = basesoc_uart_1_phy_rx_source_valid; assign basesoc_uart_1_phy_rx_source_ready = basesoc_uart_1_uart_sink_ready; assign basesoc_uart_1_uart_sink_first = basesoc_uart_1_phy_rx_source_first; assign basesoc_uart_1_uart_sink_last = basesoc_uart_1_phy_rx_source_last; assign basesoc_uart_1_uart_sink_payload_data = basesoc_uart_1_phy_rx_source_payload_data; assign basesoc_uart_1_phy_tx_sink_valid = basesoc_uart_1_uart_source_valid; assign basesoc_uart_1_uart_source_ready = basesoc_uart_1_phy_tx_sink_ready; assign basesoc_uart_1_phy_tx_sink_first = basesoc_uart_1_uart_source_first; assign basesoc_uart_1_phy_tx_sink_last = basesoc_uart_1_uart_source_last; assign basesoc_uart_1_phy_tx_sink_payload_data = basesoc_uart_1_uart_source_payload_data; assign basesoc_uart_1_tx_fifo_sink_valid = basesoc_uart_1_rxtx_re; assign basesoc_uart_1_tx_fifo_sink_payload_data = basesoc_uart_1_rxtx_r; assign basesoc_uart_1_uart_source_valid = basesoc_uart_1_tx_fifo_source_valid; assign basesoc_uart_1_tx_fifo_source_ready = basesoc_uart_1_uart_source_ready; assign basesoc_uart_1_uart_source_first = basesoc_uart_1_tx_fifo_source_first; assign basesoc_uart_1_uart_source_last = basesoc_uart_1_tx_fifo_source_last; assign basesoc_uart_1_uart_source_payload_data = basesoc_uart_1_tx_fifo_source_payload_data; assign basesoc_uart_1_txfull_status = (~basesoc_uart_1_tx_fifo_sink_ready); assign basesoc_uart_1_txempty_status = (~basesoc_uart_1_tx_fifo_source_valid); assign basesoc_uart_1_tx_trigger = basesoc_uart_1_tx_fifo_sink_ready; assign basesoc_uart_1_rx_fifo_sink_valid = basesoc_uart_1_uart_sink_valid; assign basesoc_uart_1_uart_sink_ready = basesoc_uart_1_rx_fifo_sink_ready; assign basesoc_uart_1_rx_fifo_sink_first = basesoc_uart_1_uart_sink_first; assign basesoc_uart_1_rx_fifo_sink_last = basesoc_uart_1_uart_sink_last; assign basesoc_uart_1_rx_fifo_sink_payload_data = basesoc_uart_1_uart_sink_payload_data; assign basesoc_uart_1_rxtx_w = basesoc_uart_1_rx_fifo_source_payload_data; assign basesoc_uart_1_rx_fifo_source_ready = (basesoc_uart_1_rx_clear | (1'd0 & basesoc_uart_1_rxtx_we)); assign basesoc_uart_1_rxempty_status = (~basesoc_uart_1_rx_fifo_source_valid); assign basesoc_uart_1_rxfull_status = (~basesoc_uart_1_rx_fifo_sink_ready); assign basesoc_uart_1_rx_trigger = basesoc_uart_1_rx_fifo_source_valid; assign basesoc_uart_1_tx0 = basesoc_uart_1_tx_status; assign basesoc_uart_1_tx1 = basesoc_uart_1_tx_pending; always @(*) begin basesoc_uart_1_tx_clear <= 1'd0; if ((basesoc_uart_1_pending_re & basesoc_uart_1_pending_r[0])) begin basesoc_uart_1_tx_clear <= 1'd1; end end assign basesoc_uart_1_rx0 = basesoc_uart_1_rx_status; assign basesoc_uart_1_rx1 = basesoc_uart_1_rx_pending; always @(*) begin basesoc_uart_1_rx_clear <= 1'd0; if ((basesoc_uart_1_pending_re & basesoc_uart_1_pending_r[1])) begin basesoc_uart_1_rx_clear <= 1'd1; end end assign basesoc_uart_1_irq = ((basesoc_uart_1_pending_status[0] & basesoc_uart_1_enable_storage[0]) | (basesoc_uart_1_pending_status[1] & basesoc_uart_1_enable_storage[1])); assign basesoc_uart_1_tx_status = basesoc_uart_1_tx_trigger; assign basesoc_uart_1_rx_status = basesoc_uart_1_rx_trigger; assign basesoc_uart_1_tx_fifo_syncfifo_din = {basesoc_uart_1_tx_fifo_fifo_in_last, basesoc_uart_1_tx_fifo_fifo_in_first, basesoc_uart_1_tx_fifo_fifo_in_payload_data}; assign {basesoc_uart_1_tx_fifo_fifo_out_last, basesoc_uart_1_tx_fifo_fifo_out_first, basesoc_uart_1_tx_fifo_fifo_out_payload_data} = basesoc_uart_1_tx_fifo_syncfifo_dout; assign basesoc_uart_1_tx_fifo_sink_ready = basesoc_uart_1_tx_fifo_syncfifo_writable; assign basesoc_uart_1_tx_fifo_syncfifo_we = basesoc_uart_1_tx_fifo_sink_valid; assign basesoc_uart_1_tx_fifo_fifo_in_first = basesoc_uart_1_tx_fifo_sink_first; assign basesoc_uart_1_tx_fifo_fifo_in_last = basesoc_uart_1_tx_fifo_sink_last; assign basesoc_uart_1_tx_fifo_fifo_in_payload_data = basesoc_uart_1_tx_fifo_sink_payload_data; assign basesoc_uart_1_tx_fifo_source_valid = basesoc_uart_1_tx_fifo_readable; assign basesoc_uart_1_tx_fifo_source_first = basesoc_uart_1_tx_fifo_fifo_out_first; assign basesoc_uart_1_tx_fifo_source_last = basesoc_uart_1_tx_fifo_fifo_out_last; assign basesoc_uart_1_tx_fifo_source_payload_data = basesoc_uart_1_tx_fifo_fifo_out_payload_data; assign basesoc_uart_1_tx_fifo_re = basesoc_uart_1_tx_fifo_source_ready; assign basesoc_uart_1_tx_fifo_syncfifo_re = (basesoc_uart_1_tx_fifo_syncfifo_readable & ((~basesoc_uart_1_tx_fifo_readable) | basesoc_uart_1_tx_fifo_re)); assign basesoc_uart_1_tx_fifo_level1 = (basesoc_uart_1_tx_fifo_level0 + basesoc_uart_1_tx_fifo_readable); always @(*) begin basesoc_uart_1_tx_fifo_wrport_adr <= 4'd0; if (basesoc_uart_1_tx_fifo_replace) begin basesoc_uart_1_tx_fifo_wrport_adr <= (basesoc_uart_1_tx_fifo_produce - 1'd1); end else begin basesoc_uart_1_tx_fifo_wrport_adr <= basesoc_uart_1_tx_fifo_produce; end end assign basesoc_uart_1_tx_fifo_wrport_dat_w = basesoc_uart_1_tx_fifo_syncfifo_din; assign basesoc_uart_1_tx_fifo_wrport_we = (basesoc_uart_1_tx_fifo_syncfifo_we & (basesoc_uart_1_tx_fifo_syncfifo_writable | basesoc_uart_1_tx_fifo_replace)); assign basesoc_uart_1_tx_fifo_do_read = (basesoc_uart_1_tx_fifo_syncfifo_readable & basesoc_uart_1_tx_fifo_syncfifo_re); assign basesoc_uart_1_tx_fifo_rdport_adr = basesoc_uart_1_tx_fifo_consume; assign basesoc_uart_1_tx_fifo_syncfifo_dout = basesoc_uart_1_tx_fifo_rdport_dat_r; assign basesoc_uart_1_tx_fifo_rdport_re = basesoc_uart_1_tx_fifo_do_read; assign basesoc_uart_1_tx_fifo_syncfifo_writable = (basesoc_uart_1_tx_fifo_level0 != 5'd16); assign basesoc_uart_1_tx_fifo_syncfifo_readable = (basesoc_uart_1_tx_fifo_level0 != 1'd0); assign basesoc_uart_1_rx_fifo_syncfifo_din = {basesoc_uart_1_rx_fifo_fifo_in_last, basesoc_uart_1_rx_fifo_fifo_in_first, basesoc_uart_1_rx_fifo_fifo_in_payload_data}; assign {basesoc_uart_1_rx_fifo_fifo_out_last, basesoc_uart_1_rx_fifo_fifo_out_first, basesoc_uart_1_rx_fifo_fifo_out_payload_data} = basesoc_uart_1_rx_fifo_syncfifo_dout; assign basesoc_uart_1_rx_fifo_sink_ready = basesoc_uart_1_rx_fifo_syncfifo_writable; assign basesoc_uart_1_rx_fifo_syncfifo_we = basesoc_uart_1_rx_fifo_sink_valid; assign basesoc_uart_1_rx_fifo_fifo_in_first = basesoc_uart_1_rx_fifo_sink_first; assign basesoc_uart_1_rx_fifo_fifo_in_last = basesoc_uart_1_rx_fifo_sink_last; assign basesoc_uart_1_rx_fifo_fifo_in_payload_data = basesoc_uart_1_rx_fifo_sink_payload_data; assign basesoc_uart_1_rx_fifo_source_valid = basesoc_uart_1_rx_fifo_readable; assign basesoc_uart_1_rx_fifo_source_first = basesoc_uart_1_rx_fifo_fifo_out_first; assign basesoc_uart_1_rx_fifo_source_last = basesoc_uart_1_rx_fifo_fifo_out_last; assign basesoc_uart_1_rx_fifo_source_payload_data = basesoc_uart_1_rx_fifo_fifo_out_payload_data; assign basesoc_uart_1_rx_fifo_re = basesoc_uart_1_rx_fifo_source_ready; assign basesoc_uart_1_rx_fifo_syncfifo_re = (basesoc_uart_1_rx_fifo_syncfifo_readable & ((~basesoc_uart_1_rx_fifo_readable) | basesoc_uart_1_rx_fifo_re)); assign basesoc_uart_1_rx_fifo_level1 = (basesoc_uart_1_rx_fifo_level0 + basesoc_uart_1_rx_fifo_readable); always @(*) begin basesoc_uart_1_rx_fifo_wrport_adr <= 4'd0; if (basesoc_uart_1_rx_fifo_replace) begin basesoc_uart_1_rx_fifo_wrport_adr <= (basesoc_uart_1_rx_fifo_produce - 1'd1); end else begin basesoc_uart_1_rx_fifo_wrport_adr <= basesoc_uart_1_rx_fifo_produce; end end assign basesoc_uart_1_rx_fifo_wrport_dat_w = basesoc_uart_1_rx_fifo_syncfifo_din; assign basesoc_uart_1_rx_fifo_wrport_we = (basesoc_uart_1_rx_fifo_syncfifo_we & (basesoc_uart_1_rx_fifo_syncfifo_writable | basesoc_uart_1_rx_fifo_replace)); assign basesoc_uart_1_rx_fifo_do_read = (basesoc_uart_1_rx_fifo_syncfifo_readable & basesoc_uart_1_rx_fifo_syncfifo_re); assign basesoc_uart_1_rx_fifo_rdport_adr = basesoc_uart_1_rx_fifo_consume; assign basesoc_uart_1_rx_fifo_syncfifo_dout = basesoc_uart_1_rx_fifo_rdport_dat_r; assign basesoc_uart_1_rx_fifo_rdport_re = basesoc_uart_1_rx_fifo_do_read; assign basesoc_uart_1_rx_fifo_syncfifo_writable = (basesoc_uart_1_rx_fifo_level0 != 5'd16); assign basesoc_uart_1_rx_fifo_syncfifo_readable = (basesoc_uart_1_rx_fifo_level0 != 1'd0); always @(*) begin basesoc_wishbone_dat_r <= 32'd0; basesoc_adr <= 14'd0; basesoc_we <= 1'd0; next_state <= 1'd0; basesoc_dat_w <= 32'd0; basesoc_wishbone_ack <= 1'd0; next_state <= state; case (state) 1'd1: begin basesoc_wishbone_ack <= 1'd1; basesoc_wishbone_dat_r <= basesoc_dat_r; next_state <= 1'd0; end default: begin basesoc_dat_w <= basesoc_wishbone_dat_w; if ((basesoc_wishbone_cyc & basesoc_wishbone_stb)) begin basesoc_adr <= basesoc_wishbone_adr; basesoc_we <= (basesoc_wishbone_we & (basesoc_wishbone_sel != 1'd0)); next_state <= 1'd1; end end endcase end assign shared_adr = array_muxed0; assign shared_dat_w = array_muxed1; assign shared_sel = array_muxed2; assign shared_cyc = array_muxed3; assign shared_stb = array_muxed4; assign shared_we = array_muxed5; assign shared_cti = array_muxed6; assign shared_bte = array_muxed7; assign basesoc_basesoc_ibus_dat_r = shared_dat_r; assign basesoc_basesoc_dbus_dat_r = shared_dat_r; assign basesoc_basesoc_ibus_ack = (shared_ack & (grant == 1'd0)); assign basesoc_basesoc_dbus_ack = (shared_ack & (grant == 1'd1)); assign basesoc_basesoc_ibus_err = (shared_err & (grant == 1'd0)); assign basesoc_basesoc_dbus_err = (shared_err & (grant == 1'd1)); assign request = {basesoc_basesoc_dbus_cyc, basesoc_basesoc_ibus_cyc}; always @(*) begin slave_sel <= 2'd0; slave_sel[0] <= (shared_adr[29:17] == 1'd0); slave_sel[1] <= (shared_adr[29:14] == 16'd65520); end assign basesoc_sram_bus_adr = shared_adr; assign basesoc_sram_bus_dat_w = shared_dat_w; assign basesoc_sram_bus_sel = shared_sel; assign basesoc_sram_bus_stb = shared_stb; assign basesoc_sram_bus_we = shared_we; assign basesoc_sram_bus_cti = shared_cti; assign basesoc_sram_bus_bte = shared_bte; assign basesoc_wishbone_adr = shared_adr; assign basesoc_wishbone_dat_w = shared_dat_w; assign basesoc_wishbone_sel = shared_sel; assign basesoc_wishbone_stb = shared_stb; assign basesoc_wishbone_we = shared_we; assign basesoc_wishbone_cti = shared_cti; assign basesoc_wishbone_bte = shared_bte; assign basesoc_sram_bus_cyc = (shared_cyc & slave_sel[0]); assign basesoc_wishbone_cyc = (shared_cyc & slave_sel[1]); assign shared_err = (basesoc_sram_bus_err | basesoc_wishbone_err); assign wait_1 = ((shared_stb & shared_cyc) & (~shared_ack)); always @(*) begin shared_dat_r <= 32'd0; error <= 1'd0; shared_ack <= 1'd0; shared_ack <= (basesoc_sram_bus_ack | basesoc_wishbone_ack); shared_dat_r <= (({32{slave_sel_r[0]}} & basesoc_sram_bus_dat_r) | ({32{slave_sel_r[1]}} & basesoc_wishbone_dat_r)); if (done) begin shared_dat_r <= 32'd4294967295; shared_ack <= 1'd1; error <= 1'd1; end end assign done = (count == 1'd0); assign csr_bankarray_csrbank0_sel = (csr_bankarray_interface0_bank_bus_adr[13:9] == 3'd6); assign csr_bankarray_csrbank0_reset0_r = csr_bankarray_interface0_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank0_reset0_re <= 1'd0; csr_bankarray_csrbank0_reset0_we <= 1'd0; if ((csr_bankarray_csrbank0_sel & (csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd0))) begin csr_bankarray_csrbank0_reset0_re <= csr_bankarray_interface0_bank_bus_we; csr_bankarray_csrbank0_reset0_we <= (~csr_bankarray_interface0_bank_bus_we); end end assign csr_bankarray_csrbank0_scratch0_r = csr_bankarray_interface0_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank0_scratch0_we <= 1'd0; csr_bankarray_csrbank0_scratch0_re <= 1'd0; if ((csr_bankarray_csrbank0_sel & (csr_bankarray_interface0_bank_bus_adr[8:0] == 1'd1))) begin csr_bankarray_csrbank0_scratch0_re <= csr_bankarray_interface0_bank_bus_we; csr_bankarray_csrbank0_scratch0_we <= (~csr_bankarray_interface0_bank_bus_we); end end assign csr_bankarray_csrbank0_bus_errors_r = csr_bankarray_interface0_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank0_bus_errors_re <= 1'd0; csr_bankarray_csrbank0_bus_errors_we <= 1'd0; if ((csr_bankarray_csrbank0_sel & (csr_bankarray_interface0_bank_bus_adr[8:0] == 2'd2))) begin csr_bankarray_csrbank0_bus_errors_re <= csr_bankarray_interface0_bank_bus_we; csr_bankarray_csrbank0_bus_errors_we <= (~csr_bankarray_interface0_bank_bus_we); end end always @(*) begin basesoc_basesoc_soc_rst <= 1'd0; if (basesoc_basesoc_reset_re) begin basesoc_basesoc_soc_rst <= basesoc_basesoc_reset_storage[0]; end end assign basesoc_basesoc_cpu_rst = basesoc_basesoc_reset_storage[1]; assign csr_bankarray_csrbank0_reset0_w = basesoc_basesoc_reset_storage[1:0]; assign csr_bankarray_csrbank0_scratch0_w = basesoc_basesoc_scratch_storage[31:0]; assign csr_bankarray_csrbank0_bus_errors_w = basesoc_basesoc_bus_errors_status[31:0]; assign basesoc_basesoc_bus_errors_we = csr_bankarray_csrbank0_bus_errors_we; assign csr_bankarray_csrbank1_sel = (csr_bankarray_interface1_bank_bus_adr[13:9] == 1'd1); assign csr_bankarray_csrbank1_w0_r = csr_bankarray_interface1_bank_bus_dat_w[2:0]; always @(*) begin csr_bankarray_csrbank1_w0_we <= 1'd0; csr_bankarray_csrbank1_w0_re <= 1'd0; if ((csr_bankarray_csrbank1_sel & (csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd0))) begin csr_bankarray_csrbank1_w0_re <= csr_bankarray_interface1_bank_bus_we; csr_bankarray_csrbank1_w0_we <= (~csr_bankarray_interface1_bank_bus_we); end end assign csr_bankarray_csrbank1_r_r = csr_bankarray_interface1_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank1_r_re <= 1'd0; csr_bankarray_csrbank1_r_we <= 1'd0; if ((csr_bankarray_csrbank1_sel & (csr_bankarray_interface1_bank_bus_adr[8:0] == 1'd1))) begin csr_bankarray_csrbank1_r_re <= csr_bankarray_interface1_bank_bus_we; csr_bankarray_csrbank1_r_we <= (~csr_bankarray_interface1_bank_bus_we); end end assign basesoc_scl = basesoc__w_storage[0]; assign basesoc_oe = basesoc__w_storage[1]; assign basesoc_sda0 = basesoc__w_storage[2]; assign csr_bankarray_csrbank1_w0_w = basesoc__w_storage[2:0]; assign basesoc__r_status = basesoc_sda1; assign csr_bankarray_csrbank1_r_w = basesoc__r_status; assign basesoc__r_we = csr_bankarray_csrbank1_r_we; assign csr_bankarray_sel = (csr_bankarray_sram_bus_adr[13:9] == 3'd7); always @(*) begin csr_bankarray_sram_bus_dat_r <= 32'd0; if (csr_bankarray_sel_r) begin csr_bankarray_sram_bus_dat_r <= csr_bankarray_dat_r; end end assign csr_bankarray_adr = csr_bankarray_sram_bus_adr[5:0]; assign csr_bankarray_csrbank2_sel = (csr_bankarray_interface2_bank_bus_adr[13:9] == 4'd8); assign csr_bankarray_csrbank2_load0_r = csr_bankarray_interface2_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank2_load0_we <= 1'd0; csr_bankarray_csrbank2_load0_re <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd0))) begin csr_bankarray_csrbank2_load0_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_load0_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_reload0_r = csr_bankarray_interface2_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank2_reload0_re <= 1'd0; csr_bankarray_csrbank2_reload0_we <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 1'd1))) begin csr_bankarray_csrbank2_reload0_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_reload0_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_en0_r = csr_bankarray_interface2_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank2_en0_we <= 1'd0; csr_bankarray_csrbank2_en0_re <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd2))) begin csr_bankarray_csrbank2_en0_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_en0_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_update_value0_r = csr_bankarray_interface2_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank2_update_value0_we <= 1'd0; csr_bankarray_csrbank2_update_value0_re <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 2'd3))) begin csr_bankarray_csrbank2_update_value0_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_update_value0_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_value_r = csr_bankarray_interface2_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank2_value_re <= 1'd0; csr_bankarray_csrbank2_value_we <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd4))) begin csr_bankarray_csrbank2_value_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_value_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_ev_status_r = csr_bankarray_interface2_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank2_ev_status_we <= 1'd0; csr_bankarray_csrbank2_ev_status_re <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd5))) begin csr_bankarray_csrbank2_ev_status_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_ev_status_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_ev_pending_r = csr_bankarray_interface2_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank2_ev_pending_we <= 1'd0; csr_bankarray_csrbank2_ev_pending_re <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd6))) begin csr_bankarray_csrbank2_ev_pending_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_ev_pending_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_ev_enable0_r = csr_bankarray_interface2_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank2_ev_enable0_re <= 1'd0; csr_bankarray_csrbank2_ev_enable0_we <= 1'd0; if ((csr_bankarray_csrbank2_sel & (csr_bankarray_interface2_bank_bus_adr[8:0] == 3'd7))) begin csr_bankarray_csrbank2_ev_enable0_re <= csr_bankarray_interface2_bank_bus_we; csr_bankarray_csrbank2_ev_enable0_we <= (~csr_bankarray_interface2_bank_bus_we); end end assign csr_bankarray_csrbank2_load0_w = basesoc_basesoc_load_storage[31:0]; assign csr_bankarray_csrbank2_reload0_w = basesoc_basesoc_reload_storage[31:0]; assign csr_bankarray_csrbank2_en0_w = basesoc_basesoc_en_storage; assign csr_bankarray_csrbank2_update_value0_w = basesoc_basesoc_update_value_storage; assign csr_bankarray_csrbank2_value_w = basesoc_basesoc_value_status[31:0]; assign basesoc_basesoc_value_we = csr_bankarray_csrbank2_value_we; assign basesoc_basesoc_status_status = basesoc_basesoc_zero0; assign csr_bankarray_csrbank2_ev_status_w = basesoc_basesoc_status_status; assign basesoc_basesoc_status_we = csr_bankarray_csrbank2_ev_status_we; assign basesoc_basesoc_pending_status = basesoc_basesoc_zero1; assign csr_bankarray_csrbank2_ev_pending_w = basesoc_basesoc_pending_status; assign basesoc_basesoc_pending_we = csr_bankarray_csrbank2_ev_pending_we; assign basesoc_basesoc_zero2 = basesoc_basesoc_enable_storage; assign csr_bankarray_csrbank2_ev_enable0_w = basesoc_basesoc_enable_storage; assign csr_bankarray_csrbank3_sel = (csr_bankarray_interface3_bank_bus_adr[13:9] == 2'd3); assign basesoc_uart_0_rxtx_r = csr_bankarray_interface3_bank_bus_dat_w[7:0]; always @(*) begin basesoc_uart_0_rxtx_we <= 1'd0; basesoc_uart_0_rxtx_re <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd0))) begin basesoc_uart_0_rxtx_re <= csr_bankarray_interface3_bank_bus_we; basesoc_uart_0_rxtx_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_txfull_r = csr_bankarray_interface3_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank3_txfull_re <= 1'd0; csr_bankarray_csrbank3_txfull_we <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 1'd1))) begin csr_bankarray_csrbank3_txfull_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_txfull_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_rxempty_r = csr_bankarray_interface3_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank3_rxempty_we <= 1'd0; csr_bankarray_csrbank3_rxempty_re <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd2))) begin csr_bankarray_csrbank3_rxempty_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_rxempty_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_ev_status_r = csr_bankarray_interface3_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank3_ev_status_we <= 1'd0; csr_bankarray_csrbank3_ev_status_re <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 2'd3))) begin csr_bankarray_csrbank3_ev_status_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_ev_status_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_ev_pending_r = csr_bankarray_interface3_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank3_ev_pending_re <= 1'd0; csr_bankarray_csrbank3_ev_pending_we <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd4))) begin csr_bankarray_csrbank3_ev_pending_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_ev_pending_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_ev_enable0_r = csr_bankarray_interface3_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank3_ev_enable0_we <= 1'd0; csr_bankarray_csrbank3_ev_enable0_re <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd5))) begin csr_bankarray_csrbank3_ev_enable0_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_ev_enable0_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_txempty_r = csr_bankarray_interface3_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank3_txempty_we <= 1'd0; csr_bankarray_csrbank3_txempty_re <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd6))) begin csr_bankarray_csrbank3_txempty_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_txempty_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_rxfull_r = csr_bankarray_interface3_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank3_rxfull_re <= 1'd0; csr_bankarray_csrbank3_rxfull_we <= 1'd0; if ((csr_bankarray_csrbank3_sel & (csr_bankarray_interface3_bank_bus_adr[8:0] == 3'd7))) begin csr_bankarray_csrbank3_rxfull_re <= csr_bankarray_interface3_bank_bus_we; csr_bankarray_csrbank3_rxfull_we <= (~csr_bankarray_interface3_bank_bus_we); end end assign csr_bankarray_csrbank3_txfull_w = basesoc_uart_0_txfull_status; assign basesoc_uart_0_txfull_we = csr_bankarray_csrbank3_txfull_we; assign csr_bankarray_csrbank3_rxempty_w = basesoc_uart_0_rxempty_status; assign basesoc_uart_0_rxempty_we = csr_bankarray_csrbank3_rxempty_we; always @(*) begin basesoc_uart_0_status_status <= 2'd0; basesoc_uart_0_status_status[0] <= basesoc_uart_0_tx0; basesoc_uart_0_status_status[1] <= basesoc_uart_0_rx0; end assign csr_bankarray_csrbank3_ev_status_w = basesoc_uart_0_status_status[1:0]; assign basesoc_uart_0_status_we = csr_bankarray_csrbank3_ev_status_we; always @(*) begin basesoc_uart_0_pending_status <= 2'd0; basesoc_uart_0_pending_status[0] <= basesoc_uart_0_tx1; basesoc_uart_0_pending_status[1] <= basesoc_uart_0_rx1; end assign csr_bankarray_csrbank3_ev_pending_w = basesoc_uart_0_pending_status[1:0]; assign basesoc_uart_0_pending_we = csr_bankarray_csrbank3_ev_pending_we; assign basesoc_uart_0_tx2 = basesoc_uart_0_enable_storage[0]; assign basesoc_uart_0_rx2 = basesoc_uart_0_enable_storage[1]; assign csr_bankarray_csrbank3_ev_enable0_w = basesoc_uart_0_enable_storage[1:0]; assign csr_bankarray_csrbank3_txempty_w = basesoc_uart_0_txempty_status; assign basesoc_uart_0_txempty_we = csr_bankarray_csrbank3_txempty_we; assign csr_bankarray_csrbank3_rxfull_w = basesoc_uart_0_rxfull_status; assign basesoc_uart_0_rxfull_we = csr_bankarray_csrbank3_rxfull_we; assign csr_bankarray_csrbank4_sel = (csr_bankarray_interface4_bank_bus_adr[13:9] == 2'd2); assign csr_bankarray_csrbank4_tuning_word0_r = csr_bankarray_interface4_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank4_tuning_word0_re <= 1'd0; csr_bankarray_csrbank4_tuning_word0_we <= 1'd0; if ((csr_bankarray_csrbank4_sel & (csr_bankarray_interface4_bank_bus_adr[8:0] == 1'd0))) begin csr_bankarray_csrbank4_tuning_word0_re <= csr_bankarray_interface4_bank_bus_we; csr_bankarray_csrbank4_tuning_word0_we <= (~csr_bankarray_interface4_bank_bus_we); end end assign csr_bankarray_csrbank4_tuning_word0_w = basesoc_uart_0_phy_storage[31:0]; assign csr_bankarray_csrbank5_sel = (csr_bankarray_interface5_bank_bus_adr[13:9] == 3'd5); assign basesoc_uart_1_rxtx_r = csr_bankarray_interface5_bank_bus_dat_w[7:0]; always @(*) begin basesoc_uart_1_rxtx_re <= 1'd0; basesoc_uart_1_rxtx_we <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd0))) begin basesoc_uart_1_rxtx_re <= csr_bankarray_interface5_bank_bus_we; basesoc_uart_1_rxtx_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_txfull_r = csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank5_txfull_re <= 1'd0; csr_bankarray_csrbank5_txfull_we <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 1'd1))) begin csr_bankarray_csrbank5_txfull_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_txfull_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_rxempty_r = csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank5_rxempty_we <= 1'd0; csr_bankarray_csrbank5_rxempty_re <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 2'd2))) begin csr_bankarray_csrbank5_rxempty_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_rxempty_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_ev_status_r = csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank5_ev_status_we <= 1'd0; csr_bankarray_csrbank5_ev_status_re <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 2'd3))) begin csr_bankarray_csrbank5_ev_status_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_ev_status_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_ev_pending_r = csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank5_ev_pending_re <= 1'd0; csr_bankarray_csrbank5_ev_pending_we <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd4))) begin csr_bankarray_csrbank5_ev_pending_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_ev_pending_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_ev_enable0_r = csr_bankarray_interface5_bank_bus_dat_w[1:0]; always @(*) begin csr_bankarray_csrbank5_ev_enable0_we <= 1'd0; csr_bankarray_csrbank5_ev_enable0_re <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd5))) begin csr_bankarray_csrbank5_ev_enable0_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_ev_enable0_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_txempty_r = csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank5_txempty_we <= 1'd0; csr_bankarray_csrbank5_txempty_re <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd6))) begin csr_bankarray_csrbank5_txempty_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_txempty_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_rxfull_r = csr_bankarray_interface5_bank_bus_dat_w[0]; always @(*) begin csr_bankarray_csrbank5_rxfull_re <= 1'd0; csr_bankarray_csrbank5_rxfull_we <= 1'd0; if ((csr_bankarray_csrbank5_sel & (csr_bankarray_interface5_bank_bus_adr[8:0] == 3'd7))) begin csr_bankarray_csrbank5_rxfull_re <= csr_bankarray_interface5_bank_bus_we; csr_bankarray_csrbank5_rxfull_we <= (~csr_bankarray_interface5_bank_bus_we); end end assign csr_bankarray_csrbank5_txfull_w = basesoc_uart_1_txfull_status; assign basesoc_uart_1_txfull_we = csr_bankarray_csrbank5_txfull_we; assign csr_bankarray_csrbank5_rxempty_w = basesoc_uart_1_rxempty_status; assign basesoc_uart_1_rxempty_we = csr_bankarray_csrbank5_rxempty_we; always @(*) begin basesoc_uart_1_status_status <= 2'd0; basesoc_uart_1_status_status[0] <= basesoc_uart_1_tx0; basesoc_uart_1_status_status[1] <= basesoc_uart_1_rx0; end assign csr_bankarray_csrbank5_ev_status_w = basesoc_uart_1_status_status[1:0]; assign basesoc_uart_1_status_we = csr_bankarray_csrbank5_ev_status_we; always @(*) begin basesoc_uart_1_pending_status <= 2'd0; basesoc_uart_1_pending_status[0] <= basesoc_uart_1_tx1; basesoc_uart_1_pending_status[1] <= basesoc_uart_1_rx1; end assign csr_bankarray_csrbank5_ev_pending_w = basesoc_uart_1_pending_status[1:0]; assign basesoc_uart_1_pending_we = csr_bankarray_csrbank5_ev_pending_we; assign basesoc_uart_1_tx2 = basesoc_uart_1_enable_storage[0]; assign basesoc_uart_1_rx2 = basesoc_uart_1_enable_storage[1]; assign csr_bankarray_csrbank5_ev_enable0_w = basesoc_uart_1_enable_storage[1:0]; assign csr_bankarray_csrbank5_txempty_w = basesoc_uart_1_txempty_status; assign basesoc_uart_1_txempty_we = csr_bankarray_csrbank5_txempty_we; assign csr_bankarray_csrbank5_rxfull_w = basesoc_uart_1_rxfull_status; assign basesoc_uart_1_rxfull_we = csr_bankarray_csrbank5_rxfull_we; assign csr_bankarray_csrbank6_sel = (csr_bankarray_interface6_bank_bus_adr[13:9] == 3'd4); assign csr_bankarray_csrbank6_tuning_word0_r = csr_bankarray_interface6_bank_bus_dat_w[31:0]; always @(*) begin csr_bankarray_csrbank6_tuning_word0_re <= 1'd0; csr_bankarray_csrbank6_tuning_word0_we <= 1'd0; if ((csr_bankarray_csrbank6_sel & (csr_bankarray_interface6_bank_bus_adr[8:0] == 1'd0))) begin csr_bankarray_csrbank6_tuning_word0_re <= csr_bankarray_interface6_bank_bus_we; csr_bankarray_csrbank6_tuning_word0_we <= (~csr_bankarray_interface6_bank_bus_we); end end assign csr_bankarray_csrbank6_tuning_word0_w = basesoc_uart_1_phy_storage[31:0]; assign csr_interconnect_adr = basesoc_adr; assign csr_interconnect_we = basesoc_we; assign csr_interconnect_dat_w = basesoc_dat_w; assign basesoc_dat_r = csr_interconnect_dat_r; assign csr_bankarray_interface0_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface1_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface2_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface3_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface4_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface5_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface6_bank_bus_adr = csr_interconnect_adr; assign csr_bankarray_sram_bus_adr = csr_interconnect_adr; assign csr_bankarray_interface0_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface1_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface2_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface3_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface4_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface5_bank_bus_we = csr_interconnect_we; assign csr_bankarray_interface6_bank_bus_we = csr_interconnect_we; assign csr_bankarray_sram_bus_we = csr_interconnect_we; assign csr_bankarray_interface0_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface1_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface2_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface3_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface4_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface5_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_interface6_bank_bus_dat_w = csr_interconnect_dat_w; assign csr_bankarray_sram_bus_dat_w = csr_interconnect_dat_w; assign csr_interconnect_dat_r = (((((((csr_bankarray_interface0_bank_bus_dat_r | csr_bankarray_interface1_bank_bus_dat_r) | csr_bankarray_interface2_bank_bus_dat_r) | csr_bankarray_interface3_bank_bus_dat_r) | csr_bankarray_interface4_bank_bus_dat_r) | csr_bankarray_interface5_bank_bus_dat_r) | csr_bankarray_interface6_bank_bus_dat_r) | csr_bankarray_sram_bus_dat_r); assign sys_clk = wb_clk_i; assign por_clk = wb_clk_i; always @(*) begin sys_rst <= 1'd0; sys_rst <= wb_rst_i; sys_rst <= int_rst; end always @(*) begin array_muxed0 <= 30'd0; case (grant) 1'd0: begin array_muxed0 <= basesoc_basesoc_ibus_adr; end default: begin array_muxed0 <= basesoc_basesoc_dbus_adr; end endcase end always @(*) begin array_muxed1 <= 32'd0; case (grant) 1'd0: begin array_muxed1 <= basesoc_basesoc_ibus_dat_w; end default: begin array_muxed1 <= basesoc_basesoc_dbus_dat_w; end endcase end always @(*) begin array_muxed2 <= 4'd0; case (grant) 1'd0: begin array_muxed2 <= basesoc_basesoc_ibus_sel; end default: begin array_muxed2 <= basesoc_basesoc_dbus_sel; end endcase end always @(*) begin array_muxed3 <= 1'd0; case (grant) 1'd0: begin array_muxed3 <= basesoc_basesoc_ibus_cyc; end default: begin array_muxed3 <= basesoc_basesoc_dbus_cyc; end endcase end always @(*) begin array_muxed4 <= 1'd0; case (grant) 1'd0: begin array_muxed4 <= basesoc_basesoc_ibus_stb; end default: begin array_muxed4 <= basesoc_basesoc_dbus_stb; end endcase end always @(*) begin array_muxed5 <= 1'd0; case (grant) 1'd0: begin array_muxed5 <= basesoc_basesoc_ibus_we; end default: begin array_muxed5 <= basesoc_basesoc_dbus_we; end endcase end always @(*) begin array_muxed6 <= 3'd0; case (grant) 1'd0: begin array_muxed6 <= basesoc_basesoc_ibus_cti; end default: begin array_muxed6 <= basesoc_basesoc_dbus_cti; end endcase end always @(*) begin array_muxed7 <= 2'd0; case (grant) 1'd0: begin array_muxed7 <= basesoc_basesoc_ibus_bte; end default: begin array_muxed7 <= basesoc_basesoc_dbus_bte; end endcase end assign basesoc_uart_0_phy_rx_rx = multiregimpl0_regs1; assign basesoc_uart_1_phy_rx_rx = multiregimpl1_regs1; //------------------------------------------------------------------------------ // Synchronous Logic //------------------------------------------------------------------------------ always @(posedge por_clk) begin int_rst <= 1'd0; end always @(posedge sys_clk) begin if ((basesoc_basesoc_bus_errors != 32'd4294967295)) begin if (basesoc_basesoc_bus_error) begin basesoc_basesoc_bus_errors <= (basesoc_basesoc_bus_errors + 1'd1); end end if (basesoc_basesoc_en_storage) begin if ((basesoc_basesoc_value == 1'd0)) begin basesoc_basesoc_value <= basesoc_basesoc_reload_storage; end else begin basesoc_basesoc_value <= (basesoc_basesoc_value - 1'd1); end end else begin basesoc_basesoc_value <= basesoc_basesoc_load_storage; end if (basesoc_basesoc_update_value_re) begin basesoc_basesoc_value_status <= basesoc_basesoc_value; end if (basesoc_basesoc_zero_clear) begin basesoc_basesoc_zero_pending <= 1'd0; end basesoc_basesoc_zero_trigger_d <= basesoc_basesoc_zero_trigger; if ((basesoc_basesoc_zero_trigger & (~basesoc_basesoc_zero_trigger_d))) begin basesoc_basesoc_zero_pending <= 1'd1; end {basesoc_uart_0_phy_tx_tick, basesoc_uart_0_phy_tx_phase} <= basesoc_uart_0_phy_storage; if (basesoc_uart_0_phy_tx_enable) begin {basesoc_uart_0_phy_tx_tick, basesoc_uart_0_phy_tx_phase} <= (basesoc_uart_0_phy_tx_phase + basesoc_uart_0_phy_storage); end rs232phytx0_state <= rs232phytx0_next_state; if (basesoc_uart_0_phy_tx_count_rs232phytx0_next_value_ce0) begin basesoc_uart_0_phy_tx_count <= basesoc_uart_0_phy_tx_count_rs232phytx0_next_value0; end if (rs232phytx0_next_value_ce) begin basesoc_in_out[0] <= rs232phytx0_next_value; end if (basesoc_uart_0_phy_tx_data_rs232phytx0_next_value_ce1) begin basesoc_uart_0_phy_tx_data <= basesoc_uart_0_phy_tx_data_rs232phytx0_next_value1; end basesoc_uart_0_phy_rx_rx_d <= basesoc_uart_0_phy_rx_rx; {basesoc_uart_0_phy_rx_tick, basesoc_uart_0_phy_rx_phase} <= 32'd2147483648; if (basesoc_uart_0_phy_rx_enable) begin {basesoc_uart_0_phy_rx_tick, basesoc_uart_0_phy_rx_phase} <= (basesoc_uart_0_phy_rx_phase + basesoc_uart_0_phy_storage); end rs232phyrx0_state <= rs232phyrx0_next_state; if (basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value_ce0) begin basesoc_uart_0_phy_rx_count <= basesoc_uart_0_phy_rx_count_rs232phyrx0_next_value0; end if (basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value_ce1) begin basesoc_uart_0_phy_rx_data <= basesoc_uart_0_phy_rx_data_rs232phyrx0_next_value1; end if (basesoc_uart_0_tx_clear) begin basesoc_uart_0_tx_pending <= 1'd0; end basesoc_uart_0_tx_trigger_d <= basesoc_uart_0_tx_trigger; if ((basesoc_uart_0_tx_trigger & (~basesoc_uart_0_tx_trigger_d))) begin basesoc_uart_0_tx_pending <= 1'd1; end if (basesoc_uart_0_rx_clear) begin basesoc_uart_0_rx_pending <= 1'd0; end basesoc_uart_0_rx_trigger_d <= basesoc_uart_0_rx_trigger; if ((basesoc_uart_0_rx_trigger & (~basesoc_uart_0_rx_trigger_d))) begin basesoc_uart_0_rx_pending <= 1'd1; end if (basesoc_uart_0_tx_fifo_syncfifo_re) begin basesoc_uart_0_tx_fifo_readable <= 1'd1; end else begin if (basesoc_uart_0_tx_fifo_re) begin basesoc_uart_0_tx_fifo_readable <= 1'd0; end end if (((basesoc_uart_0_tx_fifo_syncfifo_we & basesoc_uart_0_tx_fifo_syncfifo_writable) & (~basesoc_uart_0_tx_fifo_replace))) begin basesoc_uart_0_tx_fifo_produce <= (basesoc_uart_0_tx_fifo_produce + 1'd1); end if (basesoc_uart_0_tx_fifo_do_read) begin basesoc_uart_0_tx_fifo_consume <= (basesoc_uart_0_tx_fifo_consume + 1'd1); end if (((basesoc_uart_0_tx_fifo_syncfifo_we & basesoc_uart_0_tx_fifo_syncfifo_writable) & (~basesoc_uart_0_tx_fifo_replace))) begin if ((~basesoc_uart_0_tx_fifo_do_read)) begin basesoc_uart_0_tx_fifo_level0 <= (basesoc_uart_0_tx_fifo_level0 + 1'd1); end end else begin if (basesoc_uart_0_tx_fifo_do_read) begin basesoc_uart_0_tx_fifo_level0 <= (basesoc_uart_0_tx_fifo_level0 - 1'd1); end end if (basesoc_uart_0_rx_fifo_syncfifo_re) begin basesoc_uart_0_rx_fifo_readable <= 1'd1; end else begin if (basesoc_uart_0_rx_fifo_re) begin basesoc_uart_0_rx_fifo_readable <= 1'd0; end end if (((basesoc_uart_0_rx_fifo_syncfifo_we & basesoc_uart_0_rx_fifo_syncfifo_writable) & (~basesoc_uart_0_rx_fifo_replace))) begin basesoc_uart_0_rx_fifo_produce <= (basesoc_uart_0_rx_fifo_produce + 1'd1); end if (basesoc_uart_0_rx_fifo_do_read) begin basesoc_uart_0_rx_fifo_consume <= (basesoc_uart_0_rx_fifo_consume + 1'd1); end if (((basesoc_uart_0_rx_fifo_syncfifo_we & basesoc_uart_0_rx_fifo_syncfifo_writable) & (~basesoc_uart_0_rx_fifo_replace))) begin if ((~basesoc_uart_0_rx_fifo_do_read)) begin basesoc_uart_0_rx_fifo_level0 <= (basesoc_uart_0_rx_fifo_level0 + 1'd1); end end else begin if (basesoc_uart_0_rx_fifo_do_read) begin basesoc_uart_0_rx_fifo_level0 <= (basesoc_uart_0_rx_fifo_level0 - 1'd1); end end {basesoc_uart_1_phy_tx_tick, basesoc_uart_1_phy_tx_phase} <= basesoc_uart_1_phy_storage; if (basesoc_uart_1_phy_tx_enable) begin {basesoc_uart_1_phy_tx_tick, basesoc_uart_1_phy_tx_phase} <= (basesoc_uart_1_phy_tx_phase + basesoc_uart_1_phy_storage); end rs232phytx1_state <= rs232phytx1_next_state; if (basesoc_uart_1_phy_tx_count_rs232phytx1_next_value_ce0) begin basesoc_uart_1_phy_tx_count <= basesoc_uart_1_phy_tx_count_rs232phytx1_next_value0; end if (rs232phytx1_next_value_ce) begin basesoc_in_out[1] <= rs232phytx1_next_value; end if (basesoc_uart_1_phy_tx_data_rs232phytx1_next_value_ce1) begin basesoc_uart_1_phy_tx_data <= basesoc_uart_1_phy_tx_data_rs232phytx1_next_value1; end basesoc_uart_1_phy_rx_rx_d <= basesoc_uart_1_phy_rx_rx; {basesoc_uart_1_phy_rx_tick, basesoc_uart_1_phy_rx_phase} <= 32'd2147483648; if (basesoc_uart_1_phy_rx_enable) begin {basesoc_uart_1_phy_rx_tick, basesoc_uart_1_phy_rx_phase} <= (basesoc_uart_1_phy_rx_phase + basesoc_uart_1_phy_storage); end rs232phyrx1_state <= rs232phyrx1_next_state; if (basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value_ce0) begin basesoc_uart_1_phy_rx_count <= basesoc_uart_1_phy_rx_count_rs232phyrx1_next_value0; end if (basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value_ce1) begin basesoc_uart_1_phy_rx_data <= basesoc_uart_1_phy_rx_data_rs232phyrx1_next_value1; end if (basesoc_uart_1_tx_clear) begin basesoc_uart_1_tx_pending <= 1'd0; end basesoc_uart_1_tx_trigger_d <= basesoc_uart_1_tx_trigger; if ((basesoc_uart_1_tx_trigger & (~basesoc_uart_1_tx_trigger_d))) begin basesoc_uart_1_tx_pending <= 1'd1; end if (basesoc_uart_1_rx_clear) begin basesoc_uart_1_rx_pending <= 1'd0; end basesoc_uart_1_rx_trigger_d <= basesoc_uart_1_rx_trigger; if ((basesoc_uart_1_rx_trigger & (~basesoc_uart_1_rx_trigger_d))) begin basesoc_uart_1_rx_pending <= 1'd1; end if (basesoc_uart_1_tx_fifo_syncfifo_re) begin basesoc_uart_1_tx_fifo_readable <= 1'd1; end else begin if (basesoc_uart_1_tx_fifo_re) begin basesoc_uart_1_tx_fifo_readable <= 1'd0; end end if (((basesoc_uart_1_tx_fifo_syncfifo_we & basesoc_uart_1_tx_fifo_syncfifo_writable) & (~basesoc_uart_1_tx_fifo_replace))) begin basesoc_uart_1_tx_fifo_produce <= (basesoc_uart_1_tx_fifo_produce + 1'd1); end if (basesoc_uart_1_tx_fifo_do_read) begin basesoc_uart_1_tx_fifo_consume <= (basesoc_uart_1_tx_fifo_consume + 1'd1); end if (((basesoc_uart_1_tx_fifo_syncfifo_we & basesoc_uart_1_tx_fifo_syncfifo_writable) & (~basesoc_uart_1_tx_fifo_replace))) begin if ((~basesoc_uart_1_tx_fifo_do_read)) begin basesoc_uart_1_tx_fifo_level0 <= (basesoc_uart_1_tx_fifo_level0 + 1'd1); end end else begin if (basesoc_uart_1_tx_fifo_do_read) begin basesoc_uart_1_tx_fifo_level0 <= (basesoc_uart_1_tx_fifo_level0 - 1'd1); end end if (basesoc_uart_1_rx_fifo_syncfifo_re) begin basesoc_uart_1_rx_fifo_readable <= 1'd1; end else begin if (basesoc_uart_1_rx_fifo_re) begin basesoc_uart_1_rx_fifo_readable <= 1'd0; end end if (((basesoc_uart_1_rx_fifo_syncfifo_we & basesoc_uart_1_rx_fifo_syncfifo_writable) & (~basesoc_uart_1_rx_fifo_replace))) begin basesoc_uart_1_rx_fifo_produce <= (basesoc_uart_1_rx_fifo_produce + 1'd1); end if (basesoc_uart_1_rx_fifo_do_read) begin basesoc_uart_1_rx_fifo_consume <= (basesoc_uart_1_rx_fifo_consume + 1'd1); end if (((basesoc_uart_1_rx_fifo_syncfifo_we & basesoc_uart_1_rx_fifo_syncfifo_writable) & (~basesoc_uart_1_rx_fifo_replace))) begin if ((~basesoc_uart_1_rx_fifo_do_read)) begin basesoc_uart_1_rx_fifo_level0 <= (basesoc_uart_1_rx_fifo_level0 + 1'd1); end end else begin if (basesoc_uart_1_rx_fifo_do_read) begin basesoc_uart_1_rx_fifo_level0 <= (basesoc_uart_1_rx_fifo_level0 - 1'd1); end end state <= next_state; case (grant) 1'd0: begin if ((~request[0])) begin if (request[1]) begin grant <= 1'd1; end end end 1'd1: begin if ((~request[1])) begin if (request[0]) begin grant <= 1'd0; end end end endcase slave_sel_r <= slave_sel; if (wait_1) begin if ((~done)) begin count <= (count - 1'd1); end end else begin count <= 20'd1000000; end csr_bankarray_interface0_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank0_sel) begin case (csr_bankarray_interface0_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface0_bank_bus_dat_r <= csr_bankarray_csrbank0_reset0_w; end 1'd1: begin csr_bankarray_interface0_bank_bus_dat_r <= csr_bankarray_csrbank0_scratch0_w; end 2'd2: begin csr_bankarray_interface0_bank_bus_dat_r <= csr_bankarray_csrbank0_bus_errors_w; end endcase end if (csr_bankarray_csrbank0_reset0_re) begin basesoc_basesoc_reset_storage[1:0] <= csr_bankarray_csrbank0_reset0_r; end basesoc_basesoc_reset_re <= csr_bankarray_csrbank0_reset0_re; if (csr_bankarray_csrbank0_scratch0_re) begin basesoc_basesoc_scratch_storage[31:0] <= csr_bankarray_csrbank0_scratch0_r; end basesoc_basesoc_scratch_re <= csr_bankarray_csrbank0_scratch0_re; basesoc_basesoc_bus_errors_re <= csr_bankarray_csrbank0_bus_errors_re; csr_bankarray_interface1_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank1_sel) begin case (csr_bankarray_interface1_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface1_bank_bus_dat_r <= csr_bankarray_csrbank1_w0_w; end 1'd1: begin csr_bankarray_interface1_bank_bus_dat_r <= csr_bankarray_csrbank1_r_w; end endcase end if (csr_bankarray_csrbank1_w0_re) begin basesoc__w_storage[2:0] <= csr_bankarray_csrbank1_w0_r; end basesoc__w_re <= csr_bankarray_csrbank1_w0_re; basesoc__r_re <= csr_bankarray_csrbank1_r_re; csr_bankarray_sel_r <= csr_bankarray_sel; csr_bankarray_interface2_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank2_sel) begin case (csr_bankarray_interface2_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_load0_w; end 1'd1: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_reload0_w; end 2'd2: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_en0_w; end 2'd3: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_update_value0_w; end 3'd4: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_value_w; end 3'd5: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_ev_status_w; end 3'd6: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_ev_pending_w; end 3'd7: begin csr_bankarray_interface2_bank_bus_dat_r <= csr_bankarray_csrbank2_ev_enable0_w; end endcase end if (csr_bankarray_csrbank2_load0_re) begin basesoc_basesoc_load_storage[31:0] <= csr_bankarray_csrbank2_load0_r; end basesoc_basesoc_load_re <= csr_bankarray_csrbank2_load0_re; if (csr_bankarray_csrbank2_reload0_re) begin basesoc_basesoc_reload_storage[31:0] <= csr_bankarray_csrbank2_reload0_r; end basesoc_basesoc_reload_re <= csr_bankarray_csrbank2_reload0_re; if (csr_bankarray_csrbank2_en0_re) begin basesoc_basesoc_en_storage <= csr_bankarray_csrbank2_en0_r; end basesoc_basesoc_en_re <= csr_bankarray_csrbank2_en0_re; if (csr_bankarray_csrbank2_update_value0_re) begin basesoc_basesoc_update_value_storage <= csr_bankarray_csrbank2_update_value0_r; end basesoc_basesoc_update_value_re <= csr_bankarray_csrbank2_update_value0_re; basesoc_basesoc_value_re <= csr_bankarray_csrbank2_value_re; basesoc_basesoc_status_re <= csr_bankarray_csrbank2_ev_status_re; if (csr_bankarray_csrbank2_ev_pending_re) begin basesoc_basesoc_pending_r <= csr_bankarray_csrbank2_ev_pending_r; end basesoc_basesoc_pending_re <= csr_bankarray_csrbank2_ev_pending_re; if (csr_bankarray_csrbank2_ev_enable0_re) begin basesoc_basesoc_enable_storage <= csr_bankarray_csrbank2_ev_enable0_r; end basesoc_basesoc_enable_re <= csr_bankarray_csrbank2_ev_enable0_re; csr_bankarray_interface3_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank3_sel) begin case (csr_bankarray_interface3_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface3_bank_bus_dat_r <= basesoc_uart_0_rxtx_w; end 1'd1: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_txfull_w; end 2'd2: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_rxempty_w; end 2'd3: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_status_w; end 3'd4: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_pending_w; end 3'd5: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_ev_enable0_w; end 3'd6: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_txempty_w; end 3'd7: begin csr_bankarray_interface3_bank_bus_dat_r <= csr_bankarray_csrbank3_rxfull_w; end endcase end basesoc_uart_0_txfull_re <= csr_bankarray_csrbank3_txfull_re; basesoc_uart_0_rxempty_re <= csr_bankarray_csrbank3_rxempty_re; basesoc_uart_0_status_re <= csr_bankarray_csrbank3_ev_status_re; if (csr_bankarray_csrbank3_ev_pending_re) begin basesoc_uart_0_pending_r[1:0] <= csr_bankarray_csrbank3_ev_pending_r; end basesoc_uart_0_pending_re <= csr_bankarray_csrbank3_ev_pending_re; if (csr_bankarray_csrbank3_ev_enable0_re) begin basesoc_uart_0_enable_storage[1:0] <= csr_bankarray_csrbank3_ev_enable0_r; end basesoc_uart_0_enable_re <= csr_bankarray_csrbank3_ev_enable0_re; basesoc_uart_0_txempty_re <= csr_bankarray_csrbank3_txempty_re; basesoc_uart_0_rxfull_re <= csr_bankarray_csrbank3_rxfull_re; csr_bankarray_interface4_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank4_sel) begin case (csr_bankarray_interface4_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface4_bank_bus_dat_r <= csr_bankarray_csrbank4_tuning_word0_w; end endcase end if (csr_bankarray_csrbank4_tuning_word0_re) begin basesoc_uart_0_phy_storage[31:0] <= csr_bankarray_csrbank4_tuning_word0_r; end basesoc_uart_0_phy_re <= csr_bankarray_csrbank4_tuning_word0_re; csr_bankarray_interface5_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank5_sel) begin case (csr_bankarray_interface5_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface5_bank_bus_dat_r <= basesoc_uart_1_rxtx_w; end 1'd1: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_txfull_w; end 2'd2: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_rxempty_w; end 2'd3: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_ev_status_w; end 3'd4: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_ev_pending_w; end 3'd5: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_ev_enable0_w; end 3'd6: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_txempty_w; end 3'd7: begin csr_bankarray_interface5_bank_bus_dat_r <= csr_bankarray_csrbank5_rxfull_w; end endcase end basesoc_uart_1_txfull_re <= csr_bankarray_csrbank5_txfull_re; basesoc_uart_1_rxempty_re <= csr_bankarray_csrbank5_rxempty_re; basesoc_uart_1_status_re <= csr_bankarray_csrbank5_ev_status_re; if (csr_bankarray_csrbank5_ev_pending_re) begin basesoc_uart_1_pending_r[1:0] <= csr_bankarray_csrbank5_ev_pending_r; end basesoc_uart_1_pending_re <= csr_bankarray_csrbank5_ev_pending_re; if (csr_bankarray_csrbank5_ev_enable0_re) begin basesoc_uart_1_enable_storage[1:0] <= csr_bankarray_csrbank5_ev_enable0_r; end basesoc_uart_1_enable_re <= csr_bankarray_csrbank5_ev_enable0_re; basesoc_uart_1_txempty_re <= csr_bankarray_csrbank5_txempty_re; basesoc_uart_1_rxfull_re <= csr_bankarray_csrbank5_rxfull_re; csr_bankarray_interface6_bank_bus_dat_r <= 1'd0; if (csr_bankarray_csrbank6_sel) begin case (csr_bankarray_interface6_bank_bus_adr[8:0]) 1'd0: begin csr_bankarray_interface6_bank_bus_dat_r <= csr_bankarray_csrbank6_tuning_word0_w; end endcase end if (csr_bankarray_csrbank6_tuning_word0_re) begin basesoc_uart_1_phy_storage[31:0] <= csr_bankarray_csrbank6_tuning_word0_r; end basesoc_uart_1_phy_re <= csr_bankarray_csrbank6_tuning_word0_re; if (sys_rst) begin basesoc_basesoc_reset_storage <= 2'd0; basesoc_basesoc_reset_re <= 1'd0; basesoc_basesoc_scratch_storage <= 32'd305419896; basesoc_basesoc_scratch_re <= 1'd0; basesoc_basesoc_bus_errors_re <= 1'd0; basesoc_basesoc_bus_errors <= 32'd0; basesoc_basesoc_load_storage <= 32'd0; basesoc_basesoc_load_re <= 1'd0; basesoc_basesoc_reload_storage <= 32'd0; basesoc_basesoc_reload_re <= 1'd0; basesoc_basesoc_en_storage <= 1'd0; basesoc_basesoc_en_re <= 1'd0; basesoc_basesoc_update_value_storage <= 1'd0; basesoc_basesoc_update_value_re <= 1'd0; basesoc_basesoc_value_status <= 32'd0; basesoc_basesoc_value_re <= 1'd0; basesoc_basesoc_zero_pending <= 1'd0; basesoc_basesoc_zero_trigger_d <= 1'd0; basesoc_basesoc_status_re <= 1'd0; basesoc_basesoc_pending_re <= 1'd0; basesoc_basesoc_pending_r <= 1'd0; basesoc_basesoc_enable_storage <= 1'd0; basesoc_basesoc_enable_re <= 1'd0; basesoc_basesoc_value <= 32'd0; basesoc_in_out <= 19'd0; basesoc__w_storage <= 3'd0; basesoc__w_re <= 1'd0; basesoc__r_re <= 1'd0; basesoc_uart_0_phy_storage <= 32'd9895604; basesoc_uart_0_phy_re <= 1'd0; basesoc_uart_0_phy_tx_tick <= 1'd0; basesoc_uart_0_phy_rx_tick <= 1'd0; basesoc_uart_0_phy_rx_rx_d <= 1'd0; basesoc_uart_0_txfull_re <= 1'd0; basesoc_uart_0_rxempty_re <= 1'd0; basesoc_uart_0_tx_pending <= 1'd0; basesoc_uart_0_tx_trigger_d <= 1'd0; basesoc_uart_0_rx_pending <= 1'd0; basesoc_uart_0_rx_trigger_d <= 1'd0; basesoc_uart_0_status_re <= 1'd0; basesoc_uart_0_pending_re <= 1'd0; basesoc_uart_0_pending_r <= 2'd0; basesoc_uart_0_enable_storage <= 2'd0; basesoc_uart_0_enable_re <= 1'd0; basesoc_uart_0_txempty_re <= 1'd0; basesoc_uart_0_rxfull_re <= 1'd0; basesoc_uart_0_tx_fifo_readable <= 1'd0; basesoc_uart_0_tx_fifo_level0 <= 5'd0; basesoc_uart_0_tx_fifo_produce <= 4'd0; basesoc_uart_0_tx_fifo_consume <= 4'd0; basesoc_uart_0_rx_fifo_readable <= 1'd0; basesoc_uart_0_rx_fifo_level0 <= 5'd0; basesoc_uart_0_rx_fifo_produce <= 4'd0; basesoc_uart_0_rx_fifo_consume <= 4'd0; basesoc_uart_1_phy_storage <= 32'd9895604; basesoc_uart_1_phy_re <= 1'd0; basesoc_uart_1_phy_tx_tick <= 1'd0; basesoc_uart_1_phy_rx_tick <= 1'd0; basesoc_uart_1_phy_rx_rx_d <= 1'd0; basesoc_uart_1_txfull_re <= 1'd0; basesoc_uart_1_rxempty_re <= 1'd0; basesoc_uart_1_tx_pending <= 1'd0; basesoc_uart_1_tx_trigger_d <= 1'd0; basesoc_uart_1_rx_pending <= 1'd0; basesoc_uart_1_rx_trigger_d <= 1'd0; basesoc_uart_1_status_re <= 1'd0; basesoc_uart_1_pending_re <= 1'd0; basesoc_uart_1_pending_r <= 2'd0; basesoc_uart_1_enable_storage <= 2'd0; basesoc_uart_1_enable_re <= 1'd0; basesoc_uart_1_txempty_re <= 1'd0; basesoc_uart_1_rxfull_re <= 1'd0; basesoc_uart_1_tx_fifo_readable <= 1'd0; basesoc_uart_1_tx_fifo_level0 <= 5'd0; basesoc_uart_1_tx_fifo_produce <= 4'd0; basesoc_uart_1_tx_fifo_consume <= 4'd0; basesoc_uart_1_rx_fifo_readable <= 1'd0; basesoc_uart_1_rx_fifo_level0 <= 5'd0; basesoc_uart_1_rx_fifo_produce <= 4'd0; basesoc_uart_1_rx_fifo_consume <= 4'd0; rs232phytx0_state <= 1'd0; rs232phyrx0_state <= 1'd0; rs232phytx1_state <= 1'd0; rs232phyrx1_state <= 1'd0; grant <= 1'd0; slave_sel_r <= 2'd0; count <= 20'd1000000; csr_bankarray_sel_r <= 1'd0; state <= 1'd0; end multiregimpl0_regs0 <= basesoc_in_in[0]; multiregimpl0_regs1 <= multiregimpl0_regs0; multiregimpl1_regs0 <= basesoc_in_out[1]; multiregimpl1_regs1 <= multiregimpl1_regs0; end //------------------------------------------------------------------------------ // Specialized Logic //------------------------------------------------------------------------------ //------------------------------------------------------------------------------ // Memory mem: 42-words x 8-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: ---- | reg [7:0] mem[0:41]; initial begin $readmemh("mem.init", mem); end reg [5:0] mem_adr0; always @(posedge sys_clk) begin mem_adr0 <= csr_bankarray_adr; end assign csr_bankarray_dat_r = mem[mem_adr0]; issiram issiram( .clk(sys_clk), .rst(sys_rst), .wbs_adr_i(basesoc_sram_bus_adr), .wbs_cyc_i(basesoc_sram_bus_cyc), .wbs_dat_i(basesoc_sram_bus_dat_w), .wbs_sel_i(basesoc_sram_bus_sel), .wbs_stb_i(basesoc_sram_bus_stb), .wbs_we_i(basesoc_sram_bus_we), .mem_dat(basesoc4), .mem_adr(basesoc3), .mem_ce_n(basesoc0), .mem_oe_n(basesoc1), .mem_we_n(basesoc2), .wbs_ack_o(basesoc_sram_bus_ack), .wbs_dat_o(basesoc_sram_bus_dat_r) ); assign basesoc_in_out[2] = (~basesoc_scl) ? 1'd0 : 1'bz; assign basesoc_in_out[3] = (basesoc_oe & (~basesoc_sda0)) ? 1'd0 : 1'bz; assign basesoc_sda1 = basesoc_in_out[3]; //------------------------------------------------------------------------------ // Memory storage: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage[0:15]; reg [9:0] storage_dat0; reg [9:0] storage_dat1; always @(posedge sys_clk) begin if (basesoc_uart_0_tx_fifo_wrport_we) storage[basesoc_uart_0_tx_fifo_wrport_adr] <= basesoc_uart_0_tx_fifo_wrport_dat_w; storage_dat0 <= storage[basesoc_uart_0_tx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (basesoc_uart_0_tx_fifo_rdport_re) storage_dat1 <= storage[basesoc_uart_0_tx_fifo_rdport_adr]; end assign basesoc_uart_0_tx_fifo_wrport_dat_r = storage_dat0; assign basesoc_uart_0_tx_fifo_rdport_dat_r = storage_dat1; //------------------------------------------------------------------------------ // Memory storage_1: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_1[0:15]; reg [9:0] storage_1_dat0; reg [9:0] storage_1_dat1; always @(posedge sys_clk) begin if (basesoc_uart_0_rx_fifo_wrport_we) storage_1[basesoc_uart_0_rx_fifo_wrport_adr] <= basesoc_uart_0_rx_fifo_wrport_dat_w; storage_1_dat0 <= storage_1[basesoc_uart_0_rx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (basesoc_uart_0_rx_fifo_rdport_re) storage_1_dat1 <= storage_1[basesoc_uart_0_rx_fifo_rdport_adr]; end assign basesoc_uart_0_rx_fifo_wrport_dat_r = storage_1_dat0; assign basesoc_uart_0_rx_fifo_rdport_dat_r = storage_1_dat1; //------------------------------------------------------------------------------ // Memory storage_2: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_2[0:15]; reg [9:0] storage_2_dat0; reg [9:0] storage_2_dat1; always @(posedge sys_clk) begin if (basesoc_uart_1_tx_fifo_wrport_we) storage_2[basesoc_uart_1_tx_fifo_wrport_adr] <= basesoc_uart_1_tx_fifo_wrport_dat_w; storage_2_dat0 <= storage_2[basesoc_uart_1_tx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (basesoc_uart_1_tx_fifo_rdport_re) storage_2_dat1 <= storage_2[basesoc_uart_1_tx_fifo_rdport_adr]; end assign basesoc_uart_1_tx_fifo_wrport_dat_r = storage_2_dat0; assign basesoc_uart_1_tx_fifo_rdport_dat_r = storage_2_dat1; //------------------------------------------------------------------------------ // Memory storage_3: 16-words x 10-bit //------------------------------------------------------------------------------ // Port 0 | Read: Sync | Write: Sync | Mode: Read-First | Write-Granularity: 10 // Port 1 | Read: Sync | Write: ---- | reg [9:0] storage_3[0:15]; reg [9:0] storage_3_dat0; reg [9:0] storage_3_dat1; always @(posedge sys_clk) begin if (basesoc_uart_1_rx_fifo_wrport_we) storage_3[basesoc_uart_1_rx_fifo_wrport_adr] <= basesoc_uart_1_rx_fifo_wrport_dat_w; storage_3_dat0 <= storage_3[basesoc_uart_1_rx_fifo_wrport_adr]; end always @(posedge sys_clk) begin if (basesoc_uart_1_rx_fifo_rdport_re) storage_3_dat1 <= storage_3[basesoc_uart_1_rx_fifo_rdport_adr]; end assign basesoc_uart_1_rx_fifo_wrport_dat_r = storage_3_dat0; assign basesoc_uart_1_rx_fifo_rdport_dat_r = storage_3_dat1; A2P_WB A2P_WB( .clk(sys_clk), .dBusWB_ACK(basesoc_basesoc_dbus_ack), .dBusWB_DAT_MISO(basesoc_basesoc_dbus_dat_r), .dBusWB_ERR(basesoc_basesoc_dbus_err), .externalInterrupt(basesoc_basesoc_interrupt[0]), .externalInterruptS(basesoc_basesoc_interruptS), .externalResetVector(basesoc_basesoc_a2p), .iBusWB_ACK(basesoc_basesoc_ibus_ack), .iBusWB_DAT_MISO(basesoc_basesoc_ibus_dat_r), .iBusWB_ERR(basesoc_basesoc_ibus_err), .reset((sys_rst | basesoc_basesoc_reset)), .softwareInterrupt(1'd0), .timerInterrupt(1'd0), .dBusWB_ADR(basesoc_basesoc_dbus_adr), .dBusWB_BTE(basesoc_basesoc_dbus_bte), .dBusWB_CTI(basesoc_basesoc_dbus_cti), .dBusWB_CYC(basesoc_basesoc_dbus_cyc), .dBusWB_DAT_MOSI(basesoc_basesoc_dbus_dat_w), .dBusWB_SEL(basesoc_basesoc_dbus_sel), .dBusWB_STB(basesoc_basesoc_dbus_stb), .dBusWB_WE(basesoc_basesoc_dbus_we), .iBusWB_ADR(basesoc_basesoc_ibus_adr), .iBusWB_BTE(basesoc_basesoc_ibus_bte), .iBusWB_CTI(basesoc_basesoc_ibus_cti), .iBusWB_CYC(basesoc_basesoc_ibus_cyc), .iBusWB_DAT_MOSI(basesoc_basesoc_ibus_dat_w), .iBusWB_SEL(basesoc_basesoc_ibus_sel), .iBusWB_STB(basesoc_basesoc_ibus_stb), .iBusWB_WE(basesoc_basesoc_ibus_we) ); endmodule // ----------------------------------------------------------------------------- // Auto-Generated by LiteX on 2021-11-25 10:16:15. //------------------------------------------------------------------------------