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274 lines
7.7 KiB
Verilog
274 lines
7.7 KiB
Verilog
// A2 Core Bridge
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// should modularize as much as possible and just do messy rewiring here!
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// one thread/core for now
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// possible extended command modifiers
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// prefetch
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// larx
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// stcx
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// lwsync
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// hwsync
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// tlbsync
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// ici, icbi
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// dci, dcbi, etc
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// dcbtst
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// dcbz
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// tlbie, etc
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// possible extended responses
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// errors
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// crit first, xfer# for larger bus width on core side
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// credits
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// resv valid
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// stcx comp/pass
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// sync ack
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// back inv val/addr
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// possible extra functions
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// integrated L2
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// doorbell/mailbox (peer/broadcast msg/rsp/intr side channel crossbar)
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// cores must be contiguous, starting at 0
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`define CORE_TYPE_NONE 4'h0
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`define CORE_TYPE_A2L2 4'h1
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`define CORE_TYPE_WB1 4'h2
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`define CORE_TYPE_WB2 4'h3
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`define BUS_TYPE_NONE 4'h0
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`define BUS_TYPE_WB1 4'h1
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`define BUS_TYPE_WB2 4'h2
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module A2WB #(
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parameter [0:15] CORE_TYPES = {`CORE_TYPE_WB2, `CORE_TYPE_NONE, `CORE_TYPE_NONE, `CORE_TYPE_NONE},
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parameter [0:3] BUS_TYPE = `BUS_TYPE_WB2
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) (
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input clk,
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input rst,
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input [0:3] core_in,
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output [0:3] core_out,
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input bus_in,
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output bus_out
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);
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integer NUMCORES = 0;
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genvar i;
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// ------------------------------------------------------------------------------------------------
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// I/O Connections
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wire i_wb_cyc [0:3];
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wire i_wb_stb [0:3];
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wire [31:2] i_wb_adr[0:3] ;
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wire i_wb_ack [0:3];
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wire [31:0] i_wb_datr[0:3];
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wire d_wb_cyc [0:3];
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wire d_wb_stb [0:3];
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wire d_wb_we [0:3];
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wire [3:0] d_wb_sel [0:3];
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wire [31:0] d_wb_adr [0:3];
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wire [31:0] d_wb_datw [0:3];
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wire d_wb_ack [0:3];
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wire [31:0] d_wb_datr[0:3];
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wire [7:0] ext_cmd [0:3];
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wire [7:0] ext_rsp [0:3];
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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4'h0: begin
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end
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4'h1: begin
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assign NUMCORES = NUMCORES + 1;
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// a2l2
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end
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4'h2: begin
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assign NUMCORES = NUMCORES + 1;
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wire [78:0] core_0_in;
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wire [32:0] core_out[i];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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4'h3: begin
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assign NUMCORES = NUMCORES + 1;
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wire [110:0] core_in[i];
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wire [65:0] core_out[i];
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assign i_wb_cyc[i] = core_in[i][110];
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assign i_wb_stb[i] = core_in[i][109];
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assign i_wb_adr[i] = core_in[i][108:79];
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assign d_wb_cyc[i] = core_in[i][78];
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assign d_wb_stb[i] = core_in[i][77];
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assign d_wb_we[i] = core_in[i][76];
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assign d_wb_sel[i] = core_in[i][75:72];
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assign d_wb_adr[i] = core_in[i][71:40];
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assign d_wb_datw[i] = core_in[i][39:8];
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assign ext_cmd[i] = core_in[i][7:0];
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assign core_out[i][65] = i_wb_ack[i];
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assign core_out[i][64:33] = i_wb_datr[i];
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assign core_out[i][32] = d_wb_ack[i];
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assign core_out[i][31:0] = d_wb_datr[i];
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Command Queues/Addr Compare/Bypass
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//
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// cores can have either 1 or 2 buses; assume single-cmd outstanding per, for now
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// a2l2 could also allow 1 ld, 1 st credit and use 2 dedicated queues
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reg [77:0] cmd_queue_q[0:3][0:1];
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wire [77:0] cmd_queue_d[0:3][0:1];
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wire [77:0] cmd_queue_in[0:3][0:1];
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wire [71:0] cmd_queue_out[0:3];
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generate
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for (i = 0; i < 4; i++) begin
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case (CORE_TYPES[i*4:i*4+3])
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4'h0: begin
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end
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4'h1: begin
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// convert a2l2 to internal format
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end
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4'h2: begin
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// q[0] = i or d
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assign cmd_queue_in[i][0][77] = d_wb_cyc[i] & d_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = d_wb_we[i];
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assign cmd_queue_in[i][0][75:72] = d_wb_sel[i];
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = d_wb_datw[i];
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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end
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4'h3: begin
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// q[0]=i, q[1]=d
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assign cmd_queue_in[i][0][77] = i_wb_cyc[i] & i_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = 'b0;
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assign cmd_queue_in[i][0][75:72] = 'b0000;
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = 'h000000;
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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assign cmd_queue_in[i][0][77] = d_wb_cyc[i] & d_wb_stb[i]; // valid
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assign cmd_queue_in[i][0][76] = d_wb_we[i];
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assign cmd_queue_in[i][0][75:72] = d_wb_sel[i];
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assign cmd_queue_in[i][0][71:40] = d_wb_adr[i];
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assign cmd_queue_in[i][0][39:8] = d_wb_datw[i];
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assign cmd_queue_in[i][0][7:0] = ext_cmd[i];
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end
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endcase
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// SMP
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// larx/stcx
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// assume: if larx hits L1, core invalidates line automatically -> do not need to send back-invalidate
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// reservation granule is 32B (or use lcd of all cores)
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// one reservation per thread
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// reservation is set before core receives reload data
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wire stcx_store [0:3];
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wire resv_ra_hit [0:3];
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wire resv_set [0:3];
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wire resv_rst [0:3];
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wire [27:0] resv_q [0:3]; // v, @31:5
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wire [27:0] resv_d [0:3];
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// sync ack
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// cache ops
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// tlb ops
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// ------------------------------------------------------------------------------------------------
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// Arbitration
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//
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// LRU, etc. select from pending cmds
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Bus Out
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generate
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if (BUS_TYPE == `BUS_TYPE_WB1) begin
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end else if (BUS_TYPE == `BUS_TYPE_WB2) begin
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wire [101:0] bus_out;
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wire bus_i_wb_stb;
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assign bus_out[101] = bus_i_wb_stb;
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wire [31:2] bus_i_wb_adr;
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assign bus_out[100:71] = bus_i_wb_adr;
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wire bus_d_wb_cyc;
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assign bus_out[70] = bus_d_wb_cyc;
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wire bus_d_wb_stb;
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assign bus_out[69] = bus_d_wb_stb;
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wire bus_d_wb_we;
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assign bus_out[68] = bus_d_wb_we;
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wire [3:0] bus_d_wb_sel;
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assign bus_out[67:64] = bus_d_wb_sel;
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wire [31:0] bus_d_wb_adr;
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assign bus_out[63:32] = bus_d_wb_adr;
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wire [31:0] bus_d_wb_datw;
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assign bus_out[31:0] = bus_d_wb_datw;
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end else begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Bus In
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generate
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if (BUS_TYPE == `BUS_TYPE_WB1) begin
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end else if (BUS_TYPE == `BUS_TYPE_WB2) begin
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wire [65:0] bus_in;
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wire bus_i_wb_ack = bus_in[65];
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wire [31:0] bus_i_wb_datr = bus_in[64:33];
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wire bus_d_wb_ack = bus_in[32];
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wire [31:0] bus_d_wb_datr = bus_in[31:0];
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end else begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Response Queues
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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// ------------------------------------------------------------------------------------------------
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// Misc/Errors/Debug
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generate
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for (i = 0; i < 4; i++) begin
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end
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endgenerate
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endmodule |